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Commit | Line | Data |
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0977f817 | 1 | /* drivers/net/ethernet/freescale/gianfar.c |
1da177e4 LT |
2 | * |
3 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
4 | * This driver is designed for the non-CPM ethernet controllers |
5 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
6 | * Based on 8260_io/fcc_enet.c |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
a12f801d | 10 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 11 | * |
6c43e046 | 12 | * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. |
a12f801d | 13 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
59deab26 JP |
64 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
65 | #define DEBUG | |
66 | ||
1da177e4 | 67 | #include <linux/kernel.h> |
1da177e4 LT |
68 | #include <linux/string.h> |
69 | #include <linux/errno.h> | |
bb40dcbb | 70 | #include <linux/unistd.h> |
1da177e4 LT |
71 | #include <linux/slab.h> |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/init.h> | |
74 | #include <linux/delay.h> | |
75 | #include <linux/netdevice.h> | |
76 | #include <linux/etherdevice.h> | |
77 | #include <linux/skbuff.h> | |
0bbaf069 | 78 | #include <linux/if_vlan.h> |
1da177e4 LT |
79 | #include <linux/spinlock.h> |
80 | #include <linux/mm.h> | |
fe192a49 | 81 | #include <linux/of_mdio.h> |
b31a1d8b | 82 | #include <linux/of_platform.h> |
0bbaf069 KG |
83 | #include <linux/ip.h> |
84 | #include <linux/tcp.h> | |
85 | #include <linux/udp.h> | |
9c07b884 | 86 | #include <linux/in.h> |
cc772ab7 | 87 | #include <linux/net_tstamp.h> |
1da177e4 LT |
88 | |
89 | #include <asm/io.h> | |
7d350977 | 90 | #include <asm/reg.h> |
1da177e4 LT |
91 | #include <asm/irq.h> |
92 | #include <asm/uaccess.h> | |
93 | #include <linux/module.h> | |
1da177e4 LT |
94 | #include <linux/dma-mapping.h> |
95 | #include <linux/crc32.h> | |
bb40dcbb AF |
96 | #include <linux/mii.h> |
97 | #include <linux/phy.h> | |
b31a1d8b AF |
98 | #include <linux/phy_fixed.h> |
99 | #include <linux/of.h> | |
4b6ba8aa | 100 | #include <linux/of_net.h> |
1da177e4 LT |
101 | |
102 | #include "gianfar.h" | |
1577ecef | 103 | #include "fsl_pq_mdio.h" |
1da177e4 LT |
104 | |
105 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 | 106 | |
7f7f5316 | 107 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 108 | |
1da177e4 LT |
109 | static int gfar_enet_open(struct net_device *dev); |
110 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 111 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
112 | static void gfar_timeout(struct net_device *dev); |
113 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 114 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 115 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
815b97c6 | 116 | struct sk_buff *skb); |
1da177e4 LT |
117 | static int gfar_set_mac_address(struct net_device *dev); |
118 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
119 | static irqreturn_t gfar_error(int irq, void *dev_id); |
120 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
121 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
122 | static void adjust_link(struct net_device *dev); |
123 | static void init_registers(struct net_device *dev); | |
124 | static int init_phy(struct net_device *dev); | |
74888760 | 125 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 126 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 127 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
128 | static void gfar_set_multi(struct net_device *dev); |
129 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 130 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 131 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
132 | #ifdef CONFIG_NET_POLL_CONTROLLER |
133 | static void gfar_netpoll(struct net_device *dev); | |
134 | #endif | |
a12f801d SG |
135 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
136 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); | |
2c2db48a | 137 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
cd754a57 | 138 | int amount_pull, struct napi_struct *napi); |
7f7f5316 | 139 | void gfar_halt(struct net_device *dev); |
d87eb127 | 140 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
141 | void gfar_start(struct net_device *dev); |
142 | static void gfar_clear_exact_match(struct net_device *dev); | |
b6bc7650 JP |
143 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
144 | const u8 *addr); | |
26ccfc37 | 145 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 146 | |
1da177e4 LT |
147 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
148 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
149 | MODULE_LICENSE("GPL"); | |
150 | ||
a12f801d | 151 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
152 | dma_addr_t buf) |
153 | { | |
8a102fe0 AV |
154 | u32 lstatus; |
155 | ||
156 | bdp->bufPtr = buf; | |
157 | ||
158 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 159 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
160 | lstatus |= BD_LFLAG(RXBD_WRAP); |
161 | ||
162 | eieio(); | |
163 | ||
164 | bdp->lstatus = lstatus; | |
165 | } | |
166 | ||
8728327e | 167 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 168 | { |
8728327e | 169 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
170 | struct gfar_priv_tx_q *tx_queue = NULL; |
171 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
172 | struct txbd8 *txbdp; |
173 | struct rxbd8 *rxbdp; | |
fba4ed03 | 174 | int i, j; |
a12f801d | 175 | |
fba4ed03 SG |
176 | for (i = 0; i < priv->num_tx_queues; i++) { |
177 | tx_queue = priv->tx_queue[i]; | |
178 | /* Initialize some variables in our dev structure */ | |
179 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
180 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
181 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
182 | tx_queue->skb_curtx = 0; | |
183 | tx_queue->skb_dirtytx = 0; | |
184 | ||
185 | /* Initialize Transmit Descriptor Ring */ | |
186 | txbdp = tx_queue->tx_bd_base; | |
187 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
188 | txbdp->lstatus = 0; | |
189 | txbdp->bufPtr = 0; | |
190 | txbdp++; | |
191 | } | |
8728327e | 192 | |
fba4ed03 SG |
193 | /* Set the last descriptor in the ring to indicate wrap */ |
194 | txbdp--; | |
195 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
196 | } |
197 | ||
fba4ed03 SG |
198 | for (i = 0; i < priv->num_rx_queues; i++) { |
199 | rx_queue = priv->rx_queue[i]; | |
200 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
201 | rx_queue->skb_currx = 0; | |
202 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 203 | |
fba4ed03 SG |
204 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
205 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 206 | |
fba4ed03 SG |
207 | if (skb) { |
208 | gfar_init_rxbdp(rx_queue, rxbdp, | |
209 | rxbdp->bufPtr); | |
210 | } else { | |
211 | skb = gfar_new_skb(ndev); | |
212 | if (!skb) { | |
59deab26 | 213 | netdev_err(ndev, "Can't allocate RX buffers\n"); |
fba4ed03 SG |
214 | goto err_rxalloc_fail; |
215 | } | |
216 | rx_queue->rx_skbuff[j] = skb; | |
217 | ||
218 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 219 | } |
8728327e | 220 | |
fba4ed03 | 221 | rxbdp++; |
8728327e AV |
222 | } |
223 | ||
8728327e AV |
224 | } |
225 | ||
226 | return 0; | |
fba4ed03 SG |
227 | |
228 | err_rxalloc_fail: | |
229 | free_skb_resources(priv); | |
230 | return -ENOMEM; | |
8728327e AV |
231 | } |
232 | ||
233 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
234 | { | |
826aa4a0 | 235 | void *vaddr; |
fba4ed03 SG |
236 | dma_addr_t addr; |
237 | int i, j, k; | |
826aa4a0 AV |
238 | struct gfar_private *priv = netdev_priv(ndev); |
239 | struct device *dev = &priv->ofdev->dev; | |
a12f801d SG |
240 | struct gfar_priv_tx_q *tx_queue = NULL; |
241 | struct gfar_priv_rx_q *rx_queue = NULL; | |
242 | ||
fba4ed03 SG |
243 | priv->total_tx_ring_size = 0; |
244 | for (i = 0; i < priv->num_tx_queues; i++) | |
245 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
246 | ||
247 | priv->total_rx_ring_size = 0; | |
248 | for (i = 0; i < priv->num_rx_queues; i++) | |
249 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
250 | |
251 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 252 | vaddr = dma_alloc_coherent(dev, |
fba4ed03 SG |
253 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
254 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
255 | &addr, GFP_KERNEL); | |
826aa4a0 | 256 | if (!vaddr) { |
59deab26 JP |
257 | netif_err(priv, ifup, ndev, |
258 | "Could not allocate buffer descriptors!\n"); | |
826aa4a0 AV |
259 | return -ENOMEM; |
260 | } | |
261 | ||
fba4ed03 SG |
262 | for (i = 0; i < priv->num_tx_queues; i++) { |
263 | tx_queue = priv->tx_queue[i]; | |
43d620c8 | 264 | tx_queue->tx_bd_base = vaddr; |
fba4ed03 SG |
265 | tx_queue->tx_bd_dma_base = addr; |
266 | tx_queue->dev = ndev; | |
267 | /* enet DMA only understands physical addresses */ | |
2281a0f3 JC |
268 | addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; |
269 | vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; | |
fba4ed03 | 270 | } |
826aa4a0 | 271 | |
826aa4a0 | 272 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
273 | for (i = 0; i < priv->num_rx_queues; i++) { |
274 | rx_queue = priv->rx_queue[i]; | |
43d620c8 | 275 | rx_queue->rx_bd_base = vaddr; |
fba4ed03 SG |
276 | rx_queue->rx_bd_dma_base = addr; |
277 | rx_queue->dev = ndev; | |
2281a0f3 JC |
278 | addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; |
279 | vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; | |
fba4ed03 | 280 | } |
826aa4a0 AV |
281 | |
282 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
283 | for (i = 0; i < priv->num_tx_queues; i++) { |
284 | tx_queue = priv->tx_queue[i]; | |
285 | tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) * | |
a12f801d | 286 | tx_queue->tx_ring_size, GFP_KERNEL); |
fba4ed03 | 287 | if (!tx_queue->tx_skbuff) { |
59deab26 JP |
288 | netif_err(priv, ifup, ndev, |
289 | "Could not allocate tx_skbuff\n"); | |
fba4ed03 SG |
290 | goto cleanup; |
291 | } | |
826aa4a0 | 292 | |
fba4ed03 SG |
293 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
294 | tx_queue->tx_skbuff[k] = NULL; | |
295 | } | |
826aa4a0 | 296 | |
fba4ed03 SG |
297 | for (i = 0; i < priv->num_rx_queues; i++) { |
298 | rx_queue = priv->rx_queue[i]; | |
299 | rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) * | |
a12f801d | 300 | rx_queue->rx_ring_size, GFP_KERNEL); |
826aa4a0 | 301 | |
fba4ed03 | 302 | if (!rx_queue->rx_skbuff) { |
59deab26 JP |
303 | netif_err(priv, ifup, ndev, |
304 | "Could not allocate rx_skbuff\n"); | |
fba4ed03 SG |
305 | goto cleanup; |
306 | } | |
307 | ||
308 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
309 | rx_queue->rx_skbuff[j] = NULL; | |
310 | } | |
826aa4a0 | 311 | |
8728327e AV |
312 | if (gfar_init_bds(ndev)) |
313 | goto cleanup; | |
826aa4a0 AV |
314 | |
315 | return 0; | |
316 | ||
317 | cleanup: | |
318 | free_skb_resources(priv); | |
319 | return -ENOMEM; | |
320 | } | |
321 | ||
fba4ed03 SG |
322 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
323 | { | |
46ceb60c | 324 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 325 | u32 __iomem *baddr; |
fba4ed03 SG |
326 | int i; |
327 | ||
328 | baddr = ®s->tbase0; | |
329 | for(i = 0; i < priv->num_tx_queues; i++) { | |
330 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); | |
331 | baddr += 2; | |
332 | } | |
333 | ||
334 | baddr = ®s->rbase0; | |
335 | for(i = 0; i < priv->num_rx_queues; i++) { | |
336 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); | |
337 | baddr += 2; | |
338 | } | |
339 | } | |
340 | ||
826aa4a0 AV |
341 | static void gfar_init_mac(struct net_device *ndev) |
342 | { | |
343 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 344 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
345 | u32 rctrl = 0; |
346 | u32 tctrl = 0; | |
347 | u32 attrs = 0; | |
348 | ||
fba4ed03 SG |
349 | /* write the tx/rx base registers */ |
350 | gfar_init_tx_rx_base(priv); | |
32c513bc | 351 | |
826aa4a0 | 352 | /* Configure the coalescing support */ |
46ceb60c | 353 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
fba4ed03 | 354 | |
1ccb8389 | 355 | if (priv->rx_filer_enable) { |
fba4ed03 | 356 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
357 | /* Program the RIR0 reg with the required distribution */ |
358 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
359 | } | |
826aa4a0 | 360 | |
8b3afe95 | 361 | if (ndev->features & NETIF_F_RXCSUM) |
826aa4a0 AV |
362 | rctrl |= RCTRL_CHECKSUMMING; |
363 | ||
364 | if (priv->extended_hash) { | |
365 | rctrl |= RCTRL_EXTHASH; | |
366 | ||
367 | gfar_clear_exact_match(ndev); | |
368 | rctrl |= RCTRL_EMEN; | |
369 | } | |
370 | ||
371 | if (priv->padding) { | |
372 | rctrl &= ~RCTRL_PAL_MASK; | |
373 | rctrl |= RCTRL_PADDING(priv->padding); | |
374 | } | |
375 | ||
cc772ab7 MR |
376 | /* Insert receive time stamps into padding alignment bytes */ |
377 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { | |
378 | rctrl &= ~RCTRL_PAL_MASK; | |
97553f7f | 379 | rctrl |= RCTRL_PADDING(8); |
cc772ab7 MR |
380 | priv->padding = 8; |
381 | } | |
382 | ||
97553f7f MR |
383 | /* Enable HW time stamping if requested from user space */ |
384 | if (priv->hwts_rx_en) | |
385 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; | |
386 | ||
87c288c6 | 387 | if (ndev->features & NETIF_F_HW_VLAN_RX) |
b852b720 | 388 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; |
826aa4a0 AV |
389 | |
390 | /* Init rctrl based on our settings */ | |
391 | gfar_write(®s->rctrl, rctrl); | |
392 | ||
393 | if (ndev->features & NETIF_F_IP_CSUM) | |
394 | tctrl |= TCTRL_INIT_CSUM; | |
395 | ||
fba4ed03 SG |
396 | tctrl |= TCTRL_TXSCHED_PRIO; |
397 | ||
826aa4a0 AV |
398 | gfar_write(®s->tctrl, tctrl); |
399 | ||
400 | /* Set the extraction length and index */ | |
401 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
402 | ATTRELI_EI(priv->rx_stash_index); | |
403 | ||
404 | gfar_write(®s->attreli, attrs); | |
405 | ||
406 | /* Start with defaults, and add stashing or locking | |
0977f817 JC |
407 | * depending on the approprate variables |
408 | */ | |
826aa4a0 AV |
409 | attrs = ATTR_INIT_SETTINGS; |
410 | ||
411 | if (priv->bd_stash_en) | |
412 | attrs |= ATTR_BDSTASH; | |
413 | ||
414 | if (priv->rx_stash_size != 0) | |
415 | attrs |= ATTR_BUFSTASH; | |
416 | ||
417 | gfar_write(®s->attr, attrs); | |
418 | ||
419 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
420 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
421 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
422 | } | |
423 | ||
a7f38041 SG |
424 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
425 | { | |
426 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
427 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
428 | unsigned long tx_packets = 0, tx_bytes = 0; | |
429 | int i = 0; | |
430 | ||
431 | for (i = 0; i < priv->num_rx_queues; i++) { | |
432 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
433 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; | |
434 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; | |
435 | } | |
436 | ||
437 | dev->stats.rx_packets = rx_packets; | |
438 | dev->stats.rx_bytes = rx_bytes; | |
439 | dev->stats.rx_dropped = rx_dropped; | |
440 | ||
441 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
442 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
443 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
444 | } |
445 | ||
446 | dev->stats.tx_bytes = tx_bytes; | |
447 | dev->stats.tx_packets = tx_packets; | |
448 | ||
449 | return &dev->stats; | |
450 | } | |
451 | ||
26ccfc37 AF |
452 | static const struct net_device_ops gfar_netdev_ops = { |
453 | .ndo_open = gfar_enet_open, | |
454 | .ndo_start_xmit = gfar_start_xmit, | |
455 | .ndo_stop = gfar_close, | |
456 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 457 | .ndo_set_features = gfar_set_features, |
afc4b13d | 458 | .ndo_set_rx_mode = gfar_set_multi, |
26ccfc37 AF |
459 | .ndo_tx_timeout = gfar_timeout, |
460 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 461 | .ndo_get_stats = gfar_get_stats, |
240c102d BH |
462 | .ndo_set_mac_address = eth_mac_addr, |
463 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
464 | #ifdef CONFIG_NET_POLL_CONTROLLER |
465 | .ndo_poll_controller = gfar_netpoll, | |
466 | #endif | |
467 | }; | |
468 | ||
fba4ed03 SG |
469 | void lock_rx_qs(struct gfar_private *priv) |
470 | { | |
471 | int i = 0x0; | |
472 | ||
473 | for (i = 0; i < priv->num_rx_queues; i++) | |
474 | spin_lock(&priv->rx_queue[i]->rxlock); | |
475 | } | |
476 | ||
477 | void lock_tx_qs(struct gfar_private *priv) | |
478 | { | |
479 | int i = 0x0; | |
480 | ||
481 | for (i = 0; i < priv->num_tx_queues; i++) | |
482 | spin_lock(&priv->tx_queue[i]->txlock); | |
483 | } | |
484 | ||
485 | void unlock_rx_qs(struct gfar_private *priv) | |
486 | { | |
487 | int i = 0x0; | |
488 | ||
489 | for (i = 0; i < priv->num_rx_queues; i++) | |
490 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
491 | } | |
492 | ||
493 | void unlock_tx_qs(struct gfar_private *priv) | |
494 | { | |
495 | int i = 0x0; | |
496 | ||
497 | for (i = 0; i < priv->num_tx_queues; i++) | |
498 | spin_unlock(&priv->tx_queue[i]->txlock); | |
499 | } | |
500 | ||
87c288c6 JP |
501 | static bool gfar_is_vlan_on(struct gfar_private *priv) |
502 | { | |
503 | return (priv->ndev->features & NETIF_F_HW_VLAN_RX) || | |
504 | (priv->ndev->features & NETIF_F_HW_VLAN_TX); | |
505 | } | |
506 | ||
7f7f5316 AF |
507 | /* Returns 1 if incoming frames use an FCB */ |
508 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 509 | { |
87c288c6 JP |
510 | return gfar_is_vlan_on(priv) || |
511 | (priv->ndev->features & NETIF_F_RXCSUM) || | |
cc772ab7 | 512 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER); |
0bbaf069 | 513 | } |
bb40dcbb | 514 | |
fba4ed03 SG |
515 | static void free_tx_pointers(struct gfar_private *priv) |
516 | { | |
517 | int i = 0; | |
518 | ||
519 | for (i = 0; i < priv->num_tx_queues; i++) | |
520 | kfree(priv->tx_queue[i]); | |
521 | } | |
522 | ||
523 | static void free_rx_pointers(struct gfar_private *priv) | |
524 | { | |
525 | int i = 0; | |
526 | ||
527 | for (i = 0; i < priv->num_rx_queues; i++) | |
528 | kfree(priv->rx_queue[i]); | |
529 | } | |
530 | ||
46ceb60c SG |
531 | static void unmap_group_regs(struct gfar_private *priv) |
532 | { | |
533 | int i = 0; | |
534 | ||
535 | for (i = 0; i < MAXGROUPS; i++) | |
536 | if (priv->gfargrp[i].regs) | |
537 | iounmap(priv->gfargrp[i].regs); | |
538 | } | |
539 | ||
540 | static void disable_napi(struct gfar_private *priv) | |
541 | { | |
542 | int i = 0; | |
543 | ||
544 | for (i = 0; i < priv->num_grps; i++) | |
545 | napi_disable(&priv->gfargrp[i].napi); | |
546 | } | |
547 | ||
548 | static void enable_napi(struct gfar_private *priv) | |
549 | { | |
550 | int i = 0; | |
551 | ||
552 | for (i = 0; i < priv->num_grps; i++) | |
553 | napi_enable(&priv->gfargrp[i].napi); | |
554 | } | |
555 | ||
556 | static int gfar_parse_group(struct device_node *np, | |
557 | struct gfar_private *priv, const char *model) | |
558 | { | |
559 | u32 *queue_mask; | |
46ceb60c | 560 | |
7ce97d4f | 561 | priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0); |
46ceb60c SG |
562 | if (!priv->gfargrp[priv->num_grps].regs) |
563 | return -ENOMEM; | |
564 | ||
565 | priv->gfargrp[priv->num_grps].interruptTransmit = | |
566 | irq_of_parse_and_map(np, 0); | |
567 | ||
568 | /* If we aren't the FEC we have multiple interrupts */ | |
569 | if (model && strcasecmp(model, "FEC")) { | |
570 | priv->gfargrp[priv->num_grps].interruptReceive = | |
571 | irq_of_parse_and_map(np, 1); | |
572 | priv->gfargrp[priv->num_grps].interruptError = | |
573 | irq_of_parse_and_map(np,2); | |
28cb6ccd NK |
574 | if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ || |
575 | priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ || | |
576 | priv->gfargrp[priv->num_grps].interruptError == NO_IRQ) | |
46ceb60c | 577 | return -EINVAL; |
46ceb60c SG |
578 | } |
579 | ||
580 | priv->gfargrp[priv->num_grps].grp_id = priv->num_grps; | |
581 | priv->gfargrp[priv->num_grps].priv = priv; | |
582 | spin_lock_init(&priv->gfargrp[priv->num_grps].grplock); | |
583 | if(priv->mode == MQ_MG_MODE) { | |
584 | queue_mask = (u32 *)of_get_property(np, | |
585 | "fsl,rx-bit-map", NULL); | |
586 | priv->gfargrp[priv->num_grps].rx_bit_map = | |
587 | queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps); | |
588 | queue_mask = (u32 *)of_get_property(np, | |
589 | "fsl,tx-bit-map", NULL); | |
590 | priv->gfargrp[priv->num_grps].tx_bit_map = | |
591 | queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); | |
592 | } else { | |
593 | priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF; | |
594 | priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF; | |
595 | } | |
596 | priv->num_grps++; | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
2dc11581 | 601 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 602 | { |
b31a1d8b AF |
603 | const char *model; |
604 | const char *ctype; | |
605 | const void *mac_addr; | |
fba4ed03 SG |
606 | int err = 0, i; |
607 | struct net_device *dev = NULL; | |
608 | struct gfar_private *priv = NULL; | |
61c7a080 | 609 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 610 | struct device_node *child = NULL; |
4d7902f2 AF |
611 | const u32 *stash; |
612 | const u32 *stash_len; | |
613 | const u32 *stash_idx; | |
fba4ed03 SG |
614 | unsigned int num_tx_qs, num_rx_qs; |
615 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
616 | |
617 | if (!np || !of_device_is_available(np)) | |
618 | return -ENODEV; | |
619 | ||
fba4ed03 SG |
620 | /* parse the num of tx and rx queues */ |
621 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
622 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
623 | ||
624 | if (num_tx_qs > MAX_TX_QS) { | |
59deab26 JP |
625 | pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", |
626 | num_tx_qs, MAX_TX_QS); | |
627 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
628 | return -EINVAL; |
629 | } | |
630 | ||
631 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
632 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
633 | ||
634 | if (num_rx_qs > MAX_RX_QS) { | |
59deab26 JP |
635 | pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", |
636 | num_rx_qs, MAX_RX_QS); | |
637 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
638 | return -EINVAL; |
639 | } | |
640 | ||
641 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
642 | dev = *pdev; | |
643 | if (NULL == dev) | |
644 | return -ENOMEM; | |
645 | ||
646 | priv = netdev_priv(dev); | |
61c7a080 | 647 | priv->node = ofdev->dev.of_node; |
fba4ed03 SG |
648 | priv->ndev = dev; |
649 | ||
fba4ed03 | 650 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 651 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 652 | priv->num_rx_queues = num_rx_qs; |
46ceb60c | 653 | priv->num_grps = 0x0; |
b31a1d8b | 654 | |
0977f817 | 655 | /* Init Rx queue filer rule set linked list */ |
4aa3a715 SP |
656 | INIT_LIST_HEAD(&priv->rx_list.list); |
657 | priv->rx_list.count = 0; | |
658 | mutex_init(&priv->rx_queue_access); | |
659 | ||
b31a1d8b AF |
660 | model = of_get_property(np, "model", NULL); |
661 | ||
46ceb60c SG |
662 | for (i = 0; i < MAXGROUPS; i++) |
663 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 664 | |
46ceb60c SG |
665 | /* Parse and initialize group specific information */ |
666 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
667 | priv->mode = MQ_MG_MODE; | |
668 | for_each_child_of_node(np, child) { | |
669 | err = gfar_parse_group(child, priv, model); | |
670 | if (err) | |
671 | goto err_grp_init; | |
b31a1d8b | 672 | } |
46ceb60c SG |
673 | } else { |
674 | priv->mode = SQ_SG_MODE; | |
675 | err = gfar_parse_group(np, priv, model); | |
676 | if(err) | |
677 | goto err_grp_init; | |
b31a1d8b AF |
678 | } |
679 | ||
fba4ed03 SG |
680 | for (i = 0; i < priv->num_tx_queues; i++) |
681 | priv->tx_queue[i] = NULL; | |
682 | for (i = 0; i < priv->num_rx_queues; i++) | |
683 | priv->rx_queue[i] = NULL; | |
684 | ||
685 | for (i = 0; i < priv->num_tx_queues; i++) { | |
de47f072 JP |
686 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), |
687 | GFP_KERNEL); | |
fba4ed03 SG |
688 | if (!priv->tx_queue[i]) { |
689 | err = -ENOMEM; | |
690 | goto tx_alloc_failed; | |
691 | } | |
692 | priv->tx_queue[i]->tx_skbuff = NULL; | |
693 | priv->tx_queue[i]->qindex = i; | |
694 | priv->tx_queue[i]->dev = dev; | |
695 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
696 | } | |
697 | ||
698 | for (i = 0; i < priv->num_rx_queues; i++) { | |
de47f072 JP |
699 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), |
700 | GFP_KERNEL); | |
fba4ed03 SG |
701 | if (!priv->rx_queue[i]) { |
702 | err = -ENOMEM; | |
703 | goto rx_alloc_failed; | |
704 | } | |
705 | priv->rx_queue[i]->rx_skbuff = NULL; | |
706 | priv->rx_queue[i]->qindex = i; | |
707 | priv->rx_queue[i]->dev = dev; | |
708 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
709 | } | |
710 | ||
711 | ||
4d7902f2 AF |
712 | stash = of_get_property(np, "bd-stash", NULL); |
713 | ||
a12f801d | 714 | if (stash) { |
4d7902f2 AF |
715 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
716 | priv->bd_stash_en = 1; | |
717 | } | |
718 | ||
719 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
720 | ||
721 | if (stash_len) | |
722 | priv->rx_stash_size = *stash_len; | |
723 | ||
724 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
725 | ||
726 | if (stash_idx) | |
727 | priv->rx_stash_index = *stash_idx; | |
728 | ||
729 | if (stash_len || stash_idx) | |
730 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
731 | ||
b31a1d8b AF |
732 | mac_addr = of_get_mac_address(np); |
733 | if (mac_addr) | |
6a3c910c | 734 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
b31a1d8b AF |
735 | |
736 | if (model && !strcasecmp(model, "TSEC")) | |
737 | priv->device_flags = | |
738 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
739 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
740 | FSL_GIANFAR_DEV_HAS_RMON | | |
741 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
742 | if (model && !strcasecmp(model, "eTSEC")) | |
743 | priv->device_flags = | |
744 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
745 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
746 | FSL_GIANFAR_DEV_HAS_RMON | | |
747 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
2c2db48a | 748 | FSL_GIANFAR_DEV_HAS_PADDING | |
b31a1d8b AF |
749 | FSL_GIANFAR_DEV_HAS_CSUM | |
750 | FSL_GIANFAR_DEV_HAS_VLAN | | |
751 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
97553f7f MR |
752 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | |
753 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
754 | |
755 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
756 | ||
757 | /* We only care about rgmii-id. The rest are autodetected */ | |
758 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
759 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
760 | else | |
761 | priv->interface = PHY_INTERFACE_MODE_MII; | |
762 | ||
763 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
764 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
765 | ||
fe192a49 | 766 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
767 | |
768 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 769 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
770 | |
771 | return 0; | |
772 | ||
fba4ed03 SG |
773 | rx_alloc_failed: |
774 | free_rx_pointers(priv); | |
775 | tx_alloc_failed: | |
776 | free_tx_pointers(priv); | |
46ceb60c SG |
777 | err_grp_init: |
778 | unmap_group_regs(priv); | |
fba4ed03 | 779 | free_netdev(dev); |
b31a1d8b AF |
780 | return err; |
781 | } | |
782 | ||
cc772ab7 MR |
783 | static int gfar_hwtstamp_ioctl(struct net_device *netdev, |
784 | struct ifreq *ifr, int cmd) | |
785 | { | |
786 | struct hwtstamp_config config; | |
787 | struct gfar_private *priv = netdev_priv(netdev); | |
788 | ||
789 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
790 | return -EFAULT; | |
791 | ||
792 | /* reserved for future extensions */ | |
793 | if (config.flags) | |
794 | return -EINVAL; | |
795 | ||
f0ee7acf MR |
796 | switch (config.tx_type) { |
797 | case HWTSTAMP_TX_OFF: | |
798 | priv->hwts_tx_en = 0; | |
799 | break; | |
800 | case HWTSTAMP_TX_ON: | |
801 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
802 | return -ERANGE; | |
803 | priv->hwts_tx_en = 1; | |
804 | break; | |
805 | default: | |
cc772ab7 | 806 | return -ERANGE; |
f0ee7acf | 807 | } |
cc772ab7 MR |
808 | |
809 | switch (config.rx_filter) { | |
810 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
811 | if (priv->hwts_rx_en) { |
812 | stop_gfar(netdev); | |
813 | priv->hwts_rx_en = 0; | |
814 | startup_gfar(netdev); | |
815 | } | |
cc772ab7 MR |
816 | break; |
817 | default: | |
818 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
819 | return -ERANGE; | |
97553f7f MR |
820 | if (!priv->hwts_rx_en) { |
821 | stop_gfar(netdev); | |
822 | priv->hwts_rx_en = 1; | |
823 | startup_gfar(netdev); | |
824 | } | |
cc772ab7 MR |
825 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
826 | break; | |
827 | } | |
828 | ||
829 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
830 | -EFAULT : 0; | |
831 | } | |
832 | ||
0faac9f7 CW |
833 | /* Ioctl MII Interface */ |
834 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
835 | { | |
836 | struct gfar_private *priv = netdev_priv(dev); | |
837 | ||
838 | if (!netif_running(dev)) | |
839 | return -EINVAL; | |
840 | ||
cc772ab7 MR |
841 | if (cmd == SIOCSHWTSTAMP) |
842 | return gfar_hwtstamp_ioctl(dev, rq, cmd); | |
843 | ||
0faac9f7 CW |
844 | if (!priv->phydev) |
845 | return -ENODEV; | |
846 | ||
28b04113 | 847 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
848 | } |
849 | ||
fba4ed03 SG |
850 | static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) |
851 | { | |
852 | unsigned int new_bit_map = 0x0; | |
853 | int mask = 0x1 << (max_qs - 1), i; | |
854 | for (i = 0; i < max_qs; i++) { | |
855 | if (bit_map & mask) | |
856 | new_bit_map = new_bit_map + (1 << i); | |
857 | mask = mask >> 0x1; | |
858 | } | |
859 | return new_bit_map; | |
860 | } | |
7a8b3372 | 861 | |
18294ad1 AV |
862 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
863 | u32 class) | |
7a8b3372 SG |
864 | { |
865 | u32 rqfpr = FPR_FILER_MASK; | |
866 | u32 rqfcr = 0x0; | |
867 | ||
868 | rqfar--; | |
869 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
870 | priv->ftp_rqfpr[rqfar] = rqfpr; |
871 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
872 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
873 | ||
874 | rqfar--; | |
875 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
876 | priv->ftp_rqfpr[rqfar] = rqfpr; |
877 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
878 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
879 | ||
880 | rqfar--; | |
881 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
882 | rqfpr = class; | |
6c43e046 WJB |
883 | priv->ftp_rqfcr[rqfar] = rqfcr; |
884 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
885 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
886 | ||
887 | rqfar--; | |
888 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
889 | rqfpr = class; | |
6c43e046 WJB |
890 | priv->ftp_rqfcr[rqfar] = rqfcr; |
891 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
892 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
893 | ||
894 | return rqfar; | |
895 | } | |
896 | ||
897 | static void gfar_init_filer_table(struct gfar_private *priv) | |
898 | { | |
899 | int i = 0x0; | |
900 | u32 rqfar = MAX_FILER_IDX; | |
901 | u32 rqfcr = 0x0; | |
902 | u32 rqfpr = FPR_FILER_MASK; | |
903 | ||
904 | /* Default rule */ | |
905 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
906 | priv->ftp_rqfcr[rqfar] = rqfcr; |
907 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
908 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
909 | ||
910 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
911 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
912 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
913 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
914 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
915 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
916 | ||
85dd08eb | 917 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
918 | priv->cur_filer_idx = rqfar; |
919 | ||
920 | /* Rest are masked rules */ | |
921 | rqfcr = RQFCR_CMP_NOMATCH; | |
922 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
923 | priv->ftp_rqfcr[i] = rqfcr; |
924 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
925 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
926 | } | |
927 | } | |
928 | ||
7d350977 AV |
929 | static void gfar_detect_errata(struct gfar_private *priv) |
930 | { | |
931 | struct device *dev = &priv->ofdev->dev; | |
932 | unsigned int pvr = mfspr(SPRN_PVR); | |
933 | unsigned int svr = mfspr(SPRN_SVR); | |
934 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
935 | unsigned int rev = svr & 0xffff; | |
936 | ||
937 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
938 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
939 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) | |
940 | priv->errata |= GFAR_ERRATA_74; | |
941 | ||
deb90eac AV |
942 | /* MPC8313 and MPC837x all rev */ |
943 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
944 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) | |
945 | priv->errata |= GFAR_ERRATA_76; | |
946 | ||
511d934f AV |
947 | /* MPC8313 and MPC837x all rev */ |
948 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
949 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) | |
950 | priv->errata |= GFAR_ERRATA_A002; | |
951 | ||
4363c2fd AD |
952 | /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ |
953 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || | |
954 | (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) | |
955 | priv->errata |= GFAR_ERRATA_12; | |
956 | ||
7d350977 AV |
957 | if (priv->errata) |
958 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
959 | priv->errata); | |
960 | } | |
961 | ||
bb40dcbb | 962 | /* Set up the ethernet device structure, private data, |
0977f817 JC |
963 | * and anything else we need before we start |
964 | */ | |
74888760 | 965 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 LT |
966 | { |
967 | u32 tempval; | |
968 | struct net_device *dev = NULL; | |
969 | struct gfar_private *priv = NULL; | |
f4983704 | 970 | struct gfar __iomem *regs = NULL; |
46ceb60c | 971 | int err = 0, i, grp_idx = 0; |
fba4ed03 | 972 | u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; |
46ceb60c | 973 | u32 isrg = 0; |
18294ad1 | 974 | u32 __iomem *baddr; |
1da177e4 | 975 | |
fba4ed03 | 976 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 977 | |
fba4ed03 SG |
978 | if (err) |
979 | return err; | |
1da177e4 LT |
980 | |
981 | priv = netdev_priv(dev); | |
4826857f KG |
982 | priv->ndev = dev; |
983 | priv->ofdev = ofdev; | |
61c7a080 | 984 | priv->node = ofdev->dev.of_node; |
4826857f | 985 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 986 | |
d87eb127 | 987 | spin_lock_init(&priv->bflock); |
ab939905 | 988 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 989 | |
b31a1d8b | 990 | dev_set_drvdata(&ofdev->dev, priv); |
46ceb60c | 991 | regs = priv->gfargrp[0].regs; |
1da177e4 | 992 | |
7d350977 AV |
993 | gfar_detect_errata(priv); |
994 | ||
0977f817 JC |
995 | /* Stop the DMA engine now, in case it was running before |
996 | * (The firmware could have used it, and left it running). | |
997 | */ | |
257d938a | 998 | gfar_halt(dev); |
1da177e4 LT |
999 | |
1000 | /* Reset MAC layer */ | |
f4983704 | 1001 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); |
1da177e4 | 1002 | |
b98ac702 AF |
1003 | /* We need to delay at least 3 TX clocks */ |
1004 | udelay(2); | |
1005 | ||
1da177e4 | 1006 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
f4983704 | 1007 | gfar_write(®s->maccfg1, tempval); |
1da177e4 LT |
1008 | |
1009 | /* Initialize MACCFG2. */ | |
7d350977 AV |
1010 | tempval = MACCFG2_INIT_SETTINGS; |
1011 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1012 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1013 | gfar_write(®s->maccfg2, tempval); | |
1da177e4 LT |
1014 | |
1015 | /* Initialize ECNTRL */ | |
f4983704 | 1016 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
1da177e4 | 1017 | |
1da177e4 | 1018 | /* Set the dev->base_addr to the gfar reg region */ |
f4983704 | 1019 | dev->base_addr = (unsigned long) regs; |
1da177e4 | 1020 | |
b31a1d8b | 1021 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
1022 | |
1023 | /* Fill in the dev structure */ | |
1da177e4 | 1024 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1025 | dev->mtu = 1500; |
26ccfc37 | 1026 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1027 | dev->ethtool_ops = &gfar_ethtool_ops; |
1028 | ||
fba4ed03 | 1029 | /* Register for napi ...We are registering NAPI for each grp */ |
46ceb60c SG |
1030 | for (i = 0; i < priv->num_grps; i++) |
1031 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT); | |
a12f801d | 1032 | |
b31a1d8b | 1033 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 MM |
1034 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
1035 | NETIF_F_RXCSUM; | |
1036 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | | |
1037 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; | |
1038 | } | |
0bbaf069 | 1039 | |
87c288c6 JP |
1040 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
1041 | dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
0bbaf069 | 1042 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
87c288c6 | 1043 | } |
0bbaf069 | 1044 | |
b31a1d8b | 1045 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
1046 | priv->extended_hash = 1; |
1047 | priv->hash_width = 9; | |
1048 | ||
f4983704 SG |
1049 | priv->hash_regs[0] = ®s->igaddr0; |
1050 | priv->hash_regs[1] = ®s->igaddr1; | |
1051 | priv->hash_regs[2] = ®s->igaddr2; | |
1052 | priv->hash_regs[3] = ®s->igaddr3; | |
1053 | priv->hash_regs[4] = ®s->igaddr4; | |
1054 | priv->hash_regs[5] = ®s->igaddr5; | |
1055 | priv->hash_regs[6] = ®s->igaddr6; | |
1056 | priv->hash_regs[7] = ®s->igaddr7; | |
1057 | priv->hash_regs[8] = ®s->gaddr0; | |
1058 | priv->hash_regs[9] = ®s->gaddr1; | |
1059 | priv->hash_regs[10] = ®s->gaddr2; | |
1060 | priv->hash_regs[11] = ®s->gaddr3; | |
1061 | priv->hash_regs[12] = ®s->gaddr4; | |
1062 | priv->hash_regs[13] = ®s->gaddr5; | |
1063 | priv->hash_regs[14] = ®s->gaddr6; | |
1064 | priv->hash_regs[15] = ®s->gaddr7; | |
0bbaf069 KG |
1065 | |
1066 | } else { | |
1067 | priv->extended_hash = 0; | |
1068 | priv->hash_width = 8; | |
1069 | ||
f4983704 SG |
1070 | priv->hash_regs[0] = ®s->gaddr0; |
1071 | priv->hash_regs[1] = ®s->gaddr1; | |
1072 | priv->hash_regs[2] = ®s->gaddr2; | |
1073 | priv->hash_regs[3] = ®s->gaddr3; | |
1074 | priv->hash_regs[4] = ®s->gaddr4; | |
1075 | priv->hash_regs[5] = ®s->gaddr5; | |
1076 | priv->hash_regs[6] = ®s->gaddr6; | |
1077 | priv->hash_regs[7] = ®s->gaddr7; | |
0bbaf069 KG |
1078 | } |
1079 | ||
b31a1d8b | 1080 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
1081 | priv->padding = DEFAULT_PADDING; |
1082 | else | |
1083 | priv->padding = 0; | |
1084 | ||
cc772ab7 MR |
1085 | if (dev->features & NETIF_F_IP_CSUM || |
1086 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) | |
bee9e58c | 1087 | dev->needed_headroom = GMAC_FCB_LEN; |
1da177e4 | 1088 | |
46ceb60c SG |
1089 | /* Program the isrg regs only if number of grps > 1 */ |
1090 | if (priv->num_grps > 1) { | |
1091 | baddr = ®s->isrg0; | |
1092 | for (i = 0; i < priv->num_grps; i++) { | |
1093 | isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); | |
1094 | isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); | |
1095 | gfar_write(baddr, isrg); | |
1096 | baddr++; | |
1097 | isrg = 0x0; | |
1098 | } | |
1099 | } | |
1100 | ||
fba4ed03 | 1101 | /* Need to reverse the bit maps as bit_map's MSB is q0 |
984b3f57 | 1102 | * but, for_each_set_bit parses from right to left, which |
0977f817 JC |
1103 | * basically reverses the queue numbers |
1104 | */ | |
46ceb60c SG |
1105 | for (i = 0; i< priv->num_grps; i++) { |
1106 | priv->gfargrp[i].tx_bit_map = reverse_bitmap( | |
1107 | priv->gfargrp[i].tx_bit_map, MAX_TX_QS); | |
1108 | priv->gfargrp[i].rx_bit_map = reverse_bitmap( | |
1109 | priv->gfargrp[i].rx_bit_map, MAX_RX_QS); | |
1110 | } | |
1111 | ||
1112 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
0977f817 JC |
1113 | * also assign queues to groups |
1114 | */ | |
46ceb60c SG |
1115 | for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { |
1116 | priv->gfargrp[grp_idx].num_rx_queues = 0x0; | |
984b3f57 | 1117 | for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, |
46ceb60c SG |
1118 | priv->num_rx_queues) { |
1119 | priv->gfargrp[grp_idx].num_rx_queues++; | |
1120 | priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1121 | rstat = rstat | (RSTAT_CLEAR_RHALT >> i); | |
1122 | rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
1123 | } | |
1124 | priv->gfargrp[grp_idx].num_tx_queues = 0x0; | |
984b3f57 | 1125 | for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, |
46ceb60c SG |
1126 | priv->num_tx_queues) { |
1127 | priv->gfargrp[grp_idx].num_tx_queues++; | |
1128 | priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1129 | tstat = tstat | (TSTAT_CLEAR_THALT >> i); | |
1130 | tqueue = tqueue | (TQUEUE_EN0 >> i); | |
1131 | } | |
1132 | priv->gfargrp[grp_idx].rstat = rstat; | |
1133 | priv->gfargrp[grp_idx].tstat = tstat; | |
1134 | rstat = tstat =0; | |
fba4ed03 | 1135 | } |
fba4ed03 SG |
1136 | |
1137 | gfar_write(®s->rqueue, rqueue); | |
1138 | gfar_write(®s->tqueue, tqueue); | |
1139 | ||
1da177e4 | 1140 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; |
1da177e4 | 1141 | |
a12f801d | 1142 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1143 | for (i = 0; i < priv->num_tx_queues; i++) { |
1144 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1145 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1146 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1147 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1148 | } | |
a12f801d | 1149 | |
fba4ed03 SG |
1150 | for (i = 0; i < priv->num_rx_queues; i++) { |
1151 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1152 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1153 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1154 | } | |
1da177e4 | 1155 | |
0977f817 | 1156 | /* always enable rx filer */ |
4aa3a715 | 1157 | priv->rx_filer_enable = 1; |
0bbaf069 KG |
1158 | /* Enable most messages by default */ |
1159 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1160 | ||
d3eab82b TP |
1161 | /* Carrier starts down, phylib will bring it up */ |
1162 | netif_carrier_off(dev); | |
1163 | ||
1da177e4 LT |
1164 | err = register_netdev(dev); |
1165 | ||
1166 | if (err) { | |
59deab26 | 1167 | pr_err("%s: Cannot register net device, aborting\n", dev->name); |
1da177e4 LT |
1168 | goto register_fail; |
1169 | } | |
1170 | ||
2884e5cc AV |
1171 | device_init_wakeup(&dev->dev, |
1172 | priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
1173 | ||
c50a5d9a | 1174 | /* fill out IRQ number and name fields */ |
46ceb60c | 1175 | for (i = 0; i < priv->num_grps; i++) { |
46ceb60c | 1176 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0015e551 JP |
1177 | sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s", |
1178 | dev->name, "_g", '0' + i, "_tx"); | |
1179 | sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s", | |
1180 | dev->name, "_g", '0' + i, "_rx"); | |
1181 | sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s", | |
1182 | dev->name, "_g", '0' + i, "_er"); | |
46ceb60c | 1183 | } else |
0015e551 | 1184 | strcpy(priv->gfargrp[i].int_name_tx, dev->name); |
46ceb60c | 1185 | } |
c50a5d9a | 1186 | |
7a8b3372 SG |
1187 | /* Initialize the filer table */ |
1188 | gfar_init_filer_table(priv); | |
1189 | ||
7f7f5316 AF |
1190 | /* Create all the sysfs files */ |
1191 | gfar_init_sysfs(dev); | |
1192 | ||
1da177e4 | 1193 | /* Print out the device info */ |
59deab26 | 1194 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
1da177e4 | 1195 | |
0977f817 JC |
1196 | /* Even more device info helps when determining which kernel |
1197 | * provided which set of benchmarks. | |
1198 | */ | |
59deab26 | 1199 | netdev_info(dev, "Running with NAPI enabled\n"); |
fba4ed03 | 1200 | for (i = 0; i < priv->num_rx_queues; i++) |
59deab26 JP |
1201 | netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", |
1202 | i, priv->rx_queue[i]->rx_ring_size); | |
fba4ed03 | 1203 | for(i = 0; i < priv->num_tx_queues; i++) |
59deab26 JP |
1204 | netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", |
1205 | i, priv->tx_queue[i]->tx_ring_size); | |
1da177e4 LT |
1206 | |
1207 | return 0; | |
1208 | ||
1209 | register_fail: | |
46ceb60c | 1210 | unmap_group_regs(priv); |
fba4ed03 SG |
1211 | free_tx_pointers(priv); |
1212 | free_rx_pointers(priv); | |
fe192a49 GL |
1213 | if (priv->phy_node) |
1214 | of_node_put(priv->phy_node); | |
1215 | if (priv->tbi_node) | |
1216 | of_node_put(priv->tbi_node); | |
1da177e4 | 1217 | free_netdev(dev); |
bb40dcbb | 1218 | return err; |
1da177e4 LT |
1219 | } |
1220 | ||
2dc11581 | 1221 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1222 | { |
b31a1d8b | 1223 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 1224 | |
fe192a49 GL |
1225 | if (priv->phy_node) |
1226 | of_node_put(priv->phy_node); | |
1227 | if (priv->tbi_node) | |
1228 | of_node_put(priv->tbi_node); | |
1229 | ||
b31a1d8b | 1230 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 1231 | |
d9d8e041 | 1232 | unregister_netdev(priv->ndev); |
46ceb60c | 1233 | unmap_group_regs(priv); |
4826857f | 1234 | free_netdev(priv->ndev); |
1da177e4 LT |
1235 | |
1236 | return 0; | |
1237 | } | |
1238 | ||
d87eb127 | 1239 | #ifdef CONFIG_PM |
be926fc4 AV |
1240 | |
1241 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1242 | { |
be926fc4 AV |
1243 | struct gfar_private *priv = dev_get_drvdata(dev); |
1244 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1245 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1246 | unsigned long flags; |
1247 | u32 tempval; | |
1248 | ||
1249 | int magic_packet = priv->wol_en && | |
b31a1d8b | 1250 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 | 1251 | |
be926fc4 | 1252 | netif_device_detach(ndev); |
d87eb127 | 1253 | |
be926fc4 | 1254 | if (netif_running(ndev)) { |
fba4ed03 SG |
1255 | |
1256 | local_irq_save(flags); | |
1257 | lock_tx_qs(priv); | |
1258 | lock_rx_qs(priv); | |
d87eb127 | 1259 | |
be926fc4 | 1260 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1261 | |
1262 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1263 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1264 | |
1265 | tempval &= ~MACCFG1_TX_EN; | |
1266 | ||
1267 | if (!magic_packet) | |
1268 | tempval &= ~MACCFG1_RX_EN; | |
1269 | ||
f4983704 | 1270 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1271 | |
fba4ed03 SG |
1272 | unlock_rx_qs(priv); |
1273 | unlock_tx_qs(priv); | |
1274 | local_irq_restore(flags); | |
d87eb127 | 1275 | |
46ceb60c | 1276 | disable_napi(priv); |
d87eb127 SW |
1277 | |
1278 | if (magic_packet) { | |
1279 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1280 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1281 | |
1282 | /* Enable Magic Packet mode */ | |
f4983704 | 1283 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1284 | tempval |= MACCFG2_MPEN; |
f4983704 | 1285 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1286 | } else { |
1287 | phy_stop(priv->phydev); | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
be926fc4 | 1294 | static int gfar_resume(struct device *dev) |
d87eb127 | 1295 | { |
be926fc4 AV |
1296 | struct gfar_private *priv = dev_get_drvdata(dev); |
1297 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1298 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1299 | unsigned long flags; |
1300 | u32 tempval; | |
1301 | int magic_packet = priv->wol_en && | |
b31a1d8b | 1302 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 | 1303 | |
be926fc4 AV |
1304 | if (!netif_running(ndev)) { |
1305 | netif_device_attach(ndev); | |
d87eb127 SW |
1306 | return 0; |
1307 | } | |
1308 | ||
1309 | if (!magic_packet && priv->phydev) | |
1310 | phy_start(priv->phydev); | |
1311 | ||
1312 | /* Disable Magic Packet mode, in case something | |
1313 | * else woke us up. | |
1314 | */ | |
fba4ed03 SG |
1315 | local_irq_save(flags); |
1316 | lock_tx_qs(priv); | |
1317 | lock_rx_qs(priv); | |
d87eb127 | 1318 | |
f4983704 | 1319 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1320 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1321 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1322 | |
be926fc4 | 1323 | gfar_start(ndev); |
d87eb127 | 1324 | |
fba4ed03 SG |
1325 | unlock_rx_qs(priv); |
1326 | unlock_tx_qs(priv); | |
1327 | local_irq_restore(flags); | |
d87eb127 | 1328 | |
be926fc4 AV |
1329 | netif_device_attach(ndev); |
1330 | ||
46ceb60c | 1331 | enable_napi(priv); |
be926fc4 AV |
1332 | |
1333 | return 0; | |
1334 | } | |
1335 | ||
1336 | static int gfar_restore(struct device *dev) | |
1337 | { | |
1338 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1339 | struct net_device *ndev = priv->ndev; | |
1340 | ||
1341 | if (!netif_running(ndev)) | |
1342 | return 0; | |
1343 | ||
1344 | gfar_init_bds(ndev); | |
1345 | init_registers(ndev); | |
1346 | gfar_set_mac_address(ndev); | |
1347 | gfar_init_mac(ndev); | |
1348 | gfar_start(ndev); | |
1349 | ||
1350 | priv->oldlink = 0; | |
1351 | priv->oldspeed = 0; | |
1352 | priv->oldduplex = -1; | |
1353 | ||
1354 | if (priv->phydev) | |
1355 | phy_start(priv->phydev); | |
d87eb127 | 1356 | |
be926fc4 | 1357 | netif_device_attach(ndev); |
5ea681d4 | 1358 | enable_napi(priv); |
d87eb127 SW |
1359 | |
1360 | return 0; | |
1361 | } | |
be926fc4 AV |
1362 | |
1363 | static struct dev_pm_ops gfar_pm_ops = { | |
1364 | .suspend = gfar_suspend, | |
1365 | .resume = gfar_resume, | |
1366 | .freeze = gfar_suspend, | |
1367 | .thaw = gfar_resume, | |
1368 | .restore = gfar_restore, | |
1369 | }; | |
1370 | ||
1371 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1372 | ||
d87eb127 | 1373 | #else |
be926fc4 AV |
1374 | |
1375 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1376 | |
d87eb127 | 1377 | #endif |
1da177e4 | 1378 | |
e8a2b6a4 AF |
1379 | /* Reads the controller's registers to determine what interface |
1380 | * connects it to the PHY. | |
1381 | */ | |
1382 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1383 | { | |
1384 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1385 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1386 | u32 ecntrl; |
1387 | ||
f4983704 | 1388 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1389 | |
1390 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1391 | return PHY_INTERFACE_MODE_SGMII; | |
1392 | ||
1393 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1394 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1395 | return PHY_INTERFACE_MODE_RTBI; | |
1396 | else | |
1397 | return PHY_INTERFACE_MODE_TBI; | |
1398 | } | |
1399 | ||
1400 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
1401 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) | |
1402 | return PHY_INTERFACE_MODE_RMII; | |
7132ab7f | 1403 | else { |
b31a1d8b | 1404 | phy_interface_t interface = priv->interface; |
7132ab7f | 1405 | |
0977f817 | 1406 | /* This isn't autodetected right now, so it must |
7132ab7f AF |
1407 | * be set by the device tree or platform code. |
1408 | */ | |
1409 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1410 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1411 | ||
e8a2b6a4 | 1412 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1413 | } |
e8a2b6a4 AF |
1414 | } |
1415 | ||
b31a1d8b | 1416 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1417 | return PHY_INTERFACE_MODE_GMII; |
1418 | ||
1419 | return PHY_INTERFACE_MODE_MII; | |
1420 | } | |
1421 | ||
1422 | ||
bb40dcbb AF |
1423 | /* Initializes driver's PHY state, and attaches to the PHY. |
1424 | * Returns 0 on success. | |
1da177e4 LT |
1425 | */ |
1426 | static int init_phy(struct net_device *dev) | |
1427 | { | |
1428 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1429 | uint gigabit_support = |
b31a1d8b | 1430 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 1431 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 1432 | phy_interface_t interface; |
1da177e4 LT |
1433 | |
1434 | priv->oldlink = 0; | |
1435 | priv->oldspeed = 0; | |
1436 | priv->oldduplex = -1; | |
1437 | ||
e8a2b6a4 AF |
1438 | interface = gfar_get_interface(dev); |
1439 | ||
1db780f8 AV |
1440 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1441 | interface); | |
1442 | if (!priv->phydev) | |
1443 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1444 | interface); | |
1445 | if (!priv->phydev) { | |
1446 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1447 | return -ENODEV; | |
fe192a49 | 1448 | } |
1da177e4 | 1449 | |
d3c12873 KJ |
1450 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1451 | gfar_configure_serdes(dev); | |
1452 | ||
bb40dcbb | 1453 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1454 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1455 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1456 | |
1457 | return 0; | |
1da177e4 LT |
1458 | } |
1459 | ||
0977f817 | 1460 | /* Initialize TBI PHY interface for communicating with the |
d0313587 PG |
1461 | * SERDES lynx PHY on the chip. We communicate with this PHY |
1462 | * through the MDIO bus on each controller, treating it as a | |
1463 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1464 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1465 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1466 | * value doesn't matter, as there are no other PHYs on the bus. | |
1467 | */ | |
d3c12873 KJ |
1468 | static void gfar_configure_serdes(struct net_device *dev) |
1469 | { | |
1470 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1471 | struct phy_device *tbiphy; |
1472 | ||
1473 | if (!priv->tbi_node) { | |
1474 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1475 | "device tree specify a tbi-handle\n"); | |
1476 | return; | |
1477 | } | |
c132419e | 1478 | |
fe192a49 GL |
1479 | tbiphy = of_phy_find_device(priv->tbi_node); |
1480 | if (!tbiphy) { | |
1481 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1482 | return; |
1483 | } | |
d3c12873 | 1484 | |
0977f817 | 1485 | /* If the link is already up, we must already be ok, and don't need to |
bdb59f94 TP |
1486 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1487 | * everything for us? Resetting it takes the link down and requires | |
1488 | * several seconds for it to come back. | |
1489 | */ | |
fe192a49 | 1490 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1491 | return; |
d3c12873 | 1492 | |
d0313587 | 1493 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1494 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1495 | |
fe192a49 | 1496 | phy_write(tbiphy, MII_ADVERTISE, |
d3c12873 KJ |
1497 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1498 | ADVERTISE_1000XPSE_ASYM); | |
1499 | ||
fe192a49 | 1500 | phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE | |
d3c12873 KJ |
1501 | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); |
1502 | } | |
1503 | ||
1da177e4 LT |
1504 | static void init_registers(struct net_device *dev) |
1505 | { | |
1506 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 1507 | struct gfar __iomem *regs = NULL; |
46ceb60c | 1508 | int i = 0; |
1da177e4 | 1509 | |
46ceb60c SG |
1510 | for (i = 0; i < priv->num_grps; i++) { |
1511 | regs = priv->gfargrp[i].regs; | |
1512 | /* Clear IEVENT */ | |
1513 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1da177e4 | 1514 | |
46ceb60c SG |
1515 | /* Initialize IMASK */ |
1516 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1517 | } | |
1da177e4 | 1518 | |
46ceb60c | 1519 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1520 | /* Init hash registers to zero */ |
f4983704 SG |
1521 | gfar_write(®s->igaddr0, 0); |
1522 | gfar_write(®s->igaddr1, 0); | |
1523 | gfar_write(®s->igaddr2, 0); | |
1524 | gfar_write(®s->igaddr3, 0); | |
1525 | gfar_write(®s->igaddr4, 0); | |
1526 | gfar_write(®s->igaddr5, 0); | |
1527 | gfar_write(®s->igaddr6, 0); | |
1528 | gfar_write(®s->igaddr7, 0); | |
1529 | ||
1530 | gfar_write(®s->gaddr0, 0); | |
1531 | gfar_write(®s->gaddr1, 0); | |
1532 | gfar_write(®s->gaddr2, 0); | |
1533 | gfar_write(®s->gaddr3, 0); | |
1534 | gfar_write(®s->gaddr4, 0); | |
1535 | gfar_write(®s->gaddr5, 0); | |
1536 | gfar_write(®s->gaddr6, 0); | |
1537 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1538 | |
1da177e4 | 1539 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1540 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1541 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1542 | |
1543 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1544 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1545 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1546 | } |
1547 | ||
1548 | /* Initialize the max receive buffer length */ | |
f4983704 | 1549 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1550 | |
1da177e4 | 1551 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1552 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1553 | } |
1554 | ||
511d934f AV |
1555 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1556 | { | |
1557 | u32 res; | |
1558 | ||
0977f817 | 1559 | /* Normaly TSEC should not hang on GRS commands, so we should |
511d934f AV |
1560 | * actually wait for IEVENT_GRSC flag. |
1561 | */ | |
1562 | if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) | |
1563 | return 0; | |
1564 | ||
0977f817 | 1565 | /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are |
511d934f AV |
1566 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle |
1567 | * and the Rx can be safely reset. | |
1568 | */ | |
1569 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1570 | res &= 0x7f807f80; | |
1571 | if ((res & 0xffff) == (res >> 16)) | |
1572 | return 1; | |
1573 | ||
1574 | return 0; | |
1575 | } | |
0bbaf069 KG |
1576 | |
1577 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1578 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1579 | { |
1580 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1581 | struct gfar __iomem *regs = NULL; |
1da177e4 | 1582 | u32 tempval; |
46ceb60c | 1583 | int i = 0; |
1da177e4 | 1584 | |
46ceb60c SG |
1585 | for (i = 0; i < priv->num_grps; i++) { |
1586 | regs = priv->gfargrp[i].regs; | |
1587 | /* Mask all interrupts */ | |
1588 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1da177e4 | 1589 | |
46ceb60c SG |
1590 | /* Clear all interrupts */ |
1591 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1592 | } | |
1da177e4 | 1593 | |
46ceb60c | 1594 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1595 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1596 | tempval = gfar_read(®s->dmactrl); |
1da177e4 LT |
1597 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) |
1598 | != (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1599 | int ret; |
1600 | ||
1da177e4 | 1601 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1602 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1603 | |
511d934f AV |
1604 | do { |
1605 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1606 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1607 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1608 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1609 | ret = __gfar_is_rx_idle(priv); | |
1610 | } while (!ret); | |
1da177e4 | 1611 | } |
d87eb127 | 1612 | } |
d87eb127 SW |
1613 | |
1614 | /* Halt the receive and transmit queues */ | |
1615 | void gfar_halt(struct net_device *dev) | |
1616 | { | |
1617 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1618 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1619 | u32 tempval; |
1da177e4 | 1620 | |
2a54adc3 SW |
1621 | gfar_halt_nodisable(dev); |
1622 | ||
1da177e4 LT |
1623 | /* Disable Rx and Tx */ |
1624 | tempval = gfar_read(®s->maccfg1); | |
1625 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1626 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1627 | } |
1628 | ||
46ceb60c SG |
1629 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1630 | { | |
1631 | free_irq(grp->interruptError, grp); | |
1632 | free_irq(grp->interruptTransmit, grp); | |
1633 | free_irq(grp->interruptReceive, grp); | |
1634 | } | |
1635 | ||
0bbaf069 KG |
1636 | void stop_gfar(struct net_device *dev) |
1637 | { | |
1638 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1639 | unsigned long flags; |
46ceb60c | 1640 | int i; |
0bbaf069 | 1641 | |
bb40dcbb AF |
1642 | phy_stop(priv->phydev); |
1643 | ||
a12f801d | 1644 | |
0bbaf069 | 1645 | /* Lock it down */ |
fba4ed03 SG |
1646 | local_irq_save(flags); |
1647 | lock_tx_qs(priv); | |
1648 | lock_rx_qs(priv); | |
0bbaf069 | 1649 | |
0bbaf069 | 1650 | gfar_halt(dev); |
1da177e4 | 1651 | |
fba4ed03 SG |
1652 | unlock_rx_qs(priv); |
1653 | unlock_tx_qs(priv); | |
1654 | local_irq_restore(flags); | |
1da177e4 LT |
1655 | |
1656 | /* Free the IRQs */ | |
b31a1d8b | 1657 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1658 | for (i = 0; i < priv->num_grps; i++) |
1659 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1660 | } else { |
46ceb60c SG |
1661 | for (i = 0; i < priv->num_grps; i++) |
1662 | free_irq(priv->gfargrp[i].interruptTransmit, | |
1663 | &priv->gfargrp[i]); | |
1da177e4 LT |
1664 | } |
1665 | ||
1666 | free_skb_resources(priv); | |
1da177e4 LT |
1667 | } |
1668 | ||
fba4ed03 | 1669 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1670 | { |
1da177e4 | 1671 | struct txbd8 *txbdp; |
fba4ed03 | 1672 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1673 | int i, j; |
1da177e4 | 1674 | |
a12f801d | 1675 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1676 | |
a12f801d SG |
1677 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1678 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1679 | continue; |
1da177e4 | 1680 | |
4826857f | 1681 | dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 DH |
1682 | txbdp->length, DMA_TO_DEVICE); |
1683 | txbdp->lstatus = 0; | |
fba4ed03 SG |
1684 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
1685 | j++) { | |
4669bc90 | 1686 | txbdp++; |
4826857f | 1687 | dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 | 1688 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1689 | } |
ad5da7ab | 1690 | txbdp++; |
a12f801d SG |
1691 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1692 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1693 | } |
a12f801d | 1694 | kfree(tx_queue->tx_skbuff); |
fba4ed03 | 1695 | } |
1da177e4 | 1696 | |
fba4ed03 SG |
1697 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1698 | { | |
1699 | struct rxbd8 *rxbdp; | |
1700 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1701 | int i; | |
1da177e4 | 1702 | |
fba4ed03 | 1703 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1704 | |
a12f801d SG |
1705 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1706 | if (rx_queue->rx_skbuff[i]) { | |
fba4ed03 SG |
1707 | dma_unmap_single(&priv->ofdev->dev, |
1708 | rxbdp->bufPtr, priv->rx_buffer_size, | |
e69edd21 | 1709 | DMA_FROM_DEVICE); |
a12f801d SG |
1710 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1711 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1712 | } |
e69edd21 AV |
1713 | rxbdp->lstatus = 0; |
1714 | rxbdp->bufPtr = 0; | |
1715 | rxbdp++; | |
1da177e4 | 1716 | } |
a12f801d | 1717 | kfree(rx_queue->rx_skbuff); |
fba4ed03 | 1718 | } |
e69edd21 | 1719 | |
fba4ed03 | 1720 | /* If there are any tx skbs or rx skbs still around, free them. |
0977f817 JC |
1721 | * Then free tx_skbuff and rx_skbuff |
1722 | */ | |
fba4ed03 SG |
1723 | static void free_skb_resources(struct gfar_private *priv) |
1724 | { | |
1725 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1726 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1727 | int i; | |
1728 | ||
1729 | /* Go through all the buffer descriptors and free their data buffers */ | |
1730 | for (i = 0; i < priv->num_tx_queues; i++) { | |
d8a0f1b0 | 1731 | struct netdev_queue *txq; |
fba4ed03 | 1732 | tx_queue = priv->tx_queue[i]; |
d8a0f1b0 | 1733 | txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); |
7c0d10d3 | 1734 | if(tx_queue->tx_skbuff) |
fba4ed03 | 1735 | free_skb_tx_queue(tx_queue); |
d8a0f1b0 | 1736 | netdev_tx_reset_queue(txq); |
fba4ed03 SG |
1737 | } |
1738 | ||
1739 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1740 | rx_queue = priv->rx_queue[i]; | |
7c0d10d3 | 1741 | if(rx_queue->rx_skbuff) |
fba4ed03 SG |
1742 | free_skb_rx_queue(rx_queue); |
1743 | } | |
1744 | ||
1745 | dma_free_coherent(&priv->ofdev->dev, | |
1746 | sizeof(struct txbd8) * priv->total_tx_ring_size + | |
1747 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1748 | priv->tx_queue[0]->tx_bd_base, | |
1749 | priv->tx_queue[0]->tx_bd_dma_base); | |
7df9c43f | 1750 | skb_queue_purge(&priv->rx_recycle); |
1da177e4 LT |
1751 | } |
1752 | ||
0bbaf069 KG |
1753 | void gfar_start(struct net_device *dev) |
1754 | { | |
1755 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1756 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1757 | u32 tempval; |
46ceb60c | 1758 | int i = 0; |
0bbaf069 KG |
1759 | |
1760 | /* Enable Rx and Tx in MACCFG1 */ | |
1761 | tempval = gfar_read(®s->maccfg1); | |
1762 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1763 | gfar_write(®s->maccfg1, tempval); | |
1764 | ||
1765 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1766 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1767 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1768 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1769 | |
0bbaf069 | 1770 | /* Make sure we aren't stopped */ |
f4983704 | 1771 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1772 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1773 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1774 | |
46ceb60c SG |
1775 | for (i = 0; i < priv->num_grps; i++) { |
1776 | regs = priv->gfargrp[i].regs; | |
1777 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1778 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1779 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
1780 | /* Unmask the interrupts we look for */ | |
1781 | gfar_write(®s->imask, IMASK_DEFAULT); | |
1782 | } | |
12dea57b | 1783 | |
1ae5dc34 | 1784 | dev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1785 | } |
1786 | ||
46ceb60c | 1787 | void gfar_configure_coalescing(struct gfar_private *priv, |
18294ad1 | 1788 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1789 | { |
46ceb60c | 1790 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1791 | u32 __iomem *baddr; |
46ceb60c | 1792 | int i = 0; |
1da177e4 | 1793 | |
46ceb60c SG |
1794 | /* Backward compatible case ---- even if we enable |
1795 | * multiple queues, there's only single reg to program | |
1796 | */ | |
1797 | gfar_write(®s->txic, 0); | |
1798 | if(likely(priv->tx_queue[0]->txcoalescing)) | |
1799 | gfar_write(®s->txic, priv->tx_queue[0]->txic); | |
1da177e4 | 1800 | |
46ceb60c SG |
1801 | gfar_write(®s->rxic, 0); |
1802 | if(unlikely(priv->rx_queue[0]->rxcoalescing)) | |
1803 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); | |
815b97c6 | 1804 | |
46ceb60c SG |
1805 | if (priv->mode == MQ_MG_MODE) { |
1806 | baddr = ®s->txic0; | |
984b3f57 | 1807 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
46ceb60c SG |
1808 | if (likely(priv->tx_queue[i]->txcoalescing)) { |
1809 | gfar_write(baddr + i, 0); | |
1810 | gfar_write(baddr + i, priv->tx_queue[i]->txic); | |
1811 | } | |
1812 | } | |
1813 | ||
1814 | baddr = ®s->rxic0; | |
984b3f57 | 1815 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
46ceb60c SG |
1816 | if (likely(priv->rx_queue[i]->rxcoalescing)) { |
1817 | gfar_write(baddr + i, 0); | |
1818 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); | |
1819 | } | |
1820 | } | |
1821 | } | |
1822 | } | |
1823 | ||
1824 | static int register_grp_irqs(struct gfar_priv_grp *grp) | |
1825 | { | |
1826 | struct gfar_private *priv = grp->priv; | |
1827 | struct net_device *dev = priv->ndev; | |
1828 | int err; | |
1da177e4 | 1829 | |
1da177e4 | 1830 | /* If the device has multiple interrupts, register for |
0977f817 JC |
1831 | * them. Otherwise, only register for the one |
1832 | */ | |
b31a1d8b | 1833 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1834 | /* Install our interrupt handlers for Error, |
0977f817 JC |
1835 | * Transmit, and Receive |
1836 | */ | |
46ceb60c SG |
1837 | if ((err = request_irq(grp->interruptError, gfar_error, 0, |
1838 | grp->int_name_er,grp)) < 0) { | |
59deab26 JP |
1839 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1840 | grp->interruptError); | |
46ceb60c | 1841 | |
2145f1af | 1842 | goto err_irq_fail; |
1da177e4 LT |
1843 | } |
1844 | ||
46ceb60c SG |
1845 | if ((err = request_irq(grp->interruptTransmit, gfar_transmit, |
1846 | 0, grp->int_name_tx, grp)) < 0) { | |
59deab26 JP |
1847 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1848 | grp->interruptTransmit); | |
1da177e4 LT |
1849 | goto tx_irq_fail; |
1850 | } | |
1851 | ||
46ceb60c SG |
1852 | if ((err = request_irq(grp->interruptReceive, gfar_receive, 0, |
1853 | grp->int_name_rx, grp)) < 0) { | |
59deab26 JP |
1854 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1855 | grp->interruptReceive); | |
1da177e4 LT |
1856 | goto rx_irq_fail; |
1857 | } | |
1858 | } else { | |
46ceb60c SG |
1859 | if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0, |
1860 | grp->int_name_tx, grp)) < 0) { | |
59deab26 JP |
1861 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1862 | grp->interruptTransmit); | |
1da177e4 LT |
1863 | goto err_irq_fail; |
1864 | } | |
1865 | } | |
1866 | ||
46ceb60c SG |
1867 | return 0; |
1868 | ||
1869 | rx_irq_fail: | |
1870 | free_irq(grp->interruptTransmit, grp); | |
1871 | tx_irq_fail: | |
1872 | free_irq(grp->interruptError, grp); | |
1873 | err_irq_fail: | |
1874 | return err; | |
1875 | ||
1876 | } | |
1877 | ||
1878 | /* Bring the controller up and running */ | |
1879 | int startup_gfar(struct net_device *ndev) | |
1880 | { | |
1881 | struct gfar_private *priv = netdev_priv(ndev); | |
1882 | struct gfar __iomem *regs = NULL; | |
1883 | int err, i, j; | |
1884 | ||
1885 | for (i = 0; i < priv->num_grps; i++) { | |
1886 | regs= priv->gfargrp[i].regs; | |
1887 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1888 | } | |
1889 | ||
1890 | regs= priv->gfargrp[0].regs; | |
1891 | err = gfar_alloc_skb_resources(ndev); | |
1892 | if (err) | |
1893 | return err; | |
1894 | ||
1895 | gfar_init_mac(ndev); | |
1896 | ||
1897 | for (i = 0; i < priv->num_grps; i++) { | |
1898 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1899 | if (err) { | |
1900 | for (j = 0; j < i; j++) | |
1901 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1902 | goto irq_fail; |
46ceb60c SG |
1903 | } |
1904 | } | |
1905 | ||
7f7f5316 | 1906 | /* Start the controller */ |
ccc05c6e | 1907 | gfar_start(ndev); |
1da177e4 | 1908 | |
826aa4a0 AV |
1909 | phy_start(priv->phydev); |
1910 | ||
46ceb60c SG |
1911 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
1912 | ||
1da177e4 LT |
1913 | return 0; |
1914 | ||
46ceb60c | 1915 | irq_fail: |
e69edd21 | 1916 | free_skb_resources(priv); |
1da177e4 LT |
1917 | return err; |
1918 | } | |
1919 | ||
0977f817 JC |
1920 | /* Called when something needs to use the ethernet device |
1921 | * Returns 0 for success. | |
1922 | */ | |
1da177e4 LT |
1923 | static int gfar_enet_open(struct net_device *dev) |
1924 | { | |
94e8cc35 | 1925 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1926 | int err; |
1927 | ||
46ceb60c | 1928 | enable_napi(priv); |
bea3348e | 1929 | |
0fd56bb5 AF |
1930 | skb_queue_head_init(&priv->rx_recycle); |
1931 | ||
1da177e4 LT |
1932 | /* Initialize a bunch of registers */ |
1933 | init_registers(dev); | |
1934 | ||
1935 | gfar_set_mac_address(dev); | |
1936 | ||
1937 | err = init_phy(dev); | |
1938 | ||
a12f801d | 1939 | if (err) { |
46ceb60c | 1940 | disable_napi(priv); |
1da177e4 | 1941 | return err; |
bea3348e | 1942 | } |
1da177e4 LT |
1943 | |
1944 | err = startup_gfar(dev); | |
db0e8e3f | 1945 | if (err) { |
46ceb60c | 1946 | disable_napi(priv); |
db0e8e3f AV |
1947 | return err; |
1948 | } | |
1da177e4 | 1949 | |
fba4ed03 | 1950 | netif_tx_start_all_queues(dev); |
1da177e4 | 1951 | |
2884e5cc AV |
1952 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1953 | ||
1da177e4 LT |
1954 | return err; |
1955 | } | |
1956 | ||
54dc79fe | 1957 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1958 | { |
54dc79fe | 1959 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1960 | |
1961 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1962 | |
0bbaf069 KG |
1963 | return fcb; |
1964 | } | |
1965 | ||
9c4886e5 MR |
1966 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, |
1967 | int fcb_length) | |
0bbaf069 | 1968 | { |
7f7f5316 | 1969 | u8 flags = 0; |
0bbaf069 KG |
1970 | |
1971 | /* If we're here, it's a IP packet with a TCP or UDP | |
1972 | * payload. We set it to checksum, using a pseudo-header | |
1973 | * we provide | |
1974 | */ | |
7f7f5316 | 1975 | flags = TXFCB_DEFAULT; |
0bbaf069 | 1976 | |
0977f817 JC |
1977 | /* Tell the controller what the protocol is |
1978 | * And provide the already calculated phcs | |
1979 | */ | |
eddc9ec5 | 1980 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 1981 | flags |= TXFCB_UDP; |
4bedb452 | 1982 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 1983 | } else |
8da32de5 | 1984 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
1985 | |
1986 | /* l3os is the distance between the start of the | |
1987 | * frame (skb->data) and the start of the IP hdr. | |
1988 | * l4os is the distance between the start of the | |
0977f817 JC |
1989 | * l3 hdr and the l4 hdr |
1990 | */ | |
9c4886e5 | 1991 | fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); |
cfe1fc77 | 1992 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 1993 | |
7f7f5316 | 1994 | fcb->flags = flags; |
0bbaf069 KG |
1995 | } |
1996 | ||
7f7f5316 | 1997 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 1998 | { |
7f7f5316 | 1999 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2000 | fcb->vlctl = vlan_tx_tag_get(skb); |
2001 | } | |
2002 | ||
4669bc90 DH |
2003 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
2004 | struct txbd8 *base, int ring_size) | |
2005 | { | |
2006 | struct txbd8 *new_bd = bdp + stride; | |
2007 | ||
2008 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2009 | } | |
2010 | ||
2011 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
2012 | int ring_size) | |
2013 | { | |
2014 | return skip_txbd(bdp, 1, base, ring_size); | |
2015 | } | |
2016 | ||
0977f817 JC |
2017 | /* This is called by the kernel when a frame is ready for transmission. |
2018 | * It is pointed to by the dev->hard_start_xmit function pointer | |
2019 | */ | |
1da177e4 LT |
2020 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2021 | { | |
2022 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2023 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2024 | struct netdev_queue *txq; |
f4983704 | 2025 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2026 | struct txfcb *fcb = NULL; |
f0ee7acf | 2027 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2028 | u32 lstatus; |
f0ee7acf | 2029 | int i, rq = 0, do_tstamp = 0; |
4669bc90 | 2030 | u32 bufaddr; |
fef6108d | 2031 | unsigned long flags; |
9c4886e5 | 2032 | unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN; |
fba4ed03 | 2033 | |
0977f817 | 2034 | /* TOE=1 frames larger than 2500 bytes may see excess delays |
deb90eac AV |
2035 | * before start of transmission. |
2036 | */ | |
2037 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) && | |
2038 | skb->ip_summed == CHECKSUM_PARTIAL && | |
2039 | skb->len > 2500)) { | |
2040 | int ret; | |
2041 | ||
2042 | ret = skb_checksum_help(skb); | |
2043 | if (ret) | |
2044 | return ret; | |
2045 | } | |
2046 | ||
fba4ed03 SG |
2047 | rq = skb->queue_mapping; |
2048 | tx_queue = priv->tx_queue[rq]; | |
2049 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2050 | base = tx_queue->tx_bd_base; |
46ceb60c | 2051 | regs = tx_queue->grp->regs; |
f0ee7acf MR |
2052 | |
2053 | /* check if time stamp should be generated */ | |
2244d07b | 2054 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
9c4886e5 | 2055 | priv->hwts_tx_en)) { |
f0ee7acf | 2056 | do_tstamp = 1; |
9c4886e5 MR |
2057 | fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
2058 | } | |
4669bc90 | 2059 | |
5b28beaf LY |
2060 | /* make space for additional header when fcb is needed */ |
2061 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
eab6d18d | 2062 | vlan_tx_tag_present(skb) || |
f0ee7acf | 2063 | unlikely(do_tstamp)) && |
9c4886e5 | 2064 | (skb_headroom(skb) < fcb_length)) { |
54dc79fe SH |
2065 | struct sk_buff *skb_new; |
2066 | ||
9c4886e5 | 2067 | skb_new = skb_realloc_headroom(skb, fcb_length); |
54dc79fe SH |
2068 | if (!skb_new) { |
2069 | dev->stats.tx_errors++; | |
bd14ba84 | 2070 | kfree_skb(skb); |
54dc79fe SH |
2071 | return NETDEV_TX_OK; |
2072 | } | |
db83d136 MR |
2073 | |
2074 | /* Steal sock reference for processing TX time stamps */ | |
2075 | swap(skb_new->sk, skb->sk); | |
2076 | swap(skb_new->destructor, skb->destructor); | |
54dc79fe SH |
2077 | kfree_skb(skb); |
2078 | skb = skb_new; | |
2079 | } | |
2080 | ||
4669bc90 DH |
2081 | /* total number of fragments in the SKB */ |
2082 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2083 | ||
f0ee7acf MR |
2084 | /* calculate the required number of TxBDs for this skb */ |
2085 | if (unlikely(do_tstamp)) | |
2086 | nr_txbds = nr_frags + 2; | |
2087 | else | |
2088 | nr_txbds = nr_frags + 1; | |
2089 | ||
4669bc90 | 2090 | /* check if there is space to queue this packet */ |
f0ee7acf | 2091 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2092 | /* no space, stop the queue */ |
fba4ed03 | 2093 | netif_tx_stop_queue(txq); |
4669bc90 | 2094 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2095 | return NETDEV_TX_BUSY; |
2096 | } | |
1da177e4 LT |
2097 | |
2098 | /* Update transmit stats */ | |
1ac9ad13 ED |
2099 | tx_queue->stats.tx_bytes += skb->len; |
2100 | tx_queue->stats.tx_packets++; | |
1da177e4 | 2101 | |
a12f801d | 2102 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2103 | lstatus = txbdp->lstatus; |
2104 | ||
2105 | /* Time stamp insertion requires one additional TxBD */ | |
2106 | if (unlikely(do_tstamp)) | |
2107 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
2108 | tx_queue->tx_ring_size); | |
1da177e4 | 2109 | |
4669bc90 | 2110 | if (nr_frags == 0) { |
f0ee7acf MR |
2111 | if (unlikely(do_tstamp)) |
2112 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
2113 | TXBD_INTERRUPT); | |
2114 | else | |
2115 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2116 | } else { |
2117 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2118 | for (i = 0; i < nr_frags; i++) { | |
2119 | /* Point at the next BD, wrapping as needed */ | |
a12f801d | 2120 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2121 | |
2122 | length = skb_shinfo(skb)->frags[i].size; | |
2123 | ||
2124 | lstatus = txbdp->lstatus | length | | |
2125 | BD_LFLAG(TXBD_READY); | |
2126 | ||
2127 | /* Handle the last BD specially */ | |
2128 | if (i == nr_frags - 1) | |
2129 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2130 | |
2234a722 IC |
2131 | bufaddr = skb_frag_dma_map(&priv->ofdev->dev, |
2132 | &skb_shinfo(skb)->frags[i], | |
2133 | 0, | |
2134 | length, | |
2135 | DMA_TO_DEVICE); | |
4669bc90 DH |
2136 | |
2137 | /* set the TxBD length and buffer pointer */ | |
2138 | txbdp->bufPtr = bufaddr; | |
2139 | txbdp->lstatus = lstatus; | |
2140 | } | |
2141 | ||
2142 | lstatus = txbdp_start->lstatus; | |
2143 | } | |
1da177e4 | 2144 | |
9c4886e5 MR |
2145 | /* Add TxPAL between FCB and frame if required */ |
2146 | if (unlikely(do_tstamp)) { | |
2147 | skb_push(skb, GMAC_TXPAL_LEN); | |
2148 | memset(skb->data, 0, GMAC_TXPAL_LEN); | |
2149 | } | |
2150 | ||
0bbaf069 | 2151 | /* Set up checksumming */ |
12dea57b | 2152 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe | 2153 | fcb = gfar_add_fcb(skb); |
4363c2fd AD |
2154 | /* as specified by errata */ |
2155 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) | |
2156 | && ((unsigned long)fcb % 0x20) > 0x18)) { | |
2157 | __skb_pull(skb, GMAC_FCB_LEN); | |
2158 | skb_checksum_help(skb); | |
2159 | } else { | |
2160 | lstatus |= BD_LFLAG(TXBD_TOE); | |
9c4886e5 | 2161 | gfar_tx_checksum(skb, fcb, fcb_length); |
4363c2fd | 2162 | } |
0bbaf069 KG |
2163 | } |
2164 | ||
eab6d18d | 2165 | if (vlan_tx_tag_present(skb)) { |
54dc79fe SH |
2166 | if (unlikely(NULL == fcb)) { |
2167 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 2168 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 2169 | } |
54dc79fe SH |
2170 | |
2171 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
2172 | } |
2173 | ||
f0ee7acf MR |
2174 | /* Setup tx hardware time stamping if requested */ |
2175 | if (unlikely(do_tstamp)) { | |
2244d07b | 2176 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf MR |
2177 | if (fcb == NULL) |
2178 | fcb = gfar_add_fcb(skb); | |
2179 | fcb->ptp = 1; | |
2180 | lstatus |= BD_LFLAG(TXBD_TOE); | |
2181 | } | |
2182 | ||
4826857f | 2183 | txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
4669bc90 | 2184 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2185 | |
0977f817 | 2186 | /* If time stamping is requested one additional TxBD must be set up. The |
f0ee7acf MR |
2187 | * first TxBD points to the FCB and must have a data length of |
2188 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2189 | * the full frame length. | |
2190 | */ | |
2191 | if (unlikely(do_tstamp)) { | |
9c4886e5 | 2192 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length; |
f0ee7acf | 2193 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | |
9c4886e5 | 2194 | (skb_headlen(skb) - fcb_length); |
f0ee7acf MR |
2195 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; |
2196 | } else { | |
2197 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2198 | } | |
1da177e4 | 2199 | |
d8a0f1b0 PG |
2200 | netdev_tx_sent_queue(txq, skb->len); |
2201 | ||
0977f817 | 2202 | /* We can work in parallel with gfar_clean_tx_ring(), except |
a3bc1f11 AV |
2203 | * when modifying num_txbdfree. Note that we didn't grab the lock |
2204 | * when we were reading the num_txbdfree and checking for available | |
2205 | * space, that's because outside of this function it can only grow, | |
2206 | * and once we've got needed space, it cannot suddenly disappear. | |
2207 | * | |
2208 | * The lock also protects us from gfar_error(), which can modify | |
2209 | * regs->tstat and thus retrigger the transfers, which is why we | |
2210 | * also must grab the lock before setting ready bit for the first | |
2211 | * to be transmitted BD. | |
2212 | */ | |
2213 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2214 | ||
0977f817 | 2215 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
3b6330ce SW |
2216 | * semantics (it requires synchronization between cacheable and |
2217 | * uncacheable mappings, which eieio doesn't provide and which we | |
2218 | * don't need), thus requiring a more expensive sync instruction. At | |
2219 | * some point, the set of architecture-independent barrier functions | |
2220 | * should be expanded to include weaker barriers. | |
2221 | */ | |
3b6330ce | 2222 | eieio(); |
7f7f5316 | 2223 | |
4669bc90 DH |
2224 | txbdp_start->lstatus = lstatus; |
2225 | ||
0eddba52 AV |
2226 | eieio(); /* force lstatus write before tx_skbuff */ |
2227 | ||
2228 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2229 | ||
4669bc90 | 2230 | /* Update the current skb pointer to the next entry we will use |
0977f817 JC |
2231 | * (wrapping if necessary) |
2232 | */ | |
a12f801d SG |
2233 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
2234 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); | |
4669bc90 | 2235 | |
a12f801d | 2236 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2237 | |
2238 | /* reduce TxBD free count */ | |
f0ee7acf | 2239 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2240 | |
2241 | /* If the next BD still needs to be cleaned up, then the bds | |
0977f817 JC |
2242 | * are full. We need to tell the kernel to stop sending us stuff. |
2243 | */ | |
a12f801d | 2244 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2245 | netif_tx_stop_queue(txq); |
1da177e4 | 2246 | |
09f75cd7 | 2247 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2248 | } |
2249 | ||
1da177e4 | 2250 | /* Tell the DMA to go go go */ |
fba4ed03 | 2251 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2252 | |
2253 | /* Unlock priv */ | |
a12f801d | 2254 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2255 | |
54dc79fe | 2256 | return NETDEV_TX_OK; |
1da177e4 LT |
2257 | } |
2258 | ||
2259 | /* Stops the kernel queue, and halts the controller */ | |
2260 | static int gfar_close(struct net_device *dev) | |
2261 | { | |
2262 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2263 | |
46ceb60c | 2264 | disable_napi(priv); |
bea3348e | 2265 | |
ab939905 | 2266 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2267 | stop_gfar(dev); |
2268 | ||
bb40dcbb AF |
2269 | /* Disconnect from the PHY */ |
2270 | phy_disconnect(priv->phydev); | |
2271 | priv->phydev = NULL; | |
1da177e4 | 2272 | |
fba4ed03 | 2273 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2274 | |
2275 | return 0; | |
2276 | } | |
2277 | ||
1da177e4 | 2278 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2279 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2280 | { |
7f7f5316 | 2281 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2282 | |
2283 | return 0; | |
2284 | } | |
2285 | ||
f3dc1586 SP |
2286 | /* Check if rx parser should be activated */ |
2287 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2288 | { | |
2289 | struct gfar __iomem *regs; | |
2290 | u32 tempval; | |
2291 | ||
2292 | regs = priv->gfargrp[0].regs; | |
2293 | ||
2294 | tempval = gfar_read(®s->rctrl); | |
2295 | /* If parse is no longer required, then disable parser */ | |
2296 | if (tempval & RCTRL_REQ_PARSER) | |
2297 | tempval |= RCTRL_PRSDEP_INIT; | |
2298 | else | |
2299 | tempval &= ~RCTRL_PRSDEP_INIT; | |
2300 | gfar_write(®s->rctrl, tempval); | |
2301 | } | |
2302 | ||
0bbaf069 | 2303 | /* Enables and disables VLAN insertion/extraction */ |
c8f44aff | 2304 | void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) |
0bbaf069 KG |
2305 | { |
2306 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2307 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2308 | unsigned long flags; |
2309 | u32 tempval; | |
2310 | ||
46ceb60c | 2311 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2312 | local_irq_save(flags); |
2313 | lock_rx_qs(priv); | |
0bbaf069 | 2314 | |
87c288c6 | 2315 | if (features & NETIF_F_HW_VLAN_TX) { |
0bbaf069 | 2316 | /* Enable VLAN tag insertion */ |
f4983704 | 2317 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2318 | tempval |= TCTRL_VLINS; |
f4983704 | 2319 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2320 | } else { |
2321 | /* Disable VLAN tag insertion */ | |
f4983704 | 2322 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2323 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2324 | gfar_write(®s->tctrl, tempval); |
87c288c6 | 2325 | } |
0bbaf069 | 2326 | |
87c288c6 JP |
2327 | if (features & NETIF_F_HW_VLAN_RX) { |
2328 | /* Enable VLAN tag extraction */ | |
2329 | tempval = gfar_read(®s->rctrl); | |
2330 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); | |
2331 | gfar_write(®s->rctrl, tempval); | |
2332 | } else { | |
0bbaf069 | 2333 | /* Disable VLAN tag extraction */ |
f4983704 | 2334 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2335 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2336 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2337 | |
2338 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2339 | } |
2340 | ||
77ecaf2d DH |
2341 | gfar_change_mtu(dev, dev->mtu); |
2342 | ||
fba4ed03 SG |
2343 | unlock_rx_qs(priv); |
2344 | local_irq_restore(flags); | |
0bbaf069 KG |
2345 | } |
2346 | ||
1da177e4 LT |
2347 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2348 | { | |
2349 | int tempsize, tempval; | |
2350 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2351 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2352 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2353 | int frame_size = new_mtu + ETH_HLEN; |
2354 | ||
87c288c6 | 2355 | if (gfar_is_vlan_on(priv)) |
faa89577 | 2356 | frame_size += VLAN_HLEN; |
0bbaf069 | 2357 | |
1da177e4 | 2358 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
59deab26 | 2359 | netif_err(priv, drv, dev, "Invalid MTU setting\n"); |
1da177e4 LT |
2360 | return -EINVAL; |
2361 | } | |
2362 | ||
77ecaf2d DH |
2363 | if (gfar_uses_fcb(priv)) |
2364 | frame_size += GMAC_FCB_LEN; | |
2365 | ||
2366 | frame_size += priv->padding; | |
2367 | ||
1da177e4 LT |
2368 | tempsize = |
2369 | (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + | |
2370 | INCREMENTAL_BUFFER_SIZE; | |
2371 | ||
2372 | /* Only stop and start the controller if it isn't already | |
0977f817 JC |
2373 | * stopped, and we changed something |
2374 | */ | |
1da177e4 LT |
2375 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2376 | stop_gfar(dev); | |
2377 | ||
2378 | priv->rx_buffer_size = tempsize; | |
2379 | ||
2380 | dev->mtu = new_mtu; | |
2381 | ||
f4983704 SG |
2382 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2383 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2384 | |
2385 | /* If the mtu is larger than the max size for standard | |
2386 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
0977f817 JC |
2387 | * to allow huge frames, and to check the length |
2388 | */ | |
f4983704 | 2389 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2390 | |
7d350977 AV |
2391 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
2392 | gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1da177e4 LT |
2393 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2394 | else | |
2395 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2396 | ||
f4983704 | 2397 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2398 | |
2399 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2400 | startup_gfar(dev); | |
2401 | ||
2402 | return 0; | |
2403 | } | |
2404 | ||
ab939905 | 2405 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2406 | * transmitted after a set amount of time. |
2407 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2408 | * starting over will fix the problem. |
2409 | */ | |
2410 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2411 | { |
ab939905 SS |
2412 | struct gfar_private *priv = container_of(work, struct gfar_private, |
2413 | reset_task); | |
4826857f | 2414 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2415 | |
2416 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2417 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2418 | stop_gfar(dev); |
2419 | startup_gfar(dev); | |
fba4ed03 | 2420 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2421 | } |
2422 | ||
263ba320 | 2423 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2424 | } |
2425 | ||
ab939905 SS |
2426 | static void gfar_timeout(struct net_device *dev) |
2427 | { | |
2428 | struct gfar_private *priv = netdev_priv(dev); | |
2429 | ||
2430 | dev->stats.tx_errors++; | |
2431 | schedule_work(&priv->reset_task); | |
2432 | } | |
2433 | ||
acbc0f03 EL |
2434 | static void gfar_align_skb(struct sk_buff *skb) |
2435 | { | |
2436 | /* We need the data buffer to be aligned properly. We will reserve | |
2437 | * as many bytes as needed to align the data properly | |
2438 | */ | |
2439 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
2440 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); | |
2441 | } | |
2442 | ||
1da177e4 | 2443 | /* Interrupt Handler for Transmit complete */ |
a12f801d | 2444 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2445 | { |
a12f801d | 2446 | struct net_device *dev = tx_queue->dev; |
d8a0f1b0 | 2447 | struct netdev_queue *txq; |
d080cd63 | 2448 | struct gfar_private *priv = netdev_priv(dev); |
a12f801d | 2449 | struct gfar_priv_rx_q *rx_queue = NULL; |
f0ee7acf | 2450 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2451 | struct txbd8 *lbdp = NULL; |
a12f801d | 2452 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2453 | struct sk_buff *skb; |
2454 | int skb_dirtytx; | |
a12f801d | 2455 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2456 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2457 | int i; |
d080cd63 | 2458 | int howmany = 0; |
d8a0f1b0 PG |
2459 | int tqi = tx_queue->qindex; |
2460 | unsigned int bytes_sent = 0; | |
4669bc90 | 2461 | u32 lstatus; |
f0ee7acf | 2462 | size_t buflen; |
1da177e4 | 2463 | |
d8a0f1b0 PG |
2464 | rx_queue = priv->rx_queue[tqi]; |
2465 | txq = netdev_get_tx_queue(dev, tqi); | |
a12f801d SG |
2466 | bdp = tx_queue->dirty_tx; |
2467 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2468 | |
a12f801d | 2469 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2470 | unsigned long flags; |
2471 | ||
4669bc90 | 2472 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf | 2473 | |
0977f817 | 2474 | /* When time stamping, one additional TxBD must be freed. |
f0ee7acf MR |
2475 | * Also, we need to dma_unmap_single() the TxPAL. |
2476 | */ | |
2244d07b | 2477 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2478 | nr_txbds = frags + 2; |
2479 | else | |
2480 | nr_txbds = frags + 1; | |
2481 | ||
2482 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2483 | |
4669bc90 | 2484 | lstatus = lbdp->lstatus; |
1da177e4 | 2485 | |
4669bc90 DH |
2486 | /* Only clean completed frames */ |
2487 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
2488 | (lstatus & BD_LENGTH_MASK)) | |
2489 | break; | |
2490 | ||
2244d07b | 2491 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf | 2492 | next = next_txbd(bdp, base, tx_ring_size); |
9c4886e5 | 2493 | buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
f0ee7acf MR |
2494 | } else |
2495 | buflen = bdp->length; | |
2496 | ||
2497 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, | |
2498 | buflen, DMA_TO_DEVICE); | |
2499 | ||
2244d07b | 2500 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2501 | struct skb_shared_hwtstamps shhwtstamps; |
2502 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
2503 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
2504 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
9c4886e5 | 2505 | skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); |
f0ee7acf MR |
2506 | skb_tstamp_tx(skb, &shhwtstamps); |
2507 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2508 | bdp = next; | |
2509 | } | |
81183059 | 2510 | |
4669bc90 DH |
2511 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2512 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2513 | |
4669bc90 | 2514 | for (i = 0; i < frags; i++) { |
4826857f | 2515 | dma_unmap_page(&priv->ofdev->dev, |
4669bc90 DH |
2516 | bdp->bufPtr, |
2517 | bdp->length, | |
2518 | DMA_TO_DEVICE); | |
2519 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2520 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2521 | } | |
1da177e4 | 2522 | |
d8a0f1b0 PG |
2523 | bytes_sent += skb->len; |
2524 | ||
0977f817 | 2525 | /* If there's room in the queue (limit it to rx_buffer_size) |
0fd56bb5 AF |
2526 | * we add this skb back into the pool, if it's the right size |
2527 | */ | |
a12f801d | 2528 | if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size && |
0fd56bb5 | 2529 | skb_recycle_check(skb, priv->rx_buffer_size + |
acbc0f03 EL |
2530 | RXBUF_ALIGNMENT)) { |
2531 | gfar_align_skb(skb); | |
cd0ea241 | 2532 | skb_queue_head(&priv->rx_recycle, skb); |
acbc0f03 | 2533 | } else |
0fd56bb5 AF |
2534 | dev_kfree_skb_any(skb); |
2535 | ||
a12f801d | 2536 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2537 | |
4669bc90 DH |
2538 | skb_dirtytx = (skb_dirtytx + 1) & |
2539 | TX_RING_MOD_MASK(tx_ring_size); | |
2540 | ||
2541 | howmany++; | |
a3bc1f11 | 2542 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2543 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2544 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2545 | } |
1da177e4 | 2546 | |
4669bc90 | 2547 | /* If we freed a buffer, we can restart transmission, if necessary */ |
5407b14c | 2548 | if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) |
d8a0f1b0 | 2549 | netif_wake_subqueue(dev, tqi); |
1da177e4 | 2550 | |
4669bc90 | 2551 | /* Update dirty indicators */ |
a12f801d SG |
2552 | tx_queue->skb_dirtytx = skb_dirtytx; |
2553 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2554 | |
d8a0f1b0 PG |
2555 | netdev_tx_completed_queue(txq, howmany, bytes_sent); |
2556 | ||
d080cd63 DH |
2557 | return howmany; |
2558 | } | |
2559 | ||
f4983704 | 2560 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2561 | { |
a6d0b91a AV |
2562 | unsigned long flags; |
2563 | ||
fba4ed03 SG |
2564 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2565 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2566 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2567 | __napi_schedule(&gfargrp->napi); |
8707bdd4 | 2568 | } else { |
0977f817 | 2569 | /* Clear IEVENT, so interrupts aren't called again |
8707bdd4 JP |
2570 | * because of the packets that have already arrived. |
2571 | */ | |
f4983704 | 2572 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2573 | } |
fba4ed03 | 2574 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2575 | |
8c7396ae | 2576 | } |
1da177e4 | 2577 | |
8c7396ae | 2578 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2579 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2580 | { |
f4983704 | 2581 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2582 | return IRQ_HANDLED; |
2583 | } | |
2584 | ||
a12f801d | 2585 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
815b97c6 AF |
2586 | struct sk_buff *skb) |
2587 | { | |
a12f801d | 2588 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2589 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2590 | dma_addr_t buf; |
815b97c6 | 2591 | |
8a102fe0 AV |
2592 | buf = dma_map_single(&priv->ofdev->dev, skb->data, |
2593 | priv->rx_buffer_size, DMA_FROM_DEVICE); | |
a12f801d | 2594 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2595 | } |
2596 | ||
2281a0f3 | 2597 | static struct sk_buff *gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2598 | { |
2599 | struct gfar_private *priv = netdev_priv(dev); | |
2600 | struct sk_buff *skb = NULL; | |
1da177e4 | 2601 | |
acbc0f03 | 2602 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2603 | if (!skb) |
1da177e4 LT |
2604 | return NULL; |
2605 | ||
acbc0f03 | 2606 | gfar_align_skb(skb); |
7f7f5316 | 2607 | |
acbc0f03 EL |
2608 | return skb; |
2609 | } | |
2610 | ||
2281a0f3 | 2611 | struct sk_buff *gfar_new_skb(struct net_device *dev) |
acbc0f03 EL |
2612 | { |
2613 | struct gfar_private *priv = netdev_priv(dev); | |
2614 | struct sk_buff *skb = NULL; | |
2615 | ||
cd0ea241 | 2616 | skb = skb_dequeue(&priv->rx_recycle); |
acbc0f03 EL |
2617 | if (!skb) |
2618 | skb = gfar_alloc_skb(dev); | |
1da177e4 | 2619 | |
1da177e4 LT |
2620 | return skb; |
2621 | } | |
2622 | ||
298e1a9e | 2623 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2624 | { |
298e1a9e | 2625 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2626 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2627 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2628 | ||
0977f817 | 2629 | /* If the packet was truncated, none of the other errors matter */ |
1da177e4 LT |
2630 | if (status & RXBD_TRUNCATED) { |
2631 | stats->rx_length_errors++; | |
2632 | ||
2633 | estats->rx_trunc++; | |
2634 | ||
2635 | return; | |
2636 | } | |
2637 | /* Count the errors, if there were any */ | |
2638 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2639 | stats->rx_length_errors++; | |
2640 | ||
2641 | if (status & RXBD_LARGE) | |
2642 | estats->rx_large++; | |
2643 | else | |
2644 | estats->rx_short++; | |
2645 | } | |
2646 | if (status & RXBD_NONOCTET) { | |
2647 | stats->rx_frame_errors++; | |
2648 | estats->rx_nonoctet++; | |
2649 | } | |
2650 | if (status & RXBD_CRCERR) { | |
2651 | estats->rx_crcerr++; | |
2652 | stats->rx_crc_errors++; | |
2653 | } | |
2654 | if (status & RXBD_OVERRUN) { | |
2655 | estats->rx_overrun++; | |
2656 | stats->rx_crc_errors++; | |
2657 | } | |
2658 | } | |
2659 | ||
f4983704 | 2660 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2661 | { |
f4983704 | 2662 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2663 | return IRQ_HANDLED; |
2664 | } | |
2665 | ||
0bbaf069 KG |
2666 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2667 | { | |
2668 | /* If valid headers were found, and valid sums | |
2669 | * were verified, then we tell the kernel that no | |
0977f817 JC |
2670 | * checksumming is necessary. Otherwise, it is [FIXME] |
2671 | */ | |
7f7f5316 | 2672 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2673 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2674 | else | |
bc8acf2c | 2675 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2676 | } |
2677 | ||
2678 | ||
0977f817 | 2679 | /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ |
1da177e4 | 2680 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
cd754a57 | 2681 | int amount_pull, struct napi_struct *napi) |
1da177e4 LT |
2682 | { |
2683 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2684 | struct rxfcb *fcb = NULL; |
1da177e4 | 2685 | |
cd754a57 | 2686 | gro_result_t ret; |
1da177e4 | 2687 | |
2c2db48a DH |
2688 | /* fcb is at the beginning if exists */ |
2689 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2690 | |
0977f817 JC |
2691 | /* Remove the FCB from the skb |
2692 | * Remove the padded bytes, if there are any | |
2693 | */ | |
f74dac08 SG |
2694 | if (amount_pull) { |
2695 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2696 | skb_pull(skb, amount_pull); |
f74dac08 | 2697 | } |
0bbaf069 | 2698 | |
cc772ab7 MR |
2699 | /* Get receive timestamp from the skb */ |
2700 | if (priv->hwts_rx_en) { | |
2701 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2702 | u64 *ns = (u64 *) skb->data; | |
2703 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
2704 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2705 | } | |
2706 | ||
2707 | if (priv->padding) | |
2708 | skb_pull(skb, priv->padding); | |
2709 | ||
8b3afe95 | 2710 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2711 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2712 | |
2c2db48a DH |
2713 | /* Tell the skb what kind of packet this is */ |
2714 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2715 | |
0977f817 | 2716 | /* There's need to check for NETIF_F_HW_VLAN_RX here. |
32f7fd44 JP |
2717 | * Even if vlan rx accel is disabled, on some chips |
2718 | * RXFCB_VLN is pseudo randomly set. | |
2719 | */ | |
2720 | if (dev->features & NETIF_F_HW_VLAN_RX && | |
2721 | fcb->flags & RXFCB_VLN) | |
87c288c6 JP |
2722 | __vlan_hwaccel_put_tag(skb, fcb->vlctl); |
2723 | ||
2c2db48a | 2724 | /* Send the packet up the stack */ |
cd754a57 | 2725 | ret = napi_gro_receive(napi, skb); |
0bbaf069 | 2726 | |
cd754a57 | 2727 | if (GRO_DROP == ret) |
2c2db48a | 2728 | priv->extra_stats.kernel_dropped++; |
1da177e4 LT |
2729 | |
2730 | return 0; | |
2731 | } | |
2732 | ||
2733 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
2281a0f3 JC |
2734 | * until the budget/quota has been reached. Returns the number |
2735 | * of frames handled | |
1da177e4 | 2736 | */ |
a12f801d | 2737 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2738 | { |
a12f801d | 2739 | struct net_device *dev = rx_queue->dev; |
31de198b | 2740 | struct rxbd8 *bdp, *base; |
1da177e4 | 2741 | struct sk_buff *skb; |
2c2db48a DH |
2742 | int pkt_len; |
2743 | int amount_pull; | |
1da177e4 LT |
2744 | int howmany = 0; |
2745 | struct gfar_private *priv = netdev_priv(dev); | |
2746 | ||
2747 | /* Get the first full descriptor */ | |
a12f801d SG |
2748 | bdp = rx_queue->cur_rx; |
2749 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2750 | |
cc772ab7 | 2751 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0); |
2c2db48a | 2752 | |
1da177e4 | 2753 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2754 | struct sk_buff *newskb; |
3b6330ce | 2755 | rmb(); |
815b97c6 AF |
2756 | |
2757 | /* Add another skb for the future */ | |
2758 | newskb = gfar_new_skb(dev); | |
2759 | ||
a12f801d | 2760 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2761 | |
4826857f | 2762 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, |
81183059 AF |
2763 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
2764 | ||
63b88b90 AV |
2765 | if (unlikely(!(bdp->status & RXBD_ERR) && |
2766 | bdp->length > priv->rx_buffer_size)) | |
2767 | bdp->status = RXBD_LARGE; | |
2768 | ||
815b97c6 AF |
2769 | /* We drop the frame if we failed to allocate a new buffer */ |
2770 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
2771 | bdp->status & RXBD_ERR)) { | |
2772 | count_errors(bdp->status, dev); | |
2773 | ||
2774 | if (unlikely(!newskb)) | |
2775 | newskb = skb; | |
acbc0f03 | 2776 | else if (skb) |
cd0ea241 | 2777 | skb_queue_head(&priv->rx_recycle, skb); |
815b97c6 | 2778 | } else { |
1da177e4 | 2779 | /* Increment the number of packets */ |
a7f38041 | 2780 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2781 | howmany++; |
2782 | ||
2c2db48a DH |
2783 | if (likely(skb)) { |
2784 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2785 | /* Remove the FCS from the packet length */ | |
2786 | skb_put(skb, pkt_len); | |
a7f38041 | 2787 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2788 | skb_record_rx_queue(skb, rx_queue->qindex); |
cd754a57 WJB |
2789 | gfar_process_frame(dev, skb, amount_pull, |
2790 | &rx_queue->grp->napi); | |
2c2db48a DH |
2791 | |
2792 | } else { | |
59deab26 | 2793 | netif_warn(priv, rx_err, dev, "Missing skb!\n"); |
a7f38041 | 2794 | rx_queue->stats.rx_dropped++; |
2c2db48a DH |
2795 | priv->extra_stats.rx_skbmissing++; |
2796 | } | |
1da177e4 | 2797 | |
1da177e4 LT |
2798 | } |
2799 | ||
a12f801d | 2800 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2801 | |
815b97c6 | 2802 | /* Setup the new bdp */ |
a12f801d | 2803 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2804 | |
2805 | /* Update to the next pointer */ | |
a12f801d | 2806 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2807 | |
2808 | /* update to point at the next skb */ | |
a12f801d SG |
2809 | rx_queue->skb_currx = |
2810 | (rx_queue->skb_currx + 1) & | |
2811 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2812 | } |
2813 | ||
2814 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2815 | rx_queue->cur_rx = bdp; |
1da177e4 | 2816 | |
1da177e4 LT |
2817 | return howmany; |
2818 | } | |
2819 | ||
bea3348e | 2820 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2821 | { |
fba4ed03 SG |
2822 | struct gfar_priv_grp *gfargrp = container_of(napi, |
2823 | struct gfar_priv_grp, napi); | |
2824 | struct gfar_private *priv = gfargrp->priv; | |
46ceb60c | 2825 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2826 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 SG |
2827 | struct gfar_priv_rx_q *rx_queue = NULL; |
2828 | int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0; | |
18294ad1 AV |
2829 | int tx_cleaned = 0, i, left_over_budget = budget; |
2830 | unsigned long serviced_queues = 0; | |
fba4ed03 | 2831 | int num_queues = 0; |
d080cd63 | 2832 | |
fba4ed03 SG |
2833 | num_queues = gfargrp->num_rx_queues; |
2834 | budget_per_queue = budget/num_queues; | |
2835 | ||
8c7396ae | 2836 | /* Clear IEVENT, so interrupts aren't called again |
0977f817 JC |
2837 | * because of the packets that have already arrived |
2838 | */ | |
f4983704 | 2839 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2840 | |
fba4ed03 | 2841 | while (num_queues && left_over_budget) { |
1da177e4 | 2842 | |
fba4ed03 SG |
2843 | budget_per_queue = left_over_budget/num_queues; |
2844 | left_over_budget = 0; | |
2845 | ||
984b3f57 | 2846 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
fba4ed03 SG |
2847 | if (test_bit(i, &serviced_queues)) |
2848 | continue; | |
2849 | rx_queue = priv->rx_queue[i]; | |
2850 | tx_queue = priv->tx_queue[rx_queue->qindex]; | |
2851 | ||
a3bc1f11 | 2852 | tx_cleaned += gfar_clean_tx_ring(tx_queue); |
fba4ed03 SG |
2853 | rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue, |
2854 | budget_per_queue); | |
2855 | rx_cleaned += rx_cleaned_per_queue; | |
2856 | if(rx_cleaned_per_queue < budget_per_queue) { | |
2857 | left_over_budget = left_over_budget + | |
2858 | (budget_per_queue - rx_cleaned_per_queue); | |
2859 | set_bit(i, &serviced_queues); | |
2860 | num_queues--; | |
2861 | } | |
2862 | } | |
2863 | } | |
1da177e4 | 2864 | |
42199884 AF |
2865 | if (tx_cleaned) |
2866 | return budget; | |
2867 | ||
2868 | if (rx_cleaned < budget) { | |
288379f0 | 2869 | napi_complete(napi); |
1da177e4 LT |
2870 | |
2871 | /* Clear the halt bit in RSTAT */ | |
fba4ed03 | 2872 | gfar_write(®s->rstat, gfargrp->rstat); |
1da177e4 | 2873 | |
f4983704 | 2874 | gfar_write(®s->imask, IMASK_DEFAULT); |
1da177e4 | 2875 | |
0977f817 JC |
2876 | /* If we are coalescing interrupts, update the timer |
2877 | * Otherwise, clear it | |
2878 | */ | |
46ceb60c SG |
2879 | gfar_configure_coalescing(priv, |
2880 | gfargrp->rx_bit_map, gfargrp->tx_bit_map); | |
1da177e4 LT |
2881 | } |
2882 | ||
42199884 | 2883 | return rx_cleaned; |
1da177e4 | 2884 | } |
1da177e4 | 2885 | |
f2d71c2d | 2886 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0977f817 | 2887 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
f2d71c2d VW |
2888 | * without having to re-enable interrupts. It's not called while |
2889 | * the interrupt routine is executing. | |
2890 | */ | |
2891 | static void gfar_netpoll(struct net_device *dev) | |
2892 | { | |
2893 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2894 | int i = 0; |
f2d71c2d VW |
2895 | |
2896 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2897 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
2898 | for (i = 0; i < priv->num_grps; i++) { |
2899 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2900 | disable_irq(priv->gfargrp[i].interruptReceive); | |
2901 | disable_irq(priv->gfargrp[i].interruptError); | |
2902 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
2903 | &priv->gfargrp[i]); | |
2904 | enable_irq(priv->gfargrp[i].interruptError); | |
2905 | enable_irq(priv->gfargrp[i].interruptReceive); | |
2906 | enable_irq(priv->gfargrp[i].interruptTransmit); | |
2907 | } | |
f2d71c2d | 2908 | } else { |
46ceb60c SG |
2909 | for (i = 0; i < priv->num_grps; i++) { |
2910 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2911 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
2912 | &priv->gfargrp[i]); | |
2913 | enable_irq(priv->gfargrp[i].interruptTransmit); | |
43de004b | 2914 | } |
f2d71c2d VW |
2915 | } |
2916 | } | |
2917 | #endif | |
2918 | ||
1da177e4 | 2919 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 2920 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 2921 | { |
f4983704 | 2922 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
2923 | |
2924 | /* Save ievent for future reference */ | |
f4983704 | 2925 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 2926 | |
1da177e4 | 2927 | /* Check for reception */ |
538cc7ee | 2928 | if (events & IEVENT_RX_MASK) |
f4983704 | 2929 | gfar_receive(irq, grp_id); |
1da177e4 LT |
2930 | |
2931 | /* Check for transmit completion */ | |
538cc7ee | 2932 | if (events & IEVENT_TX_MASK) |
f4983704 | 2933 | gfar_transmit(irq, grp_id); |
1da177e4 | 2934 | |
538cc7ee SS |
2935 | /* Check for errors */ |
2936 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 2937 | gfar_error(irq, grp_id); |
1da177e4 LT |
2938 | |
2939 | return IRQ_HANDLED; | |
2940 | } | |
2941 | ||
1da177e4 LT |
2942 | /* Called every time the controller might need to be made |
2943 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2944 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2945 | * function converts those variables into the appropriate |
2946 | * register values, and can bring down the device if needed. | |
2947 | */ | |
2948 | static void adjust_link(struct net_device *dev) | |
2949 | { | |
2950 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2951 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
2952 | unsigned long flags; |
2953 | struct phy_device *phydev = priv->phydev; | |
2954 | int new_state = 0; | |
2955 | ||
fba4ed03 SG |
2956 | local_irq_save(flags); |
2957 | lock_tx_qs(priv); | |
2958 | ||
bb40dcbb AF |
2959 | if (phydev->link) { |
2960 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2961 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2962 | |
1da177e4 | 2963 | /* Now we make sure that we can be in full duplex mode. |
0977f817 JC |
2964 | * If not, we operate in half-duplex mode. |
2965 | */ | |
bb40dcbb AF |
2966 | if (phydev->duplex != priv->oldduplex) { |
2967 | new_state = 1; | |
2968 | if (!(phydev->duplex)) | |
1da177e4 | 2969 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2970 | else |
1da177e4 | 2971 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2972 | |
bb40dcbb | 2973 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2974 | } |
2975 | ||
bb40dcbb AF |
2976 | if (phydev->speed != priv->oldspeed) { |
2977 | new_state = 1; | |
2978 | switch (phydev->speed) { | |
1da177e4 | 2979 | case 1000: |
1da177e4 LT |
2980 | tempval = |
2981 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2982 | |
2983 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2984 | break; |
2985 | case 100: | |
2986 | case 10: | |
1da177e4 LT |
2987 | tempval = |
2988 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2989 | |
2990 | /* Reduced mode distinguishes | |
0977f817 JC |
2991 | * between 10 and 100 |
2992 | */ | |
7f7f5316 AF |
2993 | if (phydev->speed == SPEED_100) |
2994 | ecntrl |= ECNTRL_R100; | |
2995 | else | |
2996 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2997 | break; |
2998 | default: | |
59deab26 JP |
2999 | netif_warn(priv, link, dev, |
3000 | "Ack! Speed (%d) is not 10/100/1000!\n", | |
3001 | phydev->speed); | |
1da177e4 LT |
3002 | break; |
3003 | } | |
3004 | ||
bb40dcbb | 3005 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3006 | } |
3007 | ||
bb40dcbb | 3008 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3009 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3010 | |
1da177e4 | 3011 | if (!priv->oldlink) { |
bb40dcbb | 3012 | new_state = 1; |
1da177e4 | 3013 | priv->oldlink = 1; |
1da177e4 | 3014 | } |
bb40dcbb AF |
3015 | } else if (priv->oldlink) { |
3016 | new_state = 1; | |
3017 | priv->oldlink = 0; | |
3018 | priv->oldspeed = 0; | |
3019 | priv->oldduplex = -1; | |
1da177e4 | 3020 | } |
1da177e4 | 3021 | |
bb40dcbb AF |
3022 | if (new_state && netif_msg_link(priv)) |
3023 | phy_print_status(phydev); | |
fba4ed03 SG |
3024 | unlock_tx_qs(priv); |
3025 | local_irq_restore(flags); | |
bb40dcbb | 3026 | } |
1da177e4 LT |
3027 | |
3028 | /* Update the hash table based on the current list of multicast | |
3029 | * addresses we subscribe to. Also, change the promiscuity of | |
3030 | * the device based on the flags (this function is called | |
0977f817 JC |
3031 | * whenever dev->flags is changed |
3032 | */ | |
1da177e4 LT |
3033 | static void gfar_set_multi(struct net_device *dev) |
3034 | { | |
22bedad3 | 3035 | struct netdev_hw_addr *ha; |
1da177e4 | 3036 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3037 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3038 | u32 tempval; |
3039 | ||
a12f801d | 3040 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3041 | /* Set RCTRL to PROM */ |
3042 | tempval = gfar_read(®s->rctrl); | |
3043 | tempval |= RCTRL_PROM; | |
3044 | gfar_write(®s->rctrl, tempval); | |
3045 | } else { | |
3046 | /* Set RCTRL to not PROM */ | |
3047 | tempval = gfar_read(®s->rctrl); | |
3048 | tempval &= ~(RCTRL_PROM); | |
3049 | gfar_write(®s->rctrl, tempval); | |
3050 | } | |
6aa20a22 | 3051 | |
a12f801d | 3052 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3053 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3054 | gfar_write(®s->igaddr0, 0xffffffff); |
3055 | gfar_write(®s->igaddr1, 0xffffffff); | |
3056 | gfar_write(®s->igaddr2, 0xffffffff); | |
3057 | gfar_write(®s->igaddr3, 0xffffffff); | |
3058 | gfar_write(®s->igaddr4, 0xffffffff); | |
3059 | gfar_write(®s->igaddr5, 0xffffffff); | |
3060 | gfar_write(®s->igaddr6, 0xffffffff); | |
3061 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3062 | gfar_write(®s->gaddr0, 0xffffffff); |
3063 | gfar_write(®s->gaddr1, 0xffffffff); | |
3064 | gfar_write(®s->gaddr2, 0xffffffff); | |
3065 | gfar_write(®s->gaddr3, 0xffffffff); | |
3066 | gfar_write(®s->gaddr4, 0xffffffff); | |
3067 | gfar_write(®s->gaddr5, 0xffffffff); | |
3068 | gfar_write(®s->gaddr6, 0xffffffff); | |
3069 | gfar_write(®s->gaddr7, 0xffffffff); | |
3070 | } else { | |
7f7f5316 AF |
3071 | int em_num; |
3072 | int idx; | |
3073 | ||
1da177e4 | 3074 | /* zero out the hash */ |
0bbaf069 KG |
3075 | gfar_write(®s->igaddr0, 0x0); |
3076 | gfar_write(®s->igaddr1, 0x0); | |
3077 | gfar_write(®s->igaddr2, 0x0); | |
3078 | gfar_write(®s->igaddr3, 0x0); | |
3079 | gfar_write(®s->igaddr4, 0x0); | |
3080 | gfar_write(®s->igaddr5, 0x0); | |
3081 | gfar_write(®s->igaddr6, 0x0); | |
3082 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3083 | gfar_write(®s->gaddr0, 0x0); |
3084 | gfar_write(®s->gaddr1, 0x0); | |
3085 | gfar_write(®s->gaddr2, 0x0); | |
3086 | gfar_write(®s->gaddr3, 0x0); | |
3087 | gfar_write(®s->gaddr4, 0x0); | |
3088 | gfar_write(®s->gaddr5, 0x0); | |
3089 | gfar_write(®s->gaddr6, 0x0); | |
3090 | gfar_write(®s->gaddr7, 0x0); | |
3091 | ||
7f7f5316 AF |
3092 | /* If we have extended hash tables, we need to |
3093 | * clear the exact match registers to prepare for | |
0977f817 JC |
3094 | * setting them |
3095 | */ | |
7f7f5316 AF |
3096 | if (priv->extended_hash) { |
3097 | em_num = GFAR_EM_NUM + 1; | |
3098 | gfar_clear_exact_match(dev); | |
3099 | idx = 1; | |
3100 | } else { | |
3101 | idx = 0; | |
3102 | em_num = 0; | |
3103 | } | |
3104 | ||
4cd24eaf | 3105 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3106 | return; |
3107 | ||
3108 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3109 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3110 | if (idx < em_num) { |
22bedad3 | 3111 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3112 | idx++; |
3113 | } else | |
22bedad3 | 3114 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3115 | } |
3116 | } | |
1da177e4 LT |
3117 | } |
3118 | ||
7f7f5316 AF |
3119 | |
3120 | /* Clears each of the exact match registers to zero, so they | |
0977f817 JC |
3121 | * don't interfere with normal reception |
3122 | */ | |
7f7f5316 AF |
3123 | static void gfar_clear_exact_match(struct net_device *dev) |
3124 | { | |
3125 | int idx; | |
6a3c910c | 3126 | static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 AF |
3127 | |
3128 | for(idx = 1;idx < GFAR_EM_NUM + 1;idx++) | |
b6bc7650 | 3129 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3130 | } |
3131 | ||
1da177e4 LT |
3132 | /* Set the appropriate hash bit for the given addr */ |
3133 | /* The algorithm works like so: | |
3134 | * 1) Take the Destination Address (ie the multicast address), and | |
3135 | * do a CRC on it (little endian), and reverse the bits of the | |
3136 | * result. | |
3137 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3138 | * table. The table is controlled through 8 32-bit registers: | |
3139 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3140 | * gaddr7. This means that the 3 most significant bits in the | |
3141 | * hash index which gaddr register to use, and the 5 other bits | |
3142 | * indicate which bit (assuming an IBM numbering scheme, which | |
3143 | * for PowerPC (tm) is usually the case) in the register holds | |
0977f817 JC |
3144 | * the entry. |
3145 | */ | |
1da177e4 LT |
3146 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) |
3147 | { | |
3148 | u32 tempval; | |
3149 | struct gfar_private *priv = netdev_priv(dev); | |
6a3c910c | 3150 | u32 result = ether_crc(ETH_ALEN, addr); |
0bbaf069 KG |
3151 | int width = priv->hash_width; |
3152 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3153 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3154 | u32 value = (1 << (31-whichbit)); |
3155 | ||
0bbaf069 | 3156 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3157 | tempval |= value; |
0bbaf069 | 3158 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3159 | } |
3160 | ||
7f7f5316 AF |
3161 | |
3162 | /* There are multiple MAC Address register pairs on some controllers | |
3163 | * This function sets the numth pair to a given address | |
3164 | */ | |
b6bc7650 JP |
3165 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3166 | const u8 *addr) | |
7f7f5316 AF |
3167 | { |
3168 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3169 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 | 3170 | int idx; |
6a3c910c | 3171 | char tmpbuf[ETH_ALEN]; |
7f7f5316 | 3172 | u32 tempval; |
f4983704 | 3173 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3174 | |
3175 | macptr += num*2; | |
3176 | ||
0977f817 JC |
3177 | /* Now copy it into the mac registers backwards, cuz |
3178 | * little endian is silly | |
3179 | */ | |
6a3c910c JP |
3180 | for (idx = 0; idx < ETH_ALEN; idx++) |
3181 | tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; | |
7f7f5316 AF |
3182 | |
3183 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3184 | ||
3185 | tempval = *((u32 *) (tmpbuf + 4)); | |
3186 | ||
3187 | gfar_write(macptr+1, tempval); | |
3188 | } | |
3189 | ||
1da177e4 | 3190 | /* GFAR error interrupt handler */ |
f4983704 | 3191 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3192 | { |
f4983704 SG |
3193 | struct gfar_priv_grp *gfargrp = grp_id; |
3194 | struct gfar __iomem *regs = gfargrp->regs; | |
3195 | struct gfar_private *priv= gfargrp->priv; | |
3196 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3197 | |
3198 | /* Save ievent for future reference */ | |
f4983704 | 3199 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3200 | |
3201 | /* Clear IEVENT */ | |
f4983704 | 3202 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3203 | |
3204 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3205 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3206 | (events & IEVENT_MAG)) |
3207 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3208 | |
3209 | /* Hmm... */ | |
0bbaf069 | 3210 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
59deab26 JP |
3211 | netdev_dbg(dev, "error interrupt (ievent=0x%08x imask=0x%08x)\n", |
3212 | events, gfar_read(®s->imask)); | |
1da177e4 LT |
3213 | |
3214 | /* Update the error counters */ | |
3215 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3216 | dev->stats.tx_errors++; |
1da177e4 LT |
3217 | |
3218 | if (events & IEVENT_LC) | |
09f75cd7 | 3219 | dev->stats.tx_window_errors++; |
1da177e4 | 3220 | if (events & IEVENT_CRL) |
09f75cd7 | 3221 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3222 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3223 | unsigned long flags; |
3224 | ||
59deab26 JP |
3225 | netif_dbg(priv, tx_err, dev, |
3226 | "TX FIFO underrun, packet dropped\n"); | |
09f75cd7 | 3227 | dev->stats.tx_dropped++; |
1da177e4 LT |
3228 | priv->extra_stats.tx_underrun++; |
3229 | ||
836cf7fa AV |
3230 | local_irq_save(flags); |
3231 | lock_tx_qs(priv); | |
3232 | ||
1da177e4 | 3233 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3234 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3235 | |
3236 | unlock_tx_qs(priv); | |
3237 | local_irq_restore(flags); | |
1da177e4 | 3238 | } |
59deab26 | 3239 | netif_dbg(priv, tx_err, dev, "Transmit Error\n"); |
1da177e4 LT |
3240 | } |
3241 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3242 | dev->stats.rx_errors++; |
1da177e4 LT |
3243 | priv->extra_stats.rx_bsy++; |
3244 | ||
f4983704 | 3245 | gfar_receive(irq, grp_id); |
1da177e4 | 3246 | |
59deab26 JP |
3247 | netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", |
3248 | gfar_read(®s->rstat)); | |
1da177e4 LT |
3249 | } |
3250 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3251 | dev->stats.rx_errors++; |
1da177e4 LT |
3252 | priv->extra_stats.rx_babr++; |
3253 | ||
59deab26 | 3254 | netif_dbg(priv, rx_err, dev, "babbling RX error\n"); |
1da177e4 LT |
3255 | } |
3256 | if (events & IEVENT_EBERR) { | |
3257 | priv->extra_stats.eberr++; | |
59deab26 | 3258 | netif_dbg(priv, rx_err, dev, "bus error\n"); |
1da177e4 | 3259 | } |
59deab26 JP |
3260 | if (events & IEVENT_RXC) |
3261 | netif_dbg(priv, rx_status, dev, "control frame\n"); | |
1da177e4 LT |
3262 | |
3263 | if (events & IEVENT_BABT) { | |
3264 | priv->extra_stats.tx_babt++; | |
59deab26 | 3265 | netif_dbg(priv, tx_err, dev, "babbling TX error\n"); |
1da177e4 LT |
3266 | } |
3267 | return IRQ_HANDLED; | |
3268 | } | |
3269 | ||
b31a1d8b AF |
3270 | static struct of_device_id gfar_match[] = |
3271 | { | |
3272 | { | |
3273 | .type = "network", | |
3274 | .compatible = "gianfar", | |
3275 | }, | |
46ceb60c SG |
3276 | { |
3277 | .compatible = "fsl,etsec2", | |
3278 | }, | |
b31a1d8b AF |
3279 | {}, |
3280 | }; | |
e72701ac | 3281 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3282 | |
1da177e4 | 3283 | /* Structure for a device driver */ |
74888760 | 3284 | static struct platform_driver gfar_driver = { |
4018294b GL |
3285 | .driver = { |
3286 | .name = "fsl-gianfar", | |
3287 | .owner = THIS_MODULE, | |
3288 | .pm = GFAR_PM_OPS, | |
3289 | .of_match_table = gfar_match, | |
3290 | }, | |
1da177e4 LT |
3291 | .probe = gfar_probe, |
3292 | .remove = gfar_remove, | |
3293 | }; | |
3294 | ||
db62f684 | 3295 | module_platform_driver(gfar_driver); |