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Commit | Line | Data |
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0977f817 | 1 | /* drivers/net/ethernet/freescale/gianfar.c |
1da177e4 LT |
2 | * |
3 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
4 | * This driver is designed for the non-CPM ethernet controllers |
5 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
6 | * Based on 8260_io/fcc_enet.c |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
a12f801d | 10 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 11 | * |
6c43e046 | 12 | * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. |
a12f801d | 13 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
59deab26 JP |
64 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
65 | #define DEBUG | |
66 | ||
1da177e4 | 67 | #include <linux/kernel.h> |
1da177e4 LT |
68 | #include <linux/string.h> |
69 | #include <linux/errno.h> | |
bb40dcbb | 70 | #include <linux/unistd.h> |
1da177e4 LT |
71 | #include <linux/slab.h> |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/init.h> | |
74 | #include <linux/delay.h> | |
75 | #include <linux/netdevice.h> | |
76 | #include <linux/etherdevice.h> | |
77 | #include <linux/skbuff.h> | |
0bbaf069 | 78 | #include <linux/if_vlan.h> |
1da177e4 LT |
79 | #include <linux/spinlock.h> |
80 | #include <linux/mm.h> | |
fe192a49 | 81 | #include <linux/of_mdio.h> |
b31a1d8b | 82 | #include <linux/of_platform.h> |
0bbaf069 KG |
83 | #include <linux/ip.h> |
84 | #include <linux/tcp.h> | |
85 | #include <linux/udp.h> | |
9c07b884 | 86 | #include <linux/in.h> |
cc772ab7 | 87 | #include <linux/net_tstamp.h> |
1da177e4 LT |
88 | |
89 | #include <asm/io.h> | |
7d350977 | 90 | #include <asm/reg.h> |
1da177e4 LT |
91 | #include <asm/irq.h> |
92 | #include <asm/uaccess.h> | |
93 | #include <linux/module.h> | |
1da177e4 LT |
94 | #include <linux/dma-mapping.h> |
95 | #include <linux/crc32.h> | |
bb40dcbb AF |
96 | #include <linux/mii.h> |
97 | #include <linux/phy.h> | |
b31a1d8b AF |
98 | #include <linux/phy_fixed.h> |
99 | #include <linux/of.h> | |
4b6ba8aa | 100 | #include <linux/of_net.h> |
1da177e4 LT |
101 | |
102 | #include "gianfar.h" | |
1da177e4 LT |
103 | |
104 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 | 105 | |
7f7f5316 | 106 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 107 | |
1da177e4 LT |
108 | static int gfar_enet_open(struct net_device *dev); |
109 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 110 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
111 | static void gfar_timeout(struct net_device *dev); |
112 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 113 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 114 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 115 | struct sk_buff *skb); |
1da177e4 LT |
116 | static int gfar_set_mac_address(struct net_device *dev); |
117 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
118 | static irqreturn_t gfar_error(int irq, void *dev_id); |
119 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
120 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
121 | static void adjust_link(struct net_device *dev); |
122 | static void init_registers(struct net_device *dev); | |
123 | static int init_phy(struct net_device *dev); | |
74888760 | 124 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 125 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 126 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
127 | static void gfar_set_multi(struct net_device *dev); |
128 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 129 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 130 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
131 | #ifdef CONFIG_NET_POLL_CONTROLLER |
132 | static void gfar_netpoll(struct net_device *dev); | |
133 | #endif | |
a12f801d SG |
134 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
135 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); | |
61db26c6 CM |
136 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
137 | int amount_pull, struct napi_struct *napi); | |
7f7f5316 | 138 | void gfar_halt(struct net_device *dev); |
d87eb127 | 139 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
140 | void gfar_start(struct net_device *dev); |
141 | static void gfar_clear_exact_match(struct net_device *dev); | |
b6bc7650 JP |
142 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
143 | const u8 *addr); | |
26ccfc37 | 144 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 145 | |
1da177e4 LT |
146 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
147 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | ||
a12f801d | 150 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
151 | dma_addr_t buf) |
152 | { | |
8a102fe0 AV |
153 | u32 lstatus; |
154 | ||
155 | bdp->bufPtr = buf; | |
156 | ||
157 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 158 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
159 | lstatus |= BD_LFLAG(RXBD_WRAP); |
160 | ||
161 | eieio(); | |
162 | ||
163 | bdp->lstatus = lstatus; | |
164 | } | |
165 | ||
8728327e | 166 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 167 | { |
8728327e | 168 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
169 | struct gfar_priv_tx_q *tx_queue = NULL; |
170 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
171 | struct txbd8 *txbdp; |
172 | struct rxbd8 *rxbdp; | |
fba4ed03 | 173 | int i, j; |
a12f801d | 174 | |
fba4ed03 SG |
175 | for (i = 0; i < priv->num_tx_queues; i++) { |
176 | tx_queue = priv->tx_queue[i]; | |
177 | /* Initialize some variables in our dev structure */ | |
178 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
179 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
180 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
181 | tx_queue->skb_curtx = 0; | |
182 | tx_queue->skb_dirtytx = 0; | |
183 | ||
184 | /* Initialize Transmit Descriptor Ring */ | |
185 | txbdp = tx_queue->tx_bd_base; | |
186 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
187 | txbdp->lstatus = 0; | |
188 | txbdp->bufPtr = 0; | |
189 | txbdp++; | |
190 | } | |
8728327e | 191 | |
fba4ed03 SG |
192 | /* Set the last descriptor in the ring to indicate wrap */ |
193 | txbdp--; | |
194 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
195 | } |
196 | ||
fba4ed03 SG |
197 | for (i = 0; i < priv->num_rx_queues; i++) { |
198 | rx_queue = priv->rx_queue[i]; | |
199 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
200 | rx_queue->skb_currx = 0; | |
201 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 202 | |
fba4ed03 SG |
203 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
204 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 205 | |
fba4ed03 SG |
206 | if (skb) { |
207 | gfar_init_rxbdp(rx_queue, rxbdp, | |
208 | rxbdp->bufPtr); | |
209 | } else { | |
210 | skb = gfar_new_skb(ndev); | |
211 | if (!skb) { | |
59deab26 | 212 | netdev_err(ndev, "Can't allocate RX buffers\n"); |
1eb8f7a7 | 213 | return -ENOMEM; |
fba4ed03 SG |
214 | } |
215 | rx_queue->rx_skbuff[j] = skb; | |
216 | ||
217 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 218 | } |
8728327e | 219 | |
fba4ed03 | 220 | rxbdp++; |
8728327e AV |
221 | } |
222 | ||
8728327e AV |
223 | } |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
229 | { | |
826aa4a0 | 230 | void *vaddr; |
fba4ed03 SG |
231 | dma_addr_t addr; |
232 | int i, j, k; | |
826aa4a0 | 233 | struct gfar_private *priv = netdev_priv(ndev); |
369ec162 | 234 | struct device *dev = priv->dev; |
a12f801d SG |
235 | struct gfar_priv_tx_q *tx_queue = NULL; |
236 | struct gfar_priv_rx_q *rx_queue = NULL; | |
237 | ||
fba4ed03 SG |
238 | priv->total_tx_ring_size = 0; |
239 | for (i = 0; i < priv->num_tx_queues; i++) | |
240 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
241 | ||
242 | priv->total_rx_ring_size = 0; | |
243 | for (i = 0; i < priv->num_rx_queues; i++) | |
244 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
245 | |
246 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 247 | vaddr = dma_alloc_coherent(dev, |
fba4ed03 SG |
248 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
249 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
250 | &addr, GFP_KERNEL); | |
826aa4a0 | 251 | if (!vaddr) { |
59deab26 JP |
252 | netif_err(priv, ifup, ndev, |
253 | "Could not allocate buffer descriptors!\n"); | |
826aa4a0 AV |
254 | return -ENOMEM; |
255 | } | |
256 | ||
fba4ed03 SG |
257 | for (i = 0; i < priv->num_tx_queues; i++) { |
258 | tx_queue = priv->tx_queue[i]; | |
43d620c8 | 259 | tx_queue->tx_bd_base = vaddr; |
fba4ed03 SG |
260 | tx_queue->tx_bd_dma_base = addr; |
261 | tx_queue->dev = ndev; | |
262 | /* enet DMA only understands physical addresses */ | |
bc4598bc JC |
263 | addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; |
264 | vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; | |
fba4ed03 | 265 | } |
826aa4a0 | 266 | |
826aa4a0 | 267 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
268 | for (i = 0; i < priv->num_rx_queues; i++) { |
269 | rx_queue = priv->rx_queue[i]; | |
43d620c8 | 270 | rx_queue->rx_bd_base = vaddr; |
fba4ed03 SG |
271 | rx_queue->rx_bd_dma_base = addr; |
272 | rx_queue->dev = ndev; | |
bc4598bc JC |
273 | addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; |
274 | vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; | |
fba4ed03 | 275 | } |
826aa4a0 AV |
276 | |
277 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
278 | for (i = 0; i < priv->num_tx_queues; i++) { |
279 | tx_queue = priv->tx_queue[i]; | |
14f8dc49 JP |
280 | tx_queue->tx_skbuff = |
281 | kmalloc_array(tx_queue->tx_ring_size, | |
282 | sizeof(*tx_queue->tx_skbuff), | |
283 | GFP_KERNEL); | |
284 | if (!tx_queue->tx_skbuff) | |
fba4ed03 | 285 | goto cleanup; |
826aa4a0 | 286 | |
fba4ed03 SG |
287 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
288 | tx_queue->tx_skbuff[k] = NULL; | |
289 | } | |
826aa4a0 | 290 | |
fba4ed03 SG |
291 | for (i = 0; i < priv->num_rx_queues; i++) { |
292 | rx_queue = priv->rx_queue[i]; | |
14f8dc49 JP |
293 | rx_queue->rx_skbuff = |
294 | kmalloc_array(rx_queue->rx_ring_size, | |
295 | sizeof(*rx_queue->rx_skbuff), | |
296 | GFP_KERNEL); | |
297 | if (!rx_queue->rx_skbuff) | |
fba4ed03 | 298 | goto cleanup; |
fba4ed03 SG |
299 | |
300 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
301 | rx_queue->rx_skbuff[j] = NULL; | |
302 | } | |
826aa4a0 | 303 | |
8728327e AV |
304 | if (gfar_init_bds(ndev)) |
305 | goto cleanup; | |
826aa4a0 AV |
306 | |
307 | return 0; | |
308 | ||
309 | cleanup: | |
310 | free_skb_resources(priv); | |
311 | return -ENOMEM; | |
312 | } | |
313 | ||
fba4ed03 SG |
314 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
315 | { | |
46ceb60c | 316 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 317 | u32 __iomem *baddr; |
fba4ed03 SG |
318 | int i; |
319 | ||
320 | baddr = ®s->tbase0; | |
bc4598bc | 321 | for (i = 0; i < priv->num_tx_queues; i++) { |
fba4ed03 | 322 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); |
bc4598bc | 323 | baddr += 2; |
fba4ed03 SG |
324 | } |
325 | ||
326 | baddr = ®s->rbase0; | |
bc4598bc | 327 | for (i = 0; i < priv->num_rx_queues; i++) { |
fba4ed03 | 328 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); |
bc4598bc | 329 | baddr += 2; |
fba4ed03 SG |
330 | } |
331 | } | |
332 | ||
826aa4a0 AV |
333 | static void gfar_init_mac(struct net_device *ndev) |
334 | { | |
335 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 336 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
337 | u32 rctrl = 0; |
338 | u32 tctrl = 0; | |
339 | u32 attrs = 0; | |
340 | ||
fba4ed03 SG |
341 | /* write the tx/rx base registers */ |
342 | gfar_init_tx_rx_base(priv); | |
32c513bc | 343 | |
826aa4a0 | 344 | /* Configure the coalescing support */ |
46ceb60c | 345 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
fba4ed03 | 346 | |
1ccb8389 | 347 | if (priv->rx_filer_enable) { |
fba4ed03 | 348 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
349 | /* Program the RIR0 reg with the required distribution */ |
350 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
351 | } | |
826aa4a0 | 352 | |
f5ae6279 CM |
353 | /* Restore PROMISC mode */ |
354 | if (ndev->flags & IFF_PROMISC) | |
355 | rctrl |= RCTRL_PROM; | |
356 | ||
8b3afe95 | 357 | if (ndev->features & NETIF_F_RXCSUM) |
826aa4a0 AV |
358 | rctrl |= RCTRL_CHECKSUMMING; |
359 | ||
360 | if (priv->extended_hash) { | |
361 | rctrl |= RCTRL_EXTHASH; | |
362 | ||
363 | gfar_clear_exact_match(ndev); | |
364 | rctrl |= RCTRL_EMEN; | |
365 | } | |
366 | ||
367 | if (priv->padding) { | |
368 | rctrl &= ~RCTRL_PAL_MASK; | |
369 | rctrl |= RCTRL_PADDING(priv->padding); | |
370 | } | |
371 | ||
cc772ab7 MR |
372 | /* Insert receive time stamps into padding alignment bytes */ |
373 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { | |
374 | rctrl &= ~RCTRL_PAL_MASK; | |
97553f7f | 375 | rctrl |= RCTRL_PADDING(8); |
cc772ab7 MR |
376 | priv->padding = 8; |
377 | } | |
378 | ||
97553f7f MR |
379 | /* Enable HW time stamping if requested from user space */ |
380 | if (priv->hwts_rx_en) | |
381 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; | |
382 | ||
87c288c6 | 383 | if (ndev->features & NETIF_F_HW_VLAN_RX) |
b852b720 | 384 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; |
826aa4a0 AV |
385 | |
386 | /* Init rctrl based on our settings */ | |
387 | gfar_write(®s->rctrl, rctrl); | |
388 | ||
389 | if (ndev->features & NETIF_F_IP_CSUM) | |
390 | tctrl |= TCTRL_INIT_CSUM; | |
391 | ||
b98b8bab CM |
392 | if (priv->prio_sched_en) |
393 | tctrl |= TCTRL_TXSCHED_PRIO; | |
394 | else { | |
395 | tctrl |= TCTRL_TXSCHED_WRRS; | |
396 | gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); | |
397 | gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); | |
398 | } | |
fba4ed03 | 399 | |
826aa4a0 AV |
400 | gfar_write(®s->tctrl, tctrl); |
401 | ||
402 | /* Set the extraction length and index */ | |
403 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
404 | ATTRELI_EI(priv->rx_stash_index); | |
405 | ||
406 | gfar_write(®s->attreli, attrs); | |
407 | ||
408 | /* Start with defaults, and add stashing or locking | |
0977f817 JC |
409 | * depending on the approprate variables |
410 | */ | |
826aa4a0 AV |
411 | attrs = ATTR_INIT_SETTINGS; |
412 | ||
413 | if (priv->bd_stash_en) | |
414 | attrs |= ATTR_BDSTASH; | |
415 | ||
416 | if (priv->rx_stash_size != 0) | |
417 | attrs |= ATTR_BUFSTASH; | |
418 | ||
419 | gfar_write(®s->attr, attrs); | |
420 | ||
421 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
422 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
423 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
424 | } | |
425 | ||
a7f38041 SG |
426 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
427 | { | |
428 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
429 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
430 | unsigned long tx_packets = 0, tx_bytes = 0; | |
3a2e16c8 | 431 | int i; |
a7f38041 SG |
432 | |
433 | for (i = 0; i < priv->num_rx_queues; i++) { | |
434 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
bc4598bc | 435 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; |
a7f38041 SG |
436 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; |
437 | } | |
438 | ||
439 | dev->stats.rx_packets = rx_packets; | |
bc4598bc | 440 | dev->stats.rx_bytes = rx_bytes; |
a7f38041 SG |
441 | dev->stats.rx_dropped = rx_dropped; |
442 | ||
443 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
444 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
445 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
446 | } |
447 | ||
bc4598bc | 448 | dev->stats.tx_bytes = tx_bytes; |
a7f38041 SG |
449 | dev->stats.tx_packets = tx_packets; |
450 | ||
451 | return &dev->stats; | |
452 | } | |
453 | ||
26ccfc37 AF |
454 | static const struct net_device_ops gfar_netdev_ops = { |
455 | .ndo_open = gfar_enet_open, | |
456 | .ndo_start_xmit = gfar_start_xmit, | |
457 | .ndo_stop = gfar_close, | |
458 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 459 | .ndo_set_features = gfar_set_features, |
afc4b13d | 460 | .ndo_set_rx_mode = gfar_set_multi, |
26ccfc37 AF |
461 | .ndo_tx_timeout = gfar_timeout, |
462 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 463 | .ndo_get_stats = gfar_get_stats, |
240c102d BH |
464 | .ndo_set_mac_address = eth_mac_addr, |
465 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
466 | #ifdef CONFIG_NET_POLL_CONTROLLER |
467 | .ndo_poll_controller = gfar_netpoll, | |
468 | #endif | |
469 | }; | |
470 | ||
fba4ed03 SG |
471 | void lock_rx_qs(struct gfar_private *priv) |
472 | { | |
3a2e16c8 | 473 | int i; |
fba4ed03 SG |
474 | |
475 | for (i = 0; i < priv->num_rx_queues; i++) | |
476 | spin_lock(&priv->rx_queue[i]->rxlock); | |
477 | } | |
478 | ||
479 | void lock_tx_qs(struct gfar_private *priv) | |
480 | { | |
3a2e16c8 | 481 | int i; |
fba4ed03 SG |
482 | |
483 | for (i = 0; i < priv->num_tx_queues; i++) | |
484 | spin_lock(&priv->tx_queue[i]->txlock); | |
485 | } | |
486 | ||
487 | void unlock_rx_qs(struct gfar_private *priv) | |
488 | { | |
3a2e16c8 | 489 | int i; |
fba4ed03 SG |
490 | |
491 | for (i = 0; i < priv->num_rx_queues; i++) | |
492 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
493 | } | |
494 | ||
495 | void unlock_tx_qs(struct gfar_private *priv) | |
496 | { | |
3a2e16c8 | 497 | int i; |
fba4ed03 SG |
498 | |
499 | for (i = 0; i < priv->num_tx_queues; i++) | |
500 | spin_unlock(&priv->tx_queue[i]->txlock); | |
501 | } | |
502 | ||
87c288c6 JP |
503 | static bool gfar_is_vlan_on(struct gfar_private *priv) |
504 | { | |
505 | return (priv->ndev->features & NETIF_F_HW_VLAN_RX) || | |
506 | (priv->ndev->features & NETIF_F_HW_VLAN_TX); | |
507 | } | |
508 | ||
7f7f5316 AF |
509 | /* Returns 1 if incoming frames use an FCB */ |
510 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 511 | { |
87c288c6 | 512 | return gfar_is_vlan_on(priv) || |
bc4598bc JC |
513 | (priv->ndev->features & NETIF_F_RXCSUM) || |
514 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER); | |
0bbaf069 | 515 | } |
bb40dcbb | 516 | |
fba4ed03 SG |
517 | static void free_tx_pointers(struct gfar_private *priv) |
518 | { | |
3a2e16c8 | 519 | int i; |
fba4ed03 SG |
520 | |
521 | for (i = 0; i < priv->num_tx_queues; i++) | |
522 | kfree(priv->tx_queue[i]); | |
523 | } | |
524 | ||
525 | static void free_rx_pointers(struct gfar_private *priv) | |
526 | { | |
3a2e16c8 | 527 | int i; |
fba4ed03 SG |
528 | |
529 | for (i = 0; i < priv->num_rx_queues; i++) | |
530 | kfree(priv->rx_queue[i]); | |
531 | } | |
532 | ||
46ceb60c SG |
533 | static void unmap_group_regs(struct gfar_private *priv) |
534 | { | |
3a2e16c8 | 535 | int i; |
46ceb60c SG |
536 | |
537 | for (i = 0; i < MAXGROUPS; i++) | |
538 | if (priv->gfargrp[i].regs) | |
539 | iounmap(priv->gfargrp[i].regs); | |
540 | } | |
541 | ||
ee873fda CM |
542 | static void free_gfar_dev(struct gfar_private *priv) |
543 | { | |
544 | int i, j; | |
545 | ||
546 | for (i = 0; i < priv->num_grps; i++) | |
547 | for (j = 0; j < GFAR_NUM_IRQS; j++) { | |
548 | kfree(priv->gfargrp[i].irqinfo[j]); | |
549 | priv->gfargrp[i].irqinfo[j] = NULL; | |
550 | } | |
551 | ||
552 | free_netdev(priv->ndev); | |
553 | } | |
554 | ||
46ceb60c SG |
555 | static void disable_napi(struct gfar_private *priv) |
556 | { | |
3a2e16c8 | 557 | int i; |
46ceb60c SG |
558 | |
559 | for (i = 0; i < priv->num_grps; i++) | |
560 | napi_disable(&priv->gfargrp[i].napi); | |
561 | } | |
562 | ||
563 | static void enable_napi(struct gfar_private *priv) | |
564 | { | |
3a2e16c8 | 565 | int i; |
46ceb60c SG |
566 | |
567 | for (i = 0; i < priv->num_grps; i++) | |
568 | napi_enable(&priv->gfargrp[i].napi); | |
569 | } | |
570 | ||
571 | static int gfar_parse_group(struct device_node *np, | |
bc4598bc | 572 | struct gfar_private *priv, const char *model) |
46ceb60c | 573 | { |
5fedcc14 | 574 | struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; |
46ceb60c | 575 | u32 *queue_mask; |
ee873fda CM |
576 | int i; |
577 | ||
7c1e7e99 PG |
578 | for (i = 0; i < GFAR_NUM_IRQS; i++) { |
579 | grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), | |
580 | GFP_KERNEL); | |
581 | if (!grp->irqinfo[i]) | |
ee873fda | 582 | return -ENOMEM; |
ee873fda | 583 | } |
46ceb60c | 584 | |
5fedcc14 CM |
585 | grp->regs = of_iomap(np, 0); |
586 | if (!grp->regs) | |
46ceb60c SG |
587 | return -ENOMEM; |
588 | ||
ee873fda | 589 | gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); |
46ceb60c SG |
590 | |
591 | /* If we aren't the FEC we have multiple interrupts */ | |
592 | if (model && strcasecmp(model, "FEC")) { | |
ee873fda CM |
593 | gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); |
594 | gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); | |
595 | if (gfar_irq(grp, TX)->irq == NO_IRQ || | |
596 | gfar_irq(grp, RX)->irq == NO_IRQ || | |
597 | gfar_irq(grp, ER)->irq == NO_IRQ) | |
46ceb60c | 598 | return -EINVAL; |
46ceb60c SG |
599 | } |
600 | ||
5fedcc14 CM |
601 | grp->grp_id = priv->num_grps; |
602 | grp->priv = priv; | |
603 | spin_lock_init(&grp->grplock); | |
bc4598bc JC |
604 | if (priv->mode == MQ_MG_MODE) { |
605 | queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); | |
5fedcc14 | 606 | grp->rx_bit_map = queue_mask ? |
bc4598bc JC |
607 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
608 | queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); | |
5fedcc14 | 609 | grp->tx_bit_map = queue_mask ? |
bc4598bc | 610 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
46ceb60c | 611 | } else { |
5fedcc14 CM |
612 | grp->rx_bit_map = 0xFF; |
613 | grp->tx_bit_map = 0xFF; | |
46ceb60c SG |
614 | } |
615 | priv->num_grps++; | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
2dc11581 | 620 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 621 | { |
b31a1d8b AF |
622 | const char *model; |
623 | const char *ctype; | |
624 | const void *mac_addr; | |
fba4ed03 SG |
625 | int err = 0, i; |
626 | struct net_device *dev = NULL; | |
627 | struct gfar_private *priv = NULL; | |
61c7a080 | 628 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 629 | struct device_node *child = NULL; |
4d7902f2 AF |
630 | const u32 *stash; |
631 | const u32 *stash_len; | |
632 | const u32 *stash_idx; | |
fba4ed03 SG |
633 | unsigned int num_tx_qs, num_rx_qs; |
634 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
635 | |
636 | if (!np || !of_device_is_available(np)) | |
637 | return -ENODEV; | |
638 | ||
fba4ed03 SG |
639 | /* parse the num of tx and rx queues */ |
640 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
641 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
642 | ||
643 | if (num_tx_qs > MAX_TX_QS) { | |
59deab26 JP |
644 | pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", |
645 | num_tx_qs, MAX_TX_QS); | |
646 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
647 | return -EINVAL; |
648 | } | |
649 | ||
650 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
651 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
652 | ||
653 | if (num_rx_qs > MAX_RX_QS) { | |
59deab26 JP |
654 | pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", |
655 | num_rx_qs, MAX_RX_QS); | |
656 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
657 | return -EINVAL; |
658 | } | |
659 | ||
660 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
661 | dev = *pdev; | |
662 | if (NULL == dev) | |
663 | return -ENOMEM; | |
664 | ||
665 | priv = netdev_priv(dev); | |
fba4ed03 SG |
666 | priv->ndev = dev; |
667 | ||
fba4ed03 | 668 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 669 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 670 | priv->num_rx_queues = num_rx_qs; |
46ceb60c | 671 | priv->num_grps = 0x0; |
b31a1d8b | 672 | |
0977f817 | 673 | /* Init Rx queue filer rule set linked list */ |
4aa3a715 SP |
674 | INIT_LIST_HEAD(&priv->rx_list.list); |
675 | priv->rx_list.count = 0; | |
676 | mutex_init(&priv->rx_queue_access); | |
677 | ||
b31a1d8b AF |
678 | model = of_get_property(np, "model", NULL); |
679 | ||
46ceb60c SG |
680 | for (i = 0; i < MAXGROUPS; i++) |
681 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 682 | |
46ceb60c SG |
683 | /* Parse and initialize group specific information */ |
684 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
685 | priv->mode = MQ_MG_MODE; | |
686 | for_each_child_of_node(np, child) { | |
687 | err = gfar_parse_group(child, priv, model); | |
688 | if (err) | |
689 | goto err_grp_init; | |
b31a1d8b | 690 | } |
46ceb60c SG |
691 | } else { |
692 | priv->mode = SQ_SG_MODE; | |
693 | err = gfar_parse_group(np, priv, model); | |
bc4598bc | 694 | if (err) |
46ceb60c | 695 | goto err_grp_init; |
b31a1d8b AF |
696 | } |
697 | ||
fba4ed03 SG |
698 | for (i = 0; i < priv->num_tx_queues; i++) |
699 | priv->tx_queue[i] = NULL; | |
700 | for (i = 0; i < priv->num_rx_queues; i++) | |
701 | priv->rx_queue[i] = NULL; | |
702 | ||
703 | for (i = 0; i < priv->num_tx_queues; i++) { | |
de47f072 JP |
704 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), |
705 | GFP_KERNEL); | |
fba4ed03 SG |
706 | if (!priv->tx_queue[i]) { |
707 | err = -ENOMEM; | |
708 | goto tx_alloc_failed; | |
709 | } | |
710 | priv->tx_queue[i]->tx_skbuff = NULL; | |
711 | priv->tx_queue[i]->qindex = i; | |
712 | priv->tx_queue[i]->dev = dev; | |
713 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
714 | } | |
715 | ||
716 | for (i = 0; i < priv->num_rx_queues; i++) { | |
de47f072 JP |
717 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), |
718 | GFP_KERNEL); | |
fba4ed03 SG |
719 | if (!priv->rx_queue[i]) { |
720 | err = -ENOMEM; | |
721 | goto rx_alloc_failed; | |
722 | } | |
723 | priv->rx_queue[i]->rx_skbuff = NULL; | |
724 | priv->rx_queue[i]->qindex = i; | |
725 | priv->rx_queue[i]->dev = dev; | |
726 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
727 | } | |
728 | ||
729 | ||
4d7902f2 AF |
730 | stash = of_get_property(np, "bd-stash", NULL); |
731 | ||
a12f801d | 732 | if (stash) { |
4d7902f2 AF |
733 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
734 | priv->bd_stash_en = 1; | |
735 | } | |
736 | ||
737 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
738 | ||
739 | if (stash_len) | |
740 | priv->rx_stash_size = *stash_len; | |
741 | ||
742 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
743 | ||
744 | if (stash_idx) | |
745 | priv->rx_stash_index = *stash_idx; | |
746 | ||
747 | if (stash_len || stash_idx) | |
748 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
749 | ||
b31a1d8b | 750 | mac_addr = of_get_mac_address(np); |
bc4598bc | 751 | |
b31a1d8b | 752 | if (mac_addr) |
6a3c910c | 753 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
b31a1d8b AF |
754 | |
755 | if (model && !strcasecmp(model, "TSEC")) | |
bc4598bc JC |
756 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
757 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
758 | FSL_GIANFAR_DEV_HAS_RMON | | |
759 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
760 | ||
b31a1d8b | 761 | if (model && !strcasecmp(model, "eTSEC")) |
bc4598bc JC |
762 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
763 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
764 | FSL_GIANFAR_DEV_HAS_RMON | | |
765 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
766 | FSL_GIANFAR_DEV_HAS_PADDING | | |
767 | FSL_GIANFAR_DEV_HAS_CSUM | | |
768 | FSL_GIANFAR_DEV_HAS_VLAN | | |
769 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
770 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | | |
771 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
772 | |
773 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
774 | ||
775 | /* We only care about rgmii-id. The rest are autodetected */ | |
776 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
777 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
778 | else | |
779 | priv->interface = PHY_INTERFACE_MODE_MII; | |
780 | ||
781 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
782 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
783 | ||
fe192a49 | 784 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
785 | |
786 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 787 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
788 | |
789 | return 0; | |
790 | ||
fba4ed03 SG |
791 | rx_alloc_failed: |
792 | free_rx_pointers(priv); | |
793 | tx_alloc_failed: | |
794 | free_tx_pointers(priv); | |
46ceb60c SG |
795 | err_grp_init: |
796 | unmap_group_regs(priv); | |
ee873fda | 797 | free_gfar_dev(priv); |
b31a1d8b AF |
798 | return err; |
799 | } | |
800 | ||
cc772ab7 | 801 | static int gfar_hwtstamp_ioctl(struct net_device *netdev, |
bc4598bc | 802 | struct ifreq *ifr, int cmd) |
cc772ab7 MR |
803 | { |
804 | struct hwtstamp_config config; | |
805 | struct gfar_private *priv = netdev_priv(netdev); | |
806 | ||
807 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
808 | return -EFAULT; | |
809 | ||
810 | /* reserved for future extensions */ | |
811 | if (config.flags) | |
812 | return -EINVAL; | |
813 | ||
f0ee7acf MR |
814 | switch (config.tx_type) { |
815 | case HWTSTAMP_TX_OFF: | |
816 | priv->hwts_tx_en = 0; | |
817 | break; | |
818 | case HWTSTAMP_TX_ON: | |
819 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
820 | return -ERANGE; | |
821 | priv->hwts_tx_en = 1; | |
822 | break; | |
823 | default: | |
cc772ab7 | 824 | return -ERANGE; |
f0ee7acf | 825 | } |
cc772ab7 MR |
826 | |
827 | switch (config.rx_filter) { | |
828 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
829 | if (priv->hwts_rx_en) { |
830 | stop_gfar(netdev); | |
831 | priv->hwts_rx_en = 0; | |
832 | startup_gfar(netdev); | |
833 | } | |
cc772ab7 MR |
834 | break; |
835 | default: | |
836 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
837 | return -ERANGE; | |
97553f7f MR |
838 | if (!priv->hwts_rx_en) { |
839 | stop_gfar(netdev); | |
840 | priv->hwts_rx_en = 1; | |
841 | startup_gfar(netdev); | |
842 | } | |
cc772ab7 MR |
843 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
844 | break; | |
845 | } | |
846 | ||
847 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
848 | -EFAULT : 0; | |
849 | } | |
850 | ||
0faac9f7 CW |
851 | /* Ioctl MII Interface */ |
852 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
853 | { | |
854 | struct gfar_private *priv = netdev_priv(dev); | |
855 | ||
856 | if (!netif_running(dev)) | |
857 | return -EINVAL; | |
858 | ||
cc772ab7 MR |
859 | if (cmd == SIOCSHWTSTAMP) |
860 | return gfar_hwtstamp_ioctl(dev, rq, cmd); | |
861 | ||
0faac9f7 CW |
862 | if (!priv->phydev) |
863 | return -ENODEV; | |
864 | ||
28b04113 | 865 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
866 | } |
867 | ||
fba4ed03 SG |
868 | static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) |
869 | { | |
870 | unsigned int new_bit_map = 0x0; | |
871 | int mask = 0x1 << (max_qs - 1), i; | |
bc4598bc | 872 | |
fba4ed03 SG |
873 | for (i = 0; i < max_qs; i++) { |
874 | if (bit_map & mask) | |
875 | new_bit_map = new_bit_map + (1 << i); | |
876 | mask = mask >> 0x1; | |
877 | } | |
878 | return new_bit_map; | |
879 | } | |
7a8b3372 | 880 | |
18294ad1 AV |
881 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
882 | u32 class) | |
7a8b3372 SG |
883 | { |
884 | u32 rqfpr = FPR_FILER_MASK; | |
885 | u32 rqfcr = 0x0; | |
886 | ||
887 | rqfar--; | |
888 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
889 | priv->ftp_rqfpr[rqfar] = rqfpr; |
890 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
891 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
892 | ||
893 | rqfar--; | |
894 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
895 | priv->ftp_rqfpr[rqfar] = rqfpr; |
896 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
897 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
898 | ||
899 | rqfar--; | |
900 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
901 | rqfpr = class; | |
6c43e046 WJB |
902 | priv->ftp_rqfcr[rqfar] = rqfcr; |
903 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
904 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
905 | ||
906 | rqfar--; | |
907 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
908 | rqfpr = class; | |
6c43e046 WJB |
909 | priv->ftp_rqfcr[rqfar] = rqfcr; |
910 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
911 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
912 | ||
913 | return rqfar; | |
914 | } | |
915 | ||
916 | static void gfar_init_filer_table(struct gfar_private *priv) | |
917 | { | |
918 | int i = 0x0; | |
919 | u32 rqfar = MAX_FILER_IDX; | |
920 | u32 rqfcr = 0x0; | |
921 | u32 rqfpr = FPR_FILER_MASK; | |
922 | ||
923 | /* Default rule */ | |
924 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
925 | priv->ftp_rqfcr[rqfar] = rqfcr; |
926 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
927 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
928 | ||
929 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
930 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
931 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
932 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
933 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
934 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
935 | ||
85dd08eb | 936 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
937 | priv->cur_filer_idx = rqfar; |
938 | ||
939 | /* Rest are masked rules */ | |
940 | rqfcr = RQFCR_CMP_NOMATCH; | |
941 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
942 | priv->ftp_rqfcr[i] = rqfcr; |
943 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
944 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
945 | } | |
946 | } | |
947 | ||
7d350977 AV |
948 | static void gfar_detect_errata(struct gfar_private *priv) |
949 | { | |
950 | struct device *dev = &priv->ofdev->dev; | |
951 | unsigned int pvr = mfspr(SPRN_PVR); | |
952 | unsigned int svr = mfspr(SPRN_SVR); | |
953 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
954 | unsigned int rev = svr & 0xffff; | |
955 | ||
956 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
957 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
bc4598bc | 958 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
7d350977 AV |
959 | priv->errata |= GFAR_ERRATA_74; |
960 | ||
deb90eac AV |
961 | /* MPC8313 and MPC837x all rev */ |
962 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 963 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
deb90eac AV |
964 | priv->errata |= GFAR_ERRATA_76; |
965 | ||
511d934f AV |
966 | /* MPC8313 and MPC837x all rev */ |
967 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 968 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
511d934f AV |
969 | priv->errata |= GFAR_ERRATA_A002; |
970 | ||
4363c2fd AD |
971 | /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ |
972 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || | |
bc4598bc | 973 | (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) |
4363c2fd AD |
974 | priv->errata |= GFAR_ERRATA_12; |
975 | ||
7d350977 AV |
976 | if (priv->errata) |
977 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
978 | priv->errata); | |
979 | } | |
980 | ||
bb40dcbb | 981 | /* Set up the ethernet device structure, private data, |
0977f817 JC |
982 | * and anything else we need before we start |
983 | */ | |
74888760 | 984 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 LT |
985 | { |
986 | u32 tempval; | |
987 | struct net_device *dev = NULL; | |
988 | struct gfar_private *priv = NULL; | |
f4983704 | 989 | struct gfar __iomem *regs = NULL; |
46ceb60c | 990 | int err = 0, i, grp_idx = 0; |
fba4ed03 | 991 | u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; |
46ceb60c | 992 | u32 isrg = 0; |
18294ad1 | 993 | u32 __iomem *baddr; |
1da177e4 | 994 | |
fba4ed03 | 995 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 996 | |
fba4ed03 SG |
997 | if (err) |
998 | return err; | |
1da177e4 LT |
999 | |
1000 | priv = netdev_priv(dev); | |
4826857f KG |
1001 | priv->ndev = dev; |
1002 | priv->ofdev = ofdev; | |
369ec162 | 1003 | priv->dev = &ofdev->dev; |
4826857f | 1004 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 1005 | |
d87eb127 | 1006 | spin_lock_init(&priv->bflock); |
ab939905 | 1007 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 1008 | |
b31a1d8b | 1009 | dev_set_drvdata(&ofdev->dev, priv); |
46ceb60c | 1010 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1011 | |
7d350977 AV |
1012 | gfar_detect_errata(priv); |
1013 | ||
0977f817 JC |
1014 | /* Stop the DMA engine now, in case it was running before |
1015 | * (The firmware could have used it, and left it running). | |
1016 | */ | |
257d938a | 1017 | gfar_halt(dev); |
1da177e4 LT |
1018 | |
1019 | /* Reset MAC layer */ | |
f4983704 | 1020 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); |
1da177e4 | 1021 | |
b98ac702 AF |
1022 | /* We need to delay at least 3 TX clocks */ |
1023 | udelay(2); | |
1024 | ||
1da177e4 | 1025 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
f4983704 | 1026 | gfar_write(®s->maccfg1, tempval); |
1da177e4 LT |
1027 | |
1028 | /* Initialize MACCFG2. */ | |
7d350977 AV |
1029 | tempval = MACCFG2_INIT_SETTINGS; |
1030 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1031 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1032 | gfar_write(®s->maccfg2, tempval); | |
1da177e4 LT |
1033 | |
1034 | /* Initialize ECNTRL */ | |
f4983704 | 1035 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
1da177e4 | 1036 | |
1da177e4 | 1037 | /* Set the dev->base_addr to the gfar reg region */ |
f4983704 | 1038 | dev->base_addr = (unsigned long) regs; |
1da177e4 | 1039 | |
1da177e4 | 1040 | /* Fill in the dev structure */ |
1da177e4 | 1041 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1042 | dev->mtu = 1500; |
26ccfc37 | 1043 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1044 | dev->ethtool_ops = &gfar_ethtool_ops; |
1045 | ||
fba4ed03 | 1046 | /* Register for napi ...We are registering NAPI for each grp */ |
46ceb60c | 1047 | for (i = 0; i < priv->num_grps; i++) |
bc4598bc JC |
1048 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, |
1049 | GFAR_DEV_WEIGHT); | |
a12f801d | 1050 | |
b31a1d8b | 1051 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 | 1052 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1053 | NETIF_F_RXCSUM; |
8b3afe95 | 1054 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1055 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; |
8b3afe95 | 1056 | } |
0bbaf069 | 1057 | |
87c288c6 JP |
1058 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
1059 | dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
e2c53be2 | 1060 | dev->features |= NETIF_F_HW_VLAN_RX; |
87c288c6 | 1061 | } |
0bbaf069 | 1062 | |
b31a1d8b | 1063 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
1064 | priv->extended_hash = 1; |
1065 | priv->hash_width = 9; | |
1066 | ||
f4983704 SG |
1067 | priv->hash_regs[0] = ®s->igaddr0; |
1068 | priv->hash_regs[1] = ®s->igaddr1; | |
1069 | priv->hash_regs[2] = ®s->igaddr2; | |
1070 | priv->hash_regs[3] = ®s->igaddr3; | |
1071 | priv->hash_regs[4] = ®s->igaddr4; | |
1072 | priv->hash_regs[5] = ®s->igaddr5; | |
1073 | priv->hash_regs[6] = ®s->igaddr6; | |
1074 | priv->hash_regs[7] = ®s->igaddr7; | |
1075 | priv->hash_regs[8] = ®s->gaddr0; | |
1076 | priv->hash_regs[9] = ®s->gaddr1; | |
1077 | priv->hash_regs[10] = ®s->gaddr2; | |
1078 | priv->hash_regs[11] = ®s->gaddr3; | |
1079 | priv->hash_regs[12] = ®s->gaddr4; | |
1080 | priv->hash_regs[13] = ®s->gaddr5; | |
1081 | priv->hash_regs[14] = ®s->gaddr6; | |
1082 | priv->hash_regs[15] = ®s->gaddr7; | |
0bbaf069 KG |
1083 | |
1084 | } else { | |
1085 | priv->extended_hash = 0; | |
1086 | priv->hash_width = 8; | |
1087 | ||
f4983704 SG |
1088 | priv->hash_regs[0] = ®s->gaddr0; |
1089 | priv->hash_regs[1] = ®s->gaddr1; | |
1090 | priv->hash_regs[2] = ®s->gaddr2; | |
1091 | priv->hash_regs[3] = ®s->gaddr3; | |
1092 | priv->hash_regs[4] = ®s->gaddr4; | |
1093 | priv->hash_regs[5] = ®s->gaddr5; | |
1094 | priv->hash_regs[6] = ®s->gaddr6; | |
1095 | priv->hash_regs[7] = ®s->gaddr7; | |
0bbaf069 KG |
1096 | } |
1097 | ||
b31a1d8b | 1098 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
1099 | priv->padding = DEFAULT_PADDING; |
1100 | else | |
1101 | priv->padding = 0; | |
1102 | ||
cc772ab7 | 1103 | if (dev->features & NETIF_F_IP_CSUM || |
bc4598bc | 1104 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) |
bee9e58c | 1105 | dev->needed_headroom = GMAC_FCB_LEN; |
1da177e4 | 1106 | |
46ceb60c SG |
1107 | /* Program the isrg regs only if number of grps > 1 */ |
1108 | if (priv->num_grps > 1) { | |
1109 | baddr = ®s->isrg0; | |
1110 | for (i = 0; i < priv->num_grps; i++) { | |
1111 | isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); | |
1112 | isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); | |
1113 | gfar_write(baddr, isrg); | |
1114 | baddr++; | |
1115 | isrg = 0x0; | |
1116 | } | |
1117 | } | |
1118 | ||
fba4ed03 | 1119 | /* Need to reverse the bit maps as bit_map's MSB is q0 |
984b3f57 | 1120 | * but, for_each_set_bit parses from right to left, which |
0977f817 JC |
1121 | * basically reverses the queue numbers |
1122 | */ | |
46ceb60c | 1123 | for (i = 0; i< priv->num_grps; i++) { |
bc4598bc JC |
1124 | priv->gfargrp[i].tx_bit_map = |
1125 | reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS); | |
1126 | priv->gfargrp[i].rx_bit_map = | |
1127 | reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS); | |
46ceb60c SG |
1128 | } |
1129 | ||
1130 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
0977f817 JC |
1131 | * also assign queues to groups |
1132 | */ | |
46ceb60c SG |
1133 | for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { |
1134 | priv->gfargrp[grp_idx].num_rx_queues = 0x0; | |
bc4598bc | 1135 | |
984b3f57 | 1136 | for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, |
bc4598bc | 1137 | priv->num_rx_queues) { |
46ceb60c SG |
1138 | priv->gfargrp[grp_idx].num_rx_queues++; |
1139 | priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1140 | rstat = rstat | (RSTAT_CLEAR_RHALT >> i); | |
1141 | rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
1142 | } | |
1143 | priv->gfargrp[grp_idx].num_tx_queues = 0x0; | |
bc4598bc | 1144 | |
984b3f57 | 1145 | for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, |
bc4598bc | 1146 | priv->num_tx_queues) { |
46ceb60c SG |
1147 | priv->gfargrp[grp_idx].num_tx_queues++; |
1148 | priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1149 | tstat = tstat | (TSTAT_CLEAR_THALT >> i); | |
1150 | tqueue = tqueue | (TQUEUE_EN0 >> i); | |
1151 | } | |
1152 | priv->gfargrp[grp_idx].rstat = rstat; | |
1153 | priv->gfargrp[grp_idx].tstat = tstat; | |
1154 | rstat = tstat =0; | |
fba4ed03 | 1155 | } |
fba4ed03 SG |
1156 | |
1157 | gfar_write(®s->rqueue, rqueue); | |
1158 | gfar_write(®s->tqueue, tqueue); | |
1159 | ||
1da177e4 | 1160 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; |
1da177e4 | 1161 | |
a12f801d | 1162 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1163 | for (i = 0; i < priv->num_tx_queues; i++) { |
1164 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1165 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1166 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1167 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1168 | } | |
a12f801d | 1169 | |
fba4ed03 SG |
1170 | for (i = 0; i < priv->num_rx_queues; i++) { |
1171 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1172 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1173 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1174 | } | |
1da177e4 | 1175 | |
0977f817 | 1176 | /* always enable rx filer */ |
4aa3a715 | 1177 | priv->rx_filer_enable = 1; |
0bbaf069 KG |
1178 | /* Enable most messages by default */ |
1179 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
b98b8bab CM |
1180 | /* use pritority h/w tx queue scheduling for single queue devices */ |
1181 | if (priv->num_tx_queues == 1) | |
1182 | priv->prio_sched_en = 1; | |
0bbaf069 | 1183 | |
d3eab82b TP |
1184 | /* Carrier starts down, phylib will bring it up */ |
1185 | netif_carrier_off(dev); | |
1186 | ||
1da177e4 LT |
1187 | err = register_netdev(dev); |
1188 | ||
1189 | if (err) { | |
59deab26 | 1190 | pr_err("%s: Cannot register net device, aborting\n", dev->name); |
1da177e4 LT |
1191 | goto register_fail; |
1192 | } | |
1193 | ||
2884e5cc | 1194 | device_init_wakeup(&dev->dev, |
bc4598bc JC |
1195 | priv->device_flags & |
1196 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
2884e5cc | 1197 | |
c50a5d9a | 1198 | /* fill out IRQ number and name fields */ |
46ceb60c | 1199 | for (i = 0; i < priv->num_grps; i++) { |
ee873fda | 1200 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
46ceb60c | 1201 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
ee873fda | 1202 | sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", |
0015e551 | 1203 | dev->name, "_g", '0' + i, "_tx"); |
ee873fda | 1204 | sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", |
0015e551 | 1205 | dev->name, "_g", '0' + i, "_rx"); |
ee873fda | 1206 | sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", |
0015e551 | 1207 | dev->name, "_g", '0' + i, "_er"); |
46ceb60c | 1208 | } else |
ee873fda | 1209 | strcpy(gfar_irq(grp, TX)->name, dev->name); |
46ceb60c | 1210 | } |
c50a5d9a | 1211 | |
7a8b3372 SG |
1212 | /* Initialize the filer table */ |
1213 | gfar_init_filer_table(priv); | |
1214 | ||
7f7f5316 AF |
1215 | /* Create all the sysfs files */ |
1216 | gfar_init_sysfs(dev); | |
1217 | ||
1da177e4 | 1218 | /* Print out the device info */ |
59deab26 | 1219 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
1da177e4 | 1220 | |
0977f817 JC |
1221 | /* Even more device info helps when determining which kernel |
1222 | * provided which set of benchmarks. | |
1223 | */ | |
59deab26 | 1224 | netdev_info(dev, "Running with NAPI enabled\n"); |
fba4ed03 | 1225 | for (i = 0; i < priv->num_rx_queues; i++) |
59deab26 JP |
1226 | netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", |
1227 | i, priv->rx_queue[i]->rx_ring_size); | |
bc4598bc | 1228 | for (i = 0; i < priv->num_tx_queues; i++) |
59deab26 JP |
1229 | netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", |
1230 | i, priv->tx_queue[i]->tx_ring_size); | |
1da177e4 LT |
1231 | |
1232 | return 0; | |
1233 | ||
1234 | register_fail: | |
46ceb60c | 1235 | unmap_group_regs(priv); |
fba4ed03 SG |
1236 | free_tx_pointers(priv); |
1237 | free_rx_pointers(priv); | |
fe192a49 GL |
1238 | if (priv->phy_node) |
1239 | of_node_put(priv->phy_node); | |
1240 | if (priv->tbi_node) | |
1241 | of_node_put(priv->tbi_node); | |
ee873fda | 1242 | free_gfar_dev(priv); |
bb40dcbb | 1243 | return err; |
1da177e4 LT |
1244 | } |
1245 | ||
2dc11581 | 1246 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1247 | { |
b31a1d8b | 1248 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 1249 | |
fe192a49 GL |
1250 | if (priv->phy_node) |
1251 | of_node_put(priv->phy_node); | |
1252 | if (priv->tbi_node) | |
1253 | of_node_put(priv->tbi_node); | |
1254 | ||
b31a1d8b | 1255 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 1256 | |
d9d8e041 | 1257 | unregister_netdev(priv->ndev); |
46ceb60c | 1258 | unmap_group_regs(priv); |
ee873fda | 1259 | free_gfar_dev(priv); |
1da177e4 LT |
1260 | |
1261 | return 0; | |
1262 | } | |
1263 | ||
d87eb127 | 1264 | #ifdef CONFIG_PM |
be926fc4 AV |
1265 | |
1266 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1267 | { |
be926fc4 AV |
1268 | struct gfar_private *priv = dev_get_drvdata(dev); |
1269 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1270 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1271 | unsigned long flags; |
1272 | u32 tempval; | |
1273 | ||
1274 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1275 | (priv->device_flags & |
1276 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1277 | |
be926fc4 | 1278 | netif_device_detach(ndev); |
d87eb127 | 1279 | |
be926fc4 | 1280 | if (netif_running(ndev)) { |
fba4ed03 SG |
1281 | |
1282 | local_irq_save(flags); | |
1283 | lock_tx_qs(priv); | |
1284 | lock_rx_qs(priv); | |
d87eb127 | 1285 | |
be926fc4 | 1286 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1287 | |
1288 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1289 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1290 | |
1291 | tempval &= ~MACCFG1_TX_EN; | |
1292 | ||
1293 | if (!magic_packet) | |
1294 | tempval &= ~MACCFG1_RX_EN; | |
1295 | ||
f4983704 | 1296 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1297 | |
fba4ed03 SG |
1298 | unlock_rx_qs(priv); |
1299 | unlock_tx_qs(priv); | |
1300 | local_irq_restore(flags); | |
d87eb127 | 1301 | |
46ceb60c | 1302 | disable_napi(priv); |
d87eb127 SW |
1303 | |
1304 | if (magic_packet) { | |
1305 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1306 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1307 | |
1308 | /* Enable Magic Packet mode */ | |
f4983704 | 1309 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1310 | tempval |= MACCFG2_MPEN; |
f4983704 | 1311 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1312 | } else { |
1313 | phy_stop(priv->phydev); | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | return 0; | |
1318 | } | |
1319 | ||
be926fc4 | 1320 | static int gfar_resume(struct device *dev) |
d87eb127 | 1321 | { |
be926fc4 AV |
1322 | struct gfar_private *priv = dev_get_drvdata(dev); |
1323 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1324 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1325 | unsigned long flags; |
1326 | u32 tempval; | |
1327 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1328 | (priv->device_flags & |
1329 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1330 | |
be926fc4 AV |
1331 | if (!netif_running(ndev)) { |
1332 | netif_device_attach(ndev); | |
d87eb127 SW |
1333 | return 0; |
1334 | } | |
1335 | ||
1336 | if (!magic_packet && priv->phydev) | |
1337 | phy_start(priv->phydev); | |
1338 | ||
1339 | /* Disable Magic Packet mode, in case something | |
1340 | * else woke us up. | |
1341 | */ | |
fba4ed03 SG |
1342 | local_irq_save(flags); |
1343 | lock_tx_qs(priv); | |
1344 | lock_rx_qs(priv); | |
d87eb127 | 1345 | |
f4983704 | 1346 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1347 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1348 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1349 | |
be926fc4 | 1350 | gfar_start(ndev); |
d87eb127 | 1351 | |
fba4ed03 SG |
1352 | unlock_rx_qs(priv); |
1353 | unlock_tx_qs(priv); | |
1354 | local_irq_restore(flags); | |
d87eb127 | 1355 | |
be926fc4 AV |
1356 | netif_device_attach(ndev); |
1357 | ||
46ceb60c | 1358 | enable_napi(priv); |
be926fc4 AV |
1359 | |
1360 | return 0; | |
1361 | } | |
1362 | ||
1363 | static int gfar_restore(struct device *dev) | |
1364 | { | |
1365 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1366 | struct net_device *ndev = priv->ndev; | |
1367 | ||
103cdd1d WD |
1368 | if (!netif_running(ndev)) { |
1369 | netif_device_attach(ndev); | |
1370 | ||
be926fc4 | 1371 | return 0; |
103cdd1d | 1372 | } |
be926fc4 | 1373 | |
1eb8f7a7 CM |
1374 | if (gfar_init_bds(ndev)) { |
1375 | free_skb_resources(priv); | |
1376 | return -ENOMEM; | |
1377 | } | |
1378 | ||
be926fc4 AV |
1379 | init_registers(ndev); |
1380 | gfar_set_mac_address(ndev); | |
1381 | gfar_init_mac(ndev); | |
1382 | gfar_start(ndev); | |
1383 | ||
1384 | priv->oldlink = 0; | |
1385 | priv->oldspeed = 0; | |
1386 | priv->oldduplex = -1; | |
1387 | ||
1388 | if (priv->phydev) | |
1389 | phy_start(priv->phydev); | |
d87eb127 | 1390 | |
be926fc4 | 1391 | netif_device_attach(ndev); |
5ea681d4 | 1392 | enable_napi(priv); |
d87eb127 SW |
1393 | |
1394 | return 0; | |
1395 | } | |
be926fc4 AV |
1396 | |
1397 | static struct dev_pm_ops gfar_pm_ops = { | |
1398 | .suspend = gfar_suspend, | |
1399 | .resume = gfar_resume, | |
1400 | .freeze = gfar_suspend, | |
1401 | .thaw = gfar_resume, | |
1402 | .restore = gfar_restore, | |
1403 | }; | |
1404 | ||
1405 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1406 | ||
d87eb127 | 1407 | #else |
be926fc4 AV |
1408 | |
1409 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1410 | |
d87eb127 | 1411 | #endif |
1da177e4 | 1412 | |
e8a2b6a4 AF |
1413 | /* Reads the controller's registers to determine what interface |
1414 | * connects it to the PHY. | |
1415 | */ | |
1416 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1417 | { | |
1418 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1419 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1420 | u32 ecntrl; |
1421 | ||
f4983704 | 1422 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1423 | |
1424 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1425 | return PHY_INTERFACE_MODE_SGMII; | |
1426 | ||
1427 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1428 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1429 | return PHY_INTERFACE_MODE_RTBI; | |
1430 | else | |
1431 | return PHY_INTERFACE_MODE_TBI; | |
1432 | } | |
1433 | ||
1434 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
bc4598bc | 1435 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) { |
e8a2b6a4 | 1436 | return PHY_INTERFACE_MODE_RMII; |
bc4598bc | 1437 | } |
7132ab7f | 1438 | else { |
b31a1d8b | 1439 | phy_interface_t interface = priv->interface; |
7132ab7f | 1440 | |
0977f817 | 1441 | /* This isn't autodetected right now, so it must |
7132ab7f AF |
1442 | * be set by the device tree or platform code. |
1443 | */ | |
1444 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1445 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1446 | ||
e8a2b6a4 | 1447 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1448 | } |
e8a2b6a4 AF |
1449 | } |
1450 | ||
b31a1d8b | 1451 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1452 | return PHY_INTERFACE_MODE_GMII; |
1453 | ||
1454 | return PHY_INTERFACE_MODE_MII; | |
1455 | } | |
1456 | ||
1457 | ||
bb40dcbb AF |
1458 | /* Initializes driver's PHY state, and attaches to the PHY. |
1459 | * Returns 0 on success. | |
1da177e4 LT |
1460 | */ |
1461 | static int init_phy(struct net_device *dev) | |
1462 | { | |
1463 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1464 | uint gigabit_support = |
b31a1d8b | 1465 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 1466 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 1467 | phy_interface_t interface; |
1da177e4 LT |
1468 | |
1469 | priv->oldlink = 0; | |
1470 | priv->oldspeed = 0; | |
1471 | priv->oldduplex = -1; | |
1472 | ||
e8a2b6a4 AF |
1473 | interface = gfar_get_interface(dev); |
1474 | ||
1db780f8 AV |
1475 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1476 | interface); | |
1477 | if (!priv->phydev) | |
1478 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1479 | interface); | |
1480 | if (!priv->phydev) { | |
1481 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1482 | return -ENODEV; | |
fe192a49 | 1483 | } |
1da177e4 | 1484 | |
d3c12873 KJ |
1485 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1486 | gfar_configure_serdes(dev); | |
1487 | ||
bb40dcbb | 1488 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1489 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1490 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1491 | |
1492 | return 0; | |
1da177e4 LT |
1493 | } |
1494 | ||
0977f817 | 1495 | /* Initialize TBI PHY interface for communicating with the |
d0313587 PG |
1496 | * SERDES lynx PHY on the chip. We communicate with this PHY |
1497 | * through the MDIO bus on each controller, treating it as a | |
1498 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1499 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1500 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1501 | * value doesn't matter, as there are no other PHYs on the bus. | |
1502 | */ | |
d3c12873 KJ |
1503 | static void gfar_configure_serdes(struct net_device *dev) |
1504 | { | |
1505 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1506 | struct phy_device *tbiphy; |
1507 | ||
1508 | if (!priv->tbi_node) { | |
1509 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1510 | "device tree specify a tbi-handle\n"); | |
1511 | return; | |
1512 | } | |
c132419e | 1513 | |
fe192a49 GL |
1514 | tbiphy = of_phy_find_device(priv->tbi_node); |
1515 | if (!tbiphy) { | |
1516 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1517 | return; |
1518 | } | |
d3c12873 | 1519 | |
0977f817 | 1520 | /* If the link is already up, we must already be ok, and don't need to |
bdb59f94 TP |
1521 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1522 | * everything for us? Resetting it takes the link down and requires | |
1523 | * several seconds for it to come back. | |
1524 | */ | |
fe192a49 | 1525 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1526 | return; |
d3c12873 | 1527 | |
d0313587 | 1528 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1529 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1530 | |
fe192a49 | 1531 | phy_write(tbiphy, MII_ADVERTISE, |
bc4598bc JC |
1532 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1533 | ADVERTISE_1000XPSE_ASYM); | |
d3c12873 | 1534 | |
bc4598bc JC |
1535 | phy_write(tbiphy, MII_BMCR, |
1536 | BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | | |
1537 | BMCR_SPEED1000); | |
d3c12873 KJ |
1538 | } |
1539 | ||
1da177e4 LT |
1540 | static void init_registers(struct net_device *dev) |
1541 | { | |
1542 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 1543 | struct gfar __iomem *regs = NULL; |
3a2e16c8 | 1544 | int i; |
1da177e4 | 1545 | |
46ceb60c SG |
1546 | for (i = 0; i < priv->num_grps; i++) { |
1547 | regs = priv->gfargrp[i].regs; | |
1548 | /* Clear IEVENT */ | |
1549 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1da177e4 | 1550 | |
46ceb60c SG |
1551 | /* Initialize IMASK */ |
1552 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1553 | } | |
1da177e4 | 1554 | |
46ceb60c | 1555 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1556 | /* Init hash registers to zero */ |
f4983704 SG |
1557 | gfar_write(®s->igaddr0, 0); |
1558 | gfar_write(®s->igaddr1, 0); | |
1559 | gfar_write(®s->igaddr2, 0); | |
1560 | gfar_write(®s->igaddr3, 0); | |
1561 | gfar_write(®s->igaddr4, 0); | |
1562 | gfar_write(®s->igaddr5, 0); | |
1563 | gfar_write(®s->igaddr6, 0); | |
1564 | gfar_write(®s->igaddr7, 0); | |
1565 | ||
1566 | gfar_write(®s->gaddr0, 0); | |
1567 | gfar_write(®s->gaddr1, 0); | |
1568 | gfar_write(®s->gaddr2, 0); | |
1569 | gfar_write(®s->gaddr3, 0); | |
1570 | gfar_write(®s->gaddr4, 0); | |
1571 | gfar_write(®s->gaddr5, 0); | |
1572 | gfar_write(®s->gaddr6, 0); | |
1573 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1574 | |
1da177e4 | 1575 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1576 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1577 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1578 | |
1579 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1580 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1581 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1582 | } |
1583 | ||
1584 | /* Initialize the max receive buffer length */ | |
f4983704 | 1585 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1586 | |
1da177e4 | 1587 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1588 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1589 | } |
1590 | ||
511d934f AV |
1591 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1592 | { | |
1593 | u32 res; | |
1594 | ||
0977f817 | 1595 | /* Normaly TSEC should not hang on GRS commands, so we should |
511d934f AV |
1596 | * actually wait for IEVENT_GRSC flag. |
1597 | */ | |
1598 | if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) | |
1599 | return 0; | |
1600 | ||
0977f817 | 1601 | /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are |
511d934f AV |
1602 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle |
1603 | * and the Rx can be safely reset. | |
1604 | */ | |
1605 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1606 | res &= 0x7f807f80; | |
1607 | if ((res & 0xffff) == (res >> 16)) | |
1608 | return 1; | |
1609 | ||
1610 | return 0; | |
1611 | } | |
0bbaf069 KG |
1612 | |
1613 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1614 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1615 | { |
1616 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1617 | struct gfar __iomem *regs = NULL; |
1da177e4 | 1618 | u32 tempval; |
3a2e16c8 | 1619 | int i; |
1da177e4 | 1620 | |
46ceb60c SG |
1621 | for (i = 0; i < priv->num_grps; i++) { |
1622 | regs = priv->gfargrp[i].regs; | |
1623 | /* Mask all interrupts */ | |
1624 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1da177e4 | 1625 | |
46ceb60c SG |
1626 | /* Clear all interrupts */ |
1627 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1628 | } | |
1da177e4 | 1629 | |
46ceb60c | 1630 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1631 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1632 | tempval = gfar_read(®s->dmactrl); |
bc4598bc JC |
1633 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != |
1634 | (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1635 | int ret; |
1636 | ||
1da177e4 | 1637 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1638 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1639 | |
511d934f AV |
1640 | do { |
1641 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1642 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1643 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1644 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1645 | ret = __gfar_is_rx_idle(priv); | |
1646 | } while (!ret); | |
1da177e4 | 1647 | } |
d87eb127 | 1648 | } |
d87eb127 SW |
1649 | |
1650 | /* Halt the receive and transmit queues */ | |
1651 | void gfar_halt(struct net_device *dev) | |
1652 | { | |
1653 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1654 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1655 | u32 tempval; |
1da177e4 | 1656 | |
2a54adc3 SW |
1657 | gfar_halt_nodisable(dev); |
1658 | ||
1da177e4 LT |
1659 | /* Disable Rx and Tx */ |
1660 | tempval = gfar_read(®s->maccfg1); | |
1661 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1662 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1663 | } |
1664 | ||
46ceb60c SG |
1665 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1666 | { | |
ee873fda CM |
1667 | free_irq(gfar_irq(grp, TX)->irq, grp); |
1668 | free_irq(gfar_irq(grp, RX)->irq, grp); | |
1669 | free_irq(gfar_irq(grp, ER)->irq, grp); | |
46ceb60c SG |
1670 | } |
1671 | ||
0bbaf069 KG |
1672 | void stop_gfar(struct net_device *dev) |
1673 | { | |
1674 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1675 | unsigned long flags; |
46ceb60c | 1676 | int i; |
0bbaf069 | 1677 | |
bb40dcbb AF |
1678 | phy_stop(priv->phydev); |
1679 | ||
a12f801d | 1680 | |
0bbaf069 | 1681 | /* Lock it down */ |
fba4ed03 SG |
1682 | local_irq_save(flags); |
1683 | lock_tx_qs(priv); | |
1684 | lock_rx_qs(priv); | |
0bbaf069 | 1685 | |
0bbaf069 | 1686 | gfar_halt(dev); |
1da177e4 | 1687 | |
fba4ed03 SG |
1688 | unlock_rx_qs(priv); |
1689 | unlock_tx_qs(priv); | |
1690 | local_irq_restore(flags); | |
1da177e4 LT |
1691 | |
1692 | /* Free the IRQs */ | |
b31a1d8b | 1693 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1694 | for (i = 0; i < priv->num_grps; i++) |
1695 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1696 | } else { |
46ceb60c | 1697 | for (i = 0; i < priv->num_grps; i++) |
ee873fda | 1698 | free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, |
bc4598bc | 1699 | &priv->gfargrp[i]); |
1da177e4 LT |
1700 | } |
1701 | ||
1702 | free_skb_resources(priv); | |
1da177e4 LT |
1703 | } |
1704 | ||
fba4ed03 | 1705 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1706 | { |
1da177e4 | 1707 | struct txbd8 *txbdp; |
fba4ed03 | 1708 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1709 | int i, j; |
1da177e4 | 1710 | |
a12f801d | 1711 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1712 | |
a12f801d SG |
1713 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1714 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1715 | continue; |
1da177e4 | 1716 | |
369ec162 | 1717 | dma_unmap_single(priv->dev, txbdp->bufPtr, |
bc4598bc | 1718 | txbdp->length, DMA_TO_DEVICE); |
4669bc90 | 1719 | txbdp->lstatus = 0; |
fba4ed03 | 1720 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
bc4598bc | 1721 | j++) { |
4669bc90 | 1722 | txbdp++; |
369ec162 | 1723 | dma_unmap_page(priv->dev, txbdp->bufPtr, |
bc4598bc | 1724 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1725 | } |
ad5da7ab | 1726 | txbdp++; |
a12f801d SG |
1727 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1728 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1729 | } |
a12f801d | 1730 | kfree(tx_queue->tx_skbuff); |
1eb8f7a7 | 1731 | tx_queue->tx_skbuff = NULL; |
fba4ed03 | 1732 | } |
1da177e4 | 1733 | |
fba4ed03 SG |
1734 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1735 | { | |
1736 | struct rxbd8 *rxbdp; | |
1737 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1738 | int i; | |
1da177e4 | 1739 | |
fba4ed03 | 1740 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1741 | |
a12f801d SG |
1742 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1743 | if (rx_queue->rx_skbuff[i]) { | |
369ec162 CM |
1744 | dma_unmap_single(priv->dev, rxbdp->bufPtr, |
1745 | priv->rx_buffer_size, | |
bc4598bc | 1746 | DMA_FROM_DEVICE); |
a12f801d SG |
1747 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1748 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1749 | } |
e69edd21 AV |
1750 | rxbdp->lstatus = 0; |
1751 | rxbdp->bufPtr = 0; | |
1752 | rxbdp++; | |
1da177e4 | 1753 | } |
a12f801d | 1754 | kfree(rx_queue->rx_skbuff); |
1eb8f7a7 | 1755 | rx_queue->rx_skbuff = NULL; |
fba4ed03 | 1756 | } |
e69edd21 | 1757 | |
fba4ed03 | 1758 | /* If there are any tx skbs or rx skbs still around, free them. |
0977f817 JC |
1759 | * Then free tx_skbuff and rx_skbuff |
1760 | */ | |
fba4ed03 SG |
1761 | static void free_skb_resources(struct gfar_private *priv) |
1762 | { | |
1763 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1764 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1765 | int i; | |
1766 | ||
1767 | /* Go through all the buffer descriptors and free their data buffers */ | |
1768 | for (i = 0; i < priv->num_tx_queues; i++) { | |
d8a0f1b0 | 1769 | struct netdev_queue *txq; |
bc4598bc | 1770 | |
fba4ed03 | 1771 | tx_queue = priv->tx_queue[i]; |
d8a0f1b0 | 1772 | txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); |
bc4598bc | 1773 | if (tx_queue->tx_skbuff) |
fba4ed03 | 1774 | free_skb_tx_queue(tx_queue); |
d8a0f1b0 | 1775 | netdev_tx_reset_queue(txq); |
fba4ed03 SG |
1776 | } |
1777 | ||
1778 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1779 | rx_queue = priv->rx_queue[i]; | |
bc4598bc | 1780 | if (rx_queue->rx_skbuff) |
fba4ed03 SG |
1781 | free_skb_rx_queue(rx_queue); |
1782 | } | |
1783 | ||
369ec162 | 1784 | dma_free_coherent(priv->dev, |
bc4598bc JC |
1785 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
1786 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1787 | priv->tx_queue[0]->tx_bd_base, | |
1788 | priv->tx_queue[0]->tx_bd_dma_base); | |
1da177e4 LT |
1789 | } |
1790 | ||
0bbaf069 KG |
1791 | void gfar_start(struct net_device *dev) |
1792 | { | |
1793 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1794 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1795 | u32 tempval; |
46ceb60c | 1796 | int i = 0; |
0bbaf069 KG |
1797 | |
1798 | /* Enable Rx and Tx in MACCFG1 */ | |
1799 | tempval = gfar_read(®s->maccfg1); | |
1800 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1801 | gfar_write(®s->maccfg1, tempval); | |
1802 | ||
1803 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1804 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1805 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1806 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1807 | |
0bbaf069 | 1808 | /* Make sure we aren't stopped */ |
f4983704 | 1809 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1810 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1811 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1812 | |
46ceb60c SG |
1813 | for (i = 0; i < priv->num_grps; i++) { |
1814 | regs = priv->gfargrp[i].regs; | |
1815 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1816 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1817 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
1818 | /* Unmask the interrupts we look for */ | |
1819 | gfar_write(®s->imask, IMASK_DEFAULT); | |
1820 | } | |
12dea57b | 1821 | |
1ae5dc34 | 1822 | dev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1823 | } |
1824 | ||
46ceb60c | 1825 | void gfar_configure_coalescing(struct gfar_private *priv, |
bc4598bc | 1826 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1827 | { |
46ceb60c | 1828 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1829 | u32 __iomem *baddr; |
46ceb60c | 1830 | int i = 0; |
1da177e4 | 1831 | |
46ceb60c SG |
1832 | /* Backward compatible case ---- even if we enable |
1833 | * multiple queues, there's only single reg to program | |
1834 | */ | |
1835 | gfar_write(®s->txic, 0); | |
bc4598bc | 1836 | if (likely(priv->tx_queue[0]->txcoalescing)) |
46ceb60c | 1837 | gfar_write(®s->txic, priv->tx_queue[0]->txic); |
1da177e4 | 1838 | |
46ceb60c | 1839 | gfar_write(®s->rxic, 0); |
bc4598bc | 1840 | if (unlikely(priv->rx_queue[0]->rxcoalescing)) |
46ceb60c | 1841 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); |
815b97c6 | 1842 | |
46ceb60c SG |
1843 | if (priv->mode == MQ_MG_MODE) { |
1844 | baddr = ®s->txic0; | |
984b3f57 | 1845 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
9740e001 CM |
1846 | gfar_write(baddr + i, 0); |
1847 | if (likely(priv->tx_queue[i]->txcoalescing)) | |
46ceb60c | 1848 | gfar_write(baddr + i, priv->tx_queue[i]->txic); |
46ceb60c SG |
1849 | } |
1850 | ||
1851 | baddr = ®s->rxic0; | |
984b3f57 | 1852 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
9740e001 CM |
1853 | gfar_write(baddr + i, 0); |
1854 | if (likely(priv->rx_queue[i]->rxcoalescing)) | |
46ceb60c | 1855 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); |
46ceb60c SG |
1856 | } |
1857 | } | |
1858 | } | |
1859 | ||
1860 | static int register_grp_irqs(struct gfar_priv_grp *grp) | |
1861 | { | |
1862 | struct gfar_private *priv = grp->priv; | |
1863 | struct net_device *dev = priv->ndev; | |
1864 | int err; | |
1da177e4 | 1865 | |
1da177e4 | 1866 | /* If the device has multiple interrupts, register for |
0977f817 JC |
1867 | * them. Otherwise, only register for the one |
1868 | */ | |
b31a1d8b | 1869 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1870 | /* Install our interrupt handlers for Error, |
0977f817 JC |
1871 | * Transmit, and Receive |
1872 | */ | |
ee873fda CM |
1873 | err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, |
1874 | gfar_irq(grp, ER)->name, grp); | |
1875 | if (err < 0) { | |
59deab26 | 1876 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1877 | gfar_irq(grp, ER)->irq); |
46ceb60c | 1878 | |
2145f1af | 1879 | goto err_irq_fail; |
1da177e4 | 1880 | } |
ee873fda CM |
1881 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, |
1882 | gfar_irq(grp, TX)->name, grp); | |
1883 | if (err < 0) { | |
59deab26 | 1884 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1885 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1886 | goto tx_irq_fail; |
1887 | } | |
ee873fda CM |
1888 | err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, |
1889 | gfar_irq(grp, RX)->name, grp); | |
1890 | if (err < 0) { | |
59deab26 | 1891 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1892 | gfar_irq(grp, RX)->irq); |
1da177e4 LT |
1893 | goto rx_irq_fail; |
1894 | } | |
1895 | } else { | |
ee873fda CM |
1896 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, |
1897 | gfar_irq(grp, TX)->name, grp); | |
1898 | if (err < 0) { | |
59deab26 | 1899 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1900 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1901 | goto err_irq_fail; |
1902 | } | |
1903 | } | |
1904 | ||
46ceb60c SG |
1905 | return 0; |
1906 | ||
1907 | rx_irq_fail: | |
ee873fda | 1908 | free_irq(gfar_irq(grp, TX)->irq, grp); |
46ceb60c | 1909 | tx_irq_fail: |
ee873fda | 1910 | free_irq(gfar_irq(grp, ER)->irq, grp); |
46ceb60c SG |
1911 | err_irq_fail: |
1912 | return err; | |
1913 | ||
1914 | } | |
1915 | ||
1916 | /* Bring the controller up and running */ | |
1917 | int startup_gfar(struct net_device *ndev) | |
1918 | { | |
1919 | struct gfar_private *priv = netdev_priv(ndev); | |
1920 | struct gfar __iomem *regs = NULL; | |
1921 | int err, i, j; | |
1922 | ||
1923 | for (i = 0; i < priv->num_grps; i++) { | |
1924 | regs= priv->gfargrp[i].regs; | |
1925 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1926 | } | |
1927 | ||
1928 | regs= priv->gfargrp[0].regs; | |
1929 | err = gfar_alloc_skb_resources(ndev); | |
1930 | if (err) | |
1931 | return err; | |
1932 | ||
1933 | gfar_init_mac(ndev); | |
1934 | ||
1935 | for (i = 0; i < priv->num_grps; i++) { | |
1936 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1937 | if (err) { | |
1938 | for (j = 0; j < i; j++) | |
1939 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1940 | goto irq_fail; |
46ceb60c SG |
1941 | } |
1942 | } | |
1943 | ||
7f7f5316 | 1944 | /* Start the controller */ |
ccc05c6e | 1945 | gfar_start(ndev); |
1da177e4 | 1946 | |
826aa4a0 AV |
1947 | phy_start(priv->phydev); |
1948 | ||
46ceb60c SG |
1949 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
1950 | ||
1da177e4 LT |
1951 | return 0; |
1952 | ||
46ceb60c | 1953 | irq_fail: |
e69edd21 | 1954 | free_skb_resources(priv); |
1da177e4 LT |
1955 | return err; |
1956 | } | |
1957 | ||
0977f817 JC |
1958 | /* Called when something needs to use the ethernet device |
1959 | * Returns 0 for success. | |
1960 | */ | |
1da177e4 LT |
1961 | static int gfar_enet_open(struct net_device *dev) |
1962 | { | |
94e8cc35 | 1963 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1964 | int err; |
1965 | ||
46ceb60c | 1966 | enable_napi(priv); |
bea3348e | 1967 | |
1da177e4 LT |
1968 | /* Initialize a bunch of registers */ |
1969 | init_registers(dev); | |
1970 | ||
1971 | gfar_set_mac_address(dev); | |
1972 | ||
1973 | err = init_phy(dev); | |
1974 | ||
a12f801d | 1975 | if (err) { |
46ceb60c | 1976 | disable_napi(priv); |
1da177e4 | 1977 | return err; |
bea3348e | 1978 | } |
1da177e4 LT |
1979 | |
1980 | err = startup_gfar(dev); | |
db0e8e3f | 1981 | if (err) { |
46ceb60c | 1982 | disable_napi(priv); |
db0e8e3f AV |
1983 | return err; |
1984 | } | |
1da177e4 | 1985 | |
fba4ed03 | 1986 | netif_tx_start_all_queues(dev); |
1da177e4 | 1987 | |
2884e5cc AV |
1988 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1989 | ||
1da177e4 LT |
1990 | return err; |
1991 | } | |
1992 | ||
54dc79fe | 1993 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1994 | { |
54dc79fe | 1995 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1996 | |
1997 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1998 | |
0bbaf069 KG |
1999 | return fcb; |
2000 | } | |
2001 | ||
9c4886e5 | 2002 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, |
bc4598bc | 2003 | int fcb_length) |
0bbaf069 | 2004 | { |
0bbaf069 KG |
2005 | /* If we're here, it's a IP packet with a TCP or UDP |
2006 | * payload. We set it to checksum, using a pseudo-header | |
2007 | * we provide | |
2008 | */ | |
3a2e16c8 | 2009 | u8 flags = TXFCB_DEFAULT; |
0bbaf069 | 2010 | |
0977f817 JC |
2011 | /* Tell the controller what the protocol is |
2012 | * And provide the already calculated phcs | |
2013 | */ | |
eddc9ec5 | 2014 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 2015 | flags |= TXFCB_UDP; |
4bedb452 | 2016 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 2017 | } else |
8da32de5 | 2018 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
2019 | |
2020 | /* l3os is the distance between the start of the | |
2021 | * frame (skb->data) and the start of the IP hdr. | |
2022 | * l4os is the distance between the start of the | |
0977f817 JC |
2023 | * l3 hdr and the l4 hdr |
2024 | */ | |
9c4886e5 | 2025 | fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); |
cfe1fc77 | 2026 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 2027 | |
7f7f5316 | 2028 | fcb->flags = flags; |
0bbaf069 KG |
2029 | } |
2030 | ||
7f7f5316 | 2031 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 2032 | { |
7f7f5316 | 2033 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2034 | fcb->vlctl = vlan_tx_tag_get(skb); |
2035 | } | |
2036 | ||
4669bc90 | 2037 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
bc4598bc | 2038 | struct txbd8 *base, int ring_size) |
4669bc90 DH |
2039 | { |
2040 | struct txbd8 *new_bd = bdp + stride; | |
2041 | ||
2042 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2043 | } | |
2044 | ||
2045 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
bc4598bc | 2046 | int ring_size) |
4669bc90 DH |
2047 | { |
2048 | return skip_txbd(bdp, 1, base, ring_size); | |
2049 | } | |
2050 | ||
0977f817 JC |
2051 | /* This is called by the kernel when a frame is ready for transmission. |
2052 | * It is pointed to by the dev->hard_start_xmit function pointer | |
2053 | */ | |
1da177e4 LT |
2054 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2055 | { | |
2056 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2057 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2058 | struct netdev_queue *txq; |
f4983704 | 2059 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2060 | struct txfcb *fcb = NULL; |
f0ee7acf | 2061 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2062 | u32 lstatus; |
f0ee7acf | 2063 | int i, rq = 0, do_tstamp = 0; |
4669bc90 | 2064 | u32 bufaddr; |
fef6108d | 2065 | unsigned long flags; |
9c4886e5 | 2066 | unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN; |
fba4ed03 | 2067 | |
0977f817 | 2068 | /* TOE=1 frames larger than 2500 bytes may see excess delays |
deb90eac AV |
2069 | * before start of transmission. |
2070 | */ | |
2071 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) && | |
bc4598bc JC |
2072 | skb->ip_summed == CHECKSUM_PARTIAL && |
2073 | skb->len > 2500)) { | |
deb90eac AV |
2074 | int ret; |
2075 | ||
2076 | ret = skb_checksum_help(skb); | |
2077 | if (ret) | |
2078 | return ret; | |
2079 | } | |
2080 | ||
fba4ed03 SG |
2081 | rq = skb->queue_mapping; |
2082 | tx_queue = priv->tx_queue[rq]; | |
2083 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2084 | base = tx_queue->tx_bd_base; |
46ceb60c | 2085 | regs = tx_queue->grp->regs; |
f0ee7acf MR |
2086 | |
2087 | /* check if time stamp should be generated */ | |
2244d07b | 2088 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
bc4598bc | 2089 | priv->hwts_tx_en)) { |
f0ee7acf | 2090 | do_tstamp = 1; |
9c4886e5 MR |
2091 | fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
2092 | } | |
4669bc90 | 2093 | |
5b28beaf LY |
2094 | /* make space for additional header when fcb is needed */ |
2095 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
bc4598bc JC |
2096 | vlan_tx_tag_present(skb) || |
2097 | unlikely(do_tstamp)) && | |
2098 | (skb_headroom(skb) < fcb_length)) { | |
54dc79fe SH |
2099 | struct sk_buff *skb_new; |
2100 | ||
9c4886e5 | 2101 | skb_new = skb_realloc_headroom(skb, fcb_length); |
54dc79fe SH |
2102 | if (!skb_new) { |
2103 | dev->stats.tx_errors++; | |
bd14ba84 | 2104 | kfree_skb(skb); |
54dc79fe SH |
2105 | return NETDEV_TX_OK; |
2106 | } | |
db83d136 | 2107 | |
313b037c ED |
2108 | if (skb->sk) |
2109 | skb_set_owner_w(skb_new, skb->sk); | |
2110 | consume_skb(skb); | |
54dc79fe SH |
2111 | skb = skb_new; |
2112 | } | |
2113 | ||
4669bc90 DH |
2114 | /* total number of fragments in the SKB */ |
2115 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2116 | ||
f0ee7acf MR |
2117 | /* calculate the required number of TxBDs for this skb */ |
2118 | if (unlikely(do_tstamp)) | |
2119 | nr_txbds = nr_frags + 2; | |
2120 | else | |
2121 | nr_txbds = nr_frags + 1; | |
2122 | ||
4669bc90 | 2123 | /* check if there is space to queue this packet */ |
f0ee7acf | 2124 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2125 | /* no space, stop the queue */ |
fba4ed03 | 2126 | netif_tx_stop_queue(txq); |
4669bc90 | 2127 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2128 | return NETDEV_TX_BUSY; |
2129 | } | |
1da177e4 LT |
2130 | |
2131 | /* Update transmit stats */ | |
1ac9ad13 ED |
2132 | tx_queue->stats.tx_bytes += skb->len; |
2133 | tx_queue->stats.tx_packets++; | |
1da177e4 | 2134 | |
a12f801d | 2135 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2136 | lstatus = txbdp->lstatus; |
2137 | ||
2138 | /* Time stamp insertion requires one additional TxBD */ | |
2139 | if (unlikely(do_tstamp)) | |
2140 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
bc4598bc | 2141 | tx_queue->tx_ring_size); |
1da177e4 | 2142 | |
4669bc90 | 2143 | if (nr_frags == 0) { |
f0ee7acf MR |
2144 | if (unlikely(do_tstamp)) |
2145 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
bc4598bc | 2146 | TXBD_INTERRUPT); |
f0ee7acf MR |
2147 | else |
2148 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2149 | } else { |
2150 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2151 | for (i = 0; i < nr_frags; i++) { | |
2152 | /* Point at the next BD, wrapping as needed */ | |
a12f801d | 2153 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2154 | |
2155 | length = skb_shinfo(skb)->frags[i].size; | |
2156 | ||
2157 | lstatus = txbdp->lstatus | length | | |
bc4598bc | 2158 | BD_LFLAG(TXBD_READY); |
4669bc90 DH |
2159 | |
2160 | /* Handle the last BD specially */ | |
2161 | if (i == nr_frags - 1) | |
2162 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2163 | |
369ec162 | 2164 | bufaddr = skb_frag_dma_map(priv->dev, |
2234a722 IC |
2165 | &skb_shinfo(skb)->frags[i], |
2166 | 0, | |
2167 | length, | |
2168 | DMA_TO_DEVICE); | |
4669bc90 DH |
2169 | |
2170 | /* set the TxBD length and buffer pointer */ | |
2171 | txbdp->bufPtr = bufaddr; | |
2172 | txbdp->lstatus = lstatus; | |
2173 | } | |
2174 | ||
2175 | lstatus = txbdp_start->lstatus; | |
2176 | } | |
1da177e4 | 2177 | |
9c4886e5 MR |
2178 | /* Add TxPAL between FCB and frame if required */ |
2179 | if (unlikely(do_tstamp)) { | |
2180 | skb_push(skb, GMAC_TXPAL_LEN); | |
2181 | memset(skb->data, 0, GMAC_TXPAL_LEN); | |
2182 | } | |
2183 | ||
0bbaf069 | 2184 | /* Set up checksumming */ |
12dea57b | 2185 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe | 2186 | fcb = gfar_add_fcb(skb); |
4363c2fd | 2187 | /* as specified by errata */ |
bc4598bc JC |
2188 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) && |
2189 | ((unsigned long)fcb % 0x20) > 0x18)) { | |
4363c2fd AD |
2190 | __skb_pull(skb, GMAC_FCB_LEN); |
2191 | skb_checksum_help(skb); | |
2192 | } else { | |
2193 | lstatus |= BD_LFLAG(TXBD_TOE); | |
9c4886e5 | 2194 | gfar_tx_checksum(skb, fcb, fcb_length); |
4363c2fd | 2195 | } |
0bbaf069 KG |
2196 | } |
2197 | ||
eab6d18d | 2198 | if (vlan_tx_tag_present(skb)) { |
54dc79fe SH |
2199 | if (unlikely(NULL == fcb)) { |
2200 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 2201 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 2202 | } |
54dc79fe SH |
2203 | |
2204 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
2205 | } |
2206 | ||
f0ee7acf MR |
2207 | /* Setup tx hardware time stamping if requested */ |
2208 | if (unlikely(do_tstamp)) { | |
2244d07b | 2209 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf MR |
2210 | if (fcb == NULL) |
2211 | fcb = gfar_add_fcb(skb); | |
2212 | fcb->ptp = 1; | |
2213 | lstatus |= BD_LFLAG(TXBD_TOE); | |
2214 | } | |
2215 | ||
369ec162 | 2216 | txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data, |
bc4598bc | 2217 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2218 | |
0977f817 | 2219 | /* If time stamping is requested one additional TxBD must be set up. The |
f0ee7acf MR |
2220 | * first TxBD points to the FCB and must have a data length of |
2221 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2222 | * the full frame length. | |
2223 | */ | |
2224 | if (unlikely(do_tstamp)) { | |
9c4886e5 | 2225 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length; |
f0ee7acf | 2226 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | |
bc4598bc | 2227 | (skb_headlen(skb) - fcb_length); |
f0ee7acf MR |
2228 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; |
2229 | } else { | |
2230 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2231 | } | |
1da177e4 | 2232 | |
d8a0f1b0 PG |
2233 | netdev_tx_sent_queue(txq, skb->len); |
2234 | ||
0977f817 | 2235 | /* We can work in parallel with gfar_clean_tx_ring(), except |
a3bc1f11 AV |
2236 | * when modifying num_txbdfree. Note that we didn't grab the lock |
2237 | * when we were reading the num_txbdfree and checking for available | |
2238 | * space, that's because outside of this function it can only grow, | |
2239 | * and once we've got needed space, it cannot suddenly disappear. | |
2240 | * | |
2241 | * The lock also protects us from gfar_error(), which can modify | |
2242 | * regs->tstat and thus retrigger the transfers, which is why we | |
2243 | * also must grab the lock before setting ready bit for the first | |
2244 | * to be transmitted BD. | |
2245 | */ | |
2246 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2247 | ||
0977f817 | 2248 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
3b6330ce SW |
2249 | * semantics (it requires synchronization between cacheable and |
2250 | * uncacheable mappings, which eieio doesn't provide and which we | |
2251 | * don't need), thus requiring a more expensive sync instruction. At | |
2252 | * some point, the set of architecture-independent barrier functions | |
2253 | * should be expanded to include weaker barriers. | |
2254 | */ | |
3b6330ce | 2255 | eieio(); |
7f7f5316 | 2256 | |
4669bc90 DH |
2257 | txbdp_start->lstatus = lstatus; |
2258 | ||
0eddba52 AV |
2259 | eieio(); /* force lstatus write before tx_skbuff */ |
2260 | ||
2261 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2262 | ||
4669bc90 | 2263 | /* Update the current skb pointer to the next entry we will use |
0977f817 JC |
2264 | * (wrapping if necessary) |
2265 | */ | |
a12f801d | 2266 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
bc4598bc | 2267 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); |
4669bc90 | 2268 | |
a12f801d | 2269 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2270 | |
2271 | /* reduce TxBD free count */ | |
f0ee7acf | 2272 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2273 | |
2274 | /* If the next BD still needs to be cleaned up, then the bds | |
0977f817 JC |
2275 | * are full. We need to tell the kernel to stop sending us stuff. |
2276 | */ | |
a12f801d | 2277 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2278 | netif_tx_stop_queue(txq); |
1da177e4 | 2279 | |
09f75cd7 | 2280 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2281 | } |
2282 | ||
1da177e4 | 2283 | /* Tell the DMA to go go go */ |
fba4ed03 | 2284 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2285 | |
2286 | /* Unlock priv */ | |
a12f801d | 2287 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2288 | |
54dc79fe | 2289 | return NETDEV_TX_OK; |
1da177e4 LT |
2290 | } |
2291 | ||
2292 | /* Stops the kernel queue, and halts the controller */ | |
2293 | static int gfar_close(struct net_device *dev) | |
2294 | { | |
2295 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2296 | |
46ceb60c | 2297 | disable_napi(priv); |
bea3348e | 2298 | |
ab939905 | 2299 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2300 | stop_gfar(dev); |
2301 | ||
bb40dcbb AF |
2302 | /* Disconnect from the PHY */ |
2303 | phy_disconnect(priv->phydev); | |
2304 | priv->phydev = NULL; | |
1da177e4 | 2305 | |
fba4ed03 | 2306 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2307 | |
2308 | return 0; | |
2309 | } | |
2310 | ||
1da177e4 | 2311 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2312 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2313 | { |
7f7f5316 | 2314 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2315 | |
2316 | return 0; | |
2317 | } | |
2318 | ||
f3dc1586 SP |
2319 | /* Check if rx parser should be activated */ |
2320 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2321 | { | |
2322 | struct gfar __iomem *regs; | |
2323 | u32 tempval; | |
2324 | ||
2325 | regs = priv->gfargrp[0].regs; | |
2326 | ||
2327 | tempval = gfar_read(®s->rctrl); | |
2328 | /* If parse is no longer required, then disable parser */ | |
2329 | if (tempval & RCTRL_REQ_PARSER) | |
2330 | tempval |= RCTRL_PRSDEP_INIT; | |
2331 | else | |
2332 | tempval &= ~RCTRL_PRSDEP_INIT; | |
2333 | gfar_write(®s->rctrl, tempval); | |
2334 | } | |
2335 | ||
0bbaf069 | 2336 | /* Enables and disables VLAN insertion/extraction */ |
c8f44aff | 2337 | void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) |
0bbaf069 KG |
2338 | { |
2339 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2340 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2341 | unsigned long flags; |
2342 | u32 tempval; | |
2343 | ||
46ceb60c | 2344 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2345 | local_irq_save(flags); |
2346 | lock_rx_qs(priv); | |
0bbaf069 | 2347 | |
87c288c6 | 2348 | if (features & NETIF_F_HW_VLAN_TX) { |
0bbaf069 | 2349 | /* Enable VLAN tag insertion */ |
f4983704 | 2350 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2351 | tempval |= TCTRL_VLINS; |
f4983704 | 2352 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2353 | } else { |
2354 | /* Disable VLAN tag insertion */ | |
f4983704 | 2355 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2356 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2357 | gfar_write(®s->tctrl, tempval); |
87c288c6 | 2358 | } |
0bbaf069 | 2359 | |
87c288c6 JP |
2360 | if (features & NETIF_F_HW_VLAN_RX) { |
2361 | /* Enable VLAN tag extraction */ | |
2362 | tempval = gfar_read(®s->rctrl); | |
2363 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); | |
2364 | gfar_write(®s->rctrl, tempval); | |
2365 | } else { | |
0bbaf069 | 2366 | /* Disable VLAN tag extraction */ |
f4983704 | 2367 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2368 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2369 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2370 | |
2371 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2372 | } |
2373 | ||
77ecaf2d DH |
2374 | gfar_change_mtu(dev, dev->mtu); |
2375 | ||
fba4ed03 SG |
2376 | unlock_rx_qs(priv); |
2377 | local_irq_restore(flags); | |
0bbaf069 KG |
2378 | } |
2379 | ||
1da177e4 LT |
2380 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2381 | { | |
2382 | int tempsize, tempval; | |
2383 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2384 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2385 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2386 | int frame_size = new_mtu + ETH_HLEN; |
2387 | ||
1da177e4 | 2388 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
59deab26 | 2389 | netif_err(priv, drv, dev, "Invalid MTU setting\n"); |
1da177e4 LT |
2390 | return -EINVAL; |
2391 | } | |
2392 | ||
77ecaf2d DH |
2393 | if (gfar_uses_fcb(priv)) |
2394 | frame_size += GMAC_FCB_LEN; | |
2395 | ||
2396 | frame_size += priv->padding; | |
2397 | ||
bc4598bc JC |
2398 | tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + |
2399 | INCREMENTAL_BUFFER_SIZE; | |
1da177e4 LT |
2400 | |
2401 | /* Only stop and start the controller if it isn't already | |
0977f817 JC |
2402 | * stopped, and we changed something |
2403 | */ | |
1da177e4 LT |
2404 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2405 | stop_gfar(dev); | |
2406 | ||
2407 | priv->rx_buffer_size = tempsize; | |
2408 | ||
2409 | dev->mtu = new_mtu; | |
2410 | ||
f4983704 SG |
2411 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2412 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2413 | |
2414 | /* If the mtu is larger than the max size for standard | |
2415 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
0977f817 JC |
2416 | * to allow huge frames, and to check the length |
2417 | */ | |
f4983704 | 2418 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2419 | |
7d350977 | 2420 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
bc4598bc | 2421 | gfar_has_errata(priv, GFAR_ERRATA_74)) |
1da177e4 LT |
2422 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2423 | else | |
2424 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2425 | ||
f4983704 | 2426 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2427 | |
2428 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2429 | startup_gfar(dev); | |
2430 | ||
2431 | return 0; | |
2432 | } | |
2433 | ||
ab939905 | 2434 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2435 | * transmitted after a set amount of time. |
2436 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2437 | * starting over will fix the problem. |
2438 | */ | |
2439 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2440 | { |
ab939905 | 2441 | struct gfar_private *priv = container_of(work, struct gfar_private, |
bc4598bc | 2442 | reset_task); |
4826857f | 2443 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2444 | |
2445 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2446 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2447 | stop_gfar(dev); |
2448 | startup_gfar(dev); | |
fba4ed03 | 2449 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2450 | } |
2451 | ||
263ba320 | 2452 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2453 | } |
2454 | ||
ab939905 SS |
2455 | static void gfar_timeout(struct net_device *dev) |
2456 | { | |
2457 | struct gfar_private *priv = netdev_priv(dev); | |
2458 | ||
2459 | dev->stats.tx_errors++; | |
2460 | schedule_work(&priv->reset_task); | |
2461 | } | |
2462 | ||
acbc0f03 EL |
2463 | static void gfar_align_skb(struct sk_buff *skb) |
2464 | { | |
2465 | /* We need the data buffer to be aligned properly. We will reserve | |
2466 | * as many bytes as needed to align the data properly | |
2467 | */ | |
2468 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
bc4598bc | 2469 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); |
acbc0f03 EL |
2470 | } |
2471 | ||
1da177e4 | 2472 | /* Interrupt Handler for Transmit complete */ |
a12f801d | 2473 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2474 | { |
a12f801d | 2475 | struct net_device *dev = tx_queue->dev; |
d8a0f1b0 | 2476 | struct netdev_queue *txq; |
d080cd63 | 2477 | struct gfar_private *priv = netdev_priv(dev); |
a12f801d | 2478 | struct gfar_priv_rx_q *rx_queue = NULL; |
f0ee7acf | 2479 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2480 | struct txbd8 *lbdp = NULL; |
a12f801d | 2481 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2482 | struct sk_buff *skb; |
2483 | int skb_dirtytx; | |
a12f801d | 2484 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2485 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2486 | int i; |
d080cd63 | 2487 | int howmany = 0; |
d8a0f1b0 PG |
2488 | int tqi = tx_queue->qindex; |
2489 | unsigned int bytes_sent = 0; | |
4669bc90 | 2490 | u32 lstatus; |
f0ee7acf | 2491 | size_t buflen; |
1da177e4 | 2492 | |
d8a0f1b0 PG |
2493 | rx_queue = priv->rx_queue[tqi]; |
2494 | txq = netdev_get_tx_queue(dev, tqi); | |
a12f801d SG |
2495 | bdp = tx_queue->dirty_tx; |
2496 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2497 | |
a12f801d | 2498 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2499 | unsigned long flags; |
2500 | ||
4669bc90 | 2501 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf | 2502 | |
0977f817 | 2503 | /* When time stamping, one additional TxBD must be freed. |
f0ee7acf MR |
2504 | * Also, we need to dma_unmap_single() the TxPAL. |
2505 | */ | |
2244d07b | 2506 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2507 | nr_txbds = frags + 2; |
2508 | else | |
2509 | nr_txbds = frags + 1; | |
2510 | ||
2511 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2512 | |
4669bc90 | 2513 | lstatus = lbdp->lstatus; |
1da177e4 | 2514 | |
4669bc90 DH |
2515 | /* Only clean completed frames */ |
2516 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
bc4598bc | 2517 | (lstatus & BD_LENGTH_MASK)) |
4669bc90 DH |
2518 | break; |
2519 | ||
2244d07b | 2520 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf | 2521 | next = next_txbd(bdp, base, tx_ring_size); |
9c4886e5 | 2522 | buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
f0ee7acf MR |
2523 | } else |
2524 | buflen = bdp->length; | |
2525 | ||
369ec162 | 2526 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2527 | buflen, DMA_TO_DEVICE); |
f0ee7acf | 2528 | |
2244d07b | 2529 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2530 | struct skb_shared_hwtstamps shhwtstamps; |
2531 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
bc4598bc | 2532 | |
f0ee7acf MR |
2533 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
2534 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
9c4886e5 | 2535 | skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); |
f0ee7acf MR |
2536 | skb_tstamp_tx(skb, &shhwtstamps); |
2537 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2538 | bdp = next; | |
2539 | } | |
81183059 | 2540 | |
4669bc90 DH |
2541 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2542 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2543 | |
4669bc90 | 2544 | for (i = 0; i < frags; i++) { |
369ec162 | 2545 | dma_unmap_page(priv->dev, bdp->bufPtr, |
bc4598bc | 2546 | bdp->length, DMA_TO_DEVICE); |
4669bc90 DH |
2547 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2548 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2549 | } | |
1da177e4 | 2550 | |
d8a0f1b0 PG |
2551 | bytes_sent += skb->len; |
2552 | ||
acb600de | 2553 | dev_kfree_skb_any(skb); |
0fd56bb5 | 2554 | |
a12f801d | 2555 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2556 | |
4669bc90 | 2557 | skb_dirtytx = (skb_dirtytx + 1) & |
bc4598bc | 2558 | TX_RING_MOD_MASK(tx_ring_size); |
4669bc90 DH |
2559 | |
2560 | howmany++; | |
a3bc1f11 | 2561 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2562 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2563 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2564 | } |
1da177e4 | 2565 | |
4669bc90 | 2566 | /* If we freed a buffer, we can restart transmission, if necessary */ |
5407b14c | 2567 | if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) |
d8a0f1b0 | 2568 | netif_wake_subqueue(dev, tqi); |
1da177e4 | 2569 | |
4669bc90 | 2570 | /* Update dirty indicators */ |
a12f801d SG |
2571 | tx_queue->skb_dirtytx = skb_dirtytx; |
2572 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2573 | |
d8a0f1b0 PG |
2574 | netdev_tx_completed_queue(txq, howmany, bytes_sent); |
2575 | ||
d080cd63 DH |
2576 | return howmany; |
2577 | } | |
2578 | ||
f4983704 | 2579 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2580 | { |
a6d0b91a AV |
2581 | unsigned long flags; |
2582 | ||
fba4ed03 SG |
2583 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2584 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2585 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2586 | __napi_schedule(&gfargrp->napi); |
8707bdd4 | 2587 | } else { |
0977f817 | 2588 | /* Clear IEVENT, so interrupts aren't called again |
8707bdd4 JP |
2589 | * because of the packets that have already arrived. |
2590 | */ | |
f4983704 | 2591 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2592 | } |
fba4ed03 | 2593 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2594 | |
8c7396ae | 2595 | } |
1da177e4 | 2596 | |
8c7396ae | 2597 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2598 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2599 | { |
f4983704 | 2600 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2601 | return IRQ_HANDLED; |
2602 | } | |
2603 | ||
a12f801d | 2604 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 2605 | struct sk_buff *skb) |
815b97c6 | 2606 | { |
a12f801d | 2607 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2608 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2609 | dma_addr_t buf; |
815b97c6 | 2610 | |
369ec162 | 2611 | buf = dma_map_single(priv->dev, skb->data, |
8a102fe0 | 2612 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
a12f801d | 2613 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2614 | } |
2615 | ||
2281a0f3 | 2616 | static struct sk_buff *gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2617 | { |
2618 | struct gfar_private *priv = netdev_priv(dev); | |
acb600de | 2619 | struct sk_buff *skb; |
1da177e4 | 2620 | |
acbc0f03 | 2621 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2622 | if (!skb) |
1da177e4 LT |
2623 | return NULL; |
2624 | ||
acbc0f03 | 2625 | gfar_align_skb(skb); |
7f7f5316 | 2626 | |
acbc0f03 EL |
2627 | return skb; |
2628 | } | |
2629 | ||
2281a0f3 | 2630 | struct sk_buff *gfar_new_skb(struct net_device *dev) |
acbc0f03 | 2631 | { |
acb600de | 2632 | return gfar_alloc_skb(dev); |
1da177e4 LT |
2633 | } |
2634 | ||
298e1a9e | 2635 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2636 | { |
298e1a9e | 2637 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2638 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2639 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2640 | ||
0977f817 | 2641 | /* If the packet was truncated, none of the other errors matter */ |
1da177e4 LT |
2642 | if (status & RXBD_TRUNCATED) { |
2643 | stats->rx_length_errors++; | |
2644 | ||
212079df | 2645 | atomic64_inc(&estats->rx_trunc); |
1da177e4 LT |
2646 | |
2647 | return; | |
2648 | } | |
2649 | /* Count the errors, if there were any */ | |
2650 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2651 | stats->rx_length_errors++; | |
2652 | ||
2653 | if (status & RXBD_LARGE) | |
212079df | 2654 | atomic64_inc(&estats->rx_large); |
1da177e4 | 2655 | else |
212079df | 2656 | atomic64_inc(&estats->rx_short); |
1da177e4 LT |
2657 | } |
2658 | if (status & RXBD_NONOCTET) { | |
2659 | stats->rx_frame_errors++; | |
212079df | 2660 | atomic64_inc(&estats->rx_nonoctet); |
1da177e4 LT |
2661 | } |
2662 | if (status & RXBD_CRCERR) { | |
212079df | 2663 | atomic64_inc(&estats->rx_crcerr); |
1da177e4 LT |
2664 | stats->rx_crc_errors++; |
2665 | } | |
2666 | if (status & RXBD_OVERRUN) { | |
212079df | 2667 | atomic64_inc(&estats->rx_overrun); |
1da177e4 LT |
2668 | stats->rx_crc_errors++; |
2669 | } | |
2670 | } | |
2671 | ||
f4983704 | 2672 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2673 | { |
f4983704 | 2674 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2675 | return IRQ_HANDLED; |
2676 | } | |
2677 | ||
0bbaf069 KG |
2678 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2679 | { | |
2680 | /* If valid headers were found, and valid sums | |
2681 | * were verified, then we tell the kernel that no | |
0977f817 JC |
2682 | * checksumming is necessary. Otherwise, it is [FIXME] |
2683 | */ | |
7f7f5316 | 2684 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2685 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2686 | else | |
bc8acf2c | 2687 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2688 | } |
2689 | ||
2690 | ||
0977f817 | 2691 | /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ |
61db26c6 CM |
2692 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
2693 | int amount_pull, struct napi_struct *napi) | |
1da177e4 LT |
2694 | { |
2695 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2696 | struct rxfcb *fcb = NULL; |
1da177e4 | 2697 | |
cd754a57 | 2698 | gro_result_t ret; |
1da177e4 | 2699 | |
2c2db48a DH |
2700 | /* fcb is at the beginning if exists */ |
2701 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2702 | |
0977f817 JC |
2703 | /* Remove the FCB from the skb |
2704 | * Remove the padded bytes, if there are any | |
2705 | */ | |
f74dac08 SG |
2706 | if (amount_pull) { |
2707 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2708 | skb_pull(skb, amount_pull); |
f74dac08 | 2709 | } |
0bbaf069 | 2710 | |
cc772ab7 MR |
2711 | /* Get receive timestamp from the skb */ |
2712 | if (priv->hwts_rx_en) { | |
2713 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2714 | u64 *ns = (u64 *) skb->data; | |
bc4598bc | 2715 | |
cc772ab7 MR |
2716 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2717 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2718 | } | |
2719 | ||
2720 | if (priv->padding) | |
2721 | skb_pull(skb, priv->padding); | |
2722 | ||
8b3afe95 | 2723 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2724 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2725 | |
2c2db48a DH |
2726 | /* Tell the skb what kind of packet this is */ |
2727 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2728 | |
0977f817 | 2729 | /* There's need to check for NETIF_F_HW_VLAN_RX here. |
32f7fd44 JP |
2730 | * Even if vlan rx accel is disabled, on some chips |
2731 | * RXFCB_VLN is pseudo randomly set. | |
2732 | */ | |
2733 | if (dev->features & NETIF_F_HW_VLAN_RX && | |
2734 | fcb->flags & RXFCB_VLN) | |
87c288c6 JP |
2735 | __vlan_hwaccel_put_tag(skb, fcb->vlctl); |
2736 | ||
2c2db48a | 2737 | /* Send the packet up the stack */ |
cd754a57 | 2738 | ret = napi_gro_receive(napi, skb); |
0bbaf069 | 2739 | |
bd9e89f2 | 2740 | if (unlikely(GRO_DROP == ret)) |
212079df | 2741 | atomic64_inc(&priv->extra_stats.kernel_dropped); |
1da177e4 LT |
2742 | } |
2743 | ||
2744 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
2281a0f3 JC |
2745 | * until the budget/quota has been reached. Returns the number |
2746 | * of frames handled | |
1da177e4 | 2747 | */ |
a12f801d | 2748 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2749 | { |
a12f801d | 2750 | struct net_device *dev = rx_queue->dev; |
31de198b | 2751 | struct rxbd8 *bdp, *base; |
1da177e4 | 2752 | struct sk_buff *skb; |
2c2db48a DH |
2753 | int pkt_len; |
2754 | int amount_pull; | |
1da177e4 LT |
2755 | int howmany = 0; |
2756 | struct gfar_private *priv = netdev_priv(dev); | |
2757 | ||
2758 | /* Get the first full descriptor */ | |
a12f801d SG |
2759 | bdp = rx_queue->cur_rx; |
2760 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2761 | |
cc772ab7 | 2762 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0); |
2c2db48a | 2763 | |
1da177e4 | 2764 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2765 | struct sk_buff *newskb; |
bc4598bc | 2766 | |
3b6330ce | 2767 | rmb(); |
815b97c6 AF |
2768 | |
2769 | /* Add another skb for the future */ | |
2770 | newskb = gfar_new_skb(dev); | |
2771 | ||
a12f801d | 2772 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2773 | |
369ec162 | 2774 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2775 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
81183059 | 2776 | |
63b88b90 | 2777 | if (unlikely(!(bdp->status & RXBD_ERR) && |
bc4598bc | 2778 | bdp->length > priv->rx_buffer_size)) |
63b88b90 AV |
2779 | bdp->status = RXBD_LARGE; |
2780 | ||
815b97c6 AF |
2781 | /* We drop the frame if we failed to allocate a new buffer */ |
2782 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
bc4598bc | 2783 | bdp->status & RXBD_ERR)) { |
815b97c6 AF |
2784 | count_errors(bdp->status, dev); |
2785 | ||
2786 | if (unlikely(!newskb)) | |
2787 | newskb = skb; | |
acbc0f03 | 2788 | else if (skb) |
acb600de | 2789 | dev_kfree_skb(skb); |
815b97c6 | 2790 | } else { |
1da177e4 | 2791 | /* Increment the number of packets */ |
a7f38041 | 2792 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2793 | howmany++; |
2794 | ||
2c2db48a DH |
2795 | if (likely(skb)) { |
2796 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2797 | /* Remove the FCS from the packet length */ | |
2798 | skb_put(skb, pkt_len); | |
a7f38041 | 2799 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2800 | skb_record_rx_queue(skb, rx_queue->qindex); |
cd754a57 | 2801 | gfar_process_frame(dev, skb, amount_pull, |
bc4598bc | 2802 | &rx_queue->grp->napi); |
2c2db48a DH |
2803 | |
2804 | } else { | |
59deab26 | 2805 | netif_warn(priv, rx_err, dev, "Missing skb!\n"); |
a7f38041 | 2806 | rx_queue->stats.rx_dropped++; |
212079df | 2807 | atomic64_inc(&priv->extra_stats.rx_skbmissing); |
2c2db48a | 2808 | } |
1da177e4 | 2809 | |
1da177e4 LT |
2810 | } |
2811 | ||
a12f801d | 2812 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2813 | |
815b97c6 | 2814 | /* Setup the new bdp */ |
a12f801d | 2815 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2816 | |
2817 | /* Update to the next pointer */ | |
a12f801d | 2818 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2819 | |
2820 | /* update to point at the next skb */ | |
bc4598bc JC |
2821 | rx_queue->skb_currx = (rx_queue->skb_currx + 1) & |
2822 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2823 | } |
2824 | ||
2825 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2826 | rx_queue->cur_rx = bdp; |
1da177e4 | 2827 | |
1da177e4 LT |
2828 | return howmany; |
2829 | } | |
2830 | ||
bea3348e | 2831 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2832 | { |
bc4598bc JC |
2833 | struct gfar_priv_grp *gfargrp = |
2834 | container_of(napi, struct gfar_priv_grp, napi); | |
fba4ed03 | 2835 | struct gfar_private *priv = gfargrp->priv; |
46ceb60c | 2836 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2837 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 SG |
2838 | struct gfar_priv_rx_q *rx_queue = NULL; |
2839 | int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0; | |
18294ad1 AV |
2840 | int tx_cleaned = 0, i, left_over_budget = budget; |
2841 | unsigned long serviced_queues = 0; | |
fba4ed03 | 2842 | int num_queues = 0; |
d080cd63 | 2843 | |
fba4ed03 SG |
2844 | num_queues = gfargrp->num_rx_queues; |
2845 | budget_per_queue = budget/num_queues; | |
2846 | ||
8c7396ae | 2847 | /* Clear IEVENT, so interrupts aren't called again |
0977f817 JC |
2848 | * because of the packets that have already arrived |
2849 | */ | |
f4983704 | 2850 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2851 | |
fba4ed03 | 2852 | while (num_queues && left_over_budget) { |
fba4ed03 SG |
2853 | budget_per_queue = left_over_budget/num_queues; |
2854 | left_over_budget = 0; | |
2855 | ||
984b3f57 | 2856 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
fba4ed03 SG |
2857 | if (test_bit(i, &serviced_queues)) |
2858 | continue; | |
2859 | rx_queue = priv->rx_queue[i]; | |
2860 | tx_queue = priv->tx_queue[rx_queue->qindex]; | |
2861 | ||
a3bc1f11 | 2862 | tx_cleaned += gfar_clean_tx_ring(tx_queue); |
bc4598bc JC |
2863 | rx_cleaned_per_queue = |
2864 | gfar_clean_rx_ring(rx_queue, budget_per_queue); | |
fba4ed03 | 2865 | rx_cleaned += rx_cleaned_per_queue; |
bc4598bc | 2866 | if (rx_cleaned_per_queue < budget_per_queue) { |
fba4ed03 | 2867 | left_over_budget = left_over_budget + |
bc4598bc JC |
2868 | (budget_per_queue - |
2869 | rx_cleaned_per_queue); | |
fba4ed03 SG |
2870 | set_bit(i, &serviced_queues); |
2871 | num_queues--; | |
2872 | } | |
2873 | } | |
2874 | } | |
1da177e4 | 2875 | |
42199884 AF |
2876 | if (tx_cleaned) |
2877 | return budget; | |
2878 | ||
2879 | if (rx_cleaned < budget) { | |
288379f0 | 2880 | napi_complete(napi); |
1da177e4 LT |
2881 | |
2882 | /* Clear the halt bit in RSTAT */ | |
fba4ed03 | 2883 | gfar_write(®s->rstat, gfargrp->rstat); |
1da177e4 | 2884 | |
f4983704 | 2885 | gfar_write(®s->imask, IMASK_DEFAULT); |
1da177e4 | 2886 | |
0977f817 JC |
2887 | /* If we are coalescing interrupts, update the timer |
2888 | * Otherwise, clear it | |
2889 | */ | |
bc4598bc JC |
2890 | gfar_configure_coalescing(priv, gfargrp->rx_bit_map, |
2891 | gfargrp->tx_bit_map); | |
1da177e4 LT |
2892 | } |
2893 | ||
42199884 | 2894 | return rx_cleaned; |
1da177e4 | 2895 | } |
1da177e4 | 2896 | |
f2d71c2d | 2897 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0977f817 | 2898 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
f2d71c2d VW |
2899 | * without having to re-enable interrupts. It's not called while |
2900 | * the interrupt routine is executing. | |
2901 | */ | |
2902 | static void gfar_netpoll(struct net_device *dev) | |
2903 | { | |
2904 | struct gfar_private *priv = netdev_priv(dev); | |
3a2e16c8 | 2905 | int i; |
f2d71c2d VW |
2906 | |
2907 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2908 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
2909 | for (i = 0; i < priv->num_grps; i++) { |
2910 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2911 | disable_irq(priv->gfargrp[i].interruptReceive); | |
2912 | disable_irq(priv->gfargrp[i].interruptError); | |
2913 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 2914 | &priv->gfargrp[i]); |
46ceb60c SG |
2915 | enable_irq(priv->gfargrp[i].interruptError); |
2916 | enable_irq(priv->gfargrp[i].interruptReceive); | |
2917 | enable_irq(priv->gfargrp[i].interruptTransmit); | |
2918 | } | |
f2d71c2d | 2919 | } else { |
46ceb60c SG |
2920 | for (i = 0; i < priv->num_grps; i++) { |
2921 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2922 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 2923 | &priv->gfargrp[i]); |
46ceb60c | 2924 | enable_irq(priv->gfargrp[i].interruptTransmit); |
43de004b | 2925 | } |
f2d71c2d VW |
2926 | } |
2927 | } | |
2928 | #endif | |
2929 | ||
1da177e4 | 2930 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 2931 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 2932 | { |
f4983704 | 2933 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
2934 | |
2935 | /* Save ievent for future reference */ | |
f4983704 | 2936 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 2937 | |
1da177e4 | 2938 | /* Check for reception */ |
538cc7ee | 2939 | if (events & IEVENT_RX_MASK) |
f4983704 | 2940 | gfar_receive(irq, grp_id); |
1da177e4 LT |
2941 | |
2942 | /* Check for transmit completion */ | |
538cc7ee | 2943 | if (events & IEVENT_TX_MASK) |
f4983704 | 2944 | gfar_transmit(irq, grp_id); |
1da177e4 | 2945 | |
538cc7ee SS |
2946 | /* Check for errors */ |
2947 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 2948 | gfar_error(irq, grp_id); |
1da177e4 LT |
2949 | |
2950 | return IRQ_HANDLED; | |
2951 | } | |
2952 | ||
1da177e4 LT |
2953 | /* Called every time the controller might need to be made |
2954 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2955 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2956 | * function converts those variables into the appropriate |
2957 | * register values, and can bring down the device if needed. | |
2958 | */ | |
2959 | static void adjust_link(struct net_device *dev) | |
2960 | { | |
2961 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2962 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
2963 | unsigned long flags; |
2964 | struct phy_device *phydev = priv->phydev; | |
2965 | int new_state = 0; | |
2966 | ||
fba4ed03 SG |
2967 | local_irq_save(flags); |
2968 | lock_tx_qs(priv); | |
2969 | ||
bb40dcbb AF |
2970 | if (phydev->link) { |
2971 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2972 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2973 | |
1da177e4 | 2974 | /* Now we make sure that we can be in full duplex mode. |
0977f817 JC |
2975 | * If not, we operate in half-duplex mode. |
2976 | */ | |
bb40dcbb AF |
2977 | if (phydev->duplex != priv->oldduplex) { |
2978 | new_state = 1; | |
2979 | if (!(phydev->duplex)) | |
1da177e4 | 2980 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2981 | else |
1da177e4 | 2982 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2983 | |
bb40dcbb | 2984 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2985 | } |
2986 | ||
bb40dcbb AF |
2987 | if (phydev->speed != priv->oldspeed) { |
2988 | new_state = 1; | |
2989 | switch (phydev->speed) { | |
1da177e4 | 2990 | case 1000: |
1da177e4 LT |
2991 | tempval = |
2992 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2993 | |
2994 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2995 | break; |
2996 | case 100: | |
2997 | case 10: | |
1da177e4 LT |
2998 | tempval = |
2999 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
3000 | |
3001 | /* Reduced mode distinguishes | |
0977f817 JC |
3002 | * between 10 and 100 |
3003 | */ | |
7f7f5316 AF |
3004 | if (phydev->speed == SPEED_100) |
3005 | ecntrl |= ECNTRL_R100; | |
3006 | else | |
3007 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3008 | break; |
3009 | default: | |
59deab26 JP |
3010 | netif_warn(priv, link, dev, |
3011 | "Ack! Speed (%d) is not 10/100/1000!\n", | |
3012 | phydev->speed); | |
1da177e4 LT |
3013 | break; |
3014 | } | |
3015 | ||
bb40dcbb | 3016 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3017 | } |
3018 | ||
bb40dcbb | 3019 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3020 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3021 | |
1da177e4 | 3022 | if (!priv->oldlink) { |
bb40dcbb | 3023 | new_state = 1; |
1da177e4 | 3024 | priv->oldlink = 1; |
1da177e4 | 3025 | } |
bb40dcbb AF |
3026 | } else if (priv->oldlink) { |
3027 | new_state = 1; | |
3028 | priv->oldlink = 0; | |
3029 | priv->oldspeed = 0; | |
3030 | priv->oldduplex = -1; | |
1da177e4 | 3031 | } |
1da177e4 | 3032 | |
bb40dcbb AF |
3033 | if (new_state && netif_msg_link(priv)) |
3034 | phy_print_status(phydev); | |
fba4ed03 SG |
3035 | unlock_tx_qs(priv); |
3036 | local_irq_restore(flags); | |
bb40dcbb | 3037 | } |
1da177e4 LT |
3038 | |
3039 | /* Update the hash table based on the current list of multicast | |
3040 | * addresses we subscribe to. Also, change the promiscuity of | |
3041 | * the device based on the flags (this function is called | |
0977f817 JC |
3042 | * whenever dev->flags is changed |
3043 | */ | |
1da177e4 LT |
3044 | static void gfar_set_multi(struct net_device *dev) |
3045 | { | |
22bedad3 | 3046 | struct netdev_hw_addr *ha; |
1da177e4 | 3047 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3048 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3049 | u32 tempval; |
3050 | ||
a12f801d | 3051 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3052 | /* Set RCTRL to PROM */ |
3053 | tempval = gfar_read(®s->rctrl); | |
3054 | tempval |= RCTRL_PROM; | |
3055 | gfar_write(®s->rctrl, tempval); | |
3056 | } else { | |
3057 | /* Set RCTRL to not PROM */ | |
3058 | tempval = gfar_read(®s->rctrl); | |
3059 | tempval &= ~(RCTRL_PROM); | |
3060 | gfar_write(®s->rctrl, tempval); | |
3061 | } | |
6aa20a22 | 3062 | |
a12f801d | 3063 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3064 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3065 | gfar_write(®s->igaddr0, 0xffffffff); |
3066 | gfar_write(®s->igaddr1, 0xffffffff); | |
3067 | gfar_write(®s->igaddr2, 0xffffffff); | |
3068 | gfar_write(®s->igaddr3, 0xffffffff); | |
3069 | gfar_write(®s->igaddr4, 0xffffffff); | |
3070 | gfar_write(®s->igaddr5, 0xffffffff); | |
3071 | gfar_write(®s->igaddr6, 0xffffffff); | |
3072 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3073 | gfar_write(®s->gaddr0, 0xffffffff); |
3074 | gfar_write(®s->gaddr1, 0xffffffff); | |
3075 | gfar_write(®s->gaddr2, 0xffffffff); | |
3076 | gfar_write(®s->gaddr3, 0xffffffff); | |
3077 | gfar_write(®s->gaddr4, 0xffffffff); | |
3078 | gfar_write(®s->gaddr5, 0xffffffff); | |
3079 | gfar_write(®s->gaddr6, 0xffffffff); | |
3080 | gfar_write(®s->gaddr7, 0xffffffff); | |
3081 | } else { | |
7f7f5316 AF |
3082 | int em_num; |
3083 | int idx; | |
3084 | ||
1da177e4 | 3085 | /* zero out the hash */ |
0bbaf069 KG |
3086 | gfar_write(®s->igaddr0, 0x0); |
3087 | gfar_write(®s->igaddr1, 0x0); | |
3088 | gfar_write(®s->igaddr2, 0x0); | |
3089 | gfar_write(®s->igaddr3, 0x0); | |
3090 | gfar_write(®s->igaddr4, 0x0); | |
3091 | gfar_write(®s->igaddr5, 0x0); | |
3092 | gfar_write(®s->igaddr6, 0x0); | |
3093 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3094 | gfar_write(®s->gaddr0, 0x0); |
3095 | gfar_write(®s->gaddr1, 0x0); | |
3096 | gfar_write(®s->gaddr2, 0x0); | |
3097 | gfar_write(®s->gaddr3, 0x0); | |
3098 | gfar_write(®s->gaddr4, 0x0); | |
3099 | gfar_write(®s->gaddr5, 0x0); | |
3100 | gfar_write(®s->gaddr6, 0x0); | |
3101 | gfar_write(®s->gaddr7, 0x0); | |
3102 | ||
7f7f5316 AF |
3103 | /* If we have extended hash tables, we need to |
3104 | * clear the exact match registers to prepare for | |
0977f817 JC |
3105 | * setting them |
3106 | */ | |
7f7f5316 AF |
3107 | if (priv->extended_hash) { |
3108 | em_num = GFAR_EM_NUM + 1; | |
3109 | gfar_clear_exact_match(dev); | |
3110 | idx = 1; | |
3111 | } else { | |
3112 | idx = 0; | |
3113 | em_num = 0; | |
3114 | } | |
3115 | ||
4cd24eaf | 3116 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3117 | return; |
3118 | ||
3119 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3120 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3121 | if (idx < em_num) { |
22bedad3 | 3122 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3123 | idx++; |
3124 | } else | |
22bedad3 | 3125 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3126 | } |
3127 | } | |
1da177e4 LT |
3128 | } |
3129 | ||
7f7f5316 AF |
3130 | |
3131 | /* Clears each of the exact match registers to zero, so they | |
0977f817 JC |
3132 | * don't interfere with normal reception |
3133 | */ | |
7f7f5316 AF |
3134 | static void gfar_clear_exact_match(struct net_device *dev) |
3135 | { | |
3136 | int idx; | |
6a3c910c | 3137 | static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 | 3138 | |
bc4598bc | 3139 | for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) |
b6bc7650 | 3140 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3141 | } |
3142 | ||
1da177e4 LT |
3143 | /* Set the appropriate hash bit for the given addr */ |
3144 | /* The algorithm works like so: | |
3145 | * 1) Take the Destination Address (ie the multicast address), and | |
3146 | * do a CRC on it (little endian), and reverse the bits of the | |
3147 | * result. | |
3148 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3149 | * table. The table is controlled through 8 32-bit registers: | |
3150 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3151 | * gaddr7. This means that the 3 most significant bits in the | |
3152 | * hash index which gaddr register to use, and the 5 other bits | |
3153 | * indicate which bit (assuming an IBM numbering scheme, which | |
3154 | * for PowerPC (tm) is usually the case) in the register holds | |
0977f817 JC |
3155 | * the entry. |
3156 | */ | |
1da177e4 LT |
3157 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) |
3158 | { | |
3159 | u32 tempval; | |
3160 | struct gfar_private *priv = netdev_priv(dev); | |
6a3c910c | 3161 | u32 result = ether_crc(ETH_ALEN, addr); |
0bbaf069 KG |
3162 | int width = priv->hash_width; |
3163 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3164 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3165 | u32 value = (1 << (31-whichbit)); |
3166 | ||
0bbaf069 | 3167 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3168 | tempval |= value; |
0bbaf069 | 3169 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3170 | } |
3171 | ||
7f7f5316 AF |
3172 | |
3173 | /* There are multiple MAC Address register pairs on some controllers | |
3174 | * This function sets the numth pair to a given address | |
3175 | */ | |
b6bc7650 JP |
3176 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3177 | const u8 *addr) | |
7f7f5316 AF |
3178 | { |
3179 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3180 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 | 3181 | int idx; |
6a3c910c | 3182 | char tmpbuf[ETH_ALEN]; |
7f7f5316 | 3183 | u32 tempval; |
f4983704 | 3184 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3185 | |
3186 | macptr += num*2; | |
3187 | ||
0977f817 JC |
3188 | /* Now copy it into the mac registers backwards, cuz |
3189 | * little endian is silly | |
3190 | */ | |
6a3c910c JP |
3191 | for (idx = 0; idx < ETH_ALEN; idx++) |
3192 | tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; | |
7f7f5316 AF |
3193 | |
3194 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3195 | ||
3196 | tempval = *((u32 *) (tmpbuf + 4)); | |
3197 | ||
3198 | gfar_write(macptr+1, tempval); | |
3199 | } | |
3200 | ||
1da177e4 | 3201 | /* GFAR error interrupt handler */ |
f4983704 | 3202 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3203 | { |
f4983704 SG |
3204 | struct gfar_priv_grp *gfargrp = grp_id; |
3205 | struct gfar __iomem *regs = gfargrp->regs; | |
3206 | struct gfar_private *priv= gfargrp->priv; | |
3207 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3208 | |
3209 | /* Save ievent for future reference */ | |
f4983704 | 3210 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3211 | |
3212 | /* Clear IEVENT */ | |
f4983704 | 3213 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3214 | |
3215 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3216 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3217 | (events & IEVENT_MAG)) |
3218 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3219 | |
3220 | /* Hmm... */ | |
0bbaf069 | 3221 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
bc4598bc JC |
3222 | netdev_dbg(dev, |
3223 | "error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
59deab26 | 3224 | events, gfar_read(®s->imask)); |
1da177e4 LT |
3225 | |
3226 | /* Update the error counters */ | |
3227 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3228 | dev->stats.tx_errors++; |
1da177e4 LT |
3229 | |
3230 | if (events & IEVENT_LC) | |
09f75cd7 | 3231 | dev->stats.tx_window_errors++; |
1da177e4 | 3232 | if (events & IEVENT_CRL) |
09f75cd7 | 3233 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3234 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3235 | unsigned long flags; |
3236 | ||
59deab26 JP |
3237 | netif_dbg(priv, tx_err, dev, |
3238 | "TX FIFO underrun, packet dropped\n"); | |
09f75cd7 | 3239 | dev->stats.tx_dropped++; |
212079df | 3240 | atomic64_inc(&priv->extra_stats.tx_underrun); |
1da177e4 | 3241 | |
836cf7fa AV |
3242 | local_irq_save(flags); |
3243 | lock_tx_qs(priv); | |
3244 | ||
1da177e4 | 3245 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3246 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3247 | |
3248 | unlock_tx_qs(priv); | |
3249 | local_irq_restore(flags); | |
1da177e4 | 3250 | } |
59deab26 | 3251 | netif_dbg(priv, tx_err, dev, "Transmit Error\n"); |
1da177e4 LT |
3252 | } |
3253 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3254 | dev->stats.rx_errors++; |
212079df | 3255 | atomic64_inc(&priv->extra_stats.rx_bsy); |
1da177e4 | 3256 | |
f4983704 | 3257 | gfar_receive(irq, grp_id); |
1da177e4 | 3258 | |
59deab26 JP |
3259 | netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", |
3260 | gfar_read(®s->rstat)); | |
1da177e4 LT |
3261 | } |
3262 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3263 | dev->stats.rx_errors++; |
212079df | 3264 | atomic64_inc(&priv->extra_stats.rx_babr); |
1da177e4 | 3265 | |
59deab26 | 3266 | netif_dbg(priv, rx_err, dev, "babbling RX error\n"); |
1da177e4 LT |
3267 | } |
3268 | if (events & IEVENT_EBERR) { | |
212079df | 3269 | atomic64_inc(&priv->extra_stats.eberr); |
59deab26 | 3270 | netif_dbg(priv, rx_err, dev, "bus error\n"); |
1da177e4 | 3271 | } |
59deab26 JP |
3272 | if (events & IEVENT_RXC) |
3273 | netif_dbg(priv, rx_status, dev, "control frame\n"); | |
1da177e4 LT |
3274 | |
3275 | if (events & IEVENT_BABT) { | |
212079df | 3276 | atomic64_inc(&priv->extra_stats.tx_babt); |
59deab26 | 3277 | netif_dbg(priv, tx_err, dev, "babbling TX error\n"); |
1da177e4 LT |
3278 | } |
3279 | return IRQ_HANDLED; | |
3280 | } | |
3281 | ||
b31a1d8b AF |
3282 | static struct of_device_id gfar_match[] = |
3283 | { | |
3284 | { | |
3285 | .type = "network", | |
3286 | .compatible = "gianfar", | |
3287 | }, | |
46ceb60c SG |
3288 | { |
3289 | .compatible = "fsl,etsec2", | |
3290 | }, | |
b31a1d8b AF |
3291 | {}, |
3292 | }; | |
e72701ac | 3293 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3294 | |
1da177e4 | 3295 | /* Structure for a device driver */ |
74888760 | 3296 | static struct platform_driver gfar_driver = { |
4018294b GL |
3297 | .driver = { |
3298 | .name = "fsl-gianfar", | |
3299 | .owner = THIS_MODULE, | |
3300 | .pm = GFAR_PM_OPS, | |
3301 | .of_match_table = gfar_match, | |
3302 | }, | |
1da177e4 LT |
3303 | .probe = gfar_probe, |
3304 | .remove = gfar_remove, | |
3305 | }; | |
3306 | ||
db62f684 | 3307 | module_platform_driver(gfar_driver); |