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ipv4: remove ipv4_ifdown_dst from route.c
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / freescale / gianfar.c
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0977f817 1/* drivers/net/ethernet/freescale/gianfar.c
1da177e4
LT		 2 *
3 * Gianfar Ethernet Driver
7f7f5316
AF		 4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
4c8d3d99 9 * Maintainer: Kumar Gala
a12f801d 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 11 *
20862788 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
a12f801d 13 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
0bbaf069 27 *
b31a1d8b
AF		 28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
0bbaf069 38 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
bb40dcbb 42 * of frames or amount of time have passed). In NAPI, the
1da177e4 43 * interrupt handler will signal there is work to be done, and
0aa1538f 44 * exit. This method will start at the last known empty
0bbaf069 45 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
59deab26
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65#define DEBUG
66
1da177e4 67#include <linux/kernel.h>
1da177e4
LT		 68#include <linux/string.h>
69#include <linux/errno.h>
bb40dcbb 70#include <linux/unistd.h>
1da177e4
LT		 71#include <linux/slab.h>
72#include <linux/interrupt.h>
1da177e4
LT		 73#include <linux/delay.h>
74#include <linux/netdevice.h>
75#include <linux/etherdevice.h>
76#include <linux/skbuff.h>
0bbaf069 77#include <linux/if_vlan.h>
1da177e4
LT		 78#include <linux/spinlock.h>
79#include <linux/mm.h>
5af50730
RH		 80#include <linux/of_address.h>
81#include <linux/of_irq.h>
fe192a49 82#include <linux/of_mdio.h>
b31a1d8b 83#include <linux/of_platform.h>
0bbaf069
KG		 84#include <linux/ip.h>
85#include <linux/tcp.h>
86#include <linux/udp.h>
9c07b884 87#include <linux/in.h>
cc772ab7 88#include <linux/net_tstamp.h>
1da177e4
LT		 89
90#include <asm/io.h>
7d350977 91#include <asm/reg.h>
2969b1f7 92#include <asm/mpc85xx.h>
1da177e4
LT		 93#include <asm/irq.h>
94#include <asm/uaccess.h>
95#include <linux/module.h>
1da177e4
LT		 96#include <linux/dma-mapping.h>
97#include <linux/crc32.h>
bb40dcbb
AF		 98#include <linux/mii.h>
99#include <linux/phy.h>
b31a1d8b
AF		 100#include <linux/phy_fixed.h>
101#include <linux/of.h>
4b6ba8aa 102#include <linux/of_net.h>
1da177e4
LT		 103
104#include "gianfar.h"
1da177e4
LT		 105
106#define TX_TIMEOUT (1*HZ)
1da177e4 107
7f7f5316 108const char gfar_driver_version[] = "1.3";
1da177e4 109
1da177e4
LT		 110static int gfar_enet_open(struct net_device *dev);
111static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 112static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 113static void gfar_timeout(struct net_device *dev);
114static int gfar_close(struct net_device *dev);
815b97c6 115struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 116static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
bc4598bc 117 struct sk_buff *skb);
1da177e4
LT		 118static int gfar_set_mac_address(struct net_device *dev);
119static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 120static irqreturn_t gfar_error(int irq, void *dev_id);
121static irqreturn_t gfar_transmit(int irq, void *dev_id);
122static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4 123static void adjust_link(struct net_device *dev);
1da177e4 124static int init_phy(struct net_device *dev);
74888760 125static int gfar_probe(struct platform_device *ofdev);
2dc11581 126static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 127static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 128static void gfar_set_multi(struct net_device *dev);
129static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 130static void gfar_configure_serdes(struct net_device *dev);
aeb12c5e
CM		 131static int gfar_poll_rx(struct napi_struct *napi, int budget);
132static int gfar_poll_tx(struct napi_struct *napi, int budget);
133static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
134static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
f2d71c2d
VW		 135#ifdef CONFIG_NET_POLL_CONTROLLER
136static void gfar_netpoll(struct net_device *dev);
137#endif
a12f801d 138int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
c233cf40 139static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
61db26c6
CM		 140static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
141 int amount_pull, struct napi_struct *napi);
c10650b6 142static void gfar_halt_nodisable(struct gfar_private *priv);
7f7f5316 143static void gfar_clear_exact_match(struct net_device *dev);
b6bc7650
JP		 144static void gfar_set_mac_for_addr(struct net_device *dev, int num,
145 const u8 *addr);
26ccfc37 146static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 147
1da177e4
LT		 148MODULE_AUTHOR("Freescale Semiconductor, Inc");
149MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150MODULE_LICENSE("GPL");
151
a12f801d 152static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 153 dma_addr_t buf)
154{
8a102fe0
AV		 155 u32 lstatus;
156
157 bdp->bufPtr = buf;
158
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 161 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163 eieio();
164
165 bdp->lstatus = lstatus;
166}
167
8728327e 168static int gfar_init_bds(struct net_device *ndev)
826aa4a0 169{
8728327e 170 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 173 struct txbd8 *txbdp;
174 struct rxbd8 *rxbdp;
fba4ed03 175 int i, j;
a12f801d 176
fba4ed03
SG		 177 for (i = 0; i < priv->num_tx_queues; i++) {
178 tx_queue = priv->tx_queue[i];
179 /* Initialize some variables in our dev structure */
180 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182 tx_queue->cur_tx = tx_queue->tx_bd_base;
183 tx_queue->skb_curtx = 0;
184 tx_queue->skb_dirtytx = 0;
185
186 /* Initialize Transmit Descriptor Ring */
187 txbdp = tx_queue->tx_bd_base;
188 for (j = 0; j < tx_queue->tx_ring_size; j++) {
189 txbdp->lstatus = 0;
190 txbdp->bufPtr = 0;
191 txbdp++;
192 }
8728327e 193
fba4ed03
SG		 194 /* Set the last descriptor in the ring to indicate wrap */
195 txbdp--;
196 txbdp->status |= TXBD_WRAP;
8728327e
AV		 197 }
198
fba4ed03
SG		 199 for (i = 0; i < priv->num_rx_queues; i++) {
200 rx_queue = priv->rx_queue[i];
201 rx_queue->cur_rx = rx_queue->rx_bd_base;
202 rx_queue->skb_currx = 0;
203 rxbdp = rx_queue->rx_bd_base;
8728327e 204
fba4ed03
SG		 205 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 207
fba4ed03
SG		 208 if (skb) {
209 gfar_init_rxbdp(rx_queue, rxbdp,
210 rxbdp->bufPtr);
211 } else {
212 skb = gfar_new_skb(ndev);
213 if (!skb) {
59deab26 214 netdev_err(ndev, "Can't allocate RX buffers\n");
1eb8f7a7 215 return -ENOMEM;
fba4ed03
SG		 216 }
217 rx_queue->rx_skbuff[j] = skb;
218
219 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 220 }
8728327e 221
fba4ed03 222 rxbdp++;
8728327e
AV		 223 }
224
8728327e
AV		 225 }
226
227 return 0;
228}
229
230static int gfar_alloc_skb_resources(struct net_device *ndev)
231{
826aa4a0 232 void *vaddr;
fba4ed03
SG		 233 dma_addr_t addr;
234 int i, j, k;
826aa4a0 235 struct gfar_private *priv = netdev_priv(ndev);
369ec162 236 struct device *dev = priv->dev;
a12f801d
SG		 237 struct gfar_priv_tx_q *tx_queue = NULL;
238 struct gfar_priv_rx_q *rx_queue = NULL;
239
fba4ed03
SG		 240 priv->total_tx_ring_size = 0;
241 for (i = 0; i < priv->num_tx_queues; i++)
242 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
243
244 priv->total_rx_ring_size = 0;
245 for (i = 0; i < priv->num_rx_queues; i++)
246 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 247
248 /* Allocate memory for the buffer descriptors */
8728327e 249 vaddr = dma_alloc_coherent(dev,
d0320f75
JP		 250 (priv->total_tx_ring_size *
251 sizeof(struct txbd8)) +
252 (priv->total_rx_ring_size *
253 sizeof(struct rxbd8)),
254 &addr, GFP_KERNEL);
255 if (!vaddr)
826aa4a0 256 return -ENOMEM;
826aa4a0 257
fba4ed03
SG		 258 for (i = 0; i < priv->num_tx_queues; i++) {
259 tx_queue = priv->tx_queue[i];
43d620c8 260 tx_queue->tx_bd_base = vaddr;
fba4ed03
SG		 261 tx_queue->tx_bd_dma_base = addr;
262 tx_queue->dev = ndev;
263 /* enet DMA only understands physical addresses */
bc4598bc
JC		 264 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
265 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
fba4ed03 266 }
826aa4a0 267
826aa4a0 268 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 269 for (i = 0; i < priv->num_rx_queues; i++) {
270 rx_queue = priv->rx_queue[i];
43d620c8 271 rx_queue->rx_bd_base = vaddr;
fba4ed03
SG		 272 rx_queue->rx_bd_dma_base = addr;
273 rx_queue->dev = ndev;
bc4598bc
JC		 274 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
275 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
fba4ed03 276 }
826aa4a0
AV		 277
278 /* Setup the skbuff rings */
fba4ed03
SG		 279 for (i = 0; i < priv->num_tx_queues; i++) {
280 tx_queue = priv->tx_queue[i];
14f8dc49
JP		 281 tx_queue->tx_skbuff =
282 kmalloc_array(tx_queue->tx_ring_size,
283 sizeof(*tx_queue->tx_skbuff),
284 GFP_KERNEL);
285 if (!tx_queue->tx_skbuff)
fba4ed03 286 goto cleanup;
826aa4a0 287
fba4ed03
SG		 288 for (k = 0; k < tx_queue->tx_ring_size; k++)
289 tx_queue->tx_skbuff[k] = NULL;
290 }
826aa4a0 291
fba4ed03
SG		 292 for (i = 0; i < priv->num_rx_queues; i++) {
293 rx_queue = priv->rx_queue[i];
14f8dc49
JP		 294 rx_queue->rx_skbuff =
295 kmalloc_array(rx_queue->rx_ring_size,
296 sizeof(*rx_queue->rx_skbuff),
297 GFP_KERNEL);
298 if (!rx_queue->rx_skbuff)
fba4ed03 299 goto cleanup;
fba4ed03
SG		 300
301 for (j = 0; j < rx_queue->rx_ring_size; j++)
302 rx_queue->rx_skbuff[j] = NULL;
303 }
826aa4a0 304
8728327e
AV		 305 if (gfar_init_bds(ndev))
306 goto cleanup;
826aa4a0
AV		 307
308 return 0;
309
310cleanup:
311 free_skb_resources(priv);
312 return -ENOMEM;
313}
314
fba4ed03
SG		 315static void gfar_init_tx_rx_base(struct gfar_private *priv)
316{
46ceb60c 317 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 318 u32 __iomem *baddr;
fba4ed03
SG		 319 int i;
320
321 baddr = &regs->tbase0;
bc4598bc 322 for (i = 0; i < priv->num_tx_queues; i++) {
fba4ed03 323 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
bc4598bc 324 baddr += 2;
fba4ed03
SG		 325 }
326
327 baddr = &regs->rbase0;
bc4598bc 328 for (i = 0; i < priv->num_rx_queues; i++) {
fba4ed03 329 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
bc4598bc 330 baddr += 2;
fba4ed03
SG		 331 }
332}
333
88302648 334static void gfar_rx_buff_size_config(struct gfar_private *priv)
826aa4a0 335{
88302648 336 int frame_size = priv->ndev->mtu + ETH_HLEN;
fba4ed03 337
ba779711
CM		 338 /* set this when rx hw offload (TOE) functions are being used */
339 priv->uses_rxfcb = 0;
340
88302648
CM		 341 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
342 priv->uses_rxfcb = 1;
343
344 if (priv->hwts_rx_en)
345 priv->uses_rxfcb = 1;
346
347 if (priv->uses_rxfcb)
348 frame_size += GMAC_FCB_LEN;
349
350 frame_size += priv->padding;
351
352 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
353 INCREMENTAL_BUFFER_SIZE;
354
355 priv->rx_buffer_size = frame_size;
356}
357
358static void gfar_mac_rx_config(struct gfar_private *priv)
359{
360 struct gfar __iomem *regs = priv->gfargrp[0].regs;
361 u32 rctrl = 0;
362
1ccb8389 363 if (priv->rx_filer_enable) {
fba4ed03 364 rctrl |= RCTRL_FILREN;
1ccb8389 365 /* Program the RIR0 reg with the required distribution */
71ff9e3d
CM		 366 if (priv->poll_mode == GFAR_SQ_POLLING)
367 gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
368 else /* GFAR_MQ_POLLING */
369 gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
1ccb8389 370 }
826aa4a0 371
f5ae6279 372 /* Restore PROMISC mode */
a328ac92 373 if (priv->ndev->flags & IFF_PROMISC)
f5ae6279
CM		 374 rctrl |= RCTRL_PROM;
375
88302648 376 if (priv->ndev->features & NETIF_F_RXCSUM)
826aa4a0
AV		 377 rctrl |= RCTRL_CHECKSUMMING;
378
88302648
CM		 379 if (priv->extended_hash)
380 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
826aa4a0
AV		 381
382 if (priv->padding) {
383 rctrl &= ~RCTRL_PAL_MASK;
384 rctrl |= RCTRL_PADDING(priv->padding);
385 }
386
97553f7f 387 /* Enable HW time stamping if requested from user space */
88302648 388 if (priv->hwts_rx_en)
97553f7f
MR		 389 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
390
88302648 391 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
b852b720 392 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
826aa4a0
AV		 393
394 /* Init rctrl based on our settings */
395 gfar_write(&regs->rctrl, rctrl);
a328ac92 396}
826aa4a0 397
a328ac92
CM		 398static void gfar_mac_tx_config(struct gfar_private *priv)
399{
400 struct gfar __iomem *regs = priv->gfargrp[0].regs;
401 u32 tctrl = 0;
402
403 if (priv->ndev->features & NETIF_F_IP_CSUM)
826aa4a0
AV		 404 tctrl |= TCTRL_INIT_CSUM;
405
b98b8bab
CM		 406 if (priv->prio_sched_en)
407 tctrl |= TCTRL_TXSCHED_PRIO;
408 else {
409 tctrl |= TCTRL_TXSCHED_WRRS;
410 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
411 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
412 }
fba4ed03 413
88302648
CM		 414 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
415 tctrl |= TCTRL_VLINS;
416
826aa4a0 417 gfar_write(&regs->tctrl, tctrl);
826aa4a0
AV		 418}
419
f19015ba
CM		 420static void gfar_configure_coalescing(struct gfar_private *priv,
421 unsigned long tx_mask, unsigned long rx_mask)
422{
423 struct gfar __iomem *regs = priv->gfargrp[0].regs;
424 u32 __iomem *baddr;
425
426 if (priv->mode == MQ_MG_MODE) {
427 int i = 0;
428
429 baddr = &regs->txic0;
430 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
431 gfar_write(baddr + i, 0);
432 if (likely(priv->tx_queue[i]->txcoalescing))
433 gfar_write(baddr + i, priv->tx_queue[i]->txic);
434 }
435
436 baddr = &regs->rxic0;
437 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
438 gfar_write(baddr + i, 0);
439 if (likely(priv->rx_queue[i]->rxcoalescing))
440 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
441 }
442 } else {
443 /* Backward compatible case -- even if we enable
444 * multiple queues, there's only single reg to program
445 */
446 gfar_write(&regs->txic, 0);
447 if (likely(priv->tx_queue[0]->txcoalescing))
448 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
449
450 gfar_write(&regs->rxic, 0);
451 if (unlikely(priv->rx_queue[0]->rxcoalescing))
452 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
453 }
454}
455
456void gfar_configure_coalescing_all(struct gfar_private *priv)
457{
458 gfar_configure_coalescing(priv, 0xFF, 0xFF);
459}
460
a7f38041
SG		 461static struct net_device_stats *gfar_get_stats(struct net_device *dev)
462{
463 struct gfar_private *priv = netdev_priv(dev);
a7f38041
SG		 464 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
465 unsigned long tx_packets = 0, tx_bytes = 0;
3a2e16c8 466 int i;
a7f38041
SG		 467
468 for (i = 0; i < priv->num_rx_queues; i++) {
469 rx_packets += priv->rx_queue[i]->stats.rx_packets;
bc4598bc 470 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
a7f38041
SG		 471 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
472 }
473
474 dev->stats.rx_packets = rx_packets;
bc4598bc 475 dev->stats.rx_bytes = rx_bytes;
a7f38041
SG		 476 dev->stats.rx_dropped = rx_dropped;
477
478 for (i = 0; i < priv->num_tx_queues; i++) {
1ac9ad13
ED		 479 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
480 tx_packets += priv->tx_queue[i]->stats.tx_packets;
a7f38041
SG		 481 }
482
bc4598bc 483 dev->stats.tx_bytes = tx_bytes;
a7f38041
SG		 484 dev->stats.tx_packets = tx_packets;
485
486 return &dev->stats;
487}
488
26ccfc37
AF		 489static const struct net_device_ops gfar_netdev_ops = {
490 .ndo_open = gfar_enet_open,
491 .ndo_start_xmit = gfar_start_xmit,
492 .ndo_stop = gfar_close,
493 .ndo_change_mtu = gfar_change_mtu,
8b3afe95 494 .ndo_set_features = gfar_set_features,
afc4b13d 495 .ndo_set_rx_mode = gfar_set_multi,
26ccfc37
AF		 496 .ndo_tx_timeout = gfar_timeout,
497 .ndo_do_ioctl = gfar_ioctl,
a7f38041 498 .ndo_get_stats = gfar_get_stats,
240c102d
BH		 499 .ndo_set_mac_address = eth_mac_addr,
500 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 501#ifdef CONFIG_NET_POLL_CONTROLLER
502 .ndo_poll_controller = gfar_netpoll,
503#endif
504};
505
efeddce7
CM		 506static void gfar_ints_disable(struct gfar_private *priv)
507{
508 int i;
509 for (i = 0; i < priv->num_grps; i++) {
510 struct gfar __iomem *regs = priv->gfargrp[i].regs;
511 /* Clear IEVENT */
512 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
513
514 /* Initialize IMASK */
515 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
516 }
517}
518
519static void gfar_ints_enable(struct gfar_private *priv)
520{
521 int i;
522 for (i = 0; i < priv->num_grps; i++) {
523 struct gfar __iomem *regs = priv->gfargrp[i].regs;
524 /* Unmask the interrupts we look for */
525 gfar_write(&regs->imask, IMASK_DEFAULT);
526 }
527}
528
fba4ed03
SG		 529void lock_tx_qs(struct gfar_private *priv)
530{
3a2e16c8 531 int i;
fba4ed03
SG		 532
533 for (i = 0; i < priv->num_tx_queues; i++)
534 spin_lock(&priv->tx_queue[i]->txlock);
535}
536
fba4ed03
SG		 537void unlock_tx_qs(struct gfar_private *priv)
538{
3a2e16c8 539 int i;
fba4ed03
SG		 540
541 for (i = 0; i < priv->num_tx_queues; i++)
542 spin_unlock(&priv->tx_queue[i]->txlock);
543}
544
20862788
CM		 545static int gfar_alloc_tx_queues(struct gfar_private *priv)
546{
547 int i;
548
549 for (i = 0; i < priv->num_tx_queues; i++) {
550 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
551 GFP_KERNEL);
552 if (!priv->tx_queue[i])
553 return -ENOMEM;
554
555 priv->tx_queue[i]->tx_skbuff = NULL;
556 priv->tx_queue[i]->qindex = i;
557 priv->tx_queue[i]->dev = priv->ndev;
558 spin_lock_init(&(priv->tx_queue[i]->txlock));
559 }
560 return 0;
561}
562
563static int gfar_alloc_rx_queues(struct gfar_private *priv)
564{
565 int i;
566
567 for (i = 0; i < priv->num_rx_queues; i++) {
568 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
569 GFP_KERNEL);
570 if (!priv->rx_queue[i])
571 return -ENOMEM;
572
573 priv->rx_queue[i]->rx_skbuff = NULL;
574 priv->rx_queue[i]->qindex = i;
575 priv->rx_queue[i]->dev = priv->ndev;
20862788
CM		 576 }
577 return 0;
578}
579
580static void gfar_free_tx_queues(struct gfar_private *priv)
fba4ed03 581{
3a2e16c8 582 int i;
fba4ed03
SG		 583
584 for (i = 0; i < priv->num_tx_queues; i++)
585 kfree(priv->tx_queue[i]);
586}
587
20862788 588static void gfar_free_rx_queues(struct gfar_private *priv)
fba4ed03 589{
3a2e16c8 590 int i;
fba4ed03
SG		 591
592 for (i = 0; i < priv->num_rx_queues; i++)
593 kfree(priv->rx_queue[i]);
594}
595
46ceb60c
SG		 596static void unmap_group_regs(struct gfar_private *priv)
597{
3a2e16c8 598 int i;
46ceb60c
SG		 599
600 for (i = 0; i < MAXGROUPS; i++)
601 if (priv->gfargrp[i].regs)
602 iounmap(priv->gfargrp[i].regs);
603}
604
ee873fda
CM		 605static void free_gfar_dev(struct gfar_private *priv)
606{
607 int i, j;
608
609 for (i = 0; i < priv->num_grps; i++)
610 for (j = 0; j < GFAR_NUM_IRQS; j++) {
611 kfree(priv->gfargrp[i].irqinfo[j]);
612 priv->gfargrp[i].irqinfo[j] = NULL;
613 }
614
615 free_netdev(priv->ndev);
616}
617
46ceb60c
SG		 618static void disable_napi(struct gfar_private *priv)
619{
3a2e16c8 620 int i;
46ceb60c 621
aeb12c5e
CM		 622 for (i = 0; i < priv->num_grps; i++) {
623 napi_disable(&priv->gfargrp[i].napi_rx);
624 napi_disable(&priv->gfargrp[i].napi_tx);
625 }
46ceb60c
SG		 626}
627
628static void enable_napi(struct gfar_private *priv)
629{
3a2e16c8 630 int i;
46ceb60c 631
aeb12c5e
CM		 632 for (i = 0; i < priv->num_grps; i++) {
633 napi_enable(&priv->gfargrp[i].napi_rx);
634 napi_enable(&priv->gfargrp[i].napi_tx);
635 }
46ceb60c
SG		 636}
637
638static int gfar_parse_group(struct device_node *np,
bc4598bc 639 struct gfar_private *priv, const char *model)
46ceb60c 640{
5fedcc14 641 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
ee873fda
CM		 642 int i;
643
7c1e7e99
PG		 644 for (i = 0; i < GFAR_NUM_IRQS; i++) {
645 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
646 GFP_KERNEL);
647 if (!grp->irqinfo[i])
ee873fda 648 return -ENOMEM;
ee873fda 649 }
46ceb60c 650
5fedcc14
CM		 651 grp->regs = of_iomap(np, 0);
652 if (!grp->regs)
46ceb60c
SG		 653 return -ENOMEM;
654
ee873fda 655 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
46ceb60c
SG		 656
657 /* If we aren't the FEC we have multiple interrupts */
658 if (model && strcasecmp(model, "FEC")) {
ee873fda
CM		 659 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
660 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
661 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
662 gfar_irq(grp, RX)->irq == NO_IRQ ||
663 gfar_irq(grp, ER)->irq == NO_IRQ)
46ceb60c 664 return -EINVAL;
46ceb60c
SG		 665 }
666
5fedcc14
CM		 667 grp->priv = priv;
668 spin_lock_init(&grp->grplock);
bc4598bc 669 if (priv->mode == MQ_MG_MODE) {
71ff9e3d
CM		 670 u32 *rxq_mask, *txq_mask;
671 rxq_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
672 txq_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
673
674 if (priv->poll_mode == GFAR_SQ_POLLING) {
675 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
676 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
677 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
678 } else { /* GFAR_MQ_POLLING */
679 grp->rx_bit_map = rxq_mask ?
680 *rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
681 grp->tx_bit_map = txq_mask ?
682 *txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
683 }
46ceb60c 684 } else {
5fedcc14
CM		 685 grp->rx_bit_map = 0xFF;
686 grp->tx_bit_map = 0xFF;
46ceb60c 687 }
20862788
CM		 688
689 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
690 * right to left, so we need to revert the 8 bits to get the q index
691 */
692 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
693 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
694
695 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
696 * also assign queues to groups
697 */
698 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
71ff9e3d
CM		 699 if (!grp->rx_queue)
700 grp->rx_queue = priv->rx_queue[i];
20862788
CM		 701 grp->num_rx_queues++;
702 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
703 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
704 priv->rx_queue[i]->grp = grp;
705 }
706
707 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
71ff9e3d
CM		 708 if (!grp->tx_queue)
709 grp->tx_queue = priv->tx_queue[i];
20862788
CM		 710 grp->num_tx_queues++;
711 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
712 priv->tqueue |= (TQUEUE_EN0 >> i);
713 priv->tx_queue[i]->grp = grp;
714 }
715
46ceb60c
SG		 716 priv->num_grps++;
717
718 return 0;
719}
720
2dc11581 721static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 722{
b31a1d8b
AF		 723 const char *model;
724 const char *ctype;
725 const void *mac_addr;
fba4ed03
SG		 726 int err = 0, i;
727 struct net_device *dev = NULL;
728 struct gfar_private *priv = NULL;
61c7a080 729 struct device_node *np = ofdev->dev.of_node;
46ceb60c 730 struct device_node *child = NULL;
4d7902f2
AF		 731 const u32 *stash;
732 const u32 *stash_len;
733 const u32 *stash_idx;
fba4ed03
SG		 734 unsigned int num_tx_qs, num_rx_qs;
735 u32 *tx_queues, *rx_queues;
b338ce27 736 unsigned short mode, poll_mode;
b31a1d8b
AF		 737
738 if (!np || !of_device_is_available(np))
739 return -ENODEV;
740
b338ce27
CM		 741 if (of_device_is_compatible(np, "fsl,etsec2")) {
742 mode = MQ_MG_MODE;
743 poll_mode = GFAR_SQ_POLLING;
744 } else {
745 mode = SQ_SG_MODE;
746 poll_mode = GFAR_SQ_POLLING;
747 }
748
71ff9e3d 749 /* parse the num of HW tx and rx queues */
fba4ed03 750 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
71ff9e3d
CM		 751 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
752
b338ce27 753 if (mode == SQ_SG_MODE) {
71ff9e3d
CM		 754 num_tx_qs = 1;
755 num_rx_qs = 1;
756 } else { /* MQ_MG_MODE */
b338ce27
CM		 757 if (poll_mode == GFAR_SQ_POLLING) {
758 num_tx_qs = 2; /* one txq per int group */
759 num_rx_qs = 2; /* one rxq per int group */
71ff9e3d
CM		 760 } else { /* GFAR_MQ_POLLING */
761 num_tx_qs = tx_queues ? *tx_queues : 1;
762 num_rx_qs = rx_queues ? *rx_queues : 1;
763 }
764 }
fba4ed03
SG		 765
766 if (num_tx_qs > MAX_TX_QS) {
59deab26
JP		 767 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
768 num_tx_qs, MAX_TX_QS);
769 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 770 return -EINVAL;
771 }
772
fba4ed03 773 if (num_rx_qs > MAX_RX_QS) {
59deab26
JP		 774 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
775 num_rx_qs, MAX_RX_QS);
776 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 777 return -EINVAL;
778 }
779
780 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
781 dev = *pdev;
782 if (NULL == dev)
783 return -ENOMEM;
784
785 priv = netdev_priv(dev);
fba4ed03
SG		 786 priv->ndev = dev;
787
b338ce27
CM		 788 priv->mode = mode;
789 priv->poll_mode = poll_mode;
790
fba4ed03 791 priv->num_tx_queues = num_tx_qs;
fe069123 792 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 793 priv->num_rx_queues = num_rx_qs;
20862788
CM		 794
795 err = gfar_alloc_tx_queues(priv);
796 if (err)
797 goto tx_alloc_failed;
798
799 err = gfar_alloc_rx_queues(priv);
800 if (err)
801 goto rx_alloc_failed;
b31a1d8b 802
0977f817 803 /* Init Rx queue filer rule set linked list */
4aa3a715
SP		 804 INIT_LIST_HEAD(&priv->rx_list.list);
805 priv->rx_list.count = 0;
806 mutex_init(&priv->rx_queue_access);
807
b31a1d8b
AF		 808 model = of_get_property(np, "model", NULL);
809
46ceb60c
SG		 810 for (i = 0; i < MAXGROUPS; i++)
811 priv->gfargrp[i].regs = NULL;
b31a1d8b 812
46ceb60c 813 /* Parse and initialize group specific information */
b338ce27 814 if (priv->mode == MQ_MG_MODE) {
46ceb60c
SG		 815 for_each_child_of_node(np, child) {
816 err = gfar_parse_group(child, priv, model);
817 if (err)
818 goto err_grp_init;
b31a1d8b 819 }
b338ce27 820 } else { /* SQ_SG_MODE */
46ceb60c 821 err = gfar_parse_group(np, priv, model);
bc4598bc 822 if (err)
46ceb60c 823 goto err_grp_init;
b31a1d8b
AF		 824 }
825
4d7902f2
AF		 826 stash = of_get_property(np, "bd-stash", NULL);
827
a12f801d 828 if (stash) {
4d7902f2
AF		 829 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
830 priv->bd_stash_en = 1;
831 }
832
833 stash_len = of_get_property(np, "rx-stash-len", NULL);
834
835 if (stash_len)
836 priv->rx_stash_size = *stash_len;
837
838 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
839
840 if (stash_idx)
841 priv->rx_stash_index = *stash_idx;
842
843 if (stash_len || stash_idx)
844 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
845
b31a1d8b 846 mac_addr = of_get_mac_address(np);
bc4598bc 847
b31a1d8b 848 if (mac_addr)
6a3c910c 849 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
b31a1d8b
AF		 850
851 if (model && !strcasecmp(model, "TSEC"))
34018fd4 852 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 853 FSL_GIANFAR_DEV_HAS_COALESCE |
854 FSL_GIANFAR_DEV_HAS_RMON |
855 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
856
b31a1d8b 857 if (model && !strcasecmp(model, "eTSEC"))
34018fd4 858 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 859 FSL_GIANFAR_DEV_HAS_COALESCE |
860 FSL_GIANFAR_DEV_HAS_RMON |
861 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
bc4598bc
JC		 862 FSL_GIANFAR_DEV_HAS_CSUM |
863 FSL_GIANFAR_DEV_HAS_VLAN |
864 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
865 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
866 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 867
868 ctype = of_get_property(np, "phy-connection-type", NULL);
869
870 /* We only care about rgmii-id. The rest are autodetected */
871 if (ctype && !strcmp(ctype, "rgmii-id"))
872 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
873 else
874 priv->interface = PHY_INTERFACE_MODE_MII;
875
876 if (of_get_property(np, "fsl,magic-packet", NULL))
877 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
878
fe192a49 879 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 880
881 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 882 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 883
884 return 0;
885
46ceb60c
SG		 886err_grp_init:
887 unmap_group_regs(priv);
20862788
CM		 888rx_alloc_failed:
889 gfar_free_rx_queues(priv);
890tx_alloc_failed:
891 gfar_free_tx_queues(priv);
ee873fda 892 free_gfar_dev(priv);
b31a1d8b
AF		 893 return err;
894}
895
ca0c88c2 896static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
cc772ab7
MR		 897{
898 struct hwtstamp_config config;
899 struct gfar_private *priv = netdev_priv(netdev);
900
901 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
902 return -EFAULT;
903
904 /* reserved for future extensions */
905 if (config.flags)
906 return -EINVAL;
907
f0ee7acf
MR		 908 switch (config.tx_type) {
909 case HWTSTAMP_TX_OFF:
910 priv->hwts_tx_en = 0;
911 break;
912 case HWTSTAMP_TX_ON:
913 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
914 return -ERANGE;
915 priv->hwts_tx_en = 1;
916 break;
917 default:
cc772ab7 918 return -ERANGE;
f0ee7acf 919 }
cc772ab7
MR		 920
921 switch (config.rx_filter) {
922 case HWTSTAMP_FILTER_NONE:
97553f7f 923 if (priv->hwts_rx_en) {
97553f7f 924 priv->hwts_rx_en = 0;
0851133b 925 reset_gfar(netdev);
97553f7f 926 }
cc772ab7
MR		 927 break;
928 default:
929 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
930 return -ERANGE;
97553f7f 931 if (!priv->hwts_rx_en) {
97553f7f 932 priv->hwts_rx_en = 1;
0851133b 933 reset_gfar(netdev);
97553f7f 934 }
cc772ab7
MR		 935 config.rx_filter = HWTSTAMP_FILTER_ALL;
936 break;
937 }
938
939 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
940 -EFAULT : 0;
941}
942
ca0c88c2
BH		 943static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
944{
945 struct hwtstamp_config config;
946 struct gfar_private *priv = netdev_priv(netdev);
947
948 config.flags = 0;
949 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
950 config.rx_filter = (priv->hwts_rx_en ?
951 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
952
953 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
954 -EFAULT : 0;
955}
956
0faac9f7
CW		 957static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
958{
959 struct gfar_private *priv = netdev_priv(dev);
960
961 if (!netif_running(dev))
962 return -EINVAL;
963
cc772ab7 964 if (cmd == SIOCSHWTSTAMP)
ca0c88c2
BH		 965 return gfar_hwtstamp_set(dev, rq);
966 if (cmd == SIOCGHWTSTAMP)
967 return gfar_hwtstamp_get(dev, rq);
cc772ab7 968
0faac9f7
CW		 969 if (!priv->phydev)
970 return -ENODEV;
971
28b04113 972 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 973}
974
18294ad1
AV		 975static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
976 u32 class)
7a8b3372
SG		 977{
978 u32 rqfpr = FPR_FILER_MASK;
979 u32 rqfcr = 0x0;
980
981 rqfar--;
982 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
6c43e046
WJB		 983 priv->ftp_rqfpr[rqfar] = rqfpr;
984 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 985 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
986
987 rqfar--;
988 rqfcr = RQFCR_CMP_NOMATCH;
6c43e046
WJB		 989 priv->ftp_rqfpr[rqfar] = rqfpr;
990 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 991 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
992
993 rqfar--;
994 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
995 rqfpr = class;
6c43e046
WJB		 996 priv->ftp_rqfcr[rqfar] = rqfcr;
997 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 998 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
999
1000 rqfar--;
1001 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1002 rqfpr = class;
6c43e046
WJB		 1003 priv->ftp_rqfcr[rqfar] = rqfcr;
1004 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1005 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1006
1007 return rqfar;
1008}
1009
1010static void gfar_init_filer_table(struct gfar_private *priv)
1011{
1012 int i = 0x0;
1013 u32 rqfar = MAX_FILER_IDX;
1014 u32 rqfcr = 0x0;
1015 u32 rqfpr = FPR_FILER_MASK;
1016
1017 /* Default rule */
1018 rqfcr = RQFCR_CMP_MATCH;
6c43e046
WJB		 1019 priv->ftp_rqfcr[rqfar] = rqfcr;
1020 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1021 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1022
1023 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1024 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1025 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1026 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1027 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1028 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1029
85dd08eb 1030 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 1031 priv->cur_filer_idx = rqfar;
1032
1033 /* Rest are masked rules */
1034 rqfcr = RQFCR_CMP_NOMATCH;
1035 for (i = 0; i < rqfar; i++) {
6c43e046
WJB		 1036 priv->ftp_rqfcr[i] = rqfcr;
1037 priv->ftp_rqfpr[i] = rqfpr;
7a8b3372
SG		 1038 gfar_write_filer(priv, i, rqfcr, rqfpr);
1039 }
1040}
1041
2969b1f7 1042static void __gfar_detect_errata_83xx(struct gfar_private *priv)
7d350977 1043{
7d350977
AV		 1044 unsigned int pvr = mfspr(SPRN_PVR);
1045 unsigned int svr = mfspr(SPRN_SVR);
1046 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1047 unsigned int rev = svr & 0xffff;
1048
1049 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1050 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
bc4598bc 1051 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
7d350977
AV		 1052 priv->errata |= GFAR_ERRATA_74;
1053
deb90eac
AV		 1054 /* MPC8313 and MPC837x all rev */
1055 if ((pvr == 0x80850010 && mod == 0x80b0) ||
bc4598bc 1056 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
deb90eac
AV		 1057 priv->errata |= GFAR_ERRATA_76;
1058
2969b1f7
CM		 1059 /* MPC8313 Rev < 2.0 */
1060 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1061 priv->errata |= GFAR_ERRATA_12;
1062}
1063
1064static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1065{
1066 unsigned int svr = mfspr(SPRN_SVR);
1067
1068 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
4363c2fd 1069 priv->errata |= GFAR_ERRATA_12;
53fad773
CM		 1070 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1071 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1072 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
2969b1f7
CM		 1073}
1074
1075static void gfar_detect_errata(struct gfar_private *priv)
1076{
1077 struct device *dev = &priv->ofdev->dev;
1078
1079 /* no plans to fix */
1080 priv->errata |= GFAR_ERRATA_A002;
1081
1082 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1083 __gfar_detect_errata_85xx(priv);
1084 else /* non-mpc85xx parts, i.e. e300 core based */
1085 __gfar_detect_errata_83xx(priv);
4363c2fd 1086
7d350977
AV		 1087 if (priv->errata)
1088 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1089 priv->errata);
1090}
1091
0851133b 1092void gfar_mac_reset(struct gfar_private *priv)
20862788
CM		 1093{
1094 struct gfar __iomem *regs = priv->gfargrp[0].regs;
a328ac92 1095 u32 tempval;
20862788
CM		 1096
1097 /* Reset MAC layer */
1098 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1099
1100 /* We need to delay at least 3 TX clocks */
a328ac92 1101 udelay(3);
20862788
CM		 1102
1103 /* the soft reset bit is not self-resetting, so we need to
1104 * clear it before resuming normal operation
1105 */
1106 gfar_write(&regs->maccfg1, 0);
1107
a328ac92
CM		 1108 udelay(3);
1109
88302648
CM		 1110 /* Compute rx_buff_size based on config flags */
1111 gfar_rx_buff_size_config(priv);
1112
1113 /* Initialize the max receive frame/buffer lengths */
1114 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
a328ac92
CM		 1115 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1116
1117 /* Initialize the Minimum Frame Length Register */
1118 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1119
20862788
CM		 1120 /* Initialize MACCFG2. */
1121 tempval = MACCFG2_INIT_SETTINGS;
88302648
CM		 1122
1123 /* If the mtu is larger than the max size for standard
1124 * ethernet frames (ie, a jumbo frame), then set maccfg2
1125 * to allow huge frames, and to check the length
1126 */
1127 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1128 gfar_has_errata(priv, GFAR_ERRATA_74))
20862788 1129 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
88302648 1130
20862788
CM		 1131 gfar_write(&regs->maccfg2, tempval);
1132
a328ac92
CM		 1133 /* Clear mac addr hash registers */
1134 gfar_write(&regs->igaddr0, 0);
1135 gfar_write(&regs->igaddr1, 0);
1136 gfar_write(&regs->igaddr2, 0);
1137 gfar_write(&regs->igaddr3, 0);
1138 gfar_write(&regs->igaddr4, 0);
1139 gfar_write(&regs->igaddr5, 0);
1140 gfar_write(&regs->igaddr6, 0);
1141 gfar_write(&regs->igaddr7, 0);
1142
1143 gfar_write(&regs->gaddr0, 0);
1144 gfar_write(&regs->gaddr1, 0);
1145 gfar_write(&regs->gaddr2, 0);
1146 gfar_write(&regs->gaddr3, 0);
1147 gfar_write(&regs->gaddr4, 0);
1148 gfar_write(&regs->gaddr5, 0);
1149 gfar_write(&regs->gaddr6, 0);
1150 gfar_write(&regs->gaddr7, 0);
1151
1152 if (priv->extended_hash)
1153 gfar_clear_exact_match(priv->ndev);
1154
1155 gfar_mac_rx_config(priv);
1156
1157 gfar_mac_tx_config(priv);
1158
1159 gfar_set_mac_address(priv->ndev);
1160
1161 gfar_set_multi(priv->ndev);
1162
1163 /* clear ievent and imask before configuring coalescing */
1164 gfar_ints_disable(priv);
1165
1166 /* Configure the coalescing support */
1167 gfar_configure_coalescing_all(priv);
1168}
1169
1170static void gfar_hw_init(struct gfar_private *priv)
1171{
1172 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1173 u32 attrs;
1174
1175 /* Stop the DMA engine now, in case it was running before
1176 * (The firmware could have used it, and left it running).
1177 */
1178 gfar_halt(priv);
1179
1180 gfar_mac_reset(priv);
1181
1182 /* Zero out the rmon mib registers if it has them */
1183 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1184 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1185
1186 /* Mask off the CAM interrupts */
1187 gfar_write(&regs->rmon.cam1, 0xffffffff);
1188 gfar_write(&regs->rmon.cam2, 0xffffffff);
1189 }
1190
20862788
CM		 1191 /* Initialize ECNTRL */
1192 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1193
34018fd4
CM		 1194 /* Set the extraction length and index */
1195 attrs = ATTRELI_EL(priv->rx_stash_size) |
1196 ATTRELI_EI(priv->rx_stash_index);
1197
1198 gfar_write(&regs->attreli, attrs);
1199
1200 /* Start with defaults, and add stashing
1201 * depending on driver parameters
1202 */
1203 attrs = ATTR_INIT_SETTINGS;
1204
1205 if (priv->bd_stash_en)
1206 attrs |= ATTR_BDSTASH;
1207
1208 if (priv->rx_stash_size != 0)
1209 attrs |= ATTR_BUFSTASH;
1210
1211 gfar_write(&regs->attr, attrs);
1212
1213 /* FIFO configs */
1214 gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1215 gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1216 gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1217
20862788
CM		 1218 /* Program the interrupt steering regs, only for MG devices */
1219 if (priv->num_grps > 1)
1220 gfar_write_isrg(priv);
20862788
CM		 1221}
1222
1223static void __init gfar_init_addr_hash_table(struct gfar_private *priv)
1224{
1225 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1226
1227 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1228 priv->extended_hash = 1;
1229 priv->hash_width = 9;
1230
1231 priv->hash_regs[0] = &regs->igaddr0;
1232 priv->hash_regs[1] = &regs->igaddr1;
1233 priv->hash_regs[2] = &regs->igaddr2;
1234 priv->hash_regs[3] = &regs->igaddr3;
1235 priv->hash_regs[4] = &regs->igaddr4;
1236 priv->hash_regs[5] = &regs->igaddr5;
1237 priv->hash_regs[6] = &regs->igaddr6;
1238 priv->hash_regs[7] = &regs->igaddr7;
1239 priv->hash_regs[8] = &regs->gaddr0;
1240 priv->hash_regs[9] = &regs->gaddr1;
1241 priv->hash_regs[10] = &regs->gaddr2;
1242 priv->hash_regs[11] = &regs->gaddr3;
1243 priv->hash_regs[12] = &regs->gaddr4;
1244 priv->hash_regs[13] = &regs->gaddr5;
1245 priv->hash_regs[14] = &regs->gaddr6;
1246 priv->hash_regs[15] = &regs->gaddr7;
1247
1248 } else {
1249 priv->extended_hash = 0;
1250 priv->hash_width = 8;
1251
1252 priv->hash_regs[0] = &regs->gaddr0;
1253 priv->hash_regs[1] = &regs->gaddr1;
1254 priv->hash_regs[2] = &regs->gaddr2;
1255 priv->hash_regs[3] = &regs->gaddr3;
1256 priv->hash_regs[4] = &regs->gaddr4;
1257 priv->hash_regs[5] = &regs->gaddr5;
1258 priv->hash_regs[6] = &regs->gaddr6;
1259 priv->hash_regs[7] = &regs->gaddr7;
1260 }
1261}
1262
bb40dcbb 1263/* Set up the ethernet device structure, private data,
0977f817
JC		 1264 * and anything else we need before we start
1265 */
74888760 1266static int gfar_probe(struct platform_device *ofdev)
1da177e4 1267{
1da177e4
LT		 1268 struct net_device *dev = NULL;
1269 struct gfar_private *priv = NULL;
20862788 1270 int err = 0, i;
1da177e4 1271
fba4ed03 1272 err = gfar_of_init(ofdev, &dev);
1da177e4 1273
fba4ed03
SG		 1274 if (err)
1275 return err;
1da177e4
LT		 1276
1277 priv = netdev_priv(dev);
4826857f
KG		 1278 priv->ndev = dev;
1279 priv->ofdev = ofdev;
369ec162 1280 priv->dev = &ofdev->dev;
4826857f 1281 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 1282
d87eb127 1283 spin_lock_init(&priv->bflock);
ab939905 1284 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 1285
8513fbd8 1286 platform_set_drvdata(ofdev, priv);
1da177e4 1287
7d350977
AV		 1288 gfar_detect_errata(priv);
1289
1da177e4 1290 /* Set the dev->base_addr to the gfar reg region */
20862788 1291 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1da177e4 1292
1da177e4 1293 /* Fill in the dev structure */
1da177e4 1294 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1295 dev->mtu = 1500;
26ccfc37 1296 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1297 dev->ethtool_ops = &gfar_ethtool_ops;
1298
fba4ed03 1299 /* Register for napi ...We are registering NAPI for each grp */
71ff9e3d
CM		 1300 for (i = 0; i < priv->num_grps; i++) {
1301 if (priv->poll_mode == GFAR_SQ_POLLING) {
1302 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1303 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1304 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1305 gfar_poll_tx_sq, 2);
1306 } else {
aeb12c5e
CM		 1307 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1308 gfar_poll_rx, GFAR_DEV_WEIGHT);
1309 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1310 gfar_poll_tx, 2);
1311 }
1312 }
a12f801d 1313
b31a1d8b 1314 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
8b3afe95 1315 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1316 NETIF_F_RXCSUM;
8b3afe95 1317 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1318 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
8b3afe95 1319 }
0bbaf069 1320
87c288c6 1321 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
f646968f
PM		 1322 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1323 NETIF_F_HW_VLAN_CTAG_RX;
1324 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
87c288c6 1325 }
0bbaf069 1326
20862788 1327 gfar_init_addr_hash_table(priv);
0bbaf069 1328
532c37bc
CM		 1329 /* Insert receive time stamps into padding alignment bytes */
1330 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1331 priv->padding = 8;
0bbaf069 1332
cc772ab7 1333 if (dev->features & NETIF_F_IP_CSUM ||
bc4598bc 1334 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
bee9e58c 1335 dev->needed_headroom = GMAC_FCB_LEN;
1da177e4
LT		 1336
1337 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1338
a12f801d 1339 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1340 for (i = 0; i < priv->num_tx_queues; i++) {
1341 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1342 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1343 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1344 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1345 }
a12f801d 1346
fba4ed03
SG		 1347 for (i = 0; i < priv->num_rx_queues; i++) {
1348 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1349 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1350 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1351 }
1da177e4 1352
0977f817 1353 /* always enable rx filer */
4aa3a715 1354 priv->rx_filer_enable = 1;
0bbaf069
KG		 1355 /* Enable most messages by default */
1356 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
b98b8bab
CM		 1357 /* use pritority h/w tx queue scheduling for single queue devices */
1358 if (priv->num_tx_queues == 1)
1359 priv->prio_sched_en = 1;
0bbaf069 1360
0851133b
CM		 1361 set_bit(GFAR_DOWN, &priv->state);
1362
a328ac92 1363 gfar_hw_init(priv);
d3eab82b 1364
1da177e4
LT		 1365 err = register_netdev(dev);
1366
1367 if (err) {
59deab26 1368 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1da177e4
LT		 1369 goto register_fail;
1370 }
1371
a328ac92
CM		 1372 /* Carrier starts down, phylib will bring it up */
1373 netif_carrier_off(dev);
1374
2884e5cc 1375 device_init_wakeup(&dev->dev,
bc4598bc
JC		 1376 priv->device_flags &
1377 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
2884e5cc 1378
c50a5d9a 1379 /* fill out IRQ number and name fields */
46ceb60c 1380 for (i = 0; i < priv->num_grps; i++) {
ee873fda 1381 struct gfar_priv_grp *grp = &priv->gfargrp[i];
46ceb60c 1382 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
ee873fda 1383 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
0015e551 1384 dev->name, "_g", '0' + i, "_tx");
ee873fda 1385 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
0015e551 1386 dev->name, "_g", '0' + i, "_rx");
ee873fda 1387 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
0015e551 1388 dev->name, "_g", '0' + i, "_er");
46ceb60c 1389 } else
ee873fda 1390 strcpy(gfar_irq(grp, TX)->name, dev->name);
46ceb60c 1391 }
c50a5d9a 1392
7a8b3372
SG		 1393 /* Initialize the filer table */
1394 gfar_init_filer_table(priv);
1395
1da177e4 1396 /* Print out the device info */
59deab26 1397 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1da177e4 1398
0977f817
JC		 1399 /* Even more device info helps when determining which kernel
1400 * provided which set of benchmarks.
1401 */
59deab26 1402 netdev_info(dev, "Running with NAPI enabled\n");
fba4ed03 1403 for (i = 0; i < priv->num_rx_queues; i++)
59deab26
JP		 1404 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1405 i, priv->rx_queue[i]->rx_ring_size);
bc4598bc 1406 for (i = 0; i < priv->num_tx_queues; i++)
59deab26
JP		 1407 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1408 i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1409
1410 return 0;
1411
1412register_fail:
46ceb60c 1413 unmap_group_regs(priv);
20862788
CM		 1414 gfar_free_rx_queues(priv);
1415 gfar_free_tx_queues(priv);
fe192a49
GL		 1416 if (priv->phy_node)
1417 of_node_put(priv->phy_node);
1418 if (priv->tbi_node)
1419 of_node_put(priv->tbi_node);
ee873fda 1420 free_gfar_dev(priv);
bb40dcbb 1421 return err;
1da177e4
LT		 1422}
1423
2dc11581 1424static int gfar_remove(struct platform_device *ofdev)
1da177e4 1425{
8513fbd8 1426 struct gfar_private *priv = platform_get_drvdata(ofdev);
1da177e4 1427
fe192a49
GL		 1428 if (priv->phy_node)
1429 of_node_put(priv->phy_node);
1430 if (priv->tbi_node)
1431 of_node_put(priv->tbi_node);
1432
d9d8e041 1433 unregister_netdev(priv->ndev);
46ceb60c 1434 unmap_group_regs(priv);
20862788
CM		 1435 gfar_free_rx_queues(priv);
1436 gfar_free_tx_queues(priv);
ee873fda 1437 free_gfar_dev(priv);
1da177e4
LT		 1438
1439 return 0;
1440}
1441
d87eb127 1442#ifdef CONFIG_PM
be926fc4
AV		 1443
1444static int gfar_suspend(struct device *dev)
d87eb127 1445{
be926fc4
AV		 1446 struct gfar_private *priv = dev_get_drvdata(dev);
1447 struct net_device *ndev = priv->ndev;
46ceb60c 1448 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1449 unsigned long flags;
1450 u32 tempval;
1451
1452 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1453 (priv->device_flags &
1454 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1455
be926fc4 1456 netif_device_detach(ndev);
d87eb127 1457
be926fc4 1458 if (netif_running(ndev)) {
fba4ed03
SG		 1459
1460 local_irq_save(flags);
1461 lock_tx_qs(priv);
d87eb127 1462
c10650b6 1463 gfar_halt_nodisable(priv);
d87eb127
SW		 1464
1465 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1466 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1467
1468 tempval &= ~MACCFG1_TX_EN;
1469
1470 if (!magic_packet)
1471 tempval &= ~MACCFG1_RX_EN;
1472
f4983704 1473 gfar_write(&regs->maccfg1, tempval);
d87eb127 1474
fba4ed03
SG		 1475 unlock_tx_qs(priv);
1476 local_irq_restore(flags);
d87eb127 1477
46ceb60c 1478 disable_napi(priv);
d87eb127
SW		 1479
1480 if (magic_packet) {
1481 /* Enable interrupt on Magic Packet */
f4983704 1482 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1483
1484 /* Enable Magic Packet mode */
f4983704 1485 tempval = gfar_read(&regs->maccfg2);
d87eb127 1486 tempval |= MACCFG2_MPEN;
f4983704 1487 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1488 } else {
1489 phy_stop(priv->phydev);
1490 }
1491 }
1492
1493 return 0;
1494}
1495
be926fc4 1496static int gfar_resume(struct device *dev)
d87eb127 1497{
be926fc4
AV		 1498 struct gfar_private *priv = dev_get_drvdata(dev);
1499 struct net_device *ndev = priv->ndev;
46ceb60c 1500 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1501 unsigned long flags;
1502 u32 tempval;
1503 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1504 (priv->device_flags &
1505 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1506
be926fc4
AV		 1507 if (!netif_running(ndev)) {
1508 netif_device_attach(ndev);
d87eb127
SW		 1509 return 0;
1510 }
1511
1512 if (!magic_packet && priv->phydev)
1513 phy_start(priv->phydev);
1514
1515 /* Disable Magic Packet mode, in case something
1516 * else woke us up.
1517 */
fba4ed03
SG		 1518 local_irq_save(flags);
1519 lock_tx_qs(priv);
d87eb127 1520
f4983704 1521 tempval = gfar_read(&regs->maccfg2);
d87eb127 1522 tempval &= ~MACCFG2_MPEN;
f4983704 1523 gfar_write(&regs->maccfg2, tempval);
d87eb127 1524
c10650b6 1525 gfar_start(priv);
d87eb127 1526
fba4ed03
SG		 1527 unlock_tx_qs(priv);
1528 local_irq_restore(flags);
d87eb127 1529
be926fc4
AV		 1530 netif_device_attach(ndev);
1531
46ceb60c 1532 enable_napi(priv);
be926fc4
AV		 1533
1534 return 0;
1535}
1536
1537static int gfar_restore(struct device *dev)
1538{
1539 struct gfar_private *priv = dev_get_drvdata(dev);
1540 struct net_device *ndev = priv->ndev;
1541
103cdd1d
WD		 1542 if (!netif_running(ndev)) {
1543 netif_device_attach(ndev);
1544
be926fc4 1545 return 0;
103cdd1d 1546 }
be926fc4 1547
1eb8f7a7
CM		 1548 if (gfar_init_bds(ndev)) {
1549 free_skb_resources(priv);
1550 return -ENOMEM;
1551 }
1552
a328ac92
CM		 1553 gfar_mac_reset(priv);
1554
1555 gfar_init_tx_rx_base(priv);
1556
c10650b6 1557 gfar_start(priv);
be926fc4
AV		 1558
1559 priv->oldlink = 0;
1560 priv->oldspeed = 0;
1561 priv->oldduplex = -1;
1562
1563 if (priv->phydev)
1564 phy_start(priv->phydev);
d87eb127 1565
be926fc4 1566 netif_device_attach(ndev);
5ea681d4 1567 enable_napi(priv);
d87eb127
SW		 1568
1569 return 0;
1570}
be926fc4
AV		 1571
1572static struct dev_pm_ops gfar_pm_ops = {
1573 .suspend = gfar_suspend,
1574 .resume = gfar_resume,
1575 .freeze = gfar_suspend,
1576 .thaw = gfar_resume,
1577 .restore = gfar_restore,
1578};
1579
1580#define GFAR_PM_OPS (&gfar_pm_ops)
1581
d87eb127 1582#else
be926fc4
AV		 1583
1584#define GFAR_PM_OPS NULL
be926fc4 1585
d87eb127 1586#endif
1da177e4 1587
e8a2b6a4
AF		 1588/* Reads the controller's registers to determine what interface
1589 * connects it to the PHY.
1590 */
1591static phy_interface_t gfar_get_interface(struct net_device *dev)
1592{
1593 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1594 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1595 u32 ecntrl;
1596
f4983704 1597 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1598
1599 if (ecntrl & ECNTRL_SGMII_MODE)
1600 return PHY_INTERFACE_MODE_SGMII;
1601
1602 if (ecntrl & ECNTRL_TBI_MODE) {
1603 if (ecntrl & ECNTRL_REDUCED_MODE)
1604 return PHY_INTERFACE_MODE_RTBI;
1605 else
1606 return PHY_INTERFACE_MODE_TBI;
1607 }
1608
1609 if (ecntrl & ECNTRL_REDUCED_MODE) {
bc4598bc 1610 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
e8a2b6a4 1611 return PHY_INTERFACE_MODE_RMII;
bc4598bc 1612 }
7132ab7f 1613 else {
b31a1d8b 1614 phy_interface_t interface = priv->interface;
7132ab7f 1615
0977f817 1616 /* This isn't autodetected right now, so it must
7132ab7f
AF		 1617 * be set by the device tree or platform code.
1618 */
1619 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1620 return PHY_INTERFACE_MODE_RGMII_ID;
1621
e8a2b6a4 1622 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1623 }
e8a2b6a4
AF		 1624 }
1625
b31a1d8b 1626 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1627 return PHY_INTERFACE_MODE_GMII;
1628
1629 return PHY_INTERFACE_MODE_MII;
1630}
1631
1632
bb40dcbb
AF		 1633/* Initializes driver's PHY state, and attaches to the PHY.
1634 * Returns 0 on success.
1da177e4
LT		 1635 */
1636static int init_phy(struct net_device *dev)
1637{
1638 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1639 uint gigabit_support =
b31a1d8b 1640 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
23402bdd 1641 GFAR_SUPPORTED_GBIT : 0;
e8a2b6a4 1642 phy_interface_t interface;
1da177e4
LT		 1643
1644 priv->oldlink = 0;
1645 priv->oldspeed = 0;
1646 priv->oldduplex = -1;
1647
e8a2b6a4
AF		 1648 interface = gfar_get_interface(dev);
1649
1db780f8
AV		 1650 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1651 interface);
1652 if (!priv->phydev)
1653 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1654 interface);
1655 if (!priv->phydev) {
1656 dev_err(&dev->dev, "could not attach to PHY\n");
1657 return -ENODEV;
fe192a49 1658 }
1da177e4 1659
d3c12873
KJ		 1660 if (interface == PHY_INTERFACE_MODE_SGMII)
1661 gfar_configure_serdes(dev);
1662
bb40dcbb 1663 /* Remove any features not supported by the controller */
fe192a49
GL		 1664 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1665 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1666
1667 return 0;
1da177e4
LT		 1668}
1669
0977f817 1670/* Initialize TBI PHY interface for communicating with the
d0313587
PG		 1671 * SERDES lynx PHY on the chip. We communicate with this PHY
1672 * through the MDIO bus on each controller, treating it as a
1673 * "normal" PHY at the address found in the TBIPA register. We assume
1674 * that the TBIPA register is valid. Either the MDIO bus code will set
1675 * it to a value that doesn't conflict with other PHYs on the bus, or the
1676 * value doesn't matter, as there are no other PHYs on the bus.
1677 */
d3c12873
KJ		 1678static void gfar_configure_serdes(struct net_device *dev)
1679{
1680 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1681 struct phy_device *tbiphy;
1682
1683 if (!priv->tbi_node) {
1684 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1685 "device tree specify a tbi-handle\n");
1686 return;
1687 }
c132419e 1688
fe192a49
GL		 1689 tbiphy = of_phy_find_device(priv->tbi_node);
1690 if (!tbiphy) {
1691 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1692 return;
1693 }
d3c12873 1694
0977f817 1695 /* If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1696 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1697 * everything for us? Resetting it takes the link down and requires
1698 * several seconds for it to come back.
1699 */
fe192a49 1700 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1701 return;
d3c12873 1702
d0313587 1703 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1704 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1705
fe192a49 1706 phy_write(tbiphy, MII_ADVERTISE,
bc4598bc
JC		 1707 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1708 ADVERTISE_1000XPSE_ASYM);
d3c12873 1709
bc4598bc
JC		 1710 phy_write(tbiphy, MII_BMCR,
1711 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1712 BMCR_SPEED1000);
d3c12873
KJ		 1713}
1714
511d934f
AV		 1715static int __gfar_is_rx_idle(struct gfar_private *priv)
1716{
1717 u32 res;
1718
0977f817 1719 /* Normaly TSEC should not hang on GRS commands, so we should
511d934f
AV		 1720 * actually wait for IEVENT_GRSC flag.
1721 */
ad3660c2 1722 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
511d934f
AV		 1723 return 0;
1724
0977f817 1725 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
511d934f
AV		 1726 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1727 * and the Rx can be safely reset.
1728 */
1729 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1730 res &= 0x7f807f80;
1731 if ((res & 0xffff) == (res >> 16))
1732 return 1;
1733
1734 return 0;
1735}
0bbaf069
KG		 1736
1737/* Halt the receive and transmit queues */
c10650b6 1738static void gfar_halt_nodisable(struct gfar_private *priv)
1da177e4 1739{
efeddce7 1740 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 1741 u32 tempval;
1742
efeddce7 1743 gfar_ints_disable(priv);
1da177e4 1744
1da177e4 1745 /* Stop the DMA, and wait for it to stop */
f4983704 1746 tempval = gfar_read(&regs->dmactrl);
bc4598bc
JC		 1747 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1748 (DMACTRL_GRS | DMACTRL_GTS)) {
511d934f
AV		 1749 int ret;
1750
1da177e4 1751 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1752 gfar_write(&regs->dmactrl, tempval);
1da177e4 1753
511d934f
AV		 1754 do {
1755 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1756 (IEVENT_GRSC | IEVENT_GTSC)) ==
1757 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1758 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1759 ret = __gfar_is_rx_idle(priv);
1760 } while (!ret);
1da177e4 1761 }
d87eb127 1762}
d87eb127
SW		 1763
1764/* Halt the receive and transmit queues */
c10650b6 1765void gfar_halt(struct gfar_private *priv)
d87eb127 1766{
46ceb60c 1767 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1768 u32 tempval;
1da177e4 1769
c10650b6
CM		 1770 /* Dissable the Rx/Tx hw queues */
1771 gfar_write(&regs->rqueue, 0);
1772 gfar_write(&regs->tqueue, 0);
2a54adc3 1773
c10650b6
CM		 1774 mdelay(10);
1775
1776 gfar_halt_nodisable(priv);
1777
1778 /* Disable Rx/Tx DMA */
1da177e4
LT		 1779 tempval = gfar_read(&regs->maccfg1);
1780 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1781 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1782}
1783
1784void stop_gfar(struct net_device *dev)
1785{
1786 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1787
0851133b 1788 netif_tx_stop_all_queues(dev);
bb40dcbb 1789
0851133b
CM		 1790 smp_mb__before_clear_bit();
1791 set_bit(GFAR_DOWN, &priv->state);
1792 smp_mb__after_clear_bit();
a12f801d 1793
0851133b 1794 disable_napi(priv);
0bbaf069 1795
0851133b 1796 /* disable ints and gracefully shut down Rx/Tx DMA */
c10650b6 1797 gfar_halt(priv);
1da177e4 1798
0851133b 1799 phy_stop(priv->phydev);
1da177e4 1800
1da177e4 1801 free_skb_resources(priv);
1da177e4
LT		 1802}
1803
fba4ed03 1804static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1805{
1da177e4 1806 struct txbd8 *txbdp;
fba4ed03 1807 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1808 int i, j;
1da177e4 1809
a12f801d 1810 txbdp = tx_queue->tx_bd_base;
1da177e4 1811
a12f801d
SG		 1812 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1813 if (!tx_queue->tx_skbuff[i])
4669bc90 1814 continue;
1da177e4 1815
369ec162 1816 dma_unmap_single(priv->dev, txbdp->bufPtr,
bc4598bc 1817 txbdp->length, DMA_TO_DEVICE);
4669bc90 1818 txbdp->lstatus = 0;
fba4ed03 1819 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
bc4598bc 1820 j++) {
4669bc90 1821 txbdp++;
369ec162 1822 dma_unmap_page(priv->dev, txbdp->bufPtr,
bc4598bc 1823 txbdp->length, DMA_TO_DEVICE);
1da177e4 1824 }
ad5da7ab 1825 txbdp++;
a12f801d
SG		 1826 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1827 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1828 }
a12f801d 1829 kfree(tx_queue->tx_skbuff);
1eb8f7a7 1830 tx_queue->tx_skbuff = NULL;
fba4ed03 1831}
1da177e4 1832
fba4ed03
SG		 1833static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1834{
1835 struct rxbd8 *rxbdp;
1836 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1837 int i;
1da177e4 1838
fba4ed03 1839 rxbdp = rx_queue->rx_bd_base;
1da177e4 1840
a12f801d
SG		 1841 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1842 if (rx_queue->rx_skbuff[i]) {
369ec162
CM		 1843 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1844 priv->rx_buffer_size,
bc4598bc 1845 DMA_FROM_DEVICE);
a12f801d
SG		 1846 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1847 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1848 }
e69edd21
AV		 1849 rxbdp->lstatus = 0;
1850 rxbdp->bufPtr = 0;
1851 rxbdp++;
1da177e4 1852 }
a12f801d 1853 kfree(rx_queue->rx_skbuff);
1eb8f7a7 1854 rx_queue->rx_skbuff = NULL;
fba4ed03 1855}
e69edd21 1856
fba4ed03 1857/* If there are any tx skbs or rx skbs still around, free them.
0977f817
JC		 1858 * Then free tx_skbuff and rx_skbuff
1859 */
fba4ed03
SG		 1860static void free_skb_resources(struct gfar_private *priv)
1861{
1862 struct gfar_priv_tx_q *tx_queue = NULL;
1863 struct gfar_priv_rx_q *rx_queue = NULL;
1864 int i;
1865
1866 /* Go through all the buffer descriptors and free their data buffers */
1867 for (i = 0; i < priv->num_tx_queues; i++) {
d8a0f1b0 1868 struct netdev_queue *txq;
bc4598bc 1869
fba4ed03 1870 tx_queue = priv->tx_queue[i];
d8a0f1b0 1871 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
bc4598bc 1872 if (tx_queue->tx_skbuff)
fba4ed03 1873 free_skb_tx_queue(tx_queue);
d8a0f1b0 1874 netdev_tx_reset_queue(txq);
fba4ed03
SG		 1875 }
1876
1877 for (i = 0; i < priv->num_rx_queues; i++) {
1878 rx_queue = priv->rx_queue[i];
bc4598bc 1879 if (rx_queue->rx_skbuff)
fba4ed03
SG		 1880 free_skb_rx_queue(rx_queue);
1881 }
1882
369ec162 1883 dma_free_coherent(priv->dev,
bc4598bc
JC		 1884 sizeof(struct txbd8) * priv->total_tx_ring_size +
1885 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1886 priv->tx_queue[0]->tx_bd_base,
1887 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 1888}
1889
c10650b6 1890void gfar_start(struct gfar_private *priv)
0bbaf069 1891{
46ceb60c 1892 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1893 u32 tempval;
46ceb60c 1894 int i = 0;
0bbaf069 1895
c10650b6
CM		 1896 /* Enable Rx/Tx hw queues */
1897 gfar_write(&regs->rqueue, priv->rqueue);
1898 gfar_write(&regs->tqueue, priv->tqueue);
0bbaf069
KG		 1899
1900 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1901 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1902 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1903 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1904
0bbaf069 1905 /* Make sure we aren't stopped */
f4983704 1906 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1907 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1908 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1909
46ceb60c
SG		 1910 for (i = 0; i < priv->num_grps; i++) {
1911 regs = priv->gfargrp[i].regs;
1912 /* Clear THLT/RHLT, so that the DMA starts polling now */
1913 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1914 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
46ceb60c 1915 }
12dea57b 1916
c10650b6
CM		 1917 /* Enable Rx/Tx DMA */
1918 tempval = gfar_read(&regs->maccfg1);
1919 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1920 gfar_write(&regs->maccfg1, tempval);
1921
efeddce7
CM		 1922 gfar_ints_enable(priv);
1923
c10650b6 1924 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1925}
1926
80ec396c
CM		 1927static void free_grp_irqs(struct gfar_priv_grp *grp)
1928{
1929 free_irq(gfar_irq(grp, TX)->irq, grp);
1930 free_irq(gfar_irq(grp, RX)->irq, grp);
1931 free_irq(gfar_irq(grp, ER)->irq, grp);
1932}
1933
46ceb60c
SG		 1934static int register_grp_irqs(struct gfar_priv_grp *grp)
1935{
1936 struct gfar_private *priv = grp->priv;
1937 struct net_device *dev = priv->ndev;
1938 int err;
1da177e4 1939
1da177e4 1940 /* If the device has multiple interrupts, register for
0977f817
JC		 1941 * them. Otherwise, only register for the one
1942 */
b31a1d8b 1943 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1944 /* Install our interrupt handlers for Error,
0977f817
JC		 1945 * Transmit, and Receive
1946 */
ee873fda
CM		 1947 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1948 gfar_irq(grp, ER)->name, grp);
1949 if (err < 0) {
59deab26 1950 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1951 gfar_irq(grp, ER)->irq);
46ceb60c 1952
2145f1af 1953 goto err_irq_fail;
1da177e4 1954 }
ee873fda
CM		 1955 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1956 gfar_irq(grp, TX)->name, grp);
1957 if (err < 0) {
59deab26 1958 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1959 gfar_irq(grp, TX)->irq);
1da177e4
LT		 1960 goto tx_irq_fail;
1961 }
ee873fda
CM		 1962 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1963 gfar_irq(grp, RX)->name, grp);
1964 if (err < 0) {
59deab26 1965 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1966 gfar_irq(grp, RX)->irq);
1da177e4
LT		 1967 goto rx_irq_fail;
1968 }
1969 } else {
ee873fda
CM		 1970 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1971 gfar_irq(grp, TX)->name, grp);
1972 if (err < 0) {
59deab26 1973 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1974 gfar_irq(grp, TX)->irq);
1da177e4
LT		 1975 goto err_irq_fail;
1976 }
1977 }
1978
46ceb60c
SG		 1979 return 0;
1980
1981rx_irq_fail:
ee873fda 1982 free_irq(gfar_irq(grp, TX)->irq, grp);
46ceb60c 1983tx_irq_fail:
ee873fda 1984 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 1985err_irq_fail:
1986 return err;
1987
1988}
1989
80ec396c
CM		 1990static void gfar_free_irq(struct gfar_private *priv)
1991{
1992 int i;
1993
1994 /* Free the IRQs */
1995 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1996 for (i = 0; i < priv->num_grps; i++)
1997 free_grp_irqs(&priv->gfargrp[i]);
1998 } else {
1999 for (i = 0; i < priv->num_grps; i++)
2000 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2001 &priv->gfargrp[i]);
2002 }
2003}
2004
2005static int gfar_request_irq(struct gfar_private *priv)
2006{
2007 int err, i, j;
2008
2009 for (i = 0; i < priv->num_grps; i++) {
2010 err = register_grp_irqs(&priv->gfargrp[i]);
2011 if (err) {
2012 for (j = 0; j < i; j++)
2013 free_grp_irqs(&priv->gfargrp[j]);
2014 return err;
2015 }
2016 }
2017
2018 return 0;
2019}
2020
46ceb60c
SG		 2021/* Bring the controller up and running */
2022int startup_gfar(struct net_device *ndev)
2023{
2024 struct gfar_private *priv = netdev_priv(ndev);
80ec396c 2025 int err;
46ceb60c 2026
a328ac92 2027 gfar_mac_reset(priv);
46ceb60c 2028
46ceb60c
SG		 2029 err = gfar_alloc_skb_resources(ndev);
2030 if (err)
2031 return err;
2032
a328ac92 2033 gfar_init_tx_rx_base(priv);
46ceb60c 2034
0851133b
CM		 2035 smp_mb__before_clear_bit();
2036 clear_bit(GFAR_DOWN, &priv->state);
2037 smp_mb__after_clear_bit();
2038
2039 /* Start Rx/Tx DMA and enable the interrupts */
c10650b6 2040 gfar_start(priv);
1da177e4 2041
826aa4a0
AV		 2042 phy_start(priv->phydev);
2043
0851133b
CM		 2044 enable_napi(priv);
2045
2046 netif_tx_wake_all_queues(ndev);
2047
1da177e4 2048 return 0;
1da177e4
LT		 2049}
2050
0977f817
JC		 2051/* Called when something needs to use the ethernet device
2052 * Returns 0 for success.
2053 */
1da177e4
LT		 2054static int gfar_enet_open(struct net_device *dev)
2055{
94e8cc35 2056 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 2057 int err;
2058
1da177e4 2059 err = init_phy(dev);
0851133b 2060 if (err)
1da177e4
LT		 2061 return err;
2062
80ec396c
CM		 2063 err = gfar_request_irq(priv);
2064 if (err)
2065 return err;
2066
1da177e4 2067 err = startup_gfar(dev);
0851133b 2068 if (err)
db0e8e3f 2069 return err;
1da177e4 2070
2884e5cc
AV		 2071 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2072
1da177e4
LT		 2073 return err;
2074}
2075
54dc79fe 2076static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 2077{
54dc79fe 2078 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 2079
2080 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 2081
0bbaf069
KG		 2082 return fcb;
2083}
2084
9c4886e5 2085static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
bc4598bc 2086 int fcb_length)
0bbaf069 2087{
0bbaf069
KG		 2088 /* If we're here, it's a IP packet with a TCP or UDP
2089 * payload. We set it to checksum, using a pseudo-header
2090 * we provide
2091 */
3a2e16c8 2092 u8 flags = TXFCB_DEFAULT;
0bbaf069 2093
0977f817
JC		 2094 /* Tell the controller what the protocol is
2095 * And provide the already calculated phcs
2096 */
eddc9ec5 2097 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 2098 flags |= TXFCB_UDP;
4bedb452 2099 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 2100 } else
8da32de5 2101 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 2102
2103 /* l3os is the distance between the start of the
2104 * frame (skb->data) and the start of the IP hdr.
2105 * l4os is the distance between the start of the
0977f817
JC		 2106 * l3 hdr and the l4 hdr
2107 */
9c4886e5 2108 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
cfe1fc77 2109 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2110
7f7f5316 2111 fcb->flags = flags;
0bbaf069
KG		 2112}
2113
7f7f5316 2114void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2115{
7f7f5316 2116 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 2117 fcb->vlctl = vlan_tx_tag_get(skb);
2118}
2119
4669bc90 2120static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
bc4598bc 2121 struct txbd8 *base, int ring_size)
4669bc90
DH		 2122{
2123 struct txbd8 *new_bd = bdp + stride;
2124
2125 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2126}
2127
2128static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
bc4598bc 2129 int ring_size)
4669bc90
DH		 2130{
2131 return skip_txbd(bdp, 1, base, ring_size);
2132}
2133
02d88fb4
CM		 2134/* eTSEC12: csum generation not supported for some fcb offsets */
2135static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2136 unsigned long fcb_addr)
2137{
2138 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2139 (fcb_addr % 0x20) > 0x18);
2140}
2141
2142/* eTSEC76: csum generation for frames larger than 2500 may
2143 * cause excess delays before start of transmission
2144 */
2145static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2146 unsigned int len)
2147{
2148 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2149 (len > 2500));
2150}
2151
0977f817
JC		 2152/* This is called by the kernel when a frame is ready for transmission.
2153 * It is pointed to by the dev->hard_start_xmit function pointer
2154 */
1da177e4
LT		 2155static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2156{
2157 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2158 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2159 struct netdev_queue *txq;
f4983704 2160 struct gfar __iomem *regs = NULL;
0bbaf069 2161 struct txfcb *fcb = NULL;
f0ee7acf 2162 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2163 u32 lstatus;
0d0cffdc
CM		 2164 int i, rq = 0;
2165 int do_tstamp, do_csum, do_vlan;
4669bc90 2166 u32 bufaddr;
fef6108d 2167 unsigned long flags;
50ad076b 2168 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
fba4ed03
SG		 2169
2170 rq = skb->queue_mapping;
2171 tx_queue = priv->tx_queue[rq];
2172 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2173 base = tx_queue->tx_bd_base;
46ceb60c 2174 regs = tx_queue->grp->regs;
f0ee7acf 2175
0d0cffdc
CM		 2176 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2177 do_vlan = vlan_tx_tag_present(skb);
2178 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2179 priv->hwts_tx_en;
2180
2181 if (do_csum || do_vlan)
2182 fcb_len = GMAC_FCB_LEN;
2183
f0ee7acf 2184 /* check if time stamp should be generated */
0d0cffdc
CM		 2185 if (unlikely(do_tstamp))
2186 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
4669bc90 2187
5b28beaf 2188 /* make space for additional header when fcb is needed */
0d0cffdc 2189 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
54dc79fe
SH		 2190 struct sk_buff *skb_new;
2191
0d0cffdc 2192 skb_new = skb_realloc_headroom(skb, fcb_len);
54dc79fe
SH		 2193 if (!skb_new) {
2194 dev->stats.tx_errors++;
c9974ad4 2195 dev_kfree_skb_any(skb);
54dc79fe
SH		 2196 return NETDEV_TX_OK;
2197 }
db83d136 2198
313b037c
ED		 2199 if (skb->sk)
2200 skb_set_owner_w(skb_new, skb->sk);
c9974ad4 2201 dev_consume_skb_any(skb);
54dc79fe
SH		 2202 skb = skb_new;
2203 }
2204
4669bc90
DH		 2205 /* total number of fragments in the SKB */
2206 nr_frags = skb_shinfo(skb)->nr_frags;
2207
f0ee7acf
MR		 2208 /* calculate the required number of TxBDs for this skb */
2209 if (unlikely(do_tstamp))
2210 nr_txbds = nr_frags + 2;
2211 else
2212 nr_txbds = nr_frags + 1;
2213
4669bc90 2214 /* check if there is space to queue this packet */
f0ee7acf 2215 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2216 /* no space, stop the queue */
fba4ed03 2217 netif_tx_stop_queue(txq);
4669bc90 2218 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2219 return NETDEV_TX_BUSY;
2220 }
1da177e4
LT		 2221
2222 /* Update transmit stats */
50ad076b
CM		 2223 bytes_sent = skb->len;
2224 tx_queue->stats.tx_bytes += bytes_sent;
2225 /* keep Tx bytes on wire for BQL accounting */
2226 GFAR_CB(skb)->bytes_sent = bytes_sent;
1ac9ad13 2227 tx_queue->stats.tx_packets++;
1da177e4 2228
a12f801d 2229 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2230 lstatus = txbdp->lstatus;
2231
2232 /* Time stamp insertion requires one additional TxBD */
2233 if (unlikely(do_tstamp))
2234 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
bc4598bc 2235 tx_queue->tx_ring_size);
1da177e4 2236
4669bc90 2237 if (nr_frags == 0) {
f0ee7acf
MR		 2238 if (unlikely(do_tstamp))
2239 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
bc4598bc 2240 TXBD_INTERRUPT);
f0ee7acf
MR		 2241 else
2242 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2243 } else {
2244 /* Place the fragment addresses and lengths into the TxBDs */
2245 for (i = 0; i < nr_frags; i++) {
50ad076b 2246 unsigned int frag_len;
4669bc90 2247 /* Point at the next BD, wrapping as needed */
a12f801d 2248 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90 2249
50ad076b 2250 frag_len = skb_shinfo(skb)->frags[i].size;
4669bc90 2251
50ad076b 2252 lstatus = txbdp->lstatus | frag_len |
bc4598bc 2253 BD_LFLAG(TXBD_READY);
4669bc90
DH		 2254
2255 /* Handle the last BD specially */
2256 if (i == nr_frags - 1)
2257 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2258
369ec162 2259 bufaddr = skb_frag_dma_map(priv->dev,
2234a722
IC		 2260 &skb_shinfo(skb)->frags[i],
2261 0,
50ad076b 2262 frag_len,
2234a722 2263 DMA_TO_DEVICE);
4669bc90
DH		 2264
2265 /* set the TxBD length and buffer pointer */
2266 txbdp->bufPtr = bufaddr;
2267 txbdp->lstatus = lstatus;
2268 }
2269
2270 lstatus = txbdp_start->lstatus;
2271 }
1da177e4 2272
9c4886e5
MR		 2273 /* Add TxPAL between FCB and frame if required */
2274 if (unlikely(do_tstamp)) {
2275 skb_push(skb, GMAC_TXPAL_LEN);
2276 memset(skb->data, 0, GMAC_TXPAL_LEN);
2277 }
2278
0d0cffdc
CM		 2279 /* Add TxFCB if required */
2280 if (fcb_len) {
54dc79fe 2281 fcb = gfar_add_fcb(skb);
02d88fb4 2282 lstatus |= BD_LFLAG(TXBD_TOE);
0d0cffdc
CM		 2283 }
2284
2285 /* Set up checksumming */
2286 if (do_csum) {
2287 gfar_tx_checksum(skb, fcb, fcb_len);
02d88fb4
CM		 2288
2289 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2290 unlikely(gfar_csum_errata_76(priv, skb->len))) {
4363c2fd
AD		 2291 __skb_pull(skb, GMAC_FCB_LEN);
2292 skb_checksum_help(skb);
0d0cffdc
CM		 2293 if (do_vlan || do_tstamp) {
2294 /* put back a new fcb for vlan/tstamp TOE */
2295 fcb = gfar_add_fcb(skb);
2296 } else {
2297 /* Tx TOE not used */
2298 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2299 fcb = NULL;
2300 }
4363c2fd 2301 }
0bbaf069
KG		 2302 }
2303
0d0cffdc 2304 if (do_vlan)
54dc79fe 2305 gfar_tx_vlan(skb, fcb);
0bbaf069 2306
f0ee7acf
MR		 2307 /* Setup tx hardware time stamping if requested */
2308 if (unlikely(do_tstamp)) {
2244d07b 2309 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf 2310 fcb->ptp = 1;
f0ee7acf
MR		 2311 }
2312
369ec162 2313 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
bc4598bc 2314 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2315
0977f817 2316 /* If time stamping is requested one additional TxBD must be set up. The
f0ee7acf
MR		 2317 * first TxBD points to the FCB and must have a data length of
2318 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2319 * the full frame length.
2320 */
2321 if (unlikely(do_tstamp)) {
0d0cffdc 2322 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
f0ee7acf 2323 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
0d0cffdc 2324 (skb_headlen(skb) - fcb_len);
f0ee7acf
MR		 2325 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2326 } else {
2327 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2328 }
1da177e4 2329
50ad076b 2330 netdev_tx_sent_queue(txq, bytes_sent);
d8a0f1b0 2331
0977f817 2332 /* We can work in parallel with gfar_clean_tx_ring(), except
a3bc1f11
AV		 2333 * when modifying num_txbdfree. Note that we didn't grab the lock
2334 * when we were reading the num_txbdfree and checking for available
2335 * space, that's because outside of this function it can only grow,
2336 * and once we've got needed space, it cannot suddenly disappear.
2337 *
2338 * The lock also protects us from gfar_error(), which can modify
2339 * regs->tstat and thus retrigger the transfers, which is why we
2340 * also must grab the lock before setting ready bit for the first
2341 * to be transmitted BD.
2342 */
2343 spin_lock_irqsave(&tx_queue->txlock, flags);
2344
0977f817 2345 /* The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2346 * semantics (it requires synchronization between cacheable and
2347 * uncacheable mappings, which eieio doesn't provide and which we
2348 * don't need), thus requiring a more expensive sync instruction. At
2349 * some point, the set of architecture-independent barrier functions
2350 * should be expanded to include weaker barriers.
2351 */
3b6330ce 2352 eieio();
7f7f5316 2353
4669bc90
DH		 2354 txbdp_start->lstatus = lstatus;
2355
0eddba52
AV		 2356 eieio(); /* force lstatus write before tx_skbuff */
2357
2358 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2359
4669bc90 2360 /* Update the current skb pointer to the next entry we will use
0977f817
JC		 2361 * (wrapping if necessary)
2362 */
a12f801d 2363 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
bc4598bc 2364 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2365
a12f801d 2366 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2367
2368 /* reduce TxBD free count */
f0ee7acf 2369 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2370
2371 /* If the next BD still needs to be cleaned up, then the bds
0977f817
JC		 2372 * are full. We need to tell the kernel to stop sending us stuff.
2373 */
a12f801d 2374 if (!tx_queue->num_txbdfree) {
fba4ed03 2375 netif_tx_stop_queue(txq);
1da177e4 2376
09f75cd7 2377 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2378 }
2379
1da177e4 2380 /* Tell the DMA to go go go */
fba4ed03 2381 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2382
2383 /* Unlock priv */
a12f801d 2384 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2385
54dc79fe 2386 return NETDEV_TX_OK;
1da177e4
LT		 2387}
2388
2389/* Stops the kernel queue, and halts the controller */
2390static int gfar_close(struct net_device *dev)
2391{
2392 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2393
ab939905 2394 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2395 stop_gfar(dev);
2396
bb40dcbb
AF		 2397 /* Disconnect from the PHY */
2398 phy_disconnect(priv->phydev);
2399 priv->phydev = NULL;
1da177e4 2400
80ec396c
CM		 2401 gfar_free_irq(priv);
2402
1da177e4
LT		 2403 return 0;
2404}
2405
1da177e4 2406/* Changes the mac address if the controller is not running. */
f162b9d5 2407static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2408{
7f7f5316 2409 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2410
2411 return 0;
2412}
2413
1da177e4
LT		 2414static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2415{
1da177e4 2416 struct gfar_private *priv = netdev_priv(dev);
0bbaf069
KG		 2417 int frame_size = new_mtu + ETH_HLEN;
2418
1da177e4 2419 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
59deab26 2420 netif_err(priv, drv, dev, "Invalid MTU setting\n");
1da177e4
LT		 2421 return -EINVAL;
2422 }
2423
0851133b
CM		 2424 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2425 cpu_relax();
2426
88302648 2427 if (dev->flags & IFF_UP)
1da177e4
LT		 2428 stop_gfar(dev);
2429
1da177e4
LT		 2430 dev->mtu = new_mtu;
2431
88302648 2432 if (dev->flags & IFF_UP)
1da177e4
LT		 2433 startup_gfar(dev);
2434
0851133b
CM		 2435 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2436
1da177e4
LT		 2437 return 0;
2438}
2439
0851133b
CM		 2440void reset_gfar(struct net_device *ndev)
2441{
2442 struct gfar_private *priv = netdev_priv(ndev);
2443
2444 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2445 cpu_relax();
2446
2447 stop_gfar(ndev);
2448 startup_gfar(ndev);
2449
2450 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2451}
2452
ab939905 2453/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2454 * transmitted after a set amount of time.
2455 * For now, assume that clearing out all the structures, and
ab939905
SS		 2456 * starting over will fix the problem.
2457 */
2458static void gfar_reset_task(struct work_struct *work)
1da177e4 2459{
ab939905 2460 struct gfar_private *priv = container_of(work, struct gfar_private,
bc4598bc 2461 reset_task);
0851133b 2462 reset_gfar(priv->ndev);
1da177e4
LT		 2463}
2464
ab939905
SS		 2465static void gfar_timeout(struct net_device *dev)
2466{
2467 struct gfar_private *priv = netdev_priv(dev);
2468
2469 dev->stats.tx_errors++;
2470 schedule_work(&priv->reset_task);
2471}
2472
acbc0f03
EL		 2473static void gfar_align_skb(struct sk_buff *skb)
2474{
2475 /* We need the data buffer to be aligned properly. We will reserve
2476 * as many bytes as needed to align the data properly
2477 */
2478 skb_reserve(skb, RXBUF_ALIGNMENT -
bc4598bc 2479 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
acbc0f03
EL		 2480}
2481
1da177e4 2482/* Interrupt Handler for Transmit complete */
c233cf40 2483static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2484{
a12f801d 2485 struct net_device *dev = tx_queue->dev;
d8a0f1b0 2486 struct netdev_queue *txq;
d080cd63 2487 struct gfar_private *priv = netdev_priv(dev);
f0ee7acf 2488 struct txbd8 *bdp, *next = NULL;
4669bc90 2489 struct txbd8 *lbdp = NULL;
a12f801d 2490 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2491 struct sk_buff *skb;
2492 int skb_dirtytx;
a12f801d 2493 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2494 int frags = 0, nr_txbds = 0;
4669bc90 2495 int i;
d080cd63 2496 int howmany = 0;
d8a0f1b0
PG		 2497 int tqi = tx_queue->qindex;
2498 unsigned int bytes_sent = 0;
4669bc90 2499 u32 lstatus;
f0ee7acf 2500 size_t buflen;
1da177e4 2501
d8a0f1b0 2502 txq = netdev_get_tx_queue(dev, tqi);
a12f801d
SG		 2503 bdp = tx_queue->dirty_tx;
2504 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2505
a12f801d 2506 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2507 unsigned long flags;
2508
4669bc90 2509 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf 2510
0977f817 2511 /* When time stamping, one additional TxBD must be freed.
f0ee7acf
MR		 2512 * Also, we need to dma_unmap_single() the TxPAL.
2513 */
2244d07b 2514 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2515 nr_txbds = frags + 2;
2516 else
2517 nr_txbds = frags + 1;
2518
2519 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2520
4669bc90 2521 lstatus = lbdp->lstatus;
1da177e4 2522
4669bc90
DH		 2523 /* Only clean completed frames */
2524 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
bc4598bc 2525 (lstatus & BD_LENGTH_MASK))
4669bc90
DH		 2526 break;
2527
2244d07b 2528 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf 2529 next = next_txbd(bdp, base, tx_ring_size);
9c4886e5 2530 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
f0ee7acf
MR		 2531 } else
2532 buflen = bdp->length;
2533
369ec162 2534 dma_unmap_single(priv->dev, bdp->bufPtr,
bc4598bc 2535 buflen, DMA_TO_DEVICE);
f0ee7acf 2536
2244d07b 2537 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2538 struct skb_shared_hwtstamps shhwtstamps;
2539 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
bc4598bc 2540
f0ee7acf
MR		 2541 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2542 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
9c4886e5 2543 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
f0ee7acf
MR		 2544 skb_tstamp_tx(skb, &shhwtstamps);
2545 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2546 bdp = next;
2547 }
81183059 2548
4669bc90
DH		 2549 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2550 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2551
4669bc90 2552 for (i = 0; i < frags; i++) {
369ec162 2553 dma_unmap_page(priv->dev, bdp->bufPtr,
bc4598bc 2554 bdp->length, DMA_TO_DEVICE);
4669bc90
DH		 2555 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2556 bdp = next_txbd(bdp, base, tx_ring_size);
2557 }
1da177e4 2558
50ad076b 2559 bytes_sent += GFAR_CB(skb)->bytes_sent;
d8a0f1b0 2560
acb600de 2561 dev_kfree_skb_any(skb);
0fd56bb5 2562
a12f801d 2563 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2564
4669bc90 2565 skb_dirtytx = (skb_dirtytx + 1) &
bc4598bc 2566 TX_RING_MOD_MASK(tx_ring_size);
4669bc90
DH		 2567
2568 howmany++;
a3bc1f11 2569 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2570 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2571 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2572 }
1da177e4 2573
4669bc90 2574 /* If we freed a buffer, we can restart transmission, if necessary */
0851133b
CM		 2575 if (tx_queue->num_txbdfree &&
2576 netif_tx_queue_stopped(txq) &&
2577 !(test_bit(GFAR_DOWN, &priv->state)))
2578 netif_wake_subqueue(priv->ndev, tqi);
1da177e4 2579
4669bc90 2580 /* Update dirty indicators */
a12f801d
SG		 2581 tx_queue->skb_dirtytx = skb_dirtytx;
2582 tx_queue->dirty_tx = bdp;
1da177e4 2583
d8a0f1b0 2584 netdev_tx_completed_queue(txq, howmany, bytes_sent);
d080cd63
DH		 2585}
2586
a12f801d 2587static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
bc4598bc 2588 struct sk_buff *skb)
815b97c6 2589{
a12f801d 2590 struct net_device *dev = rx_queue->dev;
815b97c6 2591 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2592 dma_addr_t buf;
815b97c6 2593
369ec162 2594 buf = dma_map_single(priv->dev, skb->data,
8a102fe0 2595 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2596 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2597}
2598
2281a0f3 2599static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2600{
2601 struct gfar_private *priv = netdev_priv(dev);
acb600de 2602 struct sk_buff *skb;
1da177e4 2603
acbc0f03 2604 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2605 if (!skb)
1da177e4
LT		 2606 return NULL;
2607
acbc0f03 2608 gfar_align_skb(skb);
7f7f5316 2609
acbc0f03
EL		 2610 return skb;
2611}
2612
2281a0f3 2613struct sk_buff *gfar_new_skb(struct net_device *dev)
acbc0f03 2614{
acb600de 2615 return gfar_alloc_skb(dev);
1da177e4
LT		 2616}
2617
298e1a9e 2618static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2619{
298e1a9e 2620 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2621 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2622 struct gfar_extra_stats *estats = &priv->extra_stats;
2623
0977f817 2624 /* If the packet was truncated, none of the other errors matter */
1da177e4
LT		 2625 if (status & RXBD_TRUNCATED) {
2626 stats->rx_length_errors++;
2627
212079df 2628 atomic64_inc(&estats->rx_trunc);
1da177e4
LT		 2629
2630 return;
2631 }
2632 /* Count the errors, if there were any */
2633 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2634 stats->rx_length_errors++;
2635
2636 if (status & RXBD_LARGE)
212079df 2637 atomic64_inc(&estats->rx_large);
1da177e4 2638 else
212079df 2639 atomic64_inc(&estats->rx_short);
1da177e4
LT		 2640 }
2641 if (status & RXBD_NONOCTET) {
2642 stats->rx_frame_errors++;
212079df 2643 atomic64_inc(&estats->rx_nonoctet);
1da177e4
LT		 2644 }
2645 if (status & RXBD_CRCERR) {
212079df 2646 atomic64_inc(&estats->rx_crcerr);
1da177e4
LT		 2647 stats->rx_crc_errors++;
2648 }
2649 if (status & RXBD_OVERRUN) {
212079df 2650 atomic64_inc(&estats->rx_overrun);
1da177e4
LT		 2651 stats->rx_crc_errors++;
2652 }
2653}
2654
f4983704 2655irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2656{
aeb12c5e
CM		 2657 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2658 unsigned long flags;
2659 u32 imask;
2660
2661 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2662 spin_lock_irqsave(&grp->grplock, flags);
2663 imask = gfar_read(&grp->regs->imask);
2664 imask &= IMASK_RX_DISABLED;
2665 gfar_write(&grp->regs->imask, imask);
2666 spin_unlock_irqrestore(&grp->grplock, flags);
2667 __napi_schedule(&grp->napi_rx);
2668 } else {
2669 /* Clear IEVENT, so interrupts aren't called again
2670 * because of the packets that have already arrived.
2671 */
2672 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2673 }
2674
2675 return IRQ_HANDLED;
2676}
2677
2678/* Interrupt Handler for Transmit complete */
2679static irqreturn_t gfar_transmit(int irq, void *grp_id)
2680{
2681 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2682 unsigned long flags;
2683 u32 imask;
2684
2685 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2686 spin_lock_irqsave(&grp->grplock, flags);
2687 imask = gfar_read(&grp->regs->imask);
2688 imask &= IMASK_TX_DISABLED;
2689 gfar_write(&grp->regs->imask, imask);
2690 spin_unlock_irqrestore(&grp->grplock, flags);
2691 __napi_schedule(&grp->napi_tx);
2692 } else {
2693 /* Clear IEVENT, so interrupts aren't called again
2694 * because of the packets that have already arrived.
2695 */
2696 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2697 }
2698
1da177e4
LT		 2699 return IRQ_HANDLED;
2700}
2701
0bbaf069
KG		 2702static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2703{
2704 /* If valid headers were found, and valid sums
2705 * were verified, then we tell the kernel that no
0977f817
JC		 2706 * checksumming is necessary. Otherwise, it is [FIXME]
2707 */
7f7f5316 2708 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2709 skb->ip_summed = CHECKSUM_UNNECESSARY;
2710 else
bc8acf2c 2711 skb_checksum_none_assert(skb);
0bbaf069
KG		 2712}
2713
2714
0977f817 2715/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
61db26c6
CM		 2716static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2717 int amount_pull, struct napi_struct *napi)
1da177e4
LT		 2718{
2719 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2720 struct rxfcb *fcb = NULL;
1da177e4 2721
2c2db48a
DH		 2722 /* fcb is at the beginning if exists */
2723 fcb = (struct rxfcb *)skb->data;
0bbaf069 2724
0977f817
JC		 2725 /* Remove the FCB from the skb
2726 * Remove the padded bytes, if there are any
2727 */
f74dac08
SG		 2728 if (amount_pull) {
2729 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2730 skb_pull(skb, amount_pull);
f74dac08 2731 }
0bbaf069 2732
cc772ab7
MR		 2733 /* Get receive timestamp from the skb */
2734 if (priv->hwts_rx_en) {
2735 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2736 u64 *ns = (u64 *) skb->data;
bc4598bc 2737
cc772ab7
MR		 2738 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2739 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2740 }
2741
2742 if (priv->padding)
2743 skb_pull(skb, priv->padding);
2744
8b3afe95 2745 if (dev->features & NETIF_F_RXCSUM)
2c2db48a 2746 gfar_rx_checksum(skb, fcb);
0bbaf069 2747
2c2db48a
DH		 2748 /* Tell the skb what kind of packet this is */
2749 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2750
f646968f 2751 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
32f7fd44
JP		 2752 * Even if vlan rx accel is disabled, on some chips
2753 * RXFCB_VLN is pseudo randomly set.
2754 */
f646968f 2755 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
32f7fd44 2756 fcb->flags & RXFCB_VLN)
e5905c83 2757 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
87c288c6 2758
2c2db48a 2759 /* Send the packet up the stack */
953d2768 2760 napi_gro_receive(napi, skb);
0bbaf069 2761
1da177e4
LT		 2762}
2763
2764/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2281a0f3
JC		 2765 * until the budget/quota has been reached. Returns the number
2766 * of frames handled
1da177e4 2767 */
a12f801d 2768int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2769{
a12f801d 2770 struct net_device *dev = rx_queue->dev;
31de198b 2771 struct rxbd8 *bdp, *base;
1da177e4 2772 struct sk_buff *skb;
2c2db48a
DH		 2773 int pkt_len;
2774 int amount_pull;
1da177e4
LT		 2775 int howmany = 0;
2776 struct gfar_private *priv = netdev_priv(dev);
2777
2778 /* Get the first full descriptor */
a12f801d
SG		 2779 bdp = rx_queue->cur_rx;
2780 base = rx_queue->rx_bd_base;
1da177e4 2781
ba779711 2782 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2c2db48a 2783
1da177e4 2784 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2785 struct sk_buff *newskb;
bc4598bc 2786
3b6330ce 2787 rmb();
815b97c6
AF		 2788
2789 /* Add another skb for the future */
2790 newskb = gfar_new_skb(dev);
2791
a12f801d 2792 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2793
369ec162 2794 dma_unmap_single(priv->dev, bdp->bufPtr,
bc4598bc 2795 priv->rx_buffer_size, DMA_FROM_DEVICE);
81183059 2796
63b88b90 2797 if (unlikely(!(bdp->status & RXBD_ERR) &&
bc4598bc 2798 bdp->length > priv->rx_buffer_size))
63b88b90
AV		 2799 bdp->status = RXBD_LARGE;
2800
815b97c6
AF		 2801 /* We drop the frame if we failed to allocate a new buffer */
2802 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
bc4598bc 2803 bdp->status & RXBD_ERR)) {
815b97c6
AF		 2804 count_errors(bdp->status, dev);
2805
2806 if (unlikely(!newskb))
2807 newskb = skb;
acbc0f03 2808 else if (skb)
acb600de 2809 dev_kfree_skb(skb);
815b97c6 2810 } else {
1da177e4 2811 /* Increment the number of packets */
a7f38041 2812 rx_queue->stats.rx_packets++;
1da177e4
LT		 2813 howmany++;
2814
2c2db48a
DH		 2815 if (likely(skb)) {
2816 pkt_len = bdp->length - ETH_FCS_LEN;
2817 /* Remove the FCS from the packet length */
2818 skb_put(skb, pkt_len);
a7f38041 2819 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2820 skb_record_rx_queue(skb, rx_queue->qindex);
cd754a57 2821 gfar_process_frame(dev, skb, amount_pull,
aeb12c5e 2822 &rx_queue->grp->napi_rx);
2c2db48a
DH		 2823
2824 } else {
59deab26 2825 netif_warn(priv, rx_err, dev, "Missing skb!\n");
a7f38041 2826 rx_queue->stats.rx_dropped++;
212079df 2827 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2c2db48a 2828 }
1da177e4 2829
1da177e4
LT		 2830 }
2831
a12f801d 2832 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2833
815b97c6 2834 /* Setup the new bdp */
a12f801d 2835 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2836
2837 /* Update to the next pointer */
a12f801d 2838 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2839
2840 /* update to point at the next skb */
bc4598bc
JC		 2841 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2842 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2843 }
2844
2845 /* Update the current rxbd pointer to be the next one */
a12f801d 2846 rx_queue->cur_rx = bdp;
1da177e4 2847
1da177e4
LT		 2848 return howmany;
2849}
2850
aeb12c5e 2851static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
5eaedf31
CM		 2852{
2853 struct gfar_priv_grp *gfargrp =
aeb12c5e 2854 container_of(napi, struct gfar_priv_grp, napi_rx);
5eaedf31 2855 struct gfar __iomem *regs = gfargrp->regs;
71ff9e3d 2856 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
5eaedf31
CM		 2857 int work_done = 0;
2858
2859 /* Clear IEVENT, so interrupts aren't called again
2860 * because of the packets that have already arrived
2861 */
aeb12c5e 2862 gfar_write(&regs->ievent, IEVENT_RX_MASK);
5eaedf31
CM		 2863
2864 work_done = gfar_clean_rx_ring(rx_queue, budget);
2865
2866 if (work_done < budget) {
aeb12c5e 2867 u32 imask;
5eaedf31
CM		 2868 napi_complete(napi);
2869 /* Clear the halt bit in RSTAT */
2870 gfar_write(&regs->rstat, gfargrp->rstat);
2871
aeb12c5e
CM		 2872 spin_lock_irq(&gfargrp->grplock);
2873 imask = gfar_read(&regs->imask);
2874 imask |= IMASK_RX_DEFAULT;
2875 gfar_write(&regs->imask, imask);
2876 spin_unlock_irq(&gfargrp->grplock);
5eaedf31
CM		 2877 }
2878
2879 return work_done;
2880}
2881
aeb12c5e 2882static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
1da177e4 2883{
bc4598bc 2884 struct gfar_priv_grp *gfargrp =
aeb12c5e
CM		 2885 container_of(napi, struct gfar_priv_grp, napi_tx);
2886 struct gfar __iomem *regs = gfargrp->regs;
71ff9e3d 2887 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
aeb12c5e
CM		 2888 u32 imask;
2889
2890 /* Clear IEVENT, so interrupts aren't called again
2891 * because of the packets that have already arrived
2892 */
2893 gfar_write(&regs->ievent, IEVENT_TX_MASK);
2894
2895 /* run Tx cleanup to completion */
2896 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2897 gfar_clean_tx_ring(tx_queue);
2898
2899 napi_complete(napi);
2900
2901 spin_lock_irq(&gfargrp->grplock);
2902 imask = gfar_read(&regs->imask);
2903 imask |= IMASK_TX_DEFAULT;
2904 gfar_write(&regs->imask, imask);
2905 spin_unlock_irq(&gfargrp->grplock);
2906
2907 return 0;
2908}
2909
2910static int gfar_poll_rx(struct napi_struct *napi, int budget)
2911{
2912 struct gfar_priv_grp *gfargrp =
2913 container_of(napi, struct gfar_priv_grp, napi_rx);
fba4ed03 2914 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2915 struct gfar __iomem *regs = gfargrp->regs;
fba4ed03 2916 struct gfar_priv_rx_q *rx_queue = NULL;
c233cf40 2917 int work_done = 0, work_done_per_q = 0;
39c0a0d5 2918 int i, budget_per_q = 0;
6be5ed3f
CM		 2919 unsigned long rstat_rxf;
2920 int num_act_queues;
fba4ed03 2921
8c7396ae 2922 /* Clear IEVENT, so interrupts aren't called again
0977f817
JC		 2923 * because of the packets that have already arrived
2924 */
aeb12c5e 2925 gfar_write(&regs->ievent, IEVENT_RX_MASK);
8c7396ae 2926
6be5ed3f
CM		 2927 rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2928
2929 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2930 if (num_act_queues)
2931 budget_per_q = budget/num_act_queues;
2932
3ba405db
CM		 2933 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2934 /* skip queue if not active */
2935 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2936 continue;
1da177e4 2937
3ba405db
CM		 2938 rx_queue = priv->rx_queue[i];
2939 work_done_per_q =
2940 gfar_clean_rx_ring(rx_queue, budget_per_q);
2941 work_done += work_done_per_q;
2942
2943 /* finished processing this queue */
2944 if (work_done_per_q < budget_per_q) {
2945 /* clear active queue hw indication */
2946 gfar_write(&regs->rstat,
2947 RSTAT_CLEAR_RXF0 >> i);
2948 num_act_queues--;
2949
2950 if (!num_act_queues)
2951 break;
2952 }
2953 }
42199884 2954
aeb12c5e
CM		 2955 if (!num_act_queues) {
2956 u32 imask;
3ba405db 2957 napi_complete(napi);
1da177e4 2958
3ba405db
CM		 2959 /* Clear the halt bit in RSTAT */
2960 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2961
aeb12c5e
CM		 2962 spin_lock_irq(&gfargrp->grplock);
2963 imask = gfar_read(&regs->imask);
2964 imask |= IMASK_RX_DEFAULT;
2965 gfar_write(&regs->imask, imask);
2966 spin_unlock_irq(&gfargrp->grplock);
1da177e4
LT		 2967 }
2968
c233cf40 2969 return work_done;
1da177e4 2970}
1da177e4 2971
aeb12c5e
CM		 2972static int gfar_poll_tx(struct napi_struct *napi, int budget)
2973{
2974 struct gfar_priv_grp *gfargrp =
2975 container_of(napi, struct gfar_priv_grp, napi_tx);
2976 struct gfar_private *priv = gfargrp->priv;
2977 struct gfar __iomem *regs = gfargrp->regs;
2978 struct gfar_priv_tx_q *tx_queue = NULL;
2979 int has_tx_work = 0;
2980 int i;
2981
2982 /* Clear IEVENT, so interrupts aren't called again
2983 * because of the packets that have already arrived
2984 */
2985 gfar_write(&regs->ievent, IEVENT_TX_MASK);
2986
2987 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2988 tx_queue = priv->tx_queue[i];
2989 /* run Tx cleanup to completion */
2990 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2991 gfar_clean_tx_ring(tx_queue);
2992 has_tx_work = 1;
2993 }
2994 }
2995
2996 if (!has_tx_work) {
2997 u32 imask;
2998 napi_complete(napi);
2999
3000 spin_lock_irq(&gfargrp->grplock);
3001 imask = gfar_read(&regs->imask);
3002 imask |= IMASK_TX_DEFAULT;
3003 gfar_write(&regs->imask, imask);
3004 spin_unlock_irq(&gfargrp->grplock);
3005 }
3006
3007 return 0;
3008}
3009
3010
f2d71c2d 3011#ifdef CONFIG_NET_POLL_CONTROLLER
0977f817 3012/* Polling 'interrupt' - used by things like netconsole to send skbs
f2d71c2d
VW		 3013 * without having to re-enable interrupts. It's not called while
3014 * the interrupt routine is executing.
3015 */
3016static void gfar_netpoll(struct net_device *dev)
3017{
3018 struct gfar_private *priv = netdev_priv(dev);
3a2e16c8 3019 int i;
f2d71c2d
VW		 3020
3021 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 3022 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c 3023 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 3024 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3025
3026 disable_irq(gfar_irq(grp, TX)->irq);
3027 disable_irq(gfar_irq(grp, RX)->irq);
3028 disable_irq(gfar_irq(grp, ER)->irq);
3029 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3030 enable_irq(gfar_irq(grp, ER)->irq);
3031 enable_irq(gfar_irq(grp, RX)->irq);
3032 enable_irq(gfar_irq(grp, TX)->irq);
46ceb60c 3033 }
f2d71c2d 3034 } else {
46ceb60c 3035 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 3036 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3037
3038 disable_irq(gfar_irq(grp, TX)->irq);
3039 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3040 enable_irq(gfar_irq(grp, TX)->irq);
43de004b 3041 }
f2d71c2d
VW		 3042 }
3043}
3044#endif
3045
1da177e4 3046/* The interrupt handler for devices with one interrupt */
f4983704 3047static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 3048{
f4983704 3049 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 3050
3051 /* Save ievent for future reference */
f4983704 3052 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 3053
1da177e4 3054 /* Check for reception */
538cc7ee 3055 if (events & IEVENT_RX_MASK)
f4983704 3056 gfar_receive(irq, grp_id);
1da177e4
LT		 3057
3058 /* Check for transmit completion */
538cc7ee 3059 if (events & IEVENT_TX_MASK)
f4983704 3060 gfar_transmit(irq, grp_id);
1da177e4 3061
538cc7ee
SS		 3062 /* Check for errors */
3063 if (events & IEVENT_ERR_MASK)
f4983704 3064 gfar_error(irq, grp_id);
1da177e4
LT		 3065
3066 return IRQ_HANDLED;
3067}
3068
23402bdd
CM		 3069static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3070{
3071 struct phy_device *phydev = priv->phydev;
3072 u32 val = 0;
3073
3074 if (!phydev->duplex)
3075 return val;
3076
3077 if (!priv->pause_aneg_en) {
3078 if (priv->tx_pause_en)
3079 val |= MACCFG1_TX_FLOW;
3080 if (priv->rx_pause_en)
3081 val |= MACCFG1_RX_FLOW;
3082 } else {
3083 u16 lcl_adv, rmt_adv;
3084 u8 flowctrl;
3085 /* get link partner capabilities */
3086 rmt_adv = 0;
3087 if (phydev->pause)
3088 rmt_adv = LPA_PAUSE_CAP;
3089 if (phydev->asym_pause)
3090 rmt_adv |= LPA_PAUSE_ASYM;
3091
3092 lcl_adv = mii_advertise_flowctrl(phydev->advertising);
3093
3094 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3095 if (flowctrl & FLOW_CTRL_TX)
3096 val |= MACCFG1_TX_FLOW;
3097 if (flowctrl & FLOW_CTRL_RX)
3098 val |= MACCFG1_RX_FLOW;
3099 }
3100
3101 return val;
3102}
3103
1da177e4
LT		 3104/* Called every time the controller might need to be made
3105 * aware of new link state. The PHY code conveys this
bb40dcbb 3106 * information through variables in the phydev structure, and this
1da177e4
LT		 3107 * function converts those variables into the appropriate
3108 * register values, and can bring down the device if needed.
3109 */
3110static void adjust_link(struct net_device *dev)
3111{
3112 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3113 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 3114 struct phy_device *phydev = priv->phydev;
3115 int new_state = 0;
3116
0851133b
CM		 3117 if (test_bit(GFAR_RESETTING, &priv->state))
3118 return;
fba4ed03 3119
bb40dcbb 3120 if (phydev->link) {
23402bdd 3121 u32 tempval1 = gfar_read(&regs->maccfg1);
bb40dcbb 3122 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 3123 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 3124
1da177e4 3125 /* Now we make sure that we can be in full duplex mode.
0977f817
JC		 3126 * If not, we operate in half-duplex mode.
3127 */
bb40dcbb
AF		 3128 if (phydev->duplex != priv->oldduplex) {
3129 new_state = 1;
3130 if (!(phydev->duplex))
1da177e4 3131 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 3132 else
1da177e4 3133 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 3134
bb40dcbb 3135 priv->oldduplex = phydev->duplex;
1da177e4
LT		 3136 }
3137
bb40dcbb
AF		 3138 if (phydev->speed != priv->oldspeed) {
3139 new_state = 1;
3140 switch (phydev->speed) {
1da177e4 3141 case 1000:
1da177e4
LT		 3142 tempval =
3143 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 3144
3145 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 3146 break;
3147 case 100:
3148 case 10:
1da177e4
LT		 3149 tempval =
3150 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 3151
3152 /* Reduced mode distinguishes
0977f817
JC		 3153 * between 10 and 100
3154 */
7f7f5316
AF		 3155 if (phydev->speed == SPEED_100)
3156 ecntrl |= ECNTRL_R100;
3157 else
3158 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 3159 break;
3160 default:
59deab26
JP		 3161 netif_warn(priv, link, dev,
3162 "Ack! Speed (%d) is not 10/100/1000!\n",
3163 phydev->speed);
1da177e4
LT		 3164 break;
3165 }
3166
bb40dcbb 3167 priv->oldspeed = phydev->speed;
1da177e4
LT		 3168 }
3169
23402bdd
CM		 3170 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3171 tempval1 |= gfar_get_flowctrl_cfg(priv);
3172
3173 gfar_write(&regs->maccfg1, tempval1);
bb40dcbb 3174 gfar_write(&regs->maccfg2, tempval);
7f7f5316 3175 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 3176
1da177e4 3177 if (!priv->oldlink) {
bb40dcbb 3178 new_state = 1;
1da177e4 3179 priv->oldlink = 1;
1da177e4 3180 }
bb40dcbb
AF		 3181 } else if (priv->oldlink) {
3182 new_state = 1;
3183 priv->oldlink = 0;
3184 priv->oldspeed = 0;
3185 priv->oldduplex = -1;
1da177e4 3186 }
1da177e4 3187
bb40dcbb
AF		 3188 if (new_state && netif_msg_link(priv))
3189 phy_print_status(phydev);
bb40dcbb 3190}
1da177e4
LT		 3191
3192/* Update the hash table based on the current list of multicast
3193 * addresses we subscribe to. Also, change the promiscuity of
3194 * the device based on the flags (this function is called
0977f817
JC		 3195 * whenever dev->flags is changed
3196 */
1da177e4
LT		 3197static void gfar_set_multi(struct net_device *dev)
3198{
22bedad3 3199 struct netdev_hw_addr *ha;
1da177e4 3200 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3201 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3202 u32 tempval;
3203
a12f801d 3204 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3205 /* Set RCTRL to PROM */
3206 tempval = gfar_read(&regs->rctrl);
3207 tempval |= RCTRL_PROM;
3208 gfar_write(&regs->rctrl, tempval);
3209 } else {
3210 /* Set RCTRL to not PROM */
3211 tempval = gfar_read(&regs->rctrl);
3212 tempval &= ~(RCTRL_PROM);
3213 gfar_write(&regs->rctrl, tempval);
3214 }
6aa20a22 3215
a12f801d 3216 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3217 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3218 gfar_write(&regs->igaddr0, 0xffffffff);
3219 gfar_write(&regs->igaddr1, 0xffffffff);
3220 gfar_write(&regs->igaddr2, 0xffffffff);
3221 gfar_write(&regs->igaddr3, 0xffffffff);
3222 gfar_write(&regs->igaddr4, 0xffffffff);
3223 gfar_write(&regs->igaddr5, 0xffffffff);
3224 gfar_write(&regs->igaddr6, 0xffffffff);
3225 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3226 gfar_write(&regs->gaddr0, 0xffffffff);
3227 gfar_write(&regs->gaddr1, 0xffffffff);
3228 gfar_write(&regs->gaddr2, 0xffffffff);
3229 gfar_write(&regs->gaddr3, 0xffffffff);
3230 gfar_write(&regs->gaddr4, 0xffffffff);
3231 gfar_write(&regs->gaddr5, 0xffffffff);
3232 gfar_write(&regs->gaddr6, 0xffffffff);
3233 gfar_write(&regs->gaddr7, 0xffffffff);
3234 } else {
7f7f5316
AF		 3235 int em_num;
3236 int idx;
3237
1da177e4 3238 /* zero out the hash */
0bbaf069
KG		 3239 gfar_write(&regs->igaddr0, 0x0);
3240 gfar_write(&regs->igaddr1, 0x0);
3241 gfar_write(&regs->igaddr2, 0x0);
3242 gfar_write(&regs->igaddr3, 0x0);
3243 gfar_write(&regs->igaddr4, 0x0);
3244 gfar_write(&regs->igaddr5, 0x0);
3245 gfar_write(&regs->igaddr6, 0x0);
3246 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3247 gfar_write(&regs->gaddr0, 0x0);
3248 gfar_write(&regs->gaddr1, 0x0);
3249 gfar_write(&regs->gaddr2, 0x0);
3250 gfar_write(&regs->gaddr3, 0x0);
3251 gfar_write(&regs->gaddr4, 0x0);
3252 gfar_write(&regs->gaddr5, 0x0);
3253 gfar_write(&regs->gaddr6, 0x0);
3254 gfar_write(&regs->gaddr7, 0x0);
3255
7f7f5316
AF		 3256 /* If we have extended hash tables, we need to
3257 * clear the exact match registers to prepare for
0977f817
JC		 3258 * setting them
3259 */
7f7f5316
AF		 3260 if (priv->extended_hash) {
3261 em_num = GFAR_EM_NUM + 1;
3262 gfar_clear_exact_match(dev);
3263 idx = 1;
3264 } else {
3265 idx = 0;
3266 em_num = 0;
3267 }
3268
4cd24eaf 3269 if (netdev_mc_empty(dev))
1da177e4
LT		 3270 return;
3271
3272 /* Parse the list, and set the appropriate bits */
22bedad3 3273 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3274 if (idx < em_num) {
22bedad3 3275 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3276 idx++;
3277 } else
22bedad3 3278 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3279 }
3280 }
1da177e4
LT		 3281}
3282
7f7f5316
AF		 3283
3284/* Clears each of the exact match registers to zero, so they
0977f817
JC		 3285 * don't interfere with normal reception
3286 */
7f7f5316
AF		 3287static void gfar_clear_exact_match(struct net_device *dev)
3288{
3289 int idx;
6a3c910c 3290 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
7f7f5316 3291
bc4598bc 3292 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
b6bc7650 3293 gfar_set_mac_for_addr(dev, idx, zero_arr);
7f7f5316
AF		 3294}
3295
1da177e4
LT		 3296/* Set the appropriate hash bit for the given addr */
3297/* The algorithm works like so:
3298 * 1) Take the Destination Address (ie the multicast address), and
3299 * do a CRC on it (little endian), and reverse the bits of the
3300 * result.
3301 * 2) Use the 8 most significant bits as a hash into a 256-entry
3302 * table. The table is controlled through 8 32-bit registers:
3303 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3304 * gaddr7. This means that the 3 most significant bits in the
3305 * hash index which gaddr register to use, and the 5 other bits
3306 * indicate which bit (assuming an IBM numbering scheme, which
3307 * for PowerPC (tm) is usually the case) in the register holds
0977f817
JC		 3308 * the entry.
3309 */
1da177e4
LT		 3310static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3311{
3312 u32 tempval;
3313 struct gfar_private *priv = netdev_priv(dev);
6a3c910c 3314 u32 result = ether_crc(ETH_ALEN, addr);
0bbaf069
KG		 3315 int width = priv->hash_width;
3316 u8 whichbit = (result >> (32 - width)) & 0x1f;
3317 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3318 u32 value = (1 << (31-whichbit));
3319
0bbaf069 3320 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3321 tempval |= value;
0bbaf069 3322 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3323}
3324
7f7f5316
AF		 3325
3326/* There are multiple MAC Address register pairs on some controllers
3327 * This function sets the numth pair to a given address
3328 */
b6bc7650
JP		 3329static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3330 const u8 *addr)
7f7f5316
AF		 3331{
3332 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3333 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316 3334 int idx;
6a3c910c 3335 char tmpbuf[ETH_ALEN];
7f7f5316 3336 u32 tempval;
f4983704 3337 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3338
3339 macptr += num*2;
3340
0977f817
JC		 3341 /* Now copy it into the mac registers backwards, cuz
3342 * little endian is silly
3343 */
6a3c910c
JP		 3344 for (idx = 0; idx < ETH_ALEN; idx++)
3345 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
7f7f5316
AF		 3346
3347 gfar_write(macptr, *((u32 *) (tmpbuf)));
3348
3349 tempval = *((u32 *) (tmpbuf + 4));
3350
3351 gfar_write(macptr+1, tempval);
3352}
3353
1da177e4 3354/* GFAR error interrupt handler */
f4983704 3355static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3356{
f4983704
SG		 3357 struct gfar_priv_grp *gfargrp = grp_id;
3358 struct gfar __iomem *regs = gfargrp->regs;
3359 struct gfar_private *priv= gfargrp->priv;
3360 struct net_device *dev = priv->ndev;
1da177e4
LT		 3361
3362 /* Save ievent for future reference */
f4983704 3363 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3364
3365 /* Clear IEVENT */
f4983704 3366 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3367
3368 /* Magic Packet is not an error. */
b31a1d8b 3369 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3370 (events & IEVENT_MAG))
3371 events &= ~IEVENT_MAG;
1da177e4
LT		 3372
3373 /* Hmm... */
0bbaf069 3374 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
bc4598bc
JC		 3375 netdev_dbg(dev,
3376 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
59deab26 3377 events, gfar_read(&regs->imask));
1da177e4
LT		 3378
3379 /* Update the error counters */
3380 if (events & IEVENT_TXE) {
09f75cd7 3381 dev->stats.tx_errors++;
1da177e4
LT		 3382
3383 if (events & IEVENT_LC)
09f75cd7 3384 dev->stats.tx_window_errors++;
1da177e4 3385 if (events & IEVENT_CRL)
09f75cd7 3386 dev->stats.tx_aborted_errors++;
1da177e4 3387 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3388 unsigned long flags;
3389
59deab26
JP		 3390 netif_dbg(priv, tx_err, dev,
3391 "TX FIFO underrun, packet dropped\n");
09f75cd7 3392 dev->stats.tx_dropped++;
212079df 3393 atomic64_inc(&priv->extra_stats.tx_underrun);
1da177e4 3394
836cf7fa
AV		 3395 local_irq_save(flags);
3396 lock_tx_qs(priv);
3397
1da177e4 3398 /* Reactivate the Tx Queues */
fba4ed03 3399 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3400
3401 unlock_tx_qs(priv);
3402 local_irq_restore(flags);
1da177e4 3403 }
59deab26 3404 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
1da177e4
LT		 3405 }
3406 if (events & IEVENT_BSY) {
09f75cd7 3407 dev->stats.rx_errors++;
212079df 3408 atomic64_inc(&priv->extra_stats.rx_bsy);
1da177e4 3409
f4983704 3410 gfar_receive(irq, grp_id);
1da177e4 3411
59deab26
JP		 3412 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3413 gfar_read(&regs->rstat));
1da177e4
LT		 3414 }
3415 if (events & IEVENT_BABR) {
09f75cd7 3416 dev->stats.rx_errors++;
212079df 3417 atomic64_inc(&priv->extra_stats.rx_babr);
1da177e4 3418
59deab26 3419 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
1da177e4
LT		 3420 }
3421 if (events & IEVENT_EBERR) {
212079df 3422 atomic64_inc(&priv->extra_stats.eberr);
59deab26 3423 netif_dbg(priv, rx_err, dev, "bus error\n");
1da177e4 3424 }
59deab26
JP		 3425 if (events & IEVENT_RXC)
3426 netif_dbg(priv, rx_status, dev, "control frame\n");
1da177e4
LT		 3427
3428 if (events & IEVENT_BABT) {
212079df 3429 atomic64_inc(&priv->extra_stats.tx_babt);
59deab26 3430 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
1da177e4
LT		 3431 }
3432 return IRQ_HANDLED;
3433}
3434
b31a1d8b
AF		 3435static struct of_device_id gfar_match[] =
3436{
3437 {
3438 .type = "network",
3439 .compatible = "gianfar",
3440 },
46ceb60c
SG		 3441 {
3442 .compatible = "fsl,etsec2",
3443 },
b31a1d8b
AF		 3444 {},
3445};
e72701ac 3446MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3447
1da177e4 3448/* Structure for a device driver */
74888760 3449static struct platform_driver gfar_driver = {
4018294b
GL		 3450 .driver = {
3451 .name = "fsl-gianfar",
3452 .owner = THIS_MODULE,
3453 .pm = GFAR_PM_OPS,
3454 .of_match_table = gfar_match,
3455 },
1da177e4
LT		 3456 .probe = gfar_probe,
3457 .remove = gfar_remove,
3458};
3459
db62f684 3460module_platform_driver(gfar_driver);
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