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Merge tag 'nfc-next-4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo...
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / freescale / gianfar.c
CommitLineData
0977f817 1/* drivers/net/ethernet/freescale/gianfar.c
1da177e4
LT		 2 *
3 * Gianfar Ethernet Driver
7f7f5316
AF		 4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
4c8d3d99 9 * Maintainer: Kumar Gala
a12f801d 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 11 *
20862788 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
a12f801d 13 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
0bbaf069 27 *
b31a1d8b
AF		 28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
0bbaf069 38 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
bb40dcbb 42 * of frames or amount of time have passed). In NAPI, the
1da177e4 43 * interrupt handler will signal there is work to be done, and
0aa1538f 44 * exit. This method will start at the last known empty
0bbaf069 45 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
59deab26
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65#define DEBUG
66
1da177e4 67#include <linux/kernel.h>
1da177e4
LT		 68#include <linux/string.h>
69#include <linux/errno.h>
bb40dcbb 70#include <linux/unistd.h>
1da177e4
LT		 71#include <linux/slab.h>
72#include <linux/interrupt.h>
1da177e4
LT		 73#include <linux/delay.h>
74#include <linux/netdevice.h>
75#include <linux/etherdevice.h>
76#include <linux/skbuff.h>
0bbaf069 77#include <linux/if_vlan.h>
1da177e4
LT		 78#include <linux/spinlock.h>
79#include <linux/mm.h>
5af50730
RH		 80#include <linux/of_address.h>
81#include <linux/of_irq.h>
fe192a49 82#include <linux/of_mdio.h>
b31a1d8b 83#include <linux/of_platform.h>
0bbaf069
KG		 84#include <linux/ip.h>
85#include <linux/tcp.h>
86#include <linux/udp.h>
9c07b884 87#include <linux/in.h>
cc772ab7 88#include <linux/net_tstamp.h>
1da177e4
LT		 89
90#include <asm/io.h>
d6ef0bcc 91#ifdef CONFIG_PPC
7d350977 92#include <asm/reg.h>
2969b1f7 93#include <asm/mpc85xx.h>
d6ef0bcc 94#endif
1da177e4
LT		 95#include <asm/irq.h>
96#include <asm/uaccess.h>
97#include <linux/module.h>
1da177e4
LT		 98#include <linux/dma-mapping.h>
99#include <linux/crc32.h>
bb40dcbb
AF		 100#include <linux/mii.h>
101#include <linux/phy.h>
b31a1d8b
AF		 102#include <linux/phy_fixed.h>
103#include <linux/of.h>
4b6ba8aa 104#include <linux/of_net.h>
fd31a952
CM		 105#include <linux/of_address.h>
106#include <linux/of_irq.h>
1da177e4
LT		 107
108#include "gianfar.h"
1da177e4 109
8fcc6033 110#define TX_TIMEOUT (5*HZ)
1da177e4 111
75354148 112const char gfar_driver_version[] = "2.0";
1da177e4 113
1da177e4
LT		 114static int gfar_enet_open(struct net_device *dev);
115static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 116static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 117static void gfar_timeout(struct net_device *dev);
118static int gfar_close(struct net_device *dev);
76f31e8b
CM		 119static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
120 int alloc_cnt);
1da177e4
LT		 121static int gfar_set_mac_address(struct net_device *dev);
122static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 123static irqreturn_t gfar_error(int irq, void *dev_id);
124static irqreturn_t gfar_transmit(int irq, void *dev_id);
125static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4 126static void adjust_link(struct net_device *dev);
6ce29b0e 127static noinline void gfar_update_link_state(struct gfar_private *priv);
1da177e4 128static int init_phy(struct net_device *dev);
74888760 129static int gfar_probe(struct platform_device *ofdev);
2dc11581 130static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 131static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 132static void gfar_set_multi(struct net_device *dev);
133static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 134static void gfar_configure_serdes(struct net_device *dev);
aeb12c5e
CM		 135static int gfar_poll_rx(struct napi_struct *napi, int budget);
136static int gfar_poll_tx(struct napi_struct *napi, int budget);
137static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
f2d71c2d
VW		 139#ifdef CONFIG_NET_POLL_CONTROLLER
140static void gfar_netpoll(struct net_device *dev);
141#endif
a12f801d 142int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
c233cf40 143static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
f23223f1 144static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
c10650b6 145static void gfar_halt_nodisable(struct gfar_private *priv);
7f7f5316 146static void gfar_clear_exact_match(struct net_device *dev);
b6bc7650
JP		 147static void gfar_set_mac_for_addr(struct net_device *dev, int num,
148 const u8 *addr);
26ccfc37 149static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 150
1da177e4
LT		 151MODULE_AUTHOR("Freescale Semiconductor, Inc");
152MODULE_DESCRIPTION("Gianfar Ethernet Driver");
153MODULE_LICENSE("GPL");
154
a12f801d 155static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 156 dma_addr_t buf)
157{
8a102fe0
AV		 158 u32 lstatus;
159
a7312d58 160 bdp->bufPtr = cpu_to_be32(buf);
8a102fe0
AV		 161
162 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 163 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 164 lstatus |= BD_LFLAG(RXBD_WRAP);
165
d55398ba 166 gfar_wmb();
8a102fe0 167
a7312d58 168 bdp->lstatus = cpu_to_be32(lstatus);
8a102fe0
AV		 169}
170
76f31e8b 171static void gfar_init_bds(struct net_device *ndev)
826aa4a0 172{
8728327e 173 struct gfar_private *priv = netdev_priv(ndev);
45b679c9 174 struct gfar __iomem *regs = priv->gfargrp[0].regs;
a12f801d
SG		 175 struct gfar_priv_tx_q *tx_queue = NULL;
176 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0 177 struct txbd8 *txbdp;
03366a33 178 u32 __iomem *rfbptr;
fba4ed03 179 int i, j;
a12f801d 180
fba4ed03
SG		 181 for (i = 0; i < priv->num_tx_queues; i++) {
182 tx_queue = priv->tx_queue[i];
183 /* Initialize some variables in our dev structure */
184 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
185 tx_queue->dirty_tx = tx_queue->tx_bd_base;
186 tx_queue->cur_tx = tx_queue->tx_bd_base;
187 tx_queue->skb_curtx = 0;
188 tx_queue->skb_dirtytx = 0;
189
190 /* Initialize Transmit Descriptor Ring */
191 txbdp = tx_queue->tx_bd_base;
192 for (j = 0; j < tx_queue->tx_ring_size; j++) {
193 txbdp->lstatus = 0;
194 txbdp->bufPtr = 0;
195 txbdp++;
196 }
8728327e 197
fba4ed03
SG		 198 /* Set the last descriptor in the ring to indicate wrap */
199 txbdp--;
a7312d58
CM		 200 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
201 TXBD_WRAP);
8728327e
AV		 202 }
203
45b679c9 204 rfbptr = &regs->rfbptr0;
fba4ed03
SG		 205 for (i = 0; i < priv->num_rx_queues; i++) {
206 rx_queue = priv->rx_queue[i];
8728327e 207
76f31e8b
CM		 208 rx_queue->next_to_clean = 0;
209 rx_queue->next_to_use = 0;
75354148 210 rx_queue->next_to_alloc = 0;
8728327e 211
76f31e8b
CM		 212 /* make sure next_to_clean != next_to_use after this
213 * by leaving at least 1 unused descriptor
214 */
215 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
8728327e 216
45b679c9
MP		 217 rx_queue->rfbptr = rfbptr;
218 rfbptr += 2;
8728327e 219 }
8728327e
AV		 220}
221
222static int gfar_alloc_skb_resources(struct net_device *ndev)
223{
826aa4a0 224 void *vaddr;
fba4ed03 225 dma_addr_t addr;
75354148 226 int i, j;
826aa4a0 227 struct gfar_private *priv = netdev_priv(ndev);
369ec162 228 struct device *dev = priv->dev;
a12f801d
SG		 229 struct gfar_priv_tx_q *tx_queue = NULL;
230 struct gfar_priv_rx_q *rx_queue = NULL;
231
fba4ed03
SG		 232 priv->total_tx_ring_size = 0;
233 for (i = 0; i < priv->num_tx_queues; i++)
234 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
235
236 priv->total_rx_ring_size = 0;
237 for (i = 0; i < priv->num_rx_queues; i++)
238 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 239
240 /* Allocate memory for the buffer descriptors */
8728327e 241 vaddr = dma_alloc_coherent(dev,
d0320f75
JP		 242 (priv->total_tx_ring_size *
243 sizeof(struct txbd8)) +
244 (priv->total_rx_ring_size *
245 sizeof(struct rxbd8)),
246 &addr, GFP_KERNEL);
247 if (!vaddr)
826aa4a0 248 return -ENOMEM;
826aa4a0 249
fba4ed03
SG		 250 for (i = 0; i < priv->num_tx_queues; i++) {
251 tx_queue = priv->tx_queue[i];
43d620c8 252 tx_queue->tx_bd_base = vaddr;
fba4ed03
SG		 253 tx_queue->tx_bd_dma_base = addr;
254 tx_queue->dev = ndev;
255 /* enet DMA only understands physical addresses */
bc4598bc
JC		 256 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
257 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
fba4ed03 258 }
826aa4a0 259
826aa4a0 260 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 261 for (i = 0; i < priv->num_rx_queues; i++) {
262 rx_queue = priv->rx_queue[i];
43d620c8 263 rx_queue->rx_bd_base = vaddr;
fba4ed03 264 rx_queue->rx_bd_dma_base = addr;
f23223f1 265 rx_queue->ndev = ndev;
75354148 266 rx_queue->dev = dev;
bc4598bc
JC		 267 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
268 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
fba4ed03 269 }
826aa4a0
AV		 270
271 /* Setup the skbuff rings */
fba4ed03
SG		 272 for (i = 0; i < priv->num_tx_queues; i++) {
273 tx_queue = priv->tx_queue[i];
14f8dc49
JP		 274 tx_queue->tx_skbuff =
275 kmalloc_array(tx_queue->tx_ring_size,
276 sizeof(*tx_queue->tx_skbuff),
277 GFP_KERNEL);
278 if (!tx_queue->tx_skbuff)
fba4ed03 279 goto cleanup;
826aa4a0 280
75354148
CM		 281 for (j = 0; j < tx_queue->tx_ring_size; j++)
282 tx_queue->tx_skbuff[j] = NULL;
fba4ed03 283 }
826aa4a0 284
fba4ed03
SG		 285 for (i = 0; i < priv->num_rx_queues; i++) {
286 rx_queue = priv->rx_queue[i];
75354148
CM		 287 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
288 sizeof(*rx_queue->rx_buff),
289 GFP_KERNEL);
290 if (!rx_queue->rx_buff)
fba4ed03 291 goto cleanup;
fba4ed03 292 }
826aa4a0 293
76f31e8b 294 gfar_init_bds(ndev);
826aa4a0
AV		 295
296 return 0;
297
298cleanup:
299 free_skb_resources(priv);
300 return -ENOMEM;
301}
302
fba4ed03
SG		 303static void gfar_init_tx_rx_base(struct gfar_private *priv)
304{
46ceb60c 305 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 306 u32 __iomem *baddr;
fba4ed03
SG		 307 int i;
308
309 baddr = &regs->tbase0;
bc4598bc 310 for (i = 0; i < priv->num_tx_queues; i++) {
fba4ed03 311 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
bc4598bc 312 baddr += 2;
fba4ed03
SG		 313 }
314
315 baddr = &regs->rbase0;
bc4598bc 316 for (i = 0; i < priv->num_rx_queues; i++) {
fba4ed03 317 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
bc4598bc 318 baddr += 2;
fba4ed03
SG		 319 }
320}
321
45b679c9
MP		 322static void gfar_init_rqprm(struct gfar_private *priv)
323{
324 struct gfar __iomem *regs = priv->gfargrp[0].regs;
325 u32 __iomem *baddr;
326 int i;
327
328 baddr = &regs->rqprm0;
329 for (i = 0; i < priv->num_rx_queues; i++) {
330 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
331 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
332 baddr++;
333 }
334}
335
75354148 336static void gfar_rx_offload_en(struct gfar_private *priv)
826aa4a0 337{
ba779711
CM		 338 /* set this when rx hw offload (TOE) functions are being used */
339 priv->uses_rxfcb = 0;
340
88302648
CM		 341 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
342 priv->uses_rxfcb = 1;
343
15bf176d 344 if (priv->hwts_rx_en || priv->rx_filer_enable)
88302648 345 priv->uses_rxfcb = 1;
88302648
CM		 346}
347
348static void gfar_mac_rx_config(struct gfar_private *priv)
349{
350 struct gfar __iomem *regs = priv->gfargrp[0].regs;
351 u32 rctrl = 0;
352
1ccb8389 353 if (priv->rx_filer_enable) {
15bf176d 354 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1ccb8389 355 /* Program the RIR0 reg with the required distribution */
71ff9e3d
CM		 356 if (priv->poll_mode == GFAR_SQ_POLLING)
357 gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
358 else /* GFAR_MQ_POLLING */
359 gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
1ccb8389 360 }
826aa4a0 361
f5ae6279 362 /* Restore PROMISC mode */
a328ac92 363 if (priv->ndev->flags & IFF_PROMISC)
f5ae6279
CM		 364 rctrl |= RCTRL_PROM;
365
88302648 366 if (priv->ndev->features & NETIF_F_RXCSUM)
826aa4a0
AV		 367 rctrl |= RCTRL_CHECKSUMMING;
368
88302648
CM		 369 if (priv->extended_hash)
370 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
826aa4a0
AV		 371
372 if (priv->padding) {
373 rctrl &= ~RCTRL_PAL_MASK;
374 rctrl |= RCTRL_PADDING(priv->padding);
375 }
376
97553f7f 377 /* Enable HW time stamping if requested from user space */
88302648 378 if (priv->hwts_rx_en)
97553f7f
MR		 379 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
380
88302648 381 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
b852b720 382 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
826aa4a0 383
45b679c9
MP		 384 /* Clear the LFC bit */
385 gfar_write(&regs->rctrl, rctrl);
386 /* Init flow control threshold values */
387 gfar_init_rqprm(priv);
388 gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
389 rctrl |= RCTRL_LFC;
390
826aa4a0
AV		 391 /* Init rctrl based on our settings */
392 gfar_write(&regs->rctrl, rctrl);
a328ac92 393}
826aa4a0 394
a328ac92
CM		 395static void gfar_mac_tx_config(struct gfar_private *priv)
396{
397 struct gfar __iomem *regs = priv->gfargrp[0].regs;
398 u32 tctrl = 0;
399
400 if (priv->ndev->features & NETIF_F_IP_CSUM)
826aa4a0
AV		 401 tctrl |= TCTRL_INIT_CSUM;
402
b98b8bab
CM		 403 if (priv->prio_sched_en)
404 tctrl |= TCTRL_TXSCHED_PRIO;
405 else {
406 tctrl |= TCTRL_TXSCHED_WRRS;
407 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
408 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
409 }
fba4ed03 410
88302648
CM		 411 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
412 tctrl |= TCTRL_VLINS;
413
826aa4a0 414 gfar_write(&regs->tctrl, tctrl);
826aa4a0
AV		 415}
416
f19015ba
CM		 417static void gfar_configure_coalescing(struct gfar_private *priv,
418 unsigned long tx_mask, unsigned long rx_mask)
419{
420 struct gfar __iomem *regs = priv->gfargrp[0].regs;
421 u32 __iomem *baddr;
422
423 if (priv->mode == MQ_MG_MODE) {
424 int i = 0;
425
426 baddr = &regs->txic0;
427 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
428 gfar_write(baddr + i, 0);
429 if (likely(priv->tx_queue[i]->txcoalescing))
430 gfar_write(baddr + i, priv->tx_queue[i]->txic);
431 }
432
433 baddr = &regs->rxic0;
434 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
435 gfar_write(baddr + i, 0);
436 if (likely(priv->rx_queue[i]->rxcoalescing))
437 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
438 }
439 } else {
440 /* Backward compatible case -- even if we enable
441 * multiple queues, there's only single reg to program
442 */
443 gfar_write(&regs->txic, 0);
444 if (likely(priv->tx_queue[0]->txcoalescing))
445 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
446
447 gfar_write(&regs->rxic, 0);
448 if (unlikely(priv->rx_queue[0]->rxcoalescing))
449 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
450 }
451}
452
453void gfar_configure_coalescing_all(struct gfar_private *priv)
454{
455 gfar_configure_coalescing(priv, 0xFF, 0xFF);
456}
457
a7f38041
SG		 458static struct net_device_stats *gfar_get_stats(struct net_device *dev)
459{
460 struct gfar_private *priv = netdev_priv(dev);
a7f38041
SG		 461 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
462 unsigned long tx_packets = 0, tx_bytes = 0;
3a2e16c8 463 int i;
a7f38041
SG		 464
465 for (i = 0; i < priv->num_rx_queues; i++) {
466 rx_packets += priv->rx_queue[i]->stats.rx_packets;
bc4598bc 467 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
a7f38041
SG		 468 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
469 }
470
471 dev->stats.rx_packets = rx_packets;
bc4598bc 472 dev->stats.rx_bytes = rx_bytes;
a7f38041
SG		 473 dev->stats.rx_dropped = rx_dropped;
474
475 for (i = 0; i < priv->num_tx_queues; i++) {
1ac9ad13
ED		 476 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
477 tx_packets += priv->tx_queue[i]->stats.tx_packets;
a7f38041
SG		 478 }
479
bc4598bc 480 dev->stats.tx_bytes = tx_bytes;
a7f38041
SG		 481 dev->stats.tx_packets = tx_packets;
482
483 return &dev->stats;
484}
485
3d23a05c
CM		 486static int gfar_set_mac_addr(struct net_device *dev, void *p)
487{
488 eth_mac_addr(dev, p);
489
490 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
491
492 return 0;
493}
494
26ccfc37
AF		 495static const struct net_device_ops gfar_netdev_ops = {
496 .ndo_open = gfar_enet_open,
497 .ndo_start_xmit = gfar_start_xmit,
498 .ndo_stop = gfar_close,
499 .ndo_change_mtu = gfar_change_mtu,
8b3afe95 500 .ndo_set_features = gfar_set_features,
afc4b13d 501 .ndo_set_rx_mode = gfar_set_multi,
26ccfc37
AF		 502 .ndo_tx_timeout = gfar_timeout,
503 .ndo_do_ioctl = gfar_ioctl,
a7f38041 504 .ndo_get_stats = gfar_get_stats,
3d23a05c 505 .ndo_set_mac_address = gfar_set_mac_addr,
240c102d 506 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 507#ifdef CONFIG_NET_POLL_CONTROLLER
508 .ndo_poll_controller = gfar_netpoll,
509#endif
510};
511
efeddce7
CM		 512static void gfar_ints_disable(struct gfar_private *priv)
513{
514 int i;
515 for (i = 0; i < priv->num_grps; i++) {
516 struct gfar __iomem *regs = priv->gfargrp[i].regs;
517 /* Clear IEVENT */
518 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
519
520 /* Initialize IMASK */
521 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
522 }
523}
524
525static void gfar_ints_enable(struct gfar_private *priv)
526{
527 int i;
528 for (i = 0; i < priv->num_grps; i++) {
529 struct gfar __iomem *regs = priv->gfargrp[i].regs;
530 /* Unmask the interrupts we look for */
531 gfar_write(&regs->imask, IMASK_DEFAULT);
532 }
533}
534
20862788
CM		 535static int gfar_alloc_tx_queues(struct gfar_private *priv)
536{
537 int i;
538
539 for (i = 0; i < priv->num_tx_queues; i++) {
540 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
541 GFP_KERNEL);
542 if (!priv->tx_queue[i])
543 return -ENOMEM;
544
545 priv->tx_queue[i]->tx_skbuff = NULL;
546 priv->tx_queue[i]->qindex = i;
547 priv->tx_queue[i]->dev = priv->ndev;
548 spin_lock_init(&(priv->tx_queue[i]->txlock));
549 }
550 return 0;
551}
552
553static int gfar_alloc_rx_queues(struct gfar_private *priv)
554{
555 int i;
556
557 for (i = 0; i < priv->num_rx_queues; i++) {
558 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
559 GFP_KERNEL);
560 if (!priv->rx_queue[i])
561 return -ENOMEM;
562
20862788 563 priv->rx_queue[i]->qindex = i;
f23223f1 564 priv->rx_queue[i]->ndev = priv->ndev;
20862788
CM		 565 }
566 return 0;
567}
568
569static void gfar_free_tx_queues(struct gfar_private *priv)
fba4ed03 570{
3a2e16c8 571 int i;
fba4ed03
SG		 572
573 for (i = 0; i < priv->num_tx_queues; i++)
574 kfree(priv->tx_queue[i]);
575}
576
20862788 577static void gfar_free_rx_queues(struct gfar_private *priv)
fba4ed03 578{
3a2e16c8 579 int i;
fba4ed03
SG		 580
581 for (i = 0; i < priv->num_rx_queues; i++)
582 kfree(priv->rx_queue[i]);
583}
584
46ceb60c
SG		 585static void unmap_group_regs(struct gfar_private *priv)
586{
3a2e16c8 587 int i;
46ceb60c
SG		 588
589 for (i = 0; i < MAXGROUPS; i++)
590 if (priv->gfargrp[i].regs)
591 iounmap(priv->gfargrp[i].regs);
592}
593
ee873fda
CM		 594static void free_gfar_dev(struct gfar_private *priv)
595{
596 int i, j;
597
598 for (i = 0; i < priv->num_grps; i++)
599 for (j = 0; j < GFAR_NUM_IRQS; j++) {
600 kfree(priv->gfargrp[i].irqinfo[j]);
601 priv->gfargrp[i].irqinfo[j] = NULL;
602 }
603
604 free_netdev(priv->ndev);
605}
606
46ceb60c
SG		 607static void disable_napi(struct gfar_private *priv)
608{
3a2e16c8 609 int i;
46ceb60c 610
aeb12c5e
CM		 611 for (i = 0; i < priv->num_grps; i++) {
612 napi_disable(&priv->gfargrp[i].napi_rx);
613 napi_disable(&priv->gfargrp[i].napi_tx);
614 }
46ceb60c
SG		 615}
616
617static void enable_napi(struct gfar_private *priv)
618{
3a2e16c8 619 int i;
46ceb60c 620
aeb12c5e
CM		 621 for (i = 0; i < priv->num_grps; i++) {
622 napi_enable(&priv->gfargrp[i].napi_rx);
623 napi_enable(&priv->gfargrp[i].napi_tx);
624 }
46ceb60c
SG		 625}
626
627static int gfar_parse_group(struct device_node *np,
bc4598bc 628 struct gfar_private *priv, const char *model)
46ceb60c 629{
5fedcc14 630 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
ee873fda
CM		 631 int i;
632
7c1e7e99
PG		 633 for (i = 0; i < GFAR_NUM_IRQS; i++) {
634 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
635 GFP_KERNEL);
636 if (!grp->irqinfo[i])
ee873fda 637 return -ENOMEM;
ee873fda 638 }
46ceb60c 639
5fedcc14
CM		 640 grp->regs = of_iomap(np, 0);
641 if (!grp->regs)
46ceb60c
SG		 642 return -ENOMEM;
643
ee873fda 644 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
46ceb60c
SG		 645
646 /* If we aren't the FEC we have multiple interrupts */
647 if (model && strcasecmp(model, "FEC")) {
ee873fda
CM		 648 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
649 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
fea0f665
MB		 650 if (!gfar_irq(grp, TX)->irq ||
651 !gfar_irq(grp, RX)->irq ||
652 !gfar_irq(grp, ER)->irq)
46ceb60c 653 return -EINVAL;
46ceb60c
SG		 654 }
655
5fedcc14
CM		 656 grp->priv = priv;
657 spin_lock_init(&grp->grplock);
bc4598bc 658 if (priv->mode == MQ_MG_MODE) {
55917641
JL		 659 u32 rxq_mask, txq_mask;
660 int ret;
661
662 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
663 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
664
665 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
666 if (!ret) {
667 grp->rx_bit_map = rxq_mask ?
668 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
669 }
670
671 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
672 if (!ret) {
673 grp->tx_bit_map = txq_mask ?
674 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
675 }
71ff9e3d
CM		 676
677 if (priv->poll_mode == GFAR_SQ_POLLING) {
678 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
679 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
680 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
71ff9e3d 681 }
46ceb60c 682 } else {
5fedcc14
CM		 683 grp->rx_bit_map = 0xFF;
684 grp->tx_bit_map = 0xFF;
46ceb60c 685 }
20862788
CM		 686
687 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
688 * right to left, so we need to revert the 8 bits to get the q index
689 */
690 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
691 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
692
693 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
694 * also assign queues to groups
695 */
696 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
71ff9e3d
CM		 697 if (!grp->rx_queue)
698 grp->rx_queue = priv->rx_queue[i];
20862788
CM		 699 grp->num_rx_queues++;
700 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
701 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
702 priv->rx_queue[i]->grp = grp;
703 }
704
705 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
71ff9e3d
CM		 706 if (!grp->tx_queue)
707 grp->tx_queue = priv->tx_queue[i];
20862788
CM		 708 grp->num_tx_queues++;
709 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
710 priv->tqueue |= (TQUEUE_EN0 >> i);
711 priv->tx_queue[i]->grp = grp;
712 }
713
46ceb60c
SG		 714 priv->num_grps++;
715
716 return 0;
717}
718
f50724cd
TW		 719static int gfar_of_group_count(struct device_node *np)
720{
721 struct device_node *child;
722 int num = 0;
723
724 for_each_available_child_of_node(np, child)
725 if (!of_node_cmp(child->name, "queue-group"))
726 num++;
727
728 return num;
729}
730
2dc11581 731static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 732{
b31a1d8b
AF		 733 const char *model;
734 const char *ctype;
735 const void *mac_addr;
fba4ed03
SG		 736 int err = 0, i;
737 struct net_device *dev = NULL;
738 struct gfar_private *priv = NULL;
61c7a080 739 struct device_node *np = ofdev->dev.of_node;
46ceb60c 740 struct device_node *child = NULL;
55917641
JL		 741 u32 stash_len = 0;
742 u32 stash_idx = 0;
fba4ed03 743 unsigned int num_tx_qs, num_rx_qs;
b338ce27 744 unsigned short mode, poll_mode;
b31a1d8b 745
4b222ca6 746 if (!np)
b31a1d8b
AF		 747 return -ENODEV;
748
b338ce27
CM		 749 if (of_device_is_compatible(np, "fsl,etsec2")) {
750 mode = MQ_MG_MODE;
751 poll_mode = GFAR_SQ_POLLING;
752 } else {
753 mode = SQ_SG_MODE;
754 poll_mode = GFAR_SQ_POLLING;
755 }
756
b338ce27 757 if (mode == SQ_SG_MODE) {
71ff9e3d
CM		 758 num_tx_qs = 1;
759 num_rx_qs = 1;
760 } else { /* MQ_MG_MODE */
c65d7533 761 /* get the actual number of supported groups */
f50724cd 762 unsigned int num_grps = gfar_of_group_count(np);
c65d7533
CM		 763
764 if (num_grps == 0 || num_grps > MAXGROUPS) {
765 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
766 num_grps);
767 pr_err("Cannot do alloc_etherdev, aborting\n");
768 return -EINVAL;
769 }
770
b338ce27 771 if (poll_mode == GFAR_SQ_POLLING) {
c65d7533
CM		 772 num_tx_qs = num_grps; /* one txq per int group */
773 num_rx_qs = num_grps; /* one rxq per int group */
71ff9e3d 774 } else { /* GFAR_MQ_POLLING */
55917641
JL		 775 u32 tx_queues, rx_queues;
776 int ret;
777
778 /* parse the num of HW tx and rx queues */
779 ret = of_property_read_u32(np, "fsl,num_tx_queues",
780 &tx_queues);
781 num_tx_qs = ret ? 1 : tx_queues;
782
783 ret = of_property_read_u32(np, "fsl,num_rx_queues",
784 &rx_queues);
785 num_rx_qs = ret ? 1 : rx_queues;
71ff9e3d
CM		 786 }
787 }
fba4ed03
SG		 788
789 if (num_tx_qs > MAX_TX_QS) {
59deab26
JP		 790 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
791 num_tx_qs, MAX_TX_QS);
792 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 793 return -EINVAL;
794 }
795
fba4ed03 796 if (num_rx_qs > MAX_RX_QS) {
59deab26
JP		 797 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
798 num_rx_qs, MAX_RX_QS);
799 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 800 return -EINVAL;
801 }
802
803 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
804 dev = *pdev;
805 if (NULL == dev)
806 return -ENOMEM;
807
808 priv = netdev_priv(dev);
fba4ed03
SG		 809 priv->ndev = dev;
810
b338ce27
CM		 811 priv->mode = mode;
812 priv->poll_mode = poll_mode;
813
fba4ed03 814 priv->num_tx_queues = num_tx_qs;
fe069123 815 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 816 priv->num_rx_queues = num_rx_qs;
20862788
CM		 817
818 err = gfar_alloc_tx_queues(priv);
819 if (err)
820 goto tx_alloc_failed;
821
822 err = gfar_alloc_rx_queues(priv);
823 if (err)
824 goto rx_alloc_failed;
b31a1d8b 825
55917641
JL		 826 err = of_property_read_string(np, "model", &model);
827 if (err) {
828 pr_err("Device model property missing, aborting\n");
829 goto rx_alloc_failed;
830 }
831
0977f817 832 /* Init Rx queue filer rule set linked list */
4aa3a715
SP		 833 INIT_LIST_HEAD(&priv->rx_list.list);
834 priv->rx_list.count = 0;
835 mutex_init(&priv->rx_queue_access);
836
46ceb60c
SG		 837 for (i = 0; i < MAXGROUPS; i++)
838 priv->gfargrp[i].regs = NULL;
b31a1d8b 839
46ceb60c 840 /* Parse and initialize group specific information */
b338ce27 841 if (priv->mode == MQ_MG_MODE) {
f50724cd
TW		 842 for_each_available_child_of_node(np, child) {
843 if (of_node_cmp(child->name, "queue-group"))
844 continue;
845
46ceb60c
SG		 846 err = gfar_parse_group(child, priv, model);
847 if (err)
848 goto err_grp_init;
b31a1d8b 849 }
b338ce27 850 } else { /* SQ_SG_MODE */
46ceb60c 851 err = gfar_parse_group(np, priv, model);
bc4598bc 852 if (err)
46ceb60c 853 goto err_grp_init;
b31a1d8b
AF		 854 }
855
3f8c0f7e 856 if (of_property_read_bool(np, "bd-stash")) {
4d7902f2
AF		 857 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
858 priv->bd_stash_en = 1;
859 }
860
55917641 861 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
4d7902f2 862
55917641
JL		 863 if (err == 0)
864 priv->rx_stash_size = stash_len;
4d7902f2 865
55917641 866 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
4d7902f2 867
55917641
JL		 868 if (err == 0)
869 priv->rx_stash_index = stash_idx;
4d7902f2
AF		 870
871 if (stash_len || stash_idx)
872 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
873
b31a1d8b 874 mac_addr = of_get_mac_address(np);
bc4598bc 875
b31a1d8b 876 if (mac_addr)
6a3c910c 877 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
b31a1d8b
AF		 878
879 if (model && !strcasecmp(model, "TSEC"))
34018fd4 880 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 881 FSL_GIANFAR_DEV_HAS_COALESCE |
882 FSL_GIANFAR_DEV_HAS_RMON |
883 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
884
b31a1d8b 885 if (model && !strcasecmp(model, "eTSEC"))
34018fd4 886 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 887 FSL_GIANFAR_DEV_HAS_COALESCE |
888 FSL_GIANFAR_DEV_HAS_RMON |
889 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
bc4598bc
JC		 890 FSL_GIANFAR_DEV_HAS_CSUM |
891 FSL_GIANFAR_DEV_HAS_VLAN |
892 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
893 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
7bff47da
HM		 894 FSL_GIANFAR_DEV_HAS_TIMER |
895 FSL_GIANFAR_DEV_HAS_RX_FILER;
b31a1d8b 896
55917641 897 err = of_property_read_string(np, "phy-connection-type", &ctype);
b31a1d8b
AF		 898
899 /* We only care about rgmii-id. The rest are autodetected */
55917641 900 if (err == 0 && !strcmp(ctype, "rgmii-id"))
b31a1d8b
AF		 901 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
902 else
903 priv->interface = PHY_INTERFACE_MODE_MII;
904
55917641 905 if (of_find_property(np, "fsl,magic-packet", NULL))
b31a1d8b
AF		 906 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
907
3e905b80
CM		 908 if (of_get_property(np, "fsl,wake-on-filer", NULL))
909 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
910
fe192a49 911 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b 912
be403645
FF		 913 /* In the case of a fixed PHY, the DT node associated
914 * to the PHY is the Ethernet MAC DT node.
915 */
6f2c9bd8 916 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
be403645
FF		 917 err = of_phy_register_fixed_link(np);
918 if (err)
919 goto err_grp_init;
920
6f2c9bd8 921 priv->phy_node = of_node_get(np);
be403645
FF		 922 }
923
b31a1d8b 924 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 925 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 926
927 return 0;
928
46ceb60c
SG		 929err_grp_init:
930 unmap_group_regs(priv);
20862788
CM		 931rx_alloc_failed:
932 gfar_free_rx_queues(priv);
933tx_alloc_failed:
934 gfar_free_tx_queues(priv);
ee873fda 935 free_gfar_dev(priv);
b31a1d8b
AF		 936 return err;
937}
938
ca0c88c2 939static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
cc772ab7
MR		 940{
941 struct hwtstamp_config config;
942 struct gfar_private *priv = netdev_priv(netdev);
943
944 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
945 return -EFAULT;
946
947 /* reserved for future extensions */
948 if (config.flags)
949 return -EINVAL;
950
f0ee7acf
MR		 951 switch (config.tx_type) {
952 case HWTSTAMP_TX_OFF:
953 priv->hwts_tx_en = 0;
954 break;
955 case HWTSTAMP_TX_ON:
956 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
957 return -ERANGE;
958 priv->hwts_tx_en = 1;
959 break;
960 default:
cc772ab7 961 return -ERANGE;
f0ee7acf 962 }
cc772ab7
MR		 963
964 switch (config.rx_filter) {
965 case HWTSTAMP_FILTER_NONE:
97553f7f 966 if (priv->hwts_rx_en) {
97553f7f 967 priv->hwts_rx_en = 0;
0851133b 968 reset_gfar(netdev);
97553f7f 969 }
cc772ab7
MR		 970 break;
971 default:
972 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
973 return -ERANGE;
97553f7f 974 if (!priv->hwts_rx_en) {
97553f7f 975 priv->hwts_rx_en = 1;
0851133b 976 reset_gfar(netdev);
97553f7f 977 }
cc772ab7
MR		 978 config.rx_filter = HWTSTAMP_FILTER_ALL;
979 break;
980 }
981
982 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
983 -EFAULT : 0;
984}
985
ca0c88c2
BH		 986static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
987{
988 struct hwtstamp_config config;
989 struct gfar_private *priv = netdev_priv(netdev);
990
991 config.flags = 0;
992 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
993 config.rx_filter = (priv->hwts_rx_en ?
994 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
995
996 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
997 -EFAULT : 0;
998}
999
0faac9f7
CW		 1000static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1001{
1002 struct gfar_private *priv = netdev_priv(dev);
1003
1004 if (!netif_running(dev))
1005 return -EINVAL;
1006
cc772ab7 1007 if (cmd == SIOCSHWTSTAMP)
ca0c88c2
BH		 1008 return gfar_hwtstamp_set(dev, rq);
1009 if (cmd == SIOCGHWTSTAMP)
1010 return gfar_hwtstamp_get(dev, rq);
cc772ab7 1011
0faac9f7
CW		 1012 if (!priv->phydev)
1013 return -ENODEV;
1014
28b04113 1015 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 1016}
1017
18294ad1
AV		 1018static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1019 u32 class)
7a8b3372
SG		 1020{
1021 u32 rqfpr = FPR_FILER_MASK;
1022 u32 rqfcr = 0x0;
1023
1024 rqfar--;
1025 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
6c43e046
WJB		 1026 priv->ftp_rqfpr[rqfar] = rqfpr;
1027 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 1028 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1029
1030 rqfar--;
1031 rqfcr = RQFCR_CMP_NOMATCH;
6c43e046
WJB		 1032 priv->ftp_rqfpr[rqfar] = rqfpr;
1033 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 1034 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1035
1036 rqfar--;
1037 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1038 rqfpr = class;
6c43e046
WJB		 1039 priv->ftp_rqfcr[rqfar] = rqfcr;
1040 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1041 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1042
1043 rqfar--;
1044 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1045 rqfpr = class;
6c43e046
WJB		 1046 priv->ftp_rqfcr[rqfar] = rqfcr;
1047 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1048 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1049
1050 return rqfar;
1051}
1052
1053static void gfar_init_filer_table(struct gfar_private *priv)
1054{
1055 int i = 0x0;
1056 u32 rqfar = MAX_FILER_IDX;
1057 u32 rqfcr = 0x0;
1058 u32 rqfpr = FPR_FILER_MASK;
1059
1060 /* Default rule */
1061 rqfcr = RQFCR_CMP_MATCH;
6c43e046
WJB		 1062 priv->ftp_rqfcr[rqfar] = rqfcr;
1063 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1064 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1065
1066 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1067 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1068 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1069 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1070 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1071 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1072
85dd08eb 1073 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 1074 priv->cur_filer_idx = rqfar;
1075
1076 /* Rest are masked rules */
1077 rqfcr = RQFCR_CMP_NOMATCH;
1078 for (i = 0; i < rqfar; i++) {
6c43e046
WJB		 1079 priv->ftp_rqfcr[i] = rqfcr;
1080 priv->ftp_rqfpr[i] = rqfpr;
7a8b3372
SG		 1081 gfar_write_filer(priv, i, rqfcr, rqfpr);
1082 }
1083}
1084
d6ef0bcc 1085#ifdef CONFIG_PPC
2969b1f7 1086static void __gfar_detect_errata_83xx(struct gfar_private *priv)
7d350977 1087{
7d350977
AV		 1088 unsigned int pvr = mfspr(SPRN_PVR);
1089 unsigned int svr = mfspr(SPRN_SVR);
1090 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1091 unsigned int rev = svr & 0xffff;
1092
1093 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1094 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
bc4598bc 1095 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
7d350977
AV		 1096 priv->errata |= GFAR_ERRATA_74;
1097
deb90eac
AV		 1098 /* MPC8313 and MPC837x all rev */
1099 if ((pvr == 0x80850010 && mod == 0x80b0) ||
bc4598bc 1100 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
deb90eac
AV		 1101 priv->errata |= GFAR_ERRATA_76;
1102
2969b1f7
CM		 1103 /* MPC8313 Rev < 2.0 */
1104 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1105 priv->errata |= GFAR_ERRATA_12;
1106}
1107
1108static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1109{
1110 unsigned int svr = mfspr(SPRN_SVR);
1111
1112 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
4363c2fd 1113 priv->errata |= GFAR_ERRATA_12;
7bfc6082 1114 /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
53fad773 1115 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
7bfc6082
AN		 1116 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
1117 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
53fad773 1118 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
2969b1f7 1119}
d6ef0bcc 1120#endif
2969b1f7
CM		 1121
1122static void gfar_detect_errata(struct gfar_private *priv)
1123{
1124 struct device *dev = &priv->ofdev->dev;
1125
1126 /* no plans to fix */
1127 priv->errata |= GFAR_ERRATA_A002;
1128
d6ef0bcc 1129#ifdef CONFIG_PPC
2969b1f7
CM		 1130 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1131 __gfar_detect_errata_85xx(priv);
1132 else /* non-mpc85xx parts, i.e. e300 core based */
1133 __gfar_detect_errata_83xx(priv);
d6ef0bcc 1134#endif
4363c2fd 1135
7d350977
AV		 1136 if (priv->errata)
1137 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1138 priv->errata);
1139}
1140
0851133b 1141void gfar_mac_reset(struct gfar_private *priv)
20862788
CM		 1142{
1143 struct gfar __iomem *regs = priv->gfargrp[0].regs;
a328ac92 1144 u32 tempval;
20862788
CM		 1145
1146 /* Reset MAC layer */
1147 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1148
1149 /* We need to delay at least 3 TX clocks */
a328ac92 1150 udelay(3);
20862788
CM		 1151
1152 /* the soft reset bit is not self-resetting, so we need to
1153 * clear it before resuming normal operation
1154 */
1155 gfar_write(&regs->maccfg1, 0);
1156
a328ac92
CM		 1157 udelay(3);
1158
75354148 1159 gfar_rx_offload_en(priv);
88302648
CM		 1160
1161 /* Initialize the max receive frame/buffer lengths */
75354148
CM		 1162 gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1163 gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
a328ac92
CM		 1164
1165 /* Initialize the Minimum Frame Length Register */
1166 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1167
20862788
CM		 1168 /* Initialize MACCFG2. */
1169 tempval = MACCFG2_INIT_SETTINGS;
88302648 1170
75354148
CM		 1171 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1172 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1,
1173 * and by checking RxBD[LG] and discarding larger than MAXFRM.
88302648 1174 */
75354148 1175 if (gfar_has_errata(priv, GFAR_ERRATA_74))
20862788 1176 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
88302648 1177
20862788
CM		 1178 gfar_write(&regs->maccfg2, tempval);
1179
a328ac92
CM		 1180 /* Clear mac addr hash registers */
1181 gfar_write(&regs->igaddr0, 0);
1182 gfar_write(&regs->igaddr1, 0);
1183 gfar_write(&regs->igaddr2, 0);
1184 gfar_write(&regs->igaddr3, 0);
1185 gfar_write(&regs->igaddr4, 0);
1186 gfar_write(&regs->igaddr5, 0);
1187 gfar_write(&regs->igaddr6, 0);
1188 gfar_write(&regs->igaddr7, 0);
1189
1190 gfar_write(&regs->gaddr0, 0);
1191 gfar_write(&regs->gaddr1, 0);
1192 gfar_write(&regs->gaddr2, 0);
1193 gfar_write(&regs->gaddr3, 0);
1194 gfar_write(&regs->gaddr4, 0);
1195 gfar_write(&regs->gaddr5, 0);
1196 gfar_write(&regs->gaddr6, 0);
1197 gfar_write(&regs->gaddr7, 0);
1198
1199 if (priv->extended_hash)
1200 gfar_clear_exact_match(priv->ndev);
1201
1202 gfar_mac_rx_config(priv);
1203
1204 gfar_mac_tx_config(priv);
1205
1206 gfar_set_mac_address(priv->ndev);
1207
1208 gfar_set_multi(priv->ndev);
1209
1210 /* clear ievent and imask before configuring coalescing */
1211 gfar_ints_disable(priv);
1212
1213 /* Configure the coalescing support */
1214 gfar_configure_coalescing_all(priv);
1215}
1216
1217static void gfar_hw_init(struct gfar_private *priv)
1218{
1219 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1220 u32 attrs;
1221
1222 /* Stop the DMA engine now, in case it was running before
1223 * (The firmware could have used it, and left it running).
1224 */
1225 gfar_halt(priv);
1226
1227 gfar_mac_reset(priv);
1228
1229 /* Zero out the rmon mib registers if it has them */
1230 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1231 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1232
1233 /* Mask off the CAM interrupts */
1234 gfar_write(&regs->rmon.cam1, 0xffffffff);
1235 gfar_write(&regs->rmon.cam2, 0xffffffff);
1236 }
1237
20862788
CM		 1238 /* Initialize ECNTRL */
1239 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1240
34018fd4
CM		 1241 /* Set the extraction length and index */
1242 attrs = ATTRELI_EL(priv->rx_stash_size) |
1243 ATTRELI_EI(priv->rx_stash_index);
1244
1245 gfar_write(&regs->attreli, attrs);
1246
1247 /* Start with defaults, and add stashing
1248 * depending on driver parameters
1249 */
1250 attrs = ATTR_INIT_SETTINGS;
1251
1252 if (priv->bd_stash_en)
1253 attrs |= ATTR_BDSTASH;
1254
1255 if (priv->rx_stash_size != 0)
1256 attrs |= ATTR_BUFSTASH;
1257
1258 gfar_write(&regs->attr, attrs);
1259
1260 /* FIFO configs */
1261 gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1262 gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1263 gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1264
20862788
CM		 1265 /* Program the interrupt steering regs, only for MG devices */
1266 if (priv->num_grps > 1)
1267 gfar_write_isrg(priv);
20862788
CM		 1268}
1269
898157ed 1270static void gfar_init_addr_hash_table(struct gfar_private *priv)
20862788
CM		 1271{
1272 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1273
1274 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1275 priv->extended_hash = 1;
1276 priv->hash_width = 9;
1277
1278 priv->hash_regs[0] = &regs->igaddr0;
1279 priv->hash_regs[1] = &regs->igaddr1;
1280 priv->hash_regs[2] = &regs->igaddr2;
1281 priv->hash_regs[3] = &regs->igaddr3;
1282 priv->hash_regs[4] = &regs->igaddr4;
1283 priv->hash_regs[5] = &regs->igaddr5;
1284 priv->hash_regs[6] = &regs->igaddr6;
1285 priv->hash_regs[7] = &regs->igaddr7;
1286 priv->hash_regs[8] = &regs->gaddr0;
1287 priv->hash_regs[9] = &regs->gaddr1;
1288 priv->hash_regs[10] = &regs->gaddr2;
1289 priv->hash_regs[11] = &regs->gaddr3;
1290 priv->hash_regs[12] = &regs->gaddr4;
1291 priv->hash_regs[13] = &regs->gaddr5;
1292 priv->hash_regs[14] = &regs->gaddr6;
1293 priv->hash_regs[15] = &regs->gaddr7;
1294
1295 } else {
1296 priv->extended_hash = 0;
1297 priv->hash_width = 8;
1298
1299 priv->hash_regs[0] = &regs->gaddr0;
1300 priv->hash_regs[1] = &regs->gaddr1;
1301 priv->hash_regs[2] = &regs->gaddr2;
1302 priv->hash_regs[3] = &regs->gaddr3;
1303 priv->hash_regs[4] = &regs->gaddr4;
1304 priv->hash_regs[5] = &regs->gaddr5;
1305 priv->hash_regs[6] = &regs->gaddr6;
1306 priv->hash_regs[7] = &regs->gaddr7;
1307 }
1308}
1309
bb40dcbb 1310/* Set up the ethernet device structure, private data,
0977f817
JC		 1311 * and anything else we need before we start
1312 */
74888760 1313static int gfar_probe(struct platform_device *ofdev)
1da177e4 1314{
1da177e4
LT		 1315 struct net_device *dev = NULL;
1316 struct gfar_private *priv = NULL;
20862788 1317 int err = 0, i;
1da177e4 1318
fba4ed03 1319 err = gfar_of_init(ofdev, &dev);
1da177e4 1320
fba4ed03
SG		 1321 if (err)
1322 return err;
1da177e4
LT		 1323
1324 priv = netdev_priv(dev);
4826857f
KG		 1325 priv->ndev = dev;
1326 priv->ofdev = ofdev;
369ec162 1327 priv->dev = &ofdev->dev;
4826857f 1328 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 1329
ab939905 1330 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 1331
8513fbd8 1332 platform_set_drvdata(ofdev, priv);
1da177e4 1333
7d350977
AV		 1334 gfar_detect_errata(priv);
1335
1da177e4 1336 /* Set the dev->base_addr to the gfar reg region */
20862788 1337 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1da177e4 1338
1da177e4 1339 /* Fill in the dev structure */
1da177e4 1340 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1341 dev->mtu = 1500;
26ccfc37 1342 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1343 dev->ethtool_ops = &gfar_ethtool_ops;
1344
fba4ed03 1345 /* Register for napi ...We are registering NAPI for each grp */
71ff9e3d
CM		 1346 for (i = 0; i < priv->num_grps; i++) {
1347 if (priv->poll_mode == GFAR_SQ_POLLING) {
1348 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1349 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
d64b5e85 1350 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
71ff9e3d
CM		 1351 gfar_poll_tx_sq, 2);
1352 } else {
aeb12c5e
CM		 1353 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1354 gfar_poll_rx, GFAR_DEV_WEIGHT);
d64b5e85 1355 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
aeb12c5e
CM		 1356 gfar_poll_tx, 2);
1357 }
1358 }
a12f801d 1359
b31a1d8b 1360 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
8b3afe95 1361 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1362 NETIF_F_RXCSUM;
8b3afe95 1363 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1364 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
8b3afe95 1365 }
0bbaf069 1366
87c288c6 1367 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
f646968f
PM		 1368 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1369 NETIF_F_HW_VLAN_CTAG_RX;
1370 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
87c288c6 1371 }
0bbaf069 1372
3d23a05c
CM		 1373 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1374
20862788 1375 gfar_init_addr_hash_table(priv);
0bbaf069 1376
532c37bc
CM		 1377 /* Insert receive time stamps into padding alignment bytes */
1378 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1379 priv->padding = 8;
0bbaf069 1380
cc772ab7 1381 if (dev->features & NETIF_F_IP_CSUM ||
bc4598bc 1382 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
bee9e58c 1383 dev->needed_headroom = GMAC_FCB_LEN;
1da177e4 1384
a12f801d 1385 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1386 for (i = 0; i < priv->num_tx_queues; i++) {
1387 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1388 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1389 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1390 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1391 }
a12f801d 1392
fba4ed03
SG		 1393 for (i = 0; i < priv->num_rx_queues; i++) {
1394 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1395 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1396 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1397 }
1da177e4 1398
7bff47da
HM		 1399 /* Always enable rx filer if available */
1400 priv->rx_filer_enable =
1401 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
0bbaf069
KG		 1402 /* Enable most messages by default */
1403 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
b98b8bab
CM		 1404 /* use pritority h/w tx queue scheduling for single queue devices */
1405 if (priv->num_tx_queues == 1)
1406 priv->prio_sched_en = 1;
0bbaf069 1407
0851133b
CM		 1408 set_bit(GFAR_DOWN, &priv->state);
1409
a328ac92 1410 gfar_hw_init(priv);
d3eab82b 1411
d4c642ea
FE		 1412 /* Carrier starts down, phylib will bring it up */
1413 netif_carrier_off(dev);
1414
1da177e4
LT		 1415 err = register_netdev(dev);
1416
1417 if (err) {
59deab26 1418 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1da177e4
LT		 1419 goto register_fail;
1420 }
1421
3e905b80
CM		 1422 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1423 priv->wol_supported |= GFAR_WOL_MAGIC;
1424
1425 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1426 priv->rx_filer_enable)
1427 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1428
1429 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
2884e5cc 1430
c50a5d9a 1431 /* fill out IRQ number and name fields */
46ceb60c 1432 for (i = 0; i < priv->num_grps; i++) {
ee873fda 1433 struct gfar_priv_grp *grp = &priv->gfargrp[i];
46ceb60c 1434 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
ee873fda 1435 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
0015e551 1436 dev->name, "_g", '0' + i, "_tx");
ee873fda 1437 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
0015e551 1438 dev->name, "_g", '0' + i, "_rx");
ee873fda 1439 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
0015e551 1440 dev->name, "_g", '0' + i, "_er");
46ceb60c 1441 } else
ee873fda 1442 strcpy(gfar_irq(grp, TX)->name, dev->name);
46ceb60c 1443 }
c50a5d9a 1444
7a8b3372
SG		 1445 /* Initialize the filer table */
1446 gfar_init_filer_table(priv);
1447
1da177e4 1448 /* Print out the device info */
59deab26 1449 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1da177e4 1450
0977f817
JC		 1451 /* Even more device info helps when determining which kernel
1452 * provided which set of benchmarks.
1453 */
59deab26 1454 netdev_info(dev, "Running with NAPI enabled\n");
fba4ed03 1455 for (i = 0; i < priv->num_rx_queues; i++)
59deab26
JP		 1456 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1457 i, priv->rx_queue[i]->rx_ring_size);
bc4598bc 1458 for (i = 0; i < priv->num_tx_queues; i++)
59deab26
JP		 1459 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1460 i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1461
1462 return 0;
1463
1464register_fail:
46ceb60c 1465 unmap_group_regs(priv);
20862788
CM		 1466 gfar_free_rx_queues(priv);
1467 gfar_free_tx_queues(priv);
888c88b8
UKK		 1468 of_node_put(priv->phy_node);
1469 of_node_put(priv->tbi_node);
ee873fda 1470 free_gfar_dev(priv);
bb40dcbb 1471 return err;
1da177e4
LT		 1472}
1473
2dc11581 1474static int gfar_remove(struct platform_device *ofdev)
1da177e4 1475{
8513fbd8 1476 struct gfar_private *priv = platform_get_drvdata(ofdev);
1da177e4 1477
888c88b8
UKK		 1478 of_node_put(priv->phy_node);
1479 of_node_put(priv->tbi_node);
fe192a49 1480
d9d8e041 1481 unregister_netdev(priv->ndev);
46ceb60c 1482 unmap_group_regs(priv);
20862788
CM		 1483 gfar_free_rx_queues(priv);
1484 gfar_free_tx_queues(priv);
ee873fda 1485 free_gfar_dev(priv);
1da177e4
LT		 1486
1487 return 0;
1488}
1489
d87eb127 1490#ifdef CONFIG_PM
be926fc4 1491
3e905b80
CM		 1492static void __gfar_filer_disable(struct gfar_private *priv)
1493{
1494 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1495 u32 temp;
1496
1497 temp = gfar_read(&regs->rctrl);
1498 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1499 gfar_write(&regs->rctrl, temp);
1500}
1501
1502static void __gfar_filer_enable(struct gfar_private *priv)
1503{
1504 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1505 u32 temp;
1506
1507 temp = gfar_read(&regs->rctrl);
1508 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1509 gfar_write(&regs->rctrl, temp);
1510}
1511
1512/* Filer rules implementing wol capabilities */
1513static void gfar_filer_config_wol(struct gfar_private *priv)
1514{
1515 unsigned int i;
1516 u32 rqfcr;
1517
1518 __gfar_filer_disable(priv);
1519
1520 /* clear the filer table, reject any packet by default */
1521 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1522 for (i = 0; i <= MAX_FILER_IDX; i++)
1523 gfar_write_filer(priv, i, rqfcr, 0);
1524
1525 i = 0;
1526 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1527 /* unicast packet, accept it */
1528 struct net_device *ndev = priv->ndev;
1529 /* get the default rx queue index */
1530 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1531 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1532 (ndev->dev_addr[1] << 8) |
1533 ndev->dev_addr[2];
1534
1535 rqfcr = (qindex << 10) | RQFCR_AND |
1536 RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1537
1538 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1539
1540 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1541 (ndev->dev_addr[4] << 8) |
1542 ndev->dev_addr[5];
1543 rqfcr = (qindex << 10) | RQFCR_GPI |
1544 RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1545 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1546 }
1547
1548 __gfar_filer_enable(priv);
1549}
1550
1551static void gfar_filer_restore_table(struct gfar_private *priv)
1552{
1553 u32 rqfcr, rqfpr;
1554 unsigned int i;
1555
1556 __gfar_filer_disable(priv);
1557
1558 for (i = 0; i <= MAX_FILER_IDX; i++) {
1559 rqfcr = priv->ftp_rqfcr[i];
1560 rqfpr = priv->ftp_rqfpr[i];
1561 gfar_write_filer(priv, i, rqfcr, rqfpr);
1562 }
1563
1564 __gfar_filer_enable(priv);
1565}
1566
1567/* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1568static void gfar_start_wol_filer(struct gfar_private *priv)
1569{
1570 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1571 u32 tempval;
1572 int i = 0;
1573
1574 /* Enable Rx hw queues */
1575 gfar_write(&regs->rqueue, priv->rqueue);
1576
1577 /* Initialize DMACTRL to have WWR and WOP */
1578 tempval = gfar_read(&regs->dmactrl);
1579 tempval |= DMACTRL_INIT_SETTINGS;
1580 gfar_write(&regs->dmactrl, tempval);
1581
1582 /* Make sure we aren't stopped */
1583 tempval = gfar_read(&regs->dmactrl);
1584 tempval &= ~DMACTRL_GRS;
1585 gfar_write(&regs->dmactrl, tempval);
1586
1587 for (i = 0; i < priv->num_grps; i++) {
1588 regs = priv->gfargrp[i].regs;
1589 /* Clear RHLT, so that the DMA starts polling now */
1590 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1591 /* enable the Filer General Purpose Interrupt */
1592 gfar_write(&regs->imask, IMASK_FGPI);
1593 }
1594
1595 /* Enable Rx DMA */
1596 tempval = gfar_read(&regs->maccfg1);
1597 tempval |= MACCFG1_RX_EN;
1598 gfar_write(&regs->maccfg1, tempval);
1599}
1600
be926fc4 1601static int gfar_suspend(struct device *dev)
d87eb127 1602{
be926fc4
AV		 1603 struct gfar_private *priv = dev_get_drvdata(dev);
1604 struct net_device *ndev = priv->ndev;
46ceb60c 1605 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1606 u32 tempval;
3e905b80 1607 u16 wol = priv->wol_opts;
d87eb127 1608
614b4242
CM		 1609 if (!netif_running(ndev))
1610 return 0;
1611
1612 disable_napi(priv);
1613 netif_tx_lock(ndev);
be926fc4 1614 netif_device_detach(ndev);
614b4242 1615 netif_tx_unlock(ndev);
d87eb127 1616
614b4242 1617 gfar_halt(priv);
fba4ed03 1618
3e905b80 1619 if (wol & GFAR_WOL_MAGIC) {
614b4242
CM		 1620 /* Enable interrupt on Magic Packet */
1621 gfar_write(&regs->imask, IMASK_MAG);
d87eb127 1622
614b4242
CM		 1623 /* Enable Magic Packet mode */
1624 tempval = gfar_read(&regs->maccfg2);
1625 tempval |= MACCFG2_MPEN;
1626 gfar_write(&regs->maccfg2, tempval);
d87eb127 1627
614b4242 1628 /* re-enable the Rx block */
f4983704 1629 tempval = gfar_read(&regs->maccfg1);
614b4242 1630 tempval |= MACCFG1_RX_EN;
f4983704 1631 gfar_write(&regs->maccfg1, tempval);
d87eb127 1632
3e905b80
CM		 1633 } else if (wol & GFAR_WOL_FILER_UCAST) {
1634 gfar_filer_config_wol(priv);
1635 gfar_start_wol_filer(priv);
1636
614b4242
CM		 1637 } else {
1638 phy_stop(priv->phydev);
d87eb127
SW		 1639 }
1640
1641 return 0;
1642}
1643
be926fc4 1644static int gfar_resume(struct device *dev)
d87eb127 1645{
be926fc4
AV		 1646 struct gfar_private *priv = dev_get_drvdata(dev);
1647 struct net_device *ndev = priv->ndev;
46ceb60c 1648 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1649 u32 tempval;
3e905b80 1650 u16 wol = priv->wol_opts;
d87eb127 1651
614b4242 1652 if (!netif_running(ndev))
d87eb127 1653 return 0;
d87eb127 1654
3e905b80 1655 if (wol & GFAR_WOL_MAGIC) {
614b4242
CM		 1656 /* Disable Magic Packet mode */
1657 tempval = gfar_read(&regs->maccfg2);
1658 tempval &= ~MACCFG2_MPEN;
1659 gfar_write(&regs->maccfg2, tempval);
3e905b80
CM		 1660
1661 } else if (wol & GFAR_WOL_FILER_UCAST) {
1662 /* need to stop rx only, tx is already down */
1663 gfar_halt(priv);
1664 gfar_filer_restore_table(priv);
1665
614b4242 1666 } else {
d87eb127 1667 phy_start(priv->phydev);
614b4242 1668 }
d87eb127 1669
c10650b6 1670 gfar_start(priv);
d87eb127 1671
be926fc4 1672 netif_device_attach(ndev);
46ceb60c 1673 enable_napi(priv);
be926fc4
AV		 1674
1675 return 0;
1676}
1677
1678static int gfar_restore(struct device *dev)
1679{
1680 struct gfar_private *priv = dev_get_drvdata(dev);
1681 struct net_device *ndev = priv->ndev;
1682
103cdd1d
WD		 1683 if (!netif_running(ndev)) {
1684 netif_device_attach(ndev);
1685
be926fc4 1686 return 0;
103cdd1d 1687 }
be926fc4 1688
76f31e8b 1689 gfar_init_bds(ndev);
1eb8f7a7 1690
a328ac92
CM		 1691 gfar_mac_reset(priv);
1692
1693 gfar_init_tx_rx_base(priv);
1694
c10650b6 1695 gfar_start(priv);
be926fc4
AV		 1696
1697 priv->oldlink = 0;
1698 priv->oldspeed = 0;
1699 priv->oldduplex = -1;
1700
1701 if (priv->phydev)
1702 phy_start(priv->phydev);
d87eb127 1703
be926fc4 1704 netif_device_attach(ndev);
5ea681d4 1705 enable_napi(priv);
d87eb127
SW		 1706
1707 return 0;
1708}
be926fc4
AV		 1709
1710static struct dev_pm_ops gfar_pm_ops = {
1711 .suspend = gfar_suspend,
1712 .resume = gfar_resume,
1713 .freeze = gfar_suspend,
1714 .thaw = gfar_resume,
1715 .restore = gfar_restore,
1716};
1717
1718#define GFAR_PM_OPS (&gfar_pm_ops)
1719
d87eb127 1720#else
be926fc4
AV		 1721
1722#define GFAR_PM_OPS NULL
be926fc4 1723
d87eb127 1724#endif
1da177e4 1725
e8a2b6a4
AF		 1726/* Reads the controller's registers to determine what interface
1727 * connects it to the PHY.
1728 */
1729static phy_interface_t gfar_get_interface(struct net_device *dev)
1730{
1731 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1732 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1733 u32 ecntrl;
1734
f4983704 1735 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1736
1737 if (ecntrl & ECNTRL_SGMII_MODE)
1738 return PHY_INTERFACE_MODE_SGMII;
1739
1740 if (ecntrl & ECNTRL_TBI_MODE) {
1741 if (ecntrl & ECNTRL_REDUCED_MODE)
1742 return PHY_INTERFACE_MODE_RTBI;
1743 else
1744 return PHY_INTERFACE_MODE_TBI;
1745 }
1746
1747 if (ecntrl & ECNTRL_REDUCED_MODE) {
bc4598bc 1748 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
e8a2b6a4 1749 return PHY_INTERFACE_MODE_RMII;
bc4598bc 1750 }
7132ab7f 1751 else {
b31a1d8b 1752 phy_interface_t interface = priv->interface;
7132ab7f 1753
0977f817 1754 /* This isn't autodetected right now, so it must
7132ab7f
AF		 1755 * be set by the device tree or platform code.
1756 */
1757 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1758 return PHY_INTERFACE_MODE_RGMII_ID;
1759
e8a2b6a4 1760 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1761 }
e8a2b6a4
AF		 1762 }
1763
b31a1d8b 1764 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1765 return PHY_INTERFACE_MODE_GMII;
1766
1767 return PHY_INTERFACE_MODE_MII;
1768}
1769
1770
bb40dcbb
AF		 1771/* Initializes driver's PHY state, and attaches to the PHY.
1772 * Returns 0 on success.
1da177e4
LT		 1773 */
1774static int init_phy(struct net_device *dev)
1775{
1776 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1777 uint gigabit_support =
b31a1d8b 1778 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
23402bdd 1779 GFAR_SUPPORTED_GBIT : 0;
e8a2b6a4 1780 phy_interface_t interface;
1da177e4
LT		 1781
1782 priv->oldlink = 0;
1783 priv->oldspeed = 0;
1784 priv->oldduplex = -1;
1785
e8a2b6a4
AF		 1786 interface = gfar_get_interface(dev);
1787
1db780f8
AV		 1788 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1789 interface);
1db780f8
AV		 1790 if (!priv->phydev) {
1791 dev_err(&dev->dev, "could not attach to PHY\n");
1792 return -ENODEV;
fe192a49 1793 }
1da177e4 1794
d3c12873
KJ		 1795 if (interface == PHY_INTERFACE_MODE_SGMII)
1796 gfar_configure_serdes(dev);
1797
bb40dcbb 1798 /* Remove any features not supported by the controller */
fe192a49
GL		 1799 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1800 priv->phydev->advertising = priv->phydev->supported;
1da177e4 1801
cf987afc
PMB		 1802 /* Add support for flow control, but don't advertise it by default */
1803 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1804
1da177e4 1805 return 0;
1da177e4
LT		 1806}
1807
0977f817 1808/* Initialize TBI PHY interface for communicating with the
d0313587
PG		 1809 * SERDES lynx PHY on the chip. We communicate with this PHY
1810 * through the MDIO bus on each controller, treating it as a
1811 * "normal" PHY at the address found in the TBIPA register. We assume
1812 * that the TBIPA register is valid. Either the MDIO bus code will set
1813 * it to a value that doesn't conflict with other PHYs on the bus, or the
1814 * value doesn't matter, as there are no other PHYs on the bus.
1815 */
d3c12873
KJ		 1816static void gfar_configure_serdes(struct net_device *dev)
1817{
1818 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1819 struct phy_device *tbiphy;
1820
1821 if (!priv->tbi_node) {
1822 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1823 "device tree specify a tbi-handle\n");
1824 return;
1825 }
c132419e 1826
fe192a49
GL		 1827 tbiphy = of_phy_find_device(priv->tbi_node);
1828 if (!tbiphy) {
1829 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1830 return;
1831 }
d3c12873 1832
0977f817 1833 /* If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1834 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1835 * everything for us? Resetting it takes the link down and requires
1836 * several seconds for it to come back.
1837 */
38737e49 1838 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
e5a03bfd 1839 put_device(&tbiphy->mdio.dev);
b31a1d8b 1840 return;
38737e49 1841 }
d3c12873 1842
d0313587 1843 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1844 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1845
fe192a49 1846 phy_write(tbiphy, MII_ADVERTISE,
bc4598bc
JC		 1847 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1848 ADVERTISE_1000XPSE_ASYM);
d3c12873 1849
bc4598bc
JC		 1850 phy_write(tbiphy, MII_BMCR,
1851 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1852 BMCR_SPEED1000);
04d53b20 1853
e5a03bfd 1854 put_device(&tbiphy->mdio.dev);
d3c12873
KJ		 1855}
1856
511d934f
AV		 1857static int __gfar_is_rx_idle(struct gfar_private *priv)
1858{
1859 u32 res;
1860
0977f817 1861 /* Normaly TSEC should not hang on GRS commands, so we should
511d934f
AV		 1862 * actually wait for IEVENT_GRSC flag.
1863 */
ad3660c2 1864 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
511d934f
AV		 1865 return 0;
1866
0977f817 1867 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
511d934f
AV		 1868 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1869 * and the Rx can be safely reset.
1870 */
1871 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1872 res &= 0x7f807f80;
1873 if ((res & 0xffff) == (res >> 16))
1874 return 1;
1875
1876 return 0;
1877}
0bbaf069
KG		 1878
1879/* Halt the receive and transmit queues */
c10650b6 1880static void gfar_halt_nodisable(struct gfar_private *priv)
1da177e4 1881{
efeddce7 1882 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 1883 u32 tempval;
a4feee89
CM		 1884 unsigned int timeout;
1885 int stopped;
1da177e4 1886
efeddce7 1887 gfar_ints_disable(priv);
1da177e4 1888
a4feee89
CM		 1889 if (gfar_is_dma_stopped(priv))
1890 return;
1891
1da177e4 1892 /* Stop the DMA, and wait for it to stop */
f4983704 1893 tempval = gfar_read(&regs->dmactrl);
a4feee89
CM		 1894 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1895 gfar_write(&regs->dmactrl, tempval);
1896
1897retry:
1898 timeout = 1000;
1899 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1900 cpu_relax();
1901 timeout--;
1da177e4 1902 }
a4feee89
CM		 1903
1904 if (!timeout)
1905 stopped = gfar_is_dma_stopped(priv);
1906
1907 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1908 !__gfar_is_rx_idle(priv))
1909 goto retry;
d87eb127 1910}
d87eb127
SW		 1911
1912/* Halt the receive and transmit queues */
c10650b6 1913void gfar_halt(struct gfar_private *priv)
d87eb127 1914{
46ceb60c 1915 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1916 u32 tempval;
1da177e4 1917
c10650b6
CM		 1918 /* Dissable the Rx/Tx hw queues */
1919 gfar_write(&regs->rqueue, 0);
1920 gfar_write(&regs->tqueue, 0);
2a54adc3 1921
c10650b6
CM		 1922 mdelay(10);
1923
1924 gfar_halt_nodisable(priv);
1925
1926 /* Disable Rx/Tx DMA */
1da177e4
LT		 1927 tempval = gfar_read(&regs->maccfg1);
1928 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1929 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1930}
1931
1932void stop_gfar(struct net_device *dev)
1933{
1934 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1935
0851133b 1936 netif_tx_stop_all_queues(dev);
bb40dcbb 1937
4e857c58 1938 smp_mb__before_atomic();
0851133b 1939 set_bit(GFAR_DOWN, &priv->state);
4e857c58 1940 smp_mb__after_atomic();
a12f801d 1941
0851133b 1942 disable_napi(priv);
0bbaf069 1943
0851133b 1944 /* disable ints and gracefully shut down Rx/Tx DMA */
c10650b6 1945 gfar_halt(priv);
1da177e4 1946
0851133b 1947 phy_stop(priv->phydev);
1da177e4 1948
1da177e4 1949 free_skb_resources(priv);
1da177e4
LT		 1950}
1951
fba4ed03 1952static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1953{
1da177e4 1954 struct txbd8 *txbdp;
fba4ed03 1955 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1956 int i, j;
1da177e4 1957
a12f801d 1958 txbdp = tx_queue->tx_bd_base;
1da177e4 1959
a12f801d
SG		 1960 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1961 if (!tx_queue->tx_skbuff[i])
4669bc90 1962 continue;
1da177e4 1963
a7312d58
CM		 1964 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1965 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
4669bc90 1966 txbdp->lstatus = 0;
fba4ed03 1967 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
bc4598bc 1968 j++) {
4669bc90 1969 txbdp++;
a7312d58
CM		 1970 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1971 be16_to_cpu(txbdp->length),
1972 DMA_TO_DEVICE);
1da177e4 1973 }
ad5da7ab 1974 txbdp++;
a12f801d
SG		 1975 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1976 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1977 }
a12f801d 1978 kfree(tx_queue->tx_skbuff);
1eb8f7a7 1979 tx_queue->tx_skbuff = NULL;
fba4ed03 1980}
1da177e4 1981
fba4ed03
SG		 1982static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1983{
fba4ed03 1984 int i;
1da177e4 1985
75354148
CM		 1986 struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1987
1988 if (rx_queue->skb)
1989 dev_kfree_skb(rx_queue->skb);
1da177e4 1990
a12f801d 1991 for (i = 0; i < rx_queue->rx_ring_size; i++) {
75354148
CM		 1992 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1993
e69edd21
AV		 1994 rxbdp->lstatus = 0;
1995 rxbdp->bufPtr = 0;
1996 rxbdp++;
75354148
CM		 1997
1998 if (!rxb->page)
1999 continue;
2000
2001 dma_unmap_single(rx_queue->dev, rxb->dma,
2002 PAGE_SIZE, DMA_FROM_DEVICE);
2003 __free_page(rxb->page);
2004
2005 rxb->page = NULL;
1da177e4 2006 }
75354148
CM		 2007
2008 kfree(rx_queue->rx_buff);
2009 rx_queue->rx_buff = NULL;
fba4ed03 2010}
e69edd21 2011
fba4ed03 2012/* If there are any tx skbs or rx skbs still around, free them.
0977f817
JC		 2013 * Then free tx_skbuff and rx_skbuff
2014 */
fba4ed03
SG		 2015static void free_skb_resources(struct gfar_private *priv)
2016{
2017 struct gfar_priv_tx_q *tx_queue = NULL;
2018 struct gfar_priv_rx_q *rx_queue = NULL;
2019 int i;
2020
2021 /* Go through all the buffer descriptors and free their data buffers */
2022 for (i = 0; i < priv->num_tx_queues; i++) {
d8a0f1b0 2023 struct netdev_queue *txq;
bc4598bc 2024
fba4ed03 2025 tx_queue = priv->tx_queue[i];
d8a0f1b0 2026 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
bc4598bc 2027 if (tx_queue->tx_skbuff)
fba4ed03 2028 free_skb_tx_queue(tx_queue);
d8a0f1b0 2029 netdev_tx_reset_queue(txq);
fba4ed03
SG		 2030 }
2031
2032 for (i = 0; i < priv->num_rx_queues; i++) {
2033 rx_queue = priv->rx_queue[i];
75354148 2034 if (rx_queue->rx_buff)
fba4ed03
SG		 2035 free_skb_rx_queue(rx_queue);
2036 }
2037
369ec162 2038 dma_free_coherent(priv->dev,
bc4598bc
JC		 2039 sizeof(struct txbd8) * priv->total_tx_ring_size +
2040 sizeof(struct rxbd8) * priv->total_rx_ring_size,
2041 priv->tx_queue[0]->tx_bd_base,
2042 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 2043}
2044
c10650b6 2045void gfar_start(struct gfar_private *priv)
0bbaf069 2046{
46ceb60c 2047 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 2048 u32 tempval;
46ceb60c 2049 int i = 0;
0bbaf069 2050
c10650b6
CM		 2051 /* Enable Rx/Tx hw queues */
2052 gfar_write(&regs->rqueue, priv->rqueue);
2053 gfar_write(&regs->tqueue, priv->tqueue);
0bbaf069
KG		 2054
2055 /* Initialize DMACTRL to have WWR and WOP */
f4983704 2056 tempval = gfar_read(&regs->dmactrl);
0bbaf069 2057 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 2058 gfar_write(&regs->dmactrl, tempval);
0bbaf069 2059
0bbaf069 2060 /* Make sure we aren't stopped */
f4983704 2061 tempval = gfar_read(&regs->dmactrl);
0bbaf069 2062 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 2063 gfar_write(&regs->dmactrl, tempval);
0bbaf069 2064
46ceb60c
SG		 2065 for (i = 0; i < priv->num_grps; i++) {
2066 regs = priv->gfargrp[i].regs;
2067 /* Clear THLT/RHLT, so that the DMA starts polling now */
2068 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2069 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
46ceb60c 2070 }
12dea57b 2071
c10650b6
CM		 2072 /* Enable Rx/Tx DMA */
2073 tempval = gfar_read(&regs->maccfg1);
2074 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2075 gfar_write(&regs->maccfg1, tempval);
2076
efeddce7
CM		 2077 gfar_ints_enable(priv);
2078
860e9538 2079 netif_trans_update(priv->ndev); /* prevent tx timeout */
0bbaf069
KG		 2080}
2081
80ec396c
CM		 2082static void free_grp_irqs(struct gfar_priv_grp *grp)
2083{
2084 free_irq(gfar_irq(grp, TX)->irq, grp);
2085 free_irq(gfar_irq(grp, RX)->irq, grp);
2086 free_irq(gfar_irq(grp, ER)->irq, grp);
2087}
2088
46ceb60c
SG		 2089static int register_grp_irqs(struct gfar_priv_grp *grp)
2090{
2091 struct gfar_private *priv = grp->priv;
2092 struct net_device *dev = priv->ndev;
2093 int err;
1da177e4 2094
1da177e4 2095 /* If the device has multiple interrupts, register for
0977f817
JC		 2096 * them. Otherwise, only register for the one
2097 */
b31a1d8b 2098 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 2099 /* Install our interrupt handlers for Error,
0977f817
JC		 2100 * Transmit, and Receive
2101 */
d5b8d640 2102 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
ee873fda
CM		 2103 gfar_irq(grp, ER)->name, grp);
2104 if (err < 0) {
59deab26 2105 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2106 gfar_irq(grp, ER)->irq);
46ceb60c 2107
2145f1af 2108 goto err_irq_fail;
1da177e4 2109 }
d5b8d640
SH		 2110 enable_irq_wake(gfar_irq(grp, ER)->irq);
2111
ee873fda
CM		 2112 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2113 gfar_irq(grp, TX)->name, grp);
2114 if (err < 0) {
59deab26 2115 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2116 gfar_irq(grp, TX)->irq);
1da177e4
LT		 2117 goto tx_irq_fail;
2118 }
ee873fda
CM		 2119 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2120 gfar_irq(grp, RX)->name, grp);
2121 if (err < 0) {
59deab26 2122 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2123 gfar_irq(grp, RX)->irq);
1da177e4
LT		 2124 goto rx_irq_fail;
2125 }
3e905b80
CM		 2126 enable_irq_wake(gfar_irq(grp, RX)->irq);
2127
1da177e4 2128 } else {
d5b8d640 2129 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
ee873fda
CM		 2130 gfar_irq(grp, TX)->name, grp);
2131 if (err < 0) {
59deab26 2132 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2133 gfar_irq(grp, TX)->irq);
1da177e4
LT		 2134 goto err_irq_fail;
2135 }
d5b8d640 2136 enable_irq_wake(gfar_irq(grp, TX)->irq);
1da177e4
LT		 2137 }
2138
46ceb60c
SG		 2139 return 0;
2140
2141rx_irq_fail:
ee873fda 2142 free_irq(gfar_irq(grp, TX)->irq, grp);
46ceb60c 2143tx_irq_fail:
ee873fda 2144 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 2145err_irq_fail:
2146 return err;
2147
2148}
2149
80ec396c
CM		 2150static void gfar_free_irq(struct gfar_private *priv)
2151{
2152 int i;
2153
2154 /* Free the IRQs */
2155 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2156 for (i = 0; i < priv->num_grps; i++)
2157 free_grp_irqs(&priv->gfargrp[i]);
2158 } else {
2159 for (i = 0; i < priv->num_grps; i++)
2160 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2161 &priv->gfargrp[i]);
2162 }
2163}
2164
2165static int gfar_request_irq(struct gfar_private *priv)
2166{
2167 int err, i, j;
2168
2169 for (i = 0; i < priv->num_grps; i++) {
2170 err = register_grp_irqs(&priv->gfargrp[i]);
2171 if (err) {
2172 for (j = 0; j < i; j++)
2173 free_grp_irqs(&priv->gfargrp[j]);
2174 return err;
2175 }
2176 }
2177
2178 return 0;
2179}
2180
46ceb60c
SG		 2181/* Bring the controller up and running */
2182int startup_gfar(struct net_device *ndev)
2183{
2184 struct gfar_private *priv = netdev_priv(ndev);
80ec396c 2185 int err;
46ceb60c 2186
a328ac92 2187 gfar_mac_reset(priv);
46ceb60c 2188
46ceb60c
SG		 2189 err = gfar_alloc_skb_resources(ndev);
2190 if (err)
2191 return err;
2192
a328ac92 2193 gfar_init_tx_rx_base(priv);
46ceb60c 2194
4e857c58 2195 smp_mb__before_atomic();
0851133b 2196 clear_bit(GFAR_DOWN, &priv->state);
4e857c58 2197 smp_mb__after_atomic();
0851133b
CM		 2198
2199 /* Start Rx/Tx DMA and enable the interrupts */
c10650b6 2200 gfar_start(priv);
1da177e4 2201
2a4eebf0
CM		 2202 /* force link state update after mac reset */
2203 priv->oldlink = 0;
2204 priv->oldspeed = 0;
2205 priv->oldduplex = -1;
2206
826aa4a0
AV		 2207 phy_start(priv->phydev);
2208
0851133b
CM		 2209 enable_napi(priv);
2210
2211 netif_tx_wake_all_queues(ndev);
2212
1da177e4 2213 return 0;
1da177e4
LT		 2214}
2215
0977f817
JC		 2216/* Called when something needs to use the ethernet device
2217 * Returns 0 for success.
2218 */
1da177e4
LT		 2219static int gfar_enet_open(struct net_device *dev)
2220{
94e8cc35 2221 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 2222 int err;
2223
1da177e4 2224 err = init_phy(dev);
0851133b 2225 if (err)
1da177e4
LT		 2226 return err;
2227
80ec396c
CM		 2228 err = gfar_request_irq(priv);
2229 if (err)
2230 return err;
2231
1da177e4 2232 err = startup_gfar(dev);
0851133b 2233 if (err)
db0e8e3f 2234 return err;
1da177e4
LT		 2235
2236 return err;
2237}
2238
54dc79fe 2239static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 2240{
54dc79fe 2241 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 2242
2243 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 2244
0bbaf069
KG		 2245 return fcb;
2246}
2247
9c4886e5 2248static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
bc4598bc 2249 int fcb_length)
0bbaf069 2250{
0bbaf069
KG		 2251 /* If we're here, it's a IP packet with a TCP or UDP
2252 * payload. We set it to checksum, using a pseudo-header
2253 * we provide
2254 */
3a2e16c8 2255 u8 flags = TXFCB_DEFAULT;
0bbaf069 2256
0977f817
JC		 2257 /* Tell the controller what the protocol is
2258 * And provide the already calculated phcs
2259 */
eddc9ec5 2260 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 2261 flags |= TXFCB_UDP;
26eb9374 2262 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
7f7f5316 2263 } else
26eb9374 2264 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
0bbaf069
KG		 2265
2266 /* l3os is the distance between the start of the
2267 * frame (skb->data) and the start of the IP hdr.
2268 * l4os is the distance between the start of the
0977f817
JC		 2269 * l3 hdr and the l4 hdr
2270 */
26eb9374 2271 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
cfe1fc77 2272 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2273
7f7f5316 2274 fcb->flags = flags;
0bbaf069
KG		 2275}
2276
7f7f5316 2277void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2278{
7f7f5316 2279 fcb->flags |= TXFCB_VLN;
26eb9374 2280 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
0bbaf069
KG		 2281}
2282
4669bc90 2283static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
bc4598bc 2284 struct txbd8 *base, int ring_size)
4669bc90
DH		 2285{
2286 struct txbd8 *new_bd = bdp + stride;
2287
2288 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2289}
2290
2291static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
bc4598bc 2292 int ring_size)
4669bc90
DH		 2293{
2294 return skip_txbd(bdp, 1, base, ring_size);
2295}
2296
02d88fb4
CM		 2297/* eTSEC12: csum generation not supported for some fcb offsets */
2298static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2299 unsigned long fcb_addr)
2300{
2301 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2302 (fcb_addr % 0x20) > 0x18);
2303}
2304
2305/* eTSEC76: csum generation for frames larger than 2500 may
2306 * cause excess delays before start of transmission
2307 */
2308static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2309 unsigned int len)
2310{
2311 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2312 (len > 2500));
2313}
2314
0977f817
JC		 2315/* This is called by the kernel when a frame is ready for transmission.
2316 * It is pointed to by the dev->hard_start_xmit function pointer
2317 */
1da177e4
LT		 2318static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2319{
2320 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2321 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2322 struct netdev_queue *txq;
f4983704 2323 struct gfar __iomem *regs = NULL;
0bbaf069 2324 struct txfcb *fcb = NULL;
f0ee7acf 2325 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2326 u32 lstatus;
42f397ad 2327 skb_frag_t *frag;
0d0cffdc
CM		 2328 int i, rq = 0;
2329 int do_tstamp, do_csum, do_vlan;
4669bc90 2330 u32 bufaddr;
50ad076b 2331 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
fba4ed03
SG		 2332
2333 rq = skb->queue_mapping;
2334 tx_queue = priv->tx_queue[rq];
2335 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2336 base = tx_queue->tx_bd_base;
46ceb60c 2337 regs = tx_queue->grp->regs;
f0ee7acf 2338
0d0cffdc 2339 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
df8a39de 2340 do_vlan = skb_vlan_tag_present(skb);
0d0cffdc
CM		 2341 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2342 priv->hwts_tx_en;
2343
2344 if (do_csum || do_vlan)
2345 fcb_len = GMAC_FCB_LEN;
2346
f0ee7acf 2347 /* check if time stamp should be generated */
0d0cffdc
CM		 2348 if (unlikely(do_tstamp))
2349 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
4669bc90 2350
5b28beaf 2351 /* make space for additional header when fcb is needed */
0d0cffdc 2352 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
54dc79fe
SH		 2353 struct sk_buff *skb_new;
2354
0d0cffdc 2355 skb_new = skb_realloc_headroom(skb, fcb_len);
54dc79fe
SH		 2356 if (!skb_new) {
2357 dev->stats.tx_errors++;
c9974ad4 2358 dev_kfree_skb_any(skb);
54dc79fe
SH		 2359 return NETDEV_TX_OK;
2360 }
db83d136 2361
313b037c
ED		 2362 if (skb->sk)
2363 skb_set_owner_w(skb_new, skb->sk);
c9974ad4 2364 dev_consume_skb_any(skb);
54dc79fe
SH		 2365 skb = skb_new;
2366 }
2367
4669bc90
DH		 2368 /* total number of fragments in the SKB */
2369 nr_frags = skb_shinfo(skb)->nr_frags;
2370
f0ee7acf
MR		 2371 /* calculate the required number of TxBDs for this skb */
2372 if (unlikely(do_tstamp))
2373 nr_txbds = nr_frags + 2;
2374 else
2375 nr_txbds = nr_frags + 1;
2376
4669bc90 2377 /* check if there is space to queue this packet */
f0ee7acf 2378 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2379 /* no space, stop the queue */
fba4ed03 2380 netif_tx_stop_queue(txq);
4669bc90 2381 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2382 return NETDEV_TX_BUSY;
2383 }
1da177e4
LT		 2384
2385 /* Update transmit stats */
50ad076b
CM		 2386 bytes_sent = skb->len;
2387 tx_queue->stats.tx_bytes += bytes_sent;
2388 /* keep Tx bytes on wire for BQL accounting */
2389 GFAR_CB(skb)->bytes_sent = bytes_sent;
1ac9ad13 2390 tx_queue->stats.tx_packets++;
1da177e4 2391
a12f801d 2392 txbdp = txbdp_start = tx_queue->cur_tx;
a7312d58 2393 lstatus = be32_to_cpu(txbdp->lstatus);
f0ee7acf 2394
9c4886e5
MR		 2395 /* Add TxPAL between FCB and frame if required */
2396 if (unlikely(do_tstamp)) {
2397 skb_push(skb, GMAC_TXPAL_LEN);
2398 memset(skb->data, 0, GMAC_TXPAL_LEN);
2399 }
2400
0d0cffdc
CM		 2401 /* Add TxFCB if required */
2402 if (fcb_len) {
54dc79fe 2403 fcb = gfar_add_fcb(skb);
02d88fb4 2404 lstatus |= BD_LFLAG(TXBD_TOE);
0d0cffdc
CM		 2405 }
2406
2407 /* Set up checksumming */
2408 if (do_csum) {
2409 gfar_tx_checksum(skb, fcb, fcb_len);
02d88fb4
CM		 2410
2411 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2412 unlikely(gfar_csum_errata_76(priv, skb->len))) {
4363c2fd
AD		 2413 __skb_pull(skb, GMAC_FCB_LEN);
2414 skb_checksum_help(skb);
0d0cffdc
CM		 2415 if (do_vlan || do_tstamp) {
2416 /* put back a new fcb for vlan/tstamp TOE */
2417 fcb = gfar_add_fcb(skb);
2418 } else {
2419 /* Tx TOE not used */
2420 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2421 fcb = NULL;
2422 }
4363c2fd 2423 }
0bbaf069
KG		 2424 }
2425
0d0cffdc 2426 if (do_vlan)
54dc79fe 2427 gfar_tx_vlan(skb, fcb);
0bbaf069 2428
0a4b5a24
KH		 2429 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2430 DMA_TO_DEVICE);
2431 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2432 goto dma_map_err;
2433
a7312d58 2434 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1da177e4 2435
f0ee7acf
MR		 2436 /* Time stamp insertion requires one additional TxBD */
2437 if (unlikely(do_tstamp))
2438 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
bc4598bc 2439 tx_queue->tx_ring_size);
1da177e4 2440
48963b44
CM		 2441 if (likely(!nr_frags)) {
2442 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90 2443 } else {
e19d0839
CM		 2444 u32 lstatus_start = lstatus;
2445
4669bc90 2446 /* Place the fragment addresses and lengths into the TxBDs */
42f397ad
CM		 2447 frag = &skb_shinfo(skb)->frags[0];
2448 for (i = 0; i < nr_frags; i++, frag++) {
2449 unsigned int size;
2450
4669bc90 2451 /* Point at the next BD, wrapping as needed */
a12f801d 2452 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90 2453
42f397ad 2454 size = skb_frag_size(frag);
4669bc90 2455
42f397ad 2456 lstatus = be32_to_cpu(txbdp->lstatus) | size |
bc4598bc 2457 BD_LFLAG(TXBD_READY);
4669bc90
DH		 2458
2459 /* Handle the last BD specially */
2460 if (i == nr_frags - 1)
2461 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2462
42f397ad
CM		 2463 bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
2464 size, DMA_TO_DEVICE);
0a4b5a24
KH		 2465 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2466 goto dma_map_err;
4669bc90
DH		 2467
2468 /* set the TxBD length and buffer pointer */
a7312d58
CM		 2469 txbdp->bufPtr = cpu_to_be32(bufaddr);
2470 txbdp->lstatus = cpu_to_be32(lstatus);
4669bc90
DH		 2471 }
2472
e19d0839 2473 lstatus = lstatus_start;
4669bc90 2474 }
1da177e4 2475
0977f817 2476 /* If time stamping is requested one additional TxBD must be set up. The
f0ee7acf
MR		 2477 * first TxBD points to the FCB and must have a data length of
2478 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2479 * the full frame length.
2480 */
2481 if (unlikely(do_tstamp)) {
a7312d58
CM		 2482 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2483
2484 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2485 bufaddr += fcb_len;
48963b44 2486
a7312d58
CM		 2487 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2488 (skb_headlen(skb) - fcb_len);
48963b44
CM		 2489 if (!nr_frags)
2490 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
a7312d58
CM		 2491
2492 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2493 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
f0ee7acf 2494 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
e19d0839
CM		 2495
2496 /* Setup tx hardware time stamping */
2497 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2498 fcb->ptp = 1;
f0ee7acf
MR		 2499 } else {
2500 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2501 }
1da177e4 2502
50ad076b 2503 netdev_tx_sent_queue(txq, bytes_sent);
d8a0f1b0 2504
d55398ba 2505 gfar_wmb();
7f7f5316 2506
a7312d58 2507 txbdp_start->lstatus = cpu_to_be32(lstatus);
4669bc90 2508
d55398ba 2509 gfar_wmb(); /* force lstatus write before tx_skbuff */
0eddba52
AV		 2510
2511 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2512
4669bc90 2513 /* Update the current skb pointer to the next entry we will use
0977f817
JC		 2514 * (wrapping if necessary)
2515 */
a12f801d 2516 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
bc4598bc 2517 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2518
a12f801d 2519 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90 2520
bc602280
CM		 2521 /* We can work in parallel with gfar_clean_tx_ring(), except
2522 * when modifying num_txbdfree. Note that we didn't grab the lock
2523 * when we were reading the num_txbdfree and checking for available
2524 * space, that's because outside of this function it can only grow.
2525 */
2526 spin_lock_bh(&tx_queue->txlock);
4669bc90 2527 /* reduce TxBD free count */
f0ee7acf 2528 tx_queue->num_txbdfree -= (nr_txbds);
bc602280 2529 spin_unlock_bh(&tx_queue->txlock);
1da177e4
LT		 2530
2531 /* If the next BD still needs to be cleaned up, then the bds
0977f817
JC		 2532 * are full. We need to tell the kernel to stop sending us stuff.
2533 */
a12f801d 2534 if (!tx_queue->num_txbdfree) {
fba4ed03 2535 netif_tx_stop_queue(txq);
1da177e4 2536
09f75cd7 2537 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2538 }
2539
1da177e4 2540 /* Tell the DMA to go go go */
fba4ed03 2541 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4 2542
54dc79fe 2543 return NETDEV_TX_OK;
0a4b5a24
KH		 2544
2545dma_map_err:
2546 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2547 if (do_tstamp)
2548 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2549 for (i = 0; i < nr_frags; i++) {
a7312d58 2550 lstatus = be32_to_cpu(txbdp->lstatus);
0a4b5a24
KH		 2551 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2552 break;
2553
a7312d58
CM		 2554 lstatus &= ~BD_LFLAG(TXBD_READY);
2555 txbdp->lstatus = cpu_to_be32(lstatus);
2556 bufaddr = be32_to_cpu(txbdp->bufPtr);
2557 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
0a4b5a24
KH		 2558 DMA_TO_DEVICE);
2559 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2560 }
2561 gfar_wmb();
2562 dev_kfree_skb_any(skb);
2563 return NETDEV_TX_OK;
1da177e4
LT		 2564}
2565
2566/* Stops the kernel queue, and halts the controller */
2567static int gfar_close(struct net_device *dev)
2568{
2569 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2570
ab939905 2571 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2572 stop_gfar(dev);
2573
bb40dcbb
AF		 2574 /* Disconnect from the PHY */
2575 phy_disconnect(priv->phydev);
2576 priv->phydev = NULL;
1da177e4 2577
80ec396c
CM		 2578 gfar_free_irq(priv);
2579
1da177e4
LT		 2580 return 0;
2581}
2582
1da177e4 2583/* Changes the mac address if the controller is not running. */
f162b9d5 2584static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2585{
7f7f5316 2586 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2587
2588 return 0;
2589}
2590
1da177e4
LT		 2591static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2592{
1da177e4 2593 struct gfar_private *priv = netdev_priv(dev);
0bbaf069
KG		 2594 int frame_size = new_mtu + ETH_HLEN;
2595
75354148 2596 if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
59deab26 2597 netif_err(priv, drv, dev, "Invalid MTU setting\n");
1da177e4
LT		 2598 return -EINVAL;
2599 }
2600
0851133b
CM		 2601 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2602 cpu_relax();
2603
88302648 2604 if (dev->flags & IFF_UP)
1da177e4
LT		 2605 stop_gfar(dev);
2606
1da177e4
LT		 2607 dev->mtu = new_mtu;
2608
88302648 2609 if (dev->flags & IFF_UP)
1da177e4
LT		 2610 startup_gfar(dev);
2611
0851133b
CM		 2612 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2613
1da177e4
LT		 2614 return 0;
2615}
2616
0851133b
CM		 2617void reset_gfar(struct net_device *ndev)
2618{
2619 struct gfar_private *priv = netdev_priv(ndev);
2620
2621 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2622 cpu_relax();
2623
2624 stop_gfar(ndev);
2625 startup_gfar(ndev);
2626
2627 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2628}
2629
ab939905 2630/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2631 * transmitted after a set amount of time.
2632 * For now, assume that clearing out all the structures, and
ab939905
SS		 2633 * starting over will fix the problem.
2634 */
2635static void gfar_reset_task(struct work_struct *work)
1da177e4 2636{
ab939905 2637 struct gfar_private *priv = container_of(work, struct gfar_private,
bc4598bc 2638 reset_task);
0851133b 2639 reset_gfar(priv->ndev);
1da177e4
LT		 2640}
2641
ab939905
SS		 2642static void gfar_timeout(struct net_device *dev)
2643{
2644 struct gfar_private *priv = netdev_priv(dev);
2645
2646 dev->stats.tx_errors++;
2647 schedule_work(&priv->reset_task);
2648}
2649
1da177e4 2650/* Interrupt Handler for Transmit complete */
c233cf40 2651static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2652{
a12f801d 2653 struct net_device *dev = tx_queue->dev;
d8a0f1b0 2654 struct netdev_queue *txq;
d080cd63 2655 struct gfar_private *priv = netdev_priv(dev);
f0ee7acf 2656 struct txbd8 *bdp, *next = NULL;
4669bc90 2657 struct txbd8 *lbdp = NULL;
a12f801d 2658 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2659 struct sk_buff *skb;
2660 int skb_dirtytx;
a12f801d 2661 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2662 int frags = 0, nr_txbds = 0;
4669bc90 2663 int i;
d080cd63 2664 int howmany = 0;
d8a0f1b0
PG		 2665 int tqi = tx_queue->qindex;
2666 unsigned int bytes_sent = 0;
4669bc90 2667 u32 lstatus;
f0ee7acf 2668 size_t buflen;
1da177e4 2669
d8a0f1b0 2670 txq = netdev_get_tx_queue(dev, tqi);
a12f801d
SG		 2671 bdp = tx_queue->dirty_tx;
2672 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2673
a12f801d 2674 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11 2675
4669bc90 2676 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf 2677
0977f817 2678 /* When time stamping, one additional TxBD must be freed.
f0ee7acf
MR		 2679 * Also, we need to dma_unmap_single() the TxPAL.
2680 */
2244d07b 2681 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2682 nr_txbds = frags + 2;
2683 else
2684 nr_txbds = frags + 1;
2685
2686 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2687
a7312d58 2688 lstatus = be32_to_cpu(lbdp->lstatus);
1da177e4 2689
4669bc90
DH		 2690 /* Only clean completed frames */
2691 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
bc4598bc 2692 (lstatus & BD_LENGTH_MASK))
4669bc90
DH		 2693 break;
2694
2244d07b 2695 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf 2696 next = next_txbd(bdp, base, tx_ring_size);
a7312d58
CM		 2697 buflen = be16_to_cpu(next->length) +
2698 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
f0ee7acf 2699 } else
a7312d58 2700 buflen = be16_to_cpu(bdp->length);
f0ee7acf 2701
a7312d58 2702 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
bc4598bc 2703 buflen, DMA_TO_DEVICE);
f0ee7acf 2704
2244d07b 2705 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf 2706 struct skb_shared_hwtstamps shhwtstamps;
b4b67f26
SW		 2707 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2708 ~0x7UL);
bc4598bc 2709
f0ee7acf 2710 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
f54af12f 2711 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
9c4886e5 2712 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
f0ee7acf 2713 skb_tstamp_tx(skb, &shhwtstamps);
a7312d58 2714 gfar_clear_txbd_status(bdp);
f0ee7acf
MR		 2715 bdp = next;
2716 }
81183059 2717
a7312d58 2718 gfar_clear_txbd_status(bdp);
4669bc90 2719 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2720
4669bc90 2721 for (i = 0; i < frags; i++) {
a7312d58
CM		 2722 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2723 be16_to_cpu(bdp->length),
2724 DMA_TO_DEVICE);
2725 gfar_clear_txbd_status(bdp);
4669bc90
DH		 2726 bdp = next_txbd(bdp, base, tx_ring_size);
2727 }
1da177e4 2728
50ad076b 2729 bytes_sent += GFAR_CB(skb)->bytes_sent;
d8a0f1b0 2730
acb600de 2731 dev_kfree_skb_any(skb);
0fd56bb5 2732
a12f801d 2733 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2734
4669bc90 2735 skb_dirtytx = (skb_dirtytx + 1) &
bc4598bc 2736 TX_RING_MOD_MASK(tx_ring_size);
4669bc90
DH		 2737
2738 howmany++;
bc602280 2739 spin_lock(&tx_queue->txlock);
f0ee7acf 2740 tx_queue->num_txbdfree += nr_txbds;
bc602280 2741 spin_unlock(&tx_queue->txlock);
4669bc90 2742 }
1da177e4 2743
4669bc90 2744 /* If we freed a buffer, we can restart transmission, if necessary */
0851133b
CM		 2745 if (tx_queue->num_txbdfree &&
2746 netif_tx_queue_stopped(txq) &&
2747 !(test_bit(GFAR_DOWN, &priv->state)))
2748 netif_wake_subqueue(priv->ndev, tqi);
1da177e4 2749
4669bc90 2750 /* Update dirty indicators */
a12f801d
SG		 2751 tx_queue->skb_dirtytx = skb_dirtytx;
2752 tx_queue->dirty_tx = bdp;
1da177e4 2753
d8a0f1b0 2754 netdev_tx_completed_queue(txq, howmany, bytes_sent);
d080cd63
DH		 2755}
2756
75354148 2757static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
1da177e4 2758{
75354148 2759 struct page *page;
76f31e8b 2760 dma_addr_t addr;
1da177e4 2761
75354148
CM		 2762 page = dev_alloc_page();
2763 if (unlikely(!page))
2764 return false;
1da177e4 2765
75354148
CM		 2766 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2767 if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2768 __free_page(page);
7f7f5316 2769
75354148 2770 return false;
0a4b5a24
KH		 2771 }
2772
75354148
CM		 2773 rxb->dma = addr;
2774 rxb->page = page;
2775 rxb->page_offset = 0;
2776
2777 return true;
1da177e4
LT		 2778}
2779
76f31e8b
CM		 2780static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2781{
f23223f1 2782 struct gfar_private *priv = netdev_priv(rx_queue->ndev);
76f31e8b
CM		 2783 struct gfar_extra_stats *estats = &priv->extra_stats;
2784
f23223f1 2785 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
76f31e8b
CM		 2786 atomic64_inc(&estats->rx_alloc_err);
2787}
2788
2789static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2790 int alloc_cnt)
2791{
75354148
CM		 2792 struct rxbd8 *bdp;
2793 struct gfar_rx_buff *rxb;
76f31e8b
CM		 2794 int i;
2795
2796 i = rx_queue->next_to_use;
76f31e8b 2797 bdp = &rx_queue->rx_bd_base[i];
75354148 2798 rxb = &rx_queue->rx_buff[i];
76f31e8b
CM		 2799
2800 while (alloc_cnt--) {
75354148
CM		 2801 /* try reuse page */
2802 if (unlikely(!rxb->page)) {
2803 if (unlikely(!gfar_new_page(rx_queue, rxb))) {
76f31e8b
CM		 2804 gfar_rx_alloc_err(rx_queue);
2805 break;
2806 }
76f31e8b
CM		 2807 }
2808
76f31e8b 2809 /* Setup the new RxBD */
75354148
CM		 2810 gfar_init_rxbdp(rx_queue, bdp,
2811 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
76f31e8b
CM		 2812
2813 /* Update to the next pointer */
75354148
CM		 2814 bdp++;
2815 rxb++;
76f31e8b 2816
75354148 2817 if (unlikely(++i == rx_queue->rx_ring_size)) {
76f31e8b 2818 i = 0;
75354148
CM		 2819 bdp = rx_queue->rx_bd_base;
2820 rxb = rx_queue->rx_buff;
2821 }
76f31e8b
CM		 2822 }
2823
2824 rx_queue->next_to_use = i;
75354148 2825 rx_queue->next_to_alloc = i;
76f31e8b
CM		 2826}
2827
f23223f1 2828static void count_errors(u32 lstatus, struct net_device *ndev)
1da177e4 2829{
f23223f1
CM		 2830 struct gfar_private *priv = netdev_priv(ndev);
2831 struct net_device_stats *stats = &ndev->stats;
1da177e4
LT		 2832 struct gfar_extra_stats *estats = &priv->extra_stats;
2833
0977f817 2834 /* If the packet was truncated, none of the other errors matter */
f966082e 2835 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
1da177e4
LT		 2836 stats->rx_length_errors++;
2837
212079df 2838 atomic64_inc(&estats->rx_trunc);
1da177e4
LT		 2839
2840 return;
2841 }
2842 /* Count the errors, if there were any */
f966082e 2843 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
1da177e4
LT		 2844 stats->rx_length_errors++;
2845
f966082e 2846 if (lstatus & BD_LFLAG(RXBD_LARGE))
212079df 2847 atomic64_inc(&estats->rx_large);
1da177e4 2848 else
212079df 2849 atomic64_inc(&estats->rx_short);
1da177e4 2850 }
f966082e 2851 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
1da177e4 2852 stats->rx_frame_errors++;
212079df 2853 atomic64_inc(&estats->rx_nonoctet);
1da177e4 2854 }
f966082e 2855 if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
212079df 2856 atomic64_inc(&estats->rx_crcerr);
1da177e4
LT		 2857 stats->rx_crc_errors++;
2858 }
f966082e 2859 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
212079df 2860 atomic64_inc(&estats->rx_overrun);
f966082e 2861 stats->rx_over_errors++;
1da177e4
LT		 2862 }
2863}
2864
f4983704 2865irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2866{
aeb12c5e
CM		 2867 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2868 unsigned long flags;
3e905b80
CM		 2869 u32 imask, ievent;
2870
2871 ievent = gfar_read(&grp->regs->ievent);
2872
2873 if (unlikely(ievent & IEVENT_FGPI)) {
2874 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2875 return IRQ_HANDLED;
2876 }
aeb12c5e
CM		 2877
2878 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2879 spin_lock_irqsave(&grp->grplock, flags);
2880 imask = gfar_read(&grp->regs->imask);
2881 imask &= IMASK_RX_DISABLED;
2882 gfar_write(&grp->regs->imask, imask);
2883 spin_unlock_irqrestore(&grp->grplock, flags);
2884 __napi_schedule(&grp->napi_rx);
2885 } else {
2886 /* Clear IEVENT, so interrupts aren't called again
2887 * because of the packets that have already arrived.
2888 */
2889 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2890 }
2891
2892 return IRQ_HANDLED;
2893}
2894
2895/* Interrupt Handler for Transmit complete */
2896static irqreturn_t gfar_transmit(int irq, void *grp_id)
2897{
2898 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2899 unsigned long flags;
2900 u32 imask;
2901
2902 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2903 spin_lock_irqsave(&grp->grplock, flags);
2904 imask = gfar_read(&grp->regs->imask);
2905 imask &= IMASK_TX_DISABLED;
2906 gfar_write(&grp->regs->imask, imask);
2907 spin_unlock_irqrestore(&grp->grplock, flags);
2908 __napi_schedule(&grp->napi_tx);
2909 } else {
2910 /* Clear IEVENT, so interrupts aren't called again
2911 * because of the packets that have already arrived.
2912 */
2913 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2914 }
2915
1da177e4
LT		 2916 return IRQ_HANDLED;
2917}
2918
75354148
CM		 2919static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2920 struct sk_buff *skb, bool first)
2921{
2922 unsigned int size = lstatus & BD_LENGTH_MASK;
2923 struct page *page = rxb->page;
2924
2925 /* Remove the FCS from the packet length */
2926 if (likely(lstatus & BD_LFLAG(RXBD_LAST)))
2927 size -= ETH_FCS_LEN;
2928
2929 if (likely(first))
2930 skb_put(skb, size);
2931 else
2932 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2933 rxb->page_offset + RXBUF_ALIGNMENT,
2934 size, GFAR_RXB_TRUESIZE);
2935
2936 /* try reuse page */
2937 if (unlikely(page_count(page) != 1))
2938 return false;
2939
2940 /* change offset to the other half */
2941 rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2942
fe896d18 2943 page_ref_inc(page);
75354148
CM		 2944
2945 return true;
2946}
2947
2948static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2949 struct gfar_rx_buff *old_rxb)
2950{
2951 struct gfar_rx_buff *new_rxb;
2952 u16 nta = rxq->next_to_alloc;
2953
2954 new_rxb = &rxq->rx_buff[nta];
2955
2956 /* find next buf that can reuse a page */
2957 nta++;
2958 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2959
2960 /* copy page reference */
2961 *new_rxb = *old_rxb;
2962
2963 /* sync for use by the device */
2964 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2965 old_rxb->page_offset,
2966 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2967}
2968
2969static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2970 u32 lstatus, struct sk_buff *skb)
2971{
2972 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2973 struct page *page = rxb->page;
2974 bool first = false;
2975
2976 if (likely(!skb)) {
2977 void *buff_addr = page_address(page) + rxb->page_offset;
2978
2979 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2980 if (unlikely(!skb)) {
2981 gfar_rx_alloc_err(rx_queue);
2982 return NULL;
2983 }
2984 skb_reserve(skb, RXBUF_ALIGNMENT);
2985 first = true;
2986 }
2987
2988 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2989 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2990
2991 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2992 /* reuse the free half of the page */
2993 gfar_reuse_rx_page(rx_queue, rxb);
2994 } else {
2995 /* page cannot be reused, unmap it */
2996 dma_unmap_page(rx_queue->dev, rxb->dma,
2997 PAGE_SIZE, DMA_FROM_DEVICE);
2998 }
2999
3000 /* clear rxb content */
3001 rxb->page = NULL;
3002
3003 return skb;
3004}
3005
0bbaf069
KG		 3006static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3007{
3008 /* If valid headers were found, and valid sums
3009 * were verified, then we tell the kernel that no
0977f817
JC		 3010 * checksumming is necessary. Otherwise, it is [FIXME]
3011 */
26eb9374
CM		 3012 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3013 (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 3014 skb->ip_summed = CHECKSUM_UNNECESSARY;
3015 else
bc8acf2c 3016 skb_checksum_none_assert(skb);
0bbaf069
KG		 3017}
3018
0977f817 3019/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
f23223f1 3020static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
1da177e4 3021{
f23223f1 3022 struct gfar_private *priv = netdev_priv(ndev);
0bbaf069 3023 struct rxfcb *fcb = NULL;
1da177e4 3024
2c2db48a
DH		 3025 /* fcb is at the beginning if exists */
3026 fcb = (struct rxfcb *)skb->data;
0bbaf069 3027
0977f817
JC		 3028 /* Remove the FCB from the skb
3029 * Remove the padded bytes, if there are any
3030 */
f23223f1 3031 if (priv->uses_rxfcb)
76f31e8b 3032 skb_pull(skb, GMAC_FCB_LEN);
0bbaf069 3033
cc772ab7
MR		 3034 /* Get receive timestamp from the skb */
3035 if (priv->hwts_rx_en) {
3036 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3037 u64 *ns = (u64 *) skb->data;
bc4598bc 3038
cc772ab7 3039 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
f54af12f 3040 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
cc772ab7
MR		 3041 }
3042
3043 if (priv->padding)
3044 skb_pull(skb, priv->padding);
3045
f23223f1 3046 if (ndev->features & NETIF_F_RXCSUM)
2c2db48a 3047 gfar_rx_checksum(skb, fcb);
0bbaf069 3048
2c2db48a 3049 /* Tell the skb what kind of packet this is */
f23223f1 3050 skb->protocol = eth_type_trans(skb, ndev);
1da177e4 3051
f646968f 3052 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
32f7fd44
JP		 3053 * Even if vlan rx accel is disabled, on some chips
3054 * RXFCB_VLN is pseudo randomly set.
3055 */
f23223f1 3056 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
26eb9374
CM		 3057 be16_to_cpu(fcb->flags) & RXFCB_VLN)
3058 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3059 be16_to_cpu(fcb->vlctl));
1da177e4
LT		 3060}
3061
3062/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2281a0f3
JC		 3063 * until the budget/quota has been reached. Returns the number
3064 * of frames handled
1da177e4 3065 */
a12f801d 3066int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 3067{
f23223f1 3068 struct net_device *ndev = rx_queue->ndev;
75354148
CM		 3069 struct gfar_private *priv = netdev_priv(ndev);
3070 struct rxbd8 *bdp;
76f31e8b 3071 int i, howmany = 0;
75354148 3072 struct sk_buff *skb = rx_queue->skb;
76f31e8b 3073 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
75354148 3074 unsigned int total_bytes = 0, total_pkts = 0;
1da177e4
LT		 3075
3076 /* Get the first full descriptor */
76f31e8b 3077 i = rx_queue->next_to_clean;
1da177e4 3078
76f31e8b 3079 while (rx_work_limit--) {
f966082e 3080 u32 lstatus;
2c2db48a 3081
76f31e8b
CM		 3082 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3083 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3084 cleaned_cnt = 0;
3085 }
bc4598bc 3086
76f31e8b 3087 bdp = &rx_queue->rx_bd_base[i];
f966082e
CM		 3088 lstatus = be32_to_cpu(bdp->lstatus);
3089 if (lstatus & BD_LFLAG(RXBD_EMPTY))
76f31e8b 3090 break;
815b97c6 3091
76f31e8b
CM		 3092 /* order rx buffer descriptor reads */
3093 rmb();
815b97c6 3094
76f31e8b 3095 /* fetch next to clean buffer from the ring */
75354148
CM		 3096 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3097 if (unlikely(!skb))
3098 break;
1da177e4 3099
75354148
CM		 3100 cleaned_cnt++;
3101 howmany++;
81183059 3102
75354148
CM		 3103 if (unlikely(++i == rx_queue->rx_ring_size))
3104 i = 0;
3105
3106 rx_queue->next_to_clean = i;
3107
3108 /* fetch next buffer if not the last in frame */
3109 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3110 continue;
63b88b90 3111
75354148 3112 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
f23223f1 3113 count_errors(lstatus, ndev);
815b97c6 3114
76f31e8b
CM		 3115 /* discard faulty buffer */
3116 dev_kfree_skb(skb);
75354148
CM		 3117 skb = NULL;
3118 rx_queue->stats.rx_dropped++;
3119 continue;
3120 }
76f31e8b 3121
75354148
CM		 3122 /* Increment the number of packets */
3123 total_pkts++;
3124 total_bytes += skb->len;
2c2db48a 3125
75354148 3126 skb_record_rx_queue(skb, rx_queue->qindex);
1da177e4 3127
75354148 3128 gfar_process_frame(ndev, skb);
1da177e4 3129
75354148
CM		 3130 /* Send the packet up the stack */
3131 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3132
3133 skb = NULL;
76f31e8b 3134 }
1da177e4 3135
75354148
CM		 3136 /* Store incomplete frames for completion */
3137 rx_queue->skb = skb;
3138
3139 rx_queue->stats.rx_packets += total_pkts;
3140 rx_queue->stats.rx_bytes += total_bytes;
45b679c9 3141
76f31e8b
CM		 3142 if (cleaned_cnt)
3143 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
1da177e4 3144
76f31e8b
CM		 3145 /* Update Last Free RxBD pointer for LFC */
3146 if (unlikely(priv->tx_actual_en)) {
b4b67f26
SW		 3147 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3148
3149 gfar_write(rx_queue->rfbptr, bdp_dma);
1da177e4
LT		 3150 }
3151
1da177e4
LT		 3152 return howmany;
3153}
3154
aeb12c5e 3155static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
5eaedf31
CM		 3156{
3157 struct gfar_priv_grp *gfargrp =
aeb12c5e 3158 container_of(napi, struct gfar_priv_grp, napi_rx);
5eaedf31 3159 struct gfar __iomem *regs = gfargrp->regs;
71ff9e3d 3160 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
5eaedf31
CM		 3161 int work_done = 0;
3162
3163 /* Clear IEVENT, so interrupts aren't called again
3164 * because of the packets that have already arrived
3165 */
aeb12c5e 3166 gfar_write(&regs->ievent, IEVENT_RX_MASK);
5eaedf31
CM		 3167
3168 work_done = gfar_clean_rx_ring(rx_queue, budget);
3169
3170 if (work_done < budget) {
aeb12c5e 3171 u32 imask;
5eaedf31
CM		 3172 napi_complete(napi);
3173 /* Clear the halt bit in RSTAT */
3174 gfar_write(&regs->rstat, gfargrp->rstat);
3175
aeb12c5e
CM		 3176 spin_lock_irq(&gfargrp->grplock);
3177 imask = gfar_read(&regs->imask);
3178 imask |= IMASK_RX_DEFAULT;
3179 gfar_write(&regs->imask, imask);
3180 spin_unlock_irq(&gfargrp->grplock);
5eaedf31
CM		 3181 }
3182
3183 return work_done;
3184}
3185
aeb12c5e 3186static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
1da177e4 3187{
bc4598bc 3188 struct gfar_priv_grp *gfargrp =
aeb12c5e
CM		 3189 container_of(napi, struct gfar_priv_grp, napi_tx);
3190 struct gfar __iomem *regs = gfargrp->regs;
71ff9e3d 3191 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
aeb12c5e
CM		 3192 u32 imask;
3193
3194 /* Clear IEVENT, so interrupts aren't called again
3195 * because of the packets that have already arrived
3196 */
3197 gfar_write(&regs->ievent, IEVENT_TX_MASK);
3198
3199 /* run Tx cleanup to completion */
3200 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3201 gfar_clean_tx_ring(tx_queue);
3202
3203 napi_complete(napi);
3204
3205 spin_lock_irq(&gfargrp->grplock);
3206 imask = gfar_read(&regs->imask);
3207 imask |= IMASK_TX_DEFAULT;
3208 gfar_write(&regs->imask, imask);
3209 spin_unlock_irq(&gfargrp->grplock);
3210
3211 return 0;
3212}
3213
3214static int gfar_poll_rx(struct napi_struct *napi, int budget)
3215{
3216 struct gfar_priv_grp *gfargrp =
3217 container_of(napi, struct gfar_priv_grp, napi_rx);
fba4ed03 3218 struct gfar_private *priv = gfargrp->priv;
46ceb60c 3219 struct gfar __iomem *regs = gfargrp->regs;
fba4ed03 3220 struct gfar_priv_rx_q *rx_queue = NULL;
c233cf40 3221 int work_done = 0, work_done_per_q = 0;
39c0a0d5 3222 int i, budget_per_q = 0;
6be5ed3f
CM		 3223 unsigned long rstat_rxf;
3224 int num_act_queues;
fba4ed03 3225
8c7396ae 3226 /* Clear IEVENT, so interrupts aren't called again
0977f817
JC		 3227 * because of the packets that have already arrived
3228 */
aeb12c5e 3229 gfar_write(&regs->ievent, IEVENT_RX_MASK);
8c7396ae 3230
6be5ed3f
CM		 3231 rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3232
3233 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3234 if (num_act_queues)
3235 budget_per_q = budget/num_act_queues;
3236
3ba405db
CM		 3237 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3238 /* skip queue if not active */
3239 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3240 continue;
1da177e4 3241
3ba405db
CM		 3242 rx_queue = priv->rx_queue[i];
3243 work_done_per_q =
3244 gfar_clean_rx_ring(rx_queue, budget_per_q);
3245 work_done += work_done_per_q;
3246
3247 /* finished processing this queue */
3248 if (work_done_per_q < budget_per_q) {
3249 /* clear active queue hw indication */
3250 gfar_write(&regs->rstat,
3251 RSTAT_CLEAR_RXF0 >> i);
3252 num_act_queues--;
3253
3254 if (!num_act_queues)
3255 break;
3256 }
3257 }
42199884 3258
aeb12c5e
CM		 3259 if (!num_act_queues) {
3260 u32 imask;
3ba405db 3261 napi_complete(napi);
1da177e4 3262
3ba405db
CM		 3263 /* Clear the halt bit in RSTAT */
3264 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 3265
aeb12c5e
CM		 3266 spin_lock_irq(&gfargrp->grplock);
3267 imask = gfar_read(&regs->imask);
3268 imask |= IMASK_RX_DEFAULT;
3269 gfar_write(&regs->imask, imask);
3270 spin_unlock_irq(&gfargrp->grplock);
1da177e4
LT		 3271 }
3272
c233cf40 3273 return work_done;
1da177e4 3274}
1da177e4 3275
aeb12c5e
CM		 3276static int gfar_poll_tx(struct napi_struct *napi, int budget)
3277{
3278 struct gfar_priv_grp *gfargrp =
3279 container_of(napi, struct gfar_priv_grp, napi_tx);
3280 struct gfar_private *priv = gfargrp->priv;
3281 struct gfar __iomem *regs = gfargrp->regs;
3282 struct gfar_priv_tx_q *tx_queue = NULL;
3283 int has_tx_work = 0;
3284 int i;
3285
3286 /* Clear IEVENT, so interrupts aren't called again
3287 * because of the packets that have already arrived
3288 */
3289 gfar_write(&regs->ievent, IEVENT_TX_MASK);
3290
3291 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3292 tx_queue = priv->tx_queue[i];
3293 /* run Tx cleanup to completion */
3294 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3295 gfar_clean_tx_ring(tx_queue);
3296 has_tx_work = 1;
3297 }
3298 }
3299
3300 if (!has_tx_work) {
3301 u32 imask;
3302 napi_complete(napi);
3303
3304 spin_lock_irq(&gfargrp->grplock);
3305 imask = gfar_read(&regs->imask);
3306 imask |= IMASK_TX_DEFAULT;
3307 gfar_write(&regs->imask, imask);
3308 spin_unlock_irq(&gfargrp->grplock);
3309 }
3310
3311 return 0;
3312}
3313
3314
f2d71c2d 3315#ifdef CONFIG_NET_POLL_CONTROLLER
0977f817 3316/* Polling 'interrupt' - used by things like netconsole to send skbs
f2d71c2d
VW		 3317 * without having to re-enable interrupts. It's not called while
3318 * the interrupt routine is executing.
3319 */
3320static void gfar_netpoll(struct net_device *dev)
3321{
3322 struct gfar_private *priv = netdev_priv(dev);
3a2e16c8 3323 int i;
f2d71c2d
VW		 3324
3325 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 3326 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c 3327 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 3328 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3329
3330 disable_irq(gfar_irq(grp, TX)->irq);
3331 disable_irq(gfar_irq(grp, RX)->irq);
3332 disable_irq(gfar_irq(grp, ER)->irq);
3333 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3334 enable_irq(gfar_irq(grp, ER)->irq);
3335 enable_irq(gfar_irq(grp, RX)->irq);
3336 enable_irq(gfar_irq(grp, TX)->irq);
46ceb60c 3337 }
f2d71c2d 3338 } else {
46ceb60c 3339 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 3340 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3341
3342 disable_irq(gfar_irq(grp, TX)->irq);
3343 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3344 enable_irq(gfar_irq(grp, TX)->irq);
43de004b 3345 }
f2d71c2d
VW		 3346 }
3347}
3348#endif
3349
1da177e4 3350/* The interrupt handler for devices with one interrupt */
f4983704 3351static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 3352{
f4983704 3353 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 3354
3355 /* Save ievent for future reference */
f4983704 3356 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 3357
1da177e4 3358 /* Check for reception */
538cc7ee 3359 if (events & IEVENT_RX_MASK)
f4983704 3360 gfar_receive(irq, grp_id);
1da177e4
LT		 3361
3362 /* Check for transmit completion */
538cc7ee 3363 if (events & IEVENT_TX_MASK)
f4983704 3364 gfar_transmit(irq, grp_id);
1da177e4 3365
538cc7ee
SS		 3366 /* Check for errors */
3367 if (events & IEVENT_ERR_MASK)
f4983704 3368 gfar_error(irq, grp_id);
1da177e4
LT		 3369
3370 return IRQ_HANDLED;
3371}
3372
1da177e4
LT		 3373/* Called every time the controller might need to be made
3374 * aware of new link state. The PHY code conveys this
bb40dcbb 3375 * information through variables in the phydev structure, and this
1da177e4
LT		 3376 * function converts those variables into the appropriate
3377 * register values, and can bring down the device if needed.
3378 */
3379static void adjust_link(struct net_device *dev)
3380{
3381 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 3382 struct phy_device *phydev = priv->phydev;
bb40dcbb 3383
6ce29b0e 3384 if (unlikely(phydev->link != priv->oldlink ||
0ae93b2c
GR		 3385 (phydev->link && (phydev->duplex != priv->oldduplex ||
3386 phydev->speed != priv->oldspeed))))
6ce29b0e 3387 gfar_update_link_state(priv);
bb40dcbb 3388}
1da177e4
LT		 3389
3390/* Update the hash table based on the current list of multicast
3391 * addresses we subscribe to. Also, change the promiscuity of
3392 * the device based on the flags (this function is called
0977f817
JC		 3393 * whenever dev->flags is changed
3394 */
1da177e4
LT		 3395static void gfar_set_multi(struct net_device *dev)
3396{
22bedad3 3397 struct netdev_hw_addr *ha;
1da177e4 3398 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3399 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3400 u32 tempval;
3401
a12f801d 3402 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3403 /* Set RCTRL to PROM */
3404 tempval = gfar_read(&regs->rctrl);
3405 tempval |= RCTRL_PROM;
3406 gfar_write(&regs->rctrl, tempval);
3407 } else {
3408 /* Set RCTRL to not PROM */
3409 tempval = gfar_read(&regs->rctrl);
3410 tempval &= ~(RCTRL_PROM);
3411 gfar_write(&regs->rctrl, tempval);
3412 }
6aa20a22 3413
a12f801d 3414 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3415 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3416 gfar_write(&regs->igaddr0, 0xffffffff);
3417 gfar_write(&regs->igaddr1, 0xffffffff);
3418 gfar_write(&regs->igaddr2, 0xffffffff);
3419 gfar_write(&regs->igaddr3, 0xffffffff);
3420 gfar_write(&regs->igaddr4, 0xffffffff);
3421 gfar_write(&regs->igaddr5, 0xffffffff);
3422 gfar_write(&regs->igaddr6, 0xffffffff);
3423 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3424 gfar_write(&regs->gaddr0, 0xffffffff);
3425 gfar_write(&regs->gaddr1, 0xffffffff);
3426 gfar_write(&regs->gaddr2, 0xffffffff);
3427 gfar_write(&regs->gaddr3, 0xffffffff);
3428 gfar_write(&regs->gaddr4, 0xffffffff);
3429 gfar_write(&regs->gaddr5, 0xffffffff);
3430 gfar_write(&regs->gaddr6, 0xffffffff);
3431 gfar_write(&regs->gaddr7, 0xffffffff);
3432 } else {
7f7f5316
AF		 3433 int em_num;
3434 int idx;
3435
1da177e4 3436 /* zero out the hash */
0bbaf069
KG		 3437 gfar_write(&regs->igaddr0, 0x0);
3438 gfar_write(&regs->igaddr1, 0x0);
3439 gfar_write(&regs->igaddr2, 0x0);
3440 gfar_write(&regs->igaddr3, 0x0);
3441 gfar_write(&regs->igaddr4, 0x0);
3442 gfar_write(&regs->igaddr5, 0x0);
3443 gfar_write(&regs->igaddr6, 0x0);
3444 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3445 gfar_write(&regs->gaddr0, 0x0);
3446 gfar_write(&regs->gaddr1, 0x0);
3447 gfar_write(&regs->gaddr2, 0x0);
3448 gfar_write(&regs->gaddr3, 0x0);
3449 gfar_write(&regs->gaddr4, 0x0);
3450 gfar_write(&regs->gaddr5, 0x0);
3451 gfar_write(&regs->gaddr6, 0x0);
3452 gfar_write(&regs->gaddr7, 0x0);
3453
7f7f5316
AF		 3454 /* If we have extended hash tables, we need to
3455 * clear the exact match registers to prepare for
0977f817
JC		 3456 * setting them
3457 */
7f7f5316
AF		 3458 if (priv->extended_hash) {
3459 em_num = GFAR_EM_NUM + 1;
3460 gfar_clear_exact_match(dev);
3461 idx = 1;
3462 } else {
3463 idx = 0;
3464 em_num = 0;
3465 }
3466
4cd24eaf 3467 if (netdev_mc_empty(dev))
1da177e4
LT		 3468 return;
3469
3470 /* Parse the list, and set the appropriate bits */
22bedad3 3471 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3472 if (idx < em_num) {
22bedad3 3473 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3474 idx++;
3475 } else
22bedad3 3476 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3477 }
3478 }
1da177e4
LT		 3479}
3480
7f7f5316
AF		 3481
3482/* Clears each of the exact match registers to zero, so they
0977f817
JC		 3483 * don't interfere with normal reception
3484 */
7f7f5316
AF		 3485static void gfar_clear_exact_match(struct net_device *dev)
3486{
3487 int idx;
6a3c910c 3488 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
7f7f5316 3489
bc4598bc 3490 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
b6bc7650 3491 gfar_set_mac_for_addr(dev, idx, zero_arr);
7f7f5316
AF		 3492}
3493
1da177e4
LT		 3494/* Set the appropriate hash bit for the given addr */
3495/* The algorithm works like so:
3496 * 1) Take the Destination Address (ie the multicast address), and
3497 * do a CRC on it (little endian), and reverse the bits of the
3498 * result.
3499 * 2) Use the 8 most significant bits as a hash into a 256-entry
3500 * table. The table is controlled through 8 32-bit registers:
3501 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3502 * gaddr7. This means that the 3 most significant bits in the
3503 * hash index which gaddr register to use, and the 5 other bits
3504 * indicate which bit (assuming an IBM numbering scheme, which
3505 * for PowerPC (tm) is usually the case) in the register holds
0977f817
JC		 3506 * the entry.
3507 */
1da177e4
LT		 3508static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3509{
3510 u32 tempval;
3511 struct gfar_private *priv = netdev_priv(dev);
6a3c910c 3512 u32 result = ether_crc(ETH_ALEN, addr);
0bbaf069
KG		 3513 int width = priv->hash_width;
3514 u8 whichbit = (result >> (32 - width)) & 0x1f;
3515 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3516 u32 value = (1 << (31-whichbit));
3517
0bbaf069 3518 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3519 tempval |= value;
0bbaf069 3520 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3521}
3522
7f7f5316
AF		 3523
3524/* There are multiple MAC Address register pairs on some controllers
3525 * This function sets the numth pair to a given address
3526 */
b6bc7650
JP		 3527static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3528 const u8 *addr)
7f7f5316
AF		 3529{
3530 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3531 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316 3532 u32 tempval;
f4983704 3533 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3534
3535 macptr += num*2;
3536
83bfc3c4
CM		 3537 /* For a station address of 0x12345678ABCD in transmission
3538 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3539 * MACnADDR2 is set to 0x34120000.
0977f817 3540 */
83bfc3c4
CM		 3541 tempval = (addr[5] << 24) | (addr[4] << 16) |
3542 (addr[3] << 8) | addr[2];
7f7f5316 3543
83bfc3c4 3544 gfar_write(macptr, tempval);
7f7f5316 3545
83bfc3c4 3546 tempval = (addr[1] << 24) | (addr[0] << 16);
7f7f5316
AF		 3547
3548 gfar_write(macptr+1, tempval);
3549}
3550
1da177e4 3551/* GFAR error interrupt handler */
f4983704 3552static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3553{
f4983704
SG		 3554 struct gfar_priv_grp *gfargrp = grp_id;
3555 struct gfar __iomem *regs = gfargrp->regs;
3556 struct gfar_private *priv= gfargrp->priv;
3557 struct net_device *dev = priv->ndev;
1da177e4
LT		 3558
3559 /* Save ievent for future reference */
f4983704 3560 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3561
3562 /* Clear IEVENT */
f4983704 3563 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3564
3565 /* Magic Packet is not an error. */
b31a1d8b 3566 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3567 (events & IEVENT_MAG))
3568 events &= ~IEVENT_MAG;
1da177e4
LT		 3569
3570 /* Hmm... */
0bbaf069 3571 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
bc4598bc
JC		 3572 netdev_dbg(dev,
3573 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
59deab26 3574 events, gfar_read(&regs->imask));
1da177e4
LT		 3575
3576 /* Update the error counters */
3577 if (events & IEVENT_TXE) {
09f75cd7 3578 dev->stats.tx_errors++;
1da177e4
LT		 3579
3580 if (events & IEVENT_LC)
09f75cd7 3581 dev->stats.tx_window_errors++;
1da177e4 3582 if (events & IEVENT_CRL)
09f75cd7 3583 dev->stats.tx_aborted_errors++;
1da177e4 3584 if (events & IEVENT_XFUN) {
59deab26
JP		 3585 netif_dbg(priv, tx_err, dev,
3586 "TX FIFO underrun, packet dropped\n");
09f75cd7 3587 dev->stats.tx_dropped++;
212079df 3588 atomic64_inc(&priv->extra_stats.tx_underrun);
1da177e4 3589
bc602280 3590 schedule_work(&priv->reset_task);
1da177e4 3591 }
59deab26 3592 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
1da177e4
LT		 3593 }
3594 if (events & IEVENT_BSY) {
1de65a5e 3595 dev->stats.rx_over_errors++;
212079df 3596 atomic64_inc(&priv->extra_stats.rx_bsy);
1da177e4 3597
59deab26
JP		 3598 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3599 gfar_read(&regs->rstat));
1da177e4
LT		 3600 }
3601 if (events & IEVENT_BABR) {
09f75cd7 3602 dev->stats.rx_errors++;
212079df 3603 atomic64_inc(&priv->extra_stats.rx_babr);
1da177e4 3604
59deab26 3605 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
1da177e4
LT		 3606 }
3607 if (events & IEVENT_EBERR) {
212079df 3608 atomic64_inc(&priv->extra_stats.eberr);
59deab26 3609 netif_dbg(priv, rx_err, dev, "bus error\n");
1da177e4 3610 }
59deab26
JP		 3611 if (events & IEVENT_RXC)
3612 netif_dbg(priv, rx_status, dev, "control frame\n");
1da177e4
LT		 3613
3614 if (events & IEVENT_BABT) {
212079df 3615 atomic64_inc(&priv->extra_stats.tx_babt);
59deab26 3616 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
1da177e4
LT		 3617 }
3618 return IRQ_HANDLED;
3619}
3620
6ce29b0e
CM		 3621static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3622{
3623 struct phy_device *phydev = priv->phydev;
3624 u32 val = 0;
3625
3626 if (!phydev->duplex)
3627 return val;
3628
3629 if (!priv->pause_aneg_en) {
3630 if (priv->tx_pause_en)
3631 val |= MACCFG1_TX_FLOW;
3632 if (priv->rx_pause_en)
3633 val |= MACCFG1_RX_FLOW;
3634 } else {
3635 u16 lcl_adv, rmt_adv;
3636 u8 flowctrl;
3637 /* get link partner capabilities */
3638 rmt_adv = 0;
3639 if (phydev->pause)
3640 rmt_adv = LPA_PAUSE_CAP;
3641 if (phydev->asym_pause)
3642 rmt_adv |= LPA_PAUSE_ASYM;
3643
43ef8d29
PMB		 3644 lcl_adv = 0;
3645 if (phydev->advertising & ADVERTISED_Pause)
3646 lcl_adv |= ADVERTISE_PAUSE_CAP;
3647 if (phydev->advertising & ADVERTISED_Asym_Pause)
3648 lcl_adv |= ADVERTISE_PAUSE_ASYM;
6ce29b0e
CM		 3649
3650 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3651 if (flowctrl & FLOW_CTRL_TX)
3652 val |= MACCFG1_TX_FLOW;
3653 if (flowctrl & FLOW_CTRL_RX)
3654 val |= MACCFG1_RX_FLOW;
3655 }
3656
3657 return val;
3658}
3659
3660static noinline void gfar_update_link_state(struct gfar_private *priv)
3661{
3662 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3663 struct phy_device *phydev = priv->phydev;
45b679c9
MP		 3664 struct gfar_priv_rx_q *rx_queue = NULL;
3665 int i;
6ce29b0e
CM		 3666
3667 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3668 return;
3669
3670 if (phydev->link) {
3671 u32 tempval1 = gfar_read(&regs->maccfg1);
3672 u32 tempval = gfar_read(&regs->maccfg2);
3673 u32 ecntrl = gfar_read(&regs->ecntrl);
45b679c9 3674 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
6ce29b0e
CM		 3675
3676 if (phydev->duplex != priv->oldduplex) {
3677 if (!(phydev->duplex))
3678 tempval &= ~(MACCFG2_FULL_DUPLEX);
3679 else
3680 tempval |= MACCFG2_FULL_DUPLEX;
3681
3682 priv->oldduplex = phydev->duplex;
3683 }
3684
3685 if (phydev->speed != priv->oldspeed) {
3686 switch (phydev->speed) {
3687 case 1000:
3688 tempval =
3689 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3690
3691 ecntrl &= ~(ECNTRL_R100);
3692 break;
3693 case 100:
3694 case 10:
3695 tempval =
3696 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3697
3698 /* Reduced mode distinguishes
3699 * between 10 and 100
3700 */
3701 if (phydev->speed == SPEED_100)
3702 ecntrl |= ECNTRL_R100;
3703 else
3704 ecntrl &= ~(ECNTRL_R100);
3705 break;
3706 default:
3707 netif_warn(priv, link, priv->ndev,
3708 "Ack! Speed (%d) is not 10/100/1000!\n",
3709 phydev->speed);
3710 break;
3711 }
3712
3713 priv->oldspeed = phydev->speed;
3714 }
3715
3716 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3717 tempval1 |= gfar_get_flowctrl_cfg(priv);
3718
45b679c9
MP		 3719 /* Turn last free buffer recording on */
3720 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3721 for (i = 0; i < priv->num_rx_queues; i++) {
b4b67f26
SW		 3722 u32 bdp_dma;
3723
45b679c9 3724 rx_queue = priv->rx_queue[i];
b4b67f26
SW		 3725 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3726 gfar_write(rx_queue->rfbptr, bdp_dma);
45b679c9
MP		 3727 }
3728
3729 priv->tx_actual_en = 1;
3730 }
3731
3732 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3733 priv->tx_actual_en = 0;
3734
6ce29b0e
CM		 3735 gfar_write(&regs->maccfg1, tempval1);
3736 gfar_write(&regs->maccfg2, tempval);
3737 gfar_write(&regs->ecntrl, ecntrl);
3738
3739 if (!priv->oldlink)
3740 priv->oldlink = 1;
3741
3742 } else if (priv->oldlink) {
3743 priv->oldlink = 0;
3744 priv->oldspeed = 0;
3745 priv->oldduplex = -1;
3746 }
3747
3748 if (netif_msg_link(priv))
3749 phy_print_status(phydev);
3750}
3751
94e5a2a8 3752static const struct of_device_id gfar_match[] =
b31a1d8b
AF		 3753{
3754 {
3755 .type = "network",
3756 .compatible = "gianfar",
3757 },
46ceb60c
SG		 3758 {
3759 .compatible = "fsl,etsec2",
3760 },
b31a1d8b
AF		 3761 {},
3762};
e72701ac 3763MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3764
1da177e4 3765/* Structure for a device driver */
74888760 3766static struct platform_driver gfar_driver = {
4018294b
GL		 3767 .driver = {
3768 .name = "fsl-gianfar",
4018294b
GL		 3769 .pm = GFAR_PM_OPS,
3770 .of_match_table = gfar_match,
3771 },
1da177e4
LT		 3772 .probe = gfar_probe,
3773 .remove = gfar_remove,
3774};
3775
db62f684 3776module_platform_driver(gfar_driver);
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