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sfc: Store port number in private data, not net_device::dev_id
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / freescale / gianfar.c
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0977f817 1/* drivers/net/ethernet/freescale/gianfar.c
1da177e4
LT		 2 *
3 * Gianfar Ethernet Driver
7f7f5316
AF		 4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
4c8d3d99 9 * Maintainer: Kumar Gala
a12f801d 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 11 *
6c43e046 12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
a12f801d 13 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
0bbaf069 27 *
b31a1d8b
AF		 28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
0bbaf069 38 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
bb40dcbb 42 * of frames or amount of time have passed). In NAPI, the
1da177e4 43 * interrupt handler will signal there is work to be done, and
0aa1538f 44 * exit. This method will start at the last known empty
0bbaf069 45 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
59deab26
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65#define DEBUG
66
1da177e4 67#include <linux/kernel.h>
1da177e4
LT		 68#include <linux/string.h>
69#include <linux/errno.h>
bb40dcbb 70#include <linux/unistd.h>
1da177e4
LT		 71#include <linux/slab.h>
72#include <linux/interrupt.h>
73#include <linux/init.h>
74#include <linux/delay.h>
75#include <linux/netdevice.h>
76#include <linux/etherdevice.h>
77#include <linux/skbuff.h>
0bbaf069 78#include <linux/if_vlan.h>
1da177e4
LT		 79#include <linux/spinlock.h>
80#include <linux/mm.h>
fe192a49 81#include <linux/of_mdio.h>
b31a1d8b 82#include <linux/of_platform.h>
0bbaf069
KG		 83#include <linux/ip.h>
84#include <linux/tcp.h>
85#include <linux/udp.h>
9c07b884 86#include <linux/in.h>
cc772ab7 87#include <linux/net_tstamp.h>
1da177e4
LT		 88
89#include <asm/io.h>
7d350977 90#include <asm/reg.h>
1da177e4
LT		 91#include <asm/irq.h>
92#include <asm/uaccess.h>
93#include <linux/module.h>
1da177e4
LT		 94#include <linux/dma-mapping.h>
95#include <linux/crc32.h>
bb40dcbb
AF		 96#include <linux/mii.h>
97#include <linux/phy.h>
b31a1d8b
AF		 98#include <linux/phy_fixed.h>
99#include <linux/of.h>
4b6ba8aa 100#include <linux/of_net.h>
1da177e4
LT		 101
102#include "gianfar.h"
1da177e4
LT		 103
104#define TX_TIMEOUT (1*HZ)
1da177e4 105
7f7f5316 106const char gfar_driver_version[] = "1.3";
1da177e4 107
1da177e4
LT		 108static int gfar_enet_open(struct net_device *dev);
109static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 110static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 111static void gfar_timeout(struct net_device *dev);
112static int gfar_close(struct net_device *dev);
815b97c6 113struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 114static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
bc4598bc 115 struct sk_buff *skb);
1da177e4
LT		 116static int gfar_set_mac_address(struct net_device *dev);
117static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 118static irqreturn_t gfar_error(int irq, void *dev_id);
119static irqreturn_t gfar_transmit(int irq, void *dev_id);
120static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 121static void adjust_link(struct net_device *dev);
122static void init_registers(struct net_device *dev);
123static int init_phy(struct net_device *dev);
74888760 124static int gfar_probe(struct platform_device *ofdev);
2dc11581 125static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 126static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 127static void gfar_set_multi(struct net_device *dev);
128static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 129static void gfar_configure_serdes(struct net_device *dev);
bea3348e 130static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 131#ifdef CONFIG_NET_POLL_CONTROLLER
132static void gfar_netpoll(struct net_device *dev);
133#endif
a12f801d 134int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
c233cf40 135static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
61db26c6
CM		 136static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 int amount_pull, struct napi_struct *napi);
7f7f5316 138void gfar_halt(struct net_device *dev);
d87eb127 139static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 140void gfar_start(struct net_device *dev);
141static void gfar_clear_exact_match(struct net_device *dev);
b6bc7650
JP		 142static void gfar_set_mac_for_addr(struct net_device *dev, int num,
143 const u8 *addr);
26ccfc37 144static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 145
1da177e4
LT		 146MODULE_AUTHOR("Freescale Semiconductor, Inc");
147MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148MODULE_LICENSE("GPL");
149
a12f801d 150static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 151 dma_addr_t buf)
152{
8a102fe0
AV		 153 u32 lstatus;
154
155 bdp->bufPtr = buf;
156
157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 159 lstatus |= BD_LFLAG(RXBD_WRAP);
160
161 eieio();
162
163 bdp->lstatus = lstatus;
164}
165
8728327e 166static int gfar_init_bds(struct net_device *ndev)
826aa4a0 167{
8728327e 168 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 169 struct gfar_priv_tx_q *tx_queue = NULL;
170 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 171 struct txbd8 *txbdp;
172 struct rxbd8 *rxbdp;
fba4ed03 173 int i, j;
a12f801d 174
fba4ed03
SG		 175 for (i = 0; i < priv->num_tx_queues; i++) {
176 tx_queue = priv->tx_queue[i];
177 /* Initialize some variables in our dev structure */
178 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
179 tx_queue->dirty_tx = tx_queue->tx_bd_base;
180 tx_queue->cur_tx = tx_queue->tx_bd_base;
181 tx_queue->skb_curtx = 0;
182 tx_queue->skb_dirtytx = 0;
183
184 /* Initialize Transmit Descriptor Ring */
185 txbdp = tx_queue->tx_bd_base;
186 for (j = 0; j < tx_queue->tx_ring_size; j++) {
187 txbdp->lstatus = 0;
188 txbdp->bufPtr = 0;
189 txbdp++;
190 }
8728327e 191
fba4ed03
SG		 192 /* Set the last descriptor in the ring to indicate wrap */
193 txbdp--;
194 txbdp->status |= TXBD_WRAP;
8728327e
AV		 195 }
196
fba4ed03
SG		 197 for (i = 0; i < priv->num_rx_queues; i++) {
198 rx_queue = priv->rx_queue[i];
199 rx_queue->cur_rx = rx_queue->rx_bd_base;
200 rx_queue->skb_currx = 0;
201 rxbdp = rx_queue->rx_bd_base;
8728327e 202
fba4ed03
SG		 203 for (j = 0; j < rx_queue->rx_ring_size; j++) {
204 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 205
fba4ed03
SG		 206 if (skb) {
207 gfar_init_rxbdp(rx_queue, rxbdp,
208 rxbdp->bufPtr);
209 } else {
210 skb = gfar_new_skb(ndev);
211 if (!skb) {
59deab26 212 netdev_err(ndev, "Can't allocate RX buffers\n");
1eb8f7a7 213 return -ENOMEM;
fba4ed03
SG		 214 }
215 rx_queue->rx_skbuff[j] = skb;
216
217 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 218 }
8728327e 219
fba4ed03 220 rxbdp++;
8728327e
AV		 221 }
222
8728327e
AV		 223 }
224
225 return 0;
226}
227
228static int gfar_alloc_skb_resources(struct net_device *ndev)
229{
826aa4a0 230 void *vaddr;
fba4ed03
SG		 231 dma_addr_t addr;
232 int i, j, k;
826aa4a0 233 struct gfar_private *priv = netdev_priv(ndev);
369ec162 234 struct device *dev = priv->dev;
a12f801d
SG		 235 struct gfar_priv_tx_q *tx_queue = NULL;
236 struct gfar_priv_rx_q *rx_queue = NULL;
237
fba4ed03
SG		 238 priv->total_tx_ring_size = 0;
239 for (i = 0; i < priv->num_tx_queues; i++)
240 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
241
242 priv->total_rx_ring_size = 0;
243 for (i = 0; i < priv->num_rx_queues; i++)
244 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 245
246 /* Allocate memory for the buffer descriptors */
8728327e 247 vaddr = dma_alloc_coherent(dev,
d0320f75
JP		 248 (priv->total_tx_ring_size *
249 sizeof(struct txbd8)) +
250 (priv->total_rx_ring_size *
251 sizeof(struct rxbd8)),
252 &addr, GFP_KERNEL);
253 if (!vaddr)
826aa4a0 254 return -ENOMEM;
826aa4a0 255
fba4ed03
SG		 256 for (i = 0; i < priv->num_tx_queues; i++) {
257 tx_queue = priv->tx_queue[i];
43d620c8 258 tx_queue->tx_bd_base = vaddr;
fba4ed03
SG		 259 tx_queue->tx_bd_dma_base = addr;
260 tx_queue->dev = ndev;
261 /* enet DMA only understands physical addresses */
bc4598bc
JC		 262 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
263 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
fba4ed03 264 }
826aa4a0 265
826aa4a0 266 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 267 for (i = 0; i < priv->num_rx_queues; i++) {
268 rx_queue = priv->rx_queue[i];
43d620c8 269 rx_queue->rx_bd_base = vaddr;
fba4ed03
SG		 270 rx_queue->rx_bd_dma_base = addr;
271 rx_queue->dev = ndev;
bc4598bc
JC		 272 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
273 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
fba4ed03 274 }
826aa4a0
AV		 275
276 /* Setup the skbuff rings */
fba4ed03
SG		 277 for (i = 0; i < priv->num_tx_queues; i++) {
278 tx_queue = priv->tx_queue[i];
14f8dc49
JP		 279 tx_queue->tx_skbuff =
280 kmalloc_array(tx_queue->tx_ring_size,
281 sizeof(*tx_queue->tx_skbuff),
282 GFP_KERNEL);
283 if (!tx_queue->tx_skbuff)
fba4ed03 284 goto cleanup;
826aa4a0 285
fba4ed03
SG		 286 for (k = 0; k < tx_queue->tx_ring_size; k++)
287 tx_queue->tx_skbuff[k] = NULL;
288 }
826aa4a0 289
fba4ed03
SG		 290 for (i = 0; i < priv->num_rx_queues; i++) {
291 rx_queue = priv->rx_queue[i];
14f8dc49
JP		 292 rx_queue->rx_skbuff =
293 kmalloc_array(rx_queue->rx_ring_size,
294 sizeof(*rx_queue->rx_skbuff),
295 GFP_KERNEL);
296 if (!rx_queue->rx_skbuff)
fba4ed03 297 goto cleanup;
fba4ed03
SG		 298
299 for (j = 0; j < rx_queue->rx_ring_size; j++)
300 rx_queue->rx_skbuff[j] = NULL;
301 }
826aa4a0 302
8728327e
AV		 303 if (gfar_init_bds(ndev))
304 goto cleanup;
826aa4a0
AV		 305
306 return 0;
307
308cleanup:
309 free_skb_resources(priv);
310 return -ENOMEM;
311}
312
fba4ed03
SG		 313static void gfar_init_tx_rx_base(struct gfar_private *priv)
314{
46ceb60c 315 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 316 u32 __iomem *baddr;
fba4ed03
SG		 317 int i;
318
319 baddr = &regs->tbase0;
bc4598bc 320 for (i = 0; i < priv->num_tx_queues; i++) {
fba4ed03 321 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
bc4598bc 322 baddr += 2;
fba4ed03
SG		 323 }
324
325 baddr = &regs->rbase0;
bc4598bc 326 for (i = 0; i < priv->num_rx_queues; i++) {
fba4ed03 327 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
bc4598bc 328 baddr += 2;
fba4ed03
SG		 329 }
330}
331
826aa4a0
AV		 332static void gfar_init_mac(struct net_device *ndev)
333{
334 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 335 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 336 u32 rctrl = 0;
337 u32 tctrl = 0;
338 u32 attrs = 0;
339
fba4ed03
SG		 340 /* write the tx/rx base registers */
341 gfar_init_tx_rx_base(priv);
32c513bc 342
826aa4a0 343 /* Configure the coalescing support */
800c644b 344 gfar_configure_coalescing_all(priv);
fba4ed03 345
ba779711
CM		 346 /* set this when rx hw offload (TOE) functions are being used */
347 priv->uses_rxfcb = 0;
348
1ccb8389 349 if (priv->rx_filer_enable) {
fba4ed03 350 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 351 /* Program the RIR0 reg with the required distribution */
352 gfar_write(&regs->rir0, DEFAULT_RIR0);
353 }
826aa4a0 354
f5ae6279
CM		 355 /* Restore PROMISC mode */
356 if (ndev->flags & IFF_PROMISC)
357 rctrl |= RCTRL_PROM;
358
ba779711 359 if (ndev->features & NETIF_F_RXCSUM) {
826aa4a0 360 rctrl |= RCTRL_CHECKSUMMING;
ba779711
CM		 361 priv->uses_rxfcb = 1;
362 }
826aa4a0
AV		 363
364 if (priv->extended_hash) {
365 rctrl |= RCTRL_EXTHASH;
366
367 gfar_clear_exact_match(ndev);
368 rctrl |= RCTRL_EMEN;
369 }
370
371 if (priv->padding) {
372 rctrl &= ~RCTRL_PAL_MASK;
373 rctrl |= RCTRL_PADDING(priv->padding);
374 }
375
cc772ab7
MR		 376 /* Insert receive time stamps into padding alignment bytes */
377 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
378 rctrl &= ~RCTRL_PAL_MASK;
97553f7f 379 rctrl |= RCTRL_PADDING(8);
cc772ab7
MR		 380 priv->padding = 8;
381 }
382
97553f7f 383 /* Enable HW time stamping if requested from user space */
ba779711 384 if (priv->hwts_rx_en) {
97553f7f 385 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
ba779711
CM		 386 priv->uses_rxfcb = 1;
387 }
97553f7f 388
f646968f 389 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) {
b852b720 390 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
ba779711
CM		 391 priv->uses_rxfcb = 1;
392 }
826aa4a0
AV		 393
394 /* Init rctrl based on our settings */
395 gfar_write(&regs->rctrl, rctrl);
396
397 if (ndev->features & NETIF_F_IP_CSUM)
398 tctrl |= TCTRL_INIT_CSUM;
399
b98b8bab
CM		 400 if (priv->prio_sched_en)
401 tctrl |= TCTRL_TXSCHED_PRIO;
402 else {
403 tctrl |= TCTRL_TXSCHED_WRRS;
404 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
405 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
406 }
fba4ed03 407
826aa4a0
AV		 408 gfar_write(&regs->tctrl, tctrl);
409
410 /* Set the extraction length and index */
411 attrs = ATTRELI_EL(priv->rx_stash_size) |
412 ATTRELI_EI(priv->rx_stash_index);
413
414 gfar_write(&regs->attreli, attrs);
415
416 /* Start with defaults, and add stashing or locking
0977f817
JC		 417 * depending on the approprate variables
418 */
826aa4a0
AV		 419 attrs = ATTR_INIT_SETTINGS;
420
421 if (priv->bd_stash_en)
422 attrs |= ATTR_BDSTASH;
423
424 if (priv->rx_stash_size != 0)
425 attrs |= ATTR_BUFSTASH;
426
427 gfar_write(&regs->attr, attrs);
428
429 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
430 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
431 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
432}
433
a7f38041
SG		 434static struct net_device_stats *gfar_get_stats(struct net_device *dev)
435{
436 struct gfar_private *priv = netdev_priv(dev);
a7f38041
SG		 437 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
438 unsigned long tx_packets = 0, tx_bytes = 0;
3a2e16c8 439 int i;
a7f38041
SG		 440
441 for (i = 0; i < priv->num_rx_queues; i++) {
442 rx_packets += priv->rx_queue[i]->stats.rx_packets;
bc4598bc 443 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
a7f38041
SG		 444 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
445 }
446
447 dev->stats.rx_packets = rx_packets;
bc4598bc 448 dev->stats.rx_bytes = rx_bytes;
a7f38041
SG		 449 dev->stats.rx_dropped = rx_dropped;
450
451 for (i = 0; i < priv->num_tx_queues; i++) {
1ac9ad13
ED		 452 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
453 tx_packets += priv->tx_queue[i]->stats.tx_packets;
a7f38041
SG		 454 }
455
bc4598bc 456 dev->stats.tx_bytes = tx_bytes;
a7f38041
SG		 457 dev->stats.tx_packets = tx_packets;
458
459 return &dev->stats;
460}
461
26ccfc37
AF		 462static const struct net_device_ops gfar_netdev_ops = {
463 .ndo_open = gfar_enet_open,
464 .ndo_start_xmit = gfar_start_xmit,
465 .ndo_stop = gfar_close,
466 .ndo_change_mtu = gfar_change_mtu,
8b3afe95 467 .ndo_set_features = gfar_set_features,
afc4b13d 468 .ndo_set_rx_mode = gfar_set_multi,
26ccfc37
AF		 469 .ndo_tx_timeout = gfar_timeout,
470 .ndo_do_ioctl = gfar_ioctl,
a7f38041 471 .ndo_get_stats = gfar_get_stats,
240c102d
BH		 472 .ndo_set_mac_address = eth_mac_addr,
473 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 474#ifdef CONFIG_NET_POLL_CONTROLLER
475 .ndo_poll_controller = gfar_netpoll,
476#endif
477};
478
fba4ed03
SG		 479void lock_rx_qs(struct gfar_private *priv)
480{
3a2e16c8 481 int i;
fba4ed03
SG		 482
483 for (i = 0; i < priv->num_rx_queues; i++)
484 spin_lock(&priv->rx_queue[i]->rxlock);
485}
486
487void lock_tx_qs(struct gfar_private *priv)
488{
3a2e16c8 489 int i;
fba4ed03
SG		 490
491 for (i = 0; i < priv->num_tx_queues; i++)
492 spin_lock(&priv->tx_queue[i]->txlock);
493}
494
495void unlock_rx_qs(struct gfar_private *priv)
496{
3a2e16c8 497 int i;
fba4ed03
SG		 498
499 for (i = 0; i < priv->num_rx_queues; i++)
500 spin_unlock(&priv->rx_queue[i]->rxlock);
501}
502
503void unlock_tx_qs(struct gfar_private *priv)
504{
3a2e16c8 505 int i;
fba4ed03
SG		 506
507 for (i = 0; i < priv->num_tx_queues; i++)
508 spin_unlock(&priv->tx_queue[i]->txlock);
509}
510
fba4ed03
SG		 511static void free_tx_pointers(struct gfar_private *priv)
512{
3a2e16c8 513 int i;
fba4ed03
SG		 514
515 for (i = 0; i < priv->num_tx_queues; i++)
516 kfree(priv->tx_queue[i]);
517}
518
519static void free_rx_pointers(struct gfar_private *priv)
520{
3a2e16c8 521 int i;
fba4ed03
SG		 522
523 for (i = 0; i < priv->num_rx_queues; i++)
524 kfree(priv->rx_queue[i]);
525}
526
46ceb60c
SG		 527static void unmap_group_regs(struct gfar_private *priv)
528{
3a2e16c8 529 int i;
46ceb60c
SG		 530
531 for (i = 0; i < MAXGROUPS; i++)
532 if (priv->gfargrp[i].regs)
533 iounmap(priv->gfargrp[i].regs);
534}
535
ee873fda
CM		 536static void free_gfar_dev(struct gfar_private *priv)
537{
538 int i, j;
539
540 for (i = 0; i < priv->num_grps; i++)
541 for (j = 0; j < GFAR_NUM_IRQS; j++) {
542 kfree(priv->gfargrp[i].irqinfo[j]);
543 priv->gfargrp[i].irqinfo[j] = NULL;
544 }
545
546 free_netdev(priv->ndev);
547}
548
46ceb60c
SG		 549static void disable_napi(struct gfar_private *priv)
550{
3a2e16c8 551 int i;
46ceb60c
SG		 552
553 for (i = 0; i < priv->num_grps; i++)
554 napi_disable(&priv->gfargrp[i].napi);
555}
556
557static void enable_napi(struct gfar_private *priv)
558{
3a2e16c8 559 int i;
46ceb60c
SG		 560
561 for (i = 0; i < priv->num_grps; i++)
562 napi_enable(&priv->gfargrp[i].napi);
563}
564
565static int gfar_parse_group(struct device_node *np,
bc4598bc 566 struct gfar_private *priv, const char *model)
46ceb60c 567{
5fedcc14 568 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
46ceb60c 569 u32 *queue_mask;
ee873fda
CM		 570 int i;
571
7c1e7e99
PG		 572 for (i = 0; i < GFAR_NUM_IRQS; i++) {
573 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
574 GFP_KERNEL);
575 if (!grp->irqinfo[i])
ee873fda 576 return -ENOMEM;
ee873fda 577 }
46ceb60c 578
5fedcc14
CM		 579 grp->regs = of_iomap(np, 0);
580 if (!grp->regs)
46ceb60c
SG		 581 return -ENOMEM;
582
ee873fda 583 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
46ceb60c
SG		 584
585 /* If we aren't the FEC we have multiple interrupts */
586 if (model && strcasecmp(model, "FEC")) {
ee873fda
CM		 587 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
588 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
589 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
590 gfar_irq(grp, RX)->irq == NO_IRQ ||
591 gfar_irq(grp, ER)->irq == NO_IRQ)
46ceb60c 592 return -EINVAL;
46ceb60c
SG		 593 }
594
5fedcc14
CM		 595 grp->grp_id = priv->num_grps;
596 grp->priv = priv;
597 spin_lock_init(&grp->grplock);
bc4598bc
JC		 598 if (priv->mode == MQ_MG_MODE) {
599 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
5fedcc14 600 grp->rx_bit_map = queue_mask ?
bc4598bc
JC		 601 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
602 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
5fedcc14 603 grp->tx_bit_map = queue_mask ?
bc4598bc 604 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
46ceb60c 605 } else {
5fedcc14
CM		 606 grp->rx_bit_map = 0xFF;
607 grp->tx_bit_map = 0xFF;
46ceb60c
SG		 608 }
609 priv->num_grps++;
610
611 return 0;
612}
613
2dc11581 614static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 615{
b31a1d8b
AF		 616 const char *model;
617 const char *ctype;
618 const void *mac_addr;
fba4ed03
SG		 619 int err = 0, i;
620 struct net_device *dev = NULL;
621 struct gfar_private *priv = NULL;
61c7a080 622 struct device_node *np = ofdev->dev.of_node;
46ceb60c 623 struct device_node *child = NULL;
4d7902f2
AF		 624 const u32 *stash;
625 const u32 *stash_len;
626 const u32 *stash_idx;
fba4ed03
SG		 627 unsigned int num_tx_qs, num_rx_qs;
628 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 629
630 if (!np || !of_device_is_available(np))
631 return -ENODEV;
632
fba4ed03
SG		 633 /* parse the num of tx and rx queues */
634 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
635 num_tx_qs = tx_queues ? *tx_queues : 1;
636
637 if (num_tx_qs > MAX_TX_QS) {
59deab26
JP		 638 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
639 num_tx_qs, MAX_TX_QS);
640 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 641 return -EINVAL;
642 }
643
644 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
645 num_rx_qs = rx_queues ? *rx_queues : 1;
646
647 if (num_rx_qs > MAX_RX_QS) {
59deab26
JP		 648 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
649 num_rx_qs, MAX_RX_QS);
650 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 651 return -EINVAL;
652 }
653
654 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
655 dev = *pdev;
656 if (NULL == dev)
657 return -ENOMEM;
658
659 priv = netdev_priv(dev);
fba4ed03
SG		 660 priv->ndev = dev;
661
fba4ed03 662 priv->num_tx_queues = num_tx_qs;
fe069123 663 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 664 priv->num_rx_queues = num_rx_qs;
46ceb60c 665 priv->num_grps = 0x0;
b31a1d8b 666
0977f817 667 /* Init Rx queue filer rule set linked list */
4aa3a715
SP		 668 INIT_LIST_HEAD(&priv->rx_list.list);
669 priv->rx_list.count = 0;
670 mutex_init(&priv->rx_queue_access);
671
b31a1d8b
AF		 672 model = of_get_property(np, "model", NULL);
673
46ceb60c
SG		 674 for (i = 0; i < MAXGROUPS; i++)
675 priv->gfargrp[i].regs = NULL;
b31a1d8b 676
46ceb60c
SG		 677 /* Parse and initialize group specific information */
678 if (of_device_is_compatible(np, "fsl,etsec2")) {
679 priv->mode = MQ_MG_MODE;
680 for_each_child_of_node(np, child) {
681 err = gfar_parse_group(child, priv, model);
682 if (err)
683 goto err_grp_init;
b31a1d8b 684 }
46ceb60c
SG		 685 } else {
686 priv->mode = SQ_SG_MODE;
687 err = gfar_parse_group(np, priv, model);
bc4598bc 688 if (err)
46ceb60c 689 goto err_grp_init;
b31a1d8b
AF		 690 }
691
fba4ed03 692 for (i = 0; i < priv->num_tx_queues; i++)
c6e1160e 693 priv->tx_queue[i] = NULL;
fba4ed03
SG		 694 for (i = 0; i < priv->num_rx_queues; i++)
695 priv->rx_queue[i] = NULL;
696
697 for (i = 0; i < priv->num_tx_queues; i++) {
de47f072
JP		 698 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
699 GFP_KERNEL);
fba4ed03
SG		 700 if (!priv->tx_queue[i]) {
701 err = -ENOMEM;
702 goto tx_alloc_failed;
703 }
704 priv->tx_queue[i]->tx_skbuff = NULL;
705 priv->tx_queue[i]->qindex = i;
706 priv->tx_queue[i]->dev = dev;
707 spin_lock_init(&(priv->tx_queue[i]->txlock));
708 }
709
710 for (i = 0; i < priv->num_rx_queues; i++) {
de47f072
JP		 711 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
712 GFP_KERNEL);
fba4ed03
SG		 713 if (!priv->rx_queue[i]) {
714 err = -ENOMEM;
715 goto rx_alloc_failed;
716 }
717 priv->rx_queue[i]->rx_skbuff = NULL;
718 priv->rx_queue[i]->qindex = i;
719 priv->rx_queue[i]->dev = dev;
720 spin_lock_init(&(priv->rx_queue[i]->rxlock));
721 }
722
723
4d7902f2
AF		 724 stash = of_get_property(np, "bd-stash", NULL);
725
a12f801d 726 if (stash) {
4d7902f2
AF		 727 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
728 priv->bd_stash_en = 1;
729 }
730
731 stash_len = of_get_property(np, "rx-stash-len", NULL);
732
733 if (stash_len)
734 priv->rx_stash_size = *stash_len;
735
736 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
737
738 if (stash_idx)
739 priv->rx_stash_index = *stash_idx;
740
741 if (stash_len || stash_idx)
742 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
743
b31a1d8b 744 mac_addr = of_get_mac_address(np);
bc4598bc 745
b31a1d8b 746 if (mac_addr)
6a3c910c 747 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
b31a1d8b
AF		 748
749 if (model && !strcasecmp(model, "TSEC"))
bc4598bc
JC		 750 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
751 FSL_GIANFAR_DEV_HAS_COALESCE |
752 FSL_GIANFAR_DEV_HAS_RMON |
753 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
754
b31a1d8b 755 if (model && !strcasecmp(model, "eTSEC"))
bc4598bc
JC		 756 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
757 FSL_GIANFAR_DEV_HAS_COALESCE |
758 FSL_GIANFAR_DEV_HAS_RMON |
759 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
760 FSL_GIANFAR_DEV_HAS_PADDING |
761 FSL_GIANFAR_DEV_HAS_CSUM |
762 FSL_GIANFAR_DEV_HAS_VLAN |
763 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
764 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
765 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 766
767 ctype = of_get_property(np, "phy-connection-type", NULL);
768
769 /* We only care about rgmii-id. The rest are autodetected */
770 if (ctype && !strcmp(ctype, "rgmii-id"))
771 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
772 else
773 priv->interface = PHY_INTERFACE_MODE_MII;
774
775 if (of_get_property(np, "fsl,magic-packet", NULL))
776 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
777
fe192a49 778 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 779
780 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 781 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 782
783 return 0;
784
fba4ed03
SG		 785rx_alloc_failed:
786 free_rx_pointers(priv);
787tx_alloc_failed:
788 free_tx_pointers(priv);
46ceb60c
SG		 789err_grp_init:
790 unmap_group_regs(priv);
ee873fda 791 free_gfar_dev(priv);
b31a1d8b
AF		 792 return err;
793}
794
cc772ab7 795static int gfar_hwtstamp_ioctl(struct net_device *netdev,
bc4598bc 796 struct ifreq *ifr, int cmd)
cc772ab7
MR		 797{
798 struct hwtstamp_config config;
799 struct gfar_private *priv = netdev_priv(netdev);
800
801 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
802 return -EFAULT;
803
804 /* reserved for future extensions */
805 if (config.flags)
806 return -EINVAL;
807
f0ee7acf
MR		 808 switch (config.tx_type) {
809 case HWTSTAMP_TX_OFF:
810 priv->hwts_tx_en = 0;
811 break;
812 case HWTSTAMP_TX_ON:
813 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
814 return -ERANGE;
815 priv->hwts_tx_en = 1;
816 break;
817 default:
cc772ab7 818 return -ERANGE;
f0ee7acf 819 }
cc772ab7
MR		 820
821 switch (config.rx_filter) {
822 case HWTSTAMP_FILTER_NONE:
97553f7f
MR		 823 if (priv->hwts_rx_en) {
824 stop_gfar(netdev);
825 priv->hwts_rx_en = 0;
826 startup_gfar(netdev);
827 }
cc772ab7
MR		 828 break;
829 default:
830 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
831 return -ERANGE;
97553f7f
MR		 832 if (!priv->hwts_rx_en) {
833 stop_gfar(netdev);
834 priv->hwts_rx_en = 1;
835 startup_gfar(netdev);
836 }
cc772ab7
MR		 837 config.rx_filter = HWTSTAMP_FILTER_ALL;
838 break;
839 }
840
841 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
842 -EFAULT : 0;
843}
844
0faac9f7
CW		 845/* Ioctl MII Interface */
846static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
847{
848 struct gfar_private *priv = netdev_priv(dev);
849
850 if (!netif_running(dev))
851 return -EINVAL;
852
cc772ab7
MR		 853 if (cmd == SIOCSHWTSTAMP)
854 return gfar_hwtstamp_ioctl(dev, rq, cmd);
855
0faac9f7
CW		 856 if (!priv->phydev)
857 return -ENODEV;
858
28b04113 859 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 860}
861
fba4ed03
SG		 862static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
863{
864 unsigned int new_bit_map = 0x0;
865 int mask = 0x1 << (max_qs - 1), i;
bc4598bc 866
fba4ed03
SG		 867 for (i = 0; i < max_qs; i++) {
868 if (bit_map & mask)
869 new_bit_map = new_bit_map + (1 << i);
870 mask = mask >> 0x1;
871 }
872 return new_bit_map;
873}
7a8b3372 874
18294ad1
AV		 875static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
876 u32 class)
7a8b3372
SG		 877{
878 u32 rqfpr = FPR_FILER_MASK;
879 u32 rqfcr = 0x0;
880
881 rqfar--;
882 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
6c43e046
WJB		 883 priv->ftp_rqfpr[rqfar] = rqfpr;
884 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 885 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
886
887 rqfar--;
888 rqfcr = RQFCR_CMP_NOMATCH;
6c43e046
WJB		 889 priv->ftp_rqfpr[rqfar] = rqfpr;
890 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 891 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
892
893 rqfar--;
894 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
895 rqfpr = class;
6c43e046
WJB		 896 priv->ftp_rqfcr[rqfar] = rqfcr;
897 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
899
900 rqfar--;
901 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
902 rqfpr = class;
6c43e046
WJB		 903 priv->ftp_rqfcr[rqfar] = rqfcr;
904 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 905 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
906
907 return rqfar;
908}
909
910static void gfar_init_filer_table(struct gfar_private *priv)
911{
912 int i = 0x0;
913 u32 rqfar = MAX_FILER_IDX;
914 u32 rqfcr = 0x0;
915 u32 rqfpr = FPR_FILER_MASK;
916
917 /* Default rule */
918 rqfcr = RQFCR_CMP_MATCH;
6c43e046
WJB		 919 priv->ftp_rqfcr[rqfar] = rqfcr;
920 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 921 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
922
923 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
924 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
925 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
926 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
927 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
928 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
929
85dd08eb 930 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 931 priv->cur_filer_idx = rqfar;
932
933 /* Rest are masked rules */
934 rqfcr = RQFCR_CMP_NOMATCH;
935 for (i = 0; i < rqfar; i++) {
6c43e046
WJB		 936 priv->ftp_rqfcr[i] = rqfcr;
937 priv->ftp_rqfpr[i] = rqfpr;
7a8b3372
SG		 938 gfar_write_filer(priv, i, rqfcr, rqfpr);
939 }
940}
941
7d350977
AV		 942static void gfar_detect_errata(struct gfar_private *priv)
943{
944 struct device *dev = &priv->ofdev->dev;
945 unsigned int pvr = mfspr(SPRN_PVR);
946 unsigned int svr = mfspr(SPRN_SVR);
947 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
948 unsigned int rev = svr & 0xffff;
949
950 /* MPC8313 Rev 2.0 and higher; All MPC837x */
951 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
bc4598bc 952 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
7d350977
AV		 953 priv->errata |= GFAR_ERRATA_74;
954
deb90eac
AV		 955 /* MPC8313 and MPC837x all rev */
956 if ((pvr == 0x80850010 && mod == 0x80b0) ||
bc4598bc 957 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
deb90eac
AV		 958 priv->errata |= GFAR_ERRATA_76;
959
511d934f
AV		 960 /* MPC8313 and MPC837x all rev */
961 if ((pvr == 0x80850010 && mod == 0x80b0) ||
bc4598bc 962 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
511d934f
AV		 963 priv->errata |= GFAR_ERRATA_A002;
964
4363c2fd
AD		 965 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
966 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
bc4598bc 967 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
4363c2fd
AD		 968 priv->errata |= GFAR_ERRATA_12;
969
7d350977
AV		 970 if (priv->errata)
971 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
972 priv->errata);
973}
974
bb40dcbb 975/* Set up the ethernet device structure, private data,
0977f817
JC		 976 * and anything else we need before we start
977 */
74888760 978static int gfar_probe(struct platform_device *ofdev)
1da177e4
LT		 979{
980 u32 tempval;
981 struct net_device *dev = NULL;
982 struct gfar_private *priv = NULL;
f4983704 983 struct gfar __iomem *regs = NULL;
46ceb60c 984 int err = 0, i, grp_idx = 0;
fba4ed03 985 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 986 u32 isrg = 0;
18294ad1 987 u32 __iomem *baddr;
1da177e4 988
fba4ed03 989 err = gfar_of_init(ofdev, &dev);
1da177e4 990
fba4ed03
SG		 991 if (err)
992 return err;
1da177e4
LT		 993
994 priv = netdev_priv(dev);
4826857f
KG		 995 priv->ndev = dev;
996 priv->ofdev = ofdev;
369ec162 997 priv->dev = &ofdev->dev;
4826857f 998 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 999
d87eb127 1000 spin_lock_init(&priv->bflock);
ab939905 1001 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 1002
8513fbd8 1003 platform_set_drvdata(ofdev, priv);
46ceb60c 1004 regs = priv->gfargrp[0].regs;
1da177e4 1005
7d350977
AV		 1006 gfar_detect_errata(priv);
1007
0977f817
JC		 1008 /* Stop the DMA engine now, in case it was running before
1009 * (The firmware could have used it, and left it running).
1010 */
257d938a 1011 gfar_halt(dev);
1da177e4
LT		 1012
1013 /* Reset MAC layer */
f4983704 1014 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 1015
b98ac702
AF		 1016 /* We need to delay at least 3 TX clocks */
1017 udelay(2);
1018
1da177e4 1019 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 1020 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 1021
1022 /* Initialize MACCFG2. */
7d350977
AV		 1023 tempval = MACCFG2_INIT_SETTINGS;
1024 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1025 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1026 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 1027
1028 /* Initialize ECNTRL */
f4983704 1029 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 1030
1da177e4 1031 /* Set the dev->base_addr to the gfar reg region */
f4983704 1032 dev->base_addr = (unsigned long) regs;
1da177e4 1033
1da177e4 1034 /* Fill in the dev structure */
1da177e4 1035 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1036 dev->mtu = 1500;
26ccfc37 1037 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1038 dev->ethtool_ops = &gfar_ethtool_ops;
1039
fba4ed03 1040 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c 1041 for (i = 0; i < priv->num_grps; i++)
bc4598bc
JC		 1042 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1043 GFAR_DEV_WEIGHT);
a12f801d 1044
b31a1d8b 1045 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
8b3afe95 1046 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1047 NETIF_F_RXCSUM;
8b3afe95 1048 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1049 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
8b3afe95 1050 }
0bbaf069 1051
87c288c6 1052 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
f646968f
PM		 1053 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1054 NETIF_F_HW_VLAN_CTAG_RX;
1055 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
87c288c6 1056 }
0bbaf069 1057
b31a1d8b 1058 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 1059 priv->extended_hash = 1;
1060 priv->hash_width = 9;
1061
f4983704
SG		 1062 priv->hash_regs[0] = &regs->igaddr0;
1063 priv->hash_regs[1] = &regs->igaddr1;
1064 priv->hash_regs[2] = &regs->igaddr2;
1065 priv->hash_regs[3] = &regs->igaddr3;
1066 priv->hash_regs[4] = &regs->igaddr4;
1067 priv->hash_regs[5] = &regs->igaddr5;
1068 priv->hash_regs[6] = &regs->igaddr6;
1069 priv->hash_regs[7] = &regs->igaddr7;
1070 priv->hash_regs[8] = &regs->gaddr0;
1071 priv->hash_regs[9] = &regs->gaddr1;
1072 priv->hash_regs[10] = &regs->gaddr2;
1073 priv->hash_regs[11] = &regs->gaddr3;
1074 priv->hash_regs[12] = &regs->gaddr4;
1075 priv->hash_regs[13] = &regs->gaddr5;
1076 priv->hash_regs[14] = &regs->gaddr6;
1077 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 1078
1079 } else {
1080 priv->extended_hash = 0;
1081 priv->hash_width = 8;
1082
f4983704
SG		 1083 priv->hash_regs[0] = &regs->gaddr0;
1084 priv->hash_regs[1] = &regs->gaddr1;
1085 priv->hash_regs[2] = &regs->gaddr2;
1086 priv->hash_regs[3] = &regs->gaddr3;
1087 priv->hash_regs[4] = &regs->gaddr4;
1088 priv->hash_regs[5] = &regs->gaddr5;
1089 priv->hash_regs[6] = &regs->gaddr6;
1090 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 1091 }
1092
b31a1d8b 1093 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 1094 priv->padding = DEFAULT_PADDING;
1095 else
1096 priv->padding = 0;
1097
cc772ab7 1098 if (dev->features & NETIF_F_IP_CSUM ||
bc4598bc 1099 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
bee9e58c 1100 dev->needed_headroom = GMAC_FCB_LEN;
1da177e4 1101
46ceb60c
SG		 1102 /* Program the isrg regs only if number of grps > 1 */
1103 if (priv->num_grps > 1) {
1104 baddr = &regs->isrg0;
1105 for (i = 0; i < priv->num_grps; i++) {
1106 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1107 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1108 gfar_write(baddr, isrg);
1109 baddr++;
1110 isrg = 0x0;
1111 }
1112 }
1113
fba4ed03 1114 /* Need to reverse the bit maps as bit_map's MSB is q0
984b3f57 1115 * but, for_each_set_bit parses from right to left, which
0977f817
JC		 1116 * basically reverses the queue numbers
1117 */
46ceb60c 1118 for (i = 0; i< priv->num_grps; i++) {
bc4598bc
JC		 1119 priv->gfargrp[i].tx_bit_map =
1120 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1121 priv->gfargrp[i].rx_bit_map =
1122 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
46ceb60c
SG		 1123 }
1124
1125 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
0977f817
JC		 1126 * also assign queues to groups
1127 */
46ceb60c
SG		 1128 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1129 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
bc4598bc 1130
984b3f57 1131 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
bc4598bc 1132 priv->num_rx_queues) {
46ceb60c
SG		 1133 priv->gfargrp[grp_idx].num_rx_queues++;
1134 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1135 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1136 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1137 }
1138 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
bc4598bc 1139
984b3f57 1140 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
bc4598bc 1141 priv->num_tx_queues) {
46ceb60c
SG		 1142 priv->gfargrp[grp_idx].num_tx_queues++;
1143 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1144 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1145 tqueue = tqueue | (TQUEUE_EN0 >> i);
1146 }
1147 priv->gfargrp[grp_idx].rstat = rstat;
1148 priv->gfargrp[grp_idx].tstat = tstat;
1149 rstat = tstat =0;
fba4ed03 1150 }
fba4ed03
SG		 1151
1152 gfar_write(&regs->rqueue, rqueue);
1153 gfar_write(&regs->tqueue, tqueue);
1154
1da177e4 1155 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1156
a12f801d 1157 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1158 for (i = 0; i < priv->num_tx_queues; i++) {
1159 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1160 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1161 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1162 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1163 }
a12f801d 1164
fba4ed03
SG		 1165 for (i = 0; i < priv->num_rx_queues; i++) {
1166 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1167 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1168 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1169 }
1da177e4 1170
0977f817 1171 /* always enable rx filer */
4aa3a715 1172 priv->rx_filer_enable = 1;
0bbaf069
KG		 1173 /* Enable most messages by default */
1174 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
b98b8bab
CM		 1175 /* use pritority h/w tx queue scheduling for single queue devices */
1176 if (priv->num_tx_queues == 1)
1177 priv->prio_sched_en = 1;
0bbaf069 1178
d3eab82b
TP		 1179 /* Carrier starts down, phylib will bring it up */
1180 netif_carrier_off(dev);
1181
1da177e4
LT		 1182 err = register_netdev(dev);
1183
1184 if (err) {
59deab26 1185 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1da177e4
LT		 1186 goto register_fail;
1187 }
1188
2884e5cc 1189 device_init_wakeup(&dev->dev,
bc4598bc
JC		 1190 priv->device_flags &
1191 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
2884e5cc 1192
c50a5d9a 1193 /* fill out IRQ number and name fields */
46ceb60c 1194 for (i = 0; i < priv->num_grps; i++) {
ee873fda 1195 struct gfar_priv_grp *grp = &priv->gfargrp[i];
46ceb60c 1196 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
ee873fda 1197 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
0015e551 1198 dev->name, "_g", '0' + i, "_tx");
ee873fda 1199 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
0015e551 1200 dev->name, "_g", '0' + i, "_rx");
ee873fda 1201 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
0015e551 1202 dev->name, "_g", '0' + i, "_er");
46ceb60c 1203 } else
ee873fda 1204 strcpy(gfar_irq(grp, TX)->name, dev->name);
46ceb60c 1205 }
c50a5d9a 1206
7a8b3372
SG		 1207 /* Initialize the filer table */
1208 gfar_init_filer_table(priv);
1209
7f7f5316
AF		 1210 /* Create all the sysfs files */
1211 gfar_init_sysfs(dev);
1212
1da177e4 1213 /* Print out the device info */
59deab26 1214 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1da177e4 1215
0977f817
JC		 1216 /* Even more device info helps when determining which kernel
1217 * provided which set of benchmarks.
1218 */
59deab26 1219 netdev_info(dev, "Running with NAPI enabled\n");
fba4ed03 1220 for (i = 0; i < priv->num_rx_queues; i++)
59deab26
JP		 1221 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1222 i, priv->rx_queue[i]->rx_ring_size);
bc4598bc 1223 for (i = 0; i < priv->num_tx_queues; i++)
59deab26
JP		 1224 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1225 i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1226
1227 return 0;
1228
1229register_fail:
46ceb60c 1230 unmap_group_regs(priv);
fba4ed03
SG		 1231 free_tx_pointers(priv);
1232 free_rx_pointers(priv);
fe192a49
GL		 1233 if (priv->phy_node)
1234 of_node_put(priv->phy_node);
1235 if (priv->tbi_node)
1236 of_node_put(priv->tbi_node);
ee873fda 1237 free_gfar_dev(priv);
bb40dcbb 1238 return err;
1da177e4
LT		 1239}
1240
2dc11581 1241static int gfar_remove(struct platform_device *ofdev)
1da177e4 1242{
8513fbd8 1243 struct gfar_private *priv = platform_get_drvdata(ofdev);
1da177e4 1244
fe192a49
GL		 1245 if (priv->phy_node)
1246 of_node_put(priv->phy_node);
1247 if (priv->tbi_node)
1248 of_node_put(priv->tbi_node);
1249
d9d8e041 1250 unregister_netdev(priv->ndev);
46ceb60c 1251 unmap_group_regs(priv);
ee873fda 1252 free_gfar_dev(priv);
1da177e4
LT		 1253
1254 return 0;
1255}
1256
d87eb127 1257#ifdef CONFIG_PM
be926fc4
AV		 1258
1259static int gfar_suspend(struct device *dev)
d87eb127 1260{
be926fc4
AV		 1261 struct gfar_private *priv = dev_get_drvdata(dev);
1262 struct net_device *ndev = priv->ndev;
46ceb60c 1263 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1264 unsigned long flags;
1265 u32 tempval;
1266
1267 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1268 (priv->device_flags &
1269 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1270
be926fc4 1271 netif_device_detach(ndev);
d87eb127 1272
be926fc4 1273 if (netif_running(ndev)) {
fba4ed03
SG		 1274
1275 local_irq_save(flags);
1276 lock_tx_qs(priv);
1277 lock_rx_qs(priv);
d87eb127 1278
be926fc4 1279 gfar_halt_nodisable(ndev);
d87eb127
SW		 1280
1281 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1282 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1283
1284 tempval &= ~MACCFG1_TX_EN;
1285
1286 if (!magic_packet)
1287 tempval &= ~MACCFG1_RX_EN;
1288
f4983704 1289 gfar_write(&regs->maccfg1, tempval);
d87eb127 1290
fba4ed03
SG		 1291 unlock_rx_qs(priv);
1292 unlock_tx_qs(priv);
1293 local_irq_restore(flags);
d87eb127 1294
46ceb60c 1295 disable_napi(priv);
d87eb127
SW		 1296
1297 if (magic_packet) {
1298 /* Enable interrupt on Magic Packet */
f4983704 1299 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1300
1301 /* Enable Magic Packet mode */
f4983704 1302 tempval = gfar_read(&regs->maccfg2);
d87eb127 1303 tempval |= MACCFG2_MPEN;
f4983704 1304 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1305 } else {
1306 phy_stop(priv->phydev);
1307 }
1308 }
1309
1310 return 0;
1311}
1312
be926fc4 1313static int gfar_resume(struct device *dev)
d87eb127 1314{
be926fc4
AV		 1315 struct gfar_private *priv = dev_get_drvdata(dev);
1316 struct net_device *ndev = priv->ndev;
46ceb60c 1317 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1318 unsigned long flags;
1319 u32 tempval;
1320 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1321 (priv->device_flags &
1322 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1323
be926fc4
AV		 1324 if (!netif_running(ndev)) {
1325 netif_device_attach(ndev);
d87eb127
SW		 1326 return 0;
1327 }
1328
1329 if (!magic_packet && priv->phydev)
1330 phy_start(priv->phydev);
1331
1332 /* Disable Magic Packet mode, in case something
1333 * else woke us up.
1334 */
fba4ed03
SG		 1335 local_irq_save(flags);
1336 lock_tx_qs(priv);
1337 lock_rx_qs(priv);
d87eb127 1338
f4983704 1339 tempval = gfar_read(&regs->maccfg2);
d87eb127 1340 tempval &= ~MACCFG2_MPEN;
f4983704 1341 gfar_write(&regs->maccfg2, tempval);
d87eb127 1342
be926fc4 1343 gfar_start(ndev);
d87eb127 1344
fba4ed03
SG		 1345 unlock_rx_qs(priv);
1346 unlock_tx_qs(priv);
1347 local_irq_restore(flags);
d87eb127 1348
be926fc4
AV		 1349 netif_device_attach(ndev);
1350
46ceb60c 1351 enable_napi(priv);
be926fc4
AV		 1352
1353 return 0;
1354}
1355
1356static int gfar_restore(struct device *dev)
1357{
1358 struct gfar_private *priv = dev_get_drvdata(dev);
1359 struct net_device *ndev = priv->ndev;
1360
103cdd1d
WD		 1361 if (!netif_running(ndev)) {
1362 netif_device_attach(ndev);
1363
be926fc4 1364 return 0;
103cdd1d 1365 }
be926fc4 1366
1eb8f7a7
CM		 1367 if (gfar_init_bds(ndev)) {
1368 free_skb_resources(priv);
1369 return -ENOMEM;
1370 }
1371
be926fc4
AV		 1372 init_registers(ndev);
1373 gfar_set_mac_address(ndev);
1374 gfar_init_mac(ndev);
1375 gfar_start(ndev);
1376
1377 priv->oldlink = 0;
1378 priv->oldspeed = 0;
1379 priv->oldduplex = -1;
1380
1381 if (priv->phydev)
1382 phy_start(priv->phydev);
d87eb127 1383
be926fc4 1384 netif_device_attach(ndev);
5ea681d4 1385 enable_napi(priv);
d87eb127
SW		 1386
1387 return 0;
1388}
be926fc4
AV		 1389
1390static struct dev_pm_ops gfar_pm_ops = {
1391 .suspend = gfar_suspend,
1392 .resume = gfar_resume,
1393 .freeze = gfar_suspend,
1394 .thaw = gfar_resume,
1395 .restore = gfar_restore,
1396};
1397
1398#define GFAR_PM_OPS (&gfar_pm_ops)
1399
d87eb127 1400#else
be926fc4
AV		 1401
1402#define GFAR_PM_OPS NULL
be926fc4 1403
d87eb127 1404#endif
1da177e4 1405
e8a2b6a4
AF		 1406/* Reads the controller's registers to determine what interface
1407 * connects it to the PHY.
1408 */
1409static phy_interface_t gfar_get_interface(struct net_device *dev)
1410{
1411 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1412 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1413 u32 ecntrl;
1414
f4983704 1415 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1416
1417 if (ecntrl & ECNTRL_SGMII_MODE)
1418 return PHY_INTERFACE_MODE_SGMII;
1419
1420 if (ecntrl & ECNTRL_TBI_MODE) {
1421 if (ecntrl & ECNTRL_REDUCED_MODE)
1422 return PHY_INTERFACE_MODE_RTBI;
1423 else
1424 return PHY_INTERFACE_MODE_TBI;
1425 }
1426
1427 if (ecntrl & ECNTRL_REDUCED_MODE) {
bc4598bc 1428 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
e8a2b6a4 1429 return PHY_INTERFACE_MODE_RMII;
bc4598bc 1430 }
7132ab7f 1431 else {
b31a1d8b 1432 phy_interface_t interface = priv->interface;
7132ab7f 1433
0977f817 1434 /* This isn't autodetected right now, so it must
7132ab7f
AF		 1435 * be set by the device tree or platform code.
1436 */
1437 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1438 return PHY_INTERFACE_MODE_RGMII_ID;
1439
e8a2b6a4 1440 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1441 }
e8a2b6a4
AF		 1442 }
1443
b31a1d8b 1444 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1445 return PHY_INTERFACE_MODE_GMII;
1446
1447 return PHY_INTERFACE_MODE_MII;
1448}
1449
1450
bb40dcbb
AF		 1451/* Initializes driver's PHY state, and attaches to the PHY.
1452 * Returns 0 on success.
1da177e4
LT		 1453 */
1454static int init_phy(struct net_device *dev)
1455{
1456 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1457 uint gigabit_support =
b31a1d8b 1458 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1459 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1460 phy_interface_t interface;
1da177e4
LT		 1461
1462 priv->oldlink = 0;
1463 priv->oldspeed = 0;
1464 priv->oldduplex = -1;
1465
e8a2b6a4
AF		 1466 interface = gfar_get_interface(dev);
1467
1db780f8
AV		 1468 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1469 interface);
1470 if (!priv->phydev)
1471 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1472 interface);
1473 if (!priv->phydev) {
1474 dev_err(&dev->dev, "could not attach to PHY\n");
1475 return -ENODEV;
fe192a49 1476 }
1da177e4 1477
d3c12873
KJ		 1478 if (interface == PHY_INTERFACE_MODE_SGMII)
1479 gfar_configure_serdes(dev);
1480
bb40dcbb 1481 /* Remove any features not supported by the controller */
fe192a49
GL		 1482 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1483 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1484
1485 return 0;
1da177e4
LT		 1486}
1487
0977f817 1488/* Initialize TBI PHY interface for communicating with the
d0313587
PG		 1489 * SERDES lynx PHY on the chip. We communicate with this PHY
1490 * through the MDIO bus on each controller, treating it as a
1491 * "normal" PHY at the address found in the TBIPA register. We assume
1492 * that the TBIPA register is valid. Either the MDIO bus code will set
1493 * it to a value that doesn't conflict with other PHYs on the bus, or the
1494 * value doesn't matter, as there are no other PHYs on the bus.
1495 */
d3c12873
KJ		 1496static void gfar_configure_serdes(struct net_device *dev)
1497{
1498 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1499 struct phy_device *tbiphy;
1500
1501 if (!priv->tbi_node) {
1502 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1503 "device tree specify a tbi-handle\n");
1504 return;
1505 }
c132419e 1506
fe192a49
GL		 1507 tbiphy = of_phy_find_device(priv->tbi_node);
1508 if (!tbiphy) {
1509 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1510 return;
1511 }
d3c12873 1512
0977f817 1513 /* If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1514 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1515 * everything for us? Resetting it takes the link down and requires
1516 * several seconds for it to come back.
1517 */
fe192a49 1518 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1519 return;
d3c12873 1520
d0313587 1521 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1522 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1523
fe192a49 1524 phy_write(tbiphy, MII_ADVERTISE,
bc4598bc
JC		 1525 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1526 ADVERTISE_1000XPSE_ASYM);
d3c12873 1527
bc4598bc
JC		 1528 phy_write(tbiphy, MII_BMCR,
1529 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1530 BMCR_SPEED1000);
d3c12873
KJ		 1531}
1532
1da177e4
LT		 1533static void init_registers(struct net_device *dev)
1534{
1535 struct gfar_private *priv = netdev_priv(dev);
f4983704 1536 struct gfar __iomem *regs = NULL;
3a2e16c8 1537 int i;
1da177e4 1538
46ceb60c
SG		 1539 for (i = 0; i < priv->num_grps; i++) {
1540 regs = priv->gfargrp[i].regs;
1541 /* Clear IEVENT */
1542 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1543
46ceb60c
SG		 1544 /* Initialize IMASK */
1545 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1546 }
1da177e4 1547
46ceb60c 1548 regs = priv->gfargrp[0].regs;
1da177e4 1549 /* Init hash registers to zero */
f4983704
SG		 1550 gfar_write(&regs->igaddr0, 0);
1551 gfar_write(&regs->igaddr1, 0);
1552 gfar_write(&regs->igaddr2, 0);
1553 gfar_write(&regs->igaddr3, 0);
1554 gfar_write(&regs->igaddr4, 0);
1555 gfar_write(&regs->igaddr5, 0);
1556 gfar_write(&regs->igaddr6, 0);
1557 gfar_write(&regs->igaddr7, 0);
1558
1559 gfar_write(&regs->gaddr0, 0);
1560 gfar_write(&regs->gaddr1, 0);
1561 gfar_write(&regs->gaddr2, 0);
1562 gfar_write(&regs->gaddr3, 0);
1563 gfar_write(&regs->gaddr4, 0);
1564 gfar_write(&regs->gaddr5, 0);
1565 gfar_write(&regs->gaddr6, 0);
1566 gfar_write(&regs->gaddr7, 0);
1da177e4 1567
1da177e4 1568 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1569 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1570 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1571
1572 /* Mask off the CAM interrupts */
f4983704
SG		 1573 gfar_write(&regs->rmon.cam1, 0xffffffff);
1574 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1575 }
1576
1577 /* Initialize the max receive buffer length */
f4983704 1578 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1579
1da177e4 1580 /* Initialize the Minimum Frame Length Register */
f4983704 1581 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1582}
1583
511d934f
AV		 1584static int __gfar_is_rx_idle(struct gfar_private *priv)
1585{
1586 u32 res;
1587
0977f817 1588 /* Normaly TSEC should not hang on GRS commands, so we should
511d934f
AV		 1589 * actually wait for IEVENT_GRSC flag.
1590 */
1591 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1592 return 0;
1593
0977f817 1594 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
511d934f
AV		 1595 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1596 * and the Rx can be safely reset.
1597 */
1598 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1599 res &= 0x7f807f80;
1600 if ((res & 0xffff) == (res >> 16))
1601 return 1;
1602
1603 return 0;
1604}
0bbaf069
KG		 1605
1606/* Halt the receive and transmit queues */
d87eb127 1607static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1608{
1609 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1610 struct gfar __iomem *regs = NULL;
1da177e4 1611 u32 tempval;
3a2e16c8 1612 int i;
1da177e4 1613
46ceb60c
SG		 1614 for (i = 0; i < priv->num_grps; i++) {
1615 regs = priv->gfargrp[i].regs;
1616 /* Mask all interrupts */
1617 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1618
46ceb60c
SG		 1619 /* Clear all interrupts */
1620 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1621 }
1da177e4 1622
46ceb60c 1623 regs = priv->gfargrp[0].regs;
1da177e4 1624 /* Stop the DMA, and wait for it to stop */
f4983704 1625 tempval = gfar_read(&regs->dmactrl);
bc4598bc
JC		 1626 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1627 (DMACTRL_GRS | DMACTRL_GTS)) {
511d934f
AV		 1628 int ret;
1629
1da177e4 1630 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1631 gfar_write(&regs->dmactrl, tempval);
1da177e4 1632
511d934f
AV		 1633 do {
1634 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1635 (IEVENT_GRSC | IEVENT_GTSC)) ==
1636 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1637 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1638 ret = __gfar_is_rx_idle(priv);
1639 } while (!ret);
1da177e4 1640 }
d87eb127 1641}
d87eb127
SW		 1642
1643/* Halt the receive and transmit queues */
1644void gfar_halt(struct net_device *dev)
1645{
1646 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1647 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1648 u32 tempval;
1da177e4 1649
2a54adc3
SW		 1650 gfar_halt_nodisable(dev);
1651
1da177e4
LT		 1652 /* Disable Rx and Tx */
1653 tempval = gfar_read(&regs->maccfg1);
1654 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1655 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1656}
1657
46ceb60c
SG		 1658static void free_grp_irqs(struct gfar_priv_grp *grp)
1659{
ee873fda
CM		 1660 free_irq(gfar_irq(grp, TX)->irq, grp);
1661 free_irq(gfar_irq(grp, RX)->irq, grp);
1662 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 1663}
1664
0bbaf069
KG		 1665void stop_gfar(struct net_device *dev)
1666{
1667 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1668 unsigned long flags;
46ceb60c 1669 int i;
0bbaf069 1670
bb40dcbb
AF		 1671 phy_stop(priv->phydev);
1672
a12f801d 1673
0bbaf069 1674 /* Lock it down */
fba4ed03
SG		 1675 local_irq_save(flags);
1676 lock_tx_qs(priv);
1677 lock_rx_qs(priv);
0bbaf069 1678
0bbaf069 1679 gfar_halt(dev);
1da177e4 1680
fba4ed03
SG		 1681 unlock_rx_qs(priv);
1682 unlock_tx_qs(priv);
1683 local_irq_restore(flags);
1da177e4
LT		 1684
1685 /* Free the IRQs */
b31a1d8b 1686 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1687 for (i = 0; i < priv->num_grps; i++)
1688 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1689 } else {
46ceb60c 1690 for (i = 0; i < priv->num_grps; i++)
ee873fda 1691 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
bc4598bc 1692 &priv->gfargrp[i]);
1da177e4
LT		 1693 }
1694
1695 free_skb_resources(priv);
1da177e4
LT		 1696}
1697
fba4ed03 1698static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1699{
1da177e4 1700 struct txbd8 *txbdp;
fba4ed03 1701 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1702 int i, j;
1da177e4 1703
a12f801d 1704 txbdp = tx_queue->tx_bd_base;
1da177e4 1705
a12f801d
SG		 1706 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1707 if (!tx_queue->tx_skbuff[i])
4669bc90 1708 continue;
1da177e4 1709
369ec162 1710 dma_unmap_single(priv->dev, txbdp->bufPtr,
bc4598bc 1711 txbdp->length, DMA_TO_DEVICE);
4669bc90 1712 txbdp->lstatus = 0;
fba4ed03 1713 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
bc4598bc 1714 j++) {
4669bc90 1715 txbdp++;
369ec162 1716 dma_unmap_page(priv->dev, txbdp->bufPtr,
bc4598bc 1717 txbdp->length, DMA_TO_DEVICE);
1da177e4 1718 }
ad5da7ab 1719 txbdp++;
a12f801d
SG		 1720 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1721 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1722 }
a12f801d 1723 kfree(tx_queue->tx_skbuff);
1eb8f7a7 1724 tx_queue->tx_skbuff = NULL;
fba4ed03 1725}
1da177e4 1726
fba4ed03
SG		 1727static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1728{
1729 struct rxbd8 *rxbdp;
1730 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1731 int i;
1da177e4 1732
fba4ed03 1733 rxbdp = rx_queue->rx_bd_base;
1da177e4 1734
a12f801d
SG		 1735 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1736 if (rx_queue->rx_skbuff[i]) {
369ec162
CM		 1737 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1738 priv->rx_buffer_size,
bc4598bc 1739 DMA_FROM_DEVICE);
a12f801d
SG		 1740 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1741 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1742 }
e69edd21
AV		 1743 rxbdp->lstatus = 0;
1744 rxbdp->bufPtr = 0;
1745 rxbdp++;
1da177e4 1746 }
a12f801d 1747 kfree(rx_queue->rx_skbuff);
1eb8f7a7 1748 rx_queue->rx_skbuff = NULL;
fba4ed03 1749}
e69edd21 1750
fba4ed03 1751/* If there are any tx skbs or rx skbs still around, free them.
0977f817
JC		 1752 * Then free tx_skbuff and rx_skbuff
1753 */
fba4ed03
SG		 1754static void free_skb_resources(struct gfar_private *priv)
1755{
1756 struct gfar_priv_tx_q *tx_queue = NULL;
1757 struct gfar_priv_rx_q *rx_queue = NULL;
1758 int i;
1759
1760 /* Go through all the buffer descriptors and free their data buffers */
1761 for (i = 0; i < priv->num_tx_queues; i++) {
d8a0f1b0 1762 struct netdev_queue *txq;
bc4598bc 1763
fba4ed03 1764 tx_queue = priv->tx_queue[i];
d8a0f1b0 1765 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
bc4598bc 1766 if (tx_queue->tx_skbuff)
fba4ed03 1767 free_skb_tx_queue(tx_queue);
d8a0f1b0 1768 netdev_tx_reset_queue(txq);
fba4ed03
SG		 1769 }
1770
1771 for (i = 0; i < priv->num_rx_queues; i++) {
1772 rx_queue = priv->rx_queue[i];
bc4598bc 1773 if (rx_queue->rx_skbuff)
fba4ed03
SG		 1774 free_skb_rx_queue(rx_queue);
1775 }
1776
369ec162 1777 dma_free_coherent(priv->dev,
bc4598bc
JC		 1778 sizeof(struct txbd8) * priv->total_tx_ring_size +
1779 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1780 priv->tx_queue[0]->tx_bd_base,
1781 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 1782}
1783
0bbaf069
KG		 1784void gfar_start(struct net_device *dev)
1785{
1786 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1787 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1788 u32 tempval;
46ceb60c 1789 int i = 0;
0bbaf069
KG		 1790
1791 /* Enable Rx and Tx in MACCFG1 */
1792 tempval = gfar_read(&regs->maccfg1);
1793 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1794 gfar_write(&regs->maccfg1, tempval);
1795
1796 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1797 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1798 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1799 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1800
0bbaf069 1801 /* Make sure we aren't stopped */
f4983704 1802 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1803 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1804 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1805
46ceb60c
SG		 1806 for (i = 0; i < priv->num_grps; i++) {
1807 regs = priv->gfargrp[i].regs;
1808 /* Clear THLT/RHLT, so that the DMA starts polling now */
1809 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1810 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1811 /* Unmask the interrupts we look for */
1812 gfar_write(&regs->imask, IMASK_DEFAULT);
1813 }
12dea57b 1814
1ae5dc34 1815 dev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1816}
1817
800c644b 1818static void gfar_configure_coalescing(struct gfar_private *priv,
bc4598bc 1819 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1820{
46ceb60c 1821 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1822 u32 __iomem *baddr;
815b97c6 1823
46ceb60c 1824 if (priv->mode == MQ_MG_MODE) {
5d9657d8 1825 int i = 0;
c6e1160e 1826
46ceb60c 1827 baddr = &regs->txic0;
984b3f57 1828 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
9740e001
CM		 1829 gfar_write(baddr + i, 0);
1830 if (likely(priv->tx_queue[i]->txcoalescing))
46ceb60c 1831 gfar_write(baddr + i, priv->tx_queue[i]->txic);
46ceb60c
SG		 1832 }
1833
1834 baddr = &regs->rxic0;
984b3f57 1835 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
9740e001
CM		 1836 gfar_write(baddr + i, 0);
1837 if (likely(priv->rx_queue[i]->rxcoalescing))
46ceb60c 1838 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
46ceb60c 1839 }
5d9657d8 1840 } else {
c6e1160e 1841 /* Backward compatible case -- even if we enable
5d9657d8
CM		 1842 * multiple queues, there's only single reg to program
1843 */
1844 gfar_write(&regs->txic, 0);
1845 if (likely(priv->tx_queue[0]->txcoalescing))
1846 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1847
1848 gfar_write(&regs->rxic, 0);
1849 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1850 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
46ceb60c
SG		 1851 }
1852}
1853
800c644b
CM		 1854void gfar_configure_coalescing_all(struct gfar_private *priv)
1855{
1856 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1857}
1858
46ceb60c
SG		 1859static int register_grp_irqs(struct gfar_priv_grp *grp)
1860{
1861 struct gfar_private *priv = grp->priv;
1862 struct net_device *dev = priv->ndev;
1863 int err;
1da177e4 1864
1da177e4 1865 /* If the device has multiple interrupts, register for
0977f817
JC		 1866 * them. Otherwise, only register for the one
1867 */
b31a1d8b 1868 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1869 /* Install our interrupt handlers for Error,
0977f817
JC		 1870 * Transmit, and Receive
1871 */
ee873fda
CM		 1872 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1873 gfar_irq(grp, ER)->name, grp);
1874 if (err < 0) {
59deab26 1875 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1876 gfar_irq(grp, ER)->irq);
46ceb60c 1877
2145f1af 1878 goto err_irq_fail;
1da177e4 1879 }
ee873fda
CM		 1880 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1881 gfar_irq(grp, TX)->name, grp);
1882 if (err < 0) {
59deab26 1883 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1884 gfar_irq(grp, TX)->irq);
1da177e4
LT		 1885 goto tx_irq_fail;
1886 }
ee873fda
CM		 1887 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1888 gfar_irq(grp, RX)->name, grp);
1889 if (err < 0) {
59deab26 1890 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1891 gfar_irq(grp, RX)->irq);
1da177e4
LT		 1892 goto rx_irq_fail;
1893 }
1894 } else {
ee873fda
CM		 1895 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1896 gfar_irq(grp, TX)->name, grp);
1897 if (err < 0) {
59deab26 1898 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 1899 gfar_irq(grp, TX)->irq);
1da177e4
LT		 1900 goto err_irq_fail;
1901 }
1902 }
1903
46ceb60c
SG		 1904 return 0;
1905
1906rx_irq_fail:
ee873fda 1907 free_irq(gfar_irq(grp, TX)->irq, grp);
46ceb60c 1908tx_irq_fail:
ee873fda 1909 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 1910err_irq_fail:
1911 return err;
1912
1913}
1914
1915/* Bring the controller up and running */
1916int startup_gfar(struct net_device *ndev)
1917{
1918 struct gfar_private *priv = netdev_priv(ndev);
1919 struct gfar __iomem *regs = NULL;
1920 int err, i, j;
1921
1922 for (i = 0; i < priv->num_grps; i++) {
1923 regs= priv->gfargrp[i].regs;
1924 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1925 }
1926
1927 regs= priv->gfargrp[0].regs;
1928 err = gfar_alloc_skb_resources(ndev);
1929 if (err)
1930 return err;
1931
1932 gfar_init_mac(ndev);
1933
1934 for (i = 0; i < priv->num_grps; i++) {
1935 err = register_grp_irqs(&priv->gfargrp[i]);
1936 if (err) {
1937 for (j = 0; j < i; j++)
1938 free_grp_irqs(&priv->gfargrp[j]);
ff76015f 1939 goto irq_fail;
46ceb60c
SG		 1940 }
1941 }
1942
7f7f5316 1943 /* Start the controller */
ccc05c6e 1944 gfar_start(ndev);
1da177e4 1945
826aa4a0
AV		 1946 phy_start(priv->phydev);
1947
800c644b 1948 gfar_configure_coalescing_all(priv);
46ceb60c 1949
1da177e4
LT		 1950 return 0;
1951
46ceb60c 1952irq_fail:
e69edd21 1953 free_skb_resources(priv);
1da177e4
LT		 1954 return err;
1955}
1956
0977f817
JC		 1957/* Called when something needs to use the ethernet device
1958 * Returns 0 for success.
1959 */
1da177e4
LT		 1960static int gfar_enet_open(struct net_device *dev)
1961{
94e8cc35 1962 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1963 int err;
1964
46ceb60c 1965 enable_napi(priv);
bea3348e 1966
1da177e4
LT		 1967 /* Initialize a bunch of registers */
1968 init_registers(dev);
1969
1970 gfar_set_mac_address(dev);
1971
1972 err = init_phy(dev);
1973
a12f801d 1974 if (err) {
46ceb60c 1975 disable_napi(priv);
1da177e4 1976 return err;
bea3348e 1977 }
1da177e4
LT		 1978
1979 err = startup_gfar(dev);
db0e8e3f 1980 if (err) {
46ceb60c 1981 disable_napi(priv);
db0e8e3f
AV		 1982 return err;
1983 }
1da177e4 1984
fba4ed03 1985 netif_tx_start_all_queues(dev);
1da177e4 1986
2884e5cc
AV		 1987 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1988
1da177e4
LT		 1989 return err;
1990}
1991
54dc79fe 1992static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1993{
54dc79fe 1994 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1995
1996 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1997
0bbaf069
KG		 1998 return fcb;
1999}
2000
9c4886e5 2001static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
bc4598bc 2002 int fcb_length)
0bbaf069 2003{
0bbaf069
KG		 2004 /* If we're here, it's a IP packet with a TCP or UDP
2005 * payload. We set it to checksum, using a pseudo-header
2006 * we provide
2007 */
3a2e16c8 2008 u8 flags = TXFCB_DEFAULT;
0bbaf069 2009
0977f817
JC		 2010 /* Tell the controller what the protocol is
2011 * And provide the already calculated phcs
2012 */
eddc9ec5 2013 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 2014 flags |= TXFCB_UDP;
4bedb452 2015 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 2016 } else
8da32de5 2017 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 2018
2019 /* l3os is the distance between the start of the
2020 * frame (skb->data) and the start of the IP hdr.
2021 * l4os is the distance between the start of the
0977f817
JC		 2022 * l3 hdr and the l4 hdr
2023 */
9c4886e5 2024 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
cfe1fc77 2025 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2026
7f7f5316 2027 fcb->flags = flags;
0bbaf069
KG		 2028}
2029
7f7f5316 2030void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2031{
7f7f5316 2032 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 2033 fcb->vlctl = vlan_tx_tag_get(skb);
2034}
2035
4669bc90 2036static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
bc4598bc 2037 struct txbd8 *base, int ring_size)
4669bc90
DH		 2038{
2039 struct txbd8 *new_bd = bdp + stride;
2040
2041 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2042}
2043
2044static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
bc4598bc 2045 int ring_size)
4669bc90
DH		 2046{
2047 return skip_txbd(bdp, 1, base, ring_size);
2048}
2049
0977f817
JC		 2050/* This is called by the kernel when a frame is ready for transmission.
2051 * It is pointed to by the dev->hard_start_xmit function pointer
2052 */
1da177e4
LT		 2053static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2054{
2055 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2056 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2057 struct netdev_queue *txq;
f4983704 2058 struct gfar __iomem *regs = NULL;
0bbaf069 2059 struct txfcb *fcb = NULL;
f0ee7acf 2060 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2061 u32 lstatus;
f0ee7acf 2062 int i, rq = 0, do_tstamp = 0;
4669bc90 2063 u32 bufaddr;
fef6108d 2064 unsigned long flags;
9c4886e5 2065 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
fba4ed03 2066
0977f817 2067 /* TOE=1 frames larger than 2500 bytes may see excess delays
deb90eac
AV		 2068 * before start of transmission.
2069 */
2070 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
bc4598bc
JC		 2071 skb->ip_summed == CHECKSUM_PARTIAL &&
2072 skb->len > 2500)) {
deb90eac
AV		 2073 int ret;
2074
2075 ret = skb_checksum_help(skb);
2076 if (ret)
2077 return ret;
2078 }
2079
fba4ed03
SG		 2080 rq = skb->queue_mapping;
2081 tx_queue = priv->tx_queue[rq];
2082 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2083 base = tx_queue->tx_bd_base;
46ceb60c 2084 regs = tx_queue->grp->regs;
f0ee7acf
MR		 2085
2086 /* check if time stamp should be generated */
2244d07b 2087 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
bc4598bc 2088 priv->hwts_tx_en)) {
f0ee7acf 2089 do_tstamp = 1;
9c4886e5
MR		 2090 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2091 }
4669bc90 2092
5b28beaf
LY		 2093 /* make space for additional header when fcb is needed */
2094 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
bc4598bc
JC		 2095 vlan_tx_tag_present(skb) ||
2096 unlikely(do_tstamp)) &&
2097 (skb_headroom(skb) < fcb_length)) {
54dc79fe
SH		 2098 struct sk_buff *skb_new;
2099
9c4886e5 2100 skb_new = skb_realloc_headroom(skb, fcb_length);
54dc79fe
SH		 2101 if (!skb_new) {
2102 dev->stats.tx_errors++;
bd14ba84 2103 kfree_skb(skb);
54dc79fe
SH		 2104 return NETDEV_TX_OK;
2105 }
db83d136 2106
313b037c
ED		 2107 if (skb->sk)
2108 skb_set_owner_w(skb_new, skb->sk);
2109 consume_skb(skb);
54dc79fe
SH		 2110 skb = skb_new;
2111 }
2112
4669bc90
DH		 2113 /* total number of fragments in the SKB */
2114 nr_frags = skb_shinfo(skb)->nr_frags;
2115
f0ee7acf
MR		 2116 /* calculate the required number of TxBDs for this skb */
2117 if (unlikely(do_tstamp))
2118 nr_txbds = nr_frags + 2;
2119 else
2120 nr_txbds = nr_frags + 1;
2121
4669bc90 2122 /* check if there is space to queue this packet */
f0ee7acf 2123 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2124 /* no space, stop the queue */
fba4ed03 2125 netif_tx_stop_queue(txq);
4669bc90 2126 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2127 return NETDEV_TX_BUSY;
2128 }
1da177e4
LT		 2129
2130 /* Update transmit stats */
1ac9ad13
ED		 2131 tx_queue->stats.tx_bytes += skb->len;
2132 tx_queue->stats.tx_packets++;
1da177e4 2133
a12f801d 2134 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2135 lstatus = txbdp->lstatus;
2136
2137 /* Time stamp insertion requires one additional TxBD */
2138 if (unlikely(do_tstamp))
2139 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
bc4598bc 2140 tx_queue->tx_ring_size);
1da177e4 2141
4669bc90 2142 if (nr_frags == 0) {
f0ee7acf
MR		 2143 if (unlikely(do_tstamp))
2144 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
bc4598bc 2145 TXBD_INTERRUPT);
f0ee7acf
MR		 2146 else
2147 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2148 } else {
2149 /* Place the fragment addresses and lengths into the TxBDs */
2150 for (i = 0; i < nr_frags; i++) {
2151 /* Point at the next BD, wrapping as needed */
a12f801d 2152 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2153
2154 length = skb_shinfo(skb)->frags[i].size;
2155
2156 lstatus = txbdp->lstatus | length |
bc4598bc 2157 BD_LFLAG(TXBD_READY);
4669bc90
DH		 2158
2159 /* Handle the last BD specially */
2160 if (i == nr_frags - 1)
2161 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2162
369ec162 2163 bufaddr = skb_frag_dma_map(priv->dev,
2234a722
IC		 2164 &skb_shinfo(skb)->frags[i],
2165 0,
2166 length,
2167 DMA_TO_DEVICE);
4669bc90
DH		 2168
2169 /* set the TxBD length and buffer pointer */
2170 txbdp->bufPtr = bufaddr;
2171 txbdp->lstatus = lstatus;
2172 }
2173
2174 lstatus = txbdp_start->lstatus;
2175 }
1da177e4 2176
9c4886e5
MR		 2177 /* Add TxPAL between FCB and frame if required */
2178 if (unlikely(do_tstamp)) {
2179 skb_push(skb, GMAC_TXPAL_LEN);
2180 memset(skb->data, 0, GMAC_TXPAL_LEN);
2181 }
2182
0bbaf069 2183 /* Set up checksumming */
12dea57b 2184 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe 2185 fcb = gfar_add_fcb(skb);
4363c2fd 2186 /* as specified by errata */
bc4598bc
JC		 2187 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2188 ((unsigned long)fcb % 0x20) > 0x18)) {
4363c2fd
AD		 2189 __skb_pull(skb, GMAC_FCB_LEN);
2190 skb_checksum_help(skb);
2191 } else {
2192 lstatus |= BD_LFLAG(TXBD_TOE);
9c4886e5 2193 gfar_tx_checksum(skb, fcb, fcb_length);
4363c2fd 2194 }
0bbaf069
KG		 2195 }
2196
eab6d18d 2197 if (vlan_tx_tag_present(skb)) {
54dc79fe
SH		 2198 if (unlikely(NULL == fcb)) {
2199 fcb = gfar_add_fcb(skb);
5a5efed4 2200 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 2201 }
54dc79fe
SH		 2202
2203 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 2204 }
2205
f0ee7acf
MR		 2206 /* Setup tx hardware time stamping if requested */
2207 if (unlikely(do_tstamp)) {
2244d07b 2208 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf
MR		 2209 if (fcb == NULL)
2210 fcb = gfar_add_fcb(skb);
2211 fcb->ptp = 1;
2212 lstatus |= BD_LFLAG(TXBD_TOE);
2213 }
2214
369ec162 2215 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
bc4598bc 2216 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2217
0977f817 2218 /* If time stamping is requested one additional TxBD must be set up. The
f0ee7acf
MR		 2219 * first TxBD points to the FCB and must have a data length of
2220 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2221 * the full frame length.
2222 */
2223 if (unlikely(do_tstamp)) {
9c4886e5 2224 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
f0ee7acf 2225 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
bc4598bc 2226 (skb_headlen(skb) - fcb_length);
f0ee7acf
MR		 2227 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2228 } else {
2229 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2230 }
1da177e4 2231
d8a0f1b0
PG		 2232 netdev_tx_sent_queue(txq, skb->len);
2233
0977f817 2234 /* We can work in parallel with gfar_clean_tx_ring(), except
a3bc1f11
AV		 2235 * when modifying num_txbdfree. Note that we didn't grab the lock
2236 * when we were reading the num_txbdfree and checking for available
2237 * space, that's because outside of this function it can only grow,
2238 * and once we've got needed space, it cannot suddenly disappear.
2239 *
2240 * The lock also protects us from gfar_error(), which can modify
2241 * regs->tstat and thus retrigger the transfers, which is why we
2242 * also must grab the lock before setting ready bit for the first
2243 * to be transmitted BD.
2244 */
2245 spin_lock_irqsave(&tx_queue->txlock, flags);
2246
0977f817 2247 /* The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2248 * semantics (it requires synchronization between cacheable and
2249 * uncacheable mappings, which eieio doesn't provide and which we
2250 * don't need), thus requiring a more expensive sync instruction. At
2251 * some point, the set of architecture-independent barrier functions
2252 * should be expanded to include weaker barriers.
2253 */
3b6330ce 2254 eieio();
7f7f5316 2255
4669bc90
DH		 2256 txbdp_start->lstatus = lstatus;
2257
0eddba52
AV		 2258 eieio(); /* force lstatus write before tx_skbuff */
2259
2260 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2261
4669bc90 2262 /* Update the current skb pointer to the next entry we will use
0977f817
JC		 2263 * (wrapping if necessary)
2264 */
a12f801d 2265 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
bc4598bc 2266 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2267
a12f801d 2268 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2269
2270 /* reduce TxBD free count */
f0ee7acf 2271 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2272
2273 /* If the next BD still needs to be cleaned up, then the bds
0977f817
JC		 2274 * are full. We need to tell the kernel to stop sending us stuff.
2275 */
a12f801d 2276 if (!tx_queue->num_txbdfree) {
fba4ed03 2277 netif_tx_stop_queue(txq);
1da177e4 2278
09f75cd7 2279 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2280 }
2281
1da177e4 2282 /* Tell the DMA to go go go */
fba4ed03 2283 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2284
2285 /* Unlock priv */
a12f801d 2286 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2287
54dc79fe 2288 return NETDEV_TX_OK;
1da177e4
LT		 2289}
2290
2291/* Stops the kernel queue, and halts the controller */
2292static int gfar_close(struct net_device *dev)
2293{
2294 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2295
46ceb60c 2296 disable_napi(priv);
bea3348e 2297
ab939905 2298 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2299 stop_gfar(dev);
2300
bb40dcbb
AF		 2301 /* Disconnect from the PHY */
2302 phy_disconnect(priv->phydev);
2303 priv->phydev = NULL;
1da177e4 2304
fba4ed03 2305 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2306
2307 return 0;
2308}
2309
1da177e4 2310/* Changes the mac address if the controller is not running. */
f162b9d5 2311static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2312{
7f7f5316 2313 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2314
2315 return 0;
2316}
2317
f3dc1586
SP		 2318/* Check if rx parser should be activated */
2319void gfar_check_rx_parser_mode(struct gfar_private *priv)
2320{
2321 struct gfar __iomem *regs;
2322 u32 tempval;
2323
2324 regs = priv->gfargrp[0].regs;
2325
2326 tempval = gfar_read(&regs->rctrl);
2327 /* If parse is no longer required, then disable parser */
ba779711 2328 if (tempval & RCTRL_REQ_PARSER) {
f3dc1586 2329 tempval |= RCTRL_PRSDEP_INIT;
ba779711
CM		 2330 priv->uses_rxfcb = 1;
2331 } else {
f3dc1586 2332 tempval &= ~RCTRL_PRSDEP_INIT;
ba779711
CM		 2333 priv->uses_rxfcb = 0;
2334 }
f3dc1586
SP		 2335 gfar_write(&regs->rctrl, tempval);
2336}
2337
0bbaf069 2338/* Enables and disables VLAN insertion/extraction */
c8f44aff 2339void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
0bbaf069
KG		 2340{
2341 struct gfar_private *priv = netdev_priv(dev);
f4983704 2342 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2343 unsigned long flags;
2344 u32 tempval;
2345
46ceb60c 2346 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2347 local_irq_save(flags);
2348 lock_rx_qs(priv);
0bbaf069 2349
f646968f 2350 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
0bbaf069 2351 /* Enable VLAN tag insertion */
f4983704 2352 tempval = gfar_read(&regs->tctrl);
0bbaf069 2353 tempval |= TCTRL_VLINS;
f4983704 2354 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2355 } else {
2356 /* Disable VLAN tag insertion */
f4983704 2357 tempval = gfar_read(&regs->tctrl);
0bbaf069 2358 tempval &= ~TCTRL_VLINS;
f4983704 2359 gfar_write(&regs->tctrl, tempval);
87c288c6 2360 }
0bbaf069 2361
f646968f 2362 if (features & NETIF_F_HW_VLAN_CTAG_RX) {
87c288c6
JP		 2363 /* Enable VLAN tag extraction */
2364 tempval = gfar_read(&regs->rctrl);
2365 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2366 gfar_write(&regs->rctrl, tempval);
ba779711 2367 priv->uses_rxfcb = 1;
87c288c6 2368 } else {
0bbaf069 2369 /* Disable VLAN tag extraction */
f4983704 2370 tempval = gfar_read(&regs->rctrl);
0bbaf069 2371 tempval &= ~RCTRL_VLEX;
f4983704 2372 gfar_write(&regs->rctrl, tempval);
f3dc1586
SP		 2373
2374 gfar_check_rx_parser_mode(priv);
0bbaf069
KG		 2375 }
2376
77ecaf2d
DH		 2377 gfar_change_mtu(dev, dev->mtu);
2378
fba4ed03
SG		 2379 unlock_rx_qs(priv);
2380 local_irq_restore(flags);
0bbaf069
KG		 2381}
2382
1da177e4
LT		 2383static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2384{
2385 int tempsize, tempval;
2386 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2387 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2388 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2389 int frame_size = new_mtu + ETH_HLEN;
2390
1da177e4 2391 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
59deab26 2392 netif_err(priv, drv, dev, "Invalid MTU setting\n");
1da177e4
LT		 2393 return -EINVAL;
2394 }
2395
ba779711 2396 if (priv->uses_rxfcb)
77ecaf2d
DH		 2397 frame_size += GMAC_FCB_LEN;
2398
2399 frame_size += priv->padding;
2400
bc4598bc
JC		 2401 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2402 INCREMENTAL_BUFFER_SIZE;
1da177e4
LT		 2403
2404 /* Only stop and start the controller if it isn't already
0977f817
JC		 2405 * stopped, and we changed something
2406 */
1da177e4
LT		 2407 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2408 stop_gfar(dev);
2409
2410 priv->rx_buffer_size = tempsize;
2411
2412 dev->mtu = new_mtu;
2413
f4983704
SG		 2414 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2415 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2416
2417 /* If the mtu is larger than the max size for standard
2418 * ethernet frames (ie, a jumbo frame), then set maccfg2
0977f817
JC		 2419 * to allow huge frames, and to check the length
2420 */
f4983704 2421 tempval = gfar_read(&regs->maccfg2);
1da177e4 2422
7d350977 2423 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
bc4598bc 2424 gfar_has_errata(priv, GFAR_ERRATA_74))
1da177e4
LT		 2425 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2426 else
2427 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2428
f4983704 2429 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2430
2431 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2432 startup_gfar(dev);
2433
2434 return 0;
2435}
2436
ab939905 2437/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2438 * transmitted after a set amount of time.
2439 * For now, assume that clearing out all the structures, and
ab939905
SS		 2440 * starting over will fix the problem.
2441 */
2442static void gfar_reset_task(struct work_struct *work)
1da177e4 2443{
ab939905 2444 struct gfar_private *priv = container_of(work, struct gfar_private,
bc4598bc 2445 reset_task);
4826857f 2446 struct net_device *dev = priv->ndev;
1da177e4
LT		 2447
2448 if (dev->flags & IFF_UP) {
fba4ed03 2449 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2450 stop_gfar(dev);
2451 startup_gfar(dev);
fba4ed03 2452 netif_tx_start_all_queues(dev);
1da177e4
LT		 2453 }
2454
263ba320 2455 netif_tx_schedule_all(dev);
1da177e4
LT		 2456}
2457
ab939905
SS		 2458static void gfar_timeout(struct net_device *dev)
2459{
2460 struct gfar_private *priv = netdev_priv(dev);
2461
2462 dev->stats.tx_errors++;
2463 schedule_work(&priv->reset_task);
2464}
2465
acbc0f03
EL		 2466static void gfar_align_skb(struct sk_buff *skb)
2467{
2468 /* We need the data buffer to be aligned properly. We will reserve
2469 * as many bytes as needed to align the data properly
2470 */
2471 skb_reserve(skb, RXBUF_ALIGNMENT -
bc4598bc 2472 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
acbc0f03
EL		 2473}
2474
1da177e4 2475/* Interrupt Handler for Transmit complete */
c233cf40 2476static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2477{
a12f801d 2478 struct net_device *dev = tx_queue->dev;
d8a0f1b0 2479 struct netdev_queue *txq;
d080cd63 2480 struct gfar_private *priv = netdev_priv(dev);
f0ee7acf 2481 struct txbd8 *bdp, *next = NULL;
4669bc90 2482 struct txbd8 *lbdp = NULL;
a12f801d 2483 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2484 struct sk_buff *skb;
2485 int skb_dirtytx;
a12f801d 2486 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2487 int frags = 0, nr_txbds = 0;
4669bc90 2488 int i;
d080cd63 2489 int howmany = 0;
d8a0f1b0
PG		 2490 int tqi = tx_queue->qindex;
2491 unsigned int bytes_sent = 0;
4669bc90 2492 u32 lstatus;
f0ee7acf 2493 size_t buflen;
1da177e4 2494
d8a0f1b0 2495 txq = netdev_get_tx_queue(dev, tqi);
a12f801d
SG		 2496 bdp = tx_queue->dirty_tx;
2497 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2498
a12f801d 2499 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2500 unsigned long flags;
2501
4669bc90 2502 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf 2503
0977f817 2504 /* When time stamping, one additional TxBD must be freed.
f0ee7acf
MR		 2505 * Also, we need to dma_unmap_single() the TxPAL.
2506 */
2244d07b 2507 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2508 nr_txbds = frags + 2;
2509 else
2510 nr_txbds = frags + 1;
2511
2512 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2513
4669bc90 2514 lstatus = lbdp->lstatus;
1da177e4 2515
4669bc90
DH		 2516 /* Only clean completed frames */
2517 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
bc4598bc 2518 (lstatus & BD_LENGTH_MASK))
4669bc90
DH		 2519 break;
2520
2244d07b 2521 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf 2522 next = next_txbd(bdp, base, tx_ring_size);
9c4886e5 2523 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
f0ee7acf
MR		 2524 } else
2525 buflen = bdp->length;
2526
369ec162 2527 dma_unmap_single(priv->dev, bdp->bufPtr,
bc4598bc 2528 buflen, DMA_TO_DEVICE);
f0ee7acf 2529
2244d07b 2530 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2531 struct skb_shared_hwtstamps shhwtstamps;
2532 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
bc4598bc 2533
f0ee7acf
MR		 2534 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2535 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
9c4886e5 2536 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
f0ee7acf
MR		 2537 skb_tstamp_tx(skb, &shhwtstamps);
2538 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2539 bdp = next;
2540 }
81183059 2541
4669bc90
DH		 2542 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2543 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2544
4669bc90 2545 for (i = 0; i < frags; i++) {
369ec162 2546 dma_unmap_page(priv->dev, bdp->bufPtr,
bc4598bc 2547 bdp->length, DMA_TO_DEVICE);
4669bc90
DH		 2548 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2549 bdp = next_txbd(bdp, base, tx_ring_size);
2550 }
1da177e4 2551
d8a0f1b0
PG		 2552 bytes_sent += skb->len;
2553
acb600de 2554 dev_kfree_skb_any(skb);
0fd56bb5 2555
a12f801d 2556 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2557
4669bc90 2558 skb_dirtytx = (skb_dirtytx + 1) &
bc4598bc 2559 TX_RING_MOD_MASK(tx_ring_size);
4669bc90
DH		 2560
2561 howmany++;
a3bc1f11 2562 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2563 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2564 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2565 }
1da177e4 2566
4669bc90 2567 /* If we freed a buffer, we can restart transmission, if necessary */
5407b14c 2568 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
d8a0f1b0 2569 netif_wake_subqueue(dev, tqi);
1da177e4 2570
4669bc90 2571 /* Update dirty indicators */
a12f801d
SG		 2572 tx_queue->skb_dirtytx = skb_dirtytx;
2573 tx_queue->dirty_tx = bdp;
1da177e4 2574
d8a0f1b0 2575 netdev_tx_completed_queue(txq, howmany, bytes_sent);
d080cd63
DH		 2576}
2577
f4983704 2578static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2579{
a6d0b91a
AV		 2580 unsigned long flags;
2581
fba4ed03
SG		 2582 spin_lock_irqsave(&gfargrp->grplock, flags);
2583 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2584 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2585 __napi_schedule(&gfargrp->napi);
8707bdd4 2586 } else {
0977f817 2587 /* Clear IEVENT, so interrupts aren't called again
8707bdd4
JP		 2588 * because of the packets that have already arrived.
2589 */
f4983704 2590 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2591 }
fba4ed03 2592 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2593
8c7396ae 2594}
1da177e4 2595
8c7396ae 2596/* Interrupt Handler for Transmit complete */
f4983704 2597static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2598{
f4983704 2599 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2600 return IRQ_HANDLED;
2601}
2602
a12f801d 2603static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
bc4598bc 2604 struct sk_buff *skb)
815b97c6 2605{
a12f801d 2606 struct net_device *dev = rx_queue->dev;
815b97c6 2607 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2608 dma_addr_t buf;
815b97c6 2609
369ec162 2610 buf = dma_map_single(priv->dev, skb->data,
8a102fe0 2611 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2612 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2613}
2614
2281a0f3 2615static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2616{
2617 struct gfar_private *priv = netdev_priv(dev);
acb600de 2618 struct sk_buff *skb;
1da177e4 2619
acbc0f03 2620 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2621 if (!skb)
1da177e4
LT		 2622 return NULL;
2623
acbc0f03 2624 gfar_align_skb(skb);
7f7f5316 2625
acbc0f03
EL		 2626 return skb;
2627}
2628
2281a0f3 2629struct sk_buff *gfar_new_skb(struct net_device *dev)
acbc0f03 2630{
acb600de 2631 return gfar_alloc_skb(dev);
1da177e4
LT		 2632}
2633
298e1a9e 2634static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2635{
298e1a9e 2636 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2637 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2638 struct gfar_extra_stats *estats = &priv->extra_stats;
2639
0977f817 2640 /* If the packet was truncated, none of the other errors matter */
1da177e4
LT		 2641 if (status & RXBD_TRUNCATED) {
2642 stats->rx_length_errors++;
2643
212079df 2644 atomic64_inc(&estats->rx_trunc);
1da177e4
LT		 2645
2646 return;
2647 }
2648 /* Count the errors, if there were any */
2649 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2650 stats->rx_length_errors++;
2651
2652 if (status & RXBD_LARGE)
212079df 2653 atomic64_inc(&estats->rx_large);
1da177e4 2654 else
212079df 2655 atomic64_inc(&estats->rx_short);
1da177e4
LT		 2656 }
2657 if (status & RXBD_NONOCTET) {
2658 stats->rx_frame_errors++;
212079df 2659 atomic64_inc(&estats->rx_nonoctet);
1da177e4
LT		 2660 }
2661 if (status & RXBD_CRCERR) {
212079df 2662 atomic64_inc(&estats->rx_crcerr);
1da177e4
LT		 2663 stats->rx_crc_errors++;
2664 }
2665 if (status & RXBD_OVERRUN) {
212079df 2666 atomic64_inc(&estats->rx_overrun);
1da177e4
LT		 2667 stats->rx_crc_errors++;
2668 }
2669}
2670
f4983704 2671irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2672{
f4983704 2673 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2674 return IRQ_HANDLED;
2675}
2676
0bbaf069
KG		 2677static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2678{
2679 /* If valid headers were found, and valid sums
2680 * were verified, then we tell the kernel that no
0977f817
JC		 2681 * checksumming is necessary. Otherwise, it is [FIXME]
2682 */
7f7f5316 2683 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2684 skb->ip_summed = CHECKSUM_UNNECESSARY;
2685 else
bc8acf2c 2686 skb_checksum_none_assert(skb);
0bbaf069
KG		 2687}
2688
2689
0977f817 2690/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
61db26c6
CM		 2691static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2692 int amount_pull, struct napi_struct *napi)
1da177e4
LT		 2693{
2694 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2695 struct rxfcb *fcb = NULL;
1da177e4 2696
2c2db48a
DH		 2697 /* fcb is at the beginning if exists */
2698 fcb = (struct rxfcb *)skb->data;
0bbaf069 2699
0977f817
JC		 2700 /* Remove the FCB from the skb
2701 * Remove the padded bytes, if there are any
2702 */
f74dac08
SG		 2703 if (amount_pull) {
2704 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2705 skb_pull(skb, amount_pull);
f74dac08 2706 }
0bbaf069 2707
cc772ab7
MR		 2708 /* Get receive timestamp from the skb */
2709 if (priv->hwts_rx_en) {
2710 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2711 u64 *ns = (u64 *) skb->data;
bc4598bc 2712
cc772ab7
MR		 2713 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2714 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2715 }
2716
2717 if (priv->padding)
2718 skb_pull(skb, priv->padding);
2719
8b3afe95 2720 if (dev->features & NETIF_F_RXCSUM)
2c2db48a 2721 gfar_rx_checksum(skb, fcb);
0bbaf069 2722
2c2db48a
DH		 2723 /* Tell the skb what kind of packet this is */
2724 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2725
f646968f 2726 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
32f7fd44
JP		 2727 * Even if vlan rx accel is disabled, on some chips
2728 * RXFCB_VLN is pseudo randomly set.
2729 */
f646968f 2730 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
32f7fd44 2731 fcb->flags & RXFCB_VLN)
e5905c83 2732 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
87c288c6 2733
2c2db48a 2734 /* Send the packet up the stack */
953d2768 2735 napi_gro_receive(napi, skb);
0bbaf069 2736
1da177e4
LT		 2737}
2738
2739/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2281a0f3
JC		 2740 * until the budget/quota has been reached. Returns the number
2741 * of frames handled
1da177e4 2742 */
a12f801d 2743int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2744{
a12f801d 2745 struct net_device *dev = rx_queue->dev;
31de198b 2746 struct rxbd8 *bdp, *base;
1da177e4 2747 struct sk_buff *skb;
2c2db48a
DH		 2748 int pkt_len;
2749 int amount_pull;
1da177e4
LT		 2750 int howmany = 0;
2751 struct gfar_private *priv = netdev_priv(dev);
2752
2753 /* Get the first full descriptor */
a12f801d
SG		 2754 bdp = rx_queue->cur_rx;
2755 base = rx_queue->rx_bd_base;
1da177e4 2756
ba779711 2757 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2c2db48a 2758
1da177e4 2759 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2760 struct sk_buff *newskb;
bc4598bc 2761
3b6330ce 2762 rmb();
815b97c6
AF		 2763
2764 /* Add another skb for the future */
2765 newskb = gfar_new_skb(dev);
2766
a12f801d 2767 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2768
369ec162 2769 dma_unmap_single(priv->dev, bdp->bufPtr,
bc4598bc 2770 priv->rx_buffer_size, DMA_FROM_DEVICE);
81183059 2771
63b88b90 2772 if (unlikely(!(bdp->status & RXBD_ERR) &&
bc4598bc 2773 bdp->length > priv->rx_buffer_size))
63b88b90
AV		 2774 bdp->status = RXBD_LARGE;
2775
815b97c6
AF		 2776 /* We drop the frame if we failed to allocate a new buffer */
2777 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
bc4598bc 2778 bdp->status & RXBD_ERR)) {
815b97c6
AF		 2779 count_errors(bdp->status, dev);
2780
2781 if (unlikely(!newskb))
2782 newskb = skb;
acbc0f03 2783 else if (skb)
acb600de 2784 dev_kfree_skb(skb);
815b97c6 2785 } else {
1da177e4 2786 /* Increment the number of packets */
a7f38041 2787 rx_queue->stats.rx_packets++;
1da177e4
LT		 2788 howmany++;
2789
2c2db48a
DH		 2790 if (likely(skb)) {
2791 pkt_len = bdp->length - ETH_FCS_LEN;
2792 /* Remove the FCS from the packet length */
2793 skb_put(skb, pkt_len);
a7f38041 2794 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2795 skb_record_rx_queue(skb, rx_queue->qindex);
cd754a57 2796 gfar_process_frame(dev, skb, amount_pull,
bc4598bc 2797 &rx_queue->grp->napi);
2c2db48a
DH		 2798
2799 } else {
59deab26 2800 netif_warn(priv, rx_err, dev, "Missing skb!\n");
a7f38041 2801 rx_queue->stats.rx_dropped++;
212079df 2802 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2c2db48a 2803 }
1da177e4 2804
1da177e4
LT		 2805 }
2806
a12f801d 2807 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2808
815b97c6 2809 /* Setup the new bdp */
a12f801d 2810 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2811
2812 /* Update to the next pointer */
a12f801d 2813 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2814
2815 /* update to point at the next skb */
bc4598bc
JC		 2816 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2817 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2818 }
2819
2820 /* Update the current rxbd pointer to be the next one */
a12f801d 2821 rx_queue->cur_rx = bdp;
1da177e4 2822
1da177e4
LT		 2823 return howmany;
2824}
2825
bea3348e 2826static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2827{
bc4598bc
JC		 2828 struct gfar_priv_grp *gfargrp =
2829 container_of(napi, struct gfar_priv_grp, napi);
fba4ed03 2830 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2831 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2832 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2833 struct gfar_priv_rx_q *rx_queue = NULL;
c233cf40 2834 int work_done = 0, work_done_per_q = 0;
39c0a0d5 2835 int i, budget_per_q = 0;
c233cf40 2836 int has_tx_work;
6be5ed3f
CM		 2837 unsigned long rstat_rxf;
2838 int num_act_queues;
fba4ed03 2839
8c7396ae 2840 /* Clear IEVENT, so interrupts aren't called again
0977f817
JC		 2841 * because of the packets that have already arrived
2842 */
f4983704 2843 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2844
6be5ed3f
CM		 2845 rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2846
2847 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2848 if (num_act_queues)
2849 budget_per_q = budget/num_act_queues;
2850
c233cf40
CM		 2851 while (1) {
2852 has_tx_work = 0;
2853 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2854 tx_queue = priv->tx_queue[i];
2855 /* run Tx cleanup to completion */
2856 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2857 gfar_clean_tx_ring(tx_queue);
2858 has_tx_work = 1;
2859 }
2860 }
fba4ed03 2861
984b3f57 2862 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
6be5ed3f
CM		 2863 /* skip queue if not active */
2864 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
fba4ed03 2865 continue;
c233cf40 2866
fba4ed03 2867 rx_queue = priv->rx_queue[i];
c233cf40
CM		 2868 work_done_per_q =
2869 gfar_clean_rx_ring(rx_queue, budget_per_q);
2870 work_done += work_done_per_q;
2871
2872 /* finished processing this queue */
2873 if (work_done_per_q < budget_per_q) {
6be5ed3f
CM		 2874 /* clear active queue hw indication */
2875 gfar_write(&regs->rstat,
2876 RSTAT_CLEAR_RXF0 >> i);
2877 rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i);
2878 num_act_queues--;
2879
2880 if (!num_act_queues)
c233cf40
CM		 2881 break;
2882 /* recompute budget per Rx queue */
2883 budget_per_q =
6be5ed3f 2884 (budget - work_done) / num_act_queues;
fba4ed03
SG		 2885 }
2886 }
1da177e4 2887
c233cf40
CM		 2888 if (work_done >= budget)
2889 break;
42199884 2890
6be5ed3f 2891 if (!num_act_queues && !has_tx_work) {
1da177e4 2892
c233cf40 2893 napi_complete(napi);
1da177e4 2894
c233cf40
CM		 2895 /* Clear the halt bit in RSTAT */
2896 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2897
c233cf40
CM		 2898 gfar_write(&regs->imask, IMASK_DEFAULT);
2899
2900 /* If we are coalescing interrupts, update the timer
2901 * Otherwise, clear it
2902 */
2903 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2904 gfargrp->tx_bit_map);
2905 break;
2906 }
1da177e4
LT		 2907 }
2908
c233cf40 2909 return work_done;
1da177e4 2910}
1da177e4 2911
f2d71c2d 2912#ifdef CONFIG_NET_POLL_CONTROLLER
0977f817 2913/* Polling 'interrupt' - used by things like netconsole to send skbs
f2d71c2d
VW		 2914 * without having to re-enable interrupts. It's not called while
2915 * the interrupt routine is executing.
2916 */
2917static void gfar_netpoll(struct net_device *dev)
2918{
2919 struct gfar_private *priv = netdev_priv(dev);
3a2e16c8 2920 int i;
f2d71c2d
VW		 2921
2922 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2923 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c 2924 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 2925 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2926
2927 disable_irq(gfar_irq(grp, TX)->irq);
2928 disable_irq(gfar_irq(grp, RX)->irq);
2929 disable_irq(gfar_irq(grp, ER)->irq);
2930 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2931 enable_irq(gfar_irq(grp, ER)->irq);
2932 enable_irq(gfar_irq(grp, RX)->irq);
2933 enable_irq(gfar_irq(grp, TX)->irq);
46ceb60c 2934 }
f2d71c2d 2935 } else {
46ceb60c 2936 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 2937 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2938
2939 disable_irq(gfar_irq(grp, TX)->irq);
2940 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2941 enable_irq(gfar_irq(grp, TX)->irq);
43de004b 2942 }
f2d71c2d
VW		 2943 }
2944}
2945#endif
2946
1da177e4 2947/* The interrupt handler for devices with one interrupt */
f4983704 2948static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2949{
f4983704 2950 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2951
2952 /* Save ievent for future reference */
f4983704 2953 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2954
1da177e4 2955 /* Check for reception */
538cc7ee 2956 if (events & IEVENT_RX_MASK)
f4983704 2957 gfar_receive(irq, grp_id);
1da177e4
LT		 2958
2959 /* Check for transmit completion */
538cc7ee 2960 if (events & IEVENT_TX_MASK)
f4983704 2961 gfar_transmit(irq, grp_id);
1da177e4 2962
538cc7ee
SS		 2963 /* Check for errors */
2964 if (events & IEVENT_ERR_MASK)
f4983704 2965 gfar_error(irq, grp_id);
1da177e4
LT		 2966
2967 return IRQ_HANDLED;
2968}
2969
1da177e4
LT		 2970/* Called every time the controller might need to be made
2971 * aware of new link state. The PHY code conveys this
bb40dcbb 2972 * information through variables in the phydev structure, and this
1da177e4
LT		 2973 * function converts those variables into the appropriate
2974 * register values, and can bring down the device if needed.
2975 */
2976static void adjust_link(struct net_device *dev)
2977{
2978 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2979 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2980 unsigned long flags;
2981 struct phy_device *phydev = priv->phydev;
2982 int new_state = 0;
2983
fba4ed03
SG		 2984 local_irq_save(flags);
2985 lock_tx_qs(priv);
2986
bb40dcbb
AF		 2987 if (phydev->link) {
2988 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2989 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2990
1da177e4 2991 /* Now we make sure that we can be in full duplex mode.
0977f817
JC		 2992 * If not, we operate in half-duplex mode.
2993 */
bb40dcbb
AF		 2994 if (phydev->duplex != priv->oldduplex) {
2995 new_state = 1;
2996 if (!(phydev->duplex))
1da177e4 2997 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2998 else
1da177e4 2999 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 3000
bb40dcbb 3001 priv->oldduplex = phydev->duplex;
1da177e4
LT		 3002 }
3003
bb40dcbb
AF		 3004 if (phydev->speed != priv->oldspeed) {
3005 new_state = 1;
3006 switch (phydev->speed) {
1da177e4 3007 case 1000:
1da177e4
LT		 3008 tempval =
3009 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 3010
3011 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 3012 break;
3013 case 100:
3014 case 10:
1da177e4
LT		 3015 tempval =
3016 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 3017
3018 /* Reduced mode distinguishes
0977f817
JC		 3019 * between 10 and 100
3020 */
7f7f5316
AF		 3021 if (phydev->speed == SPEED_100)
3022 ecntrl |= ECNTRL_R100;
3023 else
3024 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 3025 break;
3026 default:
59deab26
JP		 3027 netif_warn(priv, link, dev,
3028 "Ack! Speed (%d) is not 10/100/1000!\n",
3029 phydev->speed);
1da177e4
LT		 3030 break;
3031 }
3032
bb40dcbb 3033 priv->oldspeed = phydev->speed;
1da177e4
LT		 3034 }
3035
bb40dcbb 3036 gfar_write(&regs->maccfg2, tempval);
7f7f5316 3037 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 3038
1da177e4 3039 if (!priv->oldlink) {
bb40dcbb 3040 new_state = 1;
1da177e4 3041 priv->oldlink = 1;
1da177e4 3042 }
bb40dcbb
AF		 3043 } else if (priv->oldlink) {
3044 new_state = 1;
3045 priv->oldlink = 0;
3046 priv->oldspeed = 0;
3047 priv->oldduplex = -1;
1da177e4 3048 }
1da177e4 3049
bb40dcbb
AF		 3050 if (new_state && netif_msg_link(priv))
3051 phy_print_status(phydev);
fba4ed03
SG		 3052 unlock_tx_qs(priv);
3053 local_irq_restore(flags);
bb40dcbb 3054}
1da177e4
LT		 3055
3056/* Update the hash table based on the current list of multicast
3057 * addresses we subscribe to. Also, change the promiscuity of
3058 * the device based on the flags (this function is called
0977f817
JC		 3059 * whenever dev->flags is changed
3060 */
1da177e4
LT		 3061static void gfar_set_multi(struct net_device *dev)
3062{
22bedad3 3063 struct netdev_hw_addr *ha;
1da177e4 3064 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3065 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3066 u32 tempval;
3067
a12f801d 3068 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3069 /* Set RCTRL to PROM */
3070 tempval = gfar_read(&regs->rctrl);
3071 tempval |= RCTRL_PROM;
3072 gfar_write(&regs->rctrl, tempval);
3073 } else {
3074 /* Set RCTRL to not PROM */
3075 tempval = gfar_read(&regs->rctrl);
3076 tempval &= ~(RCTRL_PROM);
3077 gfar_write(&regs->rctrl, tempval);
3078 }
6aa20a22 3079
a12f801d 3080 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3081 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3082 gfar_write(&regs->igaddr0, 0xffffffff);
3083 gfar_write(&regs->igaddr1, 0xffffffff);
3084 gfar_write(&regs->igaddr2, 0xffffffff);
3085 gfar_write(&regs->igaddr3, 0xffffffff);
3086 gfar_write(&regs->igaddr4, 0xffffffff);
3087 gfar_write(&regs->igaddr5, 0xffffffff);
3088 gfar_write(&regs->igaddr6, 0xffffffff);
3089 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3090 gfar_write(&regs->gaddr0, 0xffffffff);
3091 gfar_write(&regs->gaddr1, 0xffffffff);
3092 gfar_write(&regs->gaddr2, 0xffffffff);
3093 gfar_write(&regs->gaddr3, 0xffffffff);
3094 gfar_write(&regs->gaddr4, 0xffffffff);
3095 gfar_write(&regs->gaddr5, 0xffffffff);
3096 gfar_write(&regs->gaddr6, 0xffffffff);
3097 gfar_write(&regs->gaddr7, 0xffffffff);
3098 } else {
7f7f5316
AF		 3099 int em_num;
3100 int idx;
3101
1da177e4 3102 /* zero out the hash */
0bbaf069
KG		 3103 gfar_write(&regs->igaddr0, 0x0);
3104 gfar_write(&regs->igaddr1, 0x0);
3105 gfar_write(&regs->igaddr2, 0x0);
3106 gfar_write(&regs->igaddr3, 0x0);
3107 gfar_write(&regs->igaddr4, 0x0);
3108 gfar_write(&regs->igaddr5, 0x0);
3109 gfar_write(&regs->igaddr6, 0x0);
3110 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3111 gfar_write(&regs->gaddr0, 0x0);
3112 gfar_write(&regs->gaddr1, 0x0);
3113 gfar_write(&regs->gaddr2, 0x0);
3114 gfar_write(&regs->gaddr3, 0x0);
3115 gfar_write(&regs->gaddr4, 0x0);
3116 gfar_write(&regs->gaddr5, 0x0);
3117 gfar_write(&regs->gaddr6, 0x0);
3118 gfar_write(&regs->gaddr7, 0x0);
3119
7f7f5316
AF		 3120 /* If we have extended hash tables, we need to
3121 * clear the exact match registers to prepare for
0977f817
JC		 3122 * setting them
3123 */
7f7f5316
AF		 3124 if (priv->extended_hash) {
3125 em_num = GFAR_EM_NUM + 1;
3126 gfar_clear_exact_match(dev);
3127 idx = 1;
3128 } else {
3129 idx = 0;
3130 em_num = 0;
3131 }
3132
4cd24eaf 3133 if (netdev_mc_empty(dev))
1da177e4
LT		 3134 return;
3135
3136 /* Parse the list, and set the appropriate bits */
22bedad3 3137 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3138 if (idx < em_num) {
22bedad3 3139 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3140 idx++;
3141 } else
22bedad3 3142 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3143 }
3144 }
1da177e4
LT		 3145}
3146
7f7f5316
AF		 3147
3148/* Clears each of the exact match registers to zero, so they
0977f817
JC		 3149 * don't interfere with normal reception
3150 */
7f7f5316
AF		 3151static void gfar_clear_exact_match(struct net_device *dev)
3152{
3153 int idx;
6a3c910c 3154 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
7f7f5316 3155
bc4598bc 3156 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
b6bc7650 3157 gfar_set_mac_for_addr(dev, idx, zero_arr);
7f7f5316
AF		 3158}
3159
1da177e4
LT		 3160/* Set the appropriate hash bit for the given addr */
3161/* The algorithm works like so:
3162 * 1) Take the Destination Address (ie the multicast address), and
3163 * do a CRC on it (little endian), and reverse the bits of the
3164 * result.
3165 * 2) Use the 8 most significant bits as a hash into a 256-entry
3166 * table. The table is controlled through 8 32-bit registers:
3167 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3168 * gaddr7. This means that the 3 most significant bits in the
3169 * hash index which gaddr register to use, and the 5 other bits
3170 * indicate which bit (assuming an IBM numbering scheme, which
3171 * for PowerPC (tm) is usually the case) in the register holds
0977f817
JC		 3172 * the entry.
3173 */
1da177e4
LT		 3174static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3175{
3176 u32 tempval;
3177 struct gfar_private *priv = netdev_priv(dev);
6a3c910c 3178 u32 result = ether_crc(ETH_ALEN, addr);
0bbaf069
KG		 3179 int width = priv->hash_width;
3180 u8 whichbit = (result >> (32 - width)) & 0x1f;
3181 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3182 u32 value = (1 << (31-whichbit));
3183
0bbaf069 3184 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3185 tempval |= value;
0bbaf069 3186 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3187}
3188
7f7f5316
AF		 3189
3190/* There are multiple MAC Address register pairs on some controllers
3191 * This function sets the numth pair to a given address
3192 */
b6bc7650
JP		 3193static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3194 const u8 *addr)
7f7f5316
AF		 3195{
3196 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3197 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316 3198 int idx;
6a3c910c 3199 char tmpbuf[ETH_ALEN];
7f7f5316 3200 u32 tempval;
f4983704 3201 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3202
3203 macptr += num*2;
3204
0977f817
JC		 3205 /* Now copy it into the mac registers backwards, cuz
3206 * little endian is silly
3207 */
6a3c910c
JP		 3208 for (idx = 0; idx < ETH_ALEN; idx++)
3209 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
7f7f5316
AF		 3210
3211 gfar_write(macptr, *((u32 *) (tmpbuf)));
3212
3213 tempval = *((u32 *) (tmpbuf + 4));
3214
3215 gfar_write(macptr+1, tempval);
3216}
3217
1da177e4 3218/* GFAR error interrupt handler */
f4983704 3219static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3220{
f4983704
SG		 3221 struct gfar_priv_grp *gfargrp = grp_id;
3222 struct gfar __iomem *regs = gfargrp->regs;
3223 struct gfar_private *priv= gfargrp->priv;
3224 struct net_device *dev = priv->ndev;
1da177e4
LT		 3225
3226 /* Save ievent for future reference */
f4983704 3227 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3228
3229 /* Clear IEVENT */
f4983704 3230 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3231
3232 /* Magic Packet is not an error. */
b31a1d8b 3233 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3234 (events & IEVENT_MAG))
3235 events &= ~IEVENT_MAG;
1da177e4
LT		 3236
3237 /* Hmm... */
0bbaf069 3238 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
bc4598bc
JC		 3239 netdev_dbg(dev,
3240 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
59deab26 3241 events, gfar_read(&regs->imask));
1da177e4
LT		 3242
3243 /* Update the error counters */
3244 if (events & IEVENT_TXE) {
09f75cd7 3245 dev->stats.tx_errors++;
1da177e4
LT		 3246
3247 if (events & IEVENT_LC)
09f75cd7 3248 dev->stats.tx_window_errors++;
1da177e4 3249 if (events & IEVENT_CRL)
09f75cd7 3250 dev->stats.tx_aborted_errors++;
1da177e4 3251 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3252 unsigned long flags;
3253
59deab26
JP		 3254 netif_dbg(priv, tx_err, dev,
3255 "TX FIFO underrun, packet dropped\n");
09f75cd7 3256 dev->stats.tx_dropped++;
212079df 3257 atomic64_inc(&priv->extra_stats.tx_underrun);
1da177e4 3258
836cf7fa
AV		 3259 local_irq_save(flags);
3260 lock_tx_qs(priv);
3261
1da177e4 3262 /* Reactivate the Tx Queues */
fba4ed03 3263 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3264
3265 unlock_tx_qs(priv);
3266 local_irq_restore(flags);
1da177e4 3267 }
59deab26 3268 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
1da177e4
LT		 3269 }
3270 if (events & IEVENT_BSY) {
09f75cd7 3271 dev->stats.rx_errors++;
212079df 3272 atomic64_inc(&priv->extra_stats.rx_bsy);
1da177e4 3273
f4983704 3274 gfar_receive(irq, grp_id);
1da177e4 3275
59deab26
JP		 3276 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3277 gfar_read(&regs->rstat));
1da177e4
LT		 3278 }
3279 if (events & IEVENT_BABR) {
09f75cd7 3280 dev->stats.rx_errors++;
212079df 3281 atomic64_inc(&priv->extra_stats.rx_babr);
1da177e4 3282
59deab26 3283 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
1da177e4
LT		 3284 }
3285 if (events & IEVENT_EBERR) {
212079df 3286 atomic64_inc(&priv->extra_stats.eberr);
59deab26 3287 netif_dbg(priv, rx_err, dev, "bus error\n");
1da177e4 3288 }
59deab26
JP		 3289 if (events & IEVENT_RXC)
3290 netif_dbg(priv, rx_status, dev, "control frame\n");
1da177e4
LT		 3291
3292 if (events & IEVENT_BABT) {
212079df 3293 atomic64_inc(&priv->extra_stats.tx_babt);
59deab26 3294 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
1da177e4
LT		 3295 }
3296 return IRQ_HANDLED;
3297}
3298
b31a1d8b
AF		 3299static struct of_device_id gfar_match[] =
3300{
3301 {
3302 .type = "network",
3303 .compatible = "gianfar",
3304 },
46ceb60c
SG		 3305 {
3306 .compatible = "fsl,etsec2",
3307 },
b31a1d8b
AF		 3308 {},
3309};
e72701ac 3310MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3311
1da177e4 3312/* Structure for a device driver */
74888760 3313static struct platform_driver gfar_driver = {
4018294b
GL		 3314 .driver = {
3315 .name = "fsl-gianfar",
3316 .owner = THIS_MODULE,
3317 .pm = GFAR_PM_OPS,
3318 .of_match_table = gfar_match,
3319 },
1da177e4
LT		 3320 .probe = gfar_probe,
3321 .remove = gfar_remove,
3322};
3323
db62f684 3324module_platform_driver(gfar_driver);
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