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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / freescale / gianfar.c
CommitLineData
0977f817 1/* drivers/net/ethernet/freescale/gianfar.c
1da177e4
LT		 2 *
3 * Gianfar Ethernet Driver
7f7f5316
AF		 4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
4c8d3d99 9 * Maintainer: Kumar Gala
a12f801d 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 11 *
20862788 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
a12f801d 13 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
0bbaf069 27 *
b31a1d8b
AF		 28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
0bbaf069 38 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
bb40dcbb 42 * of frames or amount of time have passed). In NAPI, the
1da177e4 43 * interrupt handler will signal there is work to be done, and
0aa1538f 44 * exit. This method will start at the last known empty
0bbaf069 45 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
59deab26
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65#define DEBUG
66
1da177e4 67#include <linux/kernel.h>
1da177e4
LT		 68#include <linux/string.h>
69#include <linux/errno.h>
bb40dcbb 70#include <linux/unistd.h>
1da177e4
LT		 71#include <linux/slab.h>
72#include <linux/interrupt.h>
1da177e4
LT		 73#include <linux/delay.h>
74#include <linux/netdevice.h>
75#include <linux/etherdevice.h>
76#include <linux/skbuff.h>
0bbaf069 77#include <linux/if_vlan.h>
1da177e4
LT		 78#include <linux/spinlock.h>
79#include <linux/mm.h>
5af50730
RH		 80#include <linux/of_address.h>
81#include <linux/of_irq.h>
fe192a49 82#include <linux/of_mdio.h>
b31a1d8b 83#include <linux/of_platform.h>
0bbaf069
KG		 84#include <linux/ip.h>
85#include <linux/tcp.h>
86#include <linux/udp.h>
9c07b884 87#include <linux/in.h>
cc772ab7 88#include <linux/net_tstamp.h>
1da177e4
LT		 89
90#include <asm/io.h>
d6ef0bcc 91#ifdef CONFIG_PPC
7d350977 92#include <asm/reg.h>
2969b1f7 93#include <asm/mpc85xx.h>
d6ef0bcc 94#endif
1da177e4
LT		 95#include <asm/irq.h>
96#include <asm/uaccess.h>
97#include <linux/module.h>
1da177e4
LT		 98#include <linux/dma-mapping.h>
99#include <linux/crc32.h>
bb40dcbb
AF		 100#include <linux/mii.h>
101#include <linux/phy.h>
b31a1d8b
AF		 102#include <linux/phy_fixed.h>
103#include <linux/of.h>
4b6ba8aa 104#include <linux/of_net.h>
fd31a952
CM		 105#include <linux/of_address.h>
106#include <linux/of_irq.h>
1da177e4
LT		 107
108#include "gianfar.h"
1da177e4
LT		 109
110#define TX_TIMEOUT (1*HZ)
1da177e4 111
7f7f5316 112const char gfar_driver_version[] = "1.3";
1da177e4 113
1da177e4
LT		 114static int gfar_enet_open(struct net_device *dev);
115static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 116static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 117static void gfar_timeout(struct net_device *dev);
118static int gfar_close(struct net_device *dev);
91c53f76
KH		 119static struct sk_buff *gfar_new_skb(struct net_device *dev,
120 dma_addr_t *bufaddr);
1da177e4
LT		 121static int gfar_set_mac_address(struct net_device *dev);
122static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 123static irqreturn_t gfar_error(int irq, void *dev_id);
124static irqreturn_t gfar_transmit(int irq, void *dev_id);
125static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4 126static void adjust_link(struct net_device *dev);
6ce29b0e 127static noinline void gfar_update_link_state(struct gfar_private *priv);
1da177e4 128static int init_phy(struct net_device *dev);
74888760 129static int gfar_probe(struct platform_device *ofdev);
2dc11581 130static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 131static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 132static void gfar_set_multi(struct net_device *dev);
133static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 134static void gfar_configure_serdes(struct net_device *dev);
aeb12c5e
CM		 135static int gfar_poll_rx(struct napi_struct *napi, int budget);
136static int gfar_poll_tx(struct napi_struct *napi, int budget);
137static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
f2d71c2d
VW		 139#ifdef CONFIG_NET_POLL_CONTROLLER
140static void gfar_netpoll(struct net_device *dev);
141#endif
a12f801d 142int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
c233cf40 143static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
61db26c6
CM		 144static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
145 int amount_pull, struct napi_struct *napi);
c10650b6 146static void gfar_halt_nodisable(struct gfar_private *priv);
7f7f5316 147static void gfar_clear_exact_match(struct net_device *dev);
b6bc7650
JP		 148static void gfar_set_mac_for_addr(struct net_device *dev, int num,
149 const u8 *addr);
26ccfc37 150static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 151
1da177e4
LT		 152MODULE_AUTHOR("Freescale Semiconductor, Inc");
153MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154MODULE_LICENSE("GPL");
155
a12f801d 156static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 157 dma_addr_t buf)
158{
8a102fe0
AV		 159 u32 lstatus;
160
161 bdp->bufPtr = buf;
162
163 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 164 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 165 lstatus |= BD_LFLAG(RXBD_WRAP);
166
d55398ba 167 gfar_wmb();
8a102fe0
AV		 168
169 bdp->lstatus = lstatus;
170}
171
8728327e 172static int gfar_init_bds(struct net_device *ndev)
826aa4a0 173{
8728327e 174 struct gfar_private *priv = netdev_priv(ndev);
45b679c9 175 struct gfar __iomem *regs = priv->gfargrp[0].regs;
a12f801d
SG		 176 struct gfar_priv_tx_q *tx_queue = NULL;
177 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 178 struct txbd8 *txbdp;
179 struct rxbd8 *rxbdp;
03366a33 180 u32 __iomem *rfbptr;
fba4ed03 181 int i, j;
0a4b5a24 182 dma_addr_t bufaddr;
a12f801d 183
fba4ed03
SG		 184 for (i = 0; i < priv->num_tx_queues; i++) {
185 tx_queue = priv->tx_queue[i];
186 /* Initialize some variables in our dev structure */
187 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
188 tx_queue->dirty_tx = tx_queue->tx_bd_base;
189 tx_queue->cur_tx = tx_queue->tx_bd_base;
190 tx_queue->skb_curtx = 0;
191 tx_queue->skb_dirtytx = 0;
192
193 /* Initialize Transmit Descriptor Ring */
194 txbdp = tx_queue->tx_bd_base;
195 for (j = 0; j < tx_queue->tx_ring_size; j++) {
196 txbdp->lstatus = 0;
197 txbdp->bufPtr = 0;
198 txbdp++;
199 }
8728327e 200
fba4ed03
SG		 201 /* Set the last descriptor in the ring to indicate wrap */
202 txbdp--;
203 txbdp->status |= TXBD_WRAP;
8728327e
AV		 204 }
205
45b679c9 206 rfbptr = &regs->rfbptr0;
fba4ed03
SG		 207 for (i = 0; i < priv->num_rx_queues; i++) {
208 rx_queue = priv->rx_queue[i];
209 rx_queue->cur_rx = rx_queue->rx_bd_base;
210 rx_queue->skb_currx = 0;
211 rxbdp = rx_queue->rx_bd_base;
8728327e 212
fba4ed03
SG		 213 for (j = 0; j < rx_queue->rx_ring_size; j++) {
214 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 215
fba4ed03 216 if (skb) {
0a4b5a24 217 bufaddr = rxbdp->bufPtr;
fba4ed03 218 } else {
0a4b5a24 219 skb = gfar_new_skb(ndev, &bufaddr);
fba4ed03 220 if (!skb) {
59deab26 221 netdev_err(ndev, "Can't allocate RX buffers\n");
1eb8f7a7 222 return -ENOMEM;
fba4ed03
SG		 223 }
224 rx_queue->rx_skbuff[j] = skb;
8728327e 225 }
8728327e 226
0a4b5a24 227 gfar_init_rxbdp(rx_queue, rxbdp, bufaddr);
fba4ed03 228 rxbdp++;
8728327e
AV		 229 }
230
45b679c9
MP		 231 rx_queue->rfbptr = rfbptr;
232 rfbptr += 2;
8728327e
AV		 233 }
234
235 return 0;
236}
237
238static int gfar_alloc_skb_resources(struct net_device *ndev)
239{
826aa4a0 240 void *vaddr;
fba4ed03
SG		 241 dma_addr_t addr;
242 int i, j, k;
826aa4a0 243 struct gfar_private *priv = netdev_priv(ndev);
369ec162 244 struct device *dev = priv->dev;
a12f801d
SG		 245 struct gfar_priv_tx_q *tx_queue = NULL;
246 struct gfar_priv_rx_q *rx_queue = NULL;
247
fba4ed03
SG		 248 priv->total_tx_ring_size = 0;
249 for (i = 0; i < priv->num_tx_queues; i++)
250 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
251
252 priv->total_rx_ring_size = 0;
253 for (i = 0; i < priv->num_rx_queues; i++)
254 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 255
256 /* Allocate memory for the buffer descriptors */
8728327e 257 vaddr = dma_alloc_coherent(dev,
d0320f75
JP		 258 (priv->total_tx_ring_size *
259 sizeof(struct txbd8)) +
260 (priv->total_rx_ring_size *
261 sizeof(struct rxbd8)),
262 &addr, GFP_KERNEL);
263 if (!vaddr)
826aa4a0 264 return -ENOMEM;
826aa4a0 265
fba4ed03
SG		 266 for (i = 0; i < priv->num_tx_queues; i++) {
267 tx_queue = priv->tx_queue[i];
43d620c8 268 tx_queue->tx_bd_base = vaddr;
fba4ed03
SG		 269 tx_queue->tx_bd_dma_base = addr;
270 tx_queue->dev = ndev;
271 /* enet DMA only understands physical addresses */
bc4598bc
JC		 272 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
273 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
fba4ed03 274 }
826aa4a0 275
826aa4a0 276 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 277 for (i = 0; i < priv->num_rx_queues; i++) {
278 rx_queue = priv->rx_queue[i];
43d620c8 279 rx_queue->rx_bd_base = vaddr;
fba4ed03
SG		 280 rx_queue->rx_bd_dma_base = addr;
281 rx_queue->dev = ndev;
bc4598bc
JC		 282 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
283 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
fba4ed03 284 }
826aa4a0
AV		 285
286 /* Setup the skbuff rings */
fba4ed03
SG		 287 for (i = 0; i < priv->num_tx_queues; i++) {
288 tx_queue = priv->tx_queue[i];
14f8dc49
JP		 289 tx_queue->tx_skbuff =
290 kmalloc_array(tx_queue->tx_ring_size,
291 sizeof(*tx_queue->tx_skbuff),
292 GFP_KERNEL);
293 if (!tx_queue->tx_skbuff)
fba4ed03 294 goto cleanup;
826aa4a0 295
fba4ed03
SG		 296 for (k = 0; k < tx_queue->tx_ring_size; k++)
297 tx_queue->tx_skbuff[k] = NULL;
298 }
826aa4a0 299
fba4ed03
SG		 300 for (i = 0; i < priv->num_rx_queues; i++) {
301 rx_queue = priv->rx_queue[i];
14f8dc49
JP		 302 rx_queue->rx_skbuff =
303 kmalloc_array(rx_queue->rx_ring_size,
304 sizeof(*rx_queue->rx_skbuff),
305 GFP_KERNEL);
306 if (!rx_queue->rx_skbuff)
fba4ed03 307 goto cleanup;
fba4ed03
SG		 308
309 for (j = 0; j < rx_queue->rx_ring_size; j++)
310 rx_queue->rx_skbuff[j] = NULL;
311 }
826aa4a0 312
8728327e
AV		 313 if (gfar_init_bds(ndev))
314 goto cleanup;
826aa4a0
AV		 315
316 return 0;
317
318cleanup:
319 free_skb_resources(priv);
320 return -ENOMEM;
321}
322
fba4ed03
SG		 323static void gfar_init_tx_rx_base(struct gfar_private *priv)
324{
46ceb60c 325 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 326 u32 __iomem *baddr;
fba4ed03
SG		 327 int i;
328
329 baddr = &regs->tbase0;
bc4598bc 330 for (i = 0; i < priv->num_tx_queues; i++) {
fba4ed03 331 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
bc4598bc 332 baddr += 2;
fba4ed03
SG		 333 }
334
335 baddr = &regs->rbase0;
bc4598bc 336 for (i = 0; i < priv->num_rx_queues; i++) {
fba4ed03 337 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
bc4598bc 338 baddr += 2;
fba4ed03
SG		 339 }
340}
341
45b679c9
MP		 342static void gfar_init_rqprm(struct gfar_private *priv)
343{
344 struct gfar __iomem *regs = priv->gfargrp[0].regs;
345 u32 __iomem *baddr;
346 int i;
347
348 baddr = &regs->rqprm0;
349 for (i = 0; i < priv->num_rx_queues; i++) {
350 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
351 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
352 baddr++;
353 }
354}
355
88302648 356static void gfar_rx_buff_size_config(struct gfar_private *priv)
826aa4a0 357{
f5b720b8 358 int frame_size = priv->ndev->mtu + ETH_HLEN + ETH_FCS_LEN;
fba4ed03 359
ba779711
CM		 360 /* set this when rx hw offload (TOE) functions are being used */
361 priv->uses_rxfcb = 0;
362
88302648
CM		 363 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
364 priv->uses_rxfcb = 1;
365
366 if (priv->hwts_rx_en)
367 priv->uses_rxfcb = 1;
368
369 if (priv->uses_rxfcb)
370 frame_size += GMAC_FCB_LEN;
371
372 frame_size += priv->padding;
373
374 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
375 INCREMENTAL_BUFFER_SIZE;
376
377 priv->rx_buffer_size = frame_size;
378}
379
380static void gfar_mac_rx_config(struct gfar_private *priv)
381{
382 struct gfar __iomem *regs = priv->gfargrp[0].regs;
383 u32 rctrl = 0;
384
1ccb8389 385 if (priv->rx_filer_enable) {
fba4ed03 386 rctrl |= RCTRL_FILREN;
1ccb8389 387 /* Program the RIR0 reg with the required distribution */
71ff9e3d
CM		 388 if (priv->poll_mode == GFAR_SQ_POLLING)
389 gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
390 else /* GFAR_MQ_POLLING */
391 gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
1ccb8389 392 }
826aa4a0 393
f5ae6279 394 /* Restore PROMISC mode */
a328ac92 395 if (priv->ndev->flags & IFF_PROMISC)
f5ae6279
CM		 396 rctrl |= RCTRL_PROM;
397
88302648 398 if (priv->ndev->features & NETIF_F_RXCSUM)
826aa4a0
AV		 399 rctrl |= RCTRL_CHECKSUMMING;
400
88302648
CM		 401 if (priv->extended_hash)
402 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
826aa4a0
AV		 403
404 if (priv->padding) {
405 rctrl &= ~RCTRL_PAL_MASK;
406 rctrl |= RCTRL_PADDING(priv->padding);
407 }
408
97553f7f 409 /* Enable HW time stamping if requested from user space */
88302648 410 if (priv->hwts_rx_en)
97553f7f
MR		 411 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
412
88302648 413 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
b852b720 414 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
826aa4a0 415
45b679c9
MP		 416 /* Clear the LFC bit */
417 gfar_write(&regs->rctrl, rctrl);
418 /* Init flow control threshold values */
419 gfar_init_rqprm(priv);
420 gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
421 rctrl |= RCTRL_LFC;
422
826aa4a0
AV		 423 /* Init rctrl based on our settings */
424 gfar_write(&regs->rctrl, rctrl);
a328ac92 425}
826aa4a0 426
a328ac92
CM		 427static void gfar_mac_tx_config(struct gfar_private *priv)
428{
429 struct gfar __iomem *regs = priv->gfargrp[0].regs;
430 u32 tctrl = 0;
431
432 if (priv->ndev->features & NETIF_F_IP_CSUM)
826aa4a0
AV		 433 tctrl |= TCTRL_INIT_CSUM;
434
b98b8bab
CM		 435 if (priv->prio_sched_en)
436 tctrl |= TCTRL_TXSCHED_PRIO;
437 else {
438 tctrl |= TCTRL_TXSCHED_WRRS;
439 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
440 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
441 }
fba4ed03 442
88302648
CM		 443 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
444 tctrl |= TCTRL_VLINS;
445
826aa4a0 446 gfar_write(&regs->tctrl, tctrl);
826aa4a0
AV		 447}
448
f19015ba
CM		 449static void gfar_configure_coalescing(struct gfar_private *priv,
450 unsigned long tx_mask, unsigned long rx_mask)
451{
452 struct gfar __iomem *regs = priv->gfargrp[0].regs;
453 u32 __iomem *baddr;
454
455 if (priv->mode == MQ_MG_MODE) {
456 int i = 0;
457
458 baddr = &regs->txic0;
459 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
460 gfar_write(baddr + i, 0);
461 if (likely(priv->tx_queue[i]->txcoalescing))
462 gfar_write(baddr + i, priv->tx_queue[i]->txic);
463 }
464
465 baddr = &regs->rxic0;
466 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
467 gfar_write(baddr + i, 0);
468 if (likely(priv->rx_queue[i]->rxcoalescing))
469 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
470 }
471 } else {
472 /* Backward compatible case -- even if we enable
473 * multiple queues, there's only single reg to program
474 */
475 gfar_write(&regs->txic, 0);
476 if (likely(priv->tx_queue[0]->txcoalescing))
477 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
478
479 gfar_write(&regs->rxic, 0);
480 if (unlikely(priv->rx_queue[0]->rxcoalescing))
481 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
482 }
483}
484
485void gfar_configure_coalescing_all(struct gfar_private *priv)
486{
487 gfar_configure_coalescing(priv, 0xFF, 0xFF);
488}
489
a7f38041
SG		 490static struct net_device_stats *gfar_get_stats(struct net_device *dev)
491{
492 struct gfar_private *priv = netdev_priv(dev);
a7f38041
SG		 493 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
494 unsigned long tx_packets = 0, tx_bytes = 0;
3a2e16c8 495 int i;
a7f38041
SG		 496
497 for (i = 0; i < priv->num_rx_queues; i++) {
498 rx_packets += priv->rx_queue[i]->stats.rx_packets;
bc4598bc 499 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
a7f38041
SG		 500 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
501 }
502
503 dev->stats.rx_packets = rx_packets;
bc4598bc 504 dev->stats.rx_bytes = rx_bytes;
a7f38041
SG		 505 dev->stats.rx_dropped = rx_dropped;
506
507 for (i = 0; i < priv->num_tx_queues; i++) {
1ac9ad13
ED		 508 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
509 tx_packets += priv->tx_queue[i]->stats.tx_packets;
a7f38041
SG		 510 }
511
bc4598bc 512 dev->stats.tx_bytes = tx_bytes;
a7f38041
SG		 513 dev->stats.tx_packets = tx_packets;
514
515 return &dev->stats;
516}
517
26ccfc37
AF		 518static const struct net_device_ops gfar_netdev_ops = {
519 .ndo_open = gfar_enet_open,
520 .ndo_start_xmit = gfar_start_xmit,
521 .ndo_stop = gfar_close,
522 .ndo_change_mtu = gfar_change_mtu,
8b3afe95 523 .ndo_set_features = gfar_set_features,
afc4b13d 524 .ndo_set_rx_mode = gfar_set_multi,
26ccfc37
AF		 525 .ndo_tx_timeout = gfar_timeout,
526 .ndo_do_ioctl = gfar_ioctl,
a7f38041 527 .ndo_get_stats = gfar_get_stats,
240c102d
BH		 528 .ndo_set_mac_address = eth_mac_addr,
529 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 530#ifdef CONFIG_NET_POLL_CONTROLLER
531 .ndo_poll_controller = gfar_netpoll,
532#endif
533};
534
efeddce7
CM		 535static void gfar_ints_disable(struct gfar_private *priv)
536{
537 int i;
538 for (i = 0; i < priv->num_grps; i++) {
539 struct gfar __iomem *regs = priv->gfargrp[i].regs;
540 /* Clear IEVENT */
541 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
542
543 /* Initialize IMASK */
544 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
545 }
546}
547
548static void gfar_ints_enable(struct gfar_private *priv)
549{
550 int i;
551 for (i = 0; i < priv->num_grps; i++) {
552 struct gfar __iomem *regs = priv->gfargrp[i].regs;
553 /* Unmask the interrupts we look for */
554 gfar_write(&regs->imask, IMASK_DEFAULT);
555 }
556}
557
91c53f76 558static void lock_tx_qs(struct gfar_private *priv)
fba4ed03 559{
3a2e16c8 560 int i;
fba4ed03
SG		 561
562 for (i = 0; i < priv->num_tx_queues; i++)
563 spin_lock(&priv->tx_queue[i]->txlock);
564}
565
91c53f76 566static void unlock_tx_qs(struct gfar_private *priv)
fba4ed03 567{
3a2e16c8 568 int i;
fba4ed03
SG		 569
570 for (i = 0; i < priv->num_tx_queues; i++)
571 spin_unlock(&priv->tx_queue[i]->txlock);
572}
573
20862788
CM		 574static int gfar_alloc_tx_queues(struct gfar_private *priv)
575{
576 int i;
577
578 for (i = 0; i < priv->num_tx_queues; i++) {
579 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
580 GFP_KERNEL);
581 if (!priv->tx_queue[i])
582 return -ENOMEM;
583
584 priv->tx_queue[i]->tx_skbuff = NULL;
585 priv->tx_queue[i]->qindex = i;
586 priv->tx_queue[i]->dev = priv->ndev;
587 spin_lock_init(&(priv->tx_queue[i]->txlock));
588 }
589 return 0;
590}
591
592static int gfar_alloc_rx_queues(struct gfar_private *priv)
593{
594 int i;
595
596 for (i = 0; i < priv->num_rx_queues; i++) {
597 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
598 GFP_KERNEL);
599 if (!priv->rx_queue[i])
600 return -ENOMEM;
601
602 priv->rx_queue[i]->rx_skbuff = NULL;
603 priv->rx_queue[i]->qindex = i;
604 priv->rx_queue[i]->dev = priv->ndev;
20862788
CM		 605 }
606 return 0;
607}
608
609static void gfar_free_tx_queues(struct gfar_private *priv)
fba4ed03 610{
3a2e16c8 611 int i;
fba4ed03
SG		 612
613 for (i = 0; i < priv->num_tx_queues; i++)
614 kfree(priv->tx_queue[i]);
615}
616
20862788 617static void gfar_free_rx_queues(struct gfar_private *priv)
fba4ed03 618{
3a2e16c8 619 int i;
fba4ed03
SG		 620
621 for (i = 0; i < priv->num_rx_queues; i++)
622 kfree(priv->rx_queue[i]);
623}
624
46ceb60c
SG		 625static void unmap_group_regs(struct gfar_private *priv)
626{
3a2e16c8 627 int i;
46ceb60c
SG		 628
629 for (i = 0; i < MAXGROUPS; i++)
630 if (priv->gfargrp[i].regs)
631 iounmap(priv->gfargrp[i].regs);
632}
633
ee873fda
CM		 634static void free_gfar_dev(struct gfar_private *priv)
635{
636 int i, j;
637
638 for (i = 0; i < priv->num_grps; i++)
639 for (j = 0; j < GFAR_NUM_IRQS; j++) {
640 kfree(priv->gfargrp[i].irqinfo[j]);
641 priv->gfargrp[i].irqinfo[j] = NULL;
642 }
643
644 free_netdev(priv->ndev);
645}
646
46ceb60c
SG		 647static void disable_napi(struct gfar_private *priv)
648{
3a2e16c8 649 int i;
46ceb60c 650
aeb12c5e
CM		 651 for (i = 0; i < priv->num_grps; i++) {
652 napi_disable(&priv->gfargrp[i].napi_rx);
653 napi_disable(&priv->gfargrp[i].napi_tx);
654 }
46ceb60c
SG		 655}
656
657static void enable_napi(struct gfar_private *priv)
658{
3a2e16c8 659 int i;
46ceb60c 660
aeb12c5e
CM		 661 for (i = 0; i < priv->num_grps; i++) {
662 napi_enable(&priv->gfargrp[i].napi_rx);
663 napi_enable(&priv->gfargrp[i].napi_tx);
664 }
46ceb60c
SG		 665}
666
667static int gfar_parse_group(struct device_node *np,
bc4598bc 668 struct gfar_private *priv, const char *model)
46ceb60c 669{
5fedcc14 670 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
ee873fda
CM		 671 int i;
672
7c1e7e99
PG		 673 for (i = 0; i < GFAR_NUM_IRQS; i++) {
674 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
675 GFP_KERNEL);
676 if (!grp->irqinfo[i])
ee873fda 677 return -ENOMEM;
ee873fda 678 }
46ceb60c 679
5fedcc14
CM		 680 grp->regs = of_iomap(np, 0);
681 if (!grp->regs)
46ceb60c
SG		 682 return -ENOMEM;
683
ee873fda 684 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
46ceb60c
SG		 685
686 /* If we aren't the FEC we have multiple interrupts */
687 if (model && strcasecmp(model, "FEC")) {
ee873fda
CM		 688 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
689 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
690 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
691 gfar_irq(grp, RX)->irq == NO_IRQ ||
692 gfar_irq(grp, ER)->irq == NO_IRQ)
46ceb60c 693 return -EINVAL;
46ceb60c
SG		 694 }
695
5fedcc14
CM		 696 grp->priv = priv;
697 spin_lock_init(&grp->grplock);
bc4598bc 698 if (priv->mode == MQ_MG_MODE) {
71ff9e3d
CM		 699 u32 *rxq_mask, *txq_mask;
700 rxq_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
701 txq_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
702
703 if (priv->poll_mode == GFAR_SQ_POLLING) {
704 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
705 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
706 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
707 } else { /* GFAR_MQ_POLLING */
708 grp->rx_bit_map = rxq_mask ?
709 *rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
710 grp->tx_bit_map = txq_mask ?
711 *txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
712 }
46ceb60c 713 } else {
5fedcc14
CM		 714 grp->rx_bit_map = 0xFF;
715 grp->tx_bit_map = 0xFF;
46ceb60c 716 }
20862788
CM		 717
718 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
719 * right to left, so we need to revert the 8 bits to get the q index
720 */
721 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
722 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
723
724 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
725 * also assign queues to groups
726 */
727 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
71ff9e3d
CM		 728 if (!grp->rx_queue)
729 grp->rx_queue = priv->rx_queue[i];
20862788
CM		 730 grp->num_rx_queues++;
731 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
732 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
733 priv->rx_queue[i]->grp = grp;
734 }
735
736 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
71ff9e3d
CM		 737 if (!grp->tx_queue)
738 grp->tx_queue = priv->tx_queue[i];
20862788
CM		 739 grp->num_tx_queues++;
740 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
741 priv->tqueue |= (TQUEUE_EN0 >> i);
742 priv->tx_queue[i]->grp = grp;
743 }
744
46ceb60c
SG		 745 priv->num_grps++;
746
747 return 0;
748}
749
2dc11581 750static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 751{
b31a1d8b
AF		 752 const char *model;
753 const char *ctype;
754 const void *mac_addr;
fba4ed03
SG		 755 int err = 0, i;
756 struct net_device *dev = NULL;
757 struct gfar_private *priv = NULL;
61c7a080 758 struct device_node *np = ofdev->dev.of_node;
46ceb60c 759 struct device_node *child = NULL;
4d7902f2
AF		 760 const u32 *stash;
761 const u32 *stash_len;
762 const u32 *stash_idx;
fba4ed03
SG		 763 unsigned int num_tx_qs, num_rx_qs;
764 u32 *tx_queues, *rx_queues;
b338ce27 765 unsigned short mode, poll_mode;
b31a1d8b 766
4b222ca6 767 if (!np)
b31a1d8b
AF		 768 return -ENODEV;
769
b338ce27
CM		 770 if (of_device_is_compatible(np, "fsl,etsec2")) {
771 mode = MQ_MG_MODE;
772 poll_mode = GFAR_SQ_POLLING;
773 } else {
774 mode = SQ_SG_MODE;
775 poll_mode = GFAR_SQ_POLLING;
776 }
777
71ff9e3d 778 /* parse the num of HW tx and rx queues */
fba4ed03 779 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
71ff9e3d
CM		 780 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
781
b338ce27 782 if (mode == SQ_SG_MODE) {
71ff9e3d
CM		 783 num_tx_qs = 1;
784 num_rx_qs = 1;
785 } else { /* MQ_MG_MODE */
c65d7533
CM		 786 /* get the actual number of supported groups */
787 unsigned int num_grps = of_get_available_child_count(np);
788
789 if (num_grps == 0 || num_grps > MAXGROUPS) {
790 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
791 num_grps);
792 pr_err("Cannot do alloc_etherdev, aborting\n");
793 return -EINVAL;
794 }
795
b338ce27 796 if (poll_mode == GFAR_SQ_POLLING) {
c65d7533
CM		 797 num_tx_qs = num_grps; /* one txq per int group */
798 num_rx_qs = num_grps; /* one rxq per int group */
71ff9e3d
CM		 799 } else { /* GFAR_MQ_POLLING */
800 num_tx_qs = tx_queues ? *tx_queues : 1;
801 num_rx_qs = rx_queues ? *rx_queues : 1;
802 }
803 }
fba4ed03
SG		 804
805 if (num_tx_qs > MAX_TX_QS) {
59deab26
JP		 806 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
807 num_tx_qs, MAX_TX_QS);
808 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 809 return -EINVAL;
810 }
811
fba4ed03 812 if (num_rx_qs > MAX_RX_QS) {
59deab26
JP		 813 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
814 num_rx_qs, MAX_RX_QS);
815 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 816 return -EINVAL;
817 }
818
819 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
820 dev = *pdev;
821 if (NULL == dev)
822 return -ENOMEM;
823
824 priv = netdev_priv(dev);
fba4ed03
SG		 825 priv->ndev = dev;
826
b338ce27
CM		 827 priv->mode = mode;
828 priv->poll_mode = poll_mode;
829
fba4ed03 830 priv->num_tx_queues = num_tx_qs;
fe069123 831 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 832 priv->num_rx_queues = num_rx_qs;
20862788
CM		 833
834 err = gfar_alloc_tx_queues(priv);
835 if (err)
836 goto tx_alloc_failed;
837
838 err = gfar_alloc_rx_queues(priv);
839 if (err)
840 goto rx_alloc_failed;
b31a1d8b 841
0977f817 842 /* Init Rx queue filer rule set linked list */
4aa3a715
SP		 843 INIT_LIST_HEAD(&priv->rx_list.list);
844 priv->rx_list.count = 0;
845 mutex_init(&priv->rx_queue_access);
846
b31a1d8b
AF		 847 model = of_get_property(np, "model", NULL);
848
46ceb60c
SG		 849 for (i = 0; i < MAXGROUPS; i++)
850 priv->gfargrp[i].regs = NULL;
b31a1d8b 851
46ceb60c 852 /* Parse and initialize group specific information */
b338ce27 853 if (priv->mode == MQ_MG_MODE) {
46ceb60c
SG		 854 for_each_child_of_node(np, child) {
855 err = gfar_parse_group(child, priv, model);
856 if (err)
857 goto err_grp_init;
b31a1d8b 858 }
b338ce27 859 } else { /* SQ_SG_MODE */
46ceb60c 860 err = gfar_parse_group(np, priv, model);
bc4598bc 861 if (err)
46ceb60c 862 goto err_grp_init;
b31a1d8b
AF		 863 }
864
4d7902f2
AF		 865 stash = of_get_property(np, "bd-stash", NULL);
866
a12f801d 867 if (stash) {
4d7902f2
AF		 868 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
869 priv->bd_stash_en = 1;
870 }
871
872 stash_len = of_get_property(np, "rx-stash-len", NULL);
873
874 if (stash_len)
875 priv->rx_stash_size = *stash_len;
876
877 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
878
879 if (stash_idx)
880 priv->rx_stash_index = *stash_idx;
881
882 if (stash_len || stash_idx)
883 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
884
b31a1d8b 885 mac_addr = of_get_mac_address(np);
bc4598bc 886
b31a1d8b 887 if (mac_addr)
6a3c910c 888 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
b31a1d8b
AF		 889
890 if (model && !strcasecmp(model, "TSEC"))
34018fd4 891 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 892 FSL_GIANFAR_DEV_HAS_COALESCE |
893 FSL_GIANFAR_DEV_HAS_RMON |
894 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
895
b31a1d8b 896 if (model && !strcasecmp(model, "eTSEC"))
34018fd4 897 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 898 FSL_GIANFAR_DEV_HAS_COALESCE |
899 FSL_GIANFAR_DEV_HAS_RMON |
900 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
bc4598bc
JC		 901 FSL_GIANFAR_DEV_HAS_CSUM |
902 FSL_GIANFAR_DEV_HAS_VLAN |
903 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
904 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
905 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 906
907 ctype = of_get_property(np, "phy-connection-type", NULL);
908
909 /* We only care about rgmii-id. The rest are autodetected */
910 if (ctype && !strcmp(ctype, "rgmii-id"))
911 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
912 else
913 priv->interface = PHY_INTERFACE_MODE_MII;
914
915 if (of_get_property(np, "fsl,magic-packet", NULL))
916 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
917
fe192a49 918 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b 919
be403645
FF		 920 /* In the case of a fixed PHY, the DT node associated
921 * to the PHY is the Ethernet MAC DT node.
922 */
6f2c9bd8 923 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
be403645
FF		 924 err = of_phy_register_fixed_link(np);
925 if (err)
926 goto err_grp_init;
927
6f2c9bd8 928 priv->phy_node = of_node_get(np);
be403645
FF		 929 }
930
b31a1d8b 931 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 932 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 933
934 return 0;
935
46ceb60c
SG		 936err_grp_init:
937 unmap_group_regs(priv);
20862788
CM		 938rx_alloc_failed:
939 gfar_free_rx_queues(priv);
940tx_alloc_failed:
941 gfar_free_tx_queues(priv);
ee873fda 942 free_gfar_dev(priv);
b31a1d8b
AF		 943 return err;
944}
945
ca0c88c2 946static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
cc772ab7
MR		 947{
948 struct hwtstamp_config config;
949 struct gfar_private *priv = netdev_priv(netdev);
950
951 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
952 return -EFAULT;
953
954 /* reserved for future extensions */
955 if (config.flags)
956 return -EINVAL;
957
f0ee7acf
MR		 958 switch (config.tx_type) {
959 case HWTSTAMP_TX_OFF:
960 priv->hwts_tx_en = 0;
961 break;
962 case HWTSTAMP_TX_ON:
963 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
964 return -ERANGE;
965 priv->hwts_tx_en = 1;
966 break;
967 default:
cc772ab7 968 return -ERANGE;
f0ee7acf 969 }
cc772ab7
MR		 970
971 switch (config.rx_filter) {
972 case HWTSTAMP_FILTER_NONE:
97553f7f 973 if (priv->hwts_rx_en) {
97553f7f 974 priv->hwts_rx_en = 0;
0851133b 975 reset_gfar(netdev);
97553f7f 976 }
cc772ab7
MR		 977 break;
978 default:
979 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
980 return -ERANGE;
97553f7f 981 if (!priv->hwts_rx_en) {
97553f7f 982 priv->hwts_rx_en = 1;
0851133b 983 reset_gfar(netdev);
97553f7f 984 }
cc772ab7
MR		 985 config.rx_filter = HWTSTAMP_FILTER_ALL;
986 break;
987 }
988
989 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
990 -EFAULT : 0;
991}
992
ca0c88c2
BH		 993static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
994{
995 struct hwtstamp_config config;
996 struct gfar_private *priv = netdev_priv(netdev);
997
998 config.flags = 0;
999 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1000 config.rx_filter = (priv->hwts_rx_en ?
1001 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1002
1003 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1004 -EFAULT : 0;
1005}
1006
0faac9f7
CW		 1007static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1008{
1009 struct gfar_private *priv = netdev_priv(dev);
1010
1011 if (!netif_running(dev))
1012 return -EINVAL;
1013
cc772ab7 1014 if (cmd == SIOCSHWTSTAMP)
ca0c88c2
BH		 1015 return gfar_hwtstamp_set(dev, rq);
1016 if (cmd == SIOCGHWTSTAMP)
1017 return gfar_hwtstamp_get(dev, rq);
cc772ab7 1018
0faac9f7
CW		 1019 if (!priv->phydev)
1020 return -ENODEV;
1021
28b04113 1022 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 1023}
1024
18294ad1
AV		 1025static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1026 u32 class)
7a8b3372
SG		 1027{
1028 u32 rqfpr = FPR_FILER_MASK;
1029 u32 rqfcr = 0x0;
1030
1031 rqfar--;
1032 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
6c43e046
WJB		 1033 priv->ftp_rqfpr[rqfar] = rqfpr;
1034 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 1035 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1036
1037 rqfar--;
1038 rqfcr = RQFCR_CMP_NOMATCH;
6c43e046
WJB		 1039 priv->ftp_rqfpr[rqfar] = rqfpr;
1040 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 1041 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1042
1043 rqfar--;
1044 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1045 rqfpr = class;
6c43e046
WJB		 1046 priv->ftp_rqfcr[rqfar] = rqfcr;
1047 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1048 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1049
1050 rqfar--;
1051 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1052 rqfpr = class;
6c43e046
WJB		 1053 priv->ftp_rqfcr[rqfar] = rqfcr;
1054 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1055 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1056
1057 return rqfar;
1058}
1059
1060static void gfar_init_filer_table(struct gfar_private *priv)
1061{
1062 int i = 0x0;
1063 u32 rqfar = MAX_FILER_IDX;
1064 u32 rqfcr = 0x0;
1065 u32 rqfpr = FPR_FILER_MASK;
1066
1067 /* Default rule */
1068 rqfcr = RQFCR_CMP_MATCH;
6c43e046
WJB		 1069 priv->ftp_rqfcr[rqfar] = rqfcr;
1070 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1071 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1072
1073 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1074 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1075 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1076 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1077 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1078 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1079
85dd08eb 1080 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 1081 priv->cur_filer_idx = rqfar;
1082
1083 /* Rest are masked rules */
1084 rqfcr = RQFCR_CMP_NOMATCH;
1085 for (i = 0; i < rqfar; i++) {
6c43e046
WJB		 1086 priv->ftp_rqfcr[i] = rqfcr;
1087 priv->ftp_rqfpr[i] = rqfpr;
7a8b3372
SG		 1088 gfar_write_filer(priv, i, rqfcr, rqfpr);
1089 }
1090}
1091
d6ef0bcc 1092#ifdef CONFIG_PPC
2969b1f7 1093static void __gfar_detect_errata_83xx(struct gfar_private *priv)
7d350977 1094{
7d350977
AV		 1095 unsigned int pvr = mfspr(SPRN_PVR);
1096 unsigned int svr = mfspr(SPRN_SVR);
1097 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1098 unsigned int rev = svr & 0xffff;
1099
1100 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1101 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
bc4598bc 1102 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
7d350977
AV		 1103 priv->errata |= GFAR_ERRATA_74;
1104
deb90eac
AV		 1105 /* MPC8313 and MPC837x all rev */
1106 if ((pvr == 0x80850010 && mod == 0x80b0) ||
bc4598bc 1107 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
deb90eac
AV		 1108 priv->errata |= GFAR_ERRATA_76;
1109
2969b1f7
CM		 1110 /* MPC8313 Rev < 2.0 */
1111 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1112 priv->errata |= GFAR_ERRATA_12;
1113}
1114
1115static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1116{
1117 unsigned int svr = mfspr(SPRN_SVR);
1118
1119 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
4363c2fd 1120 priv->errata |= GFAR_ERRATA_12;
53fad773
CM		 1121 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1122 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1123 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
2969b1f7 1124}
d6ef0bcc 1125#endif
2969b1f7
CM		 1126
1127static void gfar_detect_errata(struct gfar_private *priv)
1128{
1129 struct device *dev = &priv->ofdev->dev;
1130
1131 /* no plans to fix */
1132 priv->errata |= GFAR_ERRATA_A002;
1133
d6ef0bcc 1134#ifdef CONFIG_PPC
2969b1f7
CM		 1135 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1136 __gfar_detect_errata_85xx(priv);
1137 else /* non-mpc85xx parts, i.e. e300 core based */
1138 __gfar_detect_errata_83xx(priv);
d6ef0bcc 1139#endif
4363c2fd 1140
7d350977
AV		 1141 if (priv->errata)
1142 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1143 priv->errata);
1144}
1145
0851133b 1146void gfar_mac_reset(struct gfar_private *priv)
20862788
CM		 1147{
1148 struct gfar __iomem *regs = priv->gfargrp[0].regs;
a328ac92 1149 u32 tempval;
20862788
CM		 1150
1151 /* Reset MAC layer */
1152 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1153
1154 /* We need to delay at least 3 TX clocks */
a328ac92 1155 udelay(3);
20862788
CM		 1156
1157 /* the soft reset bit is not self-resetting, so we need to
1158 * clear it before resuming normal operation
1159 */
1160 gfar_write(&regs->maccfg1, 0);
1161
a328ac92
CM		 1162 udelay(3);
1163
88302648
CM		 1164 /* Compute rx_buff_size based on config flags */
1165 gfar_rx_buff_size_config(priv);
1166
1167 /* Initialize the max receive frame/buffer lengths */
1168 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
a328ac92
CM		 1169 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1170
1171 /* Initialize the Minimum Frame Length Register */
1172 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1173
20862788
CM		 1174 /* Initialize MACCFG2. */
1175 tempval = MACCFG2_INIT_SETTINGS;
88302648
CM		 1176
1177 /* If the mtu is larger than the max size for standard
1178 * ethernet frames (ie, a jumbo frame), then set maccfg2
1179 * to allow huge frames, and to check the length
1180 */
1181 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1182 gfar_has_errata(priv, GFAR_ERRATA_74))
20862788 1183 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
88302648 1184
20862788
CM		 1185 gfar_write(&regs->maccfg2, tempval);
1186
a328ac92
CM		 1187 /* Clear mac addr hash registers */
1188 gfar_write(&regs->igaddr0, 0);
1189 gfar_write(&regs->igaddr1, 0);
1190 gfar_write(&regs->igaddr2, 0);
1191 gfar_write(&regs->igaddr3, 0);
1192 gfar_write(&regs->igaddr4, 0);
1193 gfar_write(&regs->igaddr5, 0);
1194 gfar_write(&regs->igaddr6, 0);
1195 gfar_write(&regs->igaddr7, 0);
1196
1197 gfar_write(&regs->gaddr0, 0);
1198 gfar_write(&regs->gaddr1, 0);
1199 gfar_write(&regs->gaddr2, 0);
1200 gfar_write(&regs->gaddr3, 0);
1201 gfar_write(&regs->gaddr4, 0);
1202 gfar_write(&regs->gaddr5, 0);
1203 gfar_write(&regs->gaddr6, 0);
1204 gfar_write(&regs->gaddr7, 0);
1205
1206 if (priv->extended_hash)
1207 gfar_clear_exact_match(priv->ndev);
1208
1209 gfar_mac_rx_config(priv);
1210
1211 gfar_mac_tx_config(priv);
1212
1213 gfar_set_mac_address(priv->ndev);
1214
1215 gfar_set_multi(priv->ndev);
1216
1217 /* clear ievent and imask before configuring coalescing */
1218 gfar_ints_disable(priv);
1219
1220 /* Configure the coalescing support */
1221 gfar_configure_coalescing_all(priv);
1222}
1223
1224static void gfar_hw_init(struct gfar_private *priv)
1225{
1226 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1227 u32 attrs;
1228
1229 /* Stop the DMA engine now, in case it was running before
1230 * (The firmware could have used it, and left it running).
1231 */
1232 gfar_halt(priv);
1233
1234 gfar_mac_reset(priv);
1235
1236 /* Zero out the rmon mib registers if it has them */
1237 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1238 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1239
1240 /* Mask off the CAM interrupts */
1241 gfar_write(&regs->rmon.cam1, 0xffffffff);
1242 gfar_write(&regs->rmon.cam2, 0xffffffff);
1243 }
1244
20862788
CM		 1245 /* Initialize ECNTRL */
1246 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1247
34018fd4
CM		 1248 /* Set the extraction length and index */
1249 attrs = ATTRELI_EL(priv->rx_stash_size) |
1250 ATTRELI_EI(priv->rx_stash_index);
1251
1252 gfar_write(&regs->attreli, attrs);
1253
1254 /* Start with defaults, and add stashing
1255 * depending on driver parameters
1256 */
1257 attrs = ATTR_INIT_SETTINGS;
1258
1259 if (priv->bd_stash_en)
1260 attrs |= ATTR_BDSTASH;
1261
1262 if (priv->rx_stash_size != 0)
1263 attrs |= ATTR_BUFSTASH;
1264
1265 gfar_write(&regs->attr, attrs);
1266
1267 /* FIFO configs */
1268 gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1269 gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1270 gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1271
20862788
CM		 1272 /* Program the interrupt steering regs, only for MG devices */
1273 if (priv->num_grps > 1)
1274 gfar_write_isrg(priv);
20862788
CM		 1275}
1276
898157ed 1277static void gfar_init_addr_hash_table(struct gfar_private *priv)
20862788
CM		 1278{
1279 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1280
1281 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1282 priv->extended_hash = 1;
1283 priv->hash_width = 9;
1284
1285 priv->hash_regs[0] = &regs->igaddr0;
1286 priv->hash_regs[1] = &regs->igaddr1;
1287 priv->hash_regs[2] = &regs->igaddr2;
1288 priv->hash_regs[3] = &regs->igaddr3;
1289 priv->hash_regs[4] = &regs->igaddr4;
1290 priv->hash_regs[5] = &regs->igaddr5;
1291 priv->hash_regs[6] = &regs->igaddr6;
1292 priv->hash_regs[7] = &regs->igaddr7;
1293 priv->hash_regs[8] = &regs->gaddr0;
1294 priv->hash_regs[9] = &regs->gaddr1;
1295 priv->hash_regs[10] = &regs->gaddr2;
1296 priv->hash_regs[11] = &regs->gaddr3;
1297 priv->hash_regs[12] = &regs->gaddr4;
1298 priv->hash_regs[13] = &regs->gaddr5;
1299 priv->hash_regs[14] = &regs->gaddr6;
1300 priv->hash_regs[15] = &regs->gaddr7;
1301
1302 } else {
1303 priv->extended_hash = 0;
1304 priv->hash_width = 8;
1305
1306 priv->hash_regs[0] = &regs->gaddr0;
1307 priv->hash_regs[1] = &regs->gaddr1;
1308 priv->hash_regs[2] = &regs->gaddr2;
1309 priv->hash_regs[3] = &regs->gaddr3;
1310 priv->hash_regs[4] = &regs->gaddr4;
1311 priv->hash_regs[5] = &regs->gaddr5;
1312 priv->hash_regs[6] = &regs->gaddr6;
1313 priv->hash_regs[7] = &regs->gaddr7;
1314 }
1315}
1316
bb40dcbb 1317/* Set up the ethernet device structure, private data,
0977f817
JC		 1318 * and anything else we need before we start
1319 */
74888760 1320static int gfar_probe(struct platform_device *ofdev)
1da177e4 1321{
1da177e4
LT		 1322 struct net_device *dev = NULL;
1323 struct gfar_private *priv = NULL;
20862788 1324 int err = 0, i;
1da177e4 1325
fba4ed03 1326 err = gfar_of_init(ofdev, &dev);
1da177e4 1327
fba4ed03
SG		 1328 if (err)
1329 return err;
1da177e4
LT		 1330
1331 priv = netdev_priv(dev);
4826857f
KG		 1332 priv->ndev = dev;
1333 priv->ofdev = ofdev;
369ec162 1334 priv->dev = &ofdev->dev;
4826857f 1335 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 1336
d87eb127 1337 spin_lock_init(&priv->bflock);
ab939905 1338 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 1339
8513fbd8 1340 platform_set_drvdata(ofdev, priv);
1da177e4 1341
7d350977
AV		 1342 gfar_detect_errata(priv);
1343
1da177e4 1344 /* Set the dev->base_addr to the gfar reg region */
20862788 1345 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1da177e4 1346
1da177e4 1347 /* Fill in the dev structure */
1da177e4 1348 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1349 dev->mtu = 1500;
26ccfc37 1350 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1351 dev->ethtool_ops = &gfar_ethtool_ops;
1352
fba4ed03 1353 /* Register for napi ...We are registering NAPI for each grp */
71ff9e3d
CM		 1354 for (i = 0; i < priv->num_grps; i++) {
1355 if (priv->poll_mode == GFAR_SQ_POLLING) {
1356 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1357 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1358 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1359 gfar_poll_tx_sq, 2);
1360 } else {
aeb12c5e
CM		 1361 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1362 gfar_poll_rx, GFAR_DEV_WEIGHT);
1363 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1364 gfar_poll_tx, 2);
1365 }
1366 }
a12f801d 1367
b31a1d8b 1368 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
8b3afe95 1369 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1370 NETIF_F_RXCSUM;
8b3afe95 1371 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1372 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
8b3afe95 1373 }
0bbaf069 1374
87c288c6 1375 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
f646968f
PM		 1376 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1377 NETIF_F_HW_VLAN_CTAG_RX;
1378 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
87c288c6 1379 }
0bbaf069 1380
20862788 1381 gfar_init_addr_hash_table(priv);
0bbaf069 1382
532c37bc
CM		 1383 /* Insert receive time stamps into padding alignment bytes */
1384 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1385 priv->padding = 8;
0bbaf069 1386
cc772ab7 1387 if (dev->features & NETIF_F_IP_CSUM ||
bc4598bc 1388 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
bee9e58c 1389 dev->needed_headroom = GMAC_FCB_LEN;
1da177e4
LT		 1390
1391 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1392
a12f801d 1393 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1394 for (i = 0; i < priv->num_tx_queues; i++) {
1395 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1396 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1397 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1398 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1399 }
a12f801d 1400
fba4ed03
SG		 1401 for (i = 0; i < priv->num_rx_queues; i++) {
1402 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1403 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1404 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1405 }
1da177e4 1406
0977f817 1407 /* always enable rx filer */
4aa3a715 1408 priv->rx_filer_enable = 1;
0bbaf069
KG		 1409 /* Enable most messages by default */
1410 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
b98b8bab
CM		 1411 /* use pritority h/w tx queue scheduling for single queue devices */
1412 if (priv->num_tx_queues == 1)
1413 priv->prio_sched_en = 1;
0bbaf069 1414
0851133b
CM		 1415 set_bit(GFAR_DOWN, &priv->state);
1416
a328ac92 1417 gfar_hw_init(priv);
d3eab82b 1418
d4c642ea
FE		 1419 /* Carrier starts down, phylib will bring it up */
1420 netif_carrier_off(dev);
1421
1da177e4
LT		 1422 err = register_netdev(dev);
1423
1424 if (err) {
59deab26 1425 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1da177e4
LT		 1426 goto register_fail;
1427 }
1428
2884e5cc 1429 device_init_wakeup(&dev->dev,
bc4598bc
JC		 1430 priv->device_flags &
1431 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
2884e5cc 1432
c50a5d9a 1433 /* fill out IRQ number and name fields */
46ceb60c 1434 for (i = 0; i < priv->num_grps; i++) {
ee873fda 1435 struct gfar_priv_grp *grp = &priv->gfargrp[i];
46ceb60c 1436 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
ee873fda 1437 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
0015e551 1438 dev->name, "_g", '0' + i, "_tx");
ee873fda 1439 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
0015e551 1440 dev->name, "_g", '0' + i, "_rx");
ee873fda 1441 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
0015e551 1442 dev->name, "_g", '0' + i, "_er");
46ceb60c 1443 } else
ee873fda 1444 strcpy(gfar_irq(grp, TX)->name, dev->name);
46ceb60c 1445 }
c50a5d9a 1446
7a8b3372
SG		 1447 /* Initialize the filer table */
1448 gfar_init_filer_table(priv);
1449
1da177e4 1450 /* Print out the device info */
59deab26 1451 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1da177e4 1452
0977f817
JC		 1453 /* Even more device info helps when determining which kernel
1454 * provided which set of benchmarks.
1455 */
59deab26 1456 netdev_info(dev, "Running with NAPI enabled\n");
fba4ed03 1457 for (i = 0; i < priv->num_rx_queues; i++)
59deab26
JP		 1458 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1459 i, priv->rx_queue[i]->rx_ring_size);
bc4598bc 1460 for (i = 0; i < priv->num_tx_queues; i++)
59deab26
JP		 1461 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1462 i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1463
1464 return 0;
1465
1466register_fail:
46ceb60c 1467 unmap_group_regs(priv);
20862788
CM		 1468 gfar_free_rx_queues(priv);
1469 gfar_free_tx_queues(priv);
888c88b8
UKK		 1470 of_node_put(priv->phy_node);
1471 of_node_put(priv->tbi_node);
ee873fda 1472 free_gfar_dev(priv);
bb40dcbb 1473 return err;
1da177e4
LT		 1474}
1475
2dc11581 1476static int gfar_remove(struct platform_device *ofdev)
1da177e4 1477{
8513fbd8 1478 struct gfar_private *priv = platform_get_drvdata(ofdev);
1da177e4 1479
888c88b8
UKK		 1480 of_node_put(priv->phy_node);
1481 of_node_put(priv->tbi_node);
fe192a49 1482
d9d8e041 1483 unregister_netdev(priv->ndev);
46ceb60c 1484 unmap_group_regs(priv);
20862788
CM		 1485 gfar_free_rx_queues(priv);
1486 gfar_free_tx_queues(priv);
ee873fda 1487 free_gfar_dev(priv);
1da177e4
LT		 1488
1489 return 0;
1490}
1491
d87eb127 1492#ifdef CONFIG_PM
be926fc4
AV		 1493
1494static int gfar_suspend(struct device *dev)
d87eb127 1495{
be926fc4
AV		 1496 struct gfar_private *priv = dev_get_drvdata(dev);
1497 struct net_device *ndev = priv->ndev;
46ceb60c 1498 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1499 unsigned long flags;
1500 u32 tempval;
1501
1502 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1503 (priv->device_flags &
1504 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1505
be926fc4 1506 netif_device_detach(ndev);
d87eb127 1507
be926fc4 1508 if (netif_running(ndev)) {
fba4ed03
SG		 1509
1510 local_irq_save(flags);
1511 lock_tx_qs(priv);
d87eb127 1512
c10650b6 1513 gfar_halt_nodisable(priv);
d87eb127
SW		 1514
1515 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1516 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1517
1518 tempval &= ~MACCFG1_TX_EN;
1519
1520 if (!magic_packet)
1521 tempval &= ~MACCFG1_RX_EN;
1522
f4983704 1523 gfar_write(&regs->maccfg1, tempval);
d87eb127 1524
fba4ed03
SG		 1525 unlock_tx_qs(priv);
1526 local_irq_restore(flags);
d87eb127 1527
46ceb60c 1528 disable_napi(priv);
d87eb127
SW		 1529
1530 if (magic_packet) {
1531 /* Enable interrupt on Magic Packet */
f4983704 1532 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1533
1534 /* Enable Magic Packet mode */
f4983704 1535 tempval = gfar_read(&regs->maccfg2);
d87eb127 1536 tempval |= MACCFG2_MPEN;
f4983704 1537 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1538 } else {
1539 phy_stop(priv->phydev);
1540 }
1541 }
1542
1543 return 0;
1544}
1545
be926fc4 1546static int gfar_resume(struct device *dev)
d87eb127 1547{
be926fc4
AV		 1548 struct gfar_private *priv = dev_get_drvdata(dev);
1549 struct net_device *ndev = priv->ndev;
46ceb60c 1550 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1551 unsigned long flags;
1552 u32 tempval;
1553 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1554 (priv->device_flags &
1555 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1556
be926fc4
AV		 1557 if (!netif_running(ndev)) {
1558 netif_device_attach(ndev);
d87eb127
SW		 1559 return 0;
1560 }
1561
1562 if (!magic_packet && priv->phydev)
1563 phy_start(priv->phydev);
1564
1565 /* Disable Magic Packet mode, in case something
1566 * else woke us up.
1567 */
fba4ed03
SG		 1568 local_irq_save(flags);
1569 lock_tx_qs(priv);
d87eb127 1570
f4983704 1571 tempval = gfar_read(&regs->maccfg2);
d87eb127 1572 tempval &= ~MACCFG2_MPEN;
f4983704 1573 gfar_write(&regs->maccfg2, tempval);
d87eb127 1574
c10650b6 1575 gfar_start(priv);
d87eb127 1576
fba4ed03
SG		 1577 unlock_tx_qs(priv);
1578 local_irq_restore(flags);
d87eb127 1579
be926fc4
AV		 1580 netif_device_attach(ndev);
1581
46ceb60c 1582 enable_napi(priv);
be926fc4
AV		 1583
1584 return 0;
1585}
1586
1587static int gfar_restore(struct device *dev)
1588{
1589 struct gfar_private *priv = dev_get_drvdata(dev);
1590 struct net_device *ndev = priv->ndev;
1591
103cdd1d
WD		 1592 if (!netif_running(ndev)) {
1593 netif_device_attach(ndev);
1594
be926fc4 1595 return 0;
103cdd1d 1596 }
be926fc4 1597
1eb8f7a7
CM		 1598 if (gfar_init_bds(ndev)) {
1599 free_skb_resources(priv);
1600 return -ENOMEM;
1601 }
1602
a328ac92
CM		 1603 gfar_mac_reset(priv);
1604
1605 gfar_init_tx_rx_base(priv);
1606
c10650b6 1607 gfar_start(priv);
be926fc4
AV		 1608
1609 priv->oldlink = 0;
1610 priv->oldspeed = 0;
1611 priv->oldduplex = -1;
1612
1613 if (priv->phydev)
1614 phy_start(priv->phydev);
d87eb127 1615
be926fc4 1616 netif_device_attach(ndev);
5ea681d4 1617 enable_napi(priv);
d87eb127
SW		 1618
1619 return 0;
1620}
be926fc4
AV		 1621
1622static struct dev_pm_ops gfar_pm_ops = {
1623 .suspend = gfar_suspend,
1624 .resume = gfar_resume,
1625 .freeze = gfar_suspend,
1626 .thaw = gfar_resume,
1627 .restore = gfar_restore,
1628};
1629
1630#define GFAR_PM_OPS (&gfar_pm_ops)
1631
d87eb127 1632#else
be926fc4
AV		 1633
1634#define GFAR_PM_OPS NULL
be926fc4 1635
d87eb127 1636#endif
1da177e4 1637
e8a2b6a4
AF		 1638/* Reads the controller's registers to determine what interface
1639 * connects it to the PHY.
1640 */
1641static phy_interface_t gfar_get_interface(struct net_device *dev)
1642{
1643 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1644 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1645 u32 ecntrl;
1646
f4983704 1647 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1648
1649 if (ecntrl & ECNTRL_SGMII_MODE)
1650 return PHY_INTERFACE_MODE_SGMII;
1651
1652 if (ecntrl & ECNTRL_TBI_MODE) {
1653 if (ecntrl & ECNTRL_REDUCED_MODE)
1654 return PHY_INTERFACE_MODE_RTBI;
1655 else
1656 return PHY_INTERFACE_MODE_TBI;
1657 }
1658
1659 if (ecntrl & ECNTRL_REDUCED_MODE) {
bc4598bc 1660 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
e8a2b6a4 1661 return PHY_INTERFACE_MODE_RMII;
bc4598bc 1662 }
7132ab7f 1663 else {
b31a1d8b 1664 phy_interface_t interface = priv->interface;
7132ab7f 1665
0977f817 1666 /* This isn't autodetected right now, so it must
7132ab7f
AF		 1667 * be set by the device tree or platform code.
1668 */
1669 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1670 return PHY_INTERFACE_MODE_RGMII_ID;
1671
e8a2b6a4 1672 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1673 }
e8a2b6a4
AF		 1674 }
1675
b31a1d8b 1676 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1677 return PHY_INTERFACE_MODE_GMII;
1678
1679 return PHY_INTERFACE_MODE_MII;
1680}
1681
1682
bb40dcbb
AF		 1683/* Initializes driver's PHY state, and attaches to the PHY.
1684 * Returns 0 on success.
1da177e4
LT		 1685 */
1686static int init_phy(struct net_device *dev)
1687{
1688 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1689 uint gigabit_support =
b31a1d8b 1690 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
23402bdd 1691 GFAR_SUPPORTED_GBIT : 0;
e8a2b6a4 1692 phy_interface_t interface;
1da177e4
LT		 1693
1694 priv->oldlink = 0;
1695 priv->oldspeed = 0;
1696 priv->oldduplex = -1;
1697
e8a2b6a4
AF		 1698 interface = gfar_get_interface(dev);
1699
1db780f8
AV		 1700 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1701 interface);
1db780f8
AV		 1702 if (!priv->phydev) {
1703 dev_err(&dev->dev, "could not attach to PHY\n");
1704 return -ENODEV;
fe192a49 1705 }
1da177e4 1706
d3c12873
KJ		 1707 if (interface == PHY_INTERFACE_MODE_SGMII)
1708 gfar_configure_serdes(dev);
1709
bb40dcbb 1710 /* Remove any features not supported by the controller */
fe192a49
GL		 1711 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1712 priv->phydev->advertising = priv->phydev->supported;
1da177e4 1713
cf987afc
PMB		 1714 /* Add support for flow control, but don't advertise it by default */
1715 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1716
1da177e4 1717 return 0;
1da177e4
LT		 1718}
1719
0977f817 1720/* Initialize TBI PHY interface for communicating with the
d0313587
PG		 1721 * SERDES lynx PHY on the chip. We communicate with this PHY
1722 * through the MDIO bus on each controller, treating it as a
1723 * "normal" PHY at the address found in the TBIPA register. We assume
1724 * that the TBIPA register is valid. Either the MDIO bus code will set
1725 * it to a value that doesn't conflict with other PHYs on the bus, or the
1726 * value doesn't matter, as there are no other PHYs on the bus.
1727 */
d3c12873
KJ		 1728static void gfar_configure_serdes(struct net_device *dev)
1729{
1730 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1731 struct phy_device *tbiphy;
1732
1733 if (!priv->tbi_node) {
1734 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1735 "device tree specify a tbi-handle\n");
1736 return;
1737 }
c132419e 1738
fe192a49
GL		 1739 tbiphy = of_phy_find_device(priv->tbi_node);
1740 if (!tbiphy) {
1741 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1742 return;
1743 }
d3c12873 1744
0977f817 1745 /* If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1746 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1747 * everything for us? Resetting it takes the link down and requires
1748 * several seconds for it to come back.
1749 */
fe192a49 1750 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1751 return;
d3c12873 1752
d0313587 1753 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1754 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1755
fe192a49 1756 phy_write(tbiphy, MII_ADVERTISE,
bc4598bc
JC		 1757 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1758 ADVERTISE_1000XPSE_ASYM);
d3c12873 1759
bc4598bc
JC		 1760 phy_write(tbiphy, MII_BMCR,
1761 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1762 BMCR_SPEED1000);
d3c12873
KJ		 1763}
1764
511d934f
AV		 1765static int __gfar_is_rx_idle(struct gfar_private *priv)
1766{
1767 u32 res;
1768
0977f817 1769 /* Normaly TSEC should not hang on GRS commands, so we should
511d934f
AV		 1770 * actually wait for IEVENT_GRSC flag.
1771 */
ad3660c2 1772 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
511d934f
AV		 1773 return 0;
1774
0977f817 1775 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
511d934f
AV		 1776 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1777 * and the Rx can be safely reset.
1778 */
1779 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1780 res &= 0x7f807f80;
1781 if ((res & 0xffff) == (res >> 16))
1782 return 1;
1783
1784 return 0;
1785}
0bbaf069
KG		 1786
1787/* Halt the receive and transmit queues */
c10650b6 1788static void gfar_halt_nodisable(struct gfar_private *priv)
1da177e4 1789{
efeddce7 1790 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 1791 u32 tempval;
a4feee89
CM		 1792 unsigned int timeout;
1793 int stopped;
1da177e4 1794
efeddce7 1795 gfar_ints_disable(priv);
1da177e4 1796
a4feee89
CM		 1797 if (gfar_is_dma_stopped(priv))
1798 return;
1799
1da177e4 1800 /* Stop the DMA, and wait for it to stop */
f4983704 1801 tempval = gfar_read(&regs->dmactrl);
a4feee89
CM		 1802 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1803 gfar_write(&regs->dmactrl, tempval);
1804
1805retry:
1806 timeout = 1000;
1807 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1808 cpu_relax();
1809 timeout--;
1da177e4 1810 }
a4feee89
CM		 1811
1812 if (!timeout)
1813 stopped = gfar_is_dma_stopped(priv);
1814
1815 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1816 !__gfar_is_rx_idle(priv))
1817 goto retry;
d87eb127 1818}
d87eb127
SW		 1819
1820/* Halt the receive and transmit queues */
c10650b6 1821void gfar_halt(struct gfar_private *priv)
d87eb127 1822{
46ceb60c 1823 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1824 u32 tempval;
1da177e4 1825
c10650b6
CM		 1826 /* Dissable the Rx/Tx hw queues */
1827 gfar_write(&regs->rqueue, 0);
1828 gfar_write(&regs->tqueue, 0);
2a54adc3 1829
c10650b6
CM		 1830 mdelay(10);
1831
1832 gfar_halt_nodisable(priv);
1833
1834 /* Disable Rx/Tx DMA */
1da177e4
LT		 1835 tempval = gfar_read(&regs->maccfg1);
1836 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1837 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1838}
1839
1840void stop_gfar(struct net_device *dev)
1841{
1842 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1843
0851133b 1844 netif_tx_stop_all_queues(dev);
bb40dcbb 1845
4e857c58 1846 smp_mb__before_atomic();
0851133b 1847 set_bit(GFAR_DOWN, &priv->state);
4e857c58 1848 smp_mb__after_atomic();
a12f801d 1849
0851133b 1850 disable_napi(priv);
0bbaf069 1851
0851133b 1852 /* disable ints and gracefully shut down Rx/Tx DMA */
c10650b6 1853 gfar_halt(priv);
1da177e4 1854
0851133b 1855 phy_stop(priv->phydev);
1da177e4 1856
1da177e4 1857 free_skb_resources(priv);
1da177e4
LT		 1858}
1859
fba4ed03 1860static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1861{
1da177e4 1862 struct txbd8 *txbdp;
fba4ed03 1863 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1864 int i, j;
1da177e4 1865
a12f801d 1866 txbdp = tx_queue->tx_bd_base;
1da177e4 1867
a12f801d
SG		 1868 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1869 if (!tx_queue->tx_skbuff[i])
4669bc90 1870 continue;
1da177e4 1871
369ec162 1872 dma_unmap_single(priv->dev, txbdp->bufPtr,
bc4598bc 1873 txbdp->length, DMA_TO_DEVICE);
4669bc90 1874 txbdp->lstatus = 0;
fba4ed03 1875 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
bc4598bc 1876 j++) {
4669bc90 1877 txbdp++;
369ec162 1878 dma_unmap_page(priv->dev, txbdp->bufPtr,
bc4598bc 1879 txbdp->length, DMA_TO_DEVICE);
1da177e4 1880 }
ad5da7ab 1881 txbdp++;
a12f801d
SG		 1882 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1883 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1884 }
a12f801d 1885 kfree(tx_queue->tx_skbuff);
1eb8f7a7 1886 tx_queue->tx_skbuff = NULL;
fba4ed03 1887}
1da177e4 1888
fba4ed03
SG		 1889static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1890{
1891 struct rxbd8 *rxbdp;
1892 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1893 int i;
1da177e4 1894
fba4ed03 1895 rxbdp = rx_queue->rx_bd_base;
1da177e4 1896
a12f801d
SG		 1897 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1898 if (rx_queue->rx_skbuff[i]) {
369ec162
CM		 1899 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1900 priv->rx_buffer_size,
bc4598bc 1901 DMA_FROM_DEVICE);
a12f801d
SG		 1902 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1903 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1904 }
e69edd21
AV		 1905 rxbdp->lstatus = 0;
1906 rxbdp->bufPtr = 0;
1907 rxbdp++;
1da177e4 1908 }
a12f801d 1909 kfree(rx_queue->rx_skbuff);
1eb8f7a7 1910 rx_queue->rx_skbuff = NULL;
fba4ed03 1911}
e69edd21 1912
fba4ed03 1913/* If there are any tx skbs or rx skbs still around, free them.
0977f817
JC		 1914 * Then free tx_skbuff and rx_skbuff
1915 */
fba4ed03
SG		 1916static void free_skb_resources(struct gfar_private *priv)
1917{
1918 struct gfar_priv_tx_q *tx_queue = NULL;
1919 struct gfar_priv_rx_q *rx_queue = NULL;
1920 int i;
1921
1922 /* Go through all the buffer descriptors and free their data buffers */
1923 for (i = 0; i < priv->num_tx_queues; i++) {
d8a0f1b0 1924 struct netdev_queue *txq;
bc4598bc 1925
fba4ed03 1926 tx_queue = priv->tx_queue[i];
d8a0f1b0 1927 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
bc4598bc 1928 if (tx_queue->tx_skbuff)
fba4ed03 1929 free_skb_tx_queue(tx_queue);
d8a0f1b0 1930 netdev_tx_reset_queue(txq);
fba4ed03
SG		 1931 }
1932
1933 for (i = 0; i < priv->num_rx_queues; i++) {
1934 rx_queue = priv->rx_queue[i];
bc4598bc 1935 if (rx_queue->rx_skbuff)
fba4ed03
SG		 1936 free_skb_rx_queue(rx_queue);
1937 }
1938
369ec162 1939 dma_free_coherent(priv->dev,
bc4598bc
JC		 1940 sizeof(struct txbd8) * priv->total_tx_ring_size +
1941 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1942 priv->tx_queue[0]->tx_bd_base,
1943 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 1944}
1945
c10650b6 1946void gfar_start(struct gfar_private *priv)
0bbaf069 1947{
46ceb60c 1948 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1949 u32 tempval;
46ceb60c 1950 int i = 0;
0bbaf069 1951
c10650b6
CM		 1952 /* Enable Rx/Tx hw queues */
1953 gfar_write(&regs->rqueue, priv->rqueue);
1954 gfar_write(&regs->tqueue, priv->tqueue);
0bbaf069
KG		 1955
1956 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1957 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1958 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1959 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1960
0bbaf069 1961 /* Make sure we aren't stopped */
f4983704 1962 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1963 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1964 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1965
46ceb60c
SG		 1966 for (i = 0; i < priv->num_grps; i++) {
1967 regs = priv->gfargrp[i].regs;
1968 /* Clear THLT/RHLT, so that the DMA starts polling now */
1969 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1970 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
46ceb60c 1971 }
12dea57b 1972
c10650b6
CM		 1973 /* Enable Rx/Tx DMA */
1974 tempval = gfar_read(&regs->maccfg1);
1975 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1976 gfar_write(&regs->maccfg1, tempval);
1977
efeddce7
CM		 1978 gfar_ints_enable(priv);
1979
c10650b6 1980 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1981}
1982
80ec396c
CM		 1983static void free_grp_irqs(struct gfar_priv_grp *grp)
1984{
1985 free_irq(gfar_irq(grp, TX)->irq, grp);
1986 free_irq(gfar_irq(grp, RX)->irq, grp);
1987 free_irq(gfar_irq(grp, ER)->irq, grp);
1988}
1989
46ceb60c
SG		 1990static int register_grp_irqs(struct gfar_priv_grp *grp)
1991{
1992 struct gfar_private *priv = grp->priv;
1993 struct net_device *dev = priv->ndev;
1994 int err;
1da177e4 1995
1da177e4 1996 /* If the device has multiple interrupts, register for
0977f817
JC		 1997 * them. Otherwise, only register for the one
1998 */
b31a1d8b 1999 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 2000 /* Install our interrupt handlers for Error,
0977f817
JC		 2001 * Transmit, and Receive
2002 */
ee873fda
CM		 2003 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2004 gfar_irq(grp, ER)->name, grp);
2005 if (err < 0) {
59deab26 2006 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2007 gfar_irq(grp, ER)->irq);
46ceb60c 2008
2145f1af 2009 goto err_irq_fail;
1da177e4 2010 }
ee873fda
CM		 2011 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2012 gfar_irq(grp, TX)->name, grp);
2013 if (err < 0) {
59deab26 2014 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2015 gfar_irq(grp, TX)->irq);
1da177e4
LT		 2016 goto tx_irq_fail;
2017 }
ee873fda
CM		 2018 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2019 gfar_irq(grp, RX)->name, grp);
2020 if (err < 0) {
59deab26 2021 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2022 gfar_irq(grp, RX)->irq);
1da177e4
LT		 2023 goto rx_irq_fail;
2024 }
2025 } else {
ee873fda
CM		 2026 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2027 gfar_irq(grp, TX)->name, grp);
2028 if (err < 0) {
59deab26 2029 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2030 gfar_irq(grp, TX)->irq);
1da177e4
LT		 2031 goto err_irq_fail;
2032 }
2033 }
2034
46ceb60c
SG		 2035 return 0;
2036
2037rx_irq_fail:
ee873fda 2038 free_irq(gfar_irq(grp, TX)->irq, grp);
46ceb60c 2039tx_irq_fail:
ee873fda 2040 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 2041err_irq_fail:
2042 return err;
2043
2044}
2045
80ec396c
CM		 2046static void gfar_free_irq(struct gfar_private *priv)
2047{
2048 int i;
2049
2050 /* Free the IRQs */
2051 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2052 for (i = 0; i < priv->num_grps; i++)
2053 free_grp_irqs(&priv->gfargrp[i]);
2054 } else {
2055 for (i = 0; i < priv->num_grps; i++)
2056 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2057 &priv->gfargrp[i]);
2058 }
2059}
2060
2061static int gfar_request_irq(struct gfar_private *priv)
2062{
2063 int err, i, j;
2064
2065 for (i = 0; i < priv->num_grps; i++) {
2066 err = register_grp_irqs(&priv->gfargrp[i]);
2067 if (err) {
2068 for (j = 0; j < i; j++)
2069 free_grp_irqs(&priv->gfargrp[j]);
2070 return err;
2071 }
2072 }
2073
2074 return 0;
2075}
2076
46ceb60c
SG		 2077/* Bring the controller up and running */
2078int startup_gfar(struct net_device *ndev)
2079{
2080 struct gfar_private *priv = netdev_priv(ndev);
80ec396c 2081 int err;
46ceb60c 2082
a328ac92 2083 gfar_mac_reset(priv);
46ceb60c 2084
46ceb60c
SG		 2085 err = gfar_alloc_skb_resources(ndev);
2086 if (err)
2087 return err;
2088
a328ac92 2089 gfar_init_tx_rx_base(priv);
46ceb60c 2090
4e857c58 2091 smp_mb__before_atomic();
0851133b 2092 clear_bit(GFAR_DOWN, &priv->state);
4e857c58 2093 smp_mb__after_atomic();
0851133b
CM		 2094
2095 /* Start Rx/Tx DMA and enable the interrupts */
c10650b6 2096 gfar_start(priv);
1da177e4 2097
826aa4a0
AV		 2098 phy_start(priv->phydev);
2099
0851133b
CM		 2100 enable_napi(priv);
2101
2102 netif_tx_wake_all_queues(ndev);
2103
1da177e4 2104 return 0;
1da177e4
LT		 2105}
2106
0977f817
JC		 2107/* Called when something needs to use the ethernet device
2108 * Returns 0 for success.
2109 */
1da177e4
LT		 2110static int gfar_enet_open(struct net_device *dev)
2111{
94e8cc35 2112 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 2113 int err;
2114
1da177e4 2115 err = init_phy(dev);
0851133b 2116 if (err)
1da177e4
LT		 2117 return err;
2118
80ec396c
CM		 2119 err = gfar_request_irq(priv);
2120 if (err)
2121 return err;
2122
1da177e4 2123 err = startup_gfar(dev);
0851133b 2124 if (err)
db0e8e3f 2125 return err;
1da177e4 2126
2884e5cc
AV		 2127 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2128
1da177e4
LT		 2129 return err;
2130}
2131
54dc79fe 2132static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 2133{
54dc79fe 2134 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 2135
2136 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 2137
0bbaf069
KG		 2138 return fcb;
2139}
2140
9c4886e5 2141static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
bc4598bc 2142 int fcb_length)
0bbaf069 2143{
0bbaf069
KG		 2144 /* If we're here, it's a IP packet with a TCP or UDP
2145 * payload. We set it to checksum, using a pseudo-header
2146 * we provide
2147 */
3a2e16c8 2148 u8 flags = TXFCB_DEFAULT;
0bbaf069 2149
0977f817
JC		 2150 /* Tell the controller what the protocol is
2151 * And provide the already calculated phcs
2152 */
eddc9ec5 2153 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 2154 flags |= TXFCB_UDP;
4bedb452 2155 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 2156 } else
8da32de5 2157 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 2158
2159 /* l3os is the distance between the start of the
2160 * frame (skb->data) and the start of the IP hdr.
2161 * l4os is the distance between the start of the
0977f817
JC		 2162 * l3 hdr and the l4 hdr
2163 */
9c4886e5 2164 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
cfe1fc77 2165 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2166
7f7f5316 2167 fcb->flags = flags;
0bbaf069
KG		 2168}
2169
7f7f5316 2170void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2171{
7f7f5316 2172 fcb->flags |= TXFCB_VLN;
df8a39de 2173 fcb->vlctl = skb_vlan_tag_get(skb);
0bbaf069
KG		 2174}
2175
4669bc90 2176static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
bc4598bc 2177 struct txbd8 *base, int ring_size)
4669bc90
DH		 2178{
2179 struct txbd8 *new_bd = bdp + stride;
2180
2181 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2182}
2183
2184static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
bc4598bc 2185 int ring_size)
4669bc90
DH		 2186{
2187 return skip_txbd(bdp, 1, base, ring_size);
2188}
2189
02d88fb4
CM		 2190/* eTSEC12: csum generation not supported for some fcb offsets */
2191static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2192 unsigned long fcb_addr)
2193{
2194 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2195 (fcb_addr % 0x20) > 0x18);
2196}
2197
2198/* eTSEC76: csum generation for frames larger than 2500 may
2199 * cause excess delays before start of transmission
2200 */
2201static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2202 unsigned int len)
2203{
2204 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2205 (len > 2500));
2206}
2207
0977f817
JC		 2208/* This is called by the kernel when a frame is ready for transmission.
2209 * It is pointed to by the dev->hard_start_xmit function pointer
2210 */
1da177e4
LT		 2211static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2212{
2213 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2214 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2215 struct netdev_queue *txq;
f4983704 2216 struct gfar __iomem *regs = NULL;
0bbaf069 2217 struct txfcb *fcb = NULL;
f0ee7acf 2218 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2219 u32 lstatus;
0d0cffdc
CM		 2220 int i, rq = 0;
2221 int do_tstamp, do_csum, do_vlan;
4669bc90 2222 u32 bufaddr;
fef6108d 2223 unsigned long flags;
50ad076b 2224 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
fba4ed03
SG		 2225
2226 rq = skb->queue_mapping;
2227 tx_queue = priv->tx_queue[rq];
2228 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2229 base = tx_queue->tx_bd_base;
46ceb60c 2230 regs = tx_queue->grp->regs;
f0ee7acf 2231
0d0cffdc 2232 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
df8a39de 2233 do_vlan = skb_vlan_tag_present(skb);
0d0cffdc
CM		 2234 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2235 priv->hwts_tx_en;
2236
2237 if (do_csum || do_vlan)
2238 fcb_len = GMAC_FCB_LEN;
2239
f0ee7acf 2240 /* check if time stamp should be generated */
0d0cffdc
CM		 2241 if (unlikely(do_tstamp))
2242 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
4669bc90 2243
5b28beaf 2244 /* make space for additional header when fcb is needed */
0d0cffdc 2245 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
54dc79fe
SH		 2246 struct sk_buff *skb_new;
2247
0d0cffdc 2248 skb_new = skb_realloc_headroom(skb, fcb_len);
54dc79fe
SH		 2249 if (!skb_new) {
2250 dev->stats.tx_errors++;
c9974ad4 2251 dev_kfree_skb_any(skb);
54dc79fe
SH		 2252 return NETDEV_TX_OK;
2253 }
db83d136 2254
313b037c
ED		 2255 if (skb->sk)
2256 skb_set_owner_w(skb_new, skb->sk);
c9974ad4 2257 dev_consume_skb_any(skb);
54dc79fe
SH		 2258 skb = skb_new;
2259 }
2260
4669bc90
DH		 2261 /* total number of fragments in the SKB */
2262 nr_frags = skb_shinfo(skb)->nr_frags;
2263
f0ee7acf
MR		 2264 /* calculate the required number of TxBDs for this skb */
2265 if (unlikely(do_tstamp))
2266 nr_txbds = nr_frags + 2;
2267 else
2268 nr_txbds = nr_frags + 1;
2269
4669bc90 2270 /* check if there is space to queue this packet */
f0ee7acf 2271 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2272 /* no space, stop the queue */
fba4ed03 2273 netif_tx_stop_queue(txq);
4669bc90 2274 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2275 return NETDEV_TX_BUSY;
2276 }
1da177e4
LT		 2277
2278 /* Update transmit stats */
50ad076b
CM		 2279 bytes_sent = skb->len;
2280 tx_queue->stats.tx_bytes += bytes_sent;
2281 /* keep Tx bytes on wire for BQL accounting */
2282 GFAR_CB(skb)->bytes_sent = bytes_sent;
1ac9ad13 2283 tx_queue->stats.tx_packets++;
1da177e4 2284
a12f801d 2285 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2286 lstatus = txbdp->lstatus;
2287
2288 /* Time stamp insertion requires one additional TxBD */
2289 if (unlikely(do_tstamp))
2290 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
bc4598bc 2291 tx_queue->tx_ring_size);
1da177e4 2292
4669bc90 2293 if (nr_frags == 0) {
f0ee7acf
MR		 2294 if (unlikely(do_tstamp))
2295 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
bc4598bc 2296 TXBD_INTERRUPT);
f0ee7acf
MR		 2297 else
2298 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2299 } else {
2300 /* Place the fragment addresses and lengths into the TxBDs */
2301 for (i = 0; i < nr_frags; i++) {
50ad076b 2302 unsigned int frag_len;
4669bc90 2303 /* Point at the next BD, wrapping as needed */
a12f801d 2304 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90 2305
50ad076b 2306 frag_len = skb_shinfo(skb)->frags[i].size;
4669bc90 2307
50ad076b 2308 lstatus = txbdp->lstatus | frag_len |
bc4598bc 2309 BD_LFLAG(TXBD_READY);
4669bc90
DH		 2310
2311 /* Handle the last BD specially */
2312 if (i == nr_frags - 1)
2313 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2314
369ec162 2315 bufaddr = skb_frag_dma_map(priv->dev,
2234a722
IC		 2316 &skb_shinfo(skb)->frags[i],
2317 0,
50ad076b 2318 frag_len,
2234a722 2319 DMA_TO_DEVICE);
0a4b5a24
KH		 2320 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2321 goto dma_map_err;
4669bc90
DH		 2322
2323 /* set the TxBD length and buffer pointer */
2324 txbdp->bufPtr = bufaddr;
2325 txbdp->lstatus = lstatus;
2326 }
2327
2328 lstatus = txbdp_start->lstatus;
2329 }
1da177e4 2330
9c4886e5
MR		 2331 /* Add TxPAL between FCB and frame if required */
2332 if (unlikely(do_tstamp)) {
2333 skb_push(skb, GMAC_TXPAL_LEN);
2334 memset(skb->data, 0, GMAC_TXPAL_LEN);
2335 }
2336
0d0cffdc
CM		 2337 /* Add TxFCB if required */
2338 if (fcb_len) {
54dc79fe 2339 fcb = gfar_add_fcb(skb);
02d88fb4 2340 lstatus |= BD_LFLAG(TXBD_TOE);
0d0cffdc
CM		 2341 }
2342
2343 /* Set up checksumming */
2344 if (do_csum) {
2345 gfar_tx_checksum(skb, fcb, fcb_len);
02d88fb4
CM		 2346
2347 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2348 unlikely(gfar_csum_errata_76(priv, skb->len))) {
4363c2fd
AD		 2349 __skb_pull(skb, GMAC_FCB_LEN);
2350 skb_checksum_help(skb);
0d0cffdc
CM		 2351 if (do_vlan || do_tstamp) {
2352 /* put back a new fcb for vlan/tstamp TOE */
2353 fcb = gfar_add_fcb(skb);
2354 } else {
2355 /* Tx TOE not used */
2356 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2357 fcb = NULL;
2358 }
4363c2fd 2359 }
0bbaf069
KG		 2360 }
2361
0d0cffdc 2362 if (do_vlan)
54dc79fe 2363 gfar_tx_vlan(skb, fcb);
0bbaf069 2364
f0ee7acf
MR		 2365 /* Setup tx hardware time stamping if requested */
2366 if (unlikely(do_tstamp)) {
2244d07b 2367 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf 2368 fcb->ptp = 1;
f0ee7acf
MR		 2369 }
2370
0a4b5a24
KH		 2371 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2372 DMA_TO_DEVICE);
2373 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2374 goto dma_map_err;
2375
2376 txbdp_start->bufPtr = bufaddr;
1da177e4 2377
0977f817 2378 /* If time stamping is requested one additional TxBD must be set up. The
f0ee7acf
MR		 2379 * first TxBD points to the FCB and must have a data length of
2380 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2381 * the full frame length.
2382 */
2383 if (unlikely(do_tstamp)) {
0d0cffdc 2384 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
f0ee7acf 2385 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
0d0cffdc 2386 (skb_headlen(skb) - fcb_len);
f0ee7acf
MR		 2387 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2388 } else {
2389 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2390 }
1da177e4 2391
50ad076b 2392 netdev_tx_sent_queue(txq, bytes_sent);
d8a0f1b0 2393
0977f817 2394 /* We can work in parallel with gfar_clean_tx_ring(), except
a3bc1f11
AV		 2395 * when modifying num_txbdfree. Note that we didn't grab the lock
2396 * when we were reading the num_txbdfree and checking for available
2397 * space, that's because outside of this function it can only grow,
2398 * and once we've got needed space, it cannot suddenly disappear.
2399 *
2400 * The lock also protects us from gfar_error(), which can modify
2401 * regs->tstat and thus retrigger the transfers, which is why we
2402 * also must grab the lock before setting ready bit for the first
2403 * to be transmitted BD.
2404 */
2405 spin_lock_irqsave(&tx_queue->txlock, flags);
2406
d55398ba 2407 gfar_wmb();
7f7f5316 2408
4669bc90
DH		 2409 txbdp_start->lstatus = lstatus;
2410
d55398ba 2411 gfar_wmb(); /* force lstatus write before tx_skbuff */
0eddba52
AV		 2412
2413 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2414
4669bc90 2415 /* Update the current skb pointer to the next entry we will use
0977f817
JC		 2416 * (wrapping if necessary)
2417 */
a12f801d 2418 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
bc4598bc 2419 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2420
a12f801d 2421 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2422
2423 /* reduce TxBD free count */
f0ee7acf 2424 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2425
2426 /* If the next BD still needs to be cleaned up, then the bds
0977f817
JC		 2427 * are full. We need to tell the kernel to stop sending us stuff.
2428 */
a12f801d 2429 if (!tx_queue->num_txbdfree) {
fba4ed03 2430 netif_tx_stop_queue(txq);
1da177e4 2431
09f75cd7 2432 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2433 }
2434
1da177e4 2435 /* Tell the DMA to go go go */
fba4ed03 2436 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2437
2438 /* Unlock priv */
a12f801d 2439 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2440
54dc79fe 2441 return NETDEV_TX_OK;
0a4b5a24
KH		 2442
2443dma_map_err:
2444 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2445 if (do_tstamp)
2446 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2447 for (i = 0; i < nr_frags; i++) {
2448 lstatus = txbdp->lstatus;
2449 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2450 break;
2451
2452 txbdp->lstatus = lstatus & ~BD_LFLAG(TXBD_READY);
2453 bufaddr = txbdp->bufPtr;
2454 dma_unmap_page(priv->dev, bufaddr, txbdp->length,
2455 DMA_TO_DEVICE);
2456 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2457 }
2458 gfar_wmb();
2459 dev_kfree_skb_any(skb);
2460 return NETDEV_TX_OK;
1da177e4
LT		 2461}
2462
2463/* Stops the kernel queue, and halts the controller */
2464static int gfar_close(struct net_device *dev)
2465{
2466 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2467
ab939905 2468 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2469 stop_gfar(dev);
2470
bb40dcbb
AF		 2471 /* Disconnect from the PHY */
2472 phy_disconnect(priv->phydev);
2473 priv->phydev = NULL;
1da177e4 2474
80ec396c
CM		 2475 gfar_free_irq(priv);
2476
1da177e4
LT		 2477 return 0;
2478}
2479
1da177e4 2480/* Changes the mac address if the controller is not running. */
f162b9d5 2481static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2482{
7f7f5316 2483 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2484
2485 return 0;
2486}
2487
1da177e4
LT		 2488static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2489{
1da177e4 2490 struct gfar_private *priv = netdev_priv(dev);
0bbaf069
KG		 2491 int frame_size = new_mtu + ETH_HLEN;
2492
1da177e4 2493 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
59deab26 2494 netif_err(priv, drv, dev, "Invalid MTU setting\n");
1da177e4
LT		 2495 return -EINVAL;
2496 }
2497
0851133b
CM		 2498 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2499 cpu_relax();
2500
88302648 2501 if (dev->flags & IFF_UP)
1da177e4
LT		 2502 stop_gfar(dev);
2503
1da177e4
LT		 2504 dev->mtu = new_mtu;
2505
88302648 2506 if (dev->flags & IFF_UP)
1da177e4
LT		 2507 startup_gfar(dev);
2508
0851133b
CM		 2509 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2510
1da177e4
LT		 2511 return 0;
2512}
2513
0851133b
CM		 2514void reset_gfar(struct net_device *ndev)
2515{
2516 struct gfar_private *priv = netdev_priv(ndev);
2517
2518 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2519 cpu_relax();
2520
2521 stop_gfar(ndev);
2522 startup_gfar(ndev);
2523
2524 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2525}
2526
ab939905 2527/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2528 * transmitted after a set amount of time.
2529 * For now, assume that clearing out all the structures, and
ab939905
SS		 2530 * starting over will fix the problem.
2531 */
2532static void gfar_reset_task(struct work_struct *work)
1da177e4 2533{
ab939905 2534 struct gfar_private *priv = container_of(work, struct gfar_private,
bc4598bc 2535 reset_task);
0851133b 2536 reset_gfar(priv->ndev);
1da177e4
LT		 2537}
2538
ab939905
SS		 2539static void gfar_timeout(struct net_device *dev)
2540{
2541 struct gfar_private *priv = netdev_priv(dev);
2542
2543 dev->stats.tx_errors++;
2544 schedule_work(&priv->reset_task);
2545}
2546
acbc0f03
EL		 2547static void gfar_align_skb(struct sk_buff *skb)
2548{
2549 /* We need the data buffer to be aligned properly. We will reserve
2550 * as many bytes as needed to align the data properly
2551 */
2552 skb_reserve(skb, RXBUF_ALIGNMENT -
bc4598bc 2553 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
acbc0f03
EL		 2554}
2555
1da177e4 2556/* Interrupt Handler for Transmit complete */
c233cf40 2557static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2558{
a12f801d 2559 struct net_device *dev = tx_queue->dev;
d8a0f1b0 2560 struct netdev_queue *txq;
d080cd63 2561 struct gfar_private *priv = netdev_priv(dev);
f0ee7acf 2562 struct txbd8 *bdp, *next = NULL;
4669bc90 2563 struct txbd8 *lbdp = NULL;
a12f801d 2564 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2565 struct sk_buff *skb;
2566 int skb_dirtytx;
a12f801d 2567 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2568 int frags = 0, nr_txbds = 0;
4669bc90 2569 int i;
d080cd63 2570 int howmany = 0;
d8a0f1b0
PG		 2571 int tqi = tx_queue->qindex;
2572 unsigned int bytes_sent = 0;
4669bc90 2573 u32 lstatus;
f0ee7acf 2574 size_t buflen;
1da177e4 2575
d8a0f1b0 2576 txq = netdev_get_tx_queue(dev, tqi);
a12f801d
SG		 2577 bdp = tx_queue->dirty_tx;
2578 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2579
a12f801d 2580 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2581 unsigned long flags;
2582
4669bc90 2583 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf 2584
0977f817 2585 /* When time stamping, one additional TxBD must be freed.
f0ee7acf
MR		 2586 * Also, we need to dma_unmap_single() the TxPAL.
2587 */
2244d07b 2588 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2589 nr_txbds = frags + 2;
2590 else
2591 nr_txbds = frags + 1;
2592
2593 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2594
4669bc90 2595 lstatus = lbdp->lstatus;
1da177e4 2596
4669bc90
DH		 2597 /* Only clean completed frames */
2598 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
bc4598bc 2599 (lstatus & BD_LENGTH_MASK))
4669bc90
DH		 2600 break;
2601
2244d07b 2602 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf 2603 next = next_txbd(bdp, base, tx_ring_size);
9c4886e5 2604 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
f0ee7acf
MR		 2605 } else
2606 buflen = bdp->length;
2607
369ec162 2608 dma_unmap_single(priv->dev, bdp->bufPtr,
bc4598bc 2609 buflen, DMA_TO_DEVICE);
f0ee7acf 2610
2244d07b 2611 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2612 struct skb_shared_hwtstamps shhwtstamps;
2613 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
bc4598bc 2614
f0ee7acf
MR		 2615 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2616 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
9c4886e5 2617 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
f0ee7acf
MR		 2618 skb_tstamp_tx(skb, &shhwtstamps);
2619 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2620 bdp = next;
2621 }
81183059 2622
4669bc90
DH		 2623 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2624 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2625
4669bc90 2626 for (i = 0; i < frags; i++) {
369ec162 2627 dma_unmap_page(priv->dev, bdp->bufPtr,
bc4598bc 2628 bdp->length, DMA_TO_DEVICE);
4669bc90
DH		 2629 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2630 bdp = next_txbd(bdp, base, tx_ring_size);
2631 }
1da177e4 2632
50ad076b 2633 bytes_sent += GFAR_CB(skb)->bytes_sent;
d8a0f1b0 2634
acb600de 2635 dev_kfree_skb_any(skb);
0fd56bb5 2636
a12f801d 2637 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2638
4669bc90 2639 skb_dirtytx = (skb_dirtytx + 1) &
bc4598bc 2640 TX_RING_MOD_MASK(tx_ring_size);
4669bc90
DH		 2641
2642 howmany++;
a3bc1f11 2643 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2644 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2645 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2646 }
1da177e4 2647
4669bc90 2648 /* If we freed a buffer, we can restart transmission, if necessary */
0851133b
CM		 2649 if (tx_queue->num_txbdfree &&
2650 netif_tx_queue_stopped(txq) &&
2651 !(test_bit(GFAR_DOWN, &priv->state)))
2652 netif_wake_subqueue(priv->ndev, tqi);
1da177e4 2653
4669bc90 2654 /* Update dirty indicators */
a12f801d
SG		 2655 tx_queue->skb_dirtytx = skb_dirtytx;
2656 tx_queue->dirty_tx = bdp;
1da177e4 2657
d8a0f1b0 2658 netdev_tx_completed_queue(txq, howmany, bytes_sent);
d080cd63
DH		 2659}
2660
2281a0f3 2661static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2662{
2663 struct gfar_private *priv = netdev_priv(dev);
acb600de 2664 struct sk_buff *skb;
1da177e4 2665
acbc0f03 2666 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2667 if (!skb)
1da177e4
LT		 2668 return NULL;
2669
acbc0f03 2670 gfar_align_skb(skb);
7f7f5316 2671
acbc0f03
EL		 2672 return skb;
2673}
2674
91c53f76 2675static struct sk_buff *gfar_new_skb(struct net_device *dev, dma_addr_t *bufaddr)
acbc0f03 2676{
0a4b5a24
KH		 2677 struct gfar_private *priv = netdev_priv(dev);
2678 struct sk_buff *skb;
2679 dma_addr_t addr;
2680
2681 skb = gfar_alloc_skb(dev);
2682 if (!skb)
2683 return NULL;
2684
2685 addr = dma_map_single(priv->dev, skb->data,
2686 priv->rx_buffer_size, DMA_FROM_DEVICE);
2687 if (unlikely(dma_mapping_error(priv->dev, addr))) {
2688 dev_kfree_skb_any(skb);
2689 return NULL;
2690 }
2691
2692 *bufaddr = addr;
2693 return skb;
1da177e4
LT		 2694}
2695
298e1a9e 2696static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2697{
298e1a9e 2698 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2699 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2700 struct gfar_extra_stats *estats = &priv->extra_stats;
2701
0977f817 2702 /* If the packet was truncated, none of the other errors matter */
1da177e4
LT		 2703 if (status & RXBD_TRUNCATED) {
2704 stats->rx_length_errors++;
2705
212079df 2706 atomic64_inc(&estats->rx_trunc);
1da177e4
LT		 2707
2708 return;
2709 }
2710 /* Count the errors, if there were any */
2711 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2712 stats->rx_length_errors++;
2713
2714 if (status & RXBD_LARGE)
212079df 2715 atomic64_inc(&estats->rx_large);
1da177e4 2716 else
212079df 2717 atomic64_inc(&estats->rx_short);
1da177e4
LT		 2718 }
2719 if (status & RXBD_NONOCTET) {
2720 stats->rx_frame_errors++;
212079df 2721 atomic64_inc(&estats->rx_nonoctet);
1da177e4
LT		 2722 }
2723 if (status & RXBD_CRCERR) {
212079df 2724 atomic64_inc(&estats->rx_crcerr);
1da177e4
LT		 2725 stats->rx_crc_errors++;
2726 }
2727 if (status & RXBD_OVERRUN) {
212079df 2728 atomic64_inc(&estats->rx_overrun);
1da177e4
LT		 2729 stats->rx_crc_errors++;
2730 }
2731}
2732
f4983704 2733irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2734{
aeb12c5e
CM		 2735 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2736 unsigned long flags;
2737 u32 imask;
2738
2739 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2740 spin_lock_irqsave(&grp->grplock, flags);
2741 imask = gfar_read(&grp->regs->imask);
2742 imask &= IMASK_RX_DISABLED;
2743 gfar_write(&grp->regs->imask, imask);
2744 spin_unlock_irqrestore(&grp->grplock, flags);
2745 __napi_schedule(&grp->napi_rx);
2746 } else {
2747 /* Clear IEVENT, so interrupts aren't called again
2748 * because of the packets that have already arrived.
2749 */
2750 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2751 }
2752
2753 return IRQ_HANDLED;
2754}
2755
2756/* Interrupt Handler for Transmit complete */
2757static irqreturn_t gfar_transmit(int irq, void *grp_id)
2758{
2759 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2760 unsigned long flags;
2761 u32 imask;
2762
2763 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2764 spin_lock_irqsave(&grp->grplock, flags);
2765 imask = gfar_read(&grp->regs->imask);
2766 imask &= IMASK_TX_DISABLED;
2767 gfar_write(&grp->regs->imask, imask);
2768 spin_unlock_irqrestore(&grp->grplock, flags);
2769 __napi_schedule(&grp->napi_tx);
2770 } else {
2771 /* Clear IEVENT, so interrupts aren't called again
2772 * because of the packets that have already arrived.
2773 */
2774 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2775 }
2776
1da177e4
LT		 2777 return IRQ_HANDLED;
2778}
2779
0bbaf069
KG		 2780static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2781{
2782 /* If valid headers were found, and valid sums
2783 * were verified, then we tell the kernel that no
0977f817
JC		 2784 * checksumming is necessary. Otherwise, it is [FIXME]
2785 */
7f7f5316 2786 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2787 skb->ip_summed = CHECKSUM_UNNECESSARY;
2788 else
bc8acf2c 2789 skb_checksum_none_assert(skb);
0bbaf069
KG		 2790}
2791
2792
0977f817 2793/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
61db26c6
CM		 2794static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2795 int amount_pull, struct napi_struct *napi)
1da177e4
LT		 2796{
2797 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2798 struct rxfcb *fcb = NULL;
1da177e4 2799
2c2db48a
DH		 2800 /* fcb is at the beginning if exists */
2801 fcb = (struct rxfcb *)skb->data;
0bbaf069 2802
0977f817
JC		 2803 /* Remove the FCB from the skb
2804 * Remove the padded bytes, if there are any
2805 */
f74dac08
SG		 2806 if (amount_pull) {
2807 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2808 skb_pull(skb, amount_pull);
f74dac08 2809 }
0bbaf069 2810
cc772ab7
MR		 2811 /* Get receive timestamp from the skb */
2812 if (priv->hwts_rx_en) {
2813 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2814 u64 *ns = (u64 *) skb->data;
bc4598bc 2815
cc772ab7
MR		 2816 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2817 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2818 }
2819
2820 if (priv->padding)
2821 skb_pull(skb, priv->padding);
2822
8b3afe95 2823 if (dev->features & NETIF_F_RXCSUM)
2c2db48a 2824 gfar_rx_checksum(skb, fcb);
0bbaf069 2825
2c2db48a
DH		 2826 /* Tell the skb what kind of packet this is */
2827 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2828
f646968f 2829 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
32f7fd44
JP		 2830 * Even if vlan rx accel is disabled, on some chips
2831 * RXFCB_VLN is pseudo randomly set.
2832 */
f646968f 2833 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
32f7fd44 2834 fcb->flags & RXFCB_VLN)
e5905c83 2835 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
87c288c6 2836
2c2db48a 2837 /* Send the packet up the stack */
953d2768 2838 napi_gro_receive(napi, skb);
0bbaf069 2839
1da177e4
LT		 2840}
2841
2842/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2281a0f3
JC		 2843 * until the budget/quota has been reached. Returns the number
2844 * of frames handled
1da177e4 2845 */
a12f801d 2846int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2847{
a12f801d 2848 struct net_device *dev = rx_queue->dev;
31de198b 2849 struct rxbd8 *bdp, *base;
1da177e4 2850 struct sk_buff *skb;
2c2db48a
DH		 2851 int pkt_len;
2852 int amount_pull;
1da177e4
LT		 2853 int howmany = 0;
2854 struct gfar_private *priv = netdev_priv(dev);
2855
2856 /* Get the first full descriptor */
a12f801d
SG		 2857 bdp = rx_queue->cur_rx;
2858 base = rx_queue->rx_bd_base;
1da177e4 2859
ba779711 2860 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2c2db48a 2861
1da177e4 2862 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2863 struct sk_buff *newskb;
0a4b5a24 2864 dma_addr_t bufaddr;
bc4598bc 2865
3b6330ce 2866 rmb();
815b97c6
AF		 2867
2868 /* Add another skb for the future */
0a4b5a24 2869 newskb = gfar_new_skb(dev, &bufaddr);
815b97c6 2870
a12f801d 2871 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2872
369ec162 2873 dma_unmap_single(priv->dev, bdp->bufPtr,
bc4598bc 2874 priv->rx_buffer_size, DMA_FROM_DEVICE);
81183059 2875
63b88b90 2876 if (unlikely(!(bdp->status & RXBD_ERR) &&
bc4598bc 2877 bdp->length > priv->rx_buffer_size))
63b88b90
AV		 2878 bdp->status = RXBD_LARGE;
2879
815b97c6
AF		 2880 /* We drop the frame if we failed to allocate a new buffer */
2881 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
bc4598bc 2882 bdp->status & RXBD_ERR)) {
815b97c6
AF		 2883 count_errors(bdp->status, dev);
2884
0a4b5a24 2885 if (unlikely(!newskb)) {
815b97c6 2886 newskb = skb;
0a4b5a24
KH		 2887 bufaddr = bdp->bufPtr;
2888 } else if (skb)
acb600de 2889 dev_kfree_skb(skb);
815b97c6 2890 } else {
1da177e4 2891 /* Increment the number of packets */
a7f38041 2892 rx_queue->stats.rx_packets++;
1da177e4
LT		 2893 howmany++;
2894
2c2db48a
DH		 2895 if (likely(skb)) {
2896 pkt_len = bdp->length - ETH_FCS_LEN;
2897 /* Remove the FCS from the packet length */
2898 skb_put(skb, pkt_len);
a7f38041 2899 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2900 skb_record_rx_queue(skb, rx_queue->qindex);
cd754a57 2901 gfar_process_frame(dev, skb, amount_pull,
aeb12c5e 2902 &rx_queue->grp->napi_rx);
2c2db48a
DH		 2903
2904 } else {
59deab26 2905 netif_warn(priv, rx_err, dev, "Missing skb!\n");
a7f38041 2906 rx_queue->stats.rx_dropped++;
212079df 2907 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2c2db48a 2908 }
1da177e4 2909
1da177e4
LT		 2910 }
2911
a12f801d 2912 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2913
815b97c6 2914 /* Setup the new bdp */
0a4b5a24 2915 gfar_init_rxbdp(rx_queue, bdp, bufaddr);
1da177e4 2916
45b679c9
MP		 2917 /* Update Last Free RxBD pointer for LFC */
2918 if (unlikely(rx_queue->rfbptr && priv->tx_actual_en))
2919 gfar_write(rx_queue->rfbptr, (u32)bdp);
2920
1da177e4 2921 /* Update to the next pointer */
a12f801d 2922 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2923
2924 /* update to point at the next skb */
bc4598bc
JC		 2925 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2926 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2927 }
2928
2929 /* Update the current rxbd pointer to be the next one */
a12f801d 2930 rx_queue->cur_rx = bdp;
1da177e4 2931
1da177e4
LT		 2932 return howmany;
2933}
2934
aeb12c5e 2935static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
5eaedf31
CM		 2936{
2937 struct gfar_priv_grp *gfargrp =
aeb12c5e 2938 container_of(napi, struct gfar_priv_grp, napi_rx);
5eaedf31 2939 struct gfar __iomem *regs = gfargrp->regs;
71ff9e3d 2940 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
5eaedf31
CM		 2941 int work_done = 0;
2942
2943 /* Clear IEVENT, so interrupts aren't called again
2944 * because of the packets that have already arrived
2945 */
aeb12c5e 2946 gfar_write(&regs->ievent, IEVENT_RX_MASK);
5eaedf31
CM		 2947
2948 work_done = gfar_clean_rx_ring(rx_queue, budget);
2949
2950 if (work_done < budget) {
aeb12c5e 2951 u32 imask;
5eaedf31
CM		 2952 napi_complete(napi);
2953 /* Clear the halt bit in RSTAT */
2954 gfar_write(&regs->rstat, gfargrp->rstat);
2955
aeb12c5e
CM		 2956 spin_lock_irq(&gfargrp->grplock);
2957 imask = gfar_read(&regs->imask);
2958 imask |= IMASK_RX_DEFAULT;
2959 gfar_write(&regs->imask, imask);
2960 spin_unlock_irq(&gfargrp->grplock);
5eaedf31
CM		 2961 }
2962
2963 return work_done;
2964}
2965
aeb12c5e 2966static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
1da177e4 2967{
bc4598bc 2968 struct gfar_priv_grp *gfargrp =
aeb12c5e
CM		 2969 container_of(napi, struct gfar_priv_grp, napi_tx);
2970 struct gfar __iomem *regs = gfargrp->regs;
71ff9e3d 2971 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
aeb12c5e
CM		 2972 u32 imask;
2973
2974 /* Clear IEVENT, so interrupts aren't called again
2975 * because of the packets that have already arrived
2976 */
2977 gfar_write(&regs->ievent, IEVENT_TX_MASK);
2978
2979 /* run Tx cleanup to completion */
2980 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2981 gfar_clean_tx_ring(tx_queue);
2982
2983 napi_complete(napi);
2984
2985 spin_lock_irq(&gfargrp->grplock);
2986 imask = gfar_read(&regs->imask);
2987 imask |= IMASK_TX_DEFAULT;
2988 gfar_write(&regs->imask, imask);
2989 spin_unlock_irq(&gfargrp->grplock);
2990
2991 return 0;
2992}
2993
2994static int gfar_poll_rx(struct napi_struct *napi, int budget)
2995{
2996 struct gfar_priv_grp *gfargrp =
2997 container_of(napi, struct gfar_priv_grp, napi_rx);
fba4ed03 2998 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2999 struct gfar __iomem *regs = gfargrp->regs;
fba4ed03 3000 struct gfar_priv_rx_q *rx_queue = NULL;
c233cf40 3001 int work_done = 0, work_done_per_q = 0;
39c0a0d5 3002 int i, budget_per_q = 0;
6be5ed3f
CM		 3003 unsigned long rstat_rxf;
3004 int num_act_queues;
fba4ed03 3005
8c7396ae 3006 /* Clear IEVENT, so interrupts aren't called again
0977f817
JC		 3007 * because of the packets that have already arrived
3008 */
aeb12c5e 3009 gfar_write(&regs->ievent, IEVENT_RX_MASK);
8c7396ae 3010
6be5ed3f
CM		 3011 rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3012
3013 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3014 if (num_act_queues)
3015 budget_per_q = budget/num_act_queues;
3016
3ba405db
CM		 3017 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3018 /* skip queue if not active */
3019 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3020 continue;
1da177e4 3021
3ba405db
CM		 3022 rx_queue = priv->rx_queue[i];
3023 work_done_per_q =
3024 gfar_clean_rx_ring(rx_queue, budget_per_q);
3025 work_done += work_done_per_q;
3026
3027 /* finished processing this queue */
3028 if (work_done_per_q < budget_per_q) {
3029 /* clear active queue hw indication */
3030 gfar_write(&regs->rstat,
3031 RSTAT_CLEAR_RXF0 >> i);
3032 num_act_queues--;
3033
3034 if (!num_act_queues)
3035 break;
3036 }
3037 }
42199884 3038
aeb12c5e
CM		 3039 if (!num_act_queues) {
3040 u32 imask;
3ba405db 3041 napi_complete(napi);
1da177e4 3042
3ba405db
CM		 3043 /* Clear the halt bit in RSTAT */
3044 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 3045
aeb12c5e
CM		 3046 spin_lock_irq(&gfargrp->grplock);
3047 imask = gfar_read(&regs->imask);
3048 imask |= IMASK_RX_DEFAULT;
3049 gfar_write(&regs->imask, imask);
3050 spin_unlock_irq(&gfargrp->grplock);
1da177e4
LT		 3051 }
3052
c233cf40 3053 return work_done;
1da177e4 3054}
1da177e4 3055
aeb12c5e
CM		 3056static int gfar_poll_tx(struct napi_struct *napi, int budget)
3057{
3058 struct gfar_priv_grp *gfargrp =
3059 container_of(napi, struct gfar_priv_grp, napi_tx);
3060 struct gfar_private *priv = gfargrp->priv;
3061 struct gfar __iomem *regs = gfargrp->regs;
3062 struct gfar_priv_tx_q *tx_queue = NULL;
3063 int has_tx_work = 0;
3064 int i;
3065
3066 /* Clear IEVENT, so interrupts aren't called again
3067 * because of the packets that have already arrived
3068 */
3069 gfar_write(&regs->ievent, IEVENT_TX_MASK);
3070
3071 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3072 tx_queue = priv->tx_queue[i];
3073 /* run Tx cleanup to completion */
3074 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3075 gfar_clean_tx_ring(tx_queue);
3076 has_tx_work = 1;
3077 }
3078 }
3079
3080 if (!has_tx_work) {
3081 u32 imask;
3082 napi_complete(napi);
3083
3084 spin_lock_irq(&gfargrp->grplock);
3085 imask = gfar_read(&regs->imask);
3086 imask |= IMASK_TX_DEFAULT;
3087 gfar_write(&regs->imask, imask);
3088 spin_unlock_irq(&gfargrp->grplock);
3089 }
3090
3091 return 0;
3092}
3093
3094
f2d71c2d 3095#ifdef CONFIG_NET_POLL_CONTROLLER
0977f817 3096/* Polling 'interrupt' - used by things like netconsole to send skbs
f2d71c2d
VW		 3097 * without having to re-enable interrupts. It's not called while
3098 * the interrupt routine is executing.
3099 */
3100static void gfar_netpoll(struct net_device *dev)
3101{
3102 struct gfar_private *priv = netdev_priv(dev);
3a2e16c8 3103 int i;
f2d71c2d
VW		 3104
3105 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 3106 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c 3107 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 3108 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3109
3110 disable_irq(gfar_irq(grp, TX)->irq);
3111 disable_irq(gfar_irq(grp, RX)->irq);
3112 disable_irq(gfar_irq(grp, ER)->irq);
3113 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3114 enable_irq(gfar_irq(grp, ER)->irq);
3115 enable_irq(gfar_irq(grp, RX)->irq);
3116 enable_irq(gfar_irq(grp, TX)->irq);
46ceb60c 3117 }
f2d71c2d 3118 } else {
46ceb60c 3119 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 3120 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3121
3122 disable_irq(gfar_irq(grp, TX)->irq);
3123 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3124 enable_irq(gfar_irq(grp, TX)->irq);
43de004b 3125 }
f2d71c2d
VW		 3126 }
3127}
3128#endif
3129
1da177e4 3130/* The interrupt handler for devices with one interrupt */
f4983704 3131static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 3132{
f4983704 3133 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 3134
3135 /* Save ievent for future reference */
f4983704 3136 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 3137
1da177e4 3138 /* Check for reception */
538cc7ee 3139 if (events & IEVENT_RX_MASK)
f4983704 3140 gfar_receive(irq, grp_id);
1da177e4
LT		 3141
3142 /* Check for transmit completion */
538cc7ee 3143 if (events & IEVENT_TX_MASK)
f4983704 3144 gfar_transmit(irq, grp_id);
1da177e4 3145
538cc7ee
SS		 3146 /* Check for errors */
3147 if (events & IEVENT_ERR_MASK)
f4983704 3148 gfar_error(irq, grp_id);
1da177e4
LT		 3149
3150 return IRQ_HANDLED;
3151}
3152
1da177e4
LT		 3153/* Called every time the controller might need to be made
3154 * aware of new link state. The PHY code conveys this
bb40dcbb 3155 * information through variables in the phydev structure, and this
1da177e4
LT		 3156 * function converts those variables into the appropriate
3157 * register values, and can bring down the device if needed.
3158 */
3159static void adjust_link(struct net_device *dev)
3160{
3161 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 3162 struct phy_device *phydev = priv->phydev;
bb40dcbb 3163
6ce29b0e
CM		 3164 if (unlikely(phydev->link != priv->oldlink ||
3165 phydev->duplex != priv->oldduplex ||
3166 phydev->speed != priv->oldspeed))
3167 gfar_update_link_state(priv);
bb40dcbb 3168}
1da177e4
LT		 3169
3170/* Update the hash table based on the current list of multicast
3171 * addresses we subscribe to. Also, change the promiscuity of
3172 * the device based on the flags (this function is called
0977f817
JC		 3173 * whenever dev->flags is changed
3174 */
1da177e4
LT		 3175static void gfar_set_multi(struct net_device *dev)
3176{
22bedad3 3177 struct netdev_hw_addr *ha;
1da177e4 3178 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3179 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3180 u32 tempval;
3181
a12f801d 3182 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3183 /* Set RCTRL to PROM */
3184 tempval = gfar_read(&regs->rctrl);
3185 tempval |= RCTRL_PROM;
3186 gfar_write(&regs->rctrl, tempval);
3187 } else {
3188 /* Set RCTRL to not PROM */
3189 tempval = gfar_read(&regs->rctrl);
3190 tempval &= ~(RCTRL_PROM);
3191 gfar_write(&regs->rctrl, tempval);
3192 }
6aa20a22 3193
a12f801d 3194 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3195 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3196 gfar_write(&regs->igaddr0, 0xffffffff);
3197 gfar_write(&regs->igaddr1, 0xffffffff);
3198 gfar_write(&regs->igaddr2, 0xffffffff);
3199 gfar_write(&regs->igaddr3, 0xffffffff);
3200 gfar_write(&regs->igaddr4, 0xffffffff);
3201 gfar_write(&regs->igaddr5, 0xffffffff);
3202 gfar_write(&regs->igaddr6, 0xffffffff);
3203 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3204 gfar_write(&regs->gaddr0, 0xffffffff);
3205 gfar_write(&regs->gaddr1, 0xffffffff);
3206 gfar_write(&regs->gaddr2, 0xffffffff);
3207 gfar_write(&regs->gaddr3, 0xffffffff);
3208 gfar_write(&regs->gaddr4, 0xffffffff);
3209 gfar_write(&regs->gaddr5, 0xffffffff);
3210 gfar_write(&regs->gaddr6, 0xffffffff);
3211 gfar_write(&regs->gaddr7, 0xffffffff);
3212 } else {
7f7f5316
AF		 3213 int em_num;
3214 int idx;
3215
1da177e4 3216 /* zero out the hash */
0bbaf069
KG		 3217 gfar_write(&regs->igaddr0, 0x0);
3218 gfar_write(&regs->igaddr1, 0x0);
3219 gfar_write(&regs->igaddr2, 0x0);
3220 gfar_write(&regs->igaddr3, 0x0);
3221 gfar_write(&regs->igaddr4, 0x0);
3222 gfar_write(&regs->igaddr5, 0x0);
3223 gfar_write(&regs->igaddr6, 0x0);
3224 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3225 gfar_write(&regs->gaddr0, 0x0);
3226 gfar_write(&regs->gaddr1, 0x0);
3227 gfar_write(&regs->gaddr2, 0x0);
3228 gfar_write(&regs->gaddr3, 0x0);
3229 gfar_write(&regs->gaddr4, 0x0);
3230 gfar_write(&regs->gaddr5, 0x0);
3231 gfar_write(&regs->gaddr6, 0x0);
3232 gfar_write(&regs->gaddr7, 0x0);
3233
7f7f5316
AF		 3234 /* If we have extended hash tables, we need to
3235 * clear the exact match registers to prepare for
0977f817
JC		 3236 * setting them
3237 */
7f7f5316
AF		 3238 if (priv->extended_hash) {
3239 em_num = GFAR_EM_NUM + 1;
3240 gfar_clear_exact_match(dev);
3241 idx = 1;
3242 } else {
3243 idx = 0;
3244 em_num = 0;
3245 }
3246
4cd24eaf 3247 if (netdev_mc_empty(dev))
1da177e4
LT		 3248 return;
3249
3250 /* Parse the list, and set the appropriate bits */
22bedad3 3251 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3252 if (idx < em_num) {
22bedad3 3253 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3254 idx++;
3255 } else
22bedad3 3256 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3257 }
3258 }
1da177e4
LT		 3259}
3260
7f7f5316
AF		 3261
3262/* Clears each of the exact match registers to zero, so they
0977f817
JC		 3263 * don't interfere with normal reception
3264 */
7f7f5316
AF		 3265static void gfar_clear_exact_match(struct net_device *dev)
3266{
3267 int idx;
6a3c910c 3268 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
7f7f5316 3269
bc4598bc 3270 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
b6bc7650 3271 gfar_set_mac_for_addr(dev, idx, zero_arr);
7f7f5316
AF		 3272}
3273
1da177e4
LT		 3274/* Set the appropriate hash bit for the given addr */
3275/* The algorithm works like so:
3276 * 1) Take the Destination Address (ie the multicast address), and
3277 * do a CRC on it (little endian), and reverse the bits of the
3278 * result.
3279 * 2) Use the 8 most significant bits as a hash into a 256-entry
3280 * table. The table is controlled through 8 32-bit registers:
3281 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3282 * gaddr7. This means that the 3 most significant bits in the
3283 * hash index which gaddr register to use, and the 5 other bits
3284 * indicate which bit (assuming an IBM numbering scheme, which
3285 * for PowerPC (tm) is usually the case) in the register holds
0977f817
JC		 3286 * the entry.
3287 */
1da177e4
LT		 3288static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3289{
3290 u32 tempval;
3291 struct gfar_private *priv = netdev_priv(dev);
6a3c910c 3292 u32 result = ether_crc(ETH_ALEN, addr);
0bbaf069
KG		 3293 int width = priv->hash_width;
3294 u8 whichbit = (result >> (32 - width)) & 0x1f;
3295 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3296 u32 value = (1 << (31-whichbit));
3297
0bbaf069 3298 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3299 tempval |= value;
0bbaf069 3300 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3301}
3302
7f7f5316
AF		 3303
3304/* There are multiple MAC Address register pairs on some controllers
3305 * This function sets the numth pair to a given address
3306 */
b6bc7650
JP		 3307static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3308 const u8 *addr)
7f7f5316
AF		 3309{
3310 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3311 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316 3312 u32 tempval;
f4983704 3313 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3314
3315 macptr += num*2;
3316
83bfc3c4
CM		 3317 /* For a station address of 0x12345678ABCD in transmission
3318 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3319 * MACnADDR2 is set to 0x34120000.
0977f817 3320 */
83bfc3c4
CM		 3321 tempval = (addr[5] << 24) | (addr[4] << 16) |
3322 (addr[3] << 8) | addr[2];
7f7f5316 3323
83bfc3c4 3324 gfar_write(macptr, tempval);
7f7f5316 3325
83bfc3c4 3326 tempval = (addr[1] << 24) | (addr[0] << 16);
7f7f5316
AF		 3327
3328 gfar_write(macptr+1, tempval);
3329}
3330
1da177e4 3331/* GFAR error interrupt handler */
f4983704 3332static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3333{
f4983704
SG		 3334 struct gfar_priv_grp *gfargrp = grp_id;
3335 struct gfar __iomem *regs = gfargrp->regs;
3336 struct gfar_private *priv= gfargrp->priv;
3337 struct net_device *dev = priv->ndev;
1da177e4
LT		 3338
3339 /* Save ievent for future reference */
f4983704 3340 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3341
3342 /* Clear IEVENT */
f4983704 3343 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3344
3345 /* Magic Packet is not an error. */
b31a1d8b 3346 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3347 (events & IEVENT_MAG))
3348 events &= ~IEVENT_MAG;
1da177e4
LT		 3349
3350 /* Hmm... */
0bbaf069 3351 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
bc4598bc
JC		 3352 netdev_dbg(dev,
3353 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
59deab26 3354 events, gfar_read(&regs->imask));
1da177e4
LT		 3355
3356 /* Update the error counters */
3357 if (events & IEVENT_TXE) {
09f75cd7 3358 dev->stats.tx_errors++;
1da177e4
LT		 3359
3360 if (events & IEVENT_LC)
09f75cd7 3361 dev->stats.tx_window_errors++;
1da177e4 3362 if (events & IEVENT_CRL)
09f75cd7 3363 dev->stats.tx_aborted_errors++;
1da177e4 3364 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3365 unsigned long flags;
3366
59deab26
JP		 3367 netif_dbg(priv, tx_err, dev,
3368 "TX FIFO underrun, packet dropped\n");
09f75cd7 3369 dev->stats.tx_dropped++;
212079df 3370 atomic64_inc(&priv->extra_stats.tx_underrun);
1da177e4 3371
836cf7fa
AV		 3372 local_irq_save(flags);
3373 lock_tx_qs(priv);
3374
1da177e4 3375 /* Reactivate the Tx Queues */
fba4ed03 3376 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3377
3378 unlock_tx_qs(priv);
3379 local_irq_restore(flags);
1da177e4 3380 }
59deab26 3381 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
1da177e4
LT		 3382 }
3383 if (events & IEVENT_BSY) {
09f75cd7 3384 dev->stats.rx_errors++;
212079df 3385 atomic64_inc(&priv->extra_stats.rx_bsy);
1da177e4 3386
f4983704 3387 gfar_receive(irq, grp_id);
1da177e4 3388
59deab26
JP		 3389 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3390 gfar_read(&regs->rstat));
1da177e4
LT		 3391 }
3392 if (events & IEVENT_BABR) {
09f75cd7 3393 dev->stats.rx_errors++;
212079df 3394 atomic64_inc(&priv->extra_stats.rx_babr);
1da177e4 3395
59deab26 3396 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
1da177e4
LT		 3397 }
3398 if (events & IEVENT_EBERR) {
212079df 3399 atomic64_inc(&priv->extra_stats.eberr);
59deab26 3400 netif_dbg(priv, rx_err, dev, "bus error\n");
1da177e4 3401 }
59deab26
JP		 3402 if (events & IEVENT_RXC)
3403 netif_dbg(priv, rx_status, dev, "control frame\n");
1da177e4
LT		 3404
3405 if (events & IEVENT_BABT) {
212079df 3406 atomic64_inc(&priv->extra_stats.tx_babt);
59deab26 3407 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
1da177e4
LT		 3408 }
3409 return IRQ_HANDLED;
3410}
3411
6ce29b0e
CM		 3412static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3413{
3414 struct phy_device *phydev = priv->phydev;
3415 u32 val = 0;
3416
3417 if (!phydev->duplex)
3418 return val;
3419
3420 if (!priv->pause_aneg_en) {
3421 if (priv->tx_pause_en)
3422 val |= MACCFG1_TX_FLOW;
3423 if (priv->rx_pause_en)
3424 val |= MACCFG1_RX_FLOW;
3425 } else {
3426 u16 lcl_adv, rmt_adv;
3427 u8 flowctrl;
3428 /* get link partner capabilities */
3429 rmt_adv = 0;
3430 if (phydev->pause)
3431 rmt_adv = LPA_PAUSE_CAP;
3432 if (phydev->asym_pause)
3433 rmt_adv |= LPA_PAUSE_ASYM;
3434
43ef8d29
PMB		 3435 lcl_adv = 0;
3436 if (phydev->advertising & ADVERTISED_Pause)
3437 lcl_adv |= ADVERTISE_PAUSE_CAP;
3438 if (phydev->advertising & ADVERTISED_Asym_Pause)
3439 lcl_adv |= ADVERTISE_PAUSE_ASYM;
6ce29b0e
CM		 3440
3441 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3442 if (flowctrl & FLOW_CTRL_TX)
3443 val |= MACCFG1_TX_FLOW;
3444 if (flowctrl & FLOW_CTRL_RX)
3445 val |= MACCFG1_RX_FLOW;
3446 }
3447
3448 return val;
3449}
3450
3451static noinline void gfar_update_link_state(struct gfar_private *priv)
3452{
3453 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3454 struct phy_device *phydev = priv->phydev;
45b679c9
MP		 3455 struct gfar_priv_rx_q *rx_queue = NULL;
3456 int i;
3457 struct rxbd8 *bdp;
6ce29b0e
CM		 3458
3459 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3460 return;
3461
3462 if (phydev->link) {
3463 u32 tempval1 = gfar_read(&regs->maccfg1);
3464 u32 tempval = gfar_read(&regs->maccfg2);
3465 u32 ecntrl = gfar_read(&regs->ecntrl);
45b679c9 3466 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
6ce29b0e
CM		 3467
3468 if (phydev->duplex != priv->oldduplex) {
3469 if (!(phydev->duplex))
3470 tempval &= ~(MACCFG2_FULL_DUPLEX);
3471 else
3472 tempval |= MACCFG2_FULL_DUPLEX;
3473
3474 priv->oldduplex = phydev->duplex;
3475 }
3476
3477 if (phydev->speed != priv->oldspeed) {
3478 switch (phydev->speed) {
3479 case 1000:
3480 tempval =
3481 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3482
3483 ecntrl &= ~(ECNTRL_R100);
3484 break;
3485 case 100:
3486 case 10:
3487 tempval =
3488 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3489
3490 /* Reduced mode distinguishes
3491 * between 10 and 100
3492 */
3493 if (phydev->speed == SPEED_100)
3494 ecntrl |= ECNTRL_R100;
3495 else
3496 ecntrl &= ~(ECNTRL_R100);
3497 break;
3498 default:
3499 netif_warn(priv, link, priv->ndev,
3500 "Ack! Speed (%d) is not 10/100/1000!\n",
3501 phydev->speed);
3502 break;
3503 }
3504
3505 priv->oldspeed = phydev->speed;
3506 }
3507
3508 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3509 tempval1 |= gfar_get_flowctrl_cfg(priv);
3510
45b679c9
MP		 3511 /* Turn last free buffer recording on */
3512 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3513 for (i = 0; i < priv->num_rx_queues; i++) {
3514 rx_queue = priv->rx_queue[i];
3515 bdp = rx_queue->cur_rx;
3516 /* skip to previous bd */
3517 bdp = skip_bd(bdp, rx_queue->rx_ring_size - 1,
3518 rx_queue->rx_bd_base,
3519 rx_queue->rx_ring_size);
3520
3521 if (rx_queue->rfbptr)
3522 gfar_write(rx_queue->rfbptr, (u32)bdp);
3523 }
3524
3525 priv->tx_actual_en = 1;
3526 }
3527
3528 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3529 priv->tx_actual_en = 0;
3530
6ce29b0e
CM		 3531 gfar_write(&regs->maccfg1, tempval1);
3532 gfar_write(&regs->maccfg2, tempval);
3533 gfar_write(&regs->ecntrl, ecntrl);
3534
3535 if (!priv->oldlink)
3536 priv->oldlink = 1;
3537
3538 } else if (priv->oldlink) {
3539 priv->oldlink = 0;
3540 priv->oldspeed = 0;
3541 priv->oldduplex = -1;
3542 }
3543
3544 if (netif_msg_link(priv))
3545 phy_print_status(phydev);
3546}
3547
b31a1d8b
AF		 3548static struct of_device_id gfar_match[] =
3549{
3550 {
3551 .type = "network",
3552 .compatible = "gianfar",
3553 },
46ceb60c
SG		 3554 {
3555 .compatible = "fsl,etsec2",
3556 },
b31a1d8b
AF		 3557 {},
3558};
e72701ac 3559MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3560
1da177e4 3561/* Structure for a device driver */
74888760 3562static struct platform_driver gfar_driver = {
4018294b
GL		 3563 .driver = {
3564 .name = "fsl-gianfar",
4018294b
GL		 3565 .pm = GFAR_PM_OPS,
3566 .of_match_table = gfar_match,
3567 },
1da177e4
LT		 3568 .probe = gfar_probe,
3569 .remove = gfar_remove,
3570};
3571
db62f684 3572module_platform_driver(gfar_driver);
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