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Commit | Line | Data |
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0977f817 | 1 | /* drivers/net/ethernet/freescale/gianfar.c |
1da177e4 LT |
2 | * |
3 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
4 | * This driver is designed for the non-CPM ethernet controllers |
5 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
6 | * Based on 8260_io/fcc_enet.c |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
a12f801d | 10 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 11 | * |
6c43e046 | 12 | * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. |
a12f801d | 13 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
59deab26 JP |
64 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
65 | #define DEBUG | |
66 | ||
1da177e4 | 67 | #include <linux/kernel.h> |
1da177e4 LT |
68 | #include <linux/string.h> |
69 | #include <linux/errno.h> | |
bb40dcbb | 70 | #include <linux/unistd.h> |
1da177e4 LT |
71 | #include <linux/slab.h> |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/init.h> | |
74 | #include <linux/delay.h> | |
75 | #include <linux/netdevice.h> | |
76 | #include <linux/etherdevice.h> | |
77 | #include <linux/skbuff.h> | |
0bbaf069 | 78 | #include <linux/if_vlan.h> |
1da177e4 LT |
79 | #include <linux/spinlock.h> |
80 | #include <linux/mm.h> | |
fe192a49 | 81 | #include <linux/of_mdio.h> |
b31a1d8b | 82 | #include <linux/of_platform.h> |
0bbaf069 KG |
83 | #include <linux/ip.h> |
84 | #include <linux/tcp.h> | |
85 | #include <linux/udp.h> | |
9c07b884 | 86 | #include <linux/in.h> |
cc772ab7 | 87 | #include <linux/net_tstamp.h> |
1da177e4 LT |
88 | |
89 | #include <asm/io.h> | |
7d350977 | 90 | #include <asm/reg.h> |
1da177e4 LT |
91 | #include <asm/irq.h> |
92 | #include <asm/uaccess.h> | |
93 | #include <linux/module.h> | |
1da177e4 LT |
94 | #include <linux/dma-mapping.h> |
95 | #include <linux/crc32.h> | |
bb40dcbb AF |
96 | #include <linux/mii.h> |
97 | #include <linux/phy.h> | |
b31a1d8b AF |
98 | #include <linux/phy_fixed.h> |
99 | #include <linux/of.h> | |
4b6ba8aa | 100 | #include <linux/of_net.h> |
1da177e4 LT |
101 | |
102 | #include "gianfar.h" | |
1da177e4 LT |
103 | |
104 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 | 105 | |
7f7f5316 | 106 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 107 | |
1da177e4 LT |
108 | static int gfar_enet_open(struct net_device *dev); |
109 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 110 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
111 | static void gfar_timeout(struct net_device *dev); |
112 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 113 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 114 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 115 | struct sk_buff *skb); |
1da177e4 LT |
116 | static int gfar_set_mac_address(struct net_device *dev); |
117 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
118 | static irqreturn_t gfar_error(int irq, void *dev_id); |
119 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
120 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
121 | static void adjust_link(struct net_device *dev); |
122 | static void init_registers(struct net_device *dev); | |
123 | static int init_phy(struct net_device *dev); | |
74888760 | 124 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 125 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 126 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
127 | static void gfar_set_multi(struct net_device *dev); |
128 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 129 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 130 | static int gfar_poll(struct napi_struct *napi, int budget); |
5eaedf31 | 131 | static int gfar_poll_sq(struct napi_struct *napi, int budget); |
f2d71c2d VW |
132 | #ifdef CONFIG_NET_POLL_CONTROLLER |
133 | static void gfar_netpoll(struct net_device *dev); | |
134 | #endif | |
a12f801d | 135 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
c233cf40 | 136 | static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); |
61db26c6 CM |
137 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
138 | int amount_pull, struct napi_struct *napi); | |
7f7f5316 | 139 | void gfar_halt(struct net_device *dev); |
d87eb127 | 140 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
141 | void gfar_start(struct net_device *dev); |
142 | static void gfar_clear_exact_match(struct net_device *dev); | |
b6bc7650 JP |
143 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
144 | const u8 *addr); | |
26ccfc37 | 145 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 146 | |
1da177e4 LT |
147 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
148 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
149 | MODULE_LICENSE("GPL"); | |
150 | ||
a12f801d | 151 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
152 | dma_addr_t buf) |
153 | { | |
8a102fe0 AV |
154 | u32 lstatus; |
155 | ||
156 | bdp->bufPtr = buf; | |
157 | ||
158 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 159 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
160 | lstatus |= BD_LFLAG(RXBD_WRAP); |
161 | ||
162 | eieio(); | |
163 | ||
164 | bdp->lstatus = lstatus; | |
165 | } | |
166 | ||
8728327e | 167 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 168 | { |
8728327e | 169 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
170 | struct gfar_priv_tx_q *tx_queue = NULL; |
171 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
172 | struct txbd8 *txbdp; |
173 | struct rxbd8 *rxbdp; | |
fba4ed03 | 174 | int i, j; |
a12f801d | 175 | |
fba4ed03 SG |
176 | for (i = 0; i < priv->num_tx_queues; i++) { |
177 | tx_queue = priv->tx_queue[i]; | |
178 | /* Initialize some variables in our dev structure */ | |
179 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
180 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
181 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
182 | tx_queue->skb_curtx = 0; | |
183 | tx_queue->skb_dirtytx = 0; | |
184 | ||
185 | /* Initialize Transmit Descriptor Ring */ | |
186 | txbdp = tx_queue->tx_bd_base; | |
187 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
188 | txbdp->lstatus = 0; | |
189 | txbdp->bufPtr = 0; | |
190 | txbdp++; | |
191 | } | |
8728327e | 192 | |
fba4ed03 SG |
193 | /* Set the last descriptor in the ring to indicate wrap */ |
194 | txbdp--; | |
195 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
196 | } |
197 | ||
fba4ed03 SG |
198 | for (i = 0; i < priv->num_rx_queues; i++) { |
199 | rx_queue = priv->rx_queue[i]; | |
200 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
201 | rx_queue->skb_currx = 0; | |
202 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 203 | |
fba4ed03 SG |
204 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
205 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 206 | |
fba4ed03 SG |
207 | if (skb) { |
208 | gfar_init_rxbdp(rx_queue, rxbdp, | |
209 | rxbdp->bufPtr); | |
210 | } else { | |
211 | skb = gfar_new_skb(ndev); | |
212 | if (!skb) { | |
59deab26 | 213 | netdev_err(ndev, "Can't allocate RX buffers\n"); |
1eb8f7a7 | 214 | return -ENOMEM; |
fba4ed03 SG |
215 | } |
216 | rx_queue->rx_skbuff[j] = skb; | |
217 | ||
218 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 219 | } |
8728327e | 220 | |
fba4ed03 | 221 | rxbdp++; |
8728327e AV |
222 | } |
223 | ||
8728327e AV |
224 | } |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
229 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
230 | { | |
826aa4a0 | 231 | void *vaddr; |
fba4ed03 SG |
232 | dma_addr_t addr; |
233 | int i, j, k; | |
826aa4a0 | 234 | struct gfar_private *priv = netdev_priv(ndev); |
369ec162 | 235 | struct device *dev = priv->dev; |
a12f801d SG |
236 | struct gfar_priv_tx_q *tx_queue = NULL; |
237 | struct gfar_priv_rx_q *rx_queue = NULL; | |
238 | ||
fba4ed03 SG |
239 | priv->total_tx_ring_size = 0; |
240 | for (i = 0; i < priv->num_tx_queues; i++) | |
241 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
242 | ||
243 | priv->total_rx_ring_size = 0; | |
244 | for (i = 0; i < priv->num_rx_queues; i++) | |
245 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
246 | |
247 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 248 | vaddr = dma_alloc_coherent(dev, |
d0320f75 JP |
249 | (priv->total_tx_ring_size * |
250 | sizeof(struct txbd8)) + | |
251 | (priv->total_rx_ring_size * | |
252 | sizeof(struct rxbd8)), | |
253 | &addr, GFP_KERNEL); | |
254 | if (!vaddr) | |
826aa4a0 | 255 | return -ENOMEM; |
826aa4a0 | 256 | |
fba4ed03 SG |
257 | for (i = 0; i < priv->num_tx_queues; i++) { |
258 | tx_queue = priv->tx_queue[i]; | |
43d620c8 | 259 | tx_queue->tx_bd_base = vaddr; |
fba4ed03 SG |
260 | tx_queue->tx_bd_dma_base = addr; |
261 | tx_queue->dev = ndev; | |
262 | /* enet DMA only understands physical addresses */ | |
bc4598bc JC |
263 | addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; |
264 | vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; | |
fba4ed03 | 265 | } |
826aa4a0 | 266 | |
826aa4a0 | 267 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
268 | for (i = 0; i < priv->num_rx_queues; i++) { |
269 | rx_queue = priv->rx_queue[i]; | |
43d620c8 | 270 | rx_queue->rx_bd_base = vaddr; |
fba4ed03 SG |
271 | rx_queue->rx_bd_dma_base = addr; |
272 | rx_queue->dev = ndev; | |
bc4598bc JC |
273 | addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; |
274 | vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; | |
fba4ed03 | 275 | } |
826aa4a0 AV |
276 | |
277 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
278 | for (i = 0; i < priv->num_tx_queues; i++) { |
279 | tx_queue = priv->tx_queue[i]; | |
14f8dc49 JP |
280 | tx_queue->tx_skbuff = |
281 | kmalloc_array(tx_queue->tx_ring_size, | |
282 | sizeof(*tx_queue->tx_skbuff), | |
283 | GFP_KERNEL); | |
284 | if (!tx_queue->tx_skbuff) | |
fba4ed03 | 285 | goto cleanup; |
826aa4a0 | 286 | |
fba4ed03 SG |
287 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
288 | tx_queue->tx_skbuff[k] = NULL; | |
289 | } | |
826aa4a0 | 290 | |
fba4ed03 SG |
291 | for (i = 0; i < priv->num_rx_queues; i++) { |
292 | rx_queue = priv->rx_queue[i]; | |
14f8dc49 JP |
293 | rx_queue->rx_skbuff = |
294 | kmalloc_array(rx_queue->rx_ring_size, | |
295 | sizeof(*rx_queue->rx_skbuff), | |
296 | GFP_KERNEL); | |
297 | if (!rx_queue->rx_skbuff) | |
fba4ed03 | 298 | goto cleanup; |
fba4ed03 SG |
299 | |
300 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
301 | rx_queue->rx_skbuff[j] = NULL; | |
302 | } | |
826aa4a0 | 303 | |
8728327e AV |
304 | if (gfar_init_bds(ndev)) |
305 | goto cleanup; | |
826aa4a0 AV |
306 | |
307 | return 0; | |
308 | ||
309 | cleanup: | |
310 | free_skb_resources(priv); | |
311 | return -ENOMEM; | |
312 | } | |
313 | ||
fba4ed03 SG |
314 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
315 | { | |
46ceb60c | 316 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 317 | u32 __iomem *baddr; |
fba4ed03 SG |
318 | int i; |
319 | ||
320 | baddr = ®s->tbase0; | |
bc4598bc | 321 | for (i = 0; i < priv->num_tx_queues; i++) { |
fba4ed03 | 322 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); |
bc4598bc | 323 | baddr += 2; |
fba4ed03 SG |
324 | } |
325 | ||
326 | baddr = ®s->rbase0; | |
bc4598bc | 327 | for (i = 0; i < priv->num_rx_queues; i++) { |
fba4ed03 | 328 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); |
bc4598bc | 329 | baddr += 2; |
fba4ed03 SG |
330 | } |
331 | } | |
332 | ||
826aa4a0 AV |
333 | static void gfar_init_mac(struct net_device *ndev) |
334 | { | |
335 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 336 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
337 | u32 rctrl = 0; |
338 | u32 tctrl = 0; | |
339 | u32 attrs = 0; | |
340 | ||
fba4ed03 SG |
341 | /* write the tx/rx base registers */ |
342 | gfar_init_tx_rx_base(priv); | |
32c513bc | 343 | |
826aa4a0 | 344 | /* Configure the coalescing support */ |
800c644b | 345 | gfar_configure_coalescing_all(priv); |
fba4ed03 | 346 | |
ba779711 CM |
347 | /* set this when rx hw offload (TOE) functions are being used */ |
348 | priv->uses_rxfcb = 0; | |
349 | ||
1ccb8389 | 350 | if (priv->rx_filer_enable) { |
fba4ed03 | 351 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
352 | /* Program the RIR0 reg with the required distribution */ |
353 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
354 | } | |
826aa4a0 | 355 | |
f5ae6279 CM |
356 | /* Restore PROMISC mode */ |
357 | if (ndev->flags & IFF_PROMISC) | |
358 | rctrl |= RCTRL_PROM; | |
359 | ||
ba779711 | 360 | if (ndev->features & NETIF_F_RXCSUM) { |
826aa4a0 | 361 | rctrl |= RCTRL_CHECKSUMMING; |
ba779711 CM |
362 | priv->uses_rxfcb = 1; |
363 | } | |
826aa4a0 AV |
364 | |
365 | if (priv->extended_hash) { | |
366 | rctrl |= RCTRL_EXTHASH; | |
367 | ||
368 | gfar_clear_exact_match(ndev); | |
369 | rctrl |= RCTRL_EMEN; | |
370 | } | |
371 | ||
372 | if (priv->padding) { | |
373 | rctrl &= ~RCTRL_PAL_MASK; | |
374 | rctrl |= RCTRL_PADDING(priv->padding); | |
375 | } | |
376 | ||
cc772ab7 MR |
377 | /* Insert receive time stamps into padding alignment bytes */ |
378 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { | |
379 | rctrl &= ~RCTRL_PAL_MASK; | |
97553f7f | 380 | rctrl |= RCTRL_PADDING(8); |
cc772ab7 MR |
381 | priv->padding = 8; |
382 | } | |
383 | ||
97553f7f | 384 | /* Enable HW time stamping if requested from user space */ |
ba779711 | 385 | if (priv->hwts_rx_en) { |
97553f7f | 386 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; |
ba779711 CM |
387 | priv->uses_rxfcb = 1; |
388 | } | |
97553f7f | 389 | |
f646968f | 390 | if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { |
b852b720 | 391 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; |
ba779711 CM |
392 | priv->uses_rxfcb = 1; |
393 | } | |
826aa4a0 AV |
394 | |
395 | /* Init rctrl based on our settings */ | |
396 | gfar_write(®s->rctrl, rctrl); | |
397 | ||
398 | if (ndev->features & NETIF_F_IP_CSUM) | |
399 | tctrl |= TCTRL_INIT_CSUM; | |
400 | ||
b98b8bab CM |
401 | if (priv->prio_sched_en) |
402 | tctrl |= TCTRL_TXSCHED_PRIO; | |
403 | else { | |
404 | tctrl |= TCTRL_TXSCHED_WRRS; | |
405 | gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); | |
406 | gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); | |
407 | } | |
fba4ed03 | 408 | |
826aa4a0 AV |
409 | gfar_write(®s->tctrl, tctrl); |
410 | ||
411 | /* Set the extraction length and index */ | |
412 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
413 | ATTRELI_EI(priv->rx_stash_index); | |
414 | ||
415 | gfar_write(®s->attreli, attrs); | |
416 | ||
417 | /* Start with defaults, and add stashing or locking | |
0977f817 JC |
418 | * depending on the approprate variables |
419 | */ | |
826aa4a0 AV |
420 | attrs = ATTR_INIT_SETTINGS; |
421 | ||
422 | if (priv->bd_stash_en) | |
423 | attrs |= ATTR_BDSTASH; | |
424 | ||
425 | if (priv->rx_stash_size != 0) | |
426 | attrs |= ATTR_BUFSTASH; | |
427 | ||
428 | gfar_write(®s->attr, attrs); | |
429 | ||
430 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
431 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
432 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
433 | } | |
434 | ||
a7f38041 SG |
435 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
436 | { | |
437 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
438 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
439 | unsigned long tx_packets = 0, tx_bytes = 0; | |
3a2e16c8 | 440 | int i; |
a7f38041 SG |
441 | |
442 | for (i = 0; i < priv->num_rx_queues; i++) { | |
443 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
bc4598bc | 444 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; |
a7f38041 SG |
445 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; |
446 | } | |
447 | ||
448 | dev->stats.rx_packets = rx_packets; | |
bc4598bc | 449 | dev->stats.rx_bytes = rx_bytes; |
a7f38041 SG |
450 | dev->stats.rx_dropped = rx_dropped; |
451 | ||
452 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
453 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
454 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
455 | } |
456 | ||
bc4598bc | 457 | dev->stats.tx_bytes = tx_bytes; |
a7f38041 SG |
458 | dev->stats.tx_packets = tx_packets; |
459 | ||
460 | return &dev->stats; | |
461 | } | |
462 | ||
26ccfc37 AF |
463 | static const struct net_device_ops gfar_netdev_ops = { |
464 | .ndo_open = gfar_enet_open, | |
465 | .ndo_start_xmit = gfar_start_xmit, | |
466 | .ndo_stop = gfar_close, | |
467 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 468 | .ndo_set_features = gfar_set_features, |
afc4b13d | 469 | .ndo_set_rx_mode = gfar_set_multi, |
26ccfc37 AF |
470 | .ndo_tx_timeout = gfar_timeout, |
471 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 472 | .ndo_get_stats = gfar_get_stats, |
240c102d BH |
473 | .ndo_set_mac_address = eth_mac_addr, |
474 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
475 | #ifdef CONFIG_NET_POLL_CONTROLLER |
476 | .ndo_poll_controller = gfar_netpoll, | |
477 | #endif | |
478 | }; | |
479 | ||
fba4ed03 SG |
480 | void lock_rx_qs(struct gfar_private *priv) |
481 | { | |
3a2e16c8 | 482 | int i; |
fba4ed03 SG |
483 | |
484 | for (i = 0; i < priv->num_rx_queues; i++) | |
485 | spin_lock(&priv->rx_queue[i]->rxlock); | |
486 | } | |
487 | ||
488 | void lock_tx_qs(struct gfar_private *priv) | |
489 | { | |
3a2e16c8 | 490 | int i; |
fba4ed03 SG |
491 | |
492 | for (i = 0; i < priv->num_tx_queues; i++) | |
493 | spin_lock(&priv->tx_queue[i]->txlock); | |
494 | } | |
495 | ||
496 | void unlock_rx_qs(struct gfar_private *priv) | |
497 | { | |
3a2e16c8 | 498 | int i; |
fba4ed03 SG |
499 | |
500 | for (i = 0; i < priv->num_rx_queues; i++) | |
501 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
502 | } | |
503 | ||
504 | void unlock_tx_qs(struct gfar_private *priv) | |
505 | { | |
3a2e16c8 | 506 | int i; |
fba4ed03 SG |
507 | |
508 | for (i = 0; i < priv->num_tx_queues; i++) | |
509 | spin_unlock(&priv->tx_queue[i]->txlock); | |
510 | } | |
511 | ||
fba4ed03 SG |
512 | static void free_tx_pointers(struct gfar_private *priv) |
513 | { | |
3a2e16c8 | 514 | int i; |
fba4ed03 SG |
515 | |
516 | for (i = 0; i < priv->num_tx_queues; i++) | |
517 | kfree(priv->tx_queue[i]); | |
518 | } | |
519 | ||
520 | static void free_rx_pointers(struct gfar_private *priv) | |
521 | { | |
3a2e16c8 | 522 | int i; |
fba4ed03 SG |
523 | |
524 | for (i = 0; i < priv->num_rx_queues; i++) | |
525 | kfree(priv->rx_queue[i]); | |
526 | } | |
527 | ||
46ceb60c SG |
528 | static void unmap_group_regs(struct gfar_private *priv) |
529 | { | |
3a2e16c8 | 530 | int i; |
46ceb60c SG |
531 | |
532 | for (i = 0; i < MAXGROUPS; i++) | |
533 | if (priv->gfargrp[i].regs) | |
534 | iounmap(priv->gfargrp[i].regs); | |
535 | } | |
536 | ||
ee873fda CM |
537 | static void free_gfar_dev(struct gfar_private *priv) |
538 | { | |
539 | int i, j; | |
540 | ||
541 | for (i = 0; i < priv->num_grps; i++) | |
542 | for (j = 0; j < GFAR_NUM_IRQS; j++) { | |
543 | kfree(priv->gfargrp[i].irqinfo[j]); | |
544 | priv->gfargrp[i].irqinfo[j] = NULL; | |
545 | } | |
546 | ||
547 | free_netdev(priv->ndev); | |
548 | } | |
549 | ||
46ceb60c SG |
550 | static void disable_napi(struct gfar_private *priv) |
551 | { | |
3a2e16c8 | 552 | int i; |
46ceb60c SG |
553 | |
554 | for (i = 0; i < priv->num_grps; i++) | |
555 | napi_disable(&priv->gfargrp[i].napi); | |
556 | } | |
557 | ||
558 | static void enable_napi(struct gfar_private *priv) | |
559 | { | |
3a2e16c8 | 560 | int i; |
46ceb60c SG |
561 | |
562 | for (i = 0; i < priv->num_grps; i++) | |
563 | napi_enable(&priv->gfargrp[i].napi); | |
564 | } | |
565 | ||
566 | static int gfar_parse_group(struct device_node *np, | |
bc4598bc | 567 | struct gfar_private *priv, const char *model) |
46ceb60c | 568 | { |
5fedcc14 | 569 | struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; |
46ceb60c | 570 | u32 *queue_mask; |
ee873fda CM |
571 | int i; |
572 | ||
7c1e7e99 PG |
573 | for (i = 0; i < GFAR_NUM_IRQS; i++) { |
574 | grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), | |
575 | GFP_KERNEL); | |
576 | if (!grp->irqinfo[i]) | |
ee873fda | 577 | return -ENOMEM; |
ee873fda | 578 | } |
46ceb60c | 579 | |
5fedcc14 CM |
580 | grp->regs = of_iomap(np, 0); |
581 | if (!grp->regs) | |
46ceb60c SG |
582 | return -ENOMEM; |
583 | ||
ee873fda | 584 | gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); |
46ceb60c SG |
585 | |
586 | /* If we aren't the FEC we have multiple interrupts */ | |
587 | if (model && strcasecmp(model, "FEC")) { | |
ee873fda CM |
588 | gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); |
589 | gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); | |
590 | if (gfar_irq(grp, TX)->irq == NO_IRQ || | |
591 | gfar_irq(grp, RX)->irq == NO_IRQ || | |
592 | gfar_irq(grp, ER)->irq == NO_IRQ) | |
46ceb60c | 593 | return -EINVAL; |
46ceb60c SG |
594 | } |
595 | ||
5fedcc14 CM |
596 | grp->priv = priv; |
597 | spin_lock_init(&grp->grplock); | |
bc4598bc JC |
598 | if (priv->mode == MQ_MG_MODE) { |
599 | queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); | |
5fedcc14 | 600 | grp->rx_bit_map = queue_mask ? |
bc4598bc JC |
601 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
602 | queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); | |
5fedcc14 | 603 | grp->tx_bit_map = queue_mask ? |
bc4598bc | 604 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
46ceb60c | 605 | } else { |
5fedcc14 CM |
606 | grp->rx_bit_map = 0xFF; |
607 | grp->tx_bit_map = 0xFF; | |
46ceb60c SG |
608 | } |
609 | priv->num_grps++; | |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
2dc11581 | 614 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 615 | { |
b31a1d8b AF |
616 | const char *model; |
617 | const char *ctype; | |
618 | const void *mac_addr; | |
fba4ed03 SG |
619 | int err = 0, i; |
620 | struct net_device *dev = NULL; | |
621 | struct gfar_private *priv = NULL; | |
61c7a080 | 622 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 623 | struct device_node *child = NULL; |
4d7902f2 AF |
624 | const u32 *stash; |
625 | const u32 *stash_len; | |
626 | const u32 *stash_idx; | |
fba4ed03 SG |
627 | unsigned int num_tx_qs, num_rx_qs; |
628 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
629 | |
630 | if (!np || !of_device_is_available(np)) | |
631 | return -ENODEV; | |
632 | ||
fba4ed03 SG |
633 | /* parse the num of tx and rx queues */ |
634 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
635 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
636 | ||
637 | if (num_tx_qs > MAX_TX_QS) { | |
59deab26 JP |
638 | pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", |
639 | num_tx_qs, MAX_TX_QS); | |
640 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
641 | return -EINVAL; |
642 | } | |
643 | ||
644 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
645 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
646 | ||
647 | if (num_rx_qs > MAX_RX_QS) { | |
59deab26 JP |
648 | pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", |
649 | num_rx_qs, MAX_RX_QS); | |
650 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
651 | return -EINVAL; |
652 | } | |
653 | ||
654 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
655 | dev = *pdev; | |
656 | if (NULL == dev) | |
657 | return -ENOMEM; | |
658 | ||
659 | priv = netdev_priv(dev); | |
fba4ed03 SG |
660 | priv->ndev = dev; |
661 | ||
fba4ed03 | 662 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 663 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 664 | priv->num_rx_queues = num_rx_qs; |
46ceb60c | 665 | priv->num_grps = 0x0; |
b31a1d8b | 666 | |
0977f817 | 667 | /* Init Rx queue filer rule set linked list */ |
4aa3a715 SP |
668 | INIT_LIST_HEAD(&priv->rx_list.list); |
669 | priv->rx_list.count = 0; | |
670 | mutex_init(&priv->rx_queue_access); | |
671 | ||
b31a1d8b AF |
672 | model = of_get_property(np, "model", NULL); |
673 | ||
46ceb60c SG |
674 | for (i = 0; i < MAXGROUPS; i++) |
675 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 676 | |
46ceb60c SG |
677 | /* Parse and initialize group specific information */ |
678 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
679 | priv->mode = MQ_MG_MODE; | |
680 | for_each_child_of_node(np, child) { | |
681 | err = gfar_parse_group(child, priv, model); | |
682 | if (err) | |
683 | goto err_grp_init; | |
b31a1d8b | 684 | } |
46ceb60c SG |
685 | } else { |
686 | priv->mode = SQ_SG_MODE; | |
687 | err = gfar_parse_group(np, priv, model); | |
bc4598bc | 688 | if (err) |
46ceb60c | 689 | goto err_grp_init; |
b31a1d8b AF |
690 | } |
691 | ||
fba4ed03 | 692 | for (i = 0; i < priv->num_tx_queues; i++) |
c6e1160e | 693 | priv->tx_queue[i] = NULL; |
fba4ed03 SG |
694 | for (i = 0; i < priv->num_rx_queues; i++) |
695 | priv->rx_queue[i] = NULL; | |
696 | ||
697 | for (i = 0; i < priv->num_tx_queues; i++) { | |
de47f072 JP |
698 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), |
699 | GFP_KERNEL); | |
fba4ed03 SG |
700 | if (!priv->tx_queue[i]) { |
701 | err = -ENOMEM; | |
702 | goto tx_alloc_failed; | |
703 | } | |
704 | priv->tx_queue[i]->tx_skbuff = NULL; | |
705 | priv->tx_queue[i]->qindex = i; | |
706 | priv->tx_queue[i]->dev = dev; | |
707 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
708 | } | |
709 | ||
710 | for (i = 0; i < priv->num_rx_queues; i++) { | |
de47f072 JP |
711 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), |
712 | GFP_KERNEL); | |
fba4ed03 SG |
713 | if (!priv->rx_queue[i]) { |
714 | err = -ENOMEM; | |
715 | goto rx_alloc_failed; | |
716 | } | |
717 | priv->rx_queue[i]->rx_skbuff = NULL; | |
718 | priv->rx_queue[i]->qindex = i; | |
719 | priv->rx_queue[i]->dev = dev; | |
720 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
721 | } | |
722 | ||
723 | ||
4d7902f2 AF |
724 | stash = of_get_property(np, "bd-stash", NULL); |
725 | ||
a12f801d | 726 | if (stash) { |
4d7902f2 AF |
727 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
728 | priv->bd_stash_en = 1; | |
729 | } | |
730 | ||
731 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
732 | ||
733 | if (stash_len) | |
734 | priv->rx_stash_size = *stash_len; | |
735 | ||
736 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
737 | ||
738 | if (stash_idx) | |
739 | priv->rx_stash_index = *stash_idx; | |
740 | ||
741 | if (stash_len || stash_idx) | |
742 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
743 | ||
b31a1d8b | 744 | mac_addr = of_get_mac_address(np); |
bc4598bc | 745 | |
b31a1d8b | 746 | if (mac_addr) |
6a3c910c | 747 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
b31a1d8b AF |
748 | |
749 | if (model && !strcasecmp(model, "TSEC")) | |
bc4598bc JC |
750 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
751 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
752 | FSL_GIANFAR_DEV_HAS_RMON | | |
753 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
754 | ||
b31a1d8b | 755 | if (model && !strcasecmp(model, "eTSEC")) |
bc4598bc JC |
756 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
757 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
758 | FSL_GIANFAR_DEV_HAS_RMON | | |
759 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
760 | FSL_GIANFAR_DEV_HAS_PADDING | | |
761 | FSL_GIANFAR_DEV_HAS_CSUM | | |
762 | FSL_GIANFAR_DEV_HAS_VLAN | | |
763 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
764 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | | |
765 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
766 | |
767 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
768 | ||
769 | /* We only care about rgmii-id. The rest are autodetected */ | |
770 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
771 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
772 | else | |
773 | priv->interface = PHY_INTERFACE_MODE_MII; | |
774 | ||
775 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
776 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
777 | ||
fe192a49 | 778 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
779 | |
780 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 781 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
782 | |
783 | return 0; | |
784 | ||
fba4ed03 SG |
785 | rx_alloc_failed: |
786 | free_rx_pointers(priv); | |
787 | tx_alloc_failed: | |
788 | free_tx_pointers(priv); | |
46ceb60c SG |
789 | err_grp_init: |
790 | unmap_group_regs(priv); | |
ee873fda | 791 | free_gfar_dev(priv); |
b31a1d8b AF |
792 | return err; |
793 | } | |
794 | ||
cc772ab7 | 795 | static int gfar_hwtstamp_ioctl(struct net_device *netdev, |
bc4598bc | 796 | struct ifreq *ifr, int cmd) |
cc772ab7 MR |
797 | { |
798 | struct hwtstamp_config config; | |
799 | struct gfar_private *priv = netdev_priv(netdev); | |
800 | ||
801 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
802 | return -EFAULT; | |
803 | ||
804 | /* reserved for future extensions */ | |
805 | if (config.flags) | |
806 | return -EINVAL; | |
807 | ||
f0ee7acf MR |
808 | switch (config.tx_type) { |
809 | case HWTSTAMP_TX_OFF: | |
810 | priv->hwts_tx_en = 0; | |
811 | break; | |
812 | case HWTSTAMP_TX_ON: | |
813 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
814 | return -ERANGE; | |
815 | priv->hwts_tx_en = 1; | |
816 | break; | |
817 | default: | |
cc772ab7 | 818 | return -ERANGE; |
f0ee7acf | 819 | } |
cc772ab7 MR |
820 | |
821 | switch (config.rx_filter) { | |
822 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
823 | if (priv->hwts_rx_en) { |
824 | stop_gfar(netdev); | |
825 | priv->hwts_rx_en = 0; | |
826 | startup_gfar(netdev); | |
827 | } | |
cc772ab7 MR |
828 | break; |
829 | default: | |
830 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
831 | return -ERANGE; | |
97553f7f MR |
832 | if (!priv->hwts_rx_en) { |
833 | stop_gfar(netdev); | |
834 | priv->hwts_rx_en = 1; | |
835 | startup_gfar(netdev); | |
836 | } | |
cc772ab7 MR |
837 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
838 | break; | |
839 | } | |
840 | ||
841 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
842 | -EFAULT : 0; | |
843 | } | |
844 | ||
0faac9f7 CW |
845 | /* Ioctl MII Interface */ |
846 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
847 | { | |
848 | struct gfar_private *priv = netdev_priv(dev); | |
849 | ||
850 | if (!netif_running(dev)) | |
851 | return -EINVAL; | |
852 | ||
cc772ab7 MR |
853 | if (cmd == SIOCSHWTSTAMP) |
854 | return gfar_hwtstamp_ioctl(dev, rq, cmd); | |
855 | ||
0faac9f7 CW |
856 | if (!priv->phydev) |
857 | return -ENODEV; | |
858 | ||
28b04113 | 859 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
860 | } |
861 | ||
fba4ed03 SG |
862 | static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) |
863 | { | |
864 | unsigned int new_bit_map = 0x0; | |
865 | int mask = 0x1 << (max_qs - 1), i; | |
bc4598bc | 866 | |
fba4ed03 SG |
867 | for (i = 0; i < max_qs; i++) { |
868 | if (bit_map & mask) | |
869 | new_bit_map = new_bit_map + (1 << i); | |
870 | mask = mask >> 0x1; | |
871 | } | |
872 | return new_bit_map; | |
873 | } | |
7a8b3372 | 874 | |
18294ad1 AV |
875 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
876 | u32 class) | |
7a8b3372 SG |
877 | { |
878 | u32 rqfpr = FPR_FILER_MASK; | |
879 | u32 rqfcr = 0x0; | |
880 | ||
881 | rqfar--; | |
882 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
883 | priv->ftp_rqfpr[rqfar] = rqfpr; |
884 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
885 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
886 | ||
887 | rqfar--; | |
888 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
889 | priv->ftp_rqfpr[rqfar] = rqfpr; |
890 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
891 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
892 | ||
893 | rqfar--; | |
894 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
895 | rqfpr = class; | |
6c43e046 WJB |
896 | priv->ftp_rqfcr[rqfar] = rqfcr; |
897 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
898 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
899 | ||
900 | rqfar--; | |
901 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
902 | rqfpr = class; | |
6c43e046 WJB |
903 | priv->ftp_rqfcr[rqfar] = rqfcr; |
904 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
905 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
906 | ||
907 | return rqfar; | |
908 | } | |
909 | ||
910 | static void gfar_init_filer_table(struct gfar_private *priv) | |
911 | { | |
912 | int i = 0x0; | |
913 | u32 rqfar = MAX_FILER_IDX; | |
914 | u32 rqfcr = 0x0; | |
915 | u32 rqfpr = FPR_FILER_MASK; | |
916 | ||
917 | /* Default rule */ | |
918 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
919 | priv->ftp_rqfcr[rqfar] = rqfcr; |
920 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
921 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
922 | ||
923 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
924 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
925 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
926 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
927 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
928 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
929 | ||
85dd08eb | 930 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
931 | priv->cur_filer_idx = rqfar; |
932 | ||
933 | /* Rest are masked rules */ | |
934 | rqfcr = RQFCR_CMP_NOMATCH; | |
935 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
936 | priv->ftp_rqfcr[i] = rqfcr; |
937 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
938 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
939 | } | |
940 | } | |
941 | ||
7d350977 AV |
942 | static void gfar_detect_errata(struct gfar_private *priv) |
943 | { | |
944 | struct device *dev = &priv->ofdev->dev; | |
945 | unsigned int pvr = mfspr(SPRN_PVR); | |
946 | unsigned int svr = mfspr(SPRN_SVR); | |
947 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
948 | unsigned int rev = svr & 0xffff; | |
949 | ||
950 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
951 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
bc4598bc | 952 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
7d350977 AV |
953 | priv->errata |= GFAR_ERRATA_74; |
954 | ||
deb90eac AV |
955 | /* MPC8313 and MPC837x all rev */ |
956 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 957 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
deb90eac AV |
958 | priv->errata |= GFAR_ERRATA_76; |
959 | ||
511d934f AV |
960 | /* MPC8313 and MPC837x all rev */ |
961 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 962 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
511d934f AV |
963 | priv->errata |= GFAR_ERRATA_A002; |
964 | ||
4363c2fd AD |
965 | /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ |
966 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || | |
bc4598bc | 967 | (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) |
4363c2fd AD |
968 | priv->errata |= GFAR_ERRATA_12; |
969 | ||
7d350977 AV |
970 | if (priv->errata) |
971 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
972 | priv->errata); | |
973 | } | |
974 | ||
bb40dcbb | 975 | /* Set up the ethernet device structure, private data, |
0977f817 JC |
976 | * and anything else we need before we start |
977 | */ | |
74888760 | 978 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 LT |
979 | { |
980 | u32 tempval; | |
981 | struct net_device *dev = NULL; | |
982 | struct gfar_private *priv = NULL; | |
f4983704 | 983 | struct gfar __iomem *regs = NULL; |
46ceb60c | 984 | int err = 0, i, grp_idx = 0; |
fba4ed03 | 985 | u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; |
46ceb60c | 986 | u32 isrg = 0; |
18294ad1 | 987 | u32 __iomem *baddr; |
1da177e4 | 988 | |
fba4ed03 | 989 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 990 | |
fba4ed03 SG |
991 | if (err) |
992 | return err; | |
1da177e4 LT |
993 | |
994 | priv = netdev_priv(dev); | |
4826857f KG |
995 | priv->ndev = dev; |
996 | priv->ofdev = ofdev; | |
369ec162 | 997 | priv->dev = &ofdev->dev; |
4826857f | 998 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 999 | |
d87eb127 | 1000 | spin_lock_init(&priv->bflock); |
ab939905 | 1001 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 1002 | |
8513fbd8 | 1003 | platform_set_drvdata(ofdev, priv); |
46ceb60c | 1004 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1005 | |
7d350977 AV |
1006 | gfar_detect_errata(priv); |
1007 | ||
0977f817 JC |
1008 | /* Stop the DMA engine now, in case it was running before |
1009 | * (The firmware could have used it, and left it running). | |
1010 | */ | |
257d938a | 1011 | gfar_halt(dev); |
1da177e4 LT |
1012 | |
1013 | /* Reset MAC layer */ | |
f4983704 | 1014 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); |
1da177e4 | 1015 | |
b98ac702 AF |
1016 | /* We need to delay at least 3 TX clocks */ |
1017 | udelay(2); | |
1018 | ||
1da177e4 | 1019 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
f4983704 | 1020 | gfar_write(®s->maccfg1, tempval); |
1da177e4 LT |
1021 | |
1022 | /* Initialize MACCFG2. */ | |
7d350977 AV |
1023 | tempval = MACCFG2_INIT_SETTINGS; |
1024 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1025 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1026 | gfar_write(®s->maccfg2, tempval); | |
1da177e4 LT |
1027 | |
1028 | /* Initialize ECNTRL */ | |
f4983704 | 1029 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
1da177e4 | 1030 | |
1da177e4 | 1031 | /* Set the dev->base_addr to the gfar reg region */ |
f4983704 | 1032 | dev->base_addr = (unsigned long) regs; |
1da177e4 | 1033 | |
1da177e4 | 1034 | /* Fill in the dev structure */ |
1da177e4 | 1035 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1036 | dev->mtu = 1500; |
26ccfc37 | 1037 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1038 | dev->ethtool_ops = &gfar_ethtool_ops; |
1039 | ||
fba4ed03 | 1040 | /* Register for napi ...We are registering NAPI for each grp */ |
5eaedf31 CM |
1041 | if (priv->mode == SQ_SG_MODE) |
1042 | netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq, | |
bc4598bc | 1043 | GFAR_DEV_WEIGHT); |
5eaedf31 CM |
1044 | else |
1045 | for (i = 0; i < priv->num_grps; i++) | |
1046 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, | |
1047 | GFAR_DEV_WEIGHT); | |
a12f801d | 1048 | |
b31a1d8b | 1049 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 | 1050 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1051 | NETIF_F_RXCSUM; |
8b3afe95 | 1052 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1053 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; |
8b3afe95 | 1054 | } |
0bbaf069 | 1055 | |
87c288c6 | 1056 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
f646968f PM |
1057 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | |
1058 | NETIF_F_HW_VLAN_CTAG_RX; | |
1059 | dev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
87c288c6 | 1060 | } |
0bbaf069 | 1061 | |
b31a1d8b | 1062 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
1063 | priv->extended_hash = 1; |
1064 | priv->hash_width = 9; | |
1065 | ||
f4983704 SG |
1066 | priv->hash_regs[0] = ®s->igaddr0; |
1067 | priv->hash_regs[1] = ®s->igaddr1; | |
1068 | priv->hash_regs[2] = ®s->igaddr2; | |
1069 | priv->hash_regs[3] = ®s->igaddr3; | |
1070 | priv->hash_regs[4] = ®s->igaddr4; | |
1071 | priv->hash_regs[5] = ®s->igaddr5; | |
1072 | priv->hash_regs[6] = ®s->igaddr6; | |
1073 | priv->hash_regs[7] = ®s->igaddr7; | |
1074 | priv->hash_regs[8] = ®s->gaddr0; | |
1075 | priv->hash_regs[9] = ®s->gaddr1; | |
1076 | priv->hash_regs[10] = ®s->gaddr2; | |
1077 | priv->hash_regs[11] = ®s->gaddr3; | |
1078 | priv->hash_regs[12] = ®s->gaddr4; | |
1079 | priv->hash_regs[13] = ®s->gaddr5; | |
1080 | priv->hash_regs[14] = ®s->gaddr6; | |
1081 | priv->hash_regs[15] = ®s->gaddr7; | |
0bbaf069 KG |
1082 | |
1083 | } else { | |
1084 | priv->extended_hash = 0; | |
1085 | priv->hash_width = 8; | |
1086 | ||
f4983704 SG |
1087 | priv->hash_regs[0] = ®s->gaddr0; |
1088 | priv->hash_regs[1] = ®s->gaddr1; | |
1089 | priv->hash_regs[2] = ®s->gaddr2; | |
1090 | priv->hash_regs[3] = ®s->gaddr3; | |
1091 | priv->hash_regs[4] = ®s->gaddr4; | |
1092 | priv->hash_regs[5] = ®s->gaddr5; | |
1093 | priv->hash_regs[6] = ®s->gaddr6; | |
1094 | priv->hash_regs[7] = ®s->gaddr7; | |
0bbaf069 KG |
1095 | } |
1096 | ||
b31a1d8b | 1097 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
1098 | priv->padding = DEFAULT_PADDING; |
1099 | else | |
1100 | priv->padding = 0; | |
1101 | ||
cc772ab7 | 1102 | if (dev->features & NETIF_F_IP_CSUM || |
bc4598bc | 1103 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) |
bee9e58c | 1104 | dev->needed_headroom = GMAC_FCB_LEN; |
1da177e4 | 1105 | |
46ceb60c SG |
1106 | /* Program the isrg regs only if number of grps > 1 */ |
1107 | if (priv->num_grps > 1) { | |
1108 | baddr = ®s->isrg0; | |
1109 | for (i = 0; i < priv->num_grps; i++) { | |
1110 | isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); | |
1111 | isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); | |
1112 | gfar_write(baddr, isrg); | |
1113 | baddr++; | |
1114 | isrg = 0x0; | |
1115 | } | |
1116 | } | |
1117 | ||
fba4ed03 | 1118 | /* Need to reverse the bit maps as bit_map's MSB is q0 |
984b3f57 | 1119 | * but, for_each_set_bit parses from right to left, which |
0977f817 JC |
1120 | * basically reverses the queue numbers |
1121 | */ | |
46ceb60c | 1122 | for (i = 0; i< priv->num_grps; i++) { |
bc4598bc JC |
1123 | priv->gfargrp[i].tx_bit_map = |
1124 | reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS); | |
1125 | priv->gfargrp[i].rx_bit_map = | |
1126 | reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS); | |
46ceb60c SG |
1127 | } |
1128 | ||
1129 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
0977f817 JC |
1130 | * also assign queues to groups |
1131 | */ | |
46ceb60c SG |
1132 | for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { |
1133 | priv->gfargrp[grp_idx].num_rx_queues = 0x0; | |
bc4598bc | 1134 | |
984b3f57 | 1135 | for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, |
bc4598bc | 1136 | priv->num_rx_queues) { |
46ceb60c SG |
1137 | priv->gfargrp[grp_idx].num_rx_queues++; |
1138 | priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1139 | rstat = rstat | (RSTAT_CLEAR_RHALT >> i); | |
1140 | rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
1141 | } | |
1142 | priv->gfargrp[grp_idx].num_tx_queues = 0x0; | |
bc4598bc | 1143 | |
984b3f57 | 1144 | for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, |
bc4598bc | 1145 | priv->num_tx_queues) { |
46ceb60c SG |
1146 | priv->gfargrp[grp_idx].num_tx_queues++; |
1147 | priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1148 | tstat = tstat | (TSTAT_CLEAR_THALT >> i); | |
1149 | tqueue = tqueue | (TQUEUE_EN0 >> i); | |
1150 | } | |
1151 | priv->gfargrp[grp_idx].rstat = rstat; | |
1152 | priv->gfargrp[grp_idx].tstat = tstat; | |
1153 | rstat = tstat =0; | |
fba4ed03 | 1154 | } |
fba4ed03 SG |
1155 | |
1156 | gfar_write(®s->rqueue, rqueue); | |
1157 | gfar_write(®s->tqueue, tqueue); | |
1158 | ||
1da177e4 | 1159 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; |
1da177e4 | 1160 | |
a12f801d | 1161 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1162 | for (i = 0; i < priv->num_tx_queues; i++) { |
1163 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1164 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1165 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1166 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1167 | } | |
a12f801d | 1168 | |
fba4ed03 SG |
1169 | for (i = 0; i < priv->num_rx_queues; i++) { |
1170 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1171 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1172 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1173 | } | |
1da177e4 | 1174 | |
0977f817 | 1175 | /* always enable rx filer */ |
4aa3a715 | 1176 | priv->rx_filer_enable = 1; |
0bbaf069 KG |
1177 | /* Enable most messages by default */ |
1178 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
b98b8bab CM |
1179 | /* use pritority h/w tx queue scheduling for single queue devices */ |
1180 | if (priv->num_tx_queues == 1) | |
1181 | priv->prio_sched_en = 1; | |
0bbaf069 | 1182 | |
d3eab82b TP |
1183 | /* Carrier starts down, phylib will bring it up */ |
1184 | netif_carrier_off(dev); | |
1185 | ||
1da177e4 LT |
1186 | err = register_netdev(dev); |
1187 | ||
1188 | if (err) { | |
59deab26 | 1189 | pr_err("%s: Cannot register net device, aborting\n", dev->name); |
1da177e4 LT |
1190 | goto register_fail; |
1191 | } | |
1192 | ||
2884e5cc | 1193 | device_init_wakeup(&dev->dev, |
bc4598bc JC |
1194 | priv->device_flags & |
1195 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
2884e5cc | 1196 | |
c50a5d9a | 1197 | /* fill out IRQ number and name fields */ |
46ceb60c | 1198 | for (i = 0; i < priv->num_grps; i++) { |
ee873fda | 1199 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
46ceb60c | 1200 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
ee873fda | 1201 | sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", |
0015e551 | 1202 | dev->name, "_g", '0' + i, "_tx"); |
ee873fda | 1203 | sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", |
0015e551 | 1204 | dev->name, "_g", '0' + i, "_rx"); |
ee873fda | 1205 | sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", |
0015e551 | 1206 | dev->name, "_g", '0' + i, "_er"); |
46ceb60c | 1207 | } else |
ee873fda | 1208 | strcpy(gfar_irq(grp, TX)->name, dev->name); |
46ceb60c | 1209 | } |
c50a5d9a | 1210 | |
7a8b3372 SG |
1211 | /* Initialize the filer table */ |
1212 | gfar_init_filer_table(priv); | |
1213 | ||
7f7f5316 AF |
1214 | /* Create all the sysfs files */ |
1215 | gfar_init_sysfs(dev); | |
1216 | ||
1da177e4 | 1217 | /* Print out the device info */ |
59deab26 | 1218 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
1da177e4 | 1219 | |
0977f817 JC |
1220 | /* Even more device info helps when determining which kernel |
1221 | * provided which set of benchmarks. | |
1222 | */ | |
59deab26 | 1223 | netdev_info(dev, "Running with NAPI enabled\n"); |
fba4ed03 | 1224 | for (i = 0; i < priv->num_rx_queues; i++) |
59deab26 JP |
1225 | netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", |
1226 | i, priv->rx_queue[i]->rx_ring_size); | |
bc4598bc | 1227 | for (i = 0; i < priv->num_tx_queues; i++) |
59deab26 JP |
1228 | netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", |
1229 | i, priv->tx_queue[i]->tx_ring_size); | |
1da177e4 LT |
1230 | |
1231 | return 0; | |
1232 | ||
1233 | register_fail: | |
46ceb60c | 1234 | unmap_group_regs(priv); |
fba4ed03 SG |
1235 | free_tx_pointers(priv); |
1236 | free_rx_pointers(priv); | |
fe192a49 GL |
1237 | if (priv->phy_node) |
1238 | of_node_put(priv->phy_node); | |
1239 | if (priv->tbi_node) | |
1240 | of_node_put(priv->tbi_node); | |
ee873fda | 1241 | free_gfar_dev(priv); |
bb40dcbb | 1242 | return err; |
1da177e4 LT |
1243 | } |
1244 | ||
2dc11581 | 1245 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1246 | { |
8513fbd8 | 1247 | struct gfar_private *priv = platform_get_drvdata(ofdev); |
1da177e4 | 1248 | |
fe192a49 GL |
1249 | if (priv->phy_node) |
1250 | of_node_put(priv->phy_node); | |
1251 | if (priv->tbi_node) | |
1252 | of_node_put(priv->tbi_node); | |
1253 | ||
d9d8e041 | 1254 | unregister_netdev(priv->ndev); |
46ceb60c | 1255 | unmap_group_regs(priv); |
ee873fda | 1256 | free_gfar_dev(priv); |
1da177e4 LT |
1257 | |
1258 | return 0; | |
1259 | } | |
1260 | ||
d87eb127 | 1261 | #ifdef CONFIG_PM |
be926fc4 AV |
1262 | |
1263 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1264 | { |
be926fc4 AV |
1265 | struct gfar_private *priv = dev_get_drvdata(dev); |
1266 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1267 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1268 | unsigned long flags; |
1269 | u32 tempval; | |
1270 | ||
1271 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1272 | (priv->device_flags & |
1273 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1274 | |
be926fc4 | 1275 | netif_device_detach(ndev); |
d87eb127 | 1276 | |
be926fc4 | 1277 | if (netif_running(ndev)) { |
fba4ed03 SG |
1278 | |
1279 | local_irq_save(flags); | |
1280 | lock_tx_qs(priv); | |
1281 | lock_rx_qs(priv); | |
d87eb127 | 1282 | |
be926fc4 | 1283 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1284 | |
1285 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1286 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1287 | |
1288 | tempval &= ~MACCFG1_TX_EN; | |
1289 | ||
1290 | if (!magic_packet) | |
1291 | tempval &= ~MACCFG1_RX_EN; | |
1292 | ||
f4983704 | 1293 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1294 | |
fba4ed03 SG |
1295 | unlock_rx_qs(priv); |
1296 | unlock_tx_qs(priv); | |
1297 | local_irq_restore(flags); | |
d87eb127 | 1298 | |
46ceb60c | 1299 | disable_napi(priv); |
d87eb127 SW |
1300 | |
1301 | if (magic_packet) { | |
1302 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1303 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1304 | |
1305 | /* Enable Magic Packet mode */ | |
f4983704 | 1306 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1307 | tempval |= MACCFG2_MPEN; |
f4983704 | 1308 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1309 | } else { |
1310 | phy_stop(priv->phydev); | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
be926fc4 | 1317 | static int gfar_resume(struct device *dev) |
d87eb127 | 1318 | { |
be926fc4 AV |
1319 | struct gfar_private *priv = dev_get_drvdata(dev); |
1320 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1321 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1322 | unsigned long flags; |
1323 | u32 tempval; | |
1324 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1325 | (priv->device_flags & |
1326 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1327 | |
be926fc4 AV |
1328 | if (!netif_running(ndev)) { |
1329 | netif_device_attach(ndev); | |
d87eb127 SW |
1330 | return 0; |
1331 | } | |
1332 | ||
1333 | if (!magic_packet && priv->phydev) | |
1334 | phy_start(priv->phydev); | |
1335 | ||
1336 | /* Disable Magic Packet mode, in case something | |
1337 | * else woke us up. | |
1338 | */ | |
fba4ed03 SG |
1339 | local_irq_save(flags); |
1340 | lock_tx_qs(priv); | |
1341 | lock_rx_qs(priv); | |
d87eb127 | 1342 | |
f4983704 | 1343 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1344 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1345 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1346 | |
be926fc4 | 1347 | gfar_start(ndev); |
d87eb127 | 1348 | |
fba4ed03 SG |
1349 | unlock_rx_qs(priv); |
1350 | unlock_tx_qs(priv); | |
1351 | local_irq_restore(flags); | |
d87eb127 | 1352 | |
be926fc4 AV |
1353 | netif_device_attach(ndev); |
1354 | ||
46ceb60c | 1355 | enable_napi(priv); |
be926fc4 AV |
1356 | |
1357 | return 0; | |
1358 | } | |
1359 | ||
1360 | static int gfar_restore(struct device *dev) | |
1361 | { | |
1362 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1363 | struct net_device *ndev = priv->ndev; | |
1364 | ||
103cdd1d WD |
1365 | if (!netif_running(ndev)) { |
1366 | netif_device_attach(ndev); | |
1367 | ||
be926fc4 | 1368 | return 0; |
103cdd1d | 1369 | } |
be926fc4 | 1370 | |
1eb8f7a7 CM |
1371 | if (gfar_init_bds(ndev)) { |
1372 | free_skb_resources(priv); | |
1373 | return -ENOMEM; | |
1374 | } | |
1375 | ||
be926fc4 AV |
1376 | init_registers(ndev); |
1377 | gfar_set_mac_address(ndev); | |
1378 | gfar_init_mac(ndev); | |
1379 | gfar_start(ndev); | |
1380 | ||
1381 | priv->oldlink = 0; | |
1382 | priv->oldspeed = 0; | |
1383 | priv->oldduplex = -1; | |
1384 | ||
1385 | if (priv->phydev) | |
1386 | phy_start(priv->phydev); | |
d87eb127 | 1387 | |
be926fc4 | 1388 | netif_device_attach(ndev); |
5ea681d4 | 1389 | enable_napi(priv); |
d87eb127 SW |
1390 | |
1391 | return 0; | |
1392 | } | |
be926fc4 AV |
1393 | |
1394 | static struct dev_pm_ops gfar_pm_ops = { | |
1395 | .suspend = gfar_suspend, | |
1396 | .resume = gfar_resume, | |
1397 | .freeze = gfar_suspend, | |
1398 | .thaw = gfar_resume, | |
1399 | .restore = gfar_restore, | |
1400 | }; | |
1401 | ||
1402 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1403 | ||
d87eb127 | 1404 | #else |
be926fc4 AV |
1405 | |
1406 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1407 | |
d87eb127 | 1408 | #endif |
1da177e4 | 1409 | |
e8a2b6a4 AF |
1410 | /* Reads the controller's registers to determine what interface |
1411 | * connects it to the PHY. | |
1412 | */ | |
1413 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1414 | { | |
1415 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1416 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1417 | u32 ecntrl; |
1418 | ||
f4983704 | 1419 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1420 | |
1421 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1422 | return PHY_INTERFACE_MODE_SGMII; | |
1423 | ||
1424 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1425 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1426 | return PHY_INTERFACE_MODE_RTBI; | |
1427 | else | |
1428 | return PHY_INTERFACE_MODE_TBI; | |
1429 | } | |
1430 | ||
1431 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
bc4598bc | 1432 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) { |
e8a2b6a4 | 1433 | return PHY_INTERFACE_MODE_RMII; |
bc4598bc | 1434 | } |
7132ab7f | 1435 | else { |
b31a1d8b | 1436 | phy_interface_t interface = priv->interface; |
7132ab7f | 1437 | |
0977f817 | 1438 | /* This isn't autodetected right now, so it must |
7132ab7f AF |
1439 | * be set by the device tree or platform code. |
1440 | */ | |
1441 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1442 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1443 | ||
e8a2b6a4 | 1444 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1445 | } |
e8a2b6a4 AF |
1446 | } |
1447 | ||
b31a1d8b | 1448 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1449 | return PHY_INTERFACE_MODE_GMII; |
1450 | ||
1451 | return PHY_INTERFACE_MODE_MII; | |
1452 | } | |
1453 | ||
1454 | ||
bb40dcbb AF |
1455 | /* Initializes driver's PHY state, and attaches to the PHY. |
1456 | * Returns 0 on success. | |
1da177e4 LT |
1457 | */ |
1458 | static int init_phy(struct net_device *dev) | |
1459 | { | |
1460 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1461 | uint gigabit_support = |
b31a1d8b | 1462 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 1463 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 1464 | phy_interface_t interface; |
1da177e4 LT |
1465 | |
1466 | priv->oldlink = 0; | |
1467 | priv->oldspeed = 0; | |
1468 | priv->oldduplex = -1; | |
1469 | ||
e8a2b6a4 AF |
1470 | interface = gfar_get_interface(dev); |
1471 | ||
1db780f8 AV |
1472 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1473 | interface); | |
1474 | if (!priv->phydev) | |
1475 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1476 | interface); | |
1477 | if (!priv->phydev) { | |
1478 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1479 | return -ENODEV; | |
fe192a49 | 1480 | } |
1da177e4 | 1481 | |
d3c12873 KJ |
1482 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1483 | gfar_configure_serdes(dev); | |
1484 | ||
bb40dcbb | 1485 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1486 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1487 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1488 | |
1489 | return 0; | |
1da177e4 LT |
1490 | } |
1491 | ||
0977f817 | 1492 | /* Initialize TBI PHY interface for communicating with the |
d0313587 PG |
1493 | * SERDES lynx PHY on the chip. We communicate with this PHY |
1494 | * through the MDIO bus on each controller, treating it as a | |
1495 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1496 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1497 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1498 | * value doesn't matter, as there are no other PHYs on the bus. | |
1499 | */ | |
d3c12873 KJ |
1500 | static void gfar_configure_serdes(struct net_device *dev) |
1501 | { | |
1502 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1503 | struct phy_device *tbiphy; |
1504 | ||
1505 | if (!priv->tbi_node) { | |
1506 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1507 | "device tree specify a tbi-handle\n"); | |
1508 | return; | |
1509 | } | |
c132419e | 1510 | |
fe192a49 GL |
1511 | tbiphy = of_phy_find_device(priv->tbi_node); |
1512 | if (!tbiphy) { | |
1513 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1514 | return; |
1515 | } | |
d3c12873 | 1516 | |
0977f817 | 1517 | /* If the link is already up, we must already be ok, and don't need to |
bdb59f94 TP |
1518 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1519 | * everything for us? Resetting it takes the link down and requires | |
1520 | * several seconds for it to come back. | |
1521 | */ | |
fe192a49 | 1522 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1523 | return; |
d3c12873 | 1524 | |
d0313587 | 1525 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1526 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1527 | |
fe192a49 | 1528 | phy_write(tbiphy, MII_ADVERTISE, |
bc4598bc JC |
1529 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1530 | ADVERTISE_1000XPSE_ASYM); | |
d3c12873 | 1531 | |
bc4598bc JC |
1532 | phy_write(tbiphy, MII_BMCR, |
1533 | BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | | |
1534 | BMCR_SPEED1000); | |
d3c12873 KJ |
1535 | } |
1536 | ||
1da177e4 LT |
1537 | static void init_registers(struct net_device *dev) |
1538 | { | |
1539 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 1540 | struct gfar __iomem *regs = NULL; |
3a2e16c8 | 1541 | int i; |
1da177e4 | 1542 | |
46ceb60c SG |
1543 | for (i = 0; i < priv->num_grps; i++) { |
1544 | regs = priv->gfargrp[i].regs; | |
1545 | /* Clear IEVENT */ | |
1546 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1da177e4 | 1547 | |
46ceb60c SG |
1548 | /* Initialize IMASK */ |
1549 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1550 | } | |
1da177e4 | 1551 | |
46ceb60c | 1552 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1553 | /* Init hash registers to zero */ |
f4983704 SG |
1554 | gfar_write(®s->igaddr0, 0); |
1555 | gfar_write(®s->igaddr1, 0); | |
1556 | gfar_write(®s->igaddr2, 0); | |
1557 | gfar_write(®s->igaddr3, 0); | |
1558 | gfar_write(®s->igaddr4, 0); | |
1559 | gfar_write(®s->igaddr5, 0); | |
1560 | gfar_write(®s->igaddr6, 0); | |
1561 | gfar_write(®s->igaddr7, 0); | |
1562 | ||
1563 | gfar_write(®s->gaddr0, 0); | |
1564 | gfar_write(®s->gaddr1, 0); | |
1565 | gfar_write(®s->gaddr2, 0); | |
1566 | gfar_write(®s->gaddr3, 0); | |
1567 | gfar_write(®s->gaddr4, 0); | |
1568 | gfar_write(®s->gaddr5, 0); | |
1569 | gfar_write(®s->gaddr6, 0); | |
1570 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1571 | |
1da177e4 | 1572 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1573 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1574 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1575 | |
1576 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1577 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1578 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1579 | } |
1580 | ||
1581 | /* Initialize the max receive buffer length */ | |
f4983704 | 1582 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1583 | |
1da177e4 | 1584 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1585 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1586 | } |
1587 | ||
511d934f AV |
1588 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1589 | { | |
1590 | u32 res; | |
1591 | ||
0977f817 | 1592 | /* Normaly TSEC should not hang on GRS commands, so we should |
511d934f AV |
1593 | * actually wait for IEVENT_GRSC flag. |
1594 | */ | |
1595 | if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) | |
1596 | return 0; | |
1597 | ||
0977f817 | 1598 | /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are |
511d934f AV |
1599 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle |
1600 | * and the Rx can be safely reset. | |
1601 | */ | |
1602 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1603 | res &= 0x7f807f80; | |
1604 | if ((res & 0xffff) == (res >> 16)) | |
1605 | return 1; | |
1606 | ||
1607 | return 0; | |
1608 | } | |
0bbaf069 KG |
1609 | |
1610 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1611 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1612 | { |
1613 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1614 | struct gfar __iomem *regs = NULL; |
1da177e4 | 1615 | u32 tempval; |
3a2e16c8 | 1616 | int i; |
1da177e4 | 1617 | |
46ceb60c SG |
1618 | for (i = 0; i < priv->num_grps; i++) { |
1619 | regs = priv->gfargrp[i].regs; | |
1620 | /* Mask all interrupts */ | |
1621 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1da177e4 | 1622 | |
46ceb60c SG |
1623 | /* Clear all interrupts */ |
1624 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1625 | } | |
1da177e4 | 1626 | |
46ceb60c | 1627 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1628 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1629 | tempval = gfar_read(®s->dmactrl); |
bc4598bc JC |
1630 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != |
1631 | (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1632 | int ret; |
1633 | ||
1da177e4 | 1634 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1635 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1636 | |
511d934f AV |
1637 | do { |
1638 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1639 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1640 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1641 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1642 | ret = __gfar_is_rx_idle(priv); | |
1643 | } while (!ret); | |
1da177e4 | 1644 | } |
d87eb127 | 1645 | } |
d87eb127 SW |
1646 | |
1647 | /* Halt the receive and transmit queues */ | |
1648 | void gfar_halt(struct net_device *dev) | |
1649 | { | |
1650 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1651 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1652 | u32 tempval; |
1da177e4 | 1653 | |
2a54adc3 SW |
1654 | gfar_halt_nodisable(dev); |
1655 | ||
1da177e4 LT |
1656 | /* Disable Rx and Tx */ |
1657 | tempval = gfar_read(®s->maccfg1); | |
1658 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1659 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1660 | } |
1661 | ||
46ceb60c SG |
1662 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1663 | { | |
ee873fda CM |
1664 | free_irq(gfar_irq(grp, TX)->irq, grp); |
1665 | free_irq(gfar_irq(grp, RX)->irq, grp); | |
1666 | free_irq(gfar_irq(grp, ER)->irq, grp); | |
46ceb60c SG |
1667 | } |
1668 | ||
0bbaf069 KG |
1669 | void stop_gfar(struct net_device *dev) |
1670 | { | |
1671 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1672 | unsigned long flags; |
46ceb60c | 1673 | int i; |
0bbaf069 | 1674 | |
bb40dcbb AF |
1675 | phy_stop(priv->phydev); |
1676 | ||
a12f801d | 1677 | |
0bbaf069 | 1678 | /* Lock it down */ |
fba4ed03 SG |
1679 | local_irq_save(flags); |
1680 | lock_tx_qs(priv); | |
1681 | lock_rx_qs(priv); | |
0bbaf069 | 1682 | |
0bbaf069 | 1683 | gfar_halt(dev); |
1da177e4 | 1684 | |
fba4ed03 SG |
1685 | unlock_rx_qs(priv); |
1686 | unlock_tx_qs(priv); | |
1687 | local_irq_restore(flags); | |
1da177e4 LT |
1688 | |
1689 | /* Free the IRQs */ | |
b31a1d8b | 1690 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1691 | for (i = 0; i < priv->num_grps; i++) |
1692 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1693 | } else { |
46ceb60c | 1694 | for (i = 0; i < priv->num_grps; i++) |
ee873fda | 1695 | free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, |
bc4598bc | 1696 | &priv->gfargrp[i]); |
1da177e4 LT |
1697 | } |
1698 | ||
1699 | free_skb_resources(priv); | |
1da177e4 LT |
1700 | } |
1701 | ||
fba4ed03 | 1702 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1703 | { |
1da177e4 | 1704 | struct txbd8 *txbdp; |
fba4ed03 | 1705 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1706 | int i, j; |
1da177e4 | 1707 | |
a12f801d | 1708 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1709 | |
a12f801d SG |
1710 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1711 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1712 | continue; |
1da177e4 | 1713 | |
369ec162 | 1714 | dma_unmap_single(priv->dev, txbdp->bufPtr, |
bc4598bc | 1715 | txbdp->length, DMA_TO_DEVICE); |
4669bc90 | 1716 | txbdp->lstatus = 0; |
fba4ed03 | 1717 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
bc4598bc | 1718 | j++) { |
4669bc90 | 1719 | txbdp++; |
369ec162 | 1720 | dma_unmap_page(priv->dev, txbdp->bufPtr, |
bc4598bc | 1721 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1722 | } |
ad5da7ab | 1723 | txbdp++; |
a12f801d SG |
1724 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1725 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1726 | } |
a12f801d | 1727 | kfree(tx_queue->tx_skbuff); |
1eb8f7a7 | 1728 | tx_queue->tx_skbuff = NULL; |
fba4ed03 | 1729 | } |
1da177e4 | 1730 | |
fba4ed03 SG |
1731 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1732 | { | |
1733 | struct rxbd8 *rxbdp; | |
1734 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1735 | int i; | |
1da177e4 | 1736 | |
fba4ed03 | 1737 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1738 | |
a12f801d SG |
1739 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1740 | if (rx_queue->rx_skbuff[i]) { | |
369ec162 CM |
1741 | dma_unmap_single(priv->dev, rxbdp->bufPtr, |
1742 | priv->rx_buffer_size, | |
bc4598bc | 1743 | DMA_FROM_DEVICE); |
a12f801d SG |
1744 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1745 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1746 | } |
e69edd21 AV |
1747 | rxbdp->lstatus = 0; |
1748 | rxbdp->bufPtr = 0; | |
1749 | rxbdp++; | |
1da177e4 | 1750 | } |
a12f801d | 1751 | kfree(rx_queue->rx_skbuff); |
1eb8f7a7 | 1752 | rx_queue->rx_skbuff = NULL; |
fba4ed03 | 1753 | } |
e69edd21 | 1754 | |
fba4ed03 | 1755 | /* If there are any tx skbs or rx skbs still around, free them. |
0977f817 JC |
1756 | * Then free tx_skbuff and rx_skbuff |
1757 | */ | |
fba4ed03 SG |
1758 | static void free_skb_resources(struct gfar_private *priv) |
1759 | { | |
1760 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1761 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1762 | int i; | |
1763 | ||
1764 | /* Go through all the buffer descriptors and free their data buffers */ | |
1765 | for (i = 0; i < priv->num_tx_queues; i++) { | |
d8a0f1b0 | 1766 | struct netdev_queue *txq; |
bc4598bc | 1767 | |
fba4ed03 | 1768 | tx_queue = priv->tx_queue[i]; |
d8a0f1b0 | 1769 | txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); |
bc4598bc | 1770 | if (tx_queue->tx_skbuff) |
fba4ed03 | 1771 | free_skb_tx_queue(tx_queue); |
d8a0f1b0 | 1772 | netdev_tx_reset_queue(txq); |
fba4ed03 SG |
1773 | } |
1774 | ||
1775 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1776 | rx_queue = priv->rx_queue[i]; | |
bc4598bc | 1777 | if (rx_queue->rx_skbuff) |
fba4ed03 SG |
1778 | free_skb_rx_queue(rx_queue); |
1779 | } | |
1780 | ||
369ec162 | 1781 | dma_free_coherent(priv->dev, |
bc4598bc JC |
1782 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
1783 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1784 | priv->tx_queue[0]->tx_bd_base, | |
1785 | priv->tx_queue[0]->tx_bd_dma_base); | |
1da177e4 LT |
1786 | } |
1787 | ||
0bbaf069 KG |
1788 | void gfar_start(struct net_device *dev) |
1789 | { | |
1790 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1791 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1792 | u32 tempval; |
46ceb60c | 1793 | int i = 0; |
0bbaf069 KG |
1794 | |
1795 | /* Enable Rx and Tx in MACCFG1 */ | |
1796 | tempval = gfar_read(®s->maccfg1); | |
1797 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1798 | gfar_write(®s->maccfg1, tempval); | |
1799 | ||
1800 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1801 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1802 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1803 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1804 | |
0bbaf069 | 1805 | /* Make sure we aren't stopped */ |
f4983704 | 1806 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1807 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1808 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1809 | |
46ceb60c SG |
1810 | for (i = 0; i < priv->num_grps; i++) { |
1811 | regs = priv->gfargrp[i].regs; | |
1812 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1813 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1814 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
1815 | /* Unmask the interrupts we look for */ | |
1816 | gfar_write(®s->imask, IMASK_DEFAULT); | |
1817 | } | |
12dea57b | 1818 | |
1ae5dc34 | 1819 | dev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1820 | } |
1821 | ||
800c644b | 1822 | static void gfar_configure_coalescing(struct gfar_private *priv, |
bc4598bc | 1823 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1824 | { |
46ceb60c | 1825 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1826 | u32 __iomem *baddr; |
815b97c6 | 1827 | |
46ceb60c | 1828 | if (priv->mode == MQ_MG_MODE) { |
5d9657d8 | 1829 | int i = 0; |
c6e1160e | 1830 | |
46ceb60c | 1831 | baddr = ®s->txic0; |
984b3f57 | 1832 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
9740e001 CM |
1833 | gfar_write(baddr + i, 0); |
1834 | if (likely(priv->tx_queue[i]->txcoalescing)) | |
46ceb60c | 1835 | gfar_write(baddr + i, priv->tx_queue[i]->txic); |
46ceb60c SG |
1836 | } |
1837 | ||
1838 | baddr = ®s->rxic0; | |
984b3f57 | 1839 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
9740e001 CM |
1840 | gfar_write(baddr + i, 0); |
1841 | if (likely(priv->rx_queue[i]->rxcoalescing)) | |
46ceb60c | 1842 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); |
46ceb60c | 1843 | } |
5d9657d8 | 1844 | } else { |
c6e1160e | 1845 | /* Backward compatible case -- even if we enable |
5d9657d8 CM |
1846 | * multiple queues, there's only single reg to program |
1847 | */ | |
1848 | gfar_write(®s->txic, 0); | |
1849 | if (likely(priv->tx_queue[0]->txcoalescing)) | |
1850 | gfar_write(®s->txic, priv->tx_queue[0]->txic); | |
1851 | ||
1852 | gfar_write(®s->rxic, 0); | |
1853 | if (unlikely(priv->rx_queue[0]->rxcoalescing)) | |
1854 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); | |
46ceb60c SG |
1855 | } |
1856 | } | |
1857 | ||
800c644b CM |
1858 | void gfar_configure_coalescing_all(struct gfar_private *priv) |
1859 | { | |
1860 | gfar_configure_coalescing(priv, 0xFF, 0xFF); | |
1861 | } | |
1862 | ||
46ceb60c SG |
1863 | static int register_grp_irqs(struct gfar_priv_grp *grp) |
1864 | { | |
1865 | struct gfar_private *priv = grp->priv; | |
1866 | struct net_device *dev = priv->ndev; | |
1867 | int err; | |
1da177e4 | 1868 | |
1da177e4 | 1869 | /* If the device has multiple interrupts, register for |
0977f817 JC |
1870 | * them. Otherwise, only register for the one |
1871 | */ | |
b31a1d8b | 1872 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1873 | /* Install our interrupt handlers for Error, |
0977f817 JC |
1874 | * Transmit, and Receive |
1875 | */ | |
ee873fda CM |
1876 | err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, |
1877 | gfar_irq(grp, ER)->name, grp); | |
1878 | if (err < 0) { | |
59deab26 | 1879 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1880 | gfar_irq(grp, ER)->irq); |
46ceb60c | 1881 | |
2145f1af | 1882 | goto err_irq_fail; |
1da177e4 | 1883 | } |
ee873fda CM |
1884 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, |
1885 | gfar_irq(grp, TX)->name, grp); | |
1886 | if (err < 0) { | |
59deab26 | 1887 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1888 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1889 | goto tx_irq_fail; |
1890 | } | |
ee873fda CM |
1891 | err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, |
1892 | gfar_irq(grp, RX)->name, grp); | |
1893 | if (err < 0) { | |
59deab26 | 1894 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1895 | gfar_irq(grp, RX)->irq); |
1da177e4 LT |
1896 | goto rx_irq_fail; |
1897 | } | |
1898 | } else { | |
ee873fda CM |
1899 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, |
1900 | gfar_irq(grp, TX)->name, grp); | |
1901 | if (err < 0) { | |
59deab26 | 1902 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1903 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1904 | goto err_irq_fail; |
1905 | } | |
1906 | } | |
1907 | ||
46ceb60c SG |
1908 | return 0; |
1909 | ||
1910 | rx_irq_fail: | |
ee873fda | 1911 | free_irq(gfar_irq(grp, TX)->irq, grp); |
46ceb60c | 1912 | tx_irq_fail: |
ee873fda | 1913 | free_irq(gfar_irq(grp, ER)->irq, grp); |
46ceb60c SG |
1914 | err_irq_fail: |
1915 | return err; | |
1916 | ||
1917 | } | |
1918 | ||
1919 | /* Bring the controller up and running */ | |
1920 | int startup_gfar(struct net_device *ndev) | |
1921 | { | |
1922 | struct gfar_private *priv = netdev_priv(ndev); | |
1923 | struct gfar __iomem *regs = NULL; | |
1924 | int err, i, j; | |
1925 | ||
1926 | for (i = 0; i < priv->num_grps; i++) { | |
1927 | regs= priv->gfargrp[i].regs; | |
1928 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1929 | } | |
1930 | ||
1931 | regs= priv->gfargrp[0].regs; | |
1932 | err = gfar_alloc_skb_resources(ndev); | |
1933 | if (err) | |
1934 | return err; | |
1935 | ||
1936 | gfar_init_mac(ndev); | |
1937 | ||
1938 | for (i = 0; i < priv->num_grps; i++) { | |
1939 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1940 | if (err) { | |
1941 | for (j = 0; j < i; j++) | |
1942 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1943 | goto irq_fail; |
46ceb60c SG |
1944 | } |
1945 | } | |
1946 | ||
7f7f5316 | 1947 | /* Start the controller */ |
ccc05c6e | 1948 | gfar_start(ndev); |
1da177e4 | 1949 | |
826aa4a0 AV |
1950 | phy_start(priv->phydev); |
1951 | ||
800c644b | 1952 | gfar_configure_coalescing_all(priv); |
46ceb60c | 1953 | |
1da177e4 LT |
1954 | return 0; |
1955 | ||
46ceb60c | 1956 | irq_fail: |
e69edd21 | 1957 | free_skb_resources(priv); |
1da177e4 LT |
1958 | return err; |
1959 | } | |
1960 | ||
0977f817 JC |
1961 | /* Called when something needs to use the ethernet device |
1962 | * Returns 0 for success. | |
1963 | */ | |
1da177e4 LT |
1964 | static int gfar_enet_open(struct net_device *dev) |
1965 | { | |
94e8cc35 | 1966 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1967 | int err; |
1968 | ||
46ceb60c | 1969 | enable_napi(priv); |
bea3348e | 1970 | |
1da177e4 LT |
1971 | /* Initialize a bunch of registers */ |
1972 | init_registers(dev); | |
1973 | ||
1974 | gfar_set_mac_address(dev); | |
1975 | ||
1976 | err = init_phy(dev); | |
1977 | ||
a12f801d | 1978 | if (err) { |
46ceb60c | 1979 | disable_napi(priv); |
1da177e4 | 1980 | return err; |
bea3348e | 1981 | } |
1da177e4 LT |
1982 | |
1983 | err = startup_gfar(dev); | |
db0e8e3f | 1984 | if (err) { |
46ceb60c | 1985 | disable_napi(priv); |
db0e8e3f AV |
1986 | return err; |
1987 | } | |
1da177e4 | 1988 | |
fba4ed03 | 1989 | netif_tx_start_all_queues(dev); |
1da177e4 | 1990 | |
2884e5cc AV |
1991 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1992 | ||
1da177e4 LT |
1993 | return err; |
1994 | } | |
1995 | ||
54dc79fe | 1996 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1997 | { |
54dc79fe | 1998 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1999 | |
2000 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 2001 | |
0bbaf069 KG |
2002 | return fcb; |
2003 | } | |
2004 | ||
9c4886e5 | 2005 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, |
bc4598bc | 2006 | int fcb_length) |
0bbaf069 | 2007 | { |
0bbaf069 KG |
2008 | /* If we're here, it's a IP packet with a TCP or UDP |
2009 | * payload. We set it to checksum, using a pseudo-header | |
2010 | * we provide | |
2011 | */ | |
3a2e16c8 | 2012 | u8 flags = TXFCB_DEFAULT; |
0bbaf069 | 2013 | |
0977f817 JC |
2014 | /* Tell the controller what the protocol is |
2015 | * And provide the already calculated phcs | |
2016 | */ | |
eddc9ec5 | 2017 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 2018 | flags |= TXFCB_UDP; |
4bedb452 | 2019 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 2020 | } else |
8da32de5 | 2021 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
2022 | |
2023 | /* l3os is the distance between the start of the | |
2024 | * frame (skb->data) and the start of the IP hdr. | |
2025 | * l4os is the distance between the start of the | |
0977f817 JC |
2026 | * l3 hdr and the l4 hdr |
2027 | */ | |
9c4886e5 | 2028 | fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); |
cfe1fc77 | 2029 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 2030 | |
7f7f5316 | 2031 | fcb->flags = flags; |
0bbaf069 KG |
2032 | } |
2033 | ||
7f7f5316 | 2034 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 2035 | { |
7f7f5316 | 2036 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2037 | fcb->vlctl = vlan_tx_tag_get(skb); |
2038 | } | |
2039 | ||
4669bc90 | 2040 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
bc4598bc | 2041 | struct txbd8 *base, int ring_size) |
4669bc90 DH |
2042 | { |
2043 | struct txbd8 *new_bd = bdp + stride; | |
2044 | ||
2045 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2046 | } | |
2047 | ||
2048 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
bc4598bc | 2049 | int ring_size) |
4669bc90 DH |
2050 | { |
2051 | return skip_txbd(bdp, 1, base, ring_size); | |
2052 | } | |
2053 | ||
0977f817 JC |
2054 | /* This is called by the kernel when a frame is ready for transmission. |
2055 | * It is pointed to by the dev->hard_start_xmit function pointer | |
2056 | */ | |
1da177e4 LT |
2057 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2058 | { | |
2059 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2060 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2061 | struct netdev_queue *txq; |
f4983704 | 2062 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2063 | struct txfcb *fcb = NULL; |
f0ee7acf | 2064 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2065 | u32 lstatus; |
f0ee7acf | 2066 | int i, rq = 0, do_tstamp = 0; |
4669bc90 | 2067 | u32 bufaddr; |
fef6108d | 2068 | unsigned long flags; |
9c4886e5 | 2069 | unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN; |
fba4ed03 | 2070 | |
0977f817 | 2071 | /* TOE=1 frames larger than 2500 bytes may see excess delays |
deb90eac AV |
2072 | * before start of transmission. |
2073 | */ | |
2074 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) && | |
bc4598bc JC |
2075 | skb->ip_summed == CHECKSUM_PARTIAL && |
2076 | skb->len > 2500)) { | |
deb90eac AV |
2077 | int ret; |
2078 | ||
2079 | ret = skb_checksum_help(skb); | |
2080 | if (ret) | |
2081 | return ret; | |
2082 | } | |
2083 | ||
fba4ed03 SG |
2084 | rq = skb->queue_mapping; |
2085 | tx_queue = priv->tx_queue[rq]; | |
2086 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2087 | base = tx_queue->tx_bd_base; |
46ceb60c | 2088 | regs = tx_queue->grp->regs; |
f0ee7acf MR |
2089 | |
2090 | /* check if time stamp should be generated */ | |
2244d07b | 2091 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
bc4598bc | 2092 | priv->hwts_tx_en)) { |
f0ee7acf | 2093 | do_tstamp = 1; |
9c4886e5 MR |
2094 | fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
2095 | } | |
4669bc90 | 2096 | |
5b28beaf LY |
2097 | /* make space for additional header when fcb is needed */ |
2098 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
bc4598bc JC |
2099 | vlan_tx_tag_present(skb) || |
2100 | unlikely(do_tstamp)) && | |
2101 | (skb_headroom(skb) < fcb_length)) { | |
54dc79fe SH |
2102 | struct sk_buff *skb_new; |
2103 | ||
9c4886e5 | 2104 | skb_new = skb_realloc_headroom(skb, fcb_length); |
54dc79fe SH |
2105 | if (!skb_new) { |
2106 | dev->stats.tx_errors++; | |
bd14ba84 | 2107 | kfree_skb(skb); |
54dc79fe SH |
2108 | return NETDEV_TX_OK; |
2109 | } | |
db83d136 | 2110 | |
313b037c ED |
2111 | if (skb->sk) |
2112 | skb_set_owner_w(skb_new, skb->sk); | |
2113 | consume_skb(skb); | |
54dc79fe SH |
2114 | skb = skb_new; |
2115 | } | |
2116 | ||
4669bc90 DH |
2117 | /* total number of fragments in the SKB */ |
2118 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2119 | ||
f0ee7acf MR |
2120 | /* calculate the required number of TxBDs for this skb */ |
2121 | if (unlikely(do_tstamp)) | |
2122 | nr_txbds = nr_frags + 2; | |
2123 | else | |
2124 | nr_txbds = nr_frags + 1; | |
2125 | ||
4669bc90 | 2126 | /* check if there is space to queue this packet */ |
f0ee7acf | 2127 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2128 | /* no space, stop the queue */ |
fba4ed03 | 2129 | netif_tx_stop_queue(txq); |
4669bc90 | 2130 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2131 | return NETDEV_TX_BUSY; |
2132 | } | |
1da177e4 LT |
2133 | |
2134 | /* Update transmit stats */ | |
1ac9ad13 ED |
2135 | tx_queue->stats.tx_bytes += skb->len; |
2136 | tx_queue->stats.tx_packets++; | |
1da177e4 | 2137 | |
a12f801d | 2138 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2139 | lstatus = txbdp->lstatus; |
2140 | ||
2141 | /* Time stamp insertion requires one additional TxBD */ | |
2142 | if (unlikely(do_tstamp)) | |
2143 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
bc4598bc | 2144 | tx_queue->tx_ring_size); |
1da177e4 | 2145 | |
4669bc90 | 2146 | if (nr_frags == 0) { |
f0ee7acf MR |
2147 | if (unlikely(do_tstamp)) |
2148 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
bc4598bc | 2149 | TXBD_INTERRUPT); |
f0ee7acf MR |
2150 | else |
2151 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2152 | } else { |
2153 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2154 | for (i = 0; i < nr_frags; i++) { | |
2155 | /* Point at the next BD, wrapping as needed */ | |
a12f801d | 2156 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2157 | |
2158 | length = skb_shinfo(skb)->frags[i].size; | |
2159 | ||
2160 | lstatus = txbdp->lstatus | length | | |
bc4598bc | 2161 | BD_LFLAG(TXBD_READY); |
4669bc90 DH |
2162 | |
2163 | /* Handle the last BD specially */ | |
2164 | if (i == nr_frags - 1) | |
2165 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2166 | |
369ec162 | 2167 | bufaddr = skb_frag_dma_map(priv->dev, |
2234a722 IC |
2168 | &skb_shinfo(skb)->frags[i], |
2169 | 0, | |
2170 | length, | |
2171 | DMA_TO_DEVICE); | |
4669bc90 DH |
2172 | |
2173 | /* set the TxBD length and buffer pointer */ | |
2174 | txbdp->bufPtr = bufaddr; | |
2175 | txbdp->lstatus = lstatus; | |
2176 | } | |
2177 | ||
2178 | lstatus = txbdp_start->lstatus; | |
2179 | } | |
1da177e4 | 2180 | |
9c4886e5 MR |
2181 | /* Add TxPAL between FCB and frame if required */ |
2182 | if (unlikely(do_tstamp)) { | |
2183 | skb_push(skb, GMAC_TXPAL_LEN); | |
2184 | memset(skb->data, 0, GMAC_TXPAL_LEN); | |
2185 | } | |
2186 | ||
0bbaf069 | 2187 | /* Set up checksumming */ |
12dea57b | 2188 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe | 2189 | fcb = gfar_add_fcb(skb); |
4363c2fd | 2190 | /* as specified by errata */ |
bc4598bc JC |
2191 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) && |
2192 | ((unsigned long)fcb % 0x20) > 0x18)) { | |
4363c2fd AD |
2193 | __skb_pull(skb, GMAC_FCB_LEN); |
2194 | skb_checksum_help(skb); | |
2195 | } else { | |
2196 | lstatus |= BD_LFLAG(TXBD_TOE); | |
9c4886e5 | 2197 | gfar_tx_checksum(skb, fcb, fcb_length); |
4363c2fd | 2198 | } |
0bbaf069 KG |
2199 | } |
2200 | ||
eab6d18d | 2201 | if (vlan_tx_tag_present(skb)) { |
54dc79fe SH |
2202 | if (unlikely(NULL == fcb)) { |
2203 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 2204 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 2205 | } |
54dc79fe SH |
2206 | |
2207 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
2208 | } |
2209 | ||
f0ee7acf MR |
2210 | /* Setup tx hardware time stamping if requested */ |
2211 | if (unlikely(do_tstamp)) { | |
2244d07b | 2212 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf MR |
2213 | if (fcb == NULL) |
2214 | fcb = gfar_add_fcb(skb); | |
2215 | fcb->ptp = 1; | |
2216 | lstatus |= BD_LFLAG(TXBD_TOE); | |
2217 | } | |
2218 | ||
369ec162 | 2219 | txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data, |
bc4598bc | 2220 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2221 | |
0977f817 | 2222 | /* If time stamping is requested one additional TxBD must be set up. The |
f0ee7acf MR |
2223 | * first TxBD points to the FCB and must have a data length of |
2224 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2225 | * the full frame length. | |
2226 | */ | |
2227 | if (unlikely(do_tstamp)) { | |
9c4886e5 | 2228 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length; |
f0ee7acf | 2229 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | |
bc4598bc | 2230 | (skb_headlen(skb) - fcb_length); |
f0ee7acf MR |
2231 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; |
2232 | } else { | |
2233 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2234 | } | |
1da177e4 | 2235 | |
d8a0f1b0 PG |
2236 | netdev_tx_sent_queue(txq, skb->len); |
2237 | ||
0977f817 | 2238 | /* We can work in parallel with gfar_clean_tx_ring(), except |
a3bc1f11 AV |
2239 | * when modifying num_txbdfree. Note that we didn't grab the lock |
2240 | * when we were reading the num_txbdfree and checking for available | |
2241 | * space, that's because outside of this function it can only grow, | |
2242 | * and once we've got needed space, it cannot suddenly disappear. | |
2243 | * | |
2244 | * The lock also protects us from gfar_error(), which can modify | |
2245 | * regs->tstat and thus retrigger the transfers, which is why we | |
2246 | * also must grab the lock before setting ready bit for the first | |
2247 | * to be transmitted BD. | |
2248 | */ | |
2249 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2250 | ||
0977f817 | 2251 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
3b6330ce SW |
2252 | * semantics (it requires synchronization between cacheable and |
2253 | * uncacheable mappings, which eieio doesn't provide and which we | |
2254 | * don't need), thus requiring a more expensive sync instruction. At | |
2255 | * some point, the set of architecture-independent barrier functions | |
2256 | * should be expanded to include weaker barriers. | |
2257 | */ | |
3b6330ce | 2258 | eieio(); |
7f7f5316 | 2259 | |
4669bc90 DH |
2260 | txbdp_start->lstatus = lstatus; |
2261 | ||
0eddba52 AV |
2262 | eieio(); /* force lstatus write before tx_skbuff */ |
2263 | ||
2264 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2265 | ||
4669bc90 | 2266 | /* Update the current skb pointer to the next entry we will use |
0977f817 JC |
2267 | * (wrapping if necessary) |
2268 | */ | |
a12f801d | 2269 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
bc4598bc | 2270 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); |
4669bc90 | 2271 | |
a12f801d | 2272 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2273 | |
2274 | /* reduce TxBD free count */ | |
f0ee7acf | 2275 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2276 | |
2277 | /* If the next BD still needs to be cleaned up, then the bds | |
0977f817 JC |
2278 | * are full. We need to tell the kernel to stop sending us stuff. |
2279 | */ | |
a12f801d | 2280 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2281 | netif_tx_stop_queue(txq); |
1da177e4 | 2282 | |
09f75cd7 | 2283 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2284 | } |
2285 | ||
1da177e4 | 2286 | /* Tell the DMA to go go go */ |
fba4ed03 | 2287 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2288 | |
2289 | /* Unlock priv */ | |
a12f801d | 2290 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2291 | |
54dc79fe | 2292 | return NETDEV_TX_OK; |
1da177e4 LT |
2293 | } |
2294 | ||
2295 | /* Stops the kernel queue, and halts the controller */ | |
2296 | static int gfar_close(struct net_device *dev) | |
2297 | { | |
2298 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2299 | |
46ceb60c | 2300 | disable_napi(priv); |
bea3348e | 2301 | |
ab939905 | 2302 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2303 | stop_gfar(dev); |
2304 | ||
bb40dcbb AF |
2305 | /* Disconnect from the PHY */ |
2306 | phy_disconnect(priv->phydev); | |
2307 | priv->phydev = NULL; | |
1da177e4 | 2308 | |
fba4ed03 | 2309 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2310 | |
2311 | return 0; | |
2312 | } | |
2313 | ||
1da177e4 | 2314 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2315 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2316 | { |
7f7f5316 | 2317 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2318 | |
2319 | return 0; | |
2320 | } | |
2321 | ||
f3dc1586 SP |
2322 | /* Check if rx parser should be activated */ |
2323 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2324 | { | |
2325 | struct gfar __iomem *regs; | |
2326 | u32 tempval; | |
2327 | ||
2328 | regs = priv->gfargrp[0].regs; | |
2329 | ||
2330 | tempval = gfar_read(®s->rctrl); | |
2331 | /* If parse is no longer required, then disable parser */ | |
ba779711 | 2332 | if (tempval & RCTRL_REQ_PARSER) { |
f3dc1586 | 2333 | tempval |= RCTRL_PRSDEP_INIT; |
ba779711 CM |
2334 | priv->uses_rxfcb = 1; |
2335 | } else { | |
f3dc1586 | 2336 | tempval &= ~RCTRL_PRSDEP_INIT; |
ba779711 CM |
2337 | priv->uses_rxfcb = 0; |
2338 | } | |
f3dc1586 SP |
2339 | gfar_write(®s->rctrl, tempval); |
2340 | } | |
2341 | ||
0bbaf069 | 2342 | /* Enables and disables VLAN insertion/extraction */ |
c8f44aff | 2343 | void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) |
0bbaf069 KG |
2344 | { |
2345 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2346 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2347 | unsigned long flags; |
2348 | u32 tempval; | |
2349 | ||
46ceb60c | 2350 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2351 | local_irq_save(flags); |
2352 | lock_rx_qs(priv); | |
0bbaf069 | 2353 | |
f646968f | 2354 | if (features & NETIF_F_HW_VLAN_CTAG_TX) { |
0bbaf069 | 2355 | /* Enable VLAN tag insertion */ |
f4983704 | 2356 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2357 | tempval |= TCTRL_VLINS; |
f4983704 | 2358 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2359 | } else { |
2360 | /* Disable VLAN tag insertion */ | |
f4983704 | 2361 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2362 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2363 | gfar_write(®s->tctrl, tempval); |
87c288c6 | 2364 | } |
0bbaf069 | 2365 | |
f646968f | 2366 | if (features & NETIF_F_HW_VLAN_CTAG_RX) { |
87c288c6 JP |
2367 | /* Enable VLAN tag extraction */ |
2368 | tempval = gfar_read(®s->rctrl); | |
2369 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); | |
2370 | gfar_write(®s->rctrl, tempval); | |
ba779711 | 2371 | priv->uses_rxfcb = 1; |
87c288c6 | 2372 | } else { |
0bbaf069 | 2373 | /* Disable VLAN tag extraction */ |
f4983704 | 2374 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2375 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2376 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2377 | |
2378 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2379 | } |
2380 | ||
77ecaf2d DH |
2381 | gfar_change_mtu(dev, dev->mtu); |
2382 | ||
fba4ed03 SG |
2383 | unlock_rx_qs(priv); |
2384 | local_irq_restore(flags); | |
0bbaf069 KG |
2385 | } |
2386 | ||
1da177e4 LT |
2387 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2388 | { | |
2389 | int tempsize, tempval; | |
2390 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2391 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2392 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2393 | int frame_size = new_mtu + ETH_HLEN; |
2394 | ||
1da177e4 | 2395 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
59deab26 | 2396 | netif_err(priv, drv, dev, "Invalid MTU setting\n"); |
1da177e4 LT |
2397 | return -EINVAL; |
2398 | } | |
2399 | ||
ba779711 | 2400 | if (priv->uses_rxfcb) |
77ecaf2d DH |
2401 | frame_size += GMAC_FCB_LEN; |
2402 | ||
2403 | frame_size += priv->padding; | |
2404 | ||
bc4598bc JC |
2405 | tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + |
2406 | INCREMENTAL_BUFFER_SIZE; | |
1da177e4 LT |
2407 | |
2408 | /* Only stop and start the controller if it isn't already | |
0977f817 JC |
2409 | * stopped, and we changed something |
2410 | */ | |
1da177e4 LT |
2411 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2412 | stop_gfar(dev); | |
2413 | ||
2414 | priv->rx_buffer_size = tempsize; | |
2415 | ||
2416 | dev->mtu = new_mtu; | |
2417 | ||
f4983704 SG |
2418 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2419 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2420 | |
2421 | /* If the mtu is larger than the max size for standard | |
2422 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
0977f817 JC |
2423 | * to allow huge frames, and to check the length |
2424 | */ | |
f4983704 | 2425 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2426 | |
7d350977 | 2427 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
bc4598bc | 2428 | gfar_has_errata(priv, GFAR_ERRATA_74)) |
1da177e4 LT |
2429 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2430 | else | |
2431 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2432 | ||
f4983704 | 2433 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2434 | |
2435 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2436 | startup_gfar(dev); | |
2437 | ||
2438 | return 0; | |
2439 | } | |
2440 | ||
ab939905 | 2441 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2442 | * transmitted after a set amount of time. |
2443 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2444 | * starting over will fix the problem. |
2445 | */ | |
2446 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2447 | { |
ab939905 | 2448 | struct gfar_private *priv = container_of(work, struct gfar_private, |
bc4598bc | 2449 | reset_task); |
4826857f | 2450 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2451 | |
2452 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2453 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2454 | stop_gfar(dev); |
2455 | startup_gfar(dev); | |
fba4ed03 | 2456 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2457 | } |
2458 | ||
263ba320 | 2459 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2460 | } |
2461 | ||
ab939905 SS |
2462 | static void gfar_timeout(struct net_device *dev) |
2463 | { | |
2464 | struct gfar_private *priv = netdev_priv(dev); | |
2465 | ||
2466 | dev->stats.tx_errors++; | |
2467 | schedule_work(&priv->reset_task); | |
2468 | } | |
2469 | ||
acbc0f03 EL |
2470 | static void gfar_align_skb(struct sk_buff *skb) |
2471 | { | |
2472 | /* We need the data buffer to be aligned properly. We will reserve | |
2473 | * as many bytes as needed to align the data properly | |
2474 | */ | |
2475 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
bc4598bc | 2476 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); |
acbc0f03 EL |
2477 | } |
2478 | ||
1da177e4 | 2479 | /* Interrupt Handler for Transmit complete */ |
c233cf40 | 2480 | static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2481 | { |
a12f801d | 2482 | struct net_device *dev = tx_queue->dev; |
d8a0f1b0 | 2483 | struct netdev_queue *txq; |
d080cd63 | 2484 | struct gfar_private *priv = netdev_priv(dev); |
f0ee7acf | 2485 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2486 | struct txbd8 *lbdp = NULL; |
a12f801d | 2487 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2488 | struct sk_buff *skb; |
2489 | int skb_dirtytx; | |
a12f801d | 2490 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2491 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2492 | int i; |
d080cd63 | 2493 | int howmany = 0; |
d8a0f1b0 PG |
2494 | int tqi = tx_queue->qindex; |
2495 | unsigned int bytes_sent = 0; | |
4669bc90 | 2496 | u32 lstatus; |
f0ee7acf | 2497 | size_t buflen; |
1da177e4 | 2498 | |
d8a0f1b0 | 2499 | txq = netdev_get_tx_queue(dev, tqi); |
a12f801d SG |
2500 | bdp = tx_queue->dirty_tx; |
2501 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2502 | |
a12f801d | 2503 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2504 | unsigned long flags; |
2505 | ||
4669bc90 | 2506 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf | 2507 | |
0977f817 | 2508 | /* When time stamping, one additional TxBD must be freed. |
f0ee7acf MR |
2509 | * Also, we need to dma_unmap_single() the TxPAL. |
2510 | */ | |
2244d07b | 2511 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2512 | nr_txbds = frags + 2; |
2513 | else | |
2514 | nr_txbds = frags + 1; | |
2515 | ||
2516 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2517 | |
4669bc90 | 2518 | lstatus = lbdp->lstatus; |
1da177e4 | 2519 | |
4669bc90 DH |
2520 | /* Only clean completed frames */ |
2521 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
bc4598bc | 2522 | (lstatus & BD_LENGTH_MASK)) |
4669bc90 DH |
2523 | break; |
2524 | ||
2244d07b | 2525 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf | 2526 | next = next_txbd(bdp, base, tx_ring_size); |
9c4886e5 | 2527 | buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
f0ee7acf MR |
2528 | } else |
2529 | buflen = bdp->length; | |
2530 | ||
369ec162 | 2531 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2532 | buflen, DMA_TO_DEVICE); |
f0ee7acf | 2533 | |
2244d07b | 2534 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2535 | struct skb_shared_hwtstamps shhwtstamps; |
2536 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
bc4598bc | 2537 | |
f0ee7acf MR |
2538 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
2539 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
9c4886e5 | 2540 | skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); |
f0ee7acf MR |
2541 | skb_tstamp_tx(skb, &shhwtstamps); |
2542 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2543 | bdp = next; | |
2544 | } | |
81183059 | 2545 | |
4669bc90 DH |
2546 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2547 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2548 | |
4669bc90 | 2549 | for (i = 0; i < frags; i++) { |
369ec162 | 2550 | dma_unmap_page(priv->dev, bdp->bufPtr, |
bc4598bc | 2551 | bdp->length, DMA_TO_DEVICE); |
4669bc90 DH |
2552 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2553 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2554 | } | |
1da177e4 | 2555 | |
d8a0f1b0 PG |
2556 | bytes_sent += skb->len; |
2557 | ||
acb600de | 2558 | dev_kfree_skb_any(skb); |
0fd56bb5 | 2559 | |
a12f801d | 2560 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2561 | |
4669bc90 | 2562 | skb_dirtytx = (skb_dirtytx + 1) & |
bc4598bc | 2563 | TX_RING_MOD_MASK(tx_ring_size); |
4669bc90 DH |
2564 | |
2565 | howmany++; | |
a3bc1f11 | 2566 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2567 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2568 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2569 | } |
1da177e4 | 2570 | |
4669bc90 | 2571 | /* If we freed a buffer, we can restart transmission, if necessary */ |
5407b14c | 2572 | if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) |
d8a0f1b0 | 2573 | netif_wake_subqueue(dev, tqi); |
1da177e4 | 2574 | |
4669bc90 | 2575 | /* Update dirty indicators */ |
a12f801d SG |
2576 | tx_queue->skb_dirtytx = skb_dirtytx; |
2577 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2578 | |
d8a0f1b0 | 2579 | netdev_tx_completed_queue(txq, howmany, bytes_sent); |
d080cd63 DH |
2580 | } |
2581 | ||
f4983704 | 2582 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2583 | { |
a6d0b91a AV |
2584 | unsigned long flags; |
2585 | ||
fba4ed03 SG |
2586 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2587 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2588 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2589 | __napi_schedule(&gfargrp->napi); |
8707bdd4 | 2590 | } else { |
0977f817 | 2591 | /* Clear IEVENT, so interrupts aren't called again |
8707bdd4 JP |
2592 | * because of the packets that have already arrived. |
2593 | */ | |
f4983704 | 2594 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2595 | } |
fba4ed03 | 2596 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2597 | |
8c7396ae | 2598 | } |
1da177e4 | 2599 | |
8c7396ae | 2600 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2601 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2602 | { |
f4983704 | 2603 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2604 | return IRQ_HANDLED; |
2605 | } | |
2606 | ||
a12f801d | 2607 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 2608 | struct sk_buff *skb) |
815b97c6 | 2609 | { |
a12f801d | 2610 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2611 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2612 | dma_addr_t buf; |
815b97c6 | 2613 | |
369ec162 | 2614 | buf = dma_map_single(priv->dev, skb->data, |
8a102fe0 | 2615 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
a12f801d | 2616 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2617 | } |
2618 | ||
2281a0f3 | 2619 | static struct sk_buff *gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2620 | { |
2621 | struct gfar_private *priv = netdev_priv(dev); | |
acb600de | 2622 | struct sk_buff *skb; |
1da177e4 | 2623 | |
acbc0f03 | 2624 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2625 | if (!skb) |
1da177e4 LT |
2626 | return NULL; |
2627 | ||
acbc0f03 | 2628 | gfar_align_skb(skb); |
7f7f5316 | 2629 | |
acbc0f03 EL |
2630 | return skb; |
2631 | } | |
2632 | ||
2281a0f3 | 2633 | struct sk_buff *gfar_new_skb(struct net_device *dev) |
acbc0f03 | 2634 | { |
acb600de | 2635 | return gfar_alloc_skb(dev); |
1da177e4 LT |
2636 | } |
2637 | ||
298e1a9e | 2638 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2639 | { |
298e1a9e | 2640 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2641 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2642 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2643 | ||
0977f817 | 2644 | /* If the packet was truncated, none of the other errors matter */ |
1da177e4 LT |
2645 | if (status & RXBD_TRUNCATED) { |
2646 | stats->rx_length_errors++; | |
2647 | ||
212079df | 2648 | atomic64_inc(&estats->rx_trunc); |
1da177e4 LT |
2649 | |
2650 | return; | |
2651 | } | |
2652 | /* Count the errors, if there were any */ | |
2653 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2654 | stats->rx_length_errors++; | |
2655 | ||
2656 | if (status & RXBD_LARGE) | |
212079df | 2657 | atomic64_inc(&estats->rx_large); |
1da177e4 | 2658 | else |
212079df | 2659 | atomic64_inc(&estats->rx_short); |
1da177e4 LT |
2660 | } |
2661 | if (status & RXBD_NONOCTET) { | |
2662 | stats->rx_frame_errors++; | |
212079df | 2663 | atomic64_inc(&estats->rx_nonoctet); |
1da177e4 LT |
2664 | } |
2665 | if (status & RXBD_CRCERR) { | |
212079df | 2666 | atomic64_inc(&estats->rx_crcerr); |
1da177e4 LT |
2667 | stats->rx_crc_errors++; |
2668 | } | |
2669 | if (status & RXBD_OVERRUN) { | |
212079df | 2670 | atomic64_inc(&estats->rx_overrun); |
1da177e4 LT |
2671 | stats->rx_crc_errors++; |
2672 | } | |
2673 | } | |
2674 | ||
f4983704 | 2675 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2676 | { |
f4983704 | 2677 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2678 | return IRQ_HANDLED; |
2679 | } | |
2680 | ||
0bbaf069 KG |
2681 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2682 | { | |
2683 | /* If valid headers were found, and valid sums | |
2684 | * were verified, then we tell the kernel that no | |
0977f817 JC |
2685 | * checksumming is necessary. Otherwise, it is [FIXME] |
2686 | */ | |
7f7f5316 | 2687 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2688 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2689 | else | |
bc8acf2c | 2690 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2691 | } |
2692 | ||
2693 | ||
0977f817 | 2694 | /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ |
61db26c6 CM |
2695 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
2696 | int amount_pull, struct napi_struct *napi) | |
1da177e4 LT |
2697 | { |
2698 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2699 | struct rxfcb *fcb = NULL; |
1da177e4 | 2700 | |
2c2db48a DH |
2701 | /* fcb is at the beginning if exists */ |
2702 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2703 | |
0977f817 JC |
2704 | /* Remove the FCB from the skb |
2705 | * Remove the padded bytes, if there are any | |
2706 | */ | |
f74dac08 SG |
2707 | if (amount_pull) { |
2708 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2709 | skb_pull(skb, amount_pull); |
f74dac08 | 2710 | } |
0bbaf069 | 2711 | |
cc772ab7 MR |
2712 | /* Get receive timestamp from the skb */ |
2713 | if (priv->hwts_rx_en) { | |
2714 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2715 | u64 *ns = (u64 *) skb->data; | |
bc4598bc | 2716 | |
cc772ab7 MR |
2717 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2718 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2719 | } | |
2720 | ||
2721 | if (priv->padding) | |
2722 | skb_pull(skb, priv->padding); | |
2723 | ||
8b3afe95 | 2724 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2725 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2726 | |
2c2db48a DH |
2727 | /* Tell the skb what kind of packet this is */ |
2728 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2729 | |
f646968f | 2730 | /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. |
32f7fd44 JP |
2731 | * Even if vlan rx accel is disabled, on some chips |
2732 | * RXFCB_VLN is pseudo randomly set. | |
2733 | */ | |
f646968f | 2734 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && |
32f7fd44 | 2735 | fcb->flags & RXFCB_VLN) |
e5905c83 | 2736 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl); |
87c288c6 | 2737 | |
2c2db48a | 2738 | /* Send the packet up the stack */ |
953d2768 | 2739 | napi_gro_receive(napi, skb); |
0bbaf069 | 2740 | |
1da177e4 LT |
2741 | } |
2742 | ||
2743 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
2281a0f3 JC |
2744 | * until the budget/quota has been reached. Returns the number |
2745 | * of frames handled | |
1da177e4 | 2746 | */ |
a12f801d | 2747 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2748 | { |
a12f801d | 2749 | struct net_device *dev = rx_queue->dev; |
31de198b | 2750 | struct rxbd8 *bdp, *base; |
1da177e4 | 2751 | struct sk_buff *skb; |
2c2db48a DH |
2752 | int pkt_len; |
2753 | int amount_pull; | |
1da177e4 LT |
2754 | int howmany = 0; |
2755 | struct gfar_private *priv = netdev_priv(dev); | |
2756 | ||
2757 | /* Get the first full descriptor */ | |
a12f801d SG |
2758 | bdp = rx_queue->cur_rx; |
2759 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2760 | |
ba779711 | 2761 | amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0; |
2c2db48a | 2762 | |
1da177e4 | 2763 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2764 | struct sk_buff *newskb; |
bc4598bc | 2765 | |
3b6330ce | 2766 | rmb(); |
815b97c6 AF |
2767 | |
2768 | /* Add another skb for the future */ | |
2769 | newskb = gfar_new_skb(dev); | |
2770 | ||
a12f801d | 2771 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2772 | |
369ec162 | 2773 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2774 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
81183059 | 2775 | |
63b88b90 | 2776 | if (unlikely(!(bdp->status & RXBD_ERR) && |
bc4598bc | 2777 | bdp->length > priv->rx_buffer_size)) |
63b88b90 AV |
2778 | bdp->status = RXBD_LARGE; |
2779 | ||
815b97c6 AF |
2780 | /* We drop the frame if we failed to allocate a new buffer */ |
2781 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
bc4598bc | 2782 | bdp->status & RXBD_ERR)) { |
815b97c6 AF |
2783 | count_errors(bdp->status, dev); |
2784 | ||
2785 | if (unlikely(!newskb)) | |
2786 | newskb = skb; | |
acbc0f03 | 2787 | else if (skb) |
acb600de | 2788 | dev_kfree_skb(skb); |
815b97c6 | 2789 | } else { |
1da177e4 | 2790 | /* Increment the number of packets */ |
a7f38041 | 2791 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2792 | howmany++; |
2793 | ||
2c2db48a DH |
2794 | if (likely(skb)) { |
2795 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2796 | /* Remove the FCS from the packet length */ | |
2797 | skb_put(skb, pkt_len); | |
a7f38041 | 2798 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2799 | skb_record_rx_queue(skb, rx_queue->qindex); |
cd754a57 | 2800 | gfar_process_frame(dev, skb, amount_pull, |
bc4598bc | 2801 | &rx_queue->grp->napi); |
2c2db48a DH |
2802 | |
2803 | } else { | |
59deab26 | 2804 | netif_warn(priv, rx_err, dev, "Missing skb!\n"); |
a7f38041 | 2805 | rx_queue->stats.rx_dropped++; |
212079df | 2806 | atomic64_inc(&priv->extra_stats.rx_skbmissing); |
2c2db48a | 2807 | } |
1da177e4 | 2808 | |
1da177e4 LT |
2809 | } |
2810 | ||
a12f801d | 2811 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2812 | |
815b97c6 | 2813 | /* Setup the new bdp */ |
a12f801d | 2814 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2815 | |
2816 | /* Update to the next pointer */ | |
a12f801d | 2817 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2818 | |
2819 | /* update to point at the next skb */ | |
bc4598bc JC |
2820 | rx_queue->skb_currx = (rx_queue->skb_currx + 1) & |
2821 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2822 | } |
2823 | ||
2824 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2825 | rx_queue->cur_rx = bdp; |
1da177e4 | 2826 | |
1da177e4 LT |
2827 | return howmany; |
2828 | } | |
2829 | ||
5eaedf31 CM |
2830 | static int gfar_poll_sq(struct napi_struct *napi, int budget) |
2831 | { | |
2832 | struct gfar_priv_grp *gfargrp = | |
2833 | container_of(napi, struct gfar_priv_grp, napi); | |
2834 | struct gfar __iomem *regs = gfargrp->regs; | |
2835 | struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0]; | |
2836 | struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0]; | |
2837 | int work_done = 0; | |
2838 | ||
2839 | /* Clear IEVENT, so interrupts aren't called again | |
2840 | * because of the packets that have already arrived | |
2841 | */ | |
2842 | gfar_write(®s->ievent, IEVENT_RTX_MASK); | |
2843 | ||
2844 | /* run Tx cleanup to completion */ | |
2845 | if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) | |
2846 | gfar_clean_tx_ring(tx_queue); | |
2847 | ||
2848 | work_done = gfar_clean_rx_ring(rx_queue, budget); | |
2849 | ||
2850 | if (work_done < budget) { | |
2851 | napi_complete(napi); | |
2852 | /* Clear the halt bit in RSTAT */ | |
2853 | gfar_write(®s->rstat, gfargrp->rstat); | |
2854 | ||
2855 | gfar_write(®s->imask, IMASK_DEFAULT); | |
2856 | ||
2857 | /* If we are coalescing interrupts, update the timer | |
2858 | * Otherwise, clear it | |
2859 | */ | |
2860 | gfar_write(®s->txic, 0); | |
2861 | if (likely(tx_queue->txcoalescing)) | |
2862 | gfar_write(®s->txic, tx_queue->txic); | |
2863 | ||
2864 | gfar_write(®s->rxic, 0); | |
2865 | if (unlikely(rx_queue->rxcoalescing)) | |
2866 | gfar_write(®s->rxic, rx_queue->rxic); | |
2867 | } | |
2868 | ||
2869 | return work_done; | |
2870 | } | |
2871 | ||
bea3348e | 2872 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2873 | { |
bc4598bc JC |
2874 | struct gfar_priv_grp *gfargrp = |
2875 | container_of(napi, struct gfar_priv_grp, napi); | |
fba4ed03 | 2876 | struct gfar_private *priv = gfargrp->priv; |
46ceb60c | 2877 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2878 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2879 | struct gfar_priv_rx_q *rx_queue = NULL; |
c233cf40 | 2880 | int work_done = 0, work_done_per_q = 0; |
39c0a0d5 | 2881 | int i, budget_per_q = 0; |
c233cf40 | 2882 | int has_tx_work; |
6be5ed3f CM |
2883 | unsigned long rstat_rxf; |
2884 | int num_act_queues; | |
fba4ed03 | 2885 | |
8c7396ae | 2886 | /* Clear IEVENT, so interrupts aren't called again |
0977f817 JC |
2887 | * because of the packets that have already arrived |
2888 | */ | |
f4983704 | 2889 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2890 | |
6be5ed3f CM |
2891 | rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; |
2892 | ||
2893 | num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); | |
2894 | if (num_act_queues) | |
2895 | budget_per_q = budget/num_act_queues; | |
2896 | ||
c233cf40 CM |
2897 | while (1) { |
2898 | has_tx_work = 0; | |
2899 | for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { | |
2900 | tx_queue = priv->tx_queue[i]; | |
2901 | /* run Tx cleanup to completion */ | |
2902 | if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { | |
2903 | gfar_clean_tx_ring(tx_queue); | |
2904 | has_tx_work = 1; | |
2905 | } | |
2906 | } | |
fba4ed03 | 2907 | |
984b3f57 | 2908 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
6be5ed3f CM |
2909 | /* skip queue if not active */ |
2910 | if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) | |
fba4ed03 | 2911 | continue; |
c233cf40 | 2912 | |
fba4ed03 | 2913 | rx_queue = priv->rx_queue[i]; |
c233cf40 CM |
2914 | work_done_per_q = |
2915 | gfar_clean_rx_ring(rx_queue, budget_per_q); | |
2916 | work_done += work_done_per_q; | |
2917 | ||
2918 | /* finished processing this queue */ | |
2919 | if (work_done_per_q < budget_per_q) { | |
6be5ed3f CM |
2920 | /* clear active queue hw indication */ |
2921 | gfar_write(®s->rstat, | |
2922 | RSTAT_CLEAR_RXF0 >> i); | |
2923 | rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i); | |
2924 | num_act_queues--; | |
2925 | ||
2926 | if (!num_act_queues) | |
c233cf40 CM |
2927 | break; |
2928 | /* recompute budget per Rx queue */ | |
2929 | budget_per_q = | |
6be5ed3f | 2930 | (budget - work_done) / num_act_queues; |
fba4ed03 SG |
2931 | } |
2932 | } | |
1da177e4 | 2933 | |
c233cf40 CM |
2934 | if (work_done >= budget) |
2935 | break; | |
42199884 | 2936 | |
6be5ed3f | 2937 | if (!num_act_queues && !has_tx_work) { |
1da177e4 | 2938 | |
c233cf40 | 2939 | napi_complete(napi); |
1da177e4 | 2940 | |
c233cf40 CM |
2941 | /* Clear the halt bit in RSTAT */ |
2942 | gfar_write(®s->rstat, gfargrp->rstat); | |
1da177e4 | 2943 | |
c233cf40 CM |
2944 | gfar_write(®s->imask, IMASK_DEFAULT); |
2945 | ||
2946 | /* If we are coalescing interrupts, update the timer | |
2947 | * Otherwise, clear it | |
2948 | */ | |
2949 | gfar_configure_coalescing(priv, gfargrp->rx_bit_map, | |
2950 | gfargrp->tx_bit_map); | |
2951 | break; | |
2952 | } | |
1da177e4 LT |
2953 | } |
2954 | ||
c233cf40 | 2955 | return work_done; |
1da177e4 | 2956 | } |
1da177e4 | 2957 | |
f2d71c2d | 2958 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0977f817 | 2959 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
f2d71c2d VW |
2960 | * without having to re-enable interrupts. It's not called while |
2961 | * the interrupt routine is executing. | |
2962 | */ | |
2963 | static void gfar_netpoll(struct net_device *dev) | |
2964 | { | |
2965 | struct gfar_private *priv = netdev_priv(dev); | |
3a2e16c8 | 2966 | int i; |
f2d71c2d VW |
2967 | |
2968 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2969 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c | 2970 | for (i = 0; i < priv->num_grps; i++) { |
62ed839d PG |
2971 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
2972 | ||
2973 | disable_irq(gfar_irq(grp, TX)->irq); | |
2974 | disable_irq(gfar_irq(grp, RX)->irq); | |
2975 | disable_irq(gfar_irq(grp, ER)->irq); | |
2976 | gfar_interrupt(gfar_irq(grp, TX)->irq, grp); | |
2977 | enable_irq(gfar_irq(grp, ER)->irq); | |
2978 | enable_irq(gfar_irq(grp, RX)->irq); | |
2979 | enable_irq(gfar_irq(grp, TX)->irq); | |
46ceb60c | 2980 | } |
f2d71c2d | 2981 | } else { |
46ceb60c | 2982 | for (i = 0; i < priv->num_grps; i++) { |
62ed839d PG |
2983 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
2984 | ||
2985 | disable_irq(gfar_irq(grp, TX)->irq); | |
2986 | gfar_interrupt(gfar_irq(grp, TX)->irq, grp); | |
2987 | enable_irq(gfar_irq(grp, TX)->irq); | |
43de004b | 2988 | } |
f2d71c2d VW |
2989 | } |
2990 | } | |
2991 | #endif | |
2992 | ||
1da177e4 | 2993 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 2994 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 2995 | { |
f4983704 | 2996 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
2997 | |
2998 | /* Save ievent for future reference */ | |
f4983704 | 2999 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 3000 | |
1da177e4 | 3001 | /* Check for reception */ |
538cc7ee | 3002 | if (events & IEVENT_RX_MASK) |
f4983704 | 3003 | gfar_receive(irq, grp_id); |
1da177e4 LT |
3004 | |
3005 | /* Check for transmit completion */ | |
538cc7ee | 3006 | if (events & IEVENT_TX_MASK) |
f4983704 | 3007 | gfar_transmit(irq, grp_id); |
1da177e4 | 3008 | |
538cc7ee SS |
3009 | /* Check for errors */ |
3010 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 3011 | gfar_error(irq, grp_id); |
1da177e4 LT |
3012 | |
3013 | return IRQ_HANDLED; | |
3014 | } | |
3015 | ||
1da177e4 LT |
3016 | /* Called every time the controller might need to be made |
3017 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 3018 | * information through variables in the phydev structure, and this |
1da177e4 LT |
3019 | * function converts those variables into the appropriate |
3020 | * register values, and can bring down the device if needed. | |
3021 | */ | |
3022 | static void adjust_link(struct net_device *dev) | |
3023 | { | |
3024 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3025 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
3026 | unsigned long flags; |
3027 | struct phy_device *phydev = priv->phydev; | |
3028 | int new_state = 0; | |
3029 | ||
fba4ed03 SG |
3030 | local_irq_save(flags); |
3031 | lock_tx_qs(priv); | |
3032 | ||
bb40dcbb AF |
3033 | if (phydev->link) { |
3034 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 3035 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 3036 | |
1da177e4 | 3037 | /* Now we make sure that we can be in full duplex mode. |
0977f817 JC |
3038 | * If not, we operate in half-duplex mode. |
3039 | */ | |
bb40dcbb AF |
3040 | if (phydev->duplex != priv->oldduplex) { |
3041 | new_state = 1; | |
3042 | if (!(phydev->duplex)) | |
1da177e4 | 3043 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 3044 | else |
1da177e4 | 3045 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 3046 | |
bb40dcbb | 3047 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
3048 | } |
3049 | ||
bb40dcbb AF |
3050 | if (phydev->speed != priv->oldspeed) { |
3051 | new_state = 1; | |
3052 | switch (phydev->speed) { | |
1da177e4 | 3053 | case 1000: |
1da177e4 LT |
3054 | tempval = |
3055 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
3056 | |
3057 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3058 | break; |
3059 | case 100: | |
3060 | case 10: | |
1da177e4 LT |
3061 | tempval = |
3062 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
3063 | |
3064 | /* Reduced mode distinguishes | |
0977f817 JC |
3065 | * between 10 and 100 |
3066 | */ | |
7f7f5316 AF |
3067 | if (phydev->speed == SPEED_100) |
3068 | ecntrl |= ECNTRL_R100; | |
3069 | else | |
3070 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3071 | break; |
3072 | default: | |
59deab26 JP |
3073 | netif_warn(priv, link, dev, |
3074 | "Ack! Speed (%d) is not 10/100/1000!\n", | |
3075 | phydev->speed); | |
1da177e4 LT |
3076 | break; |
3077 | } | |
3078 | ||
bb40dcbb | 3079 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3080 | } |
3081 | ||
bb40dcbb | 3082 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3083 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3084 | |
1da177e4 | 3085 | if (!priv->oldlink) { |
bb40dcbb | 3086 | new_state = 1; |
1da177e4 | 3087 | priv->oldlink = 1; |
1da177e4 | 3088 | } |
bb40dcbb AF |
3089 | } else if (priv->oldlink) { |
3090 | new_state = 1; | |
3091 | priv->oldlink = 0; | |
3092 | priv->oldspeed = 0; | |
3093 | priv->oldduplex = -1; | |
1da177e4 | 3094 | } |
1da177e4 | 3095 | |
bb40dcbb AF |
3096 | if (new_state && netif_msg_link(priv)) |
3097 | phy_print_status(phydev); | |
fba4ed03 SG |
3098 | unlock_tx_qs(priv); |
3099 | local_irq_restore(flags); | |
bb40dcbb | 3100 | } |
1da177e4 LT |
3101 | |
3102 | /* Update the hash table based on the current list of multicast | |
3103 | * addresses we subscribe to. Also, change the promiscuity of | |
3104 | * the device based on the flags (this function is called | |
0977f817 JC |
3105 | * whenever dev->flags is changed |
3106 | */ | |
1da177e4 LT |
3107 | static void gfar_set_multi(struct net_device *dev) |
3108 | { | |
22bedad3 | 3109 | struct netdev_hw_addr *ha; |
1da177e4 | 3110 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3111 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3112 | u32 tempval; |
3113 | ||
a12f801d | 3114 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3115 | /* Set RCTRL to PROM */ |
3116 | tempval = gfar_read(®s->rctrl); | |
3117 | tempval |= RCTRL_PROM; | |
3118 | gfar_write(®s->rctrl, tempval); | |
3119 | } else { | |
3120 | /* Set RCTRL to not PROM */ | |
3121 | tempval = gfar_read(®s->rctrl); | |
3122 | tempval &= ~(RCTRL_PROM); | |
3123 | gfar_write(®s->rctrl, tempval); | |
3124 | } | |
6aa20a22 | 3125 | |
a12f801d | 3126 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3127 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3128 | gfar_write(®s->igaddr0, 0xffffffff); |
3129 | gfar_write(®s->igaddr1, 0xffffffff); | |
3130 | gfar_write(®s->igaddr2, 0xffffffff); | |
3131 | gfar_write(®s->igaddr3, 0xffffffff); | |
3132 | gfar_write(®s->igaddr4, 0xffffffff); | |
3133 | gfar_write(®s->igaddr5, 0xffffffff); | |
3134 | gfar_write(®s->igaddr6, 0xffffffff); | |
3135 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3136 | gfar_write(®s->gaddr0, 0xffffffff); |
3137 | gfar_write(®s->gaddr1, 0xffffffff); | |
3138 | gfar_write(®s->gaddr2, 0xffffffff); | |
3139 | gfar_write(®s->gaddr3, 0xffffffff); | |
3140 | gfar_write(®s->gaddr4, 0xffffffff); | |
3141 | gfar_write(®s->gaddr5, 0xffffffff); | |
3142 | gfar_write(®s->gaddr6, 0xffffffff); | |
3143 | gfar_write(®s->gaddr7, 0xffffffff); | |
3144 | } else { | |
7f7f5316 AF |
3145 | int em_num; |
3146 | int idx; | |
3147 | ||
1da177e4 | 3148 | /* zero out the hash */ |
0bbaf069 KG |
3149 | gfar_write(®s->igaddr0, 0x0); |
3150 | gfar_write(®s->igaddr1, 0x0); | |
3151 | gfar_write(®s->igaddr2, 0x0); | |
3152 | gfar_write(®s->igaddr3, 0x0); | |
3153 | gfar_write(®s->igaddr4, 0x0); | |
3154 | gfar_write(®s->igaddr5, 0x0); | |
3155 | gfar_write(®s->igaddr6, 0x0); | |
3156 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3157 | gfar_write(®s->gaddr0, 0x0); |
3158 | gfar_write(®s->gaddr1, 0x0); | |
3159 | gfar_write(®s->gaddr2, 0x0); | |
3160 | gfar_write(®s->gaddr3, 0x0); | |
3161 | gfar_write(®s->gaddr4, 0x0); | |
3162 | gfar_write(®s->gaddr5, 0x0); | |
3163 | gfar_write(®s->gaddr6, 0x0); | |
3164 | gfar_write(®s->gaddr7, 0x0); | |
3165 | ||
7f7f5316 AF |
3166 | /* If we have extended hash tables, we need to |
3167 | * clear the exact match registers to prepare for | |
0977f817 JC |
3168 | * setting them |
3169 | */ | |
7f7f5316 AF |
3170 | if (priv->extended_hash) { |
3171 | em_num = GFAR_EM_NUM + 1; | |
3172 | gfar_clear_exact_match(dev); | |
3173 | idx = 1; | |
3174 | } else { | |
3175 | idx = 0; | |
3176 | em_num = 0; | |
3177 | } | |
3178 | ||
4cd24eaf | 3179 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3180 | return; |
3181 | ||
3182 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3183 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3184 | if (idx < em_num) { |
22bedad3 | 3185 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3186 | idx++; |
3187 | } else | |
22bedad3 | 3188 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3189 | } |
3190 | } | |
1da177e4 LT |
3191 | } |
3192 | ||
7f7f5316 AF |
3193 | |
3194 | /* Clears each of the exact match registers to zero, so they | |
0977f817 JC |
3195 | * don't interfere with normal reception |
3196 | */ | |
7f7f5316 AF |
3197 | static void gfar_clear_exact_match(struct net_device *dev) |
3198 | { | |
3199 | int idx; | |
6a3c910c | 3200 | static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 | 3201 | |
bc4598bc | 3202 | for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) |
b6bc7650 | 3203 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3204 | } |
3205 | ||
1da177e4 LT |
3206 | /* Set the appropriate hash bit for the given addr */ |
3207 | /* The algorithm works like so: | |
3208 | * 1) Take the Destination Address (ie the multicast address), and | |
3209 | * do a CRC on it (little endian), and reverse the bits of the | |
3210 | * result. | |
3211 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3212 | * table. The table is controlled through 8 32-bit registers: | |
3213 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3214 | * gaddr7. This means that the 3 most significant bits in the | |
3215 | * hash index which gaddr register to use, and the 5 other bits | |
3216 | * indicate which bit (assuming an IBM numbering scheme, which | |
3217 | * for PowerPC (tm) is usually the case) in the register holds | |
0977f817 JC |
3218 | * the entry. |
3219 | */ | |
1da177e4 LT |
3220 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) |
3221 | { | |
3222 | u32 tempval; | |
3223 | struct gfar_private *priv = netdev_priv(dev); | |
6a3c910c | 3224 | u32 result = ether_crc(ETH_ALEN, addr); |
0bbaf069 KG |
3225 | int width = priv->hash_width; |
3226 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3227 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3228 | u32 value = (1 << (31-whichbit)); |
3229 | ||
0bbaf069 | 3230 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3231 | tempval |= value; |
0bbaf069 | 3232 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3233 | } |
3234 | ||
7f7f5316 AF |
3235 | |
3236 | /* There are multiple MAC Address register pairs on some controllers | |
3237 | * This function sets the numth pair to a given address | |
3238 | */ | |
b6bc7650 JP |
3239 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3240 | const u8 *addr) | |
7f7f5316 AF |
3241 | { |
3242 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3243 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 | 3244 | int idx; |
6a3c910c | 3245 | char tmpbuf[ETH_ALEN]; |
7f7f5316 | 3246 | u32 tempval; |
f4983704 | 3247 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3248 | |
3249 | macptr += num*2; | |
3250 | ||
0977f817 JC |
3251 | /* Now copy it into the mac registers backwards, cuz |
3252 | * little endian is silly | |
3253 | */ | |
6a3c910c JP |
3254 | for (idx = 0; idx < ETH_ALEN; idx++) |
3255 | tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; | |
7f7f5316 AF |
3256 | |
3257 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3258 | ||
3259 | tempval = *((u32 *) (tmpbuf + 4)); | |
3260 | ||
3261 | gfar_write(macptr+1, tempval); | |
3262 | } | |
3263 | ||
1da177e4 | 3264 | /* GFAR error interrupt handler */ |
f4983704 | 3265 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3266 | { |
f4983704 SG |
3267 | struct gfar_priv_grp *gfargrp = grp_id; |
3268 | struct gfar __iomem *regs = gfargrp->regs; | |
3269 | struct gfar_private *priv= gfargrp->priv; | |
3270 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3271 | |
3272 | /* Save ievent for future reference */ | |
f4983704 | 3273 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3274 | |
3275 | /* Clear IEVENT */ | |
f4983704 | 3276 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3277 | |
3278 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3279 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3280 | (events & IEVENT_MAG)) |
3281 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3282 | |
3283 | /* Hmm... */ | |
0bbaf069 | 3284 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
bc4598bc JC |
3285 | netdev_dbg(dev, |
3286 | "error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
59deab26 | 3287 | events, gfar_read(®s->imask)); |
1da177e4 LT |
3288 | |
3289 | /* Update the error counters */ | |
3290 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3291 | dev->stats.tx_errors++; |
1da177e4 LT |
3292 | |
3293 | if (events & IEVENT_LC) | |
09f75cd7 | 3294 | dev->stats.tx_window_errors++; |
1da177e4 | 3295 | if (events & IEVENT_CRL) |
09f75cd7 | 3296 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3297 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3298 | unsigned long flags; |
3299 | ||
59deab26 JP |
3300 | netif_dbg(priv, tx_err, dev, |
3301 | "TX FIFO underrun, packet dropped\n"); | |
09f75cd7 | 3302 | dev->stats.tx_dropped++; |
212079df | 3303 | atomic64_inc(&priv->extra_stats.tx_underrun); |
1da177e4 | 3304 | |
836cf7fa AV |
3305 | local_irq_save(flags); |
3306 | lock_tx_qs(priv); | |
3307 | ||
1da177e4 | 3308 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3309 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3310 | |
3311 | unlock_tx_qs(priv); | |
3312 | local_irq_restore(flags); | |
1da177e4 | 3313 | } |
59deab26 | 3314 | netif_dbg(priv, tx_err, dev, "Transmit Error\n"); |
1da177e4 LT |
3315 | } |
3316 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3317 | dev->stats.rx_errors++; |
212079df | 3318 | atomic64_inc(&priv->extra_stats.rx_bsy); |
1da177e4 | 3319 | |
f4983704 | 3320 | gfar_receive(irq, grp_id); |
1da177e4 | 3321 | |
59deab26 JP |
3322 | netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", |
3323 | gfar_read(®s->rstat)); | |
1da177e4 LT |
3324 | } |
3325 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3326 | dev->stats.rx_errors++; |
212079df | 3327 | atomic64_inc(&priv->extra_stats.rx_babr); |
1da177e4 | 3328 | |
59deab26 | 3329 | netif_dbg(priv, rx_err, dev, "babbling RX error\n"); |
1da177e4 LT |
3330 | } |
3331 | if (events & IEVENT_EBERR) { | |
212079df | 3332 | atomic64_inc(&priv->extra_stats.eberr); |
59deab26 | 3333 | netif_dbg(priv, rx_err, dev, "bus error\n"); |
1da177e4 | 3334 | } |
59deab26 JP |
3335 | if (events & IEVENT_RXC) |
3336 | netif_dbg(priv, rx_status, dev, "control frame\n"); | |
1da177e4 LT |
3337 | |
3338 | if (events & IEVENT_BABT) { | |
212079df | 3339 | atomic64_inc(&priv->extra_stats.tx_babt); |
59deab26 | 3340 | netif_dbg(priv, tx_err, dev, "babbling TX error\n"); |
1da177e4 LT |
3341 | } |
3342 | return IRQ_HANDLED; | |
3343 | } | |
3344 | ||
b31a1d8b AF |
3345 | static struct of_device_id gfar_match[] = |
3346 | { | |
3347 | { | |
3348 | .type = "network", | |
3349 | .compatible = "gianfar", | |
3350 | }, | |
46ceb60c SG |
3351 | { |
3352 | .compatible = "fsl,etsec2", | |
3353 | }, | |
b31a1d8b AF |
3354 | {}, |
3355 | }; | |
e72701ac | 3356 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3357 | |
1da177e4 | 3358 | /* Structure for a device driver */ |
74888760 | 3359 | static struct platform_driver gfar_driver = { |
4018294b GL |
3360 | .driver = { |
3361 | .name = "fsl-gianfar", | |
3362 | .owner = THIS_MODULE, | |
3363 | .pm = GFAR_PM_OPS, | |
3364 | .of_match_table = gfar_match, | |
3365 | }, | |
1da177e4 LT |
3366 | .probe = gfar_probe, |
3367 | .remove = gfar_remove, | |
3368 | }; | |
3369 | ||
db62f684 | 3370 | module_platform_driver(gfar_driver); |