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Commit | Line | Data |
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0977f817 | 1 | /* drivers/net/ethernet/freescale/gianfar.c |
1da177e4 LT |
2 | * |
3 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
4 | * This driver is designed for the non-CPM ethernet controllers |
5 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
6 | * Based on 8260_io/fcc_enet.c |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
a12f801d | 10 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 11 | * |
6c43e046 | 12 | * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. |
a12f801d | 13 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
59deab26 JP |
64 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
65 | #define DEBUG | |
66 | ||
1da177e4 | 67 | #include <linux/kernel.h> |
1da177e4 LT |
68 | #include <linux/string.h> |
69 | #include <linux/errno.h> | |
bb40dcbb | 70 | #include <linux/unistd.h> |
1da177e4 LT |
71 | #include <linux/slab.h> |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/init.h> | |
74 | #include <linux/delay.h> | |
75 | #include <linux/netdevice.h> | |
76 | #include <linux/etherdevice.h> | |
77 | #include <linux/skbuff.h> | |
0bbaf069 | 78 | #include <linux/if_vlan.h> |
1da177e4 LT |
79 | #include <linux/spinlock.h> |
80 | #include <linux/mm.h> | |
fe192a49 | 81 | #include <linux/of_mdio.h> |
b31a1d8b | 82 | #include <linux/of_platform.h> |
0bbaf069 KG |
83 | #include <linux/ip.h> |
84 | #include <linux/tcp.h> | |
85 | #include <linux/udp.h> | |
9c07b884 | 86 | #include <linux/in.h> |
cc772ab7 | 87 | #include <linux/net_tstamp.h> |
1da177e4 LT |
88 | |
89 | #include <asm/io.h> | |
7d350977 | 90 | #include <asm/reg.h> |
1da177e4 LT |
91 | #include <asm/irq.h> |
92 | #include <asm/uaccess.h> | |
93 | #include <linux/module.h> | |
1da177e4 LT |
94 | #include <linux/dma-mapping.h> |
95 | #include <linux/crc32.h> | |
bb40dcbb AF |
96 | #include <linux/mii.h> |
97 | #include <linux/phy.h> | |
b31a1d8b AF |
98 | #include <linux/phy_fixed.h> |
99 | #include <linux/of.h> | |
4b6ba8aa | 100 | #include <linux/of_net.h> |
1da177e4 LT |
101 | |
102 | #include "gianfar.h" | |
1da177e4 LT |
103 | |
104 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 | 105 | |
7f7f5316 | 106 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 107 | |
1da177e4 LT |
108 | static int gfar_enet_open(struct net_device *dev); |
109 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 110 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
111 | static void gfar_timeout(struct net_device *dev); |
112 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 113 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 114 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 115 | struct sk_buff *skb); |
1da177e4 LT |
116 | static int gfar_set_mac_address(struct net_device *dev); |
117 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
118 | static irqreturn_t gfar_error(int irq, void *dev_id); |
119 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
120 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
121 | static void adjust_link(struct net_device *dev); |
122 | static void init_registers(struct net_device *dev); | |
123 | static int init_phy(struct net_device *dev); | |
74888760 | 124 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 125 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 126 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
127 | static void gfar_set_multi(struct net_device *dev); |
128 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 129 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 130 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
131 | #ifdef CONFIG_NET_POLL_CONTROLLER |
132 | static void gfar_netpoll(struct net_device *dev); | |
133 | #endif | |
a12f801d SG |
134 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
135 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); | |
2c2db48a | 136 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
cd754a57 | 137 | int amount_pull, struct napi_struct *napi); |
7f7f5316 | 138 | void gfar_halt(struct net_device *dev); |
d87eb127 | 139 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
140 | void gfar_start(struct net_device *dev); |
141 | static void gfar_clear_exact_match(struct net_device *dev); | |
b6bc7650 JP |
142 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
143 | const u8 *addr); | |
26ccfc37 | 144 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 145 | |
1da177e4 LT |
146 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
147 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | ||
a12f801d | 150 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
151 | dma_addr_t buf) |
152 | { | |
8a102fe0 AV |
153 | u32 lstatus; |
154 | ||
155 | bdp->bufPtr = buf; | |
156 | ||
157 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 158 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
159 | lstatus |= BD_LFLAG(RXBD_WRAP); |
160 | ||
161 | eieio(); | |
162 | ||
163 | bdp->lstatus = lstatus; | |
164 | } | |
165 | ||
8728327e | 166 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 167 | { |
8728327e | 168 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
169 | struct gfar_priv_tx_q *tx_queue = NULL; |
170 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
171 | struct txbd8 *txbdp; |
172 | struct rxbd8 *rxbdp; | |
fba4ed03 | 173 | int i, j; |
a12f801d | 174 | |
fba4ed03 SG |
175 | for (i = 0; i < priv->num_tx_queues; i++) { |
176 | tx_queue = priv->tx_queue[i]; | |
177 | /* Initialize some variables in our dev structure */ | |
178 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
179 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
180 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
181 | tx_queue->skb_curtx = 0; | |
182 | tx_queue->skb_dirtytx = 0; | |
183 | ||
184 | /* Initialize Transmit Descriptor Ring */ | |
185 | txbdp = tx_queue->tx_bd_base; | |
186 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
187 | txbdp->lstatus = 0; | |
188 | txbdp->bufPtr = 0; | |
189 | txbdp++; | |
190 | } | |
8728327e | 191 | |
fba4ed03 SG |
192 | /* Set the last descriptor in the ring to indicate wrap */ |
193 | txbdp--; | |
194 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
195 | } |
196 | ||
fba4ed03 SG |
197 | for (i = 0; i < priv->num_rx_queues; i++) { |
198 | rx_queue = priv->rx_queue[i]; | |
199 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
200 | rx_queue->skb_currx = 0; | |
201 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 202 | |
fba4ed03 SG |
203 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
204 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 205 | |
fba4ed03 SG |
206 | if (skb) { |
207 | gfar_init_rxbdp(rx_queue, rxbdp, | |
208 | rxbdp->bufPtr); | |
209 | } else { | |
210 | skb = gfar_new_skb(ndev); | |
211 | if (!skb) { | |
59deab26 | 212 | netdev_err(ndev, "Can't allocate RX buffers\n"); |
1eb8f7a7 | 213 | return -ENOMEM; |
fba4ed03 SG |
214 | } |
215 | rx_queue->rx_skbuff[j] = skb; | |
216 | ||
217 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 218 | } |
8728327e | 219 | |
fba4ed03 | 220 | rxbdp++; |
8728327e AV |
221 | } |
222 | ||
8728327e AV |
223 | } |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
229 | { | |
826aa4a0 | 230 | void *vaddr; |
fba4ed03 SG |
231 | dma_addr_t addr; |
232 | int i, j, k; | |
826aa4a0 AV |
233 | struct gfar_private *priv = netdev_priv(ndev); |
234 | struct device *dev = &priv->ofdev->dev; | |
a12f801d SG |
235 | struct gfar_priv_tx_q *tx_queue = NULL; |
236 | struct gfar_priv_rx_q *rx_queue = NULL; | |
237 | ||
fba4ed03 SG |
238 | priv->total_tx_ring_size = 0; |
239 | for (i = 0; i < priv->num_tx_queues; i++) | |
240 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
241 | ||
242 | priv->total_rx_ring_size = 0; | |
243 | for (i = 0; i < priv->num_rx_queues; i++) | |
244 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
245 | |
246 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 247 | vaddr = dma_alloc_coherent(dev, |
fba4ed03 SG |
248 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
249 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
250 | &addr, GFP_KERNEL); | |
826aa4a0 | 251 | if (!vaddr) { |
59deab26 JP |
252 | netif_err(priv, ifup, ndev, |
253 | "Could not allocate buffer descriptors!\n"); | |
826aa4a0 AV |
254 | return -ENOMEM; |
255 | } | |
256 | ||
fba4ed03 SG |
257 | for (i = 0; i < priv->num_tx_queues; i++) { |
258 | tx_queue = priv->tx_queue[i]; | |
43d620c8 | 259 | tx_queue->tx_bd_base = vaddr; |
fba4ed03 SG |
260 | tx_queue->tx_bd_dma_base = addr; |
261 | tx_queue->dev = ndev; | |
262 | /* enet DMA only understands physical addresses */ | |
bc4598bc JC |
263 | addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; |
264 | vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; | |
fba4ed03 | 265 | } |
826aa4a0 | 266 | |
826aa4a0 | 267 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
268 | for (i = 0; i < priv->num_rx_queues; i++) { |
269 | rx_queue = priv->rx_queue[i]; | |
43d620c8 | 270 | rx_queue->rx_bd_base = vaddr; |
fba4ed03 SG |
271 | rx_queue->rx_bd_dma_base = addr; |
272 | rx_queue->dev = ndev; | |
bc4598bc JC |
273 | addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; |
274 | vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; | |
fba4ed03 | 275 | } |
826aa4a0 AV |
276 | |
277 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
278 | for (i = 0; i < priv->num_tx_queues; i++) { |
279 | tx_queue = priv->tx_queue[i]; | |
280 | tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) * | |
bc4598bc JC |
281 | tx_queue->tx_ring_size, |
282 | GFP_KERNEL); | |
fba4ed03 | 283 | if (!tx_queue->tx_skbuff) { |
59deab26 JP |
284 | netif_err(priv, ifup, ndev, |
285 | "Could not allocate tx_skbuff\n"); | |
fba4ed03 SG |
286 | goto cleanup; |
287 | } | |
826aa4a0 | 288 | |
fba4ed03 SG |
289 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
290 | tx_queue->tx_skbuff[k] = NULL; | |
291 | } | |
826aa4a0 | 292 | |
fba4ed03 SG |
293 | for (i = 0; i < priv->num_rx_queues; i++) { |
294 | rx_queue = priv->rx_queue[i]; | |
295 | rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) * | |
bc4598bc JC |
296 | rx_queue->rx_ring_size, |
297 | GFP_KERNEL); | |
826aa4a0 | 298 | |
fba4ed03 | 299 | if (!rx_queue->rx_skbuff) { |
59deab26 JP |
300 | netif_err(priv, ifup, ndev, |
301 | "Could not allocate rx_skbuff\n"); | |
fba4ed03 SG |
302 | goto cleanup; |
303 | } | |
304 | ||
305 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
306 | rx_queue->rx_skbuff[j] = NULL; | |
307 | } | |
826aa4a0 | 308 | |
8728327e AV |
309 | if (gfar_init_bds(ndev)) |
310 | goto cleanup; | |
826aa4a0 AV |
311 | |
312 | return 0; | |
313 | ||
314 | cleanup: | |
315 | free_skb_resources(priv); | |
316 | return -ENOMEM; | |
317 | } | |
318 | ||
fba4ed03 SG |
319 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
320 | { | |
46ceb60c | 321 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 322 | u32 __iomem *baddr; |
fba4ed03 SG |
323 | int i; |
324 | ||
325 | baddr = ®s->tbase0; | |
bc4598bc | 326 | for (i = 0; i < priv->num_tx_queues; i++) { |
fba4ed03 | 327 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); |
bc4598bc | 328 | baddr += 2; |
fba4ed03 SG |
329 | } |
330 | ||
331 | baddr = ®s->rbase0; | |
bc4598bc | 332 | for (i = 0; i < priv->num_rx_queues; i++) { |
fba4ed03 | 333 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); |
bc4598bc | 334 | baddr += 2; |
fba4ed03 SG |
335 | } |
336 | } | |
337 | ||
826aa4a0 AV |
338 | static void gfar_init_mac(struct net_device *ndev) |
339 | { | |
340 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 341 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
342 | u32 rctrl = 0; |
343 | u32 tctrl = 0; | |
344 | u32 attrs = 0; | |
345 | ||
fba4ed03 SG |
346 | /* write the tx/rx base registers */ |
347 | gfar_init_tx_rx_base(priv); | |
32c513bc | 348 | |
826aa4a0 | 349 | /* Configure the coalescing support */ |
46ceb60c | 350 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
fba4ed03 | 351 | |
1ccb8389 | 352 | if (priv->rx_filer_enable) { |
fba4ed03 | 353 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
354 | /* Program the RIR0 reg with the required distribution */ |
355 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
356 | } | |
826aa4a0 | 357 | |
8b3afe95 | 358 | if (ndev->features & NETIF_F_RXCSUM) |
826aa4a0 AV |
359 | rctrl |= RCTRL_CHECKSUMMING; |
360 | ||
361 | if (priv->extended_hash) { | |
362 | rctrl |= RCTRL_EXTHASH; | |
363 | ||
364 | gfar_clear_exact_match(ndev); | |
365 | rctrl |= RCTRL_EMEN; | |
366 | } | |
367 | ||
368 | if (priv->padding) { | |
369 | rctrl &= ~RCTRL_PAL_MASK; | |
370 | rctrl |= RCTRL_PADDING(priv->padding); | |
371 | } | |
372 | ||
cc772ab7 MR |
373 | /* Insert receive time stamps into padding alignment bytes */ |
374 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { | |
375 | rctrl &= ~RCTRL_PAL_MASK; | |
97553f7f | 376 | rctrl |= RCTRL_PADDING(8); |
cc772ab7 MR |
377 | priv->padding = 8; |
378 | } | |
379 | ||
97553f7f MR |
380 | /* Enable HW time stamping if requested from user space */ |
381 | if (priv->hwts_rx_en) | |
382 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; | |
383 | ||
87c288c6 | 384 | if (ndev->features & NETIF_F_HW_VLAN_RX) |
b852b720 | 385 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; |
826aa4a0 AV |
386 | |
387 | /* Init rctrl based on our settings */ | |
388 | gfar_write(®s->rctrl, rctrl); | |
389 | ||
390 | if (ndev->features & NETIF_F_IP_CSUM) | |
391 | tctrl |= TCTRL_INIT_CSUM; | |
392 | ||
b98b8bab CM |
393 | if (priv->prio_sched_en) |
394 | tctrl |= TCTRL_TXSCHED_PRIO; | |
395 | else { | |
396 | tctrl |= TCTRL_TXSCHED_WRRS; | |
397 | gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); | |
398 | gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); | |
399 | } | |
fba4ed03 | 400 | |
826aa4a0 AV |
401 | gfar_write(®s->tctrl, tctrl); |
402 | ||
403 | /* Set the extraction length and index */ | |
404 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
405 | ATTRELI_EI(priv->rx_stash_index); | |
406 | ||
407 | gfar_write(®s->attreli, attrs); | |
408 | ||
409 | /* Start with defaults, and add stashing or locking | |
0977f817 JC |
410 | * depending on the approprate variables |
411 | */ | |
826aa4a0 AV |
412 | attrs = ATTR_INIT_SETTINGS; |
413 | ||
414 | if (priv->bd_stash_en) | |
415 | attrs |= ATTR_BDSTASH; | |
416 | ||
417 | if (priv->rx_stash_size != 0) | |
418 | attrs |= ATTR_BUFSTASH; | |
419 | ||
420 | gfar_write(®s->attr, attrs); | |
421 | ||
422 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
423 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
424 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
425 | } | |
426 | ||
a7f38041 SG |
427 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
428 | { | |
429 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
430 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
431 | unsigned long tx_packets = 0, tx_bytes = 0; | |
3a2e16c8 | 432 | int i; |
a7f38041 SG |
433 | |
434 | for (i = 0; i < priv->num_rx_queues; i++) { | |
435 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
bc4598bc | 436 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; |
a7f38041 SG |
437 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; |
438 | } | |
439 | ||
440 | dev->stats.rx_packets = rx_packets; | |
bc4598bc | 441 | dev->stats.rx_bytes = rx_bytes; |
a7f38041 SG |
442 | dev->stats.rx_dropped = rx_dropped; |
443 | ||
444 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
445 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
446 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
447 | } |
448 | ||
bc4598bc | 449 | dev->stats.tx_bytes = tx_bytes; |
a7f38041 SG |
450 | dev->stats.tx_packets = tx_packets; |
451 | ||
452 | return &dev->stats; | |
453 | } | |
454 | ||
26ccfc37 AF |
455 | static const struct net_device_ops gfar_netdev_ops = { |
456 | .ndo_open = gfar_enet_open, | |
457 | .ndo_start_xmit = gfar_start_xmit, | |
458 | .ndo_stop = gfar_close, | |
459 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 460 | .ndo_set_features = gfar_set_features, |
afc4b13d | 461 | .ndo_set_rx_mode = gfar_set_multi, |
26ccfc37 AF |
462 | .ndo_tx_timeout = gfar_timeout, |
463 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 464 | .ndo_get_stats = gfar_get_stats, |
240c102d BH |
465 | .ndo_set_mac_address = eth_mac_addr, |
466 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
467 | #ifdef CONFIG_NET_POLL_CONTROLLER |
468 | .ndo_poll_controller = gfar_netpoll, | |
469 | #endif | |
470 | }; | |
471 | ||
fba4ed03 SG |
472 | void lock_rx_qs(struct gfar_private *priv) |
473 | { | |
3a2e16c8 | 474 | int i; |
fba4ed03 SG |
475 | |
476 | for (i = 0; i < priv->num_rx_queues; i++) | |
477 | spin_lock(&priv->rx_queue[i]->rxlock); | |
478 | } | |
479 | ||
480 | void lock_tx_qs(struct gfar_private *priv) | |
481 | { | |
3a2e16c8 | 482 | int i; |
fba4ed03 SG |
483 | |
484 | for (i = 0; i < priv->num_tx_queues; i++) | |
485 | spin_lock(&priv->tx_queue[i]->txlock); | |
486 | } | |
487 | ||
488 | void unlock_rx_qs(struct gfar_private *priv) | |
489 | { | |
3a2e16c8 | 490 | int i; |
fba4ed03 SG |
491 | |
492 | for (i = 0; i < priv->num_rx_queues; i++) | |
493 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
494 | } | |
495 | ||
496 | void unlock_tx_qs(struct gfar_private *priv) | |
497 | { | |
3a2e16c8 | 498 | int i; |
fba4ed03 SG |
499 | |
500 | for (i = 0; i < priv->num_tx_queues; i++) | |
501 | spin_unlock(&priv->tx_queue[i]->txlock); | |
502 | } | |
503 | ||
87c288c6 JP |
504 | static bool gfar_is_vlan_on(struct gfar_private *priv) |
505 | { | |
506 | return (priv->ndev->features & NETIF_F_HW_VLAN_RX) || | |
507 | (priv->ndev->features & NETIF_F_HW_VLAN_TX); | |
508 | } | |
509 | ||
7f7f5316 AF |
510 | /* Returns 1 if incoming frames use an FCB */ |
511 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 512 | { |
87c288c6 | 513 | return gfar_is_vlan_on(priv) || |
bc4598bc JC |
514 | (priv->ndev->features & NETIF_F_RXCSUM) || |
515 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER); | |
0bbaf069 | 516 | } |
bb40dcbb | 517 | |
fba4ed03 SG |
518 | static void free_tx_pointers(struct gfar_private *priv) |
519 | { | |
3a2e16c8 | 520 | int i; |
fba4ed03 SG |
521 | |
522 | for (i = 0; i < priv->num_tx_queues; i++) | |
523 | kfree(priv->tx_queue[i]); | |
524 | } | |
525 | ||
526 | static void free_rx_pointers(struct gfar_private *priv) | |
527 | { | |
3a2e16c8 | 528 | int i; |
fba4ed03 SG |
529 | |
530 | for (i = 0; i < priv->num_rx_queues; i++) | |
531 | kfree(priv->rx_queue[i]); | |
532 | } | |
533 | ||
46ceb60c SG |
534 | static void unmap_group_regs(struct gfar_private *priv) |
535 | { | |
3a2e16c8 | 536 | int i; |
46ceb60c SG |
537 | |
538 | for (i = 0; i < MAXGROUPS; i++) | |
539 | if (priv->gfargrp[i].regs) | |
540 | iounmap(priv->gfargrp[i].regs); | |
541 | } | |
542 | ||
543 | static void disable_napi(struct gfar_private *priv) | |
544 | { | |
3a2e16c8 | 545 | int i; |
46ceb60c SG |
546 | |
547 | for (i = 0; i < priv->num_grps; i++) | |
548 | napi_disable(&priv->gfargrp[i].napi); | |
549 | } | |
550 | ||
551 | static void enable_napi(struct gfar_private *priv) | |
552 | { | |
3a2e16c8 | 553 | int i; |
46ceb60c SG |
554 | |
555 | for (i = 0; i < priv->num_grps; i++) | |
556 | napi_enable(&priv->gfargrp[i].napi); | |
557 | } | |
558 | ||
559 | static int gfar_parse_group(struct device_node *np, | |
bc4598bc | 560 | struct gfar_private *priv, const char *model) |
46ceb60c SG |
561 | { |
562 | u32 *queue_mask; | |
46ceb60c | 563 | |
7ce97d4f | 564 | priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0); |
46ceb60c SG |
565 | if (!priv->gfargrp[priv->num_grps].regs) |
566 | return -ENOMEM; | |
567 | ||
568 | priv->gfargrp[priv->num_grps].interruptTransmit = | |
569 | irq_of_parse_and_map(np, 0); | |
570 | ||
571 | /* If we aren't the FEC we have multiple interrupts */ | |
572 | if (model && strcasecmp(model, "FEC")) { | |
573 | priv->gfargrp[priv->num_grps].interruptReceive = | |
574 | irq_of_parse_and_map(np, 1); | |
575 | priv->gfargrp[priv->num_grps].interruptError = | |
576 | irq_of_parse_and_map(np,2); | |
28cb6ccd NK |
577 | if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ || |
578 | priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ || | |
579 | priv->gfargrp[priv->num_grps].interruptError == NO_IRQ) | |
46ceb60c | 580 | return -EINVAL; |
46ceb60c SG |
581 | } |
582 | ||
583 | priv->gfargrp[priv->num_grps].grp_id = priv->num_grps; | |
584 | priv->gfargrp[priv->num_grps].priv = priv; | |
585 | spin_lock_init(&priv->gfargrp[priv->num_grps].grplock); | |
bc4598bc JC |
586 | if (priv->mode == MQ_MG_MODE) { |
587 | queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); | |
588 | priv->gfargrp[priv->num_grps].rx_bit_map = queue_mask ? | |
589 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); | |
590 | queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); | |
591 | priv->gfargrp[priv->num_grps].tx_bit_map = queue_mask ? | |
592 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); | |
46ceb60c SG |
593 | } else { |
594 | priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF; | |
595 | priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF; | |
596 | } | |
597 | priv->num_grps++; | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
2dc11581 | 602 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 603 | { |
b31a1d8b AF |
604 | const char *model; |
605 | const char *ctype; | |
606 | const void *mac_addr; | |
fba4ed03 SG |
607 | int err = 0, i; |
608 | struct net_device *dev = NULL; | |
609 | struct gfar_private *priv = NULL; | |
61c7a080 | 610 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 611 | struct device_node *child = NULL; |
4d7902f2 AF |
612 | const u32 *stash; |
613 | const u32 *stash_len; | |
614 | const u32 *stash_idx; | |
fba4ed03 SG |
615 | unsigned int num_tx_qs, num_rx_qs; |
616 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
617 | |
618 | if (!np || !of_device_is_available(np)) | |
619 | return -ENODEV; | |
620 | ||
fba4ed03 SG |
621 | /* parse the num of tx and rx queues */ |
622 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
623 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
624 | ||
625 | if (num_tx_qs > MAX_TX_QS) { | |
59deab26 JP |
626 | pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", |
627 | num_tx_qs, MAX_TX_QS); | |
628 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
629 | return -EINVAL; |
630 | } | |
631 | ||
632 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
633 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
634 | ||
635 | if (num_rx_qs > MAX_RX_QS) { | |
59deab26 JP |
636 | pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", |
637 | num_rx_qs, MAX_RX_QS); | |
638 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
639 | return -EINVAL; |
640 | } | |
641 | ||
642 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
643 | dev = *pdev; | |
644 | if (NULL == dev) | |
645 | return -ENOMEM; | |
646 | ||
647 | priv = netdev_priv(dev); | |
61c7a080 | 648 | priv->node = ofdev->dev.of_node; |
fba4ed03 SG |
649 | priv->ndev = dev; |
650 | ||
fba4ed03 | 651 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 652 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 653 | priv->num_rx_queues = num_rx_qs; |
46ceb60c | 654 | priv->num_grps = 0x0; |
b31a1d8b | 655 | |
0977f817 | 656 | /* Init Rx queue filer rule set linked list */ |
4aa3a715 SP |
657 | INIT_LIST_HEAD(&priv->rx_list.list); |
658 | priv->rx_list.count = 0; | |
659 | mutex_init(&priv->rx_queue_access); | |
660 | ||
b31a1d8b AF |
661 | model = of_get_property(np, "model", NULL); |
662 | ||
46ceb60c SG |
663 | for (i = 0; i < MAXGROUPS; i++) |
664 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 665 | |
46ceb60c SG |
666 | /* Parse and initialize group specific information */ |
667 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
668 | priv->mode = MQ_MG_MODE; | |
669 | for_each_child_of_node(np, child) { | |
670 | err = gfar_parse_group(child, priv, model); | |
671 | if (err) | |
672 | goto err_grp_init; | |
b31a1d8b | 673 | } |
46ceb60c SG |
674 | } else { |
675 | priv->mode = SQ_SG_MODE; | |
676 | err = gfar_parse_group(np, priv, model); | |
bc4598bc | 677 | if (err) |
46ceb60c | 678 | goto err_grp_init; |
b31a1d8b AF |
679 | } |
680 | ||
fba4ed03 SG |
681 | for (i = 0; i < priv->num_tx_queues; i++) |
682 | priv->tx_queue[i] = NULL; | |
683 | for (i = 0; i < priv->num_rx_queues; i++) | |
684 | priv->rx_queue[i] = NULL; | |
685 | ||
686 | for (i = 0; i < priv->num_tx_queues; i++) { | |
de47f072 JP |
687 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), |
688 | GFP_KERNEL); | |
fba4ed03 SG |
689 | if (!priv->tx_queue[i]) { |
690 | err = -ENOMEM; | |
691 | goto tx_alloc_failed; | |
692 | } | |
693 | priv->tx_queue[i]->tx_skbuff = NULL; | |
694 | priv->tx_queue[i]->qindex = i; | |
695 | priv->tx_queue[i]->dev = dev; | |
696 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
697 | } | |
698 | ||
699 | for (i = 0; i < priv->num_rx_queues; i++) { | |
de47f072 JP |
700 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), |
701 | GFP_KERNEL); | |
fba4ed03 SG |
702 | if (!priv->rx_queue[i]) { |
703 | err = -ENOMEM; | |
704 | goto rx_alloc_failed; | |
705 | } | |
706 | priv->rx_queue[i]->rx_skbuff = NULL; | |
707 | priv->rx_queue[i]->qindex = i; | |
708 | priv->rx_queue[i]->dev = dev; | |
709 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
710 | } | |
711 | ||
712 | ||
4d7902f2 AF |
713 | stash = of_get_property(np, "bd-stash", NULL); |
714 | ||
a12f801d | 715 | if (stash) { |
4d7902f2 AF |
716 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
717 | priv->bd_stash_en = 1; | |
718 | } | |
719 | ||
720 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
721 | ||
722 | if (stash_len) | |
723 | priv->rx_stash_size = *stash_len; | |
724 | ||
725 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
726 | ||
727 | if (stash_idx) | |
728 | priv->rx_stash_index = *stash_idx; | |
729 | ||
730 | if (stash_len || stash_idx) | |
731 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
732 | ||
b31a1d8b | 733 | mac_addr = of_get_mac_address(np); |
bc4598bc | 734 | |
b31a1d8b | 735 | if (mac_addr) |
6a3c910c | 736 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
b31a1d8b AF |
737 | |
738 | if (model && !strcasecmp(model, "TSEC")) | |
bc4598bc JC |
739 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
740 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
741 | FSL_GIANFAR_DEV_HAS_RMON | | |
742 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
743 | ||
b31a1d8b | 744 | if (model && !strcasecmp(model, "eTSEC")) |
bc4598bc JC |
745 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
746 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
747 | FSL_GIANFAR_DEV_HAS_RMON | | |
748 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
749 | FSL_GIANFAR_DEV_HAS_PADDING | | |
750 | FSL_GIANFAR_DEV_HAS_CSUM | | |
751 | FSL_GIANFAR_DEV_HAS_VLAN | | |
752 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
753 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | | |
754 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
755 | |
756 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
757 | ||
758 | /* We only care about rgmii-id. The rest are autodetected */ | |
759 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
760 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
761 | else | |
762 | priv->interface = PHY_INTERFACE_MODE_MII; | |
763 | ||
764 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
765 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
766 | ||
fe192a49 | 767 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
768 | |
769 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 770 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
771 | |
772 | return 0; | |
773 | ||
fba4ed03 SG |
774 | rx_alloc_failed: |
775 | free_rx_pointers(priv); | |
776 | tx_alloc_failed: | |
777 | free_tx_pointers(priv); | |
46ceb60c SG |
778 | err_grp_init: |
779 | unmap_group_regs(priv); | |
fba4ed03 | 780 | free_netdev(dev); |
b31a1d8b AF |
781 | return err; |
782 | } | |
783 | ||
cc772ab7 | 784 | static int gfar_hwtstamp_ioctl(struct net_device *netdev, |
bc4598bc | 785 | struct ifreq *ifr, int cmd) |
cc772ab7 MR |
786 | { |
787 | struct hwtstamp_config config; | |
788 | struct gfar_private *priv = netdev_priv(netdev); | |
789 | ||
790 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
791 | return -EFAULT; | |
792 | ||
793 | /* reserved for future extensions */ | |
794 | if (config.flags) | |
795 | return -EINVAL; | |
796 | ||
f0ee7acf MR |
797 | switch (config.tx_type) { |
798 | case HWTSTAMP_TX_OFF: | |
799 | priv->hwts_tx_en = 0; | |
800 | break; | |
801 | case HWTSTAMP_TX_ON: | |
802 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
803 | return -ERANGE; | |
804 | priv->hwts_tx_en = 1; | |
805 | break; | |
806 | default: | |
cc772ab7 | 807 | return -ERANGE; |
f0ee7acf | 808 | } |
cc772ab7 MR |
809 | |
810 | switch (config.rx_filter) { | |
811 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
812 | if (priv->hwts_rx_en) { |
813 | stop_gfar(netdev); | |
814 | priv->hwts_rx_en = 0; | |
815 | startup_gfar(netdev); | |
816 | } | |
cc772ab7 MR |
817 | break; |
818 | default: | |
819 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
820 | return -ERANGE; | |
97553f7f MR |
821 | if (!priv->hwts_rx_en) { |
822 | stop_gfar(netdev); | |
823 | priv->hwts_rx_en = 1; | |
824 | startup_gfar(netdev); | |
825 | } | |
cc772ab7 MR |
826 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
827 | break; | |
828 | } | |
829 | ||
830 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
831 | -EFAULT : 0; | |
832 | } | |
833 | ||
0faac9f7 CW |
834 | /* Ioctl MII Interface */ |
835 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
836 | { | |
837 | struct gfar_private *priv = netdev_priv(dev); | |
838 | ||
839 | if (!netif_running(dev)) | |
840 | return -EINVAL; | |
841 | ||
cc772ab7 MR |
842 | if (cmd == SIOCSHWTSTAMP) |
843 | return gfar_hwtstamp_ioctl(dev, rq, cmd); | |
844 | ||
0faac9f7 CW |
845 | if (!priv->phydev) |
846 | return -ENODEV; | |
847 | ||
28b04113 | 848 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
849 | } |
850 | ||
fba4ed03 SG |
851 | static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) |
852 | { | |
853 | unsigned int new_bit_map = 0x0; | |
854 | int mask = 0x1 << (max_qs - 1), i; | |
bc4598bc | 855 | |
fba4ed03 SG |
856 | for (i = 0; i < max_qs; i++) { |
857 | if (bit_map & mask) | |
858 | new_bit_map = new_bit_map + (1 << i); | |
859 | mask = mask >> 0x1; | |
860 | } | |
861 | return new_bit_map; | |
862 | } | |
7a8b3372 | 863 | |
18294ad1 AV |
864 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
865 | u32 class) | |
7a8b3372 SG |
866 | { |
867 | u32 rqfpr = FPR_FILER_MASK; | |
868 | u32 rqfcr = 0x0; | |
869 | ||
870 | rqfar--; | |
871 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
872 | priv->ftp_rqfpr[rqfar] = rqfpr; |
873 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
874 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
875 | ||
876 | rqfar--; | |
877 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
878 | priv->ftp_rqfpr[rqfar] = rqfpr; |
879 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
880 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
881 | ||
882 | rqfar--; | |
883 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
884 | rqfpr = class; | |
6c43e046 WJB |
885 | priv->ftp_rqfcr[rqfar] = rqfcr; |
886 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
887 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
888 | ||
889 | rqfar--; | |
890 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
891 | rqfpr = class; | |
6c43e046 WJB |
892 | priv->ftp_rqfcr[rqfar] = rqfcr; |
893 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
894 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
895 | ||
896 | return rqfar; | |
897 | } | |
898 | ||
899 | static void gfar_init_filer_table(struct gfar_private *priv) | |
900 | { | |
901 | int i = 0x0; | |
902 | u32 rqfar = MAX_FILER_IDX; | |
903 | u32 rqfcr = 0x0; | |
904 | u32 rqfpr = FPR_FILER_MASK; | |
905 | ||
906 | /* Default rule */ | |
907 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
908 | priv->ftp_rqfcr[rqfar] = rqfcr; |
909 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
910 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
911 | ||
912 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
913 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
914 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
915 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
916 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
917 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
918 | ||
85dd08eb | 919 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
920 | priv->cur_filer_idx = rqfar; |
921 | ||
922 | /* Rest are masked rules */ | |
923 | rqfcr = RQFCR_CMP_NOMATCH; | |
924 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
925 | priv->ftp_rqfcr[i] = rqfcr; |
926 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
927 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
928 | } | |
929 | } | |
930 | ||
7d350977 AV |
931 | static void gfar_detect_errata(struct gfar_private *priv) |
932 | { | |
933 | struct device *dev = &priv->ofdev->dev; | |
934 | unsigned int pvr = mfspr(SPRN_PVR); | |
935 | unsigned int svr = mfspr(SPRN_SVR); | |
936 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
937 | unsigned int rev = svr & 0xffff; | |
938 | ||
939 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
940 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
bc4598bc | 941 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
7d350977 AV |
942 | priv->errata |= GFAR_ERRATA_74; |
943 | ||
deb90eac AV |
944 | /* MPC8313 and MPC837x all rev */ |
945 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 946 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
deb90eac AV |
947 | priv->errata |= GFAR_ERRATA_76; |
948 | ||
511d934f AV |
949 | /* MPC8313 and MPC837x all rev */ |
950 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 951 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
511d934f AV |
952 | priv->errata |= GFAR_ERRATA_A002; |
953 | ||
4363c2fd AD |
954 | /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ |
955 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || | |
bc4598bc | 956 | (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) |
4363c2fd AD |
957 | priv->errata |= GFAR_ERRATA_12; |
958 | ||
7d350977 AV |
959 | if (priv->errata) |
960 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
961 | priv->errata); | |
962 | } | |
963 | ||
bb40dcbb | 964 | /* Set up the ethernet device structure, private data, |
0977f817 JC |
965 | * and anything else we need before we start |
966 | */ | |
74888760 | 967 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 LT |
968 | { |
969 | u32 tempval; | |
970 | struct net_device *dev = NULL; | |
971 | struct gfar_private *priv = NULL; | |
f4983704 | 972 | struct gfar __iomem *regs = NULL; |
46ceb60c | 973 | int err = 0, i, grp_idx = 0; |
fba4ed03 | 974 | u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; |
46ceb60c | 975 | u32 isrg = 0; |
18294ad1 | 976 | u32 __iomem *baddr; |
1da177e4 | 977 | |
fba4ed03 | 978 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 979 | |
fba4ed03 SG |
980 | if (err) |
981 | return err; | |
1da177e4 LT |
982 | |
983 | priv = netdev_priv(dev); | |
4826857f KG |
984 | priv->ndev = dev; |
985 | priv->ofdev = ofdev; | |
61c7a080 | 986 | priv->node = ofdev->dev.of_node; |
4826857f | 987 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 988 | |
d87eb127 | 989 | spin_lock_init(&priv->bflock); |
ab939905 | 990 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 991 | |
b31a1d8b | 992 | dev_set_drvdata(&ofdev->dev, priv); |
46ceb60c | 993 | regs = priv->gfargrp[0].regs; |
1da177e4 | 994 | |
7d350977 AV |
995 | gfar_detect_errata(priv); |
996 | ||
0977f817 JC |
997 | /* Stop the DMA engine now, in case it was running before |
998 | * (The firmware could have used it, and left it running). | |
999 | */ | |
257d938a | 1000 | gfar_halt(dev); |
1da177e4 LT |
1001 | |
1002 | /* Reset MAC layer */ | |
f4983704 | 1003 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); |
1da177e4 | 1004 | |
b98ac702 AF |
1005 | /* We need to delay at least 3 TX clocks */ |
1006 | udelay(2); | |
1007 | ||
1da177e4 | 1008 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
f4983704 | 1009 | gfar_write(®s->maccfg1, tempval); |
1da177e4 LT |
1010 | |
1011 | /* Initialize MACCFG2. */ | |
7d350977 AV |
1012 | tempval = MACCFG2_INIT_SETTINGS; |
1013 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1014 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1015 | gfar_write(®s->maccfg2, tempval); | |
1da177e4 LT |
1016 | |
1017 | /* Initialize ECNTRL */ | |
f4983704 | 1018 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
1da177e4 | 1019 | |
1da177e4 | 1020 | /* Set the dev->base_addr to the gfar reg region */ |
f4983704 | 1021 | dev->base_addr = (unsigned long) regs; |
1da177e4 | 1022 | |
b31a1d8b | 1023 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
1024 | |
1025 | /* Fill in the dev structure */ | |
1da177e4 | 1026 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1027 | dev->mtu = 1500; |
26ccfc37 | 1028 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1029 | dev->ethtool_ops = &gfar_ethtool_ops; |
1030 | ||
fba4ed03 | 1031 | /* Register for napi ...We are registering NAPI for each grp */ |
46ceb60c | 1032 | for (i = 0; i < priv->num_grps; i++) |
bc4598bc JC |
1033 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, |
1034 | GFAR_DEV_WEIGHT); | |
a12f801d | 1035 | |
b31a1d8b | 1036 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 | 1037 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1038 | NETIF_F_RXCSUM; |
8b3afe95 | 1039 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1040 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; |
8b3afe95 | 1041 | } |
0bbaf069 | 1042 | |
87c288c6 JP |
1043 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
1044 | dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
e2c53be2 | 1045 | dev->features |= NETIF_F_HW_VLAN_RX; |
87c288c6 | 1046 | } |
0bbaf069 | 1047 | |
b31a1d8b | 1048 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
1049 | priv->extended_hash = 1; |
1050 | priv->hash_width = 9; | |
1051 | ||
f4983704 SG |
1052 | priv->hash_regs[0] = ®s->igaddr0; |
1053 | priv->hash_regs[1] = ®s->igaddr1; | |
1054 | priv->hash_regs[2] = ®s->igaddr2; | |
1055 | priv->hash_regs[3] = ®s->igaddr3; | |
1056 | priv->hash_regs[4] = ®s->igaddr4; | |
1057 | priv->hash_regs[5] = ®s->igaddr5; | |
1058 | priv->hash_regs[6] = ®s->igaddr6; | |
1059 | priv->hash_regs[7] = ®s->igaddr7; | |
1060 | priv->hash_regs[8] = ®s->gaddr0; | |
1061 | priv->hash_regs[9] = ®s->gaddr1; | |
1062 | priv->hash_regs[10] = ®s->gaddr2; | |
1063 | priv->hash_regs[11] = ®s->gaddr3; | |
1064 | priv->hash_regs[12] = ®s->gaddr4; | |
1065 | priv->hash_regs[13] = ®s->gaddr5; | |
1066 | priv->hash_regs[14] = ®s->gaddr6; | |
1067 | priv->hash_regs[15] = ®s->gaddr7; | |
0bbaf069 KG |
1068 | |
1069 | } else { | |
1070 | priv->extended_hash = 0; | |
1071 | priv->hash_width = 8; | |
1072 | ||
f4983704 SG |
1073 | priv->hash_regs[0] = ®s->gaddr0; |
1074 | priv->hash_regs[1] = ®s->gaddr1; | |
1075 | priv->hash_regs[2] = ®s->gaddr2; | |
1076 | priv->hash_regs[3] = ®s->gaddr3; | |
1077 | priv->hash_regs[4] = ®s->gaddr4; | |
1078 | priv->hash_regs[5] = ®s->gaddr5; | |
1079 | priv->hash_regs[6] = ®s->gaddr6; | |
1080 | priv->hash_regs[7] = ®s->gaddr7; | |
0bbaf069 KG |
1081 | } |
1082 | ||
b31a1d8b | 1083 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
1084 | priv->padding = DEFAULT_PADDING; |
1085 | else | |
1086 | priv->padding = 0; | |
1087 | ||
cc772ab7 | 1088 | if (dev->features & NETIF_F_IP_CSUM || |
bc4598bc | 1089 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) |
bee9e58c | 1090 | dev->needed_headroom = GMAC_FCB_LEN; |
1da177e4 | 1091 | |
46ceb60c SG |
1092 | /* Program the isrg regs only if number of grps > 1 */ |
1093 | if (priv->num_grps > 1) { | |
1094 | baddr = ®s->isrg0; | |
1095 | for (i = 0; i < priv->num_grps; i++) { | |
1096 | isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); | |
1097 | isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); | |
1098 | gfar_write(baddr, isrg); | |
1099 | baddr++; | |
1100 | isrg = 0x0; | |
1101 | } | |
1102 | } | |
1103 | ||
fba4ed03 | 1104 | /* Need to reverse the bit maps as bit_map's MSB is q0 |
984b3f57 | 1105 | * but, for_each_set_bit parses from right to left, which |
0977f817 JC |
1106 | * basically reverses the queue numbers |
1107 | */ | |
46ceb60c | 1108 | for (i = 0; i< priv->num_grps; i++) { |
bc4598bc JC |
1109 | priv->gfargrp[i].tx_bit_map = |
1110 | reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS); | |
1111 | priv->gfargrp[i].rx_bit_map = | |
1112 | reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS); | |
46ceb60c SG |
1113 | } |
1114 | ||
1115 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
0977f817 JC |
1116 | * also assign queues to groups |
1117 | */ | |
46ceb60c SG |
1118 | for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { |
1119 | priv->gfargrp[grp_idx].num_rx_queues = 0x0; | |
bc4598bc | 1120 | |
984b3f57 | 1121 | for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, |
bc4598bc | 1122 | priv->num_rx_queues) { |
46ceb60c SG |
1123 | priv->gfargrp[grp_idx].num_rx_queues++; |
1124 | priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1125 | rstat = rstat | (RSTAT_CLEAR_RHALT >> i); | |
1126 | rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
1127 | } | |
1128 | priv->gfargrp[grp_idx].num_tx_queues = 0x0; | |
bc4598bc | 1129 | |
984b3f57 | 1130 | for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, |
bc4598bc | 1131 | priv->num_tx_queues) { |
46ceb60c SG |
1132 | priv->gfargrp[grp_idx].num_tx_queues++; |
1133 | priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1134 | tstat = tstat | (TSTAT_CLEAR_THALT >> i); | |
1135 | tqueue = tqueue | (TQUEUE_EN0 >> i); | |
1136 | } | |
1137 | priv->gfargrp[grp_idx].rstat = rstat; | |
1138 | priv->gfargrp[grp_idx].tstat = tstat; | |
1139 | rstat = tstat =0; | |
fba4ed03 | 1140 | } |
fba4ed03 SG |
1141 | |
1142 | gfar_write(®s->rqueue, rqueue); | |
1143 | gfar_write(®s->tqueue, tqueue); | |
1144 | ||
1da177e4 | 1145 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; |
1da177e4 | 1146 | |
a12f801d | 1147 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1148 | for (i = 0; i < priv->num_tx_queues; i++) { |
1149 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1150 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1151 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1152 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1153 | } | |
a12f801d | 1154 | |
fba4ed03 SG |
1155 | for (i = 0; i < priv->num_rx_queues; i++) { |
1156 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1157 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1158 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1159 | } | |
1da177e4 | 1160 | |
0977f817 | 1161 | /* always enable rx filer */ |
4aa3a715 | 1162 | priv->rx_filer_enable = 1; |
0bbaf069 KG |
1163 | /* Enable most messages by default */ |
1164 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
b98b8bab CM |
1165 | /* use pritority h/w tx queue scheduling for single queue devices */ |
1166 | if (priv->num_tx_queues == 1) | |
1167 | priv->prio_sched_en = 1; | |
0bbaf069 | 1168 | |
d3eab82b TP |
1169 | /* Carrier starts down, phylib will bring it up */ |
1170 | netif_carrier_off(dev); | |
1171 | ||
1da177e4 LT |
1172 | err = register_netdev(dev); |
1173 | ||
1174 | if (err) { | |
59deab26 | 1175 | pr_err("%s: Cannot register net device, aborting\n", dev->name); |
1da177e4 LT |
1176 | goto register_fail; |
1177 | } | |
1178 | ||
2884e5cc | 1179 | device_init_wakeup(&dev->dev, |
bc4598bc JC |
1180 | priv->device_flags & |
1181 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
2884e5cc | 1182 | |
c50a5d9a | 1183 | /* fill out IRQ number and name fields */ |
46ceb60c | 1184 | for (i = 0; i < priv->num_grps; i++) { |
46ceb60c | 1185 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0015e551 JP |
1186 | sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s", |
1187 | dev->name, "_g", '0' + i, "_tx"); | |
1188 | sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s", | |
1189 | dev->name, "_g", '0' + i, "_rx"); | |
1190 | sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s", | |
1191 | dev->name, "_g", '0' + i, "_er"); | |
46ceb60c | 1192 | } else |
0015e551 | 1193 | strcpy(priv->gfargrp[i].int_name_tx, dev->name); |
46ceb60c | 1194 | } |
c50a5d9a | 1195 | |
7a8b3372 SG |
1196 | /* Initialize the filer table */ |
1197 | gfar_init_filer_table(priv); | |
1198 | ||
7f7f5316 AF |
1199 | /* Create all the sysfs files */ |
1200 | gfar_init_sysfs(dev); | |
1201 | ||
1da177e4 | 1202 | /* Print out the device info */ |
59deab26 | 1203 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
1da177e4 | 1204 | |
0977f817 JC |
1205 | /* Even more device info helps when determining which kernel |
1206 | * provided which set of benchmarks. | |
1207 | */ | |
59deab26 | 1208 | netdev_info(dev, "Running with NAPI enabled\n"); |
fba4ed03 | 1209 | for (i = 0; i < priv->num_rx_queues; i++) |
59deab26 JP |
1210 | netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", |
1211 | i, priv->rx_queue[i]->rx_ring_size); | |
bc4598bc | 1212 | for (i = 0; i < priv->num_tx_queues; i++) |
59deab26 JP |
1213 | netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", |
1214 | i, priv->tx_queue[i]->tx_ring_size); | |
1da177e4 LT |
1215 | |
1216 | return 0; | |
1217 | ||
1218 | register_fail: | |
46ceb60c | 1219 | unmap_group_regs(priv); |
fba4ed03 SG |
1220 | free_tx_pointers(priv); |
1221 | free_rx_pointers(priv); | |
fe192a49 GL |
1222 | if (priv->phy_node) |
1223 | of_node_put(priv->phy_node); | |
1224 | if (priv->tbi_node) | |
1225 | of_node_put(priv->tbi_node); | |
1da177e4 | 1226 | free_netdev(dev); |
bb40dcbb | 1227 | return err; |
1da177e4 LT |
1228 | } |
1229 | ||
2dc11581 | 1230 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1231 | { |
b31a1d8b | 1232 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 1233 | |
fe192a49 GL |
1234 | if (priv->phy_node) |
1235 | of_node_put(priv->phy_node); | |
1236 | if (priv->tbi_node) | |
1237 | of_node_put(priv->tbi_node); | |
1238 | ||
b31a1d8b | 1239 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 1240 | |
d9d8e041 | 1241 | unregister_netdev(priv->ndev); |
46ceb60c | 1242 | unmap_group_regs(priv); |
4826857f | 1243 | free_netdev(priv->ndev); |
1da177e4 LT |
1244 | |
1245 | return 0; | |
1246 | } | |
1247 | ||
d87eb127 | 1248 | #ifdef CONFIG_PM |
be926fc4 AV |
1249 | |
1250 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1251 | { |
be926fc4 AV |
1252 | struct gfar_private *priv = dev_get_drvdata(dev); |
1253 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1254 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1255 | unsigned long flags; |
1256 | u32 tempval; | |
1257 | ||
1258 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1259 | (priv->device_flags & |
1260 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1261 | |
be926fc4 | 1262 | netif_device_detach(ndev); |
d87eb127 | 1263 | |
be926fc4 | 1264 | if (netif_running(ndev)) { |
fba4ed03 SG |
1265 | |
1266 | local_irq_save(flags); | |
1267 | lock_tx_qs(priv); | |
1268 | lock_rx_qs(priv); | |
d87eb127 | 1269 | |
be926fc4 | 1270 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1271 | |
1272 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1273 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1274 | |
1275 | tempval &= ~MACCFG1_TX_EN; | |
1276 | ||
1277 | if (!magic_packet) | |
1278 | tempval &= ~MACCFG1_RX_EN; | |
1279 | ||
f4983704 | 1280 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1281 | |
fba4ed03 SG |
1282 | unlock_rx_qs(priv); |
1283 | unlock_tx_qs(priv); | |
1284 | local_irq_restore(flags); | |
d87eb127 | 1285 | |
46ceb60c | 1286 | disable_napi(priv); |
d87eb127 SW |
1287 | |
1288 | if (magic_packet) { | |
1289 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1290 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1291 | |
1292 | /* Enable Magic Packet mode */ | |
f4983704 | 1293 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1294 | tempval |= MACCFG2_MPEN; |
f4983704 | 1295 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1296 | } else { |
1297 | phy_stop(priv->phydev); | |
1298 | } | |
1299 | } | |
1300 | ||
1301 | return 0; | |
1302 | } | |
1303 | ||
be926fc4 | 1304 | static int gfar_resume(struct device *dev) |
d87eb127 | 1305 | { |
be926fc4 AV |
1306 | struct gfar_private *priv = dev_get_drvdata(dev); |
1307 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1308 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1309 | unsigned long flags; |
1310 | u32 tempval; | |
1311 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1312 | (priv->device_flags & |
1313 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1314 | |
be926fc4 AV |
1315 | if (!netif_running(ndev)) { |
1316 | netif_device_attach(ndev); | |
d87eb127 SW |
1317 | return 0; |
1318 | } | |
1319 | ||
1320 | if (!magic_packet && priv->phydev) | |
1321 | phy_start(priv->phydev); | |
1322 | ||
1323 | /* Disable Magic Packet mode, in case something | |
1324 | * else woke us up. | |
1325 | */ | |
fba4ed03 SG |
1326 | local_irq_save(flags); |
1327 | lock_tx_qs(priv); | |
1328 | lock_rx_qs(priv); | |
d87eb127 | 1329 | |
f4983704 | 1330 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1331 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1332 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1333 | |
be926fc4 | 1334 | gfar_start(ndev); |
d87eb127 | 1335 | |
fba4ed03 SG |
1336 | unlock_rx_qs(priv); |
1337 | unlock_tx_qs(priv); | |
1338 | local_irq_restore(flags); | |
d87eb127 | 1339 | |
be926fc4 AV |
1340 | netif_device_attach(ndev); |
1341 | ||
46ceb60c | 1342 | enable_napi(priv); |
be926fc4 AV |
1343 | |
1344 | return 0; | |
1345 | } | |
1346 | ||
1347 | static int gfar_restore(struct device *dev) | |
1348 | { | |
1349 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1350 | struct net_device *ndev = priv->ndev; | |
1351 | ||
103cdd1d WD |
1352 | if (!netif_running(ndev)) { |
1353 | netif_device_attach(ndev); | |
1354 | ||
be926fc4 | 1355 | return 0; |
103cdd1d | 1356 | } |
be926fc4 | 1357 | |
1eb8f7a7 CM |
1358 | if (gfar_init_bds(ndev)) { |
1359 | free_skb_resources(priv); | |
1360 | return -ENOMEM; | |
1361 | } | |
1362 | ||
be926fc4 AV |
1363 | init_registers(ndev); |
1364 | gfar_set_mac_address(ndev); | |
1365 | gfar_init_mac(ndev); | |
1366 | gfar_start(ndev); | |
1367 | ||
1368 | priv->oldlink = 0; | |
1369 | priv->oldspeed = 0; | |
1370 | priv->oldduplex = -1; | |
1371 | ||
1372 | if (priv->phydev) | |
1373 | phy_start(priv->phydev); | |
d87eb127 | 1374 | |
be926fc4 | 1375 | netif_device_attach(ndev); |
5ea681d4 | 1376 | enable_napi(priv); |
d87eb127 SW |
1377 | |
1378 | return 0; | |
1379 | } | |
be926fc4 AV |
1380 | |
1381 | static struct dev_pm_ops gfar_pm_ops = { | |
1382 | .suspend = gfar_suspend, | |
1383 | .resume = gfar_resume, | |
1384 | .freeze = gfar_suspend, | |
1385 | .thaw = gfar_resume, | |
1386 | .restore = gfar_restore, | |
1387 | }; | |
1388 | ||
1389 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1390 | ||
d87eb127 | 1391 | #else |
be926fc4 AV |
1392 | |
1393 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1394 | |
d87eb127 | 1395 | #endif |
1da177e4 | 1396 | |
e8a2b6a4 AF |
1397 | /* Reads the controller's registers to determine what interface |
1398 | * connects it to the PHY. | |
1399 | */ | |
1400 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1401 | { | |
1402 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1403 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1404 | u32 ecntrl; |
1405 | ||
f4983704 | 1406 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1407 | |
1408 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1409 | return PHY_INTERFACE_MODE_SGMII; | |
1410 | ||
1411 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1412 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1413 | return PHY_INTERFACE_MODE_RTBI; | |
1414 | else | |
1415 | return PHY_INTERFACE_MODE_TBI; | |
1416 | } | |
1417 | ||
1418 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
bc4598bc | 1419 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) { |
e8a2b6a4 | 1420 | return PHY_INTERFACE_MODE_RMII; |
bc4598bc | 1421 | } |
7132ab7f | 1422 | else { |
b31a1d8b | 1423 | phy_interface_t interface = priv->interface; |
7132ab7f | 1424 | |
0977f817 | 1425 | /* This isn't autodetected right now, so it must |
7132ab7f AF |
1426 | * be set by the device tree or platform code. |
1427 | */ | |
1428 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1429 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1430 | ||
e8a2b6a4 | 1431 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1432 | } |
e8a2b6a4 AF |
1433 | } |
1434 | ||
b31a1d8b | 1435 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1436 | return PHY_INTERFACE_MODE_GMII; |
1437 | ||
1438 | return PHY_INTERFACE_MODE_MII; | |
1439 | } | |
1440 | ||
1441 | ||
bb40dcbb AF |
1442 | /* Initializes driver's PHY state, and attaches to the PHY. |
1443 | * Returns 0 on success. | |
1da177e4 LT |
1444 | */ |
1445 | static int init_phy(struct net_device *dev) | |
1446 | { | |
1447 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1448 | uint gigabit_support = |
b31a1d8b | 1449 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 1450 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 1451 | phy_interface_t interface; |
1da177e4 LT |
1452 | |
1453 | priv->oldlink = 0; | |
1454 | priv->oldspeed = 0; | |
1455 | priv->oldduplex = -1; | |
1456 | ||
e8a2b6a4 AF |
1457 | interface = gfar_get_interface(dev); |
1458 | ||
1db780f8 AV |
1459 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1460 | interface); | |
1461 | if (!priv->phydev) | |
1462 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1463 | interface); | |
1464 | if (!priv->phydev) { | |
1465 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1466 | return -ENODEV; | |
fe192a49 | 1467 | } |
1da177e4 | 1468 | |
d3c12873 KJ |
1469 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1470 | gfar_configure_serdes(dev); | |
1471 | ||
bb40dcbb | 1472 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1473 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1474 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1475 | |
1476 | return 0; | |
1da177e4 LT |
1477 | } |
1478 | ||
0977f817 | 1479 | /* Initialize TBI PHY interface for communicating with the |
d0313587 PG |
1480 | * SERDES lynx PHY on the chip. We communicate with this PHY |
1481 | * through the MDIO bus on each controller, treating it as a | |
1482 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1483 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1484 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1485 | * value doesn't matter, as there are no other PHYs on the bus. | |
1486 | */ | |
d3c12873 KJ |
1487 | static void gfar_configure_serdes(struct net_device *dev) |
1488 | { | |
1489 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1490 | struct phy_device *tbiphy; |
1491 | ||
1492 | if (!priv->tbi_node) { | |
1493 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1494 | "device tree specify a tbi-handle\n"); | |
1495 | return; | |
1496 | } | |
c132419e | 1497 | |
fe192a49 GL |
1498 | tbiphy = of_phy_find_device(priv->tbi_node); |
1499 | if (!tbiphy) { | |
1500 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1501 | return; |
1502 | } | |
d3c12873 | 1503 | |
0977f817 | 1504 | /* If the link is already up, we must already be ok, and don't need to |
bdb59f94 TP |
1505 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1506 | * everything for us? Resetting it takes the link down and requires | |
1507 | * several seconds for it to come back. | |
1508 | */ | |
fe192a49 | 1509 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1510 | return; |
d3c12873 | 1511 | |
d0313587 | 1512 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1513 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1514 | |
fe192a49 | 1515 | phy_write(tbiphy, MII_ADVERTISE, |
bc4598bc JC |
1516 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1517 | ADVERTISE_1000XPSE_ASYM); | |
d3c12873 | 1518 | |
bc4598bc JC |
1519 | phy_write(tbiphy, MII_BMCR, |
1520 | BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | | |
1521 | BMCR_SPEED1000); | |
d3c12873 KJ |
1522 | } |
1523 | ||
1da177e4 LT |
1524 | static void init_registers(struct net_device *dev) |
1525 | { | |
1526 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 1527 | struct gfar __iomem *regs = NULL; |
3a2e16c8 | 1528 | int i; |
1da177e4 | 1529 | |
46ceb60c SG |
1530 | for (i = 0; i < priv->num_grps; i++) { |
1531 | regs = priv->gfargrp[i].regs; | |
1532 | /* Clear IEVENT */ | |
1533 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1da177e4 | 1534 | |
46ceb60c SG |
1535 | /* Initialize IMASK */ |
1536 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1537 | } | |
1da177e4 | 1538 | |
46ceb60c | 1539 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1540 | /* Init hash registers to zero */ |
f4983704 SG |
1541 | gfar_write(®s->igaddr0, 0); |
1542 | gfar_write(®s->igaddr1, 0); | |
1543 | gfar_write(®s->igaddr2, 0); | |
1544 | gfar_write(®s->igaddr3, 0); | |
1545 | gfar_write(®s->igaddr4, 0); | |
1546 | gfar_write(®s->igaddr5, 0); | |
1547 | gfar_write(®s->igaddr6, 0); | |
1548 | gfar_write(®s->igaddr7, 0); | |
1549 | ||
1550 | gfar_write(®s->gaddr0, 0); | |
1551 | gfar_write(®s->gaddr1, 0); | |
1552 | gfar_write(®s->gaddr2, 0); | |
1553 | gfar_write(®s->gaddr3, 0); | |
1554 | gfar_write(®s->gaddr4, 0); | |
1555 | gfar_write(®s->gaddr5, 0); | |
1556 | gfar_write(®s->gaddr6, 0); | |
1557 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1558 | |
1da177e4 | 1559 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1560 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1561 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1562 | |
1563 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1564 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1565 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1566 | } |
1567 | ||
1568 | /* Initialize the max receive buffer length */ | |
f4983704 | 1569 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1570 | |
1da177e4 | 1571 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1572 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1573 | } |
1574 | ||
511d934f AV |
1575 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1576 | { | |
1577 | u32 res; | |
1578 | ||
0977f817 | 1579 | /* Normaly TSEC should not hang on GRS commands, so we should |
511d934f AV |
1580 | * actually wait for IEVENT_GRSC flag. |
1581 | */ | |
1582 | if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) | |
1583 | return 0; | |
1584 | ||
0977f817 | 1585 | /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are |
511d934f AV |
1586 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle |
1587 | * and the Rx can be safely reset. | |
1588 | */ | |
1589 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1590 | res &= 0x7f807f80; | |
1591 | if ((res & 0xffff) == (res >> 16)) | |
1592 | return 1; | |
1593 | ||
1594 | return 0; | |
1595 | } | |
0bbaf069 KG |
1596 | |
1597 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1598 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1599 | { |
1600 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1601 | struct gfar __iomem *regs = NULL; |
1da177e4 | 1602 | u32 tempval; |
3a2e16c8 | 1603 | int i; |
1da177e4 | 1604 | |
46ceb60c SG |
1605 | for (i = 0; i < priv->num_grps; i++) { |
1606 | regs = priv->gfargrp[i].regs; | |
1607 | /* Mask all interrupts */ | |
1608 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1da177e4 | 1609 | |
46ceb60c SG |
1610 | /* Clear all interrupts */ |
1611 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1612 | } | |
1da177e4 | 1613 | |
46ceb60c | 1614 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1615 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1616 | tempval = gfar_read(®s->dmactrl); |
bc4598bc JC |
1617 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != |
1618 | (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1619 | int ret; |
1620 | ||
1da177e4 | 1621 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1622 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1623 | |
511d934f AV |
1624 | do { |
1625 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1626 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1627 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1628 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1629 | ret = __gfar_is_rx_idle(priv); | |
1630 | } while (!ret); | |
1da177e4 | 1631 | } |
d87eb127 | 1632 | } |
d87eb127 SW |
1633 | |
1634 | /* Halt the receive and transmit queues */ | |
1635 | void gfar_halt(struct net_device *dev) | |
1636 | { | |
1637 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1638 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1639 | u32 tempval; |
1da177e4 | 1640 | |
2a54adc3 SW |
1641 | gfar_halt_nodisable(dev); |
1642 | ||
1da177e4 LT |
1643 | /* Disable Rx and Tx */ |
1644 | tempval = gfar_read(®s->maccfg1); | |
1645 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1646 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1647 | } |
1648 | ||
46ceb60c SG |
1649 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1650 | { | |
1651 | free_irq(grp->interruptError, grp); | |
1652 | free_irq(grp->interruptTransmit, grp); | |
1653 | free_irq(grp->interruptReceive, grp); | |
1654 | } | |
1655 | ||
0bbaf069 KG |
1656 | void stop_gfar(struct net_device *dev) |
1657 | { | |
1658 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1659 | unsigned long flags; |
46ceb60c | 1660 | int i; |
0bbaf069 | 1661 | |
bb40dcbb AF |
1662 | phy_stop(priv->phydev); |
1663 | ||
a12f801d | 1664 | |
0bbaf069 | 1665 | /* Lock it down */ |
fba4ed03 SG |
1666 | local_irq_save(flags); |
1667 | lock_tx_qs(priv); | |
1668 | lock_rx_qs(priv); | |
0bbaf069 | 1669 | |
0bbaf069 | 1670 | gfar_halt(dev); |
1da177e4 | 1671 | |
fba4ed03 SG |
1672 | unlock_rx_qs(priv); |
1673 | unlock_tx_qs(priv); | |
1674 | local_irq_restore(flags); | |
1da177e4 LT |
1675 | |
1676 | /* Free the IRQs */ | |
b31a1d8b | 1677 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1678 | for (i = 0; i < priv->num_grps; i++) |
1679 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1680 | } else { |
46ceb60c SG |
1681 | for (i = 0; i < priv->num_grps; i++) |
1682 | free_irq(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 1683 | &priv->gfargrp[i]); |
1da177e4 LT |
1684 | } |
1685 | ||
1686 | free_skb_resources(priv); | |
1da177e4 LT |
1687 | } |
1688 | ||
fba4ed03 | 1689 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1690 | { |
1da177e4 | 1691 | struct txbd8 *txbdp; |
fba4ed03 | 1692 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1693 | int i, j; |
1da177e4 | 1694 | |
a12f801d | 1695 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1696 | |
a12f801d SG |
1697 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1698 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1699 | continue; |
1da177e4 | 1700 | |
4826857f | 1701 | dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, |
bc4598bc | 1702 | txbdp->length, DMA_TO_DEVICE); |
4669bc90 | 1703 | txbdp->lstatus = 0; |
fba4ed03 | 1704 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
bc4598bc | 1705 | j++) { |
4669bc90 | 1706 | txbdp++; |
4826857f | 1707 | dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, |
bc4598bc | 1708 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1709 | } |
ad5da7ab | 1710 | txbdp++; |
a12f801d SG |
1711 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1712 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1713 | } |
a12f801d | 1714 | kfree(tx_queue->tx_skbuff); |
1eb8f7a7 | 1715 | tx_queue->tx_skbuff = NULL; |
fba4ed03 | 1716 | } |
1da177e4 | 1717 | |
fba4ed03 SG |
1718 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1719 | { | |
1720 | struct rxbd8 *rxbdp; | |
1721 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1722 | int i; | |
1da177e4 | 1723 | |
fba4ed03 | 1724 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1725 | |
a12f801d SG |
1726 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1727 | if (rx_queue->rx_skbuff[i]) { | |
fba4ed03 | 1728 | dma_unmap_single(&priv->ofdev->dev, |
bc4598bc JC |
1729 | rxbdp->bufPtr, priv->rx_buffer_size, |
1730 | DMA_FROM_DEVICE); | |
a12f801d SG |
1731 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1732 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1733 | } |
e69edd21 AV |
1734 | rxbdp->lstatus = 0; |
1735 | rxbdp->bufPtr = 0; | |
1736 | rxbdp++; | |
1da177e4 | 1737 | } |
a12f801d | 1738 | kfree(rx_queue->rx_skbuff); |
1eb8f7a7 | 1739 | rx_queue->rx_skbuff = NULL; |
fba4ed03 | 1740 | } |
e69edd21 | 1741 | |
fba4ed03 | 1742 | /* If there are any tx skbs or rx skbs still around, free them. |
0977f817 JC |
1743 | * Then free tx_skbuff and rx_skbuff |
1744 | */ | |
fba4ed03 SG |
1745 | static void free_skb_resources(struct gfar_private *priv) |
1746 | { | |
1747 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1748 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1749 | int i; | |
1750 | ||
1751 | /* Go through all the buffer descriptors and free their data buffers */ | |
1752 | for (i = 0; i < priv->num_tx_queues; i++) { | |
d8a0f1b0 | 1753 | struct netdev_queue *txq; |
bc4598bc | 1754 | |
fba4ed03 | 1755 | tx_queue = priv->tx_queue[i]; |
d8a0f1b0 | 1756 | txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); |
bc4598bc | 1757 | if (tx_queue->tx_skbuff) |
fba4ed03 | 1758 | free_skb_tx_queue(tx_queue); |
d8a0f1b0 | 1759 | netdev_tx_reset_queue(txq); |
fba4ed03 SG |
1760 | } |
1761 | ||
1762 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1763 | rx_queue = priv->rx_queue[i]; | |
bc4598bc | 1764 | if (rx_queue->rx_skbuff) |
fba4ed03 SG |
1765 | free_skb_rx_queue(rx_queue); |
1766 | } | |
1767 | ||
1768 | dma_free_coherent(&priv->ofdev->dev, | |
bc4598bc JC |
1769 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
1770 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1771 | priv->tx_queue[0]->tx_bd_base, | |
1772 | priv->tx_queue[0]->tx_bd_dma_base); | |
1da177e4 LT |
1773 | } |
1774 | ||
0bbaf069 KG |
1775 | void gfar_start(struct net_device *dev) |
1776 | { | |
1777 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1778 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1779 | u32 tempval; |
46ceb60c | 1780 | int i = 0; |
0bbaf069 KG |
1781 | |
1782 | /* Enable Rx and Tx in MACCFG1 */ | |
1783 | tempval = gfar_read(®s->maccfg1); | |
1784 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1785 | gfar_write(®s->maccfg1, tempval); | |
1786 | ||
1787 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1788 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1789 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1790 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1791 | |
0bbaf069 | 1792 | /* Make sure we aren't stopped */ |
f4983704 | 1793 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1794 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1795 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1796 | |
46ceb60c SG |
1797 | for (i = 0; i < priv->num_grps; i++) { |
1798 | regs = priv->gfargrp[i].regs; | |
1799 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1800 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1801 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
1802 | /* Unmask the interrupts we look for */ | |
1803 | gfar_write(®s->imask, IMASK_DEFAULT); | |
1804 | } | |
12dea57b | 1805 | |
1ae5dc34 | 1806 | dev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1807 | } |
1808 | ||
46ceb60c | 1809 | void gfar_configure_coalescing(struct gfar_private *priv, |
bc4598bc | 1810 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1811 | { |
46ceb60c | 1812 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1813 | u32 __iomem *baddr; |
46ceb60c | 1814 | int i = 0; |
1da177e4 | 1815 | |
46ceb60c SG |
1816 | /* Backward compatible case ---- even if we enable |
1817 | * multiple queues, there's only single reg to program | |
1818 | */ | |
1819 | gfar_write(®s->txic, 0); | |
bc4598bc | 1820 | if (likely(priv->tx_queue[0]->txcoalescing)) |
46ceb60c | 1821 | gfar_write(®s->txic, priv->tx_queue[0]->txic); |
1da177e4 | 1822 | |
46ceb60c | 1823 | gfar_write(®s->rxic, 0); |
bc4598bc | 1824 | if (unlikely(priv->rx_queue[0]->rxcoalescing)) |
46ceb60c | 1825 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); |
815b97c6 | 1826 | |
46ceb60c SG |
1827 | if (priv->mode == MQ_MG_MODE) { |
1828 | baddr = ®s->txic0; | |
984b3f57 | 1829 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
9740e001 CM |
1830 | gfar_write(baddr + i, 0); |
1831 | if (likely(priv->tx_queue[i]->txcoalescing)) | |
46ceb60c | 1832 | gfar_write(baddr + i, priv->tx_queue[i]->txic); |
46ceb60c SG |
1833 | } |
1834 | ||
1835 | baddr = ®s->rxic0; | |
984b3f57 | 1836 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
9740e001 CM |
1837 | gfar_write(baddr + i, 0); |
1838 | if (likely(priv->rx_queue[i]->rxcoalescing)) | |
46ceb60c | 1839 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); |
46ceb60c SG |
1840 | } |
1841 | } | |
1842 | } | |
1843 | ||
1844 | static int register_grp_irqs(struct gfar_priv_grp *grp) | |
1845 | { | |
1846 | struct gfar_private *priv = grp->priv; | |
1847 | struct net_device *dev = priv->ndev; | |
1848 | int err; | |
1da177e4 | 1849 | |
1da177e4 | 1850 | /* If the device has multiple interrupts, register for |
0977f817 JC |
1851 | * them. Otherwise, only register for the one |
1852 | */ | |
b31a1d8b | 1853 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1854 | /* Install our interrupt handlers for Error, |
0977f817 JC |
1855 | * Transmit, and Receive |
1856 | */ | |
bc4598bc JC |
1857 | if ((err = request_irq(grp->interruptError, gfar_error, |
1858 | 0, grp->int_name_er, grp)) < 0) { | |
59deab26 JP |
1859 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1860 | grp->interruptError); | |
46ceb60c | 1861 | |
2145f1af | 1862 | goto err_irq_fail; |
1da177e4 LT |
1863 | } |
1864 | ||
46ceb60c | 1865 | if ((err = request_irq(grp->interruptTransmit, gfar_transmit, |
bc4598bc | 1866 | 0, grp->int_name_tx, grp)) < 0) { |
59deab26 JP |
1867 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1868 | grp->interruptTransmit); | |
1da177e4 LT |
1869 | goto tx_irq_fail; |
1870 | } | |
1871 | ||
bc4598bc JC |
1872 | if ((err = request_irq(grp->interruptReceive, gfar_receive, |
1873 | 0, grp->int_name_rx, grp)) < 0) { | |
59deab26 JP |
1874 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1875 | grp->interruptReceive); | |
1da177e4 LT |
1876 | goto rx_irq_fail; |
1877 | } | |
1878 | } else { | |
bc4598bc JC |
1879 | if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, |
1880 | 0, grp->int_name_tx, grp)) < 0) { | |
59deab26 JP |
1881 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
1882 | grp->interruptTransmit); | |
1da177e4 LT |
1883 | goto err_irq_fail; |
1884 | } | |
1885 | } | |
1886 | ||
46ceb60c SG |
1887 | return 0; |
1888 | ||
1889 | rx_irq_fail: | |
1890 | free_irq(grp->interruptTransmit, grp); | |
1891 | tx_irq_fail: | |
1892 | free_irq(grp->interruptError, grp); | |
1893 | err_irq_fail: | |
1894 | return err; | |
1895 | ||
1896 | } | |
1897 | ||
1898 | /* Bring the controller up and running */ | |
1899 | int startup_gfar(struct net_device *ndev) | |
1900 | { | |
1901 | struct gfar_private *priv = netdev_priv(ndev); | |
1902 | struct gfar __iomem *regs = NULL; | |
1903 | int err, i, j; | |
1904 | ||
1905 | for (i = 0; i < priv->num_grps; i++) { | |
1906 | regs= priv->gfargrp[i].regs; | |
1907 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1908 | } | |
1909 | ||
1910 | regs= priv->gfargrp[0].regs; | |
1911 | err = gfar_alloc_skb_resources(ndev); | |
1912 | if (err) | |
1913 | return err; | |
1914 | ||
1915 | gfar_init_mac(ndev); | |
1916 | ||
1917 | for (i = 0; i < priv->num_grps; i++) { | |
1918 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1919 | if (err) { | |
1920 | for (j = 0; j < i; j++) | |
1921 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1922 | goto irq_fail; |
46ceb60c SG |
1923 | } |
1924 | } | |
1925 | ||
7f7f5316 | 1926 | /* Start the controller */ |
ccc05c6e | 1927 | gfar_start(ndev); |
1da177e4 | 1928 | |
826aa4a0 AV |
1929 | phy_start(priv->phydev); |
1930 | ||
46ceb60c SG |
1931 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
1932 | ||
1da177e4 LT |
1933 | return 0; |
1934 | ||
46ceb60c | 1935 | irq_fail: |
e69edd21 | 1936 | free_skb_resources(priv); |
1da177e4 LT |
1937 | return err; |
1938 | } | |
1939 | ||
0977f817 JC |
1940 | /* Called when something needs to use the ethernet device |
1941 | * Returns 0 for success. | |
1942 | */ | |
1da177e4 LT |
1943 | static int gfar_enet_open(struct net_device *dev) |
1944 | { | |
94e8cc35 | 1945 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1946 | int err; |
1947 | ||
46ceb60c | 1948 | enable_napi(priv); |
bea3348e | 1949 | |
1da177e4 LT |
1950 | /* Initialize a bunch of registers */ |
1951 | init_registers(dev); | |
1952 | ||
1953 | gfar_set_mac_address(dev); | |
1954 | ||
1955 | err = init_phy(dev); | |
1956 | ||
a12f801d | 1957 | if (err) { |
46ceb60c | 1958 | disable_napi(priv); |
1da177e4 | 1959 | return err; |
bea3348e | 1960 | } |
1da177e4 LT |
1961 | |
1962 | err = startup_gfar(dev); | |
db0e8e3f | 1963 | if (err) { |
46ceb60c | 1964 | disable_napi(priv); |
db0e8e3f AV |
1965 | return err; |
1966 | } | |
1da177e4 | 1967 | |
fba4ed03 | 1968 | netif_tx_start_all_queues(dev); |
1da177e4 | 1969 | |
2884e5cc AV |
1970 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1971 | ||
1da177e4 LT |
1972 | return err; |
1973 | } | |
1974 | ||
54dc79fe | 1975 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1976 | { |
54dc79fe | 1977 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1978 | |
1979 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1980 | |
0bbaf069 KG |
1981 | return fcb; |
1982 | } | |
1983 | ||
9c4886e5 | 1984 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, |
bc4598bc | 1985 | int fcb_length) |
0bbaf069 | 1986 | { |
0bbaf069 KG |
1987 | /* If we're here, it's a IP packet with a TCP or UDP |
1988 | * payload. We set it to checksum, using a pseudo-header | |
1989 | * we provide | |
1990 | */ | |
3a2e16c8 | 1991 | u8 flags = TXFCB_DEFAULT; |
0bbaf069 | 1992 | |
0977f817 JC |
1993 | /* Tell the controller what the protocol is |
1994 | * And provide the already calculated phcs | |
1995 | */ | |
eddc9ec5 | 1996 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 1997 | flags |= TXFCB_UDP; |
4bedb452 | 1998 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 1999 | } else |
8da32de5 | 2000 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
2001 | |
2002 | /* l3os is the distance between the start of the | |
2003 | * frame (skb->data) and the start of the IP hdr. | |
2004 | * l4os is the distance between the start of the | |
0977f817 JC |
2005 | * l3 hdr and the l4 hdr |
2006 | */ | |
9c4886e5 | 2007 | fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); |
cfe1fc77 | 2008 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 2009 | |
7f7f5316 | 2010 | fcb->flags = flags; |
0bbaf069 KG |
2011 | } |
2012 | ||
7f7f5316 | 2013 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 2014 | { |
7f7f5316 | 2015 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2016 | fcb->vlctl = vlan_tx_tag_get(skb); |
2017 | } | |
2018 | ||
4669bc90 | 2019 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
bc4598bc | 2020 | struct txbd8 *base, int ring_size) |
4669bc90 DH |
2021 | { |
2022 | struct txbd8 *new_bd = bdp + stride; | |
2023 | ||
2024 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2025 | } | |
2026 | ||
2027 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
bc4598bc | 2028 | int ring_size) |
4669bc90 DH |
2029 | { |
2030 | return skip_txbd(bdp, 1, base, ring_size); | |
2031 | } | |
2032 | ||
0977f817 JC |
2033 | /* This is called by the kernel when a frame is ready for transmission. |
2034 | * It is pointed to by the dev->hard_start_xmit function pointer | |
2035 | */ | |
1da177e4 LT |
2036 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2037 | { | |
2038 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2039 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2040 | struct netdev_queue *txq; |
f4983704 | 2041 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2042 | struct txfcb *fcb = NULL; |
f0ee7acf | 2043 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2044 | u32 lstatus; |
f0ee7acf | 2045 | int i, rq = 0, do_tstamp = 0; |
4669bc90 | 2046 | u32 bufaddr; |
fef6108d | 2047 | unsigned long flags; |
9c4886e5 | 2048 | unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN; |
fba4ed03 | 2049 | |
0977f817 | 2050 | /* TOE=1 frames larger than 2500 bytes may see excess delays |
deb90eac AV |
2051 | * before start of transmission. |
2052 | */ | |
2053 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) && | |
bc4598bc JC |
2054 | skb->ip_summed == CHECKSUM_PARTIAL && |
2055 | skb->len > 2500)) { | |
deb90eac AV |
2056 | int ret; |
2057 | ||
2058 | ret = skb_checksum_help(skb); | |
2059 | if (ret) | |
2060 | return ret; | |
2061 | } | |
2062 | ||
fba4ed03 SG |
2063 | rq = skb->queue_mapping; |
2064 | tx_queue = priv->tx_queue[rq]; | |
2065 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2066 | base = tx_queue->tx_bd_base; |
46ceb60c | 2067 | regs = tx_queue->grp->regs; |
f0ee7acf MR |
2068 | |
2069 | /* check if time stamp should be generated */ | |
2244d07b | 2070 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
bc4598bc | 2071 | priv->hwts_tx_en)) { |
f0ee7acf | 2072 | do_tstamp = 1; |
9c4886e5 MR |
2073 | fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
2074 | } | |
4669bc90 | 2075 | |
5b28beaf LY |
2076 | /* make space for additional header when fcb is needed */ |
2077 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
bc4598bc JC |
2078 | vlan_tx_tag_present(skb) || |
2079 | unlikely(do_tstamp)) && | |
2080 | (skb_headroom(skb) < fcb_length)) { | |
54dc79fe SH |
2081 | struct sk_buff *skb_new; |
2082 | ||
9c4886e5 | 2083 | skb_new = skb_realloc_headroom(skb, fcb_length); |
54dc79fe SH |
2084 | if (!skb_new) { |
2085 | dev->stats.tx_errors++; | |
bd14ba84 | 2086 | kfree_skb(skb); |
54dc79fe SH |
2087 | return NETDEV_TX_OK; |
2088 | } | |
db83d136 | 2089 | |
313b037c ED |
2090 | if (skb->sk) |
2091 | skb_set_owner_w(skb_new, skb->sk); | |
2092 | consume_skb(skb); | |
54dc79fe SH |
2093 | skb = skb_new; |
2094 | } | |
2095 | ||
4669bc90 DH |
2096 | /* total number of fragments in the SKB */ |
2097 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2098 | ||
f0ee7acf MR |
2099 | /* calculate the required number of TxBDs for this skb */ |
2100 | if (unlikely(do_tstamp)) | |
2101 | nr_txbds = nr_frags + 2; | |
2102 | else | |
2103 | nr_txbds = nr_frags + 1; | |
2104 | ||
4669bc90 | 2105 | /* check if there is space to queue this packet */ |
f0ee7acf | 2106 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2107 | /* no space, stop the queue */ |
fba4ed03 | 2108 | netif_tx_stop_queue(txq); |
4669bc90 | 2109 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2110 | return NETDEV_TX_BUSY; |
2111 | } | |
1da177e4 LT |
2112 | |
2113 | /* Update transmit stats */ | |
1ac9ad13 ED |
2114 | tx_queue->stats.tx_bytes += skb->len; |
2115 | tx_queue->stats.tx_packets++; | |
1da177e4 | 2116 | |
a12f801d | 2117 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2118 | lstatus = txbdp->lstatus; |
2119 | ||
2120 | /* Time stamp insertion requires one additional TxBD */ | |
2121 | if (unlikely(do_tstamp)) | |
2122 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
bc4598bc | 2123 | tx_queue->tx_ring_size); |
1da177e4 | 2124 | |
4669bc90 | 2125 | if (nr_frags == 0) { |
f0ee7acf MR |
2126 | if (unlikely(do_tstamp)) |
2127 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
bc4598bc | 2128 | TXBD_INTERRUPT); |
f0ee7acf MR |
2129 | else |
2130 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2131 | } else { |
2132 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2133 | for (i = 0; i < nr_frags; i++) { | |
2134 | /* Point at the next BD, wrapping as needed */ | |
a12f801d | 2135 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2136 | |
2137 | length = skb_shinfo(skb)->frags[i].size; | |
2138 | ||
2139 | lstatus = txbdp->lstatus | length | | |
bc4598bc | 2140 | BD_LFLAG(TXBD_READY); |
4669bc90 DH |
2141 | |
2142 | /* Handle the last BD specially */ | |
2143 | if (i == nr_frags - 1) | |
2144 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2145 | |
2234a722 IC |
2146 | bufaddr = skb_frag_dma_map(&priv->ofdev->dev, |
2147 | &skb_shinfo(skb)->frags[i], | |
2148 | 0, | |
2149 | length, | |
2150 | DMA_TO_DEVICE); | |
4669bc90 DH |
2151 | |
2152 | /* set the TxBD length and buffer pointer */ | |
2153 | txbdp->bufPtr = bufaddr; | |
2154 | txbdp->lstatus = lstatus; | |
2155 | } | |
2156 | ||
2157 | lstatus = txbdp_start->lstatus; | |
2158 | } | |
1da177e4 | 2159 | |
9c4886e5 MR |
2160 | /* Add TxPAL between FCB and frame if required */ |
2161 | if (unlikely(do_tstamp)) { | |
2162 | skb_push(skb, GMAC_TXPAL_LEN); | |
2163 | memset(skb->data, 0, GMAC_TXPAL_LEN); | |
2164 | } | |
2165 | ||
0bbaf069 | 2166 | /* Set up checksumming */ |
12dea57b | 2167 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe | 2168 | fcb = gfar_add_fcb(skb); |
4363c2fd | 2169 | /* as specified by errata */ |
bc4598bc JC |
2170 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) && |
2171 | ((unsigned long)fcb % 0x20) > 0x18)) { | |
4363c2fd AD |
2172 | __skb_pull(skb, GMAC_FCB_LEN); |
2173 | skb_checksum_help(skb); | |
2174 | } else { | |
2175 | lstatus |= BD_LFLAG(TXBD_TOE); | |
9c4886e5 | 2176 | gfar_tx_checksum(skb, fcb, fcb_length); |
4363c2fd | 2177 | } |
0bbaf069 KG |
2178 | } |
2179 | ||
eab6d18d | 2180 | if (vlan_tx_tag_present(skb)) { |
54dc79fe SH |
2181 | if (unlikely(NULL == fcb)) { |
2182 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 2183 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 2184 | } |
54dc79fe SH |
2185 | |
2186 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
2187 | } |
2188 | ||
f0ee7acf MR |
2189 | /* Setup tx hardware time stamping if requested */ |
2190 | if (unlikely(do_tstamp)) { | |
2244d07b | 2191 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf MR |
2192 | if (fcb == NULL) |
2193 | fcb = gfar_add_fcb(skb); | |
2194 | fcb->ptp = 1; | |
2195 | lstatus |= BD_LFLAG(TXBD_TOE); | |
2196 | } | |
2197 | ||
4826857f | 2198 | txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
bc4598bc | 2199 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2200 | |
0977f817 | 2201 | /* If time stamping is requested one additional TxBD must be set up. The |
f0ee7acf MR |
2202 | * first TxBD points to the FCB and must have a data length of |
2203 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2204 | * the full frame length. | |
2205 | */ | |
2206 | if (unlikely(do_tstamp)) { | |
9c4886e5 | 2207 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length; |
f0ee7acf | 2208 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | |
bc4598bc | 2209 | (skb_headlen(skb) - fcb_length); |
f0ee7acf MR |
2210 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; |
2211 | } else { | |
2212 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2213 | } | |
1da177e4 | 2214 | |
d8a0f1b0 PG |
2215 | netdev_tx_sent_queue(txq, skb->len); |
2216 | ||
0977f817 | 2217 | /* We can work in parallel with gfar_clean_tx_ring(), except |
a3bc1f11 AV |
2218 | * when modifying num_txbdfree. Note that we didn't grab the lock |
2219 | * when we were reading the num_txbdfree and checking for available | |
2220 | * space, that's because outside of this function it can only grow, | |
2221 | * and once we've got needed space, it cannot suddenly disappear. | |
2222 | * | |
2223 | * The lock also protects us from gfar_error(), which can modify | |
2224 | * regs->tstat and thus retrigger the transfers, which is why we | |
2225 | * also must grab the lock before setting ready bit for the first | |
2226 | * to be transmitted BD. | |
2227 | */ | |
2228 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2229 | ||
0977f817 | 2230 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
3b6330ce SW |
2231 | * semantics (it requires synchronization between cacheable and |
2232 | * uncacheable mappings, which eieio doesn't provide and which we | |
2233 | * don't need), thus requiring a more expensive sync instruction. At | |
2234 | * some point, the set of architecture-independent barrier functions | |
2235 | * should be expanded to include weaker barriers. | |
2236 | */ | |
3b6330ce | 2237 | eieio(); |
7f7f5316 | 2238 | |
4669bc90 DH |
2239 | txbdp_start->lstatus = lstatus; |
2240 | ||
0eddba52 AV |
2241 | eieio(); /* force lstatus write before tx_skbuff */ |
2242 | ||
2243 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2244 | ||
4669bc90 | 2245 | /* Update the current skb pointer to the next entry we will use |
0977f817 JC |
2246 | * (wrapping if necessary) |
2247 | */ | |
a12f801d | 2248 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
bc4598bc | 2249 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); |
4669bc90 | 2250 | |
a12f801d | 2251 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2252 | |
2253 | /* reduce TxBD free count */ | |
f0ee7acf | 2254 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2255 | |
2256 | /* If the next BD still needs to be cleaned up, then the bds | |
0977f817 JC |
2257 | * are full. We need to tell the kernel to stop sending us stuff. |
2258 | */ | |
a12f801d | 2259 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2260 | netif_tx_stop_queue(txq); |
1da177e4 | 2261 | |
09f75cd7 | 2262 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2263 | } |
2264 | ||
1da177e4 | 2265 | /* Tell the DMA to go go go */ |
fba4ed03 | 2266 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2267 | |
2268 | /* Unlock priv */ | |
a12f801d | 2269 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2270 | |
54dc79fe | 2271 | return NETDEV_TX_OK; |
1da177e4 LT |
2272 | } |
2273 | ||
2274 | /* Stops the kernel queue, and halts the controller */ | |
2275 | static int gfar_close(struct net_device *dev) | |
2276 | { | |
2277 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2278 | |
46ceb60c | 2279 | disable_napi(priv); |
bea3348e | 2280 | |
ab939905 | 2281 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2282 | stop_gfar(dev); |
2283 | ||
bb40dcbb AF |
2284 | /* Disconnect from the PHY */ |
2285 | phy_disconnect(priv->phydev); | |
2286 | priv->phydev = NULL; | |
1da177e4 | 2287 | |
fba4ed03 | 2288 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2289 | |
2290 | return 0; | |
2291 | } | |
2292 | ||
1da177e4 | 2293 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2294 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2295 | { |
7f7f5316 | 2296 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2297 | |
2298 | return 0; | |
2299 | } | |
2300 | ||
f3dc1586 SP |
2301 | /* Check if rx parser should be activated */ |
2302 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2303 | { | |
2304 | struct gfar __iomem *regs; | |
2305 | u32 tempval; | |
2306 | ||
2307 | regs = priv->gfargrp[0].regs; | |
2308 | ||
2309 | tempval = gfar_read(®s->rctrl); | |
2310 | /* If parse is no longer required, then disable parser */ | |
2311 | if (tempval & RCTRL_REQ_PARSER) | |
2312 | tempval |= RCTRL_PRSDEP_INIT; | |
2313 | else | |
2314 | tempval &= ~RCTRL_PRSDEP_INIT; | |
2315 | gfar_write(®s->rctrl, tempval); | |
2316 | } | |
2317 | ||
0bbaf069 | 2318 | /* Enables and disables VLAN insertion/extraction */ |
c8f44aff | 2319 | void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) |
0bbaf069 KG |
2320 | { |
2321 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2322 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2323 | unsigned long flags; |
2324 | u32 tempval; | |
2325 | ||
46ceb60c | 2326 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2327 | local_irq_save(flags); |
2328 | lock_rx_qs(priv); | |
0bbaf069 | 2329 | |
87c288c6 | 2330 | if (features & NETIF_F_HW_VLAN_TX) { |
0bbaf069 | 2331 | /* Enable VLAN tag insertion */ |
f4983704 | 2332 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2333 | tempval |= TCTRL_VLINS; |
f4983704 | 2334 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2335 | } else { |
2336 | /* Disable VLAN tag insertion */ | |
f4983704 | 2337 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2338 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2339 | gfar_write(®s->tctrl, tempval); |
87c288c6 | 2340 | } |
0bbaf069 | 2341 | |
87c288c6 JP |
2342 | if (features & NETIF_F_HW_VLAN_RX) { |
2343 | /* Enable VLAN tag extraction */ | |
2344 | tempval = gfar_read(®s->rctrl); | |
2345 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); | |
2346 | gfar_write(®s->rctrl, tempval); | |
2347 | } else { | |
0bbaf069 | 2348 | /* Disable VLAN tag extraction */ |
f4983704 | 2349 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2350 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2351 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2352 | |
2353 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2354 | } |
2355 | ||
77ecaf2d DH |
2356 | gfar_change_mtu(dev, dev->mtu); |
2357 | ||
fba4ed03 SG |
2358 | unlock_rx_qs(priv); |
2359 | local_irq_restore(flags); | |
0bbaf069 KG |
2360 | } |
2361 | ||
1da177e4 LT |
2362 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2363 | { | |
2364 | int tempsize, tempval; | |
2365 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2366 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2367 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2368 | int frame_size = new_mtu + ETH_HLEN; |
2369 | ||
87c288c6 | 2370 | if (gfar_is_vlan_on(priv)) |
faa89577 | 2371 | frame_size += VLAN_HLEN; |
0bbaf069 | 2372 | |
1da177e4 | 2373 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
59deab26 | 2374 | netif_err(priv, drv, dev, "Invalid MTU setting\n"); |
1da177e4 LT |
2375 | return -EINVAL; |
2376 | } | |
2377 | ||
77ecaf2d DH |
2378 | if (gfar_uses_fcb(priv)) |
2379 | frame_size += GMAC_FCB_LEN; | |
2380 | ||
2381 | frame_size += priv->padding; | |
2382 | ||
bc4598bc JC |
2383 | tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + |
2384 | INCREMENTAL_BUFFER_SIZE; | |
1da177e4 LT |
2385 | |
2386 | /* Only stop and start the controller if it isn't already | |
0977f817 JC |
2387 | * stopped, and we changed something |
2388 | */ | |
1da177e4 LT |
2389 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2390 | stop_gfar(dev); | |
2391 | ||
2392 | priv->rx_buffer_size = tempsize; | |
2393 | ||
2394 | dev->mtu = new_mtu; | |
2395 | ||
f4983704 SG |
2396 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2397 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2398 | |
2399 | /* If the mtu is larger than the max size for standard | |
2400 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
0977f817 JC |
2401 | * to allow huge frames, and to check the length |
2402 | */ | |
f4983704 | 2403 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2404 | |
7d350977 | 2405 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
bc4598bc | 2406 | gfar_has_errata(priv, GFAR_ERRATA_74)) |
1da177e4 LT |
2407 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2408 | else | |
2409 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2410 | ||
f4983704 | 2411 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2412 | |
2413 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2414 | startup_gfar(dev); | |
2415 | ||
2416 | return 0; | |
2417 | } | |
2418 | ||
ab939905 | 2419 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2420 | * transmitted after a set amount of time. |
2421 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2422 | * starting over will fix the problem. |
2423 | */ | |
2424 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2425 | { |
ab939905 | 2426 | struct gfar_private *priv = container_of(work, struct gfar_private, |
bc4598bc | 2427 | reset_task); |
4826857f | 2428 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2429 | |
2430 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2431 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2432 | stop_gfar(dev); |
2433 | startup_gfar(dev); | |
fba4ed03 | 2434 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2435 | } |
2436 | ||
263ba320 | 2437 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2438 | } |
2439 | ||
ab939905 SS |
2440 | static void gfar_timeout(struct net_device *dev) |
2441 | { | |
2442 | struct gfar_private *priv = netdev_priv(dev); | |
2443 | ||
2444 | dev->stats.tx_errors++; | |
2445 | schedule_work(&priv->reset_task); | |
2446 | } | |
2447 | ||
acbc0f03 EL |
2448 | static void gfar_align_skb(struct sk_buff *skb) |
2449 | { | |
2450 | /* We need the data buffer to be aligned properly. We will reserve | |
2451 | * as many bytes as needed to align the data properly | |
2452 | */ | |
2453 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
bc4598bc | 2454 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); |
acbc0f03 EL |
2455 | } |
2456 | ||
1da177e4 | 2457 | /* Interrupt Handler for Transmit complete */ |
a12f801d | 2458 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2459 | { |
a12f801d | 2460 | struct net_device *dev = tx_queue->dev; |
d8a0f1b0 | 2461 | struct netdev_queue *txq; |
d080cd63 | 2462 | struct gfar_private *priv = netdev_priv(dev); |
a12f801d | 2463 | struct gfar_priv_rx_q *rx_queue = NULL; |
f0ee7acf | 2464 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2465 | struct txbd8 *lbdp = NULL; |
a12f801d | 2466 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2467 | struct sk_buff *skb; |
2468 | int skb_dirtytx; | |
a12f801d | 2469 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2470 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2471 | int i; |
d080cd63 | 2472 | int howmany = 0; |
d8a0f1b0 PG |
2473 | int tqi = tx_queue->qindex; |
2474 | unsigned int bytes_sent = 0; | |
4669bc90 | 2475 | u32 lstatus; |
f0ee7acf | 2476 | size_t buflen; |
1da177e4 | 2477 | |
d8a0f1b0 PG |
2478 | rx_queue = priv->rx_queue[tqi]; |
2479 | txq = netdev_get_tx_queue(dev, tqi); | |
a12f801d SG |
2480 | bdp = tx_queue->dirty_tx; |
2481 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2482 | |
a12f801d | 2483 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2484 | unsigned long flags; |
2485 | ||
4669bc90 | 2486 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf | 2487 | |
0977f817 | 2488 | /* When time stamping, one additional TxBD must be freed. |
f0ee7acf MR |
2489 | * Also, we need to dma_unmap_single() the TxPAL. |
2490 | */ | |
2244d07b | 2491 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2492 | nr_txbds = frags + 2; |
2493 | else | |
2494 | nr_txbds = frags + 1; | |
2495 | ||
2496 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2497 | |
4669bc90 | 2498 | lstatus = lbdp->lstatus; |
1da177e4 | 2499 | |
4669bc90 DH |
2500 | /* Only clean completed frames */ |
2501 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
bc4598bc | 2502 | (lstatus & BD_LENGTH_MASK)) |
4669bc90 DH |
2503 | break; |
2504 | ||
2244d07b | 2505 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf | 2506 | next = next_txbd(bdp, base, tx_ring_size); |
9c4886e5 | 2507 | buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
f0ee7acf MR |
2508 | } else |
2509 | buflen = bdp->length; | |
2510 | ||
2511 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, | |
bc4598bc | 2512 | buflen, DMA_TO_DEVICE); |
f0ee7acf | 2513 | |
2244d07b | 2514 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2515 | struct skb_shared_hwtstamps shhwtstamps; |
2516 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
bc4598bc | 2517 | |
f0ee7acf MR |
2518 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
2519 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
9c4886e5 | 2520 | skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); |
f0ee7acf MR |
2521 | skb_tstamp_tx(skb, &shhwtstamps); |
2522 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2523 | bdp = next; | |
2524 | } | |
81183059 | 2525 | |
4669bc90 DH |
2526 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2527 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2528 | |
4669bc90 | 2529 | for (i = 0; i < frags; i++) { |
bc4598bc JC |
2530 | dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr, |
2531 | bdp->length, DMA_TO_DEVICE); | |
4669bc90 DH |
2532 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2533 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2534 | } | |
1da177e4 | 2535 | |
d8a0f1b0 PG |
2536 | bytes_sent += skb->len; |
2537 | ||
acb600de | 2538 | dev_kfree_skb_any(skb); |
0fd56bb5 | 2539 | |
a12f801d | 2540 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2541 | |
4669bc90 | 2542 | skb_dirtytx = (skb_dirtytx + 1) & |
bc4598bc | 2543 | TX_RING_MOD_MASK(tx_ring_size); |
4669bc90 DH |
2544 | |
2545 | howmany++; | |
a3bc1f11 | 2546 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2547 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2548 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2549 | } |
1da177e4 | 2550 | |
4669bc90 | 2551 | /* If we freed a buffer, we can restart transmission, if necessary */ |
5407b14c | 2552 | if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) |
d8a0f1b0 | 2553 | netif_wake_subqueue(dev, tqi); |
1da177e4 | 2554 | |
4669bc90 | 2555 | /* Update dirty indicators */ |
a12f801d SG |
2556 | tx_queue->skb_dirtytx = skb_dirtytx; |
2557 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2558 | |
d8a0f1b0 PG |
2559 | netdev_tx_completed_queue(txq, howmany, bytes_sent); |
2560 | ||
d080cd63 DH |
2561 | return howmany; |
2562 | } | |
2563 | ||
f4983704 | 2564 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2565 | { |
a6d0b91a AV |
2566 | unsigned long flags; |
2567 | ||
fba4ed03 SG |
2568 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2569 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2570 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2571 | __napi_schedule(&gfargrp->napi); |
8707bdd4 | 2572 | } else { |
0977f817 | 2573 | /* Clear IEVENT, so interrupts aren't called again |
8707bdd4 JP |
2574 | * because of the packets that have already arrived. |
2575 | */ | |
f4983704 | 2576 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2577 | } |
fba4ed03 | 2578 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2579 | |
8c7396ae | 2580 | } |
1da177e4 | 2581 | |
8c7396ae | 2582 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2583 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2584 | { |
f4983704 | 2585 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2586 | return IRQ_HANDLED; |
2587 | } | |
2588 | ||
a12f801d | 2589 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 2590 | struct sk_buff *skb) |
815b97c6 | 2591 | { |
a12f801d | 2592 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2593 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2594 | dma_addr_t buf; |
815b97c6 | 2595 | |
8a102fe0 AV |
2596 | buf = dma_map_single(&priv->ofdev->dev, skb->data, |
2597 | priv->rx_buffer_size, DMA_FROM_DEVICE); | |
a12f801d | 2598 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2599 | } |
2600 | ||
2281a0f3 | 2601 | static struct sk_buff *gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2602 | { |
2603 | struct gfar_private *priv = netdev_priv(dev); | |
acb600de | 2604 | struct sk_buff *skb; |
1da177e4 | 2605 | |
acbc0f03 | 2606 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2607 | if (!skb) |
1da177e4 LT |
2608 | return NULL; |
2609 | ||
acbc0f03 | 2610 | gfar_align_skb(skb); |
7f7f5316 | 2611 | |
acbc0f03 EL |
2612 | return skb; |
2613 | } | |
2614 | ||
2281a0f3 | 2615 | struct sk_buff *gfar_new_skb(struct net_device *dev) |
acbc0f03 | 2616 | { |
acb600de | 2617 | return gfar_alloc_skb(dev); |
1da177e4 LT |
2618 | } |
2619 | ||
298e1a9e | 2620 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2621 | { |
298e1a9e | 2622 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2623 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2624 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2625 | ||
0977f817 | 2626 | /* If the packet was truncated, none of the other errors matter */ |
1da177e4 LT |
2627 | if (status & RXBD_TRUNCATED) { |
2628 | stats->rx_length_errors++; | |
2629 | ||
2630 | estats->rx_trunc++; | |
2631 | ||
2632 | return; | |
2633 | } | |
2634 | /* Count the errors, if there were any */ | |
2635 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2636 | stats->rx_length_errors++; | |
2637 | ||
2638 | if (status & RXBD_LARGE) | |
2639 | estats->rx_large++; | |
2640 | else | |
2641 | estats->rx_short++; | |
2642 | } | |
2643 | if (status & RXBD_NONOCTET) { | |
2644 | stats->rx_frame_errors++; | |
2645 | estats->rx_nonoctet++; | |
2646 | } | |
2647 | if (status & RXBD_CRCERR) { | |
2648 | estats->rx_crcerr++; | |
2649 | stats->rx_crc_errors++; | |
2650 | } | |
2651 | if (status & RXBD_OVERRUN) { | |
2652 | estats->rx_overrun++; | |
2653 | stats->rx_crc_errors++; | |
2654 | } | |
2655 | } | |
2656 | ||
f4983704 | 2657 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2658 | { |
f4983704 | 2659 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2660 | return IRQ_HANDLED; |
2661 | } | |
2662 | ||
0bbaf069 KG |
2663 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2664 | { | |
2665 | /* If valid headers were found, and valid sums | |
2666 | * were verified, then we tell the kernel that no | |
0977f817 JC |
2667 | * checksumming is necessary. Otherwise, it is [FIXME] |
2668 | */ | |
7f7f5316 | 2669 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2670 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2671 | else | |
bc8acf2c | 2672 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2673 | } |
2674 | ||
2675 | ||
0977f817 | 2676 | /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ |
1da177e4 | 2677 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
cd754a57 | 2678 | int amount_pull, struct napi_struct *napi) |
1da177e4 LT |
2679 | { |
2680 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2681 | struct rxfcb *fcb = NULL; |
1da177e4 | 2682 | |
cd754a57 | 2683 | gro_result_t ret; |
1da177e4 | 2684 | |
2c2db48a DH |
2685 | /* fcb is at the beginning if exists */ |
2686 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2687 | |
0977f817 JC |
2688 | /* Remove the FCB from the skb |
2689 | * Remove the padded bytes, if there are any | |
2690 | */ | |
f74dac08 SG |
2691 | if (amount_pull) { |
2692 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2693 | skb_pull(skb, amount_pull); |
f74dac08 | 2694 | } |
0bbaf069 | 2695 | |
cc772ab7 MR |
2696 | /* Get receive timestamp from the skb */ |
2697 | if (priv->hwts_rx_en) { | |
2698 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2699 | u64 *ns = (u64 *) skb->data; | |
bc4598bc | 2700 | |
cc772ab7 MR |
2701 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2702 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2703 | } | |
2704 | ||
2705 | if (priv->padding) | |
2706 | skb_pull(skb, priv->padding); | |
2707 | ||
8b3afe95 | 2708 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2709 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2710 | |
2c2db48a DH |
2711 | /* Tell the skb what kind of packet this is */ |
2712 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2713 | |
0977f817 | 2714 | /* There's need to check for NETIF_F_HW_VLAN_RX here. |
32f7fd44 JP |
2715 | * Even if vlan rx accel is disabled, on some chips |
2716 | * RXFCB_VLN is pseudo randomly set. | |
2717 | */ | |
2718 | if (dev->features & NETIF_F_HW_VLAN_RX && | |
2719 | fcb->flags & RXFCB_VLN) | |
87c288c6 JP |
2720 | __vlan_hwaccel_put_tag(skb, fcb->vlctl); |
2721 | ||
2c2db48a | 2722 | /* Send the packet up the stack */ |
cd754a57 | 2723 | ret = napi_gro_receive(napi, skb); |
0bbaf069 | 2724 | |
cd754a57 | 2725 | if (GRO_DROP == ret) |
2c2db48a | 2726 | priv->extra_stats.kernel_dropped++; |
1da177e4 LT |
2727 | |
2728 | return 0; | |
2729 | } | |
2730 | ||
2731 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
2281a0f3 JC |
2732 | * until the budget/quota has been reached. Returns the number |
2733 | * of frames handled | |
1da177e4 | 2734 | */ |
a12f801d | 2735 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2736 | { |
a12f801d | 2737 | struct net_device *dev = rx_queue->dev; |
31de198b | 2738 | struct rxbd8 *bdp, *base; |
1da177e4 | 2739 | struct sk_buff *skb; |
2c2db48a DH |
2740 | int pkt_len; |
2741 | int amount_pull; | |
1da177e4 LT |
2742 | int howmany = 0; |
2743 | struct gfar_private *priv = netdev_priv(dev); | |
2744 | ||
2745 | /* Get the first full descriptor */ | |
a12f801d SG |
2746 | bdp = rx_queue->cur_rx; |
2747 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2748 | |
cc772ab7 | 2749 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0); |
2c2db48a | 2750 | |
1da177e4 | 2751 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2752 | struct sk_buff *newskb; |
bc4598bc | 2753 | |
3b6330ce | 2754 | rmb(); |
815b97c6 AF |
2755 | |
2756 | /* Add another skb for the future */ | |
2757 | newskb = gfar_new_skb(dev); | |
2758 | ||
a12f801d | 2759 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2760 | |
4826857f | 2761 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, |
bc4598bc | 2762 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
81183059 | 2763 | |
63b88b90 | 2764 | if (unlikely(!(bdp->status & RXBD_ERR) && |
bc4598bc | 2765 | bdp->length > priv->rx_buffer_size)) |
63b88b90 AV |
2766 | bdp->status = RXBD_LARGE; |
2767 | ||
815b97c6 AF |
2768 | /* We drop the frame if we failed to allocate a new buffer */ |
2769 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
bc4598bc | 2770 | bdp->status & RXBD_ERR)) { |
815b97c6 AF |
2771 | count_errors(bdp->status, dev); |
2772 | ||
2773 | if (unlikely(!newskb)) | |
2774 | newskb = skb; | |
acbc0f03 | 2775 | else if (skb) |
acb600de | 2776 | dev_kfree_skb(skb); |
815b97c6 | 2777 | } else { |
1da177e4 | 2778 | /* Increment the number of packets */ |
a7f38041 | 2779 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2780 | howmany++; |
2781 | ||
2c2db48a DH |
2782 | if (likely(skb)) { |
2783 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2784 | /* Remove the FCS from the packet length */ | |
2785 | skb_put(skb, pkt_len); | |
a7f38041 | 2786 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2787 | skb_record_rx_queue(skb, rx_queue->qindex); |
cd754a57 | 2788 | gfar_process_frame(dev, skb, amount_pull, |
bc4598bc | 2789 | &rx_queue->grp->napi); |
2c2db48a DH |
2790 | |
2791 | } else { | |
59deab26 | 2792 | netif_warn(priv, rx_err, dev, "Missing skb!\n"); |
a7f38041 | 2793 | rx_queue->stats.rx_dropped++; |
2c2db48a DH |
2794 | priv->extra_stats.rx_skbmissing++; |
2795 | } | |
1da177e4 | 2796 | |
1da177e4 LT |
2797 | } |
2798 | ||
a12f801d | 2799 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2800 | |
815b97c6 | 2801 | /* Setup the new bdp */ |
a12f801d | 2802 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2803 | |
2804 | /* Update to the next pointer */ | |
a12f801d | 2805 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2806 | |
2807 | /* update to point at the next skb */ | |
bc4598bc JC |
2808 | rx_queue->skb_currx = (rx_queue->skb_currx + 1) & |
2809 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2810 | } |
2811 | ||
2812 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2813 | rx_queue->cur_rx = bdp; |
1da177e4 | 2814 | |
1da177e4 LT |
2815 | return howmany; |
2816 | } | |
2817 | ||
bea3348e | 2818 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2819 | { |
bc4598bc JC |
2820 | struct gfar_priv_grp *gfargrp = |
2821 | container_of(napi, struct gfar_priv_grp, napi); | |
fba4ed03 | 2822 | struct gfar_private *priv = gfargrp->priv; |
46ceb60c | 2823 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2824 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 SG |
2825 | struct gfar_priv_rx_q *rx_queue = NULL; |
2826 | int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0; | |
18294ad1 AV |
2827 | int tx_cleaned = 0, i, left_over_budget = budget; |
2828 | unsigned long serviced_queues = 0; | |
fba4ed03 | 2829 | int num_queues = 0; |
d080cd63 | 2830 | |
fba4ed03 SG |
2831 | num_queues = gfargrp->num_rx_queues; |
2832 | budget_per_queue = budget/num_queues; | |
2833 | ||
8c7396ae | 2834 | /* Clear IEVENT, so interrupts aren't called again |
0977f817 JC |
2835 | * because of the packets that have already arrived |
2836 | */ | |
f4983704 | 2837 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2838 | |
fba4ed03 | 2839 | while (num_queues && left_over_budget) { |
fba4ed03 SG |
2840 | budget_per_queue = left_over_budget/num_queues; |
2841 | left_over_budget = 0; | |
2842 | ||
984b3f57 | 2843 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
fba4ed03 SG |
2844 | if (test_bit(i, &serviced_queues)) |
2845 | continue; | |
2846 | rx_queue = priv->rx_queue[i]; | |
2847 | tx_queue = priv->tx_queue[rx_queue->qindex]; | |
2848 | ||
a3bc1f11 | 2849 | tx_cleaned += gfar_clean_tx_ring(tx_queue); |
bc4598bc JC |
2850 | rx_cleaned_per_queue = |
2851 | gfar_clean_rx_ring(rx_queue, budget_per_queue); | |
fba4ed03 | 2852 | rx_cleaned += rx_cleaned_per_queue; |
bc4598bc | 2853 | if (rx_cleaned_per_queue < budget_per_queue) { |
fba4ed03 | 2854 | left_over_budget = left_over_budget + |
bc4598bc JC |
2855 | (budget_per_queue - |
2856 | rx_cleaned_per_queue); | |
fba4ed03 SG |
2857 | set_bit(i, &serviced_queues); |
2858 | num_queues--; | |
2859 | } | |
2860 | } | |
2861 | } | |
1da177e4 | 2862 | |
42199884 AF |
2863 | if (tx_cleaned) |
2864 | return budget; | |
2865 | ||
2866 | if (rx_cleaned < budget) { | |
288379f0 | 2867 | napi_complete(napi); |
1da177e4 LT |
2868 | |
2869 | /* Clear the halt bit in RSTAT */ | |
fba4ed03 | 2870 | gfar_write(®s->rstat, gfargrp->rstat); |
1da177e4 | 2871 | |
f4983704 | 2872 | gfar_write(®s->imask, IMASK_DEFAULT); |
1da177e4 | 2873 | |
0977f817 JC |
2874 | /* If we are coalescing interrupts, update the timer |
2875 | * Otherwise, clear it | |
2876 | */ | |
bc4598bc JC |
2877 | gfar_configure_coalescing(priv, gfargrp->rx_bit_map, |
2878 | gfargrp->tx_bit_map); | |
1da177e4 LT |
2879 | } |
2880 | ||
42199884 | 2881 | return rx_cleaned; |
1da177e4 | 2882 | } |
1da177e4 | 2883 | |
f2d71c2d | 2884 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0977f817 | 2885 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
f2d71c2d VW |
2886 | * without having to re-enable interrupts. It's not called while |
2887 | * the interrupt routine is executing. | |
2888 | */ | |
2889 | static void gfar_netpoll(struct net_device *dev) | |
2890 | { | |
2891 | struct gfar_private *priv = netdev_priv(dev); | |
3a2e16c8 | 2892 | int i; |
f2d71c2d VW |
2893 | |
2894 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2895 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
2896 | for (i = 0; i < priv->num_grps; i++) { |
2897 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2898 | disable_irq(priv->gfargrp[i].interruptReceive); | |
2899 | disable_irq(priv->gfargrp[i].interruptError); | |
2900 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 2901 | &priv->gfargrp[i]); |
46ceb60c SG |
2902 | enable_irq(priv->gfargrp[i].interruptError); |
2903 | enable_irq(priv->gfargrp[i].interruptReceive); | |
2904 | enable_irq(priv->gfargrp[i].interruptTransmit); | |
2905 | } | |
f2d71c2d | 2906 | } else { |
46ceb60c SG |
2907 | for (i = 0; i < priv->num_grps; i++) { |
2908 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2909 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
bc4598bc | 2910 | &priv->gfargrp[i]); |
46ceb60c | 2911 | enable_irq(priv->gfargrp[i].interruptTransmit); |
43de004b | 2912 | } |
f2d71c2d VW |
2913 | } |
2914 | } | |
2915 | #endif | |
2916 | ||
1da177e4 | 2917 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 2918 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 2919 | { |
f4983704 | 2920 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
2921 | |
2922 | /* Save ievent for future reference */ | |
f4983704 | 2923 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 2924 | |
1da177e4 | 2925 | /* Check for reception */ |
538cc7ee | 2926 | if (events & IEVENT_RX_MASK) |
f4983704 | 2927 | gfar_receive(irq, grp_id); |
1da177e4 LT |
2928 | |
2929 | /* Check for transmit completion */ | |
538cc7ee | 2930 | if (events & IEVENT_TX_MASK) |
f4983704 | 2931 | gfar_transmit(irq, grp_id); |
1da177e4 | 2932 | |
538cc7ee SS |
2933 | /* Check for errors */ |
2934 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 2935 | gfar_error(irq, grp_id); |
1da177e4 LT |
2936 | |
2937 | return IRQ_HANDLED; | |
2938 | } | |
2939 | ||
1da177e4 LT |
2940 | /* Called every time the controller might need to be made |
2941 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2942 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2943 | * function converts those variables into the appropriate |
2944 | * register values, and can bring down the device if needed. | |
2945 | */ | |
2946 | static void adjust_link(struct net_device *dev) | |
2947 | { | |
2948 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2949 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
2950 | unsigned long flags; |
2951 | struct phy_device *phydev = priv->phydev; | |
2952 | int new_state = 0; | |
2953 | ||
fba4ed03 SG |
2954 | local_irq_save(flags); |
2955 | lock_tx_qs(priv); | |
2956 | ||
bb40dcbb AF |
2957 | if (phydev->link) { |
2958 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2959 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2960 | |
1da177e4 | 2961 | /* Now we make sure that we can be in full duplex mode. |
0977f817 JC |
2962 | * If not, we operate in half-duplex mode. |
2963 | */ | |
bb40dcbb AF |
2964 | if (phydev->duplex != priv->oldduplex) { |
2965 | new_state = 1; | |
2966 | if (!(phydev->duplex)) | |
1da177e4 | 2967 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2968 | else |
1da177e4 | 2969 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2970 | |
bb40dcbb | 2971 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2972 | } |
2973 | ||
bb40dcbb AF |
2974 | if (phydev->speed != priv->oldspeed) { |
2975 | new_state = 1; | |
2976 | switch (phydev->speed) { | |
1da177e4 | 2977 | case 1000: |
1da177e4 LT |
2978 | tempval = |
2979 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2980 | |
2981 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2982 | break; |
2983 | case 100: | |
2984 | case 10: | |
1da177e4 LT |
2985 | tempval = |
2986 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2987 | |
2988 | /* Reduced mode distinguishes | |
0977f817 JC |
2989 | * between 10 and 100 |
2990 | */ | |
7f7f5316 AF |
2991 | if (phydev->speed == SPEED_100) |
2992 | ecntrl |= ECNTRL_R100; | |
2993 | else | |
2994 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2995 | break; |
2996 | default: | |
59deab26 JP |
2997 | netif_warn(priv, link, dev, |
2998 | "Ack! Speed (%d) is not 10/100/1000!\n", | |
2999 | phydev->speed); | |
1da177e4 LT |
3000 | break; |
3001 | } | |
3002 | ||
bb40dcbb | 3003 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3004 | } |
3005 | ||
bb40dcbb | 3006 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3007 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3008 | |
1da177e4 | 3009 | if (!priv->oldlink) { |
bb40dcbb | 3010 | new_state = 1; |
1da177e4 | 3011 | priv->oldlink = 1; |
1da177e4 | 3012 | } |
bb40dcbb AF |
3013 | } else if (priv->oldlink) { |
3014 | new_state = 1; | |
3015 | priv->oldlink = 0; | |
3016 | priv->oldspeed = 0; | |
3017 | priv->oldduplex = -1; | |
1da177e4 | 3018 | } |
1da177e4 | 3019 | |
bb40dcbb AF |
3020 | if (new_state && netif_msg_link(priv)) |
3021 | phy_print_status(phydev); | |
fba4ed03 SG |
3022 | unlock_tx_qs(priv); |
3023 | local_irq_restore(flags); | |
bb40dcbb | 3024 | } |
1da177e4 LT |
3025 | |
3026 | /* Update the hash table based on the current list of multicast | |
3027 | * addresses we subscribe to. Also, change the promiscuity of | |
3028 | * the device based on the flags (this function is called | |
0977f817 JC |
3029 | * whenever dev->flags is changed |
3030 | */ | |
1da177e4 LT |
3031 | static void gfar_set_multi(struct net_device *dev) |
3032 | { | |
22bedad3 | 3033 | struct netdev_hw_addr *ha; |
1da177e4 | 3034 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3035 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3036 | u32 tempval; |
3037 | ||
a12f801d | 3038 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3039 | /* Set RCTRL to PROM */ |
3040 | tempval = gfar_read(®s->rctrl); | |
3041 | tempval |= RCTRL_PROM; | |
3042 | gfar_write(®s->rctrl, tempval); | |
3043 | } else { | |
3044 | /* Set RCTRL to not PROM */ | |
3045 | tempval = gfar_read(®s->rctrl); | |
3046 | tempval &= ~(RCTRL_PROM); | |
3047 | gfar_write(®s->rctrl, tempval); | |
3048 | } | |
6aa20a22 | 3049 | |
a12f801d | 3050 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3051 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3052 | gfar_write(®s->igaddr0, 0xffffffff); |
3053 | gfar_write(®s->igaddr1, 0xffffffff); | |
3054 | gfar_write(®s->igaddr2, 0xffffffff); | |
3055 | gfar_write(®s->igaddr3, 0xffffffff); | |
3056 | gfar_write(®s->igaddr4, 0xffffffff); | |
3057 | gfar_write(®s->igaddr5, 0xffffffff); | |
3058 | gfar_write(®s->igaddr6, 0xffffffff); | |
3059 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3060 | gfar_write(®s->gaddr0, 0xffffffff); |
3061 | gfar_write(®s->gaddr1, 0xffffffff); | |
3062 | gfar_write(®s->gaddr2, 0xffffffff); | |
3063 | gfar_write(®s->gaddr3, 0xffffffff); | |
3064 | gfar_write(®s->gaddr4, 0xffffffff); | |
3065 | gfar_write(®s->gaddr5, 0xffffffff); | |
3066 | gfar_write(®s->gaddr6, 0xffffffff); | |
3067 | gfar_write(®s->gaddr7, 0xffffffff); | |
3068 | } else { | |
7f7f5316 AF |
3069 | int em_num; |
3070 | int idx; | |
3071 | ||
1da177e4 | 3072 | /* zero out the hash */ |
0bbaf069 KG |
3073 | gfar_write(®s->igaddr0, 0x0); |
3074 | gfar_write(®s->igaddr1, 0x0); | |
3075 | gfar_write(®s->igaddr2, 0x0); | |
3076 | gfar_write(®s->igaddr3, 0x0); | |
3077 | gfar_write(®s->igaddr4, 0x0); | |
3078 | gfar_write(®s->igaddr5, 0x0); | |
3079 | gfar_write(®s->igaddr6, 0x0); | |
3080 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3081 | gfar_write(®s->gaddr0, 0x0); |
3082 | gfar_write(®s->gaddr1, 0x0); | |
3083 | gfar_write(®s->gaddr2, 0x0); | |
3084 | gfar_write(®s->gaddr3, 0x0); | |
3085 | gfar_write(®s->gaddr4, 0x0); | |
3086 | gfar_write(®s->gaddr5, 0x0); | |
3087 | gfar_write(®s->gaddr6, 0x0); | |
3088 | gfar_write(®s->gaddr7, 0x0); | |
3089 | ||
7f7f5316 AF |
3090 | /* If we have extended hash tables, we need to |
3091 | * clear the exact match registers to prepare for | |
0977f817 JC |
3092 | * setting them |
3093 | */ | |
7f7f5316 AF |
3094 | if (priv->extended_hash) { |
3095 | em_num = GFAR_EM_NUM + 1; | |
3096 | gfar_clear_exact_match(dev); | |
3097 | idx = 1; | |
3098 | } else { | |
3099 | idx = 0; | |
3100 | em_num = 0; | |
3101 | } | |
3102 | ||
4cd24eaf | 3103 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3104 | return; |
3105 | ||
3106 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3107 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3108 | if (idx < em_num) { |
22bedad3 | 3109 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3110 | idx++; |
3111 | } else | |
22bedad3 | 3112 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3113 | } |
3114 | } | |
1da177e4 LT |
3115 | } |
3116 | ||
7f7f5316 AF |
3117 | |
3118 | /* Clears each of the exact match registers to zero, so they | |
0977f817 JC |
3119 | * don't interfere with normal reception |
3120 | */ | |
7f7f5316 AF |
3121 | static void gfar_clear_exact_match(struct net_device *dev) |
3122 | { | |
3123 | int idx; | |
6a3c910c | 3124 | static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 | 3125 | |
bc4598bc | 3126 | for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) |
b6bc7650 | 3127 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3128 | } |
3129 | ||
1da177e4 LT |
3130 | /* Set the appropriate hash bit for the given addr */ |
3131 | /* The algorithm works like so: | |
3132 | * 1) Take the Destination Address (ie the multicast address), and | |
3133 | * do a CRC on it (little endian), and reverse the bits of the | |
3134 | * result. | |
3135 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3136 | * table. The table is controlled through 8 32-bit registers: | |
3137 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3138 | * gaddr7. This means that the 3 most significant bits in the | |
3139 | * hash index which gaddr register to use, and the 5 other bits | |
3140 | * indicate which bit (assuming an IBM numbering scheme, which | |
3141 | * for PowerPC (tm) is usually the case) in the register holds | |
0977f817 JC |
3142 | * the entry. |
3143 | */ | |
1da177e4 LT |
3144 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) |
3145 | { | |
3146 | u32 tempval; | |
3147 | struct gfar_private *priv = netdev_priv(dev); | |
6a3c910c | 3148 | u32 result = ether_crc(ETH_ALEN, addr); |
0bbaf069 KG |
3149 | int width = priv->hash_width; |
3150 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3151 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3152 | u32 value = (1 << (31-whichbit)); |
3153 | ||
0bbaf069 | 3154 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3155 | tempval |= value; |
0bbaf069 | 3156 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3157 | } |
3158 | ||
7f7f5316 AF |
3159 | |
3160 | /* There are multiple MAC Address register pairs on some controllers | |
3161 | * This function sets the numth pair to a given address | |
3162 | */ | |
b6bc7650 JP |
3163 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3164 | const u8 *addr) | |
7f7f5316 AF |
3165 | { |
3166 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3167 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 | 3168 | int idx; |
6a3c910c | 3169 | char tmpbuf[ETH_ALEN]; |
7f7f5316 | 3170 | u32 tempval; |
f4983704 | 3171 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3172 | |
3173 | macptr += num*2; | |
3174 | ||
0977f817 JC |
3175 | /* Now copy it into the mac registers backwards, cuz |
3176 | * little endian is silly | |
3177 | */ | |
6a3c910c JP |
3178 | for (idx = 0; idx < ETH_ALEN; idx++) |
3179 | tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; | |
7f7f5316 AF |
3180 | |
3181 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3182 | ||
3183 | tempval = *((u32 *) (tmpbuf + 4)); | |
3184 | ||
3185 | gfar_write(macptr+1, tempval); | |
3186 | } | |
3187 | ||
1da177e4 | 3188 | /* GFAR error interrupt handler */ |
f4983704 | 3189 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3190 | { |
f4983704 SG |
3191 | struct gfar_priv_grp *gfargrp = grp_id; |
3192 | struct gfar __iomem *regs = gfargrp->regs; | |
3193 | struct gfar_private *priv= gfargrp->priv; | |
3194 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3195 | |
3196 | /* Save ievent for future reference */ | |
f4983704 | 3197 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3198 | |
3199 | /* Clear IEVENT */ | |
f4983704 | 3200 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3201 | |
3202 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3203 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3204 | (events & IEVENT_MAG)) |
3205 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3206 | |
3207 | /* Hmm... */ | |
0bbaf069 | 3208 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
bc4598bc JC |
3209 | netdev_dbg(dev, |
3210 | "error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
59deab26 | 3211 | events, gfar_read(®s->imask)); |
1da177e4 LT |
3212 | |
3213 | /* Update the error counters */ | |
3214 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3215 | dev->stats.tx_errors++; |
1da177e4 LT |
3216 | |
3217 | if (events & IEVENT_LC) | |
09f75cd7 | 3218 | dev->stats.tx_window_errors++; |
1da177e4 | 3219 | if (events & IEVENT_CRL) |
09f75cd7 | 3220 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3221 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3222 | unsigned long flags; |
3223 | ||
59deab26 JP |
3224 | netif_dbg(priv, tx_err, dev, |
3225 | "TX FIFO underrun, packet dropped\n"); | |
09f75cd7 | 3226 | dev->stats.tx_dropped++; |
1da177e4 LT |
3227 | priv->extra_stats.tx_underrun++; |
3228 | ||
836cf7fa AV |
3229 | local_irq_save(flags); |
3230 | lock_tx_qs(priv); | |
3231 | ||
1da177e4 | 3232 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3233 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3234 | |
3235 | unlock_tx_qs(priv); | |
3236 | local_irq_restore(flags); | |
1da177e4 | 3237 | } |
59deab26 | 3238 | netif_dbg(priv, tx_err, dev, "Transmit Error\n"); |
1da177e4 LT |
3239 | } |
3240 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3241 | dev->stats.rx_errors++; |
1da177e4 LT |
3242 | priv->extra_stats.rx_bsy++; |
3243 | ||
f4983704 | 3244 | gfar_receive(irq, grp_id); |
1da177e4 | 3245 | |
59deab26 JP |
3246 | netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", |
3247 | gfar_read(®s->rstat)); | |
1da177e4 LT |
3248 | } |
3249 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3250 | dev->stats.rx_errors++; |
1da177e4 LT |
3251 | priv->extra_stats.rx_babr++; |
3252 | ||
59deab26 | 3253 | netif_dbg(priv, rx_err, dev, "babbling RX error\n"); |
1da177e4 LT |
3254 | } |
3255 | if (events & IEVENT_EBERR) { | |
3256 | priv->extra_stats.eberr++; | |
59deab26 | 3257 | netif_dbg(priv, rx_err, dev, "bus error\n"); |
1da177e4 | 3258 | } |
59deab26 JP |
3259 | if (events & IEVENT_RXC) |
3260 | netif_dbg(priv, rx_status, dev, "control frame\n"); | |
1da177e4 LT |
3261 | |
3262 | if (events & IEVENT_BABT) { | |
3263 | priv->extra_stats.tx_babt++; | |
59deab26 | 3264 | netif_dbg(priv, tx_err, dev, "babbling TX error\n"); |
1da177e4 LT |
3265 | } |
3266 | return IRQ_HANDLED; | |
3267 | } | |
3268 | ||
b31a1d8b AF |
3269 | static struct of_device_id gfar_match[] = |
3270 | { | |
3271 | { | |
3272 | .type = "network", | |
3273 | .compatible = "gianfar", | |
3274 | }, | |
46ceb60c SG |
3275 | { |
3276 | .compatible = "fsl,etsec2", | |
3277 | }, | |
b31a1d8b AF |
3278 | {}, |
3279 | }; | |
e72701ac | 3280 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3281 | |
1da177e4 | 3282 | /* Structure for a device driver */ |
74888760 | 3283 | static struct platform_driver gfar_driver = { |
4018294b GL |
3284 | .driver = { |
3285 | .name = "fsl-gianfar", | |
3286 | .owner = THIS_MODULE, | |
3287 | .pm = GFAR_PM_OPS, | |
3288 | .of_match_table = gfar_match, | |
3289 | }, | |
1da177e4 LT |
3290 | .probe = gfar_probe, |
3291 | .remove = gfar_remove, | |
3292 | }; | |
3293 | ||
db62f684 | 3294 | module_platform_driver(gfar_driver); |