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Commit | Line | Data |
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0977f817 | 1 | /* drivers/net/ethernet/freescale/gianfar.c |
1da177e4 LT |
2 | * |
3 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
4 | * This driver is designed for the non-CPM ethernet controllers |
5 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
6 | * Based on 8260_io/fcc_enet.c |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
a12f801d | 10 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 11 | * |
20862788 | 12 | * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. |
a12f801d | 13 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
59deab26 JP |
64 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
65 | #define DEBUG | |
66 | ||
1da177e4 | 67 | #include <linux/kernel.h> |
1da177e4 LT |
68 | #include <linux/string.h> |
69 | #include <linux/errno.h> | |
bb40dcbb | 70 | #include <linux/unistd.h> |
1da177e4 LT |
71 | #include <linux/slab.h> |
72 | #include <linux/interrupt.h> | |
1da177e4 LT |
73 | #include <linux/delay.h> |
74 | #include <linux/netdevice.h> | |
75 | #include <linux/etherdevice.h> | |
76 | #include <linux/skbuff.h> | |
0bbaf069 | 77 | #include <linux/if_vlan.h> |
1da177e4 LT |
78 | #include <linux/spinlock.h> |
79 | #include <linux/mm.h> | |
5af50730 RH |
80 | #include <linux/of_address.h> |
81 | #include <linux/of_irq.h> | |
fe192a49 | 82 | #include <linux/of_mdio.h> |
b31a1d8b | 83 | #include <linux/of_platform.h> |
0bbaf069 KG |
84 | #include <linux/ip.h> |
85 | #include <linux/tcp.h> | |
86 | #include <linux/udp.h> | |
9c07b884 | 87 | #include <linux/in.h> |
cc772ab7 | 88 | #include <linux/net_tstamp.h> |
1da177e4 LT |
89 | |
90 | #include <asm/io.h> | |
7d350977 | 91 | #include <asm/reg.h> |
2969b1f7 | 92 | #include <asm/mpc85xx.h> |
1da177e4 LT |
93 | #include <asm/irq.h> |
94 | #include <asm/uaccess.h> | |
95 | #include <linux/module.h> | |
1da177e4 LT |
96 | #include <linux/dma-mapping.h> |
97 | #include <linux/crc32.h> | |
bb40dcbb AF |
98 | #include <linux/mii.h> |
99 | #include <linux/phy.h> | |
b31a1d8b AF |
100 | #include <linux/phy_fixed.h> |
101 | #include <linux/of.h> | |
4b6ba8aa | 102 | #include <linux/of_net.h> |
1da177e4 LT |
103 | |
104 | #include "gianfar.h" | |
1da177e4 LT |
105 | |
106 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 | 107 | |
7f7f5316 | 108 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 109 | |
1da177e4 LT |
110 | static int gfar_enet_open(struct net_device *dev); |
111 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 112 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
113 | static void gfar_timeout(struct net_device *dev); |
114 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 115 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 116 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 117 | struct sk_buff *skb); |
1da177e4 LT |
118 | static int gfar_set_mac_address(struct net_device *dev); |
119 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
120 | static irqreturn_t gfar_error(int irq, void *dev_id); |
121 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
122 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
123 | static void adjust_link(struct net_device *dev); |
124 | static void init_registers(struct net_device *dev); | |
125 | static int init_phy(struct net_device *dev); | |
74888760 | 126 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 127 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 128 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
129 | static void gfar_set_multi(struct net_device *dev); |
130 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 131 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 132 | static int gfar_poll(struct napi_struct *napi, int budget); |
5eaedf31 | 133 | static int gfar_poll_sq(struct napi_struct *napi, int budget); |
f2d71c2d VW |
134 | #ifdef CONFIG_NET_POLL_CONTROLLER |
135 | static void gfar_netpoll(struct net_device *dev); | |
136 | #endif | |
a12f801d | 137 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
c233cf40 | 138 | static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); |
61db26c6 CM |
139 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
140 | int amount_pull, struct napi_struct *napi); | |
7f7f5316 | 141 | void gfar_halt(struct net_device *dev); |
d87eb127 | 142 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
143 | void gfar_start(struct net_device *dev); |
144 | static void gfar_clear_exact_match(struct net_device *dev); | |
b6bc7650 JP |
145 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
146 | const u8 *addr); | |
26ccfc37 | 147 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 148 | |
1da177e4 LT |
149 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
150 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
151 | MODULE_LICENSE("GPL"); | |
152 | ||
a12f801d | 153 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
154 | dma_addr_t buf) |
155 | { | |
8a102fe0 AV |
156 | u32 lstatus; |
157 | ||
158 | bdp->bufPtr = buf; | |
159 | ||
160 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 161 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
162 | lstatus |= BD_LFLAG(RXBD_WRAP); |
163 | ||
164 | eieio(); | |
165 | ||
166 | bdp->lstatus = lstatus; | |
167 | } | |
168 | ||
8728327e | 169 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 170 | { |
8728327e | 171 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
172 | struct gfar_priv_tx_q *tx_queue = NULL; |
173 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
174 | struct txbd8 *txbdp; |
175 | struct rxbd8 *rxbdp; | |
fba4ed03 | 176 | int i, j; |
a12f801d | 177 | |
fba4ed03 SG |
178 | for (i = 0; i < priv->num_tx_queues; i++) { |
179 | tx_queue = priv->tx_queue[i]; | |
180 | /* Initialize some variables in our dev structure */ | |
181 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
182 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
183 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
184 | tx_queue->skb_curtx = 0; | |
185 | tx_queue->skb_dirtytx = 0; | |
186 | ||
187 | /* Initialize Transmit Descriptor Ring */ | |
188 | txbdp = tx_queue->tx_bd_base; | |
189 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
190 | txbdp->lstatus = 0; | |
191 | txbdp->bufPtr = 0; | |
192 | txbdp++; | |
193 | } | |
8728327e | 194 | |
fba4ed03 SG |
195 | /* Set the last descriptor in the ring to indicate wrap */ |
196 | txbdp--; | |
197 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
198 | } |
199 | ||
fba4ed03 SG |
200 | for (i = 0; i < priv->num_rx_queues; i++) { |
201 | rx_queue = priv->rx_queue[i]; | |
202 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
203 | rx_queue->skb_currx = 0; | |
204 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 205 | |
fba4ed03 SG |
206 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
207 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 208 | |
fba4ed03 SG |
209 | if (skb) { |
210 | gfar_init_rxbdp(rx_queue, rxbdp, | |
211 | rxbdp->bufPtr); | |
212 | } else { | |
213 | skb = gfar_new_skb(ndev); | |
214 | if (!skb) { | |
59deab26 | 215 | netdev_err(ndev, "Can't allocate RX buffers\n"); |
1eb8f7a7 | 216 | return -ENOMEM; |
fba4ed03 SG |
217 | } |
218 | rx_queue->rx_skbuff[j] = skb; | |
219 | ||
220 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 221 | } |
8728327e | 222 | |
fba4ed03 | 223 | rxbdp++; |
8728327e AV |
224 | } |
225 | ||
8728327e AV |
226 | } |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
232 | { | |
826aa4a0 | 233 | void *vaddr; |
fba4ed03 SG |
234 | dma_addr_t addr; |
235 | int i, j, k; | |
826aa4a0 | 236 | struct gfar_private *priv = netdev_priv(ndev); |
369ec162 | 237 | struct device *dev = priv->dev; |
a12f801d SG |
238 | struct gfar_priv_tx_q *tx_queue = NULL; |
239 | struct gfar_priv_rx_q *rx_queue = NULL; | |
240 | ||
fba4ed03 SG |
241 | priv->total_tx_ring_size = 0; |
242 | for (i = 0; i < priv->num_tx_queues; i++) | |
243 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
244 | ||
245 | priv->total_rx_ring_size = 0; | |
246 | for (i = 0; i < priv->num_rx_queues; i++) | |
247 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
248 | |
249 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 250 | vaddr = dma_alloc_coherent(dev, |
d0320f75 JP |
251 | (priv->total_tx_ring_size * |
252 | sizeof(struct txbd8)) + | |
253 | (priv->total_rx_ring_size * | |
254 | sizeof(struct rxbd8)), | |
255 | &addr, GFP_KERNEL); | |
256 | if (!vaddr) | |
826aa4a0 | 257 | return -ENOMEM; |
826aa4a0 | 258 | |
fba4ed03 SG |
259 | for (i = 0; i < priv->num_tx_queues; i++) { |
260 | tx_queue = priv->tx_queue[i]; | |
43d620c8 | 261 | tx_queue->tx_bd_base = vaddr; |
fba4ed03 SG |
262 | tx_queue->tx_bd_dma_base = addr; |
263 | tx_queue->dev = ndev; | |
264 | /* enet DMA only understands physical addresses */ | |
bc4598bc JC |
265 | addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; |
266 | vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; | |
fba4ed03 | 267 | } |
826aa4a0 | 268 | |
826aa4a0 | 269 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
270 | for (i = 0; i < priv->num_rx_queues; i++) { |
271 | rx_queue = priv->rx_queue[i]; | |
43d620c8 | 272 | rx_queue->rx_bd_base = vaddr; |
fba4ed03 SG |
273 | rx_queue->rx_bd_dma_base = addr; |
274 | rx_queue->dev = ndev; | |
bc4598bc JC |
275 | addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; |
276 | vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; | |
fba4ed03 | 277 | } |
826aa4a0 AV |
278 | |
279 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
280 | for (i = 0; i < priv->num_tx_queues; i++) { |
281 | tx_queue = priv->tx_queue[i]; | |
14f8dc49 JP |
282 | tx_queue->tx_skbuff = |
283 | kmalloc_array(tx_queue->tx_ring_size, | |
284 | sizeof(*tx_queue->tx_skbuff), | |
285 | GFP_KERNEL); | |
286 | if (!tx_queue->tx_skbuff) | |
fba4ed03 | 287 | goto cleanup; |
826aa4a0 | 288 | |
fba4ed03 SG |
289 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
290 | tx_queue->tx_skbuff[k] = NULL; | |
291 | } | |
826aa4a0 | 292 | |
fba4ed03 SG |
293 | for (i = 0; i < priv->num_rx_queues; i++) { |
294 | rx_queue = priv->rx_queue[i]; | |
14f8dc49 JP |
295 | rx_queue->rx_skbuff = |
296 | kmalloc_array(rx_queue->rx_ring_size, | |
297 | sizeof(*rx_queue->rx_skbuff), | |
298 | GFP_KERNEL); | |
299 | if (!rx_queue->rx_skbuff) | |
fba4ed03 | 300 | goto cleanup; |
fba4ed03 SG |
301 | |
302 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
303 | rx_queue->rx_skbuff[j] = NULL; | |
304 | } | |
826aa4a0 | 305 | |
8728327e AV |
306 | if (gfar_init_bds(ndev)) |
307 | goto cleanup; | |
826aa4a0 AV |
308 | |
309 | return 0; | |
310 | ||
311 | cleanup: | |
312 | free_skb_resources(priv); | |
313 | return -ENOMEM; | |
314 | } | |
315 | ||
fba4ed03 SG |
316 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
317 | { | |
46ceb60c | 318 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 319 | u32 __iomem *baddr; |
fba4ed03 SG |
320 | int i; |
321 | ||
322 | baddr = ®s->tbase0; | |
bc4598bc | 323 | for (i = 0; i < priv->num_tx_queues; i++) { |
fba4ed03 | 324 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); |
bc4598bc | 325 | baddr += 2; |
fba4ed03 SG |
326 | } |
327 | ||
328 | baddr = ®s->rbase0; | |
bc4598bc | 329 | for (i = 0; i < priv->num_rx_queues; i++) { |
fba4ed03 | 330 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); |
bc4598bc | 331 | baddr += 2; |
fba4ed03 SG |
332 | } |
333 | } | |
334 | ||
826aa4a0 AV |
335 | static void gfar_init_mac(struct net_device *ndev) |
336 | { | |
337 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 338 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
339 | u32 rctrl = 0; |
340 | u32 tctrl = 0; | |
826aa4a0 | 341 | |
fba4ed03 SG |
342 | /* write the tx/rx base registers */ |
343 | gfar_init_tx_rx_base(priv); | |
32c513bc | 344 | |
826aa4a0 | 345 | /* Configure the coalescing support */ |
800c644b | 346 | gfar_configure_coalescing_all(priv); |
fba4ed03 | 347 | |
ba779711 CM |
348 | /* set this when rx hw offload (TOE) functions are being used */ |
349 | priv->uses_rxfcb = 0; | |
350 | ||
1ccb8389 | 351 | if (priv->rx_filer_enable) { |
fba4ed03 | 352 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
353 | /* Program the RIR0 reg with the required distribution */ |
354 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
355 | } | |
826aa4a0 | 356 | |
f5ae6279 CM |
357 | /* Restore PROMISC mode */ |
358 | if (ndev->flags & IFF_PROMISC) | |
359 | rctrl |= RCTRL_PROM; | |
360 | ||
ba779711 | 361 | if (ndev->features & NETIF_F_RXCSUM) { |
826aa4a0 | 362 | rctrl |= RCTRL_CHECKSUMMING; |
ba779711 CM |
363 | priv->uses_rxfcb = 1; |
364 | } | |
826aa4a0 AV |
365 | |
366 | if (priv->extended_hash) { | |
367 | rctrl |= RCTRL_EXTHASH; | |
368 | ||
369 | gfar_clear_exact_match(ndev); | |
370 | rctrl |= RCTRL_EMEN; | |
371 | } | |
372 | ||
373 | if (priv->padding) { | |
374 | rctrl &= ~RCTRL_PAL_MASK; | |
375 | rctrl |= RCTRL_PADDING(priv->padding); | |
376 | } | |
377 | ||
97553f7f | 378 | /* Enable HW time stamping if requested from user space */ |
ba779711 | 379 | if (priv->hwts_rx_en) { |
97553f7f | 380 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; |
ba779711 CM |
381 | priv->uses_rxfcb = 1; |
382 | } | |
97553f7f | 383 | |
f646968f | 384 | if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { |
b852b720 | 385 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; |
ba779711 CM |
386 | priv->uses_rxfcb = 1; |
387 | } | |
826aa4a0 AV |
388 | |
389 | /* Init rctrl based on our settings */ | |
390 | gfar_write(®s->rctrl, rctrl); | |
391 | ||
392 | if (ndev->features & NETIF_F_IP_CSUM) | |
393 | tctrl |= TCTRL_INIT_CSUM; | |
394 | ||
b98b8bab CM |
395 | if (priv->prio_sched_en) |
396 | tctrl |= TCTRL_TXSCHED_PRIO; | |
397 | else { | |
398 | tctrl |= TCTRL_TXSCHED_WRRS; | |
399 | gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); | |
400 | gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); | |
401 | } | |
fba4ed03 | 402 | |
826aa4a0 | 403 | gfar_write(®s->tctrl, tctrl); |
826aa4a0 AV |
404 | } |
405 | ||
a7f38041 SG |
406 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
407 | { | |
408 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
409 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
410 | unsigned long tx_packets = 0, tx_bytes = 0; | |
3a2e16c8 | 411 | int i; |
a7f38041 SG |
412 | |
413 | for (i = 0; i < priv->num_rx_queues; i++) { | |
414 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
bc4598bc | 415 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; |
a7f38041 SG |
416 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; |
417 | } | |
418 | ||
419 | dev->stats.rx_packets = rx_packets; | |
bc4598bc | 420 | dev->stats.rx_bytes = rx_bytes; |
a7f38041 SG |
421 | dev->stats.rx_dropped = rx_dropped; |
422 | ||
423 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
424 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
425 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
426 | } |
427 | ||
bc4598bc | 428 | dev->stats.tx_bytes = tx_bytes; |
a7f38041 SG |
429 | dev->stats.tx_packets = tx_packets; |
430 | ||
431 | return &dev->stats; | |
432 | } | |
433 | ||
26ccfc37 AF |
434 | static const struct net_device_ops gfar_netdev_ops = { |
435 | .ndo_open = gfar_enet_open, | |
436 | .ndo_start_xmit = gfar_start_xmit, | |
437 | .ndo_stop = gfar_close, | |
438 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 439 | .ndo_set_features = gfar_set_features, |
afc4b13d | 440 | .ndo_set_rx_mode = gfar_set_multi, |
26ccfc37 AF |
441 | .ndo_tx_timeout = gfar_timeout, |
442 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 443 | .ndo_get_stats = gfar_get_stats, |
240c102d BH |
444 | .ndo_set_mac_address = eth_mac_addr, |
445 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
446 | #ifdef CONFIG_NET_POLL_CONTROLLER |
447 | .ndo_poll_controller = gfar_netpoll, | |
448 | #endif | |
449 | }; | |
450 | ||
efeddce7 CM |
451 | static void gfar_ints_disable(struct gfar_private *priv) |
452 | { | |
453 | int i; | |
454 | for (i = 0; i < priv->num_grps; i++) { | |
455 | struct gfar __iomem *regs = priv->gfargrp[i].regs; | |
456 | /* Clear IEVENT */ | |
457 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
458 | ||
459 | /* Initialize IMASK */ | |
460 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
461 | } | |
462 | } | |
463 | ||
464 | static void gfar_ints_enable(struct gfar_private *priv) | |
465 | { | |
466 | int i; | |
467 | for (i = 0; i < priv->num_grps; i++) { | |
468 | struct gfar __iomem *regs = priv->gfargrp[i].regs; | |
469 | /* Unmask the interrupts we look for */ | |
470 | gfar_write(®s->imask, IMASK_DEFAULT); | |
471 | } | |
472 | } | |
473 | ||
fba4ed03 SG |
474 | void lock_rx_qs(struct gfar_private *priv) |
475 | { | |
3a2e16c8 | 476 | int i; |
fba4ed03 SG |
477 | |
478 | for (i = 0; i < priv->num_rx_queues; i++) | |
479 | spin_lock(&priv->rx_queue[i]->rxlock); | |
480 | } | |
481 | ||
482 | void lock_tx_qs(struct gfar_private *priv) | |
483 | { | |
3a2e16c8 | 484 | int i; |
fba4ed03 SG |
485 | |
486 | for (i = 0; i < priv->num_tx_queues; i++) | |
487 | spin_lock(&priv->tx_queue[i]->txlock); | |
488 | } | |
489 | ||
490 | void unlock_rx_qs(struct gfar_private *priv) | |
491 | { | |
3a2e16c8 | 492 | int i; |
fba4ed03 SG |
493 | |
494 | for (i = 0; i < priv->num_rx_queues; i++) | |
495 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
496 | } | |
497 | ||
498 | void unlock_tx_qs(struct gfar_private *priv) | |
499 | { | |
3a2e16c8 | 500 | int i; |
fba4ed03 SG |
501 | |
502 | for (i = 0; i < priv->num_tx_queues; i++) | |
503 | spin_unlock(&priv->tx_queue[i]->txlock); | |
504 | } | |
505 | ||
20862788 CM |
506 | static int gfar_alloc_tx_queues(struct gfar_private *priv) |
507 | { | |
508 | int i; | |
509 | ||
510 | for (i = 0; i < priv->num_tx_queues; i++) { | |
511 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), | |
512 | GFP_KERNEL); | |
513 | if (!priv->tx_queue[i]) | |
514 | return -ENOMEM; | |
515 | ||
516 | priv->tx_queue[i]->tx_skbuff = NULL; | |
517 | priv->tx_queue[i]->qindex = i; | |
518 | priv->tx_queue[i]->dev = priv->ndev; | |
519 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
520 | } | |
521 | return 0; | |
522 | } | |
523 | ||
524 | static int gfar_alloc_rx_queues(struct gfar_private *priv) | |
525 | { | |
526 | int i; | |
527 | ||
528 | for (i = 0; i < priv->num_rx_queues; i++) { | |
529 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), | |
530 | GFP_KERNEL); | |
531 | if (!priv->rx_queue[i]) | |
532 | return -ENOMEM; | |
533 | ||
534 | priv->rx_queue[i]->rx_skbuff = NULL; | |
535 | priv->rx_queue[i]->qindex = i; | |
536 | priv->rx_queue[i]->dev = priv->ndev; | |
537 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
538 | } | |
539 | return 0; | |
540 | } | |
541 | ||
542 | static void gfar_free_tx_queues(struct gfar_private *priv) | |
fba4ed03 | 543 | { |
3a2e16c8 | 544 | int i; |
fba4ed03 SG |
545 | |
546 | for (i = 0; i < priv->num_tx_queues; i++) | |
547 | kfree(priv->tx_queue[i]); | |
548 | } | |
549 | ||
20862788 | 550 | static void gfar_free_rx_queues(struct gfar_private *priv) |
fba4ed03 | 551 | { |
3a2e16c8 | 552 | int i; |
fba4ed03 SG |
553 | |
554 | for (i = 0; i < priv->num_rx_queues; i++) | |
555 | kfree(priv->rx_queue[i]); | |
556 | } | |
557 | ||
46ceb60c SG |
558 | static void unmap_group_regs(struct gfar_private *priv) |
559 | { | |
3a2e16c8 | 560 | int i; |
46ceb60c SG |
561 | |
562 | for (i = 0; i < MAXGROUPS; i++) | |
563 | if (priv->gfargrp[i].regs) | |
564 | iounmap(priv->gfargrp[i].regs); | |
565 | } | |
566 | ||
ee873fda CM |
567 | static void free_gfar_dev(struct gfar_private *priv) |
568 | { | |
569 | int i, j; | |
570 | ||
571 | for (i = 0; i < priv->num_grps; i++) | |
572 | for (j = 0; j < GFAR_NUM_IRQS; j++) { | |
573 | kfree(priv->gfargrp[i].irqinfo[j]); | |
574 | priv->gfargrp[i].irqinfo[j] = NULL; | |
575 | } | |
576 | ||
577 | free_netdev(priv->ndev); | |
578 | } | |
579 | ||
46ceb60c SG |
580 | static void disable_napi(struct gfar_private *priv) |
581 | { | |
3a2e16c8 | 582 | int i; |
46ceb60c SG |
583 | |
584 | for (i = 0; i < priv->num_grps; i++) | |
585 | napi_disable(&priv->gfargrp[i].napi); | |
586 | } | |
587 | ||
588 | static void enable_napi(struct gfar_private *priv) | |
589 | { | |
3a2e16c8 | 590 | int i; |
46ceb60c SG |
591 | |
592 | for (i = 0; i < priv->num_grps; i++) | |
593 | napi_enable(&priv->gfargrp[i].napi); | |
594 | } | |
595 | ||
596 | static int gfar_parse_group(struct device_node *np, | |
bc4598bc | 597 | struct gfar_private *priv, const char *model) |
46ceb60c | 598 | { |
5fedcc14 | 599 | struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; |
46ceb60c | 600 | u32 *queue_mask; |
ee873fda CM |
601 | int i; |
602 | ||
7c1e7e99 PG |
603 | for (i = 0; i < GFAR_NUM_IRQS; i++) { |
604 | grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), | |
605 | GFP_KERNEL); | |
606 | if (!grp->irqinfo[i]) | |
ee873fda | 607 | return -ENOMEM; |
ee873fda | 608 | } |
46ceb60c | 609 | |
5fedcc14 CM |
610 | grp->regs = of_iomap(np, 0); |
611 | if (!grp->regs) | |
46ceb60c SG |
612 | return -ENOMEM; |
613 | ||
ee873fda | 614 | gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); |
46ceb60c SG |
615 | |
616 | /* If we aren't the FEC we have multiple interrupts */ | |
617 | if (model && strcasecmp(model, "FEC")) { | |
ee873fda CM |
618 | gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); |
619 | gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); | |
620 | if (gfar_irq(grp, TX)->irq == NO_IRQ || | |
621 | gfar_irq(grp, RX)->irq == NO_IRQ || | |
622 | gfar_irq(grp, ER)->irq == NO_IRQ) | |
46ceb60c | 623 | return -EINVAL; |
46ceb60c SG |
624 | } |
625 | ||
5fedcc14 CM |
626 | grp->priv = priv; |
627 | spin_lock_init(&grp->grplock); | |
bc4598bc JC |
628 | if (priv->mode == MQ_MG_MODE) { |
629 | queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); | |
5fedcc14 | 630 | grp->rx_bit_map = queue_mask ? |
bc4598bc JC |
631 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
632 | queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); | |
5fedcc14 | 633 | grp->tx_bit_map = queue_mask ? |
bc4598bc | 634 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
46ceb60c | 635 | } else { |
5fedcc14 CM |
636 | grp->rx_bit_map = 0xFF; |
637 | grp->tx_bit_map = 0xFF; | |
46ceb60c | 638 | } |
20862788 CM |
639 | |
640 | /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses | |
641 | * right to left, so we need to revert the 8 bits to get the q index | |
642 | */ | |
643 | grp->rx_bit_map = bitrev8(grp->rx_bit_map); | |
644 | grp->tx_bit_map = bitrev8(grp->tx_bit_map); | |
645 | ||
646 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
647 | * also assign queues to groups | |
648 | */ | |
649 | for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { | |
650 | grp->num_rx_queues++; | |
651 | grp->rstat |= (RSTAT_CLEAR_RHALT >> i); | |
652 | priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
653 | priv->rx_queue[i]->grp = grp; | |
654 | } | |
655 | ||
656 | for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { | |
657 | grp->num_tx_queues++; | |
658 | grp->tstat |= (TSTAT_CLEAR_THALT >> i); | |
659 | priv->tqueue |= (TQUEUE_EN0 >> i); | |
660 | priv->tx_queue[i]->grp = grp; | |
661 | } | |
662 | ||
46ceb60c SG |
663 | priv->num_grps++; |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
2dc11581 | 668 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 669 | { |
b31a1d8b AF |
670 | const char *model; |
671 | const char *ctype; | |
672 | const void *mac_addr; | |
fba4ed03 SG |
673 | int err = 0, i; |
674 | struct net_device *dev = NULL; | |
675 | struct gfar_private *priv = NULL; | |
61c7a080 | 676 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 677 | struct device_node *child = NULL; |
4d7902f2 AF |
678 | const u32 *stash; |
679 | const u32 *stash_len; | |
680 | const u32 *stash_idx; | |
fba4ed03 SG |
681 | unsigned int num_tx_qs, num_rx_qs; |
682 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
683 | |
684 | if (!np || !of_device_is_available(np)) | |
685 | return -ENODEV; | |
686 | ||
fba4ed03 SG |
687 | /* parse the num of tx and rx queues */ |
688 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
689 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
690 | ||
691 | if (num_tx_qs > MAX_TX_QS) { | |
59deab26 JP |
692 | pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", |
693 | num_tx_qs, MAX_TX_QS); | |
694 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
695 | return -EINVAL; |
696 | } | |
697 | ||
698 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
699 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
700 | ||
701 | if (num_rx_qs > MAX_RX_QS) { | |
59deab26 JP |
702 | pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", |
703 | num_rx_qs, MAX_RX_QS); | |
704 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
705 | return -EINVAL; |
706 | } | |
707 | ||
708 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
709 | dev = *pdev; | |
710 | if (NULL == dev) | |
711 | return -ENOMEM; | |
712 | ||
713 | priv = netdev_priv(dev); | |
fba4ed03 SG |
714 | priv->ndev = dev; |
715 | ||
fba4ed03 | 716 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 717 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 718 | priv->num_rx_queues = num_rx_qs; |
20862788 CM |
719 | |
720 | err = gfar_alloc_tx_queues(priv); | |
721 | if (err) | |
722 | goto tx_alloc_failed; | |
723 | ||
724 | err = gfar_alloc_rx_queues(priv); | |
725 | if (err) | |
726 | goto rx_alloc_failed; | |
b31a1d8b | 727 | |
0977f817 | 728 | /* Init Rx queue filer rule set linked list */ |
4aa3a715 SP |
729 | INIT_LIST_HEAD(&priv->rx_list.list); |
730 | priv->rx_list.count = 0; | |
731 | mutex_init(&priv->rx_queue_access); | |
732 | ||
b31a1d8b AF |
733 | model = of_get_property(np, "model", NULL); |
734 | ||
46ceb60c SG |
735 | for (i = 0; i < MAXGROUPS; i++) |
736 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 737 | |
46ceb60c SG |
738 | /* Parse and initialize group specific information */ |
739 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
740 | priv->mode = MQ_MG_MODE; | |
741 | for_each_child_of_node(np, child) { | |
742 | err = gfar_parse_group(child, priv, model); | |
743 | if (err) | |
744 | goto err_grp_init; | |
b31a1d8b | 745 | } |
46ceb60c SG |
746 | } else { |
747 | priv->mode = SQ_SG_MODE; | |
748 | err = gfar_parse_group(np, priv, model); | |
bc4598bc | 749 | if (err) |
46ceb60c | 750 | goto err_grp_init; |
b31a1d8b AF |
751 | } |
752 | ||
4d7902f2 AF |
753 | stash = of_get_property(np, "bd-stash", NULL); |
754 | ||
a12f801d | 755 | if (stash) { |
4d7902f2 AF |
756 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
757 | priv->bd_stash_en = 1; | |
758 | } | |
759 | ||
760 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
761 | ||
762 | if (stash_len) | |
763 | priv->rx_stash_size = *stash_len; | |
764 | ||
765 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
766 | ||
767 | if (stash_idx) | |
768 | priv->rx_stash_index = *stash_idx; | |
769 | ||
770 | if (stash_len || stash_idx) | |
771 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
772 | ||
b31a1d8b | 773 | mac_addr = of_get_mac_address(np); |
bc4598bc | 774 | |
b31a1d8b | 775 | if (mac_addr) |
6a3c910c | 776 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
b31a1d8b AF |
777 | |
778 | if (model && !strcasecmp(model, "TSEC")) | |
34018fd4 | 779 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | |
bc4598bc JC |
780 | FSL_GIANFAR_DEV_HAS_COALESCE | |
781 | FSL_GIANFAR_DEV_HAS_RMON | | |
782 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
783 | ||
b31a1d8b | 784 | if (model && !strcasecmp(model, "eTSEC")) |
34018fd4 | 785 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | |
bc4598bc JC |
786 | FSL_GIANFAR_DEV_HAS_COALESCE | |
787 | FSL_GIANFAR_DEV_HAS_RMON | | |
788 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
bc4598bc JC |
789 | FSL_GIANFAR_DEV_HAS_CSUM | |
790 | FSL_GIANFAR_DEV_HAS_VLAN | | |
791 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
792 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | | |
793 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
794 | |
795 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
796 | ||
797 | /* We only care about rgmii-id. The rest are autodetected */ | |
798 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
799 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
800 | else | |
801 | priv->interface = PHY_INTERFACE_MODE_MII; | |
802 | ||
803 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
804 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
805 | ||
fe192a49 | 806 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
807 | |
808 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 809 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
810 | |
811 | return 0; | |
812 | ||
46ceb60c SG |
813 | err_grp_init: |
814 | unmap_group_regs(priv); | |
20862788 CM |
815 | rx_alloc_failed: |
816 | gfar_free_rx_queues(priv); | |
817 | tx_alloc_failed: | |
818 | gfar_free_tx_queues(priv); | |
ee873fda | 819 | free_gfar_dev(priv); |
b31a1d8b AF |
820 | return err; |
821 | } | |
822 | ||
ca0c88c2 | 823 | static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) |
cc772ab7 MR |
824 | { |
825 | struct hwtstamp_config config; | |
826 | struct gfar_private *priv = netdev_priv(netdev); | |
827 | ||
828 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
829 | return -EFAULT; | |
830 | ||
831 | /* reserved for future extensions */ | |
832 | if (config.flags) | |
833 | return -EINVAL; | |
834 | ||
f0ee7acf MR |
835 | switch (config.tx_type) { |
836 | case HWTSTAMP_TX_OFF: | |
837 | priv->hwts_tx_en = 0; | |
838 | break; | |
839 | case HWTSTAMP_TX_ON: | |
840 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
841 | return -ERANGE; | |
842 | priv->hwts_tx_en = 1; | |
843 | break; | |
844 | default: | |
cc772ab7 | 845 | return -ERANGE; |
f0ee7acf | 846 | } |
cc772ab7 MR |
847 | |
848 | switch (config.rx_filter) { | |
849 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
850 | if (priv->hwts_rx_en) { |
851 | stop_gfar(netdev); | |
852 | priv->hwts_rx_en = 0; | |
853 | startup_gfar(netdev); | |
854 | } | |
cc772ab7 MR |
855 | break; |
856 | default: | |
857 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
858 | return -ERANGE; | |
97553f7f MR |
859 | if (!priv->hwts_rx_en) { |
860 | stop_gfar(netdev); | |
861 | priv->hwts_rx_en = 1; | |
862 | startup_gfar(netdev); | |
863 | } | |
cc772ab7 MR |
864 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
865 | break; | |
866 | } | |
867 | ||
868 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
869 | -EFAULT : 0; | |
870 | } | |
871 | ||
ca0c88c2 BH |
872 | static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) |
873 | { | |
874 | struct hwtstamp_config config; | |
875 | struct gfar_private *priv = netdev_priv(netdev); | |
876 | ||
877 | config.flags = 0; | |
878 | config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; | |
879 | config.rx_filter = (priv->hwts_rx_en ? | |
880 | HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); | |
881 | ||
882 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
883 | -EFAULT : 0; | |
884 | } | |
885 | ||
0faac9f7 CW |
886 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
887 | { | |
888 | struct gfar_private *priv = netdev_priv(dev); | |
889 | ||
890 | if (!netif_running(dev)) | |
891 | return -EINVAL; | |
892 | ||
cc772ab7 | 893 | if (cmd == SIOCSHWTSTAMP) |
ca0c88c2 BH |
894 | return gfar_hwtstamp_set(dev, rq); |
895 | if (cmd == SIOCGHWTSTAMP) | |
896 | return gfar_hwtstamp_get(dev, rq); | |
cc772ab7 | 897 | |
0faac9f7 CW |
898 | if (!priv->phydev) |
899 | return -ENODEV; | |
900 | ||
28b04113 | 901 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
902 | } |
903 | ||
18294ad1 AV |
904 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
905 | u32 class) | |
7a8b3372 SG |
906 | { |
907 | u32 rqfpr = FPR_FILER_MASK; | |
908 | u32 rqfcr = 0x0; | |
909 | ||
910 | rqfar--; | |
911 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
912 | priv->ftp_rqfpr[rqfar] = rqfpr; |
913 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
914 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
915 | ||
916 | rqfar--; | |
917 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
918 | priv->ftp_rqfpr[rqfar] = rqfpr; |
919 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
920 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
921 | ||
922 | rqfar--; | |
923 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
924 | rqfpr = class; | |
6c43e046 WJB |
925 | priv->ftp_rqfcr[rqfar] = rqfcr; |
926 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
927 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
928 | ||
929 | rqfar--; | |
930 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
931 | rqfpr = class; | |
6c43e046 WJB |
932 | priv->ftp_rqfcr[rqfar] = rqfcr; |
933 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
934 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
935 | ||
936 | return rqfar; | |
937 | } | |
938 | ||
939 | static void gfar_init_filer_table(struct gfar_private *priv) | |
940 | { | |
941 | int i = 0x0; | |
942 | u32 rqfar = MAX_FILER_IDX; | |
943 | u32 rqfcr = 0x0; | |
944 | u32 rqfpr = FPR_FILER_MASK; | |
945 | ||
946 | /* Default rule */ | |
947 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
948 | priv->ftp_rqfcr[rqfar] = rqfcr; |
949 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
950 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
951 | ||
952 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
953 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
954 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
955 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
956 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
957 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
958 | ||
85dd08eb | 959 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
960 | priv->cur_filer_idx = rqfar; |
961 | ||
962 | /* Rest are masked rules */ | |
963 | rqfcr = RQFCR_CMP_NOMATCH; | |
964 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
965 | priv->ftp_rqfcr[i] = rqfcr; |
966 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
967 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
968 | } | |
969 | } | |
970 | ||
2969b1f7 | 971 | static void __gfar_detect_errata_83xx(struct gfar_private *priv) |
7d350977 | 972 | { |
7d350977 AV |
973 | unsigned int pvr = mfspr(SPRN_PVR); |
974 | unsigned int svr = mfspr(SPRN_SVR); | |
975 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
976 | unsigned int rev = svr & 0xffff; | |
977 | ||
978 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
979 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
bc4598bc | 980 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
7d350977 AV |
981 | priv->errata |= GFAR_ERRATA_74; |
982 | ||
deb90eac AV |
983 | /* MPC8313 and MPC837x all rev */ |
984 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 985 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
deb90eac AV |
986 | priv->errata |= GFAR_ERRATA_76; |
987 | ||
2969b1f7 CM |
988 | /* MPC8313 Rev < 2.0 */ |
989 | if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) | |
990 | priv->errata |= GFAR_ERRATA_12; | |
991 | } | |
992 | ||
993 | static void __gfar_detect_errata_85xx(struct gfar_private *priv) | |
994 | { | |
995 | unsigned int svr = mfspr(SPRN_SVR); | |
996 | ||
997 | if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20)) | |
4363c2fd | 998 | priv->errata |= GFAR_ERRATA_12; |
53fad773 CM |
999 | if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) || |
1000 | ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20))) | |
1001 | priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */ | |
2969b1f7 CM |
1002 | } |
1003 | ||
1004 | static void gfar_detect_errata(struct gfar_private *priv) | |
1005 | { | |
1006 | struct device *dev = &priv->ofdev->dev; | |
1007 | ||
1008 | /* no plans to fix */ | |
1009 | priv->errata |= GFAR_ERRATA_A002; | |
1010 | ||
1011 | if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)) | |
1012 | __gfar_detect_errata_85xx(priv); | |
1013 | else /* non-mpc85xx parts, i.e. e300 core based */ | |
1014 | __gfar_detect_errata_83xx(priv); | |
4363c2fd | 1015 | |
7d350977 AV |
1016 | if (priv->errata) |
1017 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
1018 | priv->errata); | |
1019 | } | |
1020 | ||
20862788 CM |
1021 | static void gfar_hw_init(struct gfar_private *priv) |
1022 | { | |
1023 | struct gfar __iomem *regs = priv->gfargrp[0].regs; | |
34018fd4 | 1024 | u32 tempval, attrs; |
20862788 CM |
1025 | |
1026 | /* Reset MAC layer */ | |
1027 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); | |
1028 | ||
1029 | /* We need to delay at least 3 TX clocks */ | |
1030 | udelay(2); | |
1031 | ||
1032 | /* the soft reset bit is not self-resetting, so we need to | |
1033 | * clear it before resuming normal operation | |
1034 | */ | |
1035 | gfar_write(®s->maccfg1, 0); | |
1036 | ||
1037 | /* Initialize MACCFG2. */ | |
1038 | tempval = MACCFG2_INIT_SETTINGS; | |
1039 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1040 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1041 | gfar_write(®s->maccfg2, tempval); | |
1042 | ||
1043 | /* Initialize ECNTRL */ | |
1044 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); | |
1045 | ||
34018fd4 CM |
1046 | /* Set the extraction length and index */ |
1047 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
1048 | ATTRELI_EI(priv->rx_stash_index); | |
1049 | ||
1050 | gfar_write(®s->attreli, attrs); | |
1051 | ||
1052 | /* Start with defaults, and add stashing | |
1053 | * depending on driver parameters | |
1054 | */ | |
1055 | attrs = ATTR_INIT_SETTINGS; | |
1056 | ||
1057 | if (priv->bd_stash_en) | |
1058 | attrs |= ATTR_BDSTASH; | |
1059 | ||
1060 | if (priv->rx_stash_size != 0) | |
1061 | attrs |= ATTR_BUFSTASH; | |
1062 | ||
1063 | gfar_write(®s->attr, attrs); | |
1064 | ||
1065 | /* FIFO configs */ | |
1066 | gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR); | |
1067 | gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE); | |
1068 | gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF); | |
1069 | ||
20862788 CM |
1070 | /* Program the interrupt steering regs, only for MG devices */ |
1071 | if (priv->num_grps > 1) | |
1072 | gfar_write_isrg(priv); | |
1073 | ||
1074 | /* Enable all Rx/Tx queues after MAC reset */ | |
1075 | gfar_write(®s->rqueue, priv->rqueue); | |
1076 | gfar_write(®s->tqueue, priv->tqueue); | |
1077 | } | |
1078 | ||
1079 | static void __init gfar_init_addr_hash_table(struct gfar_private *priv) | |
1080 | { | |
1081 | struct gfar __iomem *regs = priv->gfargrp[0].regs; | |
1082 | ||
1083 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { | |
1084 | priv->extended_hash = 1; | |
1085 | priv->hash_width = 9; | |
1086 | ||
1087 | priv->hash_regs[0] = ®s->igaddr0; | |
1088 | priv->hash_regs[1] = ®s->igaddr1; | |
1089 | priv->hash_regs[2] = ®s->igaddr2; | |
1090 | priv->hash_regs[3] = ®s->igaddr3; | |
1091 | priv->hash_regs[4] = ®s->igaddr4; | |
1092 | priv->hash_regs[5] = ®s->igaddr5; | |
1093 | priv->hash_regs[6] = ®s->igaddr6; | |
1094 | priv->hash_regs[7] = ®s->igaddr7; | |
1095 | priv->hash_regs[8] = ®s->gaddr0; | |
1096 | priv->hash_regs[9] = ®s->gaddr1; | |
1097 | priv->hash_regs[10] = ®s->gaddr2; | |
1098 | priv->hash_regs[11] = ®s->gaddr3; | |
1099 | priv->hash_regs[12] = ®s->gaddr4; | |
1100 | priv->hash_regs[13] = ®s->gaddr5; | |
1101 | priv->hash_regs[14] = ®s->gaddr6; | |
1102 | priv->hash_regs[15] = ®s->gaddr7; | |
1103 | ||
1104 | } else { | |
1105 | priv->extended_hash = 0; | |
1106 | priv->hash_width = 8; | |
1107 | ||
1108 | priv->hash_regs[0] = ®s->gaddr0; | |
1109 | priv->hash_regs[1] = ®s->gaddr1; | |
1110 | priv->hash_regs[2] = ®s->gaddr2; | |
1111 | priv->hash_regs[3] = ®s->gaddr3; | |
1112 | priv->hash_regs[4] = ®s->gaddr4; | |
1113 | priv->hash_regs[5] = ®s->gaddr5; | |
1114 | priv->hash_regs[6] = ®s->gaddr6; | |
1115 | priv->hash_regs[7] = ®s->gaddr7; | |
1116 | } | |
1117 | } | |
1118 | ||
bb40dcbb | 1119 | /* Set up the ethernet device structure, private data, |
0977f817 JC |
1120 | * and anything else we need before we start |
1121 | */ | |
74888760 | 1122 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 | 1123 | { |
1da177e4 LT |
1124 | struct net_device *dev = NULL; |
1125 | struct gfar_private *priv = NULL; | |
20862788 | 1126 | int err = 0, i; |
1da177e4 | 1127 | |
fba4ed03 | 1128 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 1129 | |
fba4ed03 SG |
1130 | if (err) |
1131 | return err; | |
1da177e4 LT |
1132 | |
1133 | priv = netdev_priv(dev); | |
4826857f KG |
1134 | priv->ndev = dev; |
1135 | priv->ofdev = ofdev; | |
369ec162 | 1136 | priv->dev = &ofdev->dev; |
4826857f | 1137 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 1138 | |
d87eb127 | 1139 | spin_lock_init(&priv->bflock); |
ab939905 | 1140 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 1141 | |
8513fbd8 | 1142 | platform_set_drvdata(ofdev, priv); |
1da177e4 | 1143 | |
7d350977 AV |
1144 | gfar_detect_errata(priv); |
1145 | ||
0977f817 JC |
1146 | /* Stop the DMA engine now, in case it was running before |
1147 | * (The firmware could have used it, and left it running). | |
1148 | */ | |
257d938a | 1149 | gfar_halt(dev); |
1da177e4 | 1150 | |
20862788 | 1151 | gfar_hw_init(priv); |
1da177e4 | 1152 | |
1da177e4 | 1153 | /* Set the dev->base_addr to the gfar reg region */ |
20862788 | 1154 | dev->base_addr = (unsigned long) priv->gfargrp[0].regs; |
1da177e4 | 1155 | |
1da177e4 | 1156 | /* Fill in the dev structure */ |
1da177e4 | 1157 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1158 | dev->mtu = 1500; |
26ccfc37 | 1159 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1160 | dev->ethtool_ops = &gfar_ethtool_ops; |
1161 | ||
fba4ed03 | 1162 | /* Register for napi ...We are registering NAPI for each grp */ |
5eaedf31 CM |
1163 | if (priv->mode == SQ_SG_MODE) |
1164 | netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq, | |
bc4598bc | 1165 | GFAR_DEV_WEIGHT); |
5eaedf31 CM |
1166 | else |
1167 | for (i = 0; i < priv->num_grps; i++) | |
1168 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, | |
1169 | GFAR_DEV_WEIGHT); | |
a12f801d | 1170 | |
b31a1d8b | 1171 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 | 1172 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1173 | NETIF_F_RXCSUM; |
8b3afe95 | 1174 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1175 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; |
8b3afe95 | 1176 | } |
0bbaf069 | 1177 | |
87c288c6 | 1178 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
f646968f PM |
1179 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | |
1180 | NETIF_F_HW_VLAN_CTAG_RX; | |
1181 | dev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
87c288c6 | 1182 | } |
0bbaf069 | 1183 | |
20862788 | 1184 | gfar_init_addr_hash_table(priv); |
0bbaf069 | 1185 | |
532c37bc CM |
1186 | /* Insert receive time stamps into padding alignment bytes */ |
1187 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) | |
1188 | priv->padding = 8; | |
0bbaf069 | 1189 | |
cc772ab7 | 1190 | if (dev->features & NETIF_F_IP_CSUM || |
bc4598bc | 1191 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) |
bee9e58c | 1192 | dev->needed_headroom = GMAC_FCB_LEN; |
1da177e4 LT |
1193 | |
1194 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; | |
1da177e4 | 1195 | |
a12f801d | 1196 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1197 | for (i = 0; i < priv->num_tx_queues; i++) { |
1198 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1199 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1200 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1201 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1202 | } | |
a12f801d | 1203 | |
fba4ed03 SG |
1204 | for (i = 0; i < priv->num_rx_queues; i++) { |
1205 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1206 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1207 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1208 | } | |
1da177e4 | 1209 | |
0977f817 | 1210 | /* always enable rx filer */ |
4aa3a715 | 1211 | priv->rx_filer_enable = 1; |
0bbaf069 KG |
1212 | /* Enable most messages by default */ |
1213 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
b98b8bab CM |
1214 | /* use pritority h/w tx queue scheduling for single queue devices */ |
1215 | if (priv->num_tx_queues == 1) | |
1216 | priv->prio_sched_en = 1; | |
0bbaf069 | 1217 | |
d3eab82b TP |
1218 | /* Carrier starts down, phylib will bring it up */ |
1219 | netif_carrier_off(dev); | |
1220 | ||
1da177e4 LT |
1221 | err = register_netdev(dev); |
1222 | ||
1223 | if (err) { | |
59deab26 | 1224 | pr_err("%s: Cannot register net device, aborting\n", dev->name); |
1da177e4 LT |
1225 | goto register_fail; |
1226 | } | |
1227 | ||
2884e5cc | 1228 | device_init_wakeup(&dev->dev, |
bc4598bc JC |
1229 | priv->device_flags & |
1230 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
2884e5cc | 1231 | |
c50a5d9a | 1232 | /* fill out IRQ number and name fields */ |
46ceb60c | 1233 | for (i = 0; i < priv->num_grps; i++) { |
ee873fda | 1234 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
46ceb60c | 1235 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
ee873fda | 1236 | sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", |
0015e551 | 1237 | dev->name, "_g", '0' + i, "_tx"); |
ee873fda | 1238 | sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", |
0015e551 | 1239 | dev->name, "_g", '0' + i, "_rx"); |
ee873fda | 1240 | sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", |
0015e551 | 1241 | dev->name, "_g", '0' + i, "_er"); |
46ceb60c | 1242 | } else |
ee873fda | 1243 | strcpy(gfar_irq(grp, TX)->name, dev->name); |
46ceb60c | 1244 | } |
c50a5d9a | 1245 | |
7a8b3372 SG |
1246 | /* Initialize the filer table */ |
1247 | gfar_init_filer_table(priv); | |
1248 | ||
1da177e4 | 1249 | /* Print out the device info */ |
59deab26 | 1250 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
1da177e4 | 1251 | |
0977f817 JC |
1252 | /* Even more device info helps when determining which kernel |
1253 | * provided which set of benchmarks. | |
1254 | */ | |
59deab26 | 1255 | netdev_info(dev, "Running with NAPI enabled\n"); |
fba4ed03 | 1256 | for (i = 0; i < priv->num_rx_queues; i++) |
59deab26 JP |
1257 | netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", |
1258 | i, priv->rx_queue[i]->rx_ring_size); | |
bc4598bc | 1259 | for (i = 0; i < priv->num_tx_queues; i++) |
59deab26 JP |
1260 | netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", |
1261 | i, priv->tx_queue[i]->tx_ring_size); | |
1da177e4 LT |
1262 | |
1263 | return 0; | |
1264 | ||
1265 | register_fail: | |
46ceb60c | 1266 | unmap_group_regs(priv); |
20862788 CM |
1267 | gfar_free_rx_queues(priv); |
1268 | gfar_free_tx_queues(priv); | |
fe192a49 GL |
1269 | if (priv->phy_node) |
1270 | of_node_put(priv->phy_node); | |
1271 | if (priv->tbi_node) | |
1272 | of_node_put(priv->tbi_node); | |
ee873fda | 1273 | free_gfar_dev(priv); |
bb40dcbb | 1274 | return err; |
1da177e4 LT |
1275 | } |
1276 | ||
2dc11581 | 1277 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1278 | { |
8513fbd8 | 1279 | struct gfar_private *priv = platform_get_drvdata(ofdev); |
1da177e4 | 1280 | |
fe192a49 GL |
1281 | if (priv->phy_node) |
1282 | of_node_put(priv->phy_node); | |
1283 | if (priv->tbi_node) | |
1284 | of_node_put(priv->tbi_node); | |
1285 | ||
d9d8e041 | 1286 | unregister_netdev(priv->ndev); |
46ceb60c | 1287 | unmap_group_regs(priv); |
20862788 CM |
1288 | gfar_free_rx_queues(priv); |
1289 | gfar_free_tx_queues(priv); | |
ee873fda | 1290 | free_gfar_dev(priv); |
1da177e4 LT |
1291 | |
1292 | return 0; | |
1293 | } | |
1294 | ||
d87eb127 | 1295 | #ifdef CONFIG_PM |
be926fc4 AV |
1296 | |
1297 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1298 | { |
be926fc4 AV |
1299 | struct gfar_private *priv = dev_get_drvdata(dev); |
1300 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1301 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1302 | unsigned long flags; |
1303 | u32 tempval; | |
1304 | ||
1305 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1306 | (priv->device_flags & |
1307 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1308 | |
be926fc4 | 1309 | netif_device_detach(ndev); |
d87eb127 | 1310 | |
be926fc4 | 1311 | if (netif_running(ndev)) { |
fba4ed03 SG |
1312 | |
1313 | local_irq_save(flags); | |
1314 | lock_tx_qs(priv); | |
1315 | lock_rx_qs(priv); | |
d87eb127 | 1316 | |
be926fc4 | 1317 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1318 | |
1319 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1320 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1321 | |
1322 | tempval &= ~MACCFG1_TX_EN; | |
1323 | ||
1324 | if (!magic_packet) | |
1325 | tempval &= ~MACCFG1_RX_EN; | |
1326 | ||
f4983704 | 1327 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1328 | |
fba4ed03 SG |
1329 | unlock_rx_qs(priv); |
1330 | unlock_tx_qs(priv); | |
1331 | local_irq_restore(flags); | |
d87eb127 | 1332 | |
46ceb60c | 1333 | disable_napi(priv); |
d87eb127 SW |
1334 | |
1335 | if (magic_packet) { | |
1336 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1337 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1338 | |
1339 | /* Enable Magic Packet mode */ | |
f4983704 | 1340 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1341 | tempval |= MACCFG2_MPEN; |
f4983704 | 1342 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1343 | } else { |
1344 | phy_stop(priv->phydev); | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | return 0; | |
1349 | } | |
1350 | ||
be926fc4 | 1351 | static int gfar_resume(struct device *dev) |
d87eb127 | 1352 | { |
be926fc4 AV |
1353 | struct gfar_private *priv = dev_get_drvdata(dev); |
1354 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1355 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1356 | unsigned long flags; |
1357 | u32 tempval; | |
1358 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1359 | (priv->device_flags & |
1360 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1361 | |
be926fc4 AV |
1362 | if (!netif_running(ndev)) { |
1363 | netif_device_attach(ndev); | |
d87eb127 SW |
1364 | return 0; |
1365 | } | |
1366 | ||
1367 | if (!magic_packet && priv->phydev) | |
1368 | phy_start(priv->phydev); | |
1369 | ||
1370 | /* Disable Magic Packet mode, in case something | |
1371 | * else woke us up. | |
1372 | */ | |
fba4ed03 SG |
1373 | local_irq_save(flags); |
1374 | lock_tx_qs(priv); | |
1375 | lock_rx_qs(priv); | |
d87eb127 | 1376 | |
f4983704 | 1377 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1378 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1379 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1380 | |
be926fc4 | 1381 | gfar_start(ndev); |
d87eb127 | 1382 | |
fba4ed03 SG |
1383 | unlock_rx_qs(priv); |
1384 | unlock_tx_qs(priv); | |
1385 | local_irq_restore(flags); | |
d87eb127 | 1386 | |
be926fc4 AV |
1387 | netif_device_attach(ndev); |
1388 | ||
46ceb60c | 1389 | enable_napi(priv); |
be926fc4 AV |
1390 | |
1391 | return 0; | |
1392 | } | |
1393 | ||
1394 | static int gfar_restore(struct device *dev) | |
1395 | { | |
1396 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1397 | struct net_device *ndev = priv->ndev; | |
1398 | ||
103cdd1d WD |
1399 | if (!netif_running(ndev)) { |
1400 | netif_device_attach(ndev); | |
1401 | ||
be926fc4 | 1402 | return 0; |
103cdd1d | 1403 | } |
be926fc4 | 1404 | |
1eb8f7a7 CM |
1405 | if (gfar_init_bds(ndev)) { |
1406 | free_skb_resources(priv); | |
1407 | return -ENOMEM; | |
1408 | } | |
1409 | ||
be926fc4 AV |
1410 | init_registers(ndev); |
1411 | gfar_set_mac_address(ndev); | |
1412 | gfar_init_mac(ndev); | |
1413 | gfar_start(ndev); | |
1414 | ||
1415 | priv->oldlink = 0; | |
1416 | priv->oldspeed = 0; | |
1417 | priv->oldduplex = -1; | |
1418 | ||
1419 | if (priv->phydev) | |
1420 | phy_start(priv->phydev); | |
d87eb127 | 1421 | |
be926fc4 | 1422 | netif_device_attach(ndev); |
5ea681d4 | 1423 | enable_napi(priv); |
d87eb127 SW |
1424 | |
1425 | return 0; | |
1426 | } | |
be926fc4 AV |
1427 | |
1428 | static struct dev_pm_ops gfar_pm_ops = { | |
1429 | .suspend = gfar_suspend, | |
1430 | .resume = gfar_resume, | |
1431 | .freeze = gfar_suspend, | |
1432 | .thaw = gfar_resume, | |
1433 | .restore = gfar_restore, | |
1434 | }; | |
1435 | ||
1436 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1437 | ||
d87eb127 | 1438 | #else |
be926fc4 AV |
1439 | |
1440 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1441 | |
d87eb127 | 1442 | #endif |
1da177e4 | 1443 | |
e8a2b6a4 AF |
1444 | /* Reads the controller's registers to determine what interface |
1445 | * connects it to the PHY. | |
1446 | */ | |
1447 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1448 | { | |
1449 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1450 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1451 | u32 ecntrl; |
1452 | ||
f4983704 | 1453 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1454 | |
1455 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1456 | return PHY_INTERFACE_MODE_SGMII; | |
1457 | ||
1458 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1459 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1460 | return PHY_INTERFACE_MODE_RTBI; | |
1461 | else | |
1462 | return PHY_INTERFACE_MODE_TBI; | |
1463 | } | |
1464 | ||
1465 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
bc4598bc | 1466 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) { |
e8a2b6a4 | 1467 | return PHY_INTERFACE_MODE_RMII; |
bc4598bc | 1468 | } |
7132ab7f | 1469 | else { |
b31a1d8b | 1470 | phy_interface_t interface = priv->interface; |
7132ab7f | 1471 | |
0977f817 | 1472 | /* This isn't autodetected right now, so it must |
7132ab7f AF |
1473 | * be set by the device tree or platform code. |
1474 | */ | |
1475 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1476 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1477 | ||
e8a2b6a4 | 1478 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1479 | } |
e8a2b6a4 AF |
1480 | } |
1481 | ||
b31a1d8b | 1482 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1483 | return PHY_INTERFACE_MODE_GMII; |
1484 | ||
1485 | return PHY_INTERFACE_MODE_MII; | |
1486 | } | |
1487 | ||
1488 | ||
bb40dcbb AF |
1489 | /* Initializes driver's PHY state, and attaches to the PHY. |
1490 | * Returns 0 on success. | |
1da177e4 LT |
1491 | */ |
1492 | static int init_phy(struct net_device *dev) | |
1493 | { | |
1494 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1495 | uint gigabit_support = |
b31a1d8b | 1496 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
23402bdd | 1497 | GFAR_SUPPORTED_GBIT : 0; |
e8a2b6a4 | 1498 | phy_interface_t interface; |
1da177e4 LT |
1499 | |
1500 | priv->oldlink = 0; | |
1501 | priv->oldspeed = 0; | |
1502 | priv->oldduplex = -1; | |
1503 | ||
e8a2b6a4 AF |
1504 | interface = gfar_get_interface(dev); |
1505 | ||
1db780f8 AV |
1506 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1507 | interface); | |
1508 | if (!priv->phydev) | |
1509 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1510 | interface); | |
1511 | if (!priv->phydev) { | |
1512 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1513 | return -ENODEV; | |
fe192a49 | 1514 | } |
1da177e4 | 1515 | |
d3c12873 KJ |
1516 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1517 | gfar_configure_serdes(dev); | |
1518 | ||
bb40dcbb | 1519 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1520 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1521 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1522 | |
1523 | return 0; | |
1da177e4 LT |
1524 | } |
1525 | ||
0977f817 | 1526 | /* Initialize TBI PHY interface for communicating with the |
d0313587 PG |
1527 | * SERDES lynx PHY on the chip. We communicate with this PHY |
1528 | * through the MDIO bus on each controller, treating it as a | |
1529 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1530 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1531 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1532 | * value doesn't matter, as there are no other PHYs on the bus. | |
1533 | */ | |
d3c12873 KJ |
1534 | static void gfar_configure_serdes(struct net_device *dev) |
1535 | { | |
1536 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1537 | struct phy_device *tbiphy; |
1538 | ||
1539 | if (!priv->tbi_node) { | |
1540 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1541 | "device tree specify a tbi-handle\n"); | |
1542 | return; | |
1543 | } | |
c132419e | 1544 | |
fe192a49 GL |
1545 | tbiphy = of_phy_find_device(priv->tbi_node); |
1546 | if (!tbiphy) { | |
1547 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1548 | return; |
1549 | } | |
d3c12873 | 1550 | |
0977f817 | 1551 | /* If the link is already up, we must already be ok, and don't need to |
bdb59f94 TP |
1552 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1553 | * everything for us? Resetting it takes the link down and requires | |
1554 | * several seconds for it to come back. | |
1555 | */ | |
fe192a49 | 1556 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1557 | return; |
d3c12873 | 1558 | |
d0313587 | 1559 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1560 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1561 | |
fe192a49 | 1562 | phy_write(tbiphy, MII_ADVERTISE, |
bc4598bc JC |
1563 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1564 | ADVERTISE_1000XPSE_ASYM); | |
d3c12873 | 1565 | |
bc4598bc JC |
1566 | phy_write(tbiphy, MII_BMCR, |
1567 | BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | | |
1568 | BMCR_SPEED1000); | |
d3c12873 KJ |
1569 | } |
1570 | ||
1da177e4 LT |
1571 | static void init_registers(struct net_device *dev) |
1572 | { | |
1573 | struct gfar_private *priv = netdev_priv(dev); | |
efeddce7 | 1574 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 1575 | |
efeddce7 | 1576 | gfar_ints_disable(priv); |
1da177e4 LT |
1577 | |
1578 | /* Init hash registers to zero */ | |
f4983704 SG |
1579 | gfar_write(®s->igaddr0, 0); |
1580 | gfar_write(®s->igaddr1, 0); | |
1581 | gfar_write(®s->igaddr2, 0); | |
1582 | gfar_write(®s->igaddr3, 0); | |
1583 | gfar_write(®s->igaddr4, 0); | |
1584 | gfar_write(®s->igaddr5, 0); | |
1585 | gfar_write(®s->igaddr6, 0); | |
1586 | gfar_write(®s->igaddr7, 0); | |
1587 | ||
1588 | gfar_write(®s->gaddr0, 0); | |
1589 | gfar_write(®s->gaddr1, 0); | |
1590 | gfar_write(®s->gaddr2, 0); | |
1591 | gfar_write(®s->gaddr3, 0); | |
1592 | gfar_write(®s->gaddr4, 0); | |
1593 | gfar_write(®s->gaddr5, 0); | |
1594 | gfar_write(®s->gaddr6, 0); | |
1595 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1596 | |
1da177e4 | 1597 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1598 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1599 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1600 | |
1601 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1602 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1603 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1604 | } |
1605 | ||
1606 | /* Initialize the max receive buffer length */ | |
f4983704 | 1607 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1608 | |
1da177e4 | 1609 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1610 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1611 | } |
1612 | ||
511d934f AV |
1613 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1614 | { | |
1615 | u32 res; | |
1616 | ||
0977f817 | 1617 | /* Normaly TSEC should not hang on GRS commands, so we should |
511d934f AV |
1618 | * actually wait for IEVENT_GRSC flag. |
1619 | */ | |
ad3660c2 | 1620 | if (!gfar_has_errata(priv, GFAR_ERRATA_A002)) |
511d934f AV |
1621 | return 0; |
1622 | ||
0977f817 | 1623 | /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are |
511d934f AV |
1624 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle |
1625 | * and the Rx can be safely reset. | |
1626 | */ | |
1627 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1628 | res &= 0x7f807f80; | |
1629 | if ((res & 0xffff) == (res >> 16)) | |
1630 | return 1; | |
1631 | ||
1632 | return 0; | |
1633 | } | |
0bbaf069 KG |
1634 | |
1635 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1636 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1637 | { |
1638 | struct gfar_private *priv = netdev_priv(dev); | |
efeddce7 | 1639 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
1640 | u32 tempval; |
1641 | ||
efeddce7 | 1642 | gfar_ints_disable(priv); |
1da177e4 | 1643 | |
1da177e4 | 1644 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1645 | tempval = gfar_read(®s->dmactrl); |
bc4598bc JC |
1646 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != |
1647 | (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1648 | int ret; |
1649 | ||
1da177e4 | 1650 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1651 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1652 | |
511d934f AV |
1653 | do { |
1654 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1655 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1656 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1657 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1658 | ret = __gfar_is_rx_idle(priv); | |
1659 | } while (!ret); | |
1da177e4 | 1660 | } |
d87eb127 | 1661 | } |
d87eb127 SW |
1662 | |
1663 | /* Halt the receive and transmit queues */ | |
1664 | void gfar_halt(struct net_device *dev) | |
1665 | { | |
1666 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1667 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1668 | u32 tempval; |
1da177e4 | 1669 | |
2a54adc3 SW |
1670 | gfar_halt_nodisable(dev); |
1671 | ||
1da177e4 LT |
1672 | /* Disable Rx and Tx */ |
1673 | tempval = gfar_read(®s->maccfg1); | |
1674 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1675 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1676 | } |
1677 | ||
46ceb60c SG |
1678 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1679 | { | |
ee873fda CM |
1680 | free_irq(gfar_irq(grp, TX)->irq, grp); |
1681 | free_irq(gfar_irq(grp, RX)->irq, grp); | |
1682 | free_irq(gfar_irq(grp, ER)->irq, grp); | |
46ceb60c SG |
1683 | } |
1684 | ||
0bbaf069 KG |
1685 | void stop_gfar(struct net_device *dev) |
1686 | { | |
1687 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1688 | unsigned long flags; |
46ceb60c | 1689 | int i; |
0bbaf069 | 1690 | |
bb40dcbb AF |
1691 | phy_stop(priv->phydev); |
1692 | ||
a12f801d | 1693 | |
0bbaf069 | 1694 | /* Lock it down */ |
fba4ed03 SG |
1695 | local_irq_save(flags); |
1696 | lock_tx_qs(priv); | |
1697 | lock_rx_qs(priv); | |
0bbaf069 | 1698 | |
0bbaf069 | 1699 | gfar_halt(dev); |
1da177e4 | 1700 | |
fba4ed03 SG |
1701 | unlock_rx_qs(priv); |
1702 | unlock_tx_qs(priv); | |
1703 | local_irq_restore(flags); | |
1da177e4 LT |
1704 | |
1705 | /* Free the IRQs */ | |
b31a1d8b | 1706 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1707 | for (i = 0; i < priv->num_grps; i++) |
1708 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1709 | } else { |
46ceb60c | 1710 | for (i = 0; i < priv->num_grps; i++) |
ee873fda | 1711 | free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, |
bc4598bc | 1712 | &priv->gfargrp[i]); |
1da177e4 LT |
1713 | } |
1714 | ||
1715 | free_skb_resources(priv); | |
1da177e4 LT |
1716 | } |
1717 | ||
fba4ed03 | 1718 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1719 | { |
1da177e4 | 1720 | struct txbd8 *txbdp; |
fba4ed03 | 1721 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1722 | int i, j; |
1da177e4 | 1723 | |
a12f801d | 1724 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1725 | |
a12f801d SG |
1726 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1727 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1728 | continue; |
1da177e4 | 1729 | |
369ec162 | 1730 | dma_unmap_single(priv->dev, txbdp->bufPtr, |
bc4598bc | 1731 | txbdp->length, DMA_TO_DEVICE); |
4669bc90 | 1732 | txbdp->lstatus = 0; |
fba4ed03 | 1733 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
bc4598bc | 1734 | j++) { |
4669bc90 | 1735 | txbdp++; |
369ec162 | 1736 | dma_unmap_page(priv->dev, txbdp->bufPtr, |
bc4598bc | 1737 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1738 | } |
ad5da7ab | 1739 | txbdp++; |
a12f801d SG |
1740 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1741 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1742 | } |
a12f801d | 1743 | kfree(tx_queue->tx_skbuff); |
1eb8f7a7 | 1744 | tx_queue->tx_skbuff = NULL; |
fba4ed03 | 1745 | } |
1da177e4 | 1746 | |
fba4ed03 SG |
1747 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1748 | { | |
1749 | struct rxbd8 *rxbdp; | |
1750 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1751 | int i; | |
1da177e4 | 1752 | |
fba4ed03 | 1753 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1754 | |
a12f801d SG |
1755 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1756 | if (rx_queue->rx_skbuff[i]) { | |
369ec162 CM |
1757 | dma_unmap_single(priv->dev, rxbdp->bufPtr, |
1758 | priv->rx_buffer_size, | |
bc4598bc | 1759 | DMA_FROM_DEVICE); |
a12f801d SG |
1760 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1761 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1762 | } |
e69edd21 AV |
1763 | rxbdp->lstatus = 0; |
1764 | rxbdp->bufPtr = 0; | |
1765 | rxbdp++; | |
1da177e4 | 1766 | } |
a12f801d | 1767 | kfree(rx_queue->rx_skbuff); |
1eb8f7a7 | 1768 | rx_queue->rx_skbuff = NULL; |
fba4ed03 | 1769 | } |
e69edd21 | 1770 | |
fba4ed03 | 1771 | /* If there are any tx skbs or rx skbs still around, free them. |
0977f817 JC |
1772 | * Then free tx_skbuff and rx_skbuff |
1773 | */ | |
fba4ed03 SG |
1774 | static void free_skb_resources(struct gfar_private *priv) |
1775 | { | |
1776 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1777 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1778 | int i; | |
1779 | ||
1780 | /* Go through all the buffer descriptors and free their data buffers */ | |
1781 | for (i = 0; i < priv->num_tx_queues; i++) { | |
d8a0f1b0 | 1782 | struct netdev_queue *txq; |
bc4598bc | 1783 | |
fba4ed03 | 1784 | tx_queue = priv->tx_queue[i]; |
d8a0f1b0 | 1785 | txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); |
bc4598bc | 1786 | if (tx_queue->tx_skbuff) |
fba4ed03 | 1787 | free_skb_tx_queue(tx_queue); |
d8a0f1b0 | 1788 | netdev_tx_reset_queue(txq); |
fba4ed03 SG |
1789 | } |
1790 | ||
1791 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1792 | rx_queue = priv->rx_queue[i]; | |
bc4598bc | 1793 | if (rx_queue->rx_skbuff) |
fba4ed03 SG |
1794 | free_skb_rx_queue(rx_queue); |
1795 | } | |
1796 | ||
369ec162 | 1797 | dma_free_coherent(priv->dev, |
bc4598bc JC |
1798 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
1799 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1800 | priv->tx_queue[0]->tx_bd_base, | |
1801 | priv->tx_queue[0]->tx_bd_dma_base); | |
1da177e4 LT |
1802 | } |
1803 | ||
0bbaf069 KG |
1804 | void gfar_start(struct net_device *dev) |
1805 | { | |
1806 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1807 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1808 | u32 tempval; |
46ceb60c | 1809 | int i = 0; |
0bbaf069 KG |
1810 | |
1811 | /* Enable Rx and Tx in MACCFG1 */ | |
1812 | tempval = gfar_read(®s->maccfg1); | |
1813 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1814 | gfar_write(®s->maccfg1, tempval); | |
1815 | ||
1816 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1817 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1818 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1819 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1820 | |
0bbaf069 | 1821 | /* Make sure we aren't stopped */ |
f4983704 | 1822 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1823 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1824 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1825 | |
46ceb60c SG |
1826 | for (i = 0; i < priv->num_grps; i++) { |
1827 | regs = priv->gfargrp[i].regs; | |
1828 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1829 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1830 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
46ceb60c | 1831 | } |
12dea57b | 1832 | |
efeddce7 CM |
1833 | gfar_ints_enable(priv); |
1834 | ||
1ae5dc34 | 1835 | dev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1836 | } |
1837 | ||
800c644b | 1838 | static void gfar_configure_coalescing(struct gfar_private *priv, |
bc4598bc | 1839 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1840 | { |
46ceb60c | 1841 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1842 | u32 __iomem *baddr; |
815b97c6 | 1843 | |
46ceb60c | 1844 | if (priv->mode == MQ_MG_MODE) { |
5d9657d8 | 1845 | int i = 0; |
c6e1160e | 1846 | |
46ceb60c | 1847 | baddr = ®s->txic0; |
984b3f57 | 1848 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
9740e001 CM |
1849 | gfar_write(baddr + i, 0); |
1850 | if (likely(priv->tx_queue[i]->txcoalescing)) | |
46ceb60c | 1851 | gfar_write(baddr + i, priv->tx_queue[i]->txic); |
46ceb60c SG |
1852 | } |
1853 | ||
1854 | baddr = ®s->rxic0; | |
984b3f57 | 1855 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
9740e001 CM |
1856 | gfar_write(baddr + i, 0); |
1857 | if (likely(priv->rx_queue[i]->rxcoalescing)) | |
46ceb60c | 1858 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); |
46ceb60c | 1859 | } |
5d9657d8 | 1860 | } else { |
c6e1160e | 1861 | /* Backward compatible case -- even if we enable |
5d9657d8 CM |
1862 | * multiple queues, there's only single reg to program |
1863 | */ | |
1864 | gfar_write(®s->txic, 0); | |
1865 | if (likely(priv->tx_queue[0]->txcoalescing)) | |
1866 | gfar_write(®s->txic, priv->tx_queue[0]->txic); | |
1867 | ||
1868 | gfar_write(®s->rxic, 0); | |
1869 | if (unlikely(priv->rx_queue[0]->rxcoalescing)) | |
1870 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); | |
46ceb60c SG |
1871 | } |
1872 | } | |
1873 | ||
800c644b CM |
1874 | void gfar_configure_coalescing_all(struct gfar_private *priv) |
1875 | { | |
1876 | gfar_configure_coalescing(priv, 0xFF, 0xFF); | |
1877 | } | |
1878 | ||
46ceb60c SG |
1879 | static int register_grp_irqs(struct gfar_priv_grp *grp) |
1880 | { | |
1881 | struct gfar_private *priv = grp->priv; | |
1882 | struct net_device *dev = priv->ndev; | |
1883 | int err; | |
1da177e4 | 1884 | |
1da177e4 | 1885 | /* If the device has multiple interrupts, register for |
0977f817 JC |
1886 | * them. Otherwise, only register for the one |
1887 | */ | |
b31a1d8b | 1888 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1889 | /* Install our interrupt handlers for Error, |
0977f817 JC |
1890 | * Transmit, and Receive |
1891 | */ | |
ee873fda CM |
1892 | err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, |
1893 | gfar_irq(grp, ER)->name, grp); | |
1894 | if (err < 0) { | |
59deab26 | 1895 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1896 | gfar_irq(grp, ER)->irq); |
46ceb60c | 1897 | |
2145f1af | 1898 | goto err_irq_fail; |
1da177e4 | 1899 | } |
ee873fda CM |
1900 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, |
1901 | gfar_irq(grp, TX)->name, grp); | |
1902 | if (err < 0) { | |
59deab26 | 1903 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1904 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1905 | goto tx_irq_fail; |
1906 | } | |
ee873fda CM |
1907 | err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, |
1908 | gfar_irq(grp, RX)->name, grp); | |
1909 | if (err < 0) { | |
59deab26 | 1910 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1911 | gfar_irq(grp, RX)->irq); |
1da177e4 LT |
1912 | goto rx_irq_fail; |
1913 | } | |
1914 | } else { | |
ee873fda CM |
1915 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, |
1916 | gfar_irq(grp, TX)->name, grp); | |
1917 | if (err < 0) { | |
59deab26 | 1918 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1919 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1920 | goto err_irq_fail; |
1921 | } | |
1922 | } | |
1923 | ||
46ceb60c SG |
1924 | return 0; |
1925 | ||
1926 | rx_irq_fail: | |
ee873fda | 1927 | free_irq(gfar_irq(grp, TX)->irq, grp); |
46ceb60c | 1928 | tx_irq_fail: |
ee873fda | 1929 | free_irq(gfar_irq(grp, ER)->irq, grp); |
46ceb60c SG |
1930 | err_irq_fail: |
1931 | return err; | |
1932 | ||
1933 | } | |
1934 | ||
1935 | /* Bring the controller up and running */ | |
1936 | int startup_gfar(struct net_device *ndev) | |
1937 | { | |
1938 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c SG |
1939 | int err, i, j; |
1940 | ||
efeddce7 | 1941 | gfar_ints_disable(priv); |
46ceb60c | 1942 | |
46ceb60c SG |
1943 | err = gfar_alloc_skb_resources(ndev); |
1944 | if (err) | |
1945 | return err; | |
1946 | ||
1947 | gfar_init_mac(ndev); | |
1948 | ||
1949 | for (i = 0; i < priv->num_grps; i++) { | |
1950 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1951 | if (err) { | |
1952 | for (j = 0; j < i; j++) | |
1953 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1954 | goto irq_fail; |
46ceb60c SG |
1955 | } |
1956 | } | |
1957 | ||
7f7f5316 | 1958 | /* Start the controller */ |
ccc05c6e | 1959 | gfar_start(ndev); |
1da177e4 | 1960 | |
826aa4a0 AV |
1961 | phy_start(priv->phydev); |
1962 | ||
800c644b | 1963 | gfar_configure_coalescing_all(priv); |
46ceb60c | 1964 | |
1da177e4 LT |
1965 | return 0; |
1966 | ||
46ceb60c | 1967 | irq_fail: |
e69edd21 | 1968 | free_skb_resources(priv); |
1da177e4 LT |
1969 | return err; |
1970 | } | |
1971 | ||
0977f817 JC |
1972 | /* Called when something needs to use the ethernet device |
1973 | * Returns 0 for success. | |
1974 | */ | |
1da177e4 LT |
1975 | static int gfar_enet_open(struct net_device *dev) |
1976 | { | |
94e8cc35 | 1977 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1978 | int err; |
1979 | ||
46ceb60c | 1980 | enable_napi(priv); |
bea3348e | 1981 | |
1da177e4 LT |
1982 | /* Initialize a bunch of registers */ |
1983 | init_registers(dev); | |
1984 | ||
1985 | gfar_set_mac_address(dev); | |
1986 | ||
1987 | err = init_phy(dev); | |
1988 | ||
a12f801d | 1989 | if (err) { |
46ceb60c | 1990 | disable_napi(priv); |
1da177e4 | 1991 | return err; |
bea3348e | 1992 | } |
1da177e4 LT |
1993 | |
1994 | err = startup_gfar(dev); | |
db0e8e3f | 1995 | if (err) { |
46ceb60c | 1996 | disable_napi(priv); |
db0e8e3f AV |
1997 | return err; |
1998 | } | |
1da177e4 | 1999 | |
fba4ed03 | 2000 | netif_tx_start_all_queues(dev); |
1da177e4 | 2001 | |
2884e5cc AV |
2002 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
2003 | ||
1da177e4 LT |
2004 | return err; |
2005 | } | |
2006 | ||
54dc79fe | 2007 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 2008 | { |
54dc79fe | 2009 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
2010 | |
2011 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 2012 | |
0bbaf069 KG |
2013 | return fcb; |
2014 | } | |
2015 | ||
9c4886e5 | 2016 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, |
bc4598bc | 2017 | int fcb_length) |
0bbaf069 | 2018 | { |
0bbaf069 KG |
2019 | /* If we're here, it's a IP packet with a TCP or UDP |
2020 | * payload. We set it to checksum, using a pseudo-header | |
2021 | * we provide | |
2022 | */ | |
3a2e16c8 | 2023 | u8 flags = TXFCB_DEFAULT; |
0bbaf069 | 2024 | |
0977f817 JC |
2025 | /* Tell the controller what the protocol is |
2026 | * And provide the already calculated phcs | |
2027 | */ | |
eddc9ec5 | 2028 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 2029 | flags |= TXFCB_UDP; |
4bedb452 | 2030 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 2031 | } else |
8da32de5 | 2032 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
2033 | |
2034 | /* l3os is the distance between the start of the | |
2035 | * frame (skb->data) and the start of the IP hdr. | |
2036 | * l4os is the distance between the start of the | |
0977f817 JC |
2037 | * l3 hdr and the l4 hdr |
2038 | */ | |
9c4886e5 | 2039 | fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); |
cfe1fc77 | 2040 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 2041 | |
7f7f5316 | 2042 | fcb->flags = flags; |
0bbaf069 KG |
2043 | } |
2044 | ||
7f7f5316 | 2045 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 2046 | { |
7f7f5316 | 2047 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2048 | fcb->vlctl = vlan_tx_tag_get(skb); |
2049 | } | |
2050 | ||
4669bc90 | 2051 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
bc4598bc | 2052 | struct txbd8 *base, int ring_size) |
4669bc90 DH |
2053 | { |
2054 | struct txbd8 *new_bd = bdp + stride; | |
2055 | ||
2056 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2057 | } | |
2058 | ||
2059 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
bc4598bc | 2060 | int ring_size) |
4669bc90 DH |
2061 | { |
2062 | return skip_txbd(bdp, 1, base, ring_size); | |
2063 | } | |
2064 | ||
02d88fb4 CM |
2065 | /* eTSEC12: csum generation not supported for some fcb offsets */ |
2066 | static inline bool gfar_csum_errata_12(struct gfar_private *priv, | |
2067 | unsigned long fcb_addr) | |
2068 | { | |
2069 | return (gfar_has_errata(priv, GFAR_ERRATA_12) && | |
2070 | (fcb_addr % 0x20) > 0x18); | |
2071 | } | |
2072 | ||
2073 | /* eTSEC76: csum generation for frames larger than 2500 may | |
2074 | * cause excess delays before start of transmission | |
2075 | */ | |
2076 | static inline bool gfar_csum_errata_76(struct gfar_private *priv, | |
2077 | unsigned int len) | |
2078 | { | |
2079 | return (gfar_has_errata(priv, GFAR_ERRATA_76) && | |
2080 | (len > 2500)); | |
2081 | } | |
2082 | ||
0977f817 JC |
2083 | /* This is called by the kernel when a frame is ready for transmission. |
2084 | * It is pointed to by the dev->hard_start_xmit function pointer | |
2085 | */ | |
1da177e4 LT |
2086 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2087 | { | |
2088 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2089 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2090 | struct netdev_queue *txq; |
f4983704 | 2091 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2092 | struct txfcb *fcb = NULL; |
f0ee7acf | 2093 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2094 | u32 lstatus; |
0d0cffdc CM |
2095 | int i, rq = 0; |
2096 | int do_tstamp, do_csum, do_vlan; | |
4669bc90 | 2097 | u32 bufaddr; |
fef6108d | 2098 | unsigned long flags; |
50ad076b | 2099 | unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0; |
fba4ed03 SG |
2100 | |
2101 | rq = skb->queue_mapping; | |
2102 | tx_queue = priv->tx_queue[rq]; | |
2103 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2104 | base = tx_queue->tx_bd_base; |
46ceb60c | 2105 | regs = tx_queue->grp->regs; |
f0ee7acf | 2106 | |
0d0cffdc CM |
2107 | do_csum = (CHECKSUM_PARTIAL == skb->ip_summed); |
2108 | do_vlan = vlan_tx_tag_present(skb); | |
2109 | do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && | |
2110 | priv->hwts_tx_en; | |
2111 | ||
2112 | if (do_csum || do_vlan) | |
2113 | fcb_len = GMAC_FCB_LEN; | |
2114 | ||
f0ee7acf | 2115 | /* check if time stamp should be generated */ |
0d0cffdc CM |
2116 | if (unlikely(do_tstamp)) |
2117 | fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN; | |
4669bc90 | 2118 | |
5b28beaf | 2119 | /* make space for additional header when fcb is needed */ |
0d0cffdc | 2120 | if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) { |
54dc79fe SH |
2121 | struct sk_buff *skb_new; |
2122 | ||
0d0cffdc | 2123 | skb_new = skb_realloc_headroom(skb, fcb_len); |
54dc79fe SH |
2124 | if (!skb_new) { |
2125 | dev->stats.tx_errors++; | |
bd14ba84 | 2126 | kfree_skb(skb); |
54dc79fe SH |
2127 | return NETDEV_TX_OK; |
2128 | } | |
db83d136 | 2129 | |
313b037c ED |
2130 | if (skb->sk) |
2131 | skb_set_owner_w(skb_new, skb->sk); | |
2132 | consume_skb(skb); | |
54dc79fe SH |
2133 | skb = skb_new; |
2134 | } | |
2135 | ||
4669bc90 DH |
2136 | /* total number of fragments in the SKB */ |
2137 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2138 | ||
f0ee7acf MR |
2139 | /* calculate the required number of TxBDs for this skb */ |
2140 | if (unlikely(do_tstamp)) | |
2141 | nr_txbds = nr_frags + 2; | |
2142 | else | |
2143 | nr_txbds = nr_frags + 1; | |
2144 | ||
4669bc90 | 2145 | /* check if there is space to queue this packet */ |
f0ee7acf | 2146 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2147 | /* no space, stop the queue */ |
fba4ed03 | 2148 | netif_tx_stop_queue(txq); |
4669bc90 | 2149 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2150 | return NETDEV_TX_BUSY; |
2151 | } | |
1da177e4 LT |
2152 | |
2153 | /* Update transmit stats */ | |
50ad076b CM |
2154 | bytes_sent = skb->len; |
2155 | tx_queue->stats.tx_bytes += bytes_sent; | |
2156 | /* keep Tx bytes on wire for BQL accounting */ | |
2157 | GFAR_CB(skb)->bytes_sent = bytes_sent; | |
1ac9ad13 | 2158 | tx_queue->stats.tx_packets++; |
1da177e4 | 2159 | |
a12f801d | 2160 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2161 | lstatus = txbdp->lstatus; |
2162 | ||
2163 | /* Time stamp insertion requires one additional TxBD */ | |
2164 | if (unlikely(do_tstamp)) | |
2165 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
bc4598bc | 2166 | tx_queue->tx_ring_size); |
1da177e4 | 2167 | |
4669bc90 | 2168 | if (nr_frags == 0) { |
f0ee7acf MR |
2169 | if (unlikely(do_tstamp)) |
2170 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
bc4598bc | 2171 | TXBD_INTERRUPT); |
f0ee7acf MR |
2172 | else |
2173 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2174 | } else { |
2175 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2176 | for (i = 0; i < nr_frags; i++) { | |
50ad076b | 2177 | unsigned int frag_len; |
4669bc90 | 2178 | /* Point at the next BD, wrapping as needed */ |
a12f801d | 2179 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 | 2180 | |
50ad076b | 2181 | frag_len = skb_shinfo(skb)->frags[i].size; |
4669bc90 | 2182 | |
50ad076b | 2183 | lstatus = txbdp->lstatus | frag_len | |
bc4598bc | 2184 | BD_LFLAG(TXBD_READY); |
4669bc90 DH |
2185 | |
2186 | /* Handle the last BD specially */ | |
2187 | if (i == nr_frags - 1) | |
2188 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2189 | |
369ec162 | 2190 | bufaddr = skb_frag_dma_map(priv->dev, |
2234a722 IC |
2191 | &skb_shinfo(skb)->frags[i], |
2192 | 0, | |
50ad076b | 2193 | frag_len, |
2234a722 | 2194 | DMA_TO_DEVICE); |
4669bc90 DH |
2195 | |
2196 | /* set the TxBD length and buffer pointer */ | |
2197 | txbdp->bufPtr = bufaddr; | |
2198 | txbdp->lstatus = lstatus; | |
2199 | } | |
2200 | ||
2201 | lstatus = txbdp_start->lstatus; | |
2202 | } | |
1da177e4 | 2203 | |
9c4886e5 MR |
2204 | /* Add TxPAL between FCB and frame if required */ |
2205 | if (unlikely(do_tstamp)) { | |
2206 | skb_push(skb, GMAC_TXPAL_LEN); | |
2207 | memset(skb->data, 0, GMAC_TXPAL_LEN); | |
2208 | } | |
2209 | ||
0d0cffdc CM |
2210 | /* Add TxFCB if required */ |
2211 | if (fcb_len) { | |
54dc79fe | 2212 | fcb = gfar_add_fcb(skb); |
02d88fb4 | 2213 | lstatus |= BD_LFLAG(TXBD_TOE); |
0d0cffdc CM |
2214 | } |
2215 | ||
2216 | /* Set up checksumming */ | |
2217 | if (do_csum) { | |
2218 | gfar_tx_checksum(skb, fcb, fcb_len); | |
02d88fb4 CM |
2219 | |
2220 | if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) || | |
2221 | unlikely(gfar_csum_errata_76(priv, skb->len))) { | |
4363c2fd AD |
2222 | __skb_pull(skb, GMAC_FCB_LEN); |
2223 | skb_checksum_help(skb); | |
0d0cffdc CM |
2224 | if (do_vlan || do_tstamp) { |
2225 | /* put back a new fcb for vlan/tstamp TOE */ | |
2226 | fcb = gfar_add_fcb(skb); | |
2227 | } else { | |
2228 | /* Tx TOE not used */ | |
2229 | lstatus &= ~(BD_LFLAG(TXBD_TOE)); | |
2230 | fcb = NULL; | |
2231 | } | |
4363c2fd | 2232 | } |
0bbaf069 KG |
2233 | } |
2234 | ||
0d0cffdc | 2235 | if (do_vlan) |
54dc79fe | 2236 | gfar_tx_vlan(skb, fcb); |
0bbaf069 | 2237 | |
f0ee7acf MR |
2238 | /* Setup tx hardware time stamping if requested */ |
2239 | if (unlikely(do_tstamp)) { | |
2244d07b | 2240 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf | 2241 | fcb->ptp = 1; |
f0ee7acf MR |
2242 | } |
2243 | ||
369ec162 | 2244 | txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data, |
bc4598bc | 2245 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2246 | |
0977f817 | 2247 | /* If time stamping is requested one additional TxBD must be set up. The |
f0ee7acf MR |
2248 | * first TxBD points to the FCB and must have a data length of |
2249 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2250 | * the full frame length. | |
2251 | */ | |
2252 | if (unlikely(do_tstamp)) { | |
0d0cffdc | 2253 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len; |
f0ee7acf | 2254 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | |
0d0cffdc | 2255 | (skb_headlen(skb) - fcb_len); |
f0ee7acf MR |
2256 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; |
2257 | } else { | |
2258 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2259 | } | |
1da177e4 | 2260 | |
50ad076b | 2261 | netdev_tx_sent_queue(txq, bytes_sent); |
d8a0f1b0 | 2262 | |
0977f817 | 2263 | /* We can work in parallel with gfar_clean_tx_ring(), except |
a3bc1f11 AV |
2264 | * when modifying num_txbdfree. Note that we didn't grab the lock |
2265 | * when we were reading the num_txbdfree and checking for available | |
2266 | * space, that's because outside of this function it can only grow, | |
2267 | * and once we've got needed space, it cannot suddenly disappear. | |
2268 | * | |
2269 | * The lock also protects us from gfar_error(), which can modify | |
2270 | * regs->tstat and thus retrigger the transfers, which is why we | |
2271 | * also must grab the lock before setting ready bit for the first | |
2272 | * to be transmitted BD. | |
2273 | */ | |
2274 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2275 | ||
0977f817 | 2276 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
3b6330ce SW |
2277 | * semantics (it requires synchronization between cacheable and |
2278 | * uncacheable mappings, which eieio doesn't provide and which we | |
2279 | * don't need), thus requiring a more expensive sync instruction. At | |
2280 | * some point, the set of architecture-independent barrier functions | |
2281 | * should be expanded to include weaker barriers. | |
2282 | */ | |
3b6330ce | 2283 | eieio(); |
7f7f5316 | 2284 | |
4669bc90 DH |
2285 | txbdp_start->lstatus = lstatus; |
2286 | ||
0eddba52 AV |
2287 | eieio(); /* force lstatus write before tx_skbuff */ |
2288 | ||
2289 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2290 | ||
4669bc90 | 2291 | /* Update the current skb pointer to the next entry we will use |
0977f817 JC |
2292 | * (wrapping if necessary) |
2293 | */ | |
a12f801d | 2294 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
bc4598bc | 2295 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); |
4669bc90 | 2296 | |
a12f801d | 2297 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2298 | |
2299 | /* reduce TxBD free count */ | |
f0ee7acf | 2300 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2301 | |
2302 | /* If the next BD still needs to be cleaned up, then the bds | |
0977f817 JC |
2303 | * are full. We need to tell the kernel to stop sending us stuff. |
2304 | */ | |
a12f801d | 2305 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2306 | netif_tx_stop_queue(txq); |
1da177e4 | 2307 | |
09f75cd7 | 2308 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2309 | } |
2310 | ||
1da177e4 | 2311 | /* Tell the DMA to go go go */ |
fba4ed03 | 2312 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2313 | |
2314 | /* Unlock priv */ | |
a12f801d | 2315 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2316 | |
54dc79fe | 2317 | return NETDEV_TX_OK; |
1da177e4 LT |
2318 | } |
2319 | ||
2320 | /* Stops the kernel queue, and halts the controller */ | |
2321 | static int gfar_close(struct net_device *dev) | |
2322 | { | |
2323 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2324 | |
46ceb60c | 2325 | disable_napi(priv); |
bea3348e | 2326 | |
ab939905 | 2327 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2328 | stop_gfar(dev); |
2329 | ||
bb40dcbb AF |
2330 | /* Disconnect from the PHY */ |
2331 | phy_disconnect(priv->phydev); | |
2332 | priv->phydev = NULL; | |
1da177e4 | 2333 | |
fba4ed03 | 2334 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2335 | |
2336 | return 0; | |
2337 | } | |
2338 | ||
1da177e4 | 2339 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2340 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2341 | { |
7f7f5316 | 2342 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2343 | |
2344 | return 0; | |
2345 | } | |
2346 | ||
f3dc1586 SP |
2347 | /* Check if rx parser should be activated */ |
2348 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2349 | { | |
2350 | struct gfar __iomem *regs; | |
2351 | u32 tempval; | |
2352 | ||
2353 | regs = priv->gfargrp[0].regs; | |
2354 | ||
2355 | tempval = gfar_read(®s->rctrl); | |
2356 | /* If parse is no longer required, then disable parser */ | |
ba779711 | 2357 | if (tempval & RCTRL_REQ_PARSER) { |
f3dc1586 | 2358 | tempval |= RCTRL_PRSDEP_INIT; |
ba779711 CM |
2359 | priv->uses_rxfcb = 1; |
2360 | } else { | |
f3dc1586 | 2361 | tempval &= ~RCTRL_PRSDEP_INIT; |
ba779711 CM |
2362 | priv->uses_rxfcb = 0; |
2363 | } | |
f3dc1586 SP |
2364 | gfar_write(®s->rctrl, tempval); |
2365 | } | |
2366 | ||
0bbaf069 | 2367 | /* Enables and disables VLAN insertion/extraction */ |
c8f44aff | 2368 | void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) |
0bbaf069 KG |
2369 | { |
2370 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2371 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2372 | unsigned long flags; |
2373 | u32 tempval; | |
2374 | ||
46ceb60c | 2375 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2376 | local_irq_save(flags); |
2377 | lock_rx_qs(priv); | |
0bbaf069 | 2378 | |
f646968f | 2379 | if (features & NETIF_F_HW_VLAN_CTAG_TX) { |
0bbaf069 | 2380 | /* Enable VLAN tag insertion */ |
f4983704 | 2381 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2382 | tempval |= TCTRL_VLINS; |
f4983704 | 2383 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2384 | } else { |
2385 | /* Disable VLAN tag insertion */ | |
f4983704 | 2386 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2387 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2388 | gfar_write(®s->tctrl, tempval); |
87c288c6 | 2389 | } |
0bbaf069 | 2390 | |
f646968f | 2391 | if (features & NETIF_F_HW_VLAN_CTAG_RX) { |
87c288c6 JP |
2392 | /* Enable VLAN tag extraction */ |
2393 | tempval = gfar_read(®s->rctrl); | |
2394 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); | |
2395 | gfar_write(®s->rctrl, tempval); | |
ba779711 | 2396 | priv->uses_rxfcb = 1; |
87c288c6 | 2397 | } else { |
0bbaf069 | 2398 | /* Disable VLAN tag extraction */ |
f4983704 | 2399 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2400 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2401 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2402 | |
2403 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2404 | } |
2405 | ||
77ecaf2d DH |
2406 | gfar_change_mtu(dev, dev->mtu); |
2407 | ||
fba4ed03 SG |
2408 | unlock_rx_qs(priv); |
2409 | local_irq_restore(flags); | |
0bbaf069 KG |
2410 | } |
2411 | ||
1da177e4 LT |
2412 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2413 | { | |
2414 | int tempsize, tempval; | |
2415 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2416 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2417 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2418 | int frame_size = new_mtu + ETH_HLEN; |
2419 | ||
1da177e4 | 2420 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
59deab26 | 2421 | netif_err(priv, drv, dev, "Invalid MTU setting\n"); |
1da177e4 LT |
2422 | return -EINVAL; |
2423 | } | |
2424 | ||
ba779711 | 2425 | if (priv->uses_rxfcb) |
77ecaf2d DH |
2426 | frame_size += GMAC_FCB_LEN; |
2427 | ||
2428 | frame_size += priv->padding; | |
2429 | ||
bc4598bc JC |
2430 | tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + |
2431 | INCREMENTAL_BUFFER_SIZE; | |
1da177e4 LT |
2432 | |
2433 | /* Only stop and start the controller if it isn't already | |
0977f817 JC |
2434 | * stopped, and we changed something |
2435 | */ | |
1da177e4 LT |
2436 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2437 | stop_gfar(dev); | |
2438 | ||
2439 | priv->rx_buffer_size = tempsize; | |
2440 | ||
2441 | dev->mtu = new_mtu; | |
2442 | ||
f4983704 SG |
2443 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2444 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2445 | |
2446 | /* If the mtu is larger than the max size for standard | |
2447 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
0977f817 JC |
2448 | * to allow huge frames, and to check the length |
2449 | */ | |
f4983704 | 2450 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2451 | |
7d350977 | 2452 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
bc4598bc | 2453 | gfar_has_errata(priv, GFAR_ERRATA_74)) |
1da177e4 LT |
2454 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2455 | else | |
2456 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2457 | ||
f4983704 | 2458 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2459 | |
2460 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2461 | startup_gfar(dev); | |
2462 | ||
2463 | return 0; | |
2464 | } | |
2465 | ||
ab939905 | 2466 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2467 | * transmitted after a set amount of time. |
2468 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2469 | * starting over will fix the problem. |
2470 | */ | |
2471 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2472 | { |
ab939905 | 2473 | struct gfar_private *priv = container_of(work, struct gfar_private, |
bc4598bc | 2474 | reset_task); |
4826857f | 2475 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2476 | |
2477 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2478 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2479 | stop_gfar(dev); |
2480 | startup_gfar(dev); | |
fba4ed03 | 2481 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2482 | } |
2483 | ||
263ba320 | 2484 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2485 | } |
2486 | ||
ab939905 SS |
2487 | static void gfar_timeout(struct net_device *dev) |
2488 | { | |
2489 | struct gfar_private *priv = netdev_priv(dev); | |
2490 | ||
2491 | dev->stats.tx_errors++; | |
2492 | schedule_work(&priv->reset_task); | |
2493 | } | |
2494 | ||
acbc0f03 EL |
2495 | static void gfar_align_skb(struct sk_buff *skb) |
2496 | { | |
2497 | /* We need the data buffer to be aligned properly. We will reserve | |
2498 | * as many bytes as needed to align the data properly | |
2499 | */ | |
2500 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
bc4598bc | 2501 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); |
acbc0f03 EL |
2502 | } |
2503 | ||
1da177e4 | 2504 | /* Interrupt Handler for Transmit complete */ |
c233cf40 | 2505 | static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2506 | { |
a12f801d | 2507 | struct net_device *dev = tx_queue->dev; |
d8a0f1b0 | 2508 | struct netdev_queue *txq; |
d080cd63 | 2509 | struct gfar_private *priv = netdev_priv(dev); |
f0ee7acf | 2510 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2511 | struct txbd8 *lbdp = NULL; |
a12f801d | 2512 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2513 | struct sk_buff *skb; |
2514 | int skb_dirtytx; | |
a12f801d | 2515 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2516 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2517 | int i; |
d080cd63 | 2518 | int howmany = 0; |
d8a0f1b0 PG |
2519 | int tqi = tx_queue->qindex; |
2520 | unsigned int bytes_sent = 0; | |
4669bc90 | 2521 | u32 lstatus; |
f0ee7acf | 2522 | size_t buflen; |
1da177e4 | 2523 | |
d8a0f1b0 | 2524 | txq = netdev_get_tx_queue(dev, tqi); |
a12f801d SG |
2525 | bdp = tx_queue->dirty_tx; |
2526 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2527 | |
a12f801d | 2528 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2529 | unsigned long flags; |
2530 | ||
4669bc90 | 2531 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf | 2532 | |
0977f817 | 2533 | /* When time stamping, one additional TxBD must be freed. |
f0ee7acf MR |
2534 | * Also, we need to dma_unmap_single() the TxPAL. |
2535 | */ | |
2244d07b | 2536 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2537 | nr_txbds = frags + 2; |
2538 | else | |
2539 | nr_txbds = frags + 1; | |
2540 | ||
2541 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2542 | |
4669bc90 | 2543 | lstatus = lbdp->lstatus; |
1da177e4 | 2544 | |
4669bc90 DH |
2545 | /* Only clean completed frames */ |
2546 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
bc4598bc | 2547 | (lstatus & BD_LENGTH_MASK)) |
4669bc90 DH |
2548 | break; |
2549 | ||
2244d07b | 2550 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf | 2551 | next = next_txbd(bdp, base, tx_ring_size); |
9c4886e5 | 2552 | buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
f0ee7acf MR |
2553 | } else |
2554 | buflen = bdp->length; | |
2555 | ||
369ec162 | 2556 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2557 | buflen, DMA_TO_DEVICE); |
f0ee7acf | 2558 | |
2244d07b | 2559 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2560 | struct skb_shared_hwtstamps shhwtstamps; |
2561 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
bc4598bc | 2562 | |
f0ee7acf MR |
2563 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
2564 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
9c4886e5 | 2565 | skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); |
f0ee7acf MR |
2566 | skb_tstamp_tx(skb, &shhwtstamps); |
2567 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2568 | bdp = next; | |
2569 | } | |
81183059 | 2570 | |
4669bc90 DH |
2571 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2572 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2573 | |
4669bc90 | 2574 | for (i = 0; i < frags; i++) { |
369ec162 | 2575 | dma_unmap_page(priv->dev, bdp->bufPtr, |
bc4598bc | 2576 | bdp->length, DMA_TO_DEVICE); |
4669bc90 DH |
2577 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2578 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2579 | } | |
1da177e4 | 2580 | |
50ad076b | 2581 | bytes_sent += GFAR_CB(skb)->bytes_sent; |
d8a0f1b0 | 2582 | |
acb600de | 2583 | dev_kfree_skb_any(skb); |
0fd56bb5 | 2584 | |
a12f801d | 2585 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2586 | |
4669bc90 | 2587 | skb_dirtytx = (skb_dirtytx + 1) & |
bc4598bc | 2588 | TX_RING_MOD_MASK(tx_ring_size); |
4669bc90 DH |
2589 | |
2590 | howmany++; | |
a3bc1f11 | 2591 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2592 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2593 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2594 | } |
1da177e4 | 2595 | |
4669bc90 | 2596 | /* If we freed a buffer, we can restart transmission, if necessary */ |
5407b14c | 2597 | if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) |
d8a0f1b0 | 2598 | netif_wake_subqueue(dev, tqi); |
1da177e4 | 2599 | |
4669bc90 | 2600 | /* Update dirty indicators */ |
a12f801d SG |
2601 | tx_queue->skb_dirtytx = skb_dirtytx; |
2602 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2603 | |
d8a0f1b0 | 2604 | netdev_tx_completed_queue(txq, howmany, bytes_sent); |
d080cd63 DH |
2605 | } |
2606 | ||
f4983704 | 2607 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2608 | { |
a6d0b91a AV |
2609 | unsigned long flags; |
2610 | ||
fba4ed03 SG |
2611 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2612 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2613 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2614 | __napi_schedule(&gfargrp->napi); |
8707bdd4 | 2615 | } else { |
0977f817 | 2616 | /* Clear IEVENT, so interrupts aren't called again |
8707bdd4 JP |
2617 | * because of the packets that have already arrived. |
2618 | */ | |
f4983704 | 2619 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2620 | } |
fba4ed03 | 2621 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2622 | |
8c7396ae | 2623 | } |
1da177e4 | 2624 | |
8c7396ae | 2625 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2626 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2627 | { |
f4983704 | 2628 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2629 | return IRQ_HANDLED; |
2630 | } | |
2631 | ||
a12f801d | 2632 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 2633 | struct sk_buff *skb) |
815b97c6 | 2634 | { |
a12f801d | 2635 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2636 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2637 | dma_addr_t buf; |
815b97c6 | 2638 | |
369ec162 | 2639 | buf = dma_map_single(priv->dev, skb->data, |
8a102fe0 | 2640 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
a12f801d | 2641 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2642 | } |
2643 | ||
2281a0f3 | 2644 | static struct sk_buff *gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2645 | { |
2646 | struct gfar_private *priv = netdev_priv(dev); | |
acb600de | 2647 | struct sk_buff *skb; |
1da177e4 | 2648 | |
acbc0f03 | 2649 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2650 | if (!skb) |
1da177e4 LT |
2651 | return NULL; |
2652 | ||
acbc0f03 | 2653 | gfar_align_skb(skb); |
7f7f5316 | 2654 | |
acbc0f03 EL |
2655 | return skb; |
2656 | } | |
2657 | ||
2281a0f3 | 2658 | struct sk_buff *gfar_new_skb(struct net_device *dev) |
acbc0f03 | 2659 | { |
acb600de | 2660 | return gfar_alloc_skb(dev); |
1da177e4 LT |
2661 | } |
2662 | ||
298e1a9e | 2663 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2664 | { |
298e1a9e | 2665 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2666 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2667 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2668 | ||
0977f817 | 2669 | /* If the packet was truncated, none of the other errors matter */ |
1da177e4 LT |
2670 | if (status & RXBD_TRUNCATED) { |
2671 | stats->rx_length_errors++; | |
2672 | ||
212079df | 2673 | atomic64_inc(&estats->rx_trunc); |
1da177e4 LT |
2674 | |
2675 | return; | |
2676 | } | |
2677 | /* Count the errors, if there were any */ | |
2678 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2679 | stats->rx_length_errors++; | |
2680 | ||
2681 | if (status & RXBD_LARGE) | |
212079df | 2682 | atomic64_inc(&estats->rx_large); |
1da177e4 | 2683 | else |
212079df | 2684 | atomic64_inc(&estats->rx_short); |
1da177e4 LT |
2685 | } |
2686 | if (status & RXBD_NONOCTET) { | |
2687 | stats->rx_frame_errors++; | |
212079df | 2688 | atomic64_inc(&estats->rx_nonoctet); |
1da177e4 LT |
2689 | } |
2690 | if (status & RXBD_CRCERR) { | |
212079df | 2691 | atomic64_inc(&estats->rx_crcerr); |
1da177e4 LT |
2692 | stats->rx_crc_errors++; |
2693 | } | |
2694 | if (status & RXBD_OVERRUN) { | |
212079df | 2695 | atomic64_inc(&estats->rx_overrun); |
1da177e4 LT |
2696 | stats->rx_crc_errors++; |
2697 | } | |
2698 | } | |
2699 | ||
f4983704 | 2700 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2701 | { |
f4983704 | 2702 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2703 | return IRQ_HANDLED; |
2704 | } | |
2705 | ||
0bbaf069 KG |
2706 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2707 | { | |
2708 | /* If valid headers were found, and valid sums | |
2709 | * were verified, then we tell the kernel that no | |
0977f817 JC |
2710 | * checksumming is necessary. Otherwise, it is [FIXME] |
2711 | */ | |
7f7f5316 | 2712 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2713 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2714 | else | |
bc8acf2c | 2715 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2716 | } |
2717 | ||
2718 | ||
0977f817 | 2719 | /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ |
61db26c6 CM |
2720 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
2721 | int amount_pull, struct napi_struct *napi) | |
1da177e4 LT |
2722 | { |
2723 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2724 | struct rxfcb *fcb = NULL; |
1da177e4 | 2725 | |
2c2db48a DH |
2726 | /* fcb is at the beginning if exists */ |
2727 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2728 | |
0977f817 JC |
2729 | /* Remove the FCB from the skb |
2730 | * Remove the padded bytes, if there are any | |
2731 | */ | |
f74dac08 SG |
2732 | if (amount_pull) { |
2733 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2734 | skb_pull(skb, amount_pull); |
f74dac08 | 2735 | } |
0bbaf069 | 2736 | |
cc772ab7 MR |
2737 | /* Get receive timestamp from the skb */ |
2738 | if (priv->hwts_rx_en) { | |
2739 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2740 | u64 *ns = (u64 *) skb->data; | |
bc4598bc | 2741 | |
cc772ab7 MR |
2742 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2743 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2744 | } | |
2745 | ||
2746 | if (priv->padding) | |
2747 | skb_pull(skb, priv->padding); | |
2748 | ||
8b3afe95 | 2749 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2750 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2751 | |
2c2db48a DH |
2752 | /* Tell the skb what kind of packet this is */ |
2753 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2754 | |
f646968f | 2755 | /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. |
32f7fd44 JP |
2756 | * Even if vlan rx accel is disabled, on some chips |
2757 | * RXFCB_VLN is pseudo randomly set. | |
2758 | */ | |
f646968f | 2759 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && |
32f7fd44 | 2760 | fcb->flags & RXFCB_VLN) |
e5905c83 | 2761 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl); |
87c288c6 | 2762 | |
2c2db48a | 2763 | /* Send the packet up the stack */ |
953d2768 | 2764 | napi_gro_receive(napi, skb); |
0bbaf069 | 2765 | |
1da177e4 LT |
2766 | } |
2767 | ||
2768 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
2281a0f3 JC |
2769 | * until the budget/quota has been reached. Returns the number |
2770 | * of frames handled | |
1da177e4 | 2771 | */ |
a12f801d | 2772 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2773 | { |
a12f801d | 2774 | struct net_device *dev = rx_queue->dev; |
31de198b | 2775 | struct rxbd8 *bdp, *base; |
1da177e4 | 2776 | struct sk_buff *skb; |
2c2db48a DH |
2777 | int pkt_len; |
2778 | int amount_pull; | |
1da177e4 LT |
2779 | int howmany = 0; |
2780 | struct gfar_private *priv = netdev_priv(dev); | |
2781 | ||
2782 | /* Get the first full descriptor */ | |
a12f801d SG |
2783 | bdp = rx_queue->cur_rx; |
2784 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2785 | |
ba779711 | 2786 | amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0; |
2c2db48a | 2787 | |
1da177e4 | 2788 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2789 | struct sk_buff *newskb; |
bc4598bc | 2790 | |
3b6330ce | 2791 | rmb(); |
815b97c6 AF |
2792 | |
2793 | /* Add another skb for the future */ | |
2794 | newskb = gfar_new_skb(dev); | |
2795 | ||
a12f801d | 2796 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2797 | |
369ec162 | 2798 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2799 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
81183059 | 2800 | |
63b88b90 | 2801 | if (unlikely(!(bdp->status & RXBD_ERR) && |
bc4598bc | 2802 | bdp->length > priv->rx_buffer_size)) |
63b88b90 AV |
2803 | bdp->status = RXBD_LARGE; |
2804 | ||
815b97c6 AF |
2805 | /* We drop the frame if we failed to allocate a new buffer */ |
2806 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
bc4598bc | 2807 | bdp->status & RXBD_ERR)) { |
815b97c6 AF |
2808 | count_errors(bdp->status, dev); |
2809 | ||
2810 | if (unlikely(!newskb)) | |
2811 | newskb = skb; | |
acbc0f03 | 2812 | else if (skb) |
acb600de | 2813 | dev_kfree_skb(skb); |
815b97c6 | 2814 | } else { |
1da177e4 | 2815 | /* Increment the number of packets */ |
a7f38041 | 2816 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2817 | howmany++; |
2818 | ||
2c2db48a DH |
2819 | if (likely(skb)) { |
2820 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2821 | /* Remove the FCS from the packet length */ | |
2822 | skb_put(skb, pkt_len); | |
a7f38041 | 2823 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2824 | skb_record_rx_queue(skb, rx_queue->qindex); |
cd754a57 | 2825 | gfar_process_frame(dev, skb, amount_pull, |
bc4598bc | 2826 | &rx_queue->grp->napi); |
2c2db48a DH |
2827 | |
2828 | } else { | |
59deab26 | 2829 | netif_warn(priv, rx_err, dev, "Missing skb!\n"); |
a7f38041 | 2830 | rx_queue->stats.rx_dropped++; |
212079df | 2831 | atomic64_inc(&priv->extra_stats.rx_skbmissing); |
2c2db48a | 2832 | } |
1da177e4 | 2833 | |
1da177e4 LT |
2834 | } |
2835 | ||
a12f801d | 2836 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2837 | |
815b97c6 | 2838 | /* Setup the new bdp */ |
a12f801d | 2839 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2840 | |
2841 | /* Update to the next pointer */ | |
a12f801d | 2842 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2843 | |
2844 | /* update to point at the next skb */ | |
bc4598bc JC |
2845 | rx_queue->skb_currx = (rx_queue->skb_currx + 1) & |
2846 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2847 | } |
2848 | ||
2849 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2850 | rx_queue->cur_rx = bdp; |
1da177e4 | 2851 | |
1da177e4 LT |
2852 | return howmany; |
2853 | } | |
2854 | ||
5eaedf31 CM |
2855 | static int gfar_poll_sq(struct napi_struct *napi, int budget) |
2856 | { | |
2857 | struct gfar_priv_grp *gfargrp = | |
2858 | container_of(napi, struct gfar_priv_grp, napi); | |
2859 | struct gfar __iomem *regs = gfargrp->regs; | |
2860 | struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0]; | |
2861 | struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0]; | |
2862 | int work_done = 0; | |
2863 | ||
2864 | /* Clear IEVENT, so interrupts aren't called again | |
2865 | * because of the packets that have already arrived | |
2866 | */ | |
2867 | gfar_write(®s->ievent, IEVENT_RTX_MASK); | |
2868 | ||
2869 | /* run Tx cleanup to completion */ | |
2870 | if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) | |
2871 | gfar_clean_tx_ring(tx_queue); | |
2872 | ||
2873 | work_done = gfar_clean_rx_ring(rx_queue, budget); | |
2874 | ||
2875 | if (work_done < budget) { | |
2876 | napi_complete(napi); | |
2877 | /* Clear the halt bit in RSTAT */ | |
2878 | gfar_write(®s->rstat, gfargrp->rstat); | |
2879 | ||
2880 | gfar_write(®s->imask, IMASK_DEFAULT); | |
2881 | ||
2882 | /* If we are coalescing interrupts, update the timer | |
2883 | * Otherwise, clear it | |
2884 | */ | |
2885 | gfar_write(®s->txic, 0); | |
2886 | if (likely(tx_queue->txcoalescing)) | |
2887 | gfar_write(®s->txic, tx_queue->txic); | |
2888 | ||
2889 | gfar_write(®s->rxic, 0); | |
2890 | if (unlikely(rx_queue->rxcoalescing)) | |
2891 | gfar_write(®s->rxic, rx_queue->rxic); | |
2892 | } | |
2893 | ||
2894 | return work_done; | |
2895 | } | |
2896 | ||
bea3348e | 2897 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2898 | { |
bc4598bc JC |
2899 | struct gfar_priv_grp *gfargrp = |
2900 | container_of(napi, struct gfar_priv_grp, napi); | |
fba4ed03 | 2901 | struct gfar_private *priv = gfargrp->priv; |
46ceb60c | 2902 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2903 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2904 | struct gfar_priv_rx_q *rx_queue = NULL; |
c233cf40 | 2905 | int work_done = 0, work_done_per_q = 0; |
39c0a0d5 | 2906 | int i, budget_per_q = 0; |
3ba405db | 2907 | int has_tx_work = 0; |
6be5ed3f CM |
2908 | unsigned long rstat_rxf; |
2909 | int num_act_queues; | |
fba4ed03 | 2910 | |
8c7396ae | 2911 | /* Clear IEVENT, so interrupts aren't called again |
0977f817 JC |
2912 | * because of the packets that have already arrived |
2913 | */ | |
f4983704 | 2914 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2915 | |
6be5ed3f CM |
2916 | rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; |
2917 | ||
2918 | num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); | |
2919 | if (num_act_queues) | |
2920 | budget_per_q = budget/num_act_queues; | |
2921 | ||
3ba405db CM |
2922 | for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { |
2923 | tx_queue = priv->tx_queue[i]; | |
2924 | /* run Tx cleanup to completion */ | |
2925 | if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { | |
2926 | gfar_clean_tx_ring(tx_queue); | |
2927 | has_tx_work = 1; | |
c233cf40 | 2928 | } |
3ba405db | 2929 | } |
fba4ed03 | 2930 | |
3ba405db CM |
2931 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
2932 | /* skip queue if not active */ | |
2933 | if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) | |
2934 | continue; | |
1da177e4 | 2935 | |
3ba405db CM |
2936 | rx_queue = priv->rx_queue[i]; |
2937 | work_done_per_q = | |
2938 | gfar_clean_rx_ring(rx_queue, budget_per_q); | |
2939 | work_done += work_done_per_q; | |
2940 | ||
2941 | /* finished processing this queue */ | |
2942 | if (work_done_per_q < budget_per_q) { | |
2943 | /* clear active queue hw indication */ | |
2944 | gfar_write(®s->rstat, | |
2945 | RSTAT_CLEAR_RXF0 >> i); | |
2946 | num_act_queues--; | |
2947 | ||
2948 | if (!num_act_queues) | |
2949 | break; | |
2950 | } | |
2951 | } | |
42199884 | 2952 | |
3ba405db | 2953 | if (!num_act_queues && !has_tx_work) { |
1da177e4 | 2954 | |
3ba405db | 2955 | napi_complete(napi); |
1da177e4 | 2956 | |
3ba405db CM |
2957 | /* Clear the halt bit in RSTAT */ |
2958 | gfar_write(®s->rstat, gfargrp->rstat); | |
1da177e4 | 2959 | |
3ba405db | 2960 | gfar_write(®s->imask, IMASK_DEFAULT); |
c233cf40 | 2961 | |
3ba405db CM |
2962 | /* If we are coalescing interrupts, update the timer |
2963 | * Otherwise, clear it | |
2964 | */ | |
2965 | gfar_configure_coalescing(priv, gfargrp->rx_bit_map, | |
2966 | gfargrp->tx_bit_map); | |
1da177e4 LT |
2967 | } |
2968 | ||
c233cf40 | 2969 | return work_done; |
1da177e4 | 2970 | } |
1da177e4 | 2971 | |
f2d71c2d | 2972 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0977f817 | 2973 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
f2d71c2d VW |
2974 | * without having to re-enable interrupts. It's not called while |
2975 | * the interrupt routine is executing. | |
2976 | */ | |
2977 | static void gfar_netpoll(struct net_device *dev) | |
2978 | { | |
2979 | struct gfar_private *priv = netdev_priv(dev); | |
3a2e16c8 | 2980 | int i; |
f2d71c2d VW |
2981 | |
2982 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2983 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c | 2984 | for (i = 0; i < priv->num_grps; i++) { |
62ed839d PG |
2985 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
2986 | ||
2987 | disable_irq(gfar_irq(grp, TX)->irq); | |
2988 | disable_irq(gfar_irq(grp, RX)->irq); | |
2989 | disable_irq(gfar_irq(grp, ER)->irq); | |
2990 | gfar_interrupt(gfar_irq(grp, TX)->irq, grp); | |
2991 | enable_irq(gfar_irq(grp, ER)->irq); | |
2992 | enable_irq(gfar_irq(grp, RX)->irq); | |
2993 | enable_irq(gfar_irq(grp, TX)->irq); | |
46ceb60c | 2994 | } |
f2d71c2d | 2995 | } else { |
46ceb60c | 2996 | for (i = 0; i < priv->num_grps; i++) { |
62ed839d PG |
2997 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
2998 | ||
2999 | disable_irq(gfar_irq(grp, TX)->irq); | |
3000 | gfar_interrupt(gfar_irq(grp, TX)->irq, grp); | |
3001 | enable_irq(gfar_irq(grp, TX)->irq); | |
43de004b | 3002 | } |
f2d71c2d VW |
3003 | } |
3004 | } | |
3005 | #endif | |
3006 | ||
1da177e4 | 3007 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 3008 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 3009 | { |
f4983704 | 3010 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
3011 | |
3012 | /* Save ievent for future reference */ | |
f4983704 | 3013 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 3014 | |
1da177e4 | 3015 | /* Check for reception */ |
538cc7ee | 3016 | if (events & IEVENT_RX_MASK) |
f4983704 | 3017 | gfar_receive(irq, grp_id); |
1da177e4 LT |
3018 | |
3019 | /* Check for transmit completion */ | |
538cc7ee | 3020 | if (events & IEVENT_TX_MASK) |
f4983704 | 3021 | gfar_transmit(irq, grp_id); |
1da177e4 | 3022 | |
538cc7ee SS |
3023 | /* Check for errors */ |
3024 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 3025 | gfar_error(irq, grp_id); |
1da177e4 LT |
3026 | |
3027 | return IRQ_HANDLED; | |
3028 | } | |
3029 | ||
23402bdd CM |
3030 | static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv) |
3031 | { | |
3032 | struct phy_device *phydev = priv->phydev; | |
3033 | u32 val = 0; | |
3034 | ||
3035 | if (!phydev->duplex) | |
3036 | return val; | |
3037 | ||
3038 | if (!priv->pause_aneg_en) { | |
3039 | if (priv->tx_pause_en) | |
3040 | val |= MACCFG1_TX_FLOW; | |
3041 | if (priv->rx_pause_en) | |
3042 | val |= MACCFG1_RX_FLOW; | |
3043 | } else { | |
3044 | u16 lcl_adv, rmt_adv; | |
3045 | u8 flowctrl; | |
3046 | /* get link partner capabilities */ | |
3047 | rmt_adv = 0; | |
3048 | if (phydev->pause) | |
3049 | rmt_adv = LPA_PAUSE_CAP; | |
3050 | if (phydev->asym_pause) | |
3051 | rmt_adv |= LPA_PAUSE_ASYM; | |
3052 | ||
3053 | lcl_adv = mii_advertise_flowctrl(phydev->advertising); | |
3054 | ||
3055 | flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); | |
3056 | if (flowctrl & FLOW_CTRL_TX) | |
3057 | val |= MACCFG1_TX_FLOW; | |
3058 | if (flowctrl & FLOW_CTRL_RX) | |
3059 | val |= MACCFG1_RX_FLOW; | |
3060 | } | |
3061 | ||
3062 | return val; | |
3063 | } | |
3064 | ||
1da177e4 LT |
3065 | /* Called every time the controller might need to be made |
3066 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 3067 | * information through variables in the phydev structure, and this |
1da177e4 LT |
3068 | * function converts those variables into the appropriate |
3069 | * register values, and can bring down the device if needed. | |
3070 | */ | |
3071 | static void adjust_link(struct net_device *dev) | |
3072 | { | |
3073 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3074 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
3075 | unsigned long flags; |
3076 | struct phy_device *phydev = priv->phydev; | |
3077 | int new_state = 0; | |
3078 | ||
fba4ed03 SG |
3079 | local_irq_save(flags); |
3080 | lock_tx_qs(priv); | |
3081 | ||
bb40dcbb | 3082 | if (phydev->link) { |
23402bdd | 3083 | u32 tempval1 = gfar_read(®s->maccfg1); |
bb40dcbb | 3084 | u32 tempval = gfar_read(®s->maccfg2); |
7f7f5316 | 3085 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 3086 | |
1da177e4 | 3087 | /* Now we make sure that we can be in full duplex mode. |
0977f817 JC |
3088 | * If not, we operate in half-duplex mode. |
3089 | */ | |
bb40dcbb AF |
3090 | if (phydev->duplex != priv->oldduplex) { |
3091 | new_state = 1; | |
3092 | if (!(phydev->duplex)) | |
1da177e4 | 3093 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 3094 | else |
1da177e4 | 3095 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 3096 | |
bb40dcbb | 3097 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
3098 | } |
3099 | ||
bb40dcbb AF |
3100 | if (phydev->speed != priv->oldspeed) { |
3101 | new_state = 1; | |
3102 | switch (phydev->speed) { | |
1da177e4 | 3103 | case 1000: |
1da177e4 LT |
3104 | tempval = |
3105 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
3106 | |
3107 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3108 | break; |
3109 | case 100: | |
3110 | case 10: | |
1da177e4 LT |
3111 | tempval = |
3112 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
3113 | |
3114 | /* Reduced mode distinguishes | |
0977f817 JC |
3115 | * between 10 and 100 |
3116 | */ | |
7f7f5316 AF |
3117 | if (phydev->speed == SPEED_100) |
3118 | ecntrl |= ECNTRL_R100; | |
3119 | else | |
3120 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3121 | break; |
3122 | default: | |
59deab26 JP |
3123 | netif_warn(priv, link, dev, |
3124 | "Ack! Speed (%d) is not 10/100/1000!\n", | |
3125 | phydev->speed); | |
1da177e4 LT |
3126 | break; |
3127 | } | |
3128 | ||
bb40dcbb | 3129 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3130 | } |
3131 | ||
23402bdd CM |
3132 | tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
3133 | tempval1 |= gfar_get_flowctrl_cfg(priv); | |
3134 | ||
3135 | gfar_write(®s->maccfg1, tempval1); | |
bb40dcbb | 3136 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3137 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3138 | |
1da177e4 | 3139 | if (!priv->oldlink) { |
bb40dcbb | 3140 | new_state = 1; |
1da177e4 | 3141 | priv->oldlink = 1; |
1da177e4 | 3142 | } |
bb40dcbb AF |
3143 | } else if (priv->oldlink) { |
3144 | new_state = 1; | |
3145 | priv->oldlink = 0; | |
3146 | priv->oldspeed = 0; | |
3147 | priv->oldduplex = -1; | |
1da177e4 | 3148 | } |
1da177e4 | 3149 | |
bb40dcbb AF |
3150 | if (new_state && netif_msg_link(priv)) |
3151 | phy_print_status(phydev); | |
fba4ed03 SG |
3152 | unlock_tx_qs(priv); |
3153 | local_irq_restore(flags); | |
bb40dcbb | 3154 | } |
1da177e4 LT |
3155 | |
3156 | /* Update the hash table based on the current list of multicast | |
3157 | * addresses we subscribe to. Also, change the promiscuity of | |
3158 | * the device based on the flags (this function is called | |
0977f817 JC |
3159 | * whenever dev->flags is changed |
3160 | */ | |
1da177e4 LT |
3161 | static void gfar_set_multi(struct net_device *dev) |
3162 | { | |
22bedad3 | 3163 | struct netdev_hw_addr *ha; |
1da177e4 | 3164 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3165 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3166 | u32 tempval; |
3167 | ||
a12f801d | 3168 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3169 | /* Set RCTRL to PROM */ |
3170 | tempval = gfar_read(®s->rctrl); | |
3171 | tempval |= RCTRL_PROM; | |
3172 | gfar_write(®s->rctrl, tempval); | |
3173 | } else { | |
3174 | /* Set RCTRL to not PROM */ | |
3175 | tempval = gfar_read(®s->rctrl); | |
3176 | tempval &= ~(RCTRL_PROM); | |
3177 | gfar_write(®s->rctrl, tempval); | |
3178 | } | |
6aa20a22 | 3179 | |
a12f801d | 3180 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3181 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3182 | gfar_write(®s->igaddr0, 0xffffffff); |
3183 | gfar_write(®s->igaddr1, 0xffffffff); | |
3184 | gfar_write(®s->igaddr2, 0xffffffff); | |
3185 | gfar_write(®s->igaddr3, 0xffffffff); | |
3186 | gfar_write(®s->igaddr4, 0xffffffff); | |
3187 | gfar_write(®s->igaddr5, 0xffffffff); | |
3188 | gfar_write(®s->igaddr6, 0xffffffff); | |
3189 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3190 | gfar_write(®s->gaddr0, 0xffffffff); |
3191 | gfar_write(®s->gaddr1, 0xffffffff); | |
3192 | gfar_write(®s->gaddr2, 0xffffffff); | |
3193 | gfar_write(®s->gaddr3, 0xffffffff); | |
3194 | gfar_write(®s->gaddr4, 0xffffffff); | |
3195 | gfar_write(®s->gaddr5, 0xffffffff); | |
3196 | gfar_write(®s->gaddr6, 0xffffffff); | |
3197 | gfar_write(®s->gaddr7, 0xffffffff); | |
3198 | } else { | |
7f7f5316 AF |
3199 | int em_num; |
3200 | int idx; | |
3201 | ||
1da177e4 | 3202 | /* zero out the hash */ |
0bbaf069 KG |
3203 | gfar_write(®s->igaddr0, 0x0); |
3204 | gfar_write(®s->igaddr1, 0x0); | |
3205 | gfar_write(®s->igaddr2, 0x0); | |
3206 | gfar_write(®s->igaddr3, 0x0); | |
3207 | gfar_write(®s->igaddr4, 0x0); | |
3208 | gfar_write(®s->igaddr5, 0x0); | |
3209 | gfar_write(®s->igaddr6, 0x0); | |
3210 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3211 | gfar_write(®s->gaddr0, 0x0); |
3212 | gfar_write(®s->gaddr1, 0x0); | |
3213 | gfar_write(®s->gaddr2, 0x0); | |
3214 | gfar_write(®s->gaddr3, 0x0); | |
3215 | gfar_write(®s->gaddr4, 0x0); | |
3216 | gfar_write(®s->gaddr5, 0x0); | |
3217 | gfar_write(®s->gaddr6, 0x0); | |
3218 | gfar_write(®s->gaddr7, 0x0); | |
3219 | ||
7f7f5316 AF |
3220 | /* If we have extended hash tables, we need to |
3221 | * clear the exact match registers to prepare for | |
0977f817 JC |
3222 | * setting them |
3223 | */ | |
7f7f5316 AF |
3224 | if (priv->extended_hash) { |
3225 | em_num = GFAR_EM_NUM + 1; | |
3226 | gfar_clear_exact_match(dev); | |
3227 | idx = 1; | |
3228 | } else { | |
3229 | idx = 0; | |
3230 | em_num = 0; | |
3231 | } | |
3232 | ||
4cd24eaf | 3233 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3234 | return; |
3235 | ||
3236 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3237 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3238 | if (idx < em_num) { |
22bedad3 | 3239 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3240 | idx++; |
3241 | } else | |
22bedad3 | 3242 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3243 | } |
3244 | } | |
1da177e4 LT |
3245 | } |
3246 | ||
7f7f5316 AF |
3247 | |
3248 | /* Clears each of the exact match registers to zero, so they | |
0977f817 JC |
3249 | * don't interfere with normal reception |
3250 | */ | |
7f7f5316 AF |
3251 | static void gfar_clear_exact_match(struct net_device *dev) |
3252 | { | |
3253 | int idx; | |
6a3c910c | 3254 | static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 | 3255 | |
bc4598bc | 3256 | for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) |
b6bc7650 | 3257 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3258 | } |
3259 | ||
1da177e4 LT |
3260 | /* Set the appropriate hash bit for the given addr */ |
3261 | /* The algorithm works like so: | |
3262 | * 1) Take the Destination Address (ie the multicast address), and | |
3263 | * do a CRC on it (little endian), and reverse the bits of the | |
3264 | * result. | |
3265 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3266 | * table. The table is controlled through 8 32-bit registers: | |
3267 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3268 | * gaddr7. This means that the 3 most significant bits in the | |
3269 | * hash index which gaddr register to use, and the 5 other bits | |
3270 | * indicate which bit (assuming an IBM numbering scheme, which | |
3271 | * for PowerPC (tm) is usually the case) in the register holds | |
0977f817 JC |
3272 | * the entry. |
3273 | */ | |
1da177e4 LT |
3274 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) |
3275 | { | |
3276 | u32 tempval; | |
3277 | struct gfar_private *priv = netdev_priv(dev); | |
6a3c910c | 3278 | u32 result = ether_crc(ETH_ALEN, addr); |
0bbaf069 KG |
3279 | int width = priv->hash_width; |
3280 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3281 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3282 | u32 value = (1 << (31-whichbit)); |
3283 | ||
0bbaf069 | 3284 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3285 | tempval |= value; |
0bbaf069 | 3286 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3287 | } |
3288 | ||
7f7f5316 AF |
3289 | |
3290 | /* There are multiple MAC Address register pairs on some controllers | |
3291 | * This function sets the numth pair to a given address | |
3292 | */ | |
b6bc7650 JP |
3293 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3294 | const u8 *addr) | |
7f7f5316 AF |
3295 | { |
3296 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3297 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 | 3298 | int idx; |
6a3c910c | 3299 | char tmpbuf[ETH_ALEN]; |
7f7f5316 | 3300 | u32 tempval; |
f4983704 | 3301 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3302 | |
3303 | macptr += num*2; | |
3304 | ||
0977f817 JC |
3305 | /* Now copy it into the mac registers backwards, cuz |
3306 | * little endian is silly | |
3307 | */ | |
6a3c910c JP |
3308 | for (idx = 0; idx < ETH_ALEN; idx++) |
3309 | tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; | |
7f7f5316 AF |
3310 | |
3311 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3312 | ||
3313 | tempval = *((u32 *) (tmpbuf + 4)); | |
3314 | ||
3315 | gfar_write(macptr+1, tempval); | |
3316 | } | |
3317 | ||
1da177e4 | 3318 | /* GFAR error interrupt handler */ |
f4983704 | 3319 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3320 | { |
f4983704 SG |
3321 | struct gfar_priv_grp *gfargrp = grp_id; |
3322 | struct gfar __iomem *regs = gfargrp->regs; | |
3323 | struct gfar_private *priv= gfargrp->priv; | |
3324 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3325 | |
3326 | /* Save ievent for future reference */ | |
f4983704 | 3327 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3328 | |
3329 | /* Clear IEVENT */ | |
f4983704 | 3330 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3331 | |
3332 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3333 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3334 | (events & IEVENT_MAG)) |
3335 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3336 | |
3337 | /* Hmm... */ | |
0bbaf069 | 3338 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
bc4598bc JC |
3339 | netdev_dbg(dev, |
3340 | "error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
59deab26 | 3341 | events, gfar_read(®s->imask)); |
1da177e4 LT |
3342 | |
3343 | /* Update the error counters */ | |
3344 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3345 | dev->stats.tx_errors++; |
1da177e4 LT |
3346 | |
3347 | if (events & IEVENT_LC) | |
09f75cd7 | 3348 | dev->stats.tx_window_errors++; |
1da177e4 | 3349 | if (events & IEVENT_CRL) |
09f75cd7 | 3350 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3351 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3352 | unsigned long flags; |
3353 | ||
59deab26 JP |
3354 | netif_dbg(priv, tx_err, dev, |
3355 | "TX FIFO underrun, packet dropped\n"); | |
09f75cd7 | 3356 | dev->stats.tx_dropped++; |
212079df | 3357 | atomic64_inc(&priv->extra_stats.tx_underrun); |
1da177e4 | 3358 | |
836cf7fa AV |
3359 | local_irq_save(flags); |
3360 | lock_tx_qs(priv); | |
3361 | ||
1da177e4 | 3362 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3363 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3364 | |
3365 | unlock_tx_qs(priv); | |
3366 | local_irq_restore(flags); | |
1da177e4 | 3367 | } |
59deab26 | 3368 | netif_dbg(priv, tx_err, dev, "Transmit Error\n"); |
1da177e4 LT |
3369 | } |
3370 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3371 | dev->stats.rx_errors++; |
212079df | 3372 | atomic64_inc(&priv->extra_stats.rx_bsy); |
1da177e4 | 3373 | |
f4983704 | 3374 | gfar_receive(irq, grp_id); |
1da177e4 | 3375 | |
59deab26 JP |
3376 | netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", |
3377 | gfar_read(®s->rstat)); | |
1da177e4 LT |
3378 | } |
3379 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3380 | dev->stats.rx_errors++; |
212079df | 3381 | atomic64_inc(&priv->extra_stats.rx_babr); |
1da177e4 | 3382 | |
59deab26 | 3383 | netif_dbg(priv, rx_err, dev, "babbling RX error\n"); |
1da177e4 LT |
3384 | } |
3385 | if (events & IEVENT_EBERR) { | |
212079df | 3386 | atomic64_inc(&priv->extra_stats.eberr); |
59deab26 | 3387 | netif_dbg(priv, rx_err, dev, "bus error\n"); |
1da177e4 | 3388 | } |
59deab26 JP |
3389 | if (events & IEVENT_RXC) |
3390 | netif_dbg(priv, rx_status, dev, "control frame\n"); | |
1da177e4 LT |
3391 | |
3392 | if (events & IEVENT_BABT) { | |
212079df | 3393 | atomic64_inc(&priv->extra_stats.tx_babt); |
59deab26 | 3394 | netif_dbg(priv, tx_err, dev, "babbling TX error\n"); |
1da177e4 LT |
3395 | } |
3396 | return IRQ_HANDLED; | |
3397 | } | |
3398 | ||
b31a1d8b AF |
3399 | static struct of_device_id gfar_match[] = |
3400 | { | |
3401 | { | |
3402 | .type = "network", | |
3403 | .compatible = "gianfar", | |
3404 | }, | |
46ceb60c SG |
3405 | { |
3406 | .compatible = "fsl,etsec2", | |
3407 | }, | |
b31a1d8b AF |
3408 | {}, |
3409 | }; | |
e72701ac | 3410 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3411 | |
1da177e4 | 3412 | /* Structure for a device driver */ |
74888760 | 3413 | static struct platform_driver gfar_driver = { |
4018294b GL |
3414 | .driver = { |
3415 | .name = "fsl-gianfar", | |
3416 | .owner = THIS_MODULE, | |
3417 | .pm = GFAR_PM_OPS, | |
3418 | .of_match_table = gfar_match, | |
3419 | }, | |
1da177e4 LT |
3420 | .probe = gfar_probe, |
3421 | .remove = gfar_remove, | |
3422 | }; | |
3423 | ||
db62f684 | 3424 | module_platform_driver(gfar_driver); |