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c78275f3 RC |
1 | /* |
2 | * PTP 1588 clock using the eTSEC | |
3 | * | |
4 | * Copyright (C) 2010 OMICRON electronics GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
375d6a1b JP |
20 | |
21 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
22 | ||
c78275f3 RC |
23 | #include <linux/device.h> |
24 | #include <linux/hrtimer.h> | |
c78275f3 RC |
25 | #include <linux/interrupt.h> |
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/of.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/timex.h> | |
31 | #include <linux/io.h> | |
32 | ||
33 | #include <linux/ptp_clock_kernel.h> | |
34 | ||
35 | #include "gianfar.h" | |
36 | ||
37 | /* | |
38 | * gianfar ptp registers | |
39 | * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010 | |
40 | */ | |
41 | struct gianfar_ptp_registers { | |
42 | u32 tmr_ctrl; /* Timer control register */ | |
43 | u32 tmr_tevent; /* Timestamp event register */ | |
44 | u32 tmr_temask; /* Timer event mask register */ | |
45 | u32 tmr_pevent; /* Timestamp event register */ | |
46 | u32 tmr_pemask; /* Timer event mask register */ | |
47 | u32 tmr_stat; /* Timestamp status register */ | |
48 | u32 tmr_cnt_h; /* Timer counter high register */ | |
49 | u32 tmr_cnt_l; /* Timer counter low register */ | |
50 | u32 tmr_add; /* Timer drift compensation addend register */ | |
51 | u32 tmr_acc; /* Timer accumulator register */ | |
52 | u32 tmr_prsc; /* Timer prescale */ | |
53 | u8 res1[4]; | |
54 | u32 tmroff_h; /* Timer offset high */ | |
55 | u32 tmroff_l; /* Timer offset low */ | |
56 | u8 res2[8]; | |
57 | u32 tmr_alarm1_h; /* Timer alarm 1 high register */ | |
58 | u32 tmr_alarm1_l; /* Timer alarm 1 high register */ | |
59 | u32 tmr_alarm2_h; /* Timer alarm 2 high register */ | |
60 | u32 tmr_alarm2_l; /* Timer alarm 2 high register */ | |
61 | u8 res3[48]; | |
62 | u32 tmr_fiper1; /* Timer fixed period interval */ | |
63 | u32 tmr_fiper2; /* Timer fixed period interval */ | |
64 | u32 tmr_fiper3; /* Timer fixed period interval */ | |
65 | u8 res4[20]; | |
66 | u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */ | |
67 | u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */ | |
68 | u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */ | |
69 | u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */ | |
70 | }; | |
71 | ||
72 | /* Bit definitions for the TMR_CTRL register */ | |
73 | #define ALM1P (1<<31) /* Alarm1 output polarity */ | |
74 | #define ALM2P (1<<30) /* Alarm2 output polarity */ | |
75 | #define FS (1<<28) /* FIPER start indication */ | |
76 | #define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */ | |
77 | #define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */ | |
78 | #define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */ | |
79 | #define TCLK_PERIOD_MASK (0x3ff) | |
80 | #define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */ | |
81 | #define FRD (1<<14) /* FIPER Realignment Disable */ | |
82 | #define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */ | |
83 | #define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */ | |
84 | #define ETEP2 (1<<9) /* External trigger 2 edge polarity */ | |
85 | #define ETEP1 (1<<8) /* External trigger 1 edge polarity */ | |
86 | #define COPH (1<<7) /* Generated clock output phase. */ | |
87 | #define CIPH (1<<6) /* External oscillator input clock phase */ | |
88 | #define TMSR (1<<5) /* Timer soft reset. */ | |
89 | #define BYP (1<<3) /* Bypass drift compensated clock */ | |
90 | #define TE (1<<2) /* 1588 timer enable. */ | |
91 | #define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */ | |
92 | #define CKSEL_MASK (0x3) | |
93 | ||
94 | /* Bit definitions for the TMR_TEVENT register */ | |
95 | #define ETS2 (1<<25) /* External trigger 2 timestamp sampled */ | |
96 | #define ETS1 (1<<24) /* External trigger 1 timestamp sampled */ | |
97 | #define ALM2 (1<<17) /* Current time = alarm time register 2 */ | |
98 | #define ALM1 (1<<16) /* Current time = alarm time register 1 */ | |
99 | #define PP1 (1<<7) /* periodic pulse generated on FIPER1 */ | |
100 | #define PP2 (1<<6) /* periodic pulse generated on FIPER2 */ | |
101 | #define PP3 (1<<5) /* periodic pulse generated on FIPER3 */ | |
102 | ||
103 | /* Bit definitions for the TMR_TEMASK register */ | |
104 | #define ETS2EN (1<<25) /* External trigger 2 timestamp enable */ | |
105 | #define ETS1EN (1<<24) /* External trigger 1 timestamp enable */ | |
106 | #define ALM2EN (1<<17) /* Timer ALM2 event enable */ | |
107 | #define ALM1EN (1<<16) /* Timer ALM1 event enable */ | |
108 | #define PP1EN (1<<7) /* Periodic pulse event 1 enable */ | |
109 | #define PP2EN (1<<6) /* Periodic pulse event 2 enable */ | |
110 | ||
111 | /* Bit definitions for the TMR_PEVENT register */ | |
112 | #define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */ | |
113 | #define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */ | |
114 | #define RXP (1<<0) /* PTP frame has been received */ | |
115 | ||
116 | /* Bit definitions for the TMR_PEMASK register */ | |
117 | #define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */ | |
118 | #define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */ | |
119 | #define RXPEN (1<<0) /* Receive PTP packet event enable */ | |
120 | ||
121 | /* Bit definitions for the TMR_STAT register */ | |
122 | #define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */ | |
123 | #define STAT_VEC_MASK (0x3f) | |
124 | ||
125 | /* Bit definitions for the TMR_PRSC register */ | |
126 | #define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */ | |
127 | #define PRSC_OCK_MASK (0xffff) | |
128 | ||
129 | ||
130 | #define DRIVER "gianfar_ptp" | |
131 | #define DEFAULT_CKSEL 1 | |
c78275f3 RC |
132 | #define N_EXT_TS 2 |
133 | #define REG_SIZE sizeof(struct gianfar_ptp_registers) | |
134 | ||
135 | struct etsects { | |
42851e88 | 136 | struct gianfar_ptp_registers __iomem *regs; |
c78275f3 RC |
137 | spinlock_t lock; /* protects regs */ |
138 | struct ptp_clock *clock; | |
139 | struct ptp_clock_info caps; | |
140 | struct resource *rsrc; | |
141 | int irq; | |
142 | u64 alarm_interval; /* for periodic alarm */ | |
143 | u64 alarm_value; | |
144 | u32 tclk_period; /* nanoseconds */ | |
145 | u32 tmr_prsc; | |
146 | u32 tmr_add; | |
147 | u32 cksel; | |
148 | u32 tmr_fiper1; | |
149 | u32 tmr_fiper2; | |
150 | }; | |
151 | ||
152 | /* | |
153 | * Register access functions | |
154 | */ | |
155 | ||
156 | /* Caller must hold etsects->lock. */ | |
157 | static u64 tmr_cnt_read(struct etsects *etsects) | |
158 | { | |
159 | u64 ns; | |
160 | u32 lo, hi; | |
161 | ||
162 | lo = gfar_read(&etsects->regs->tmr_cnt_l); | |
163 | hi = gfar_read(&etsects->regs->tmr_cnt_h); | |
164 | ns = ((u64) hi) << 32; | |
165 | ns |= lo; | |
166 | return ns; | |
167 | } | |
168 | ||
169 | /* Caller must hold etsects->lock. */ | |
170 | static void tmr_cnt_write(struct etsects *etsects, u64 ns) | |
171 | { | |
172 | u32 hi = ns >> 32; | |
173 | u32 lo = ns & 0xffffffff; | |
174 | ||
175 | gfar_write(&etsects->regs->tmr_cnt_l, lo); | |
176 | gfar_write(&etsects->regs->tmr_cnt_h, hi); | |
177 | } | |
178 | ||
179 | /* Caller must hold etsects->lock. */ | |
180 | static void set_alarm(struct etsects *etsects) | |
181 | { | |
182 | u64 ns; | |
183 | u32 lo, hi; | |
184 | ||
185 | ns = tmr_cnt_read(etsects) + 1500000000ULL; | |
186 | ns = div_u64(ns, 1000000000UL) * 1000000000ULL; | |
187 | ns -= etsects->tclk_period; | |
188 | hi = ns >> 32; | |
189 | lo = ns & 0xffffffff; | |
190 | gfar_write(&etsects->regs->tmr_alarm1_l, lo); | |
191 | gfar_write(&etsects->regs->tmr_alarm1_h, hi); | |
192 | } | |
193 | ||
194 | /* Caller must hold etsects->lock. */ | |
195 | static void set_fipers(struct etsects *etsects) | |
196 | { | |
cbc05660 | 197 | set_alarm(etsects); |
c78275f3 RC |
198 | gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1); |
199 | gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2); | |
c78275f3 RC |
200 | } |
201 | ||
202 | /* | |
203 | * Interrupt service routine | |
204 | */ | |
205 | ||
206 | static irqreturn_t isr(int irq, void *priv) | |
207 | { | |
208 | struct etsects *etsects = priv; | |
209 | struct ptp_clock_event event; | |
210 | u64 ns; | |
211 | u32 ack = 0, lo, hi, mask, val; | |
212 | ||
213 | val = gfar_read(&etsects->regs->tmr_tevent); | |
214 | ||
215 | if (val & ETS1) { | |
216 | ack |= ETS1; | |
217 | hi = gfar_read(&etsects->regs->tmr_etts1_h); | |
218 | lo = gfar_read(&etsects->regs->tmr_etts1_l); | |
219 | event.type = PTP_CLOCK_EXTTS; | |
220 | event.index = 0; | |
221 | event.timestamp = ((u64) hi) << 32; | |
222 | event.timestamp |= lo; | |
223 | ptp_clock_event(etsects->clock, &event); | |
224 | } | |
225 | ||
226 | if (val & ETS2) { | |
227 | ack |= ETS2; | |
228 | hi = gfar_read(&etsects->regs->tmr_etts2_h); | |
229 | lo = gfar_read(&etsects->regs->tmr_etts2_l); | |
230 | event.type = PTP_CLOCK_EXTTS; | |
231 | event.index = 1; | |
232 | event.timestamp = ((u64) hi) << 32; | |
233 | event.timestamp |= lo; | |
234 | ptp_clock_event(etsects->clock, &event); | |
235 | } | |
236 | ||
237 | if (val & ALM2) { | |
238 | ack |= ALM2; | |
239 | if (etsects->alarm_value) { | |
240 | event.type = PTP_CLOCK_ALARM; | |
241 | event.index = 0; | |
242 | event.timestamp = etsects->alarm_value; | |
243 | ptp_clock_event(etsects->clock, &event); | |
244 | } | |
245 | if (etsects->alarm_interval) { | |
246 | ns = etsects->alarm_value + etsects->alarm_interval; | |
247 | hi = ns >> 32; | |
248 | lo = ns & 0xffffffff; | |
249 | spin_lock(&etsects->lock); | |
250 | gfar_write(&etsects->regs->tmr_alarm2_l, lo); | |
251 | gfar_write(&etsects->regs->tmr_alarm2_h, hi); | |
252 | spin_unlock(&etsects->lock); | |
253 | etsects->alarm_value = ns; | |
254 | } else { | |
255 | gfar_write(&etsects->regs->tmr_tevent, ALM2); | |
256 | spin_lock(&etsects->lock); | |
257 | mask = gfar_read(&etsects->regs->tmr_temask); | |
258 | mask &= ~ALM2EN; | |
259 | gfar_write(&etsects->regs->tmr_temask, mask); | |
260 | spin_unlock(&etsects->lock); | |
261 | etsects->alarm_value = 0; | |
262 | etsects->alarm_interval = 0; | |
263 | } | |
264 | } | |
265 | ||
266 | if (val & PP1) { | |
267 | ack |= PP1; | |
268 | event.type = PTP_CLOCK_PPS; | |
269 | ptp_clock_event(etsects->clock, &event); | |
270 | } | |
271 | ||
272 | if (ack) { | |
273 | gfar_write(&etsects->regs->tmr_tevent, ack); | |
274 | return IRQ_HANDLED; | |
275 | } else | |
276 | return IRQ_NONE; | |
277 | } | |
278 | ||
279 | /* | |
280 | * PTP clock operations | |
281 | */ | |
282 | ||
283 | static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb) | |
284 | { | |
285 | u64 adj; | |
286 | u32 diff, tmr_add; | |
287 | int neg_adj = 0; | |
288 | struct etsects *etsects = container_of(ptp, struct etsects, caps); | |
289 | ||
290 | if (ppb < 0) { | |
291 | neg_adj = 1; | |
292 | ppb = -ppb; | |
293 | } | |
294 | tmr_add = etsects->tmr_add; | |
295 | adj = tmr_add; | |
296 | adj *= ppb; | |
297 | diff = div_u64(adj, 1000000000ULL); | |
298 | ||
299 | tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff; | |
300 | ||
301 | gfar_write(&etsects->regs->tmr_add, tmr_add); | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
307 | { | |
308 | s64 now; | |
309 | unsigned long flags; | |
310 | struct etsects *etsects = container_of(ptp, struct etsects, caps); | |
311 | ||
312 | spin_lock_irqsave(&etsects->lock, flags); | |
313 | ||
314 | now = tmr_cnt_read(etsects); | |
315 | now += delta; | |
316 | tmr_cnt_write(etsects, now); | |
317 | ||
318 | spin_unlock_irqrestore(&etsects->lock, flags); | |
319 | ||
320 | set_fipers(etsects); | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
d28fdf0f RC |
325 | static int ptp_gianfar_gettime(struct ptp_clock_info *ptp, |
326 | struct timespec64 *ts) | |
c78275f3 RC |
327 | { |
328 | u64 ns; | |
c78275f3 RC |
329 | unsigned long flags; |
330 | struct etsects *etsects = container_of(ptp, struct etsects, caps); | |
331 | ||
332 | spin_lock_irqsave(&etsects->lock, flags); | |
333 | ||
334 | ns = tmr_cnt_read(etsects); | |
335 | ||
336 | spin_unlock_irqrestore(&etsects->lock, flags); | |
337 | ||
3359e7c2 RC |
338 | *ts = ns_to_timespec64(ns); |
339 | ||
c78275f3 RC |
340 | return 0; |
341 | } | |
342 | ||
343 | static int ptp_gianfar_settime(struct ptp_clock_info *ptp, | |
d28fdf0f | 344 | const struct timespec64 *ts) |
c78275f3 RC |
345 | { |
346 | u64 ns; | |
347 | unsigned long flags; | |
348 | struct etsects *etsects = container_of(ptp, struct etsects, caps); | |
349 | ||
3359e7c2 | 350 | ns = timespec64_to_ns(ts); |
c78275f3 RC |
351 | |
352 | spin_lock_irqsave(&etsects->lock, flags); | |
353 | ||
354 | tmr_cnt_write(etsects, ns); | |
355 | set_fipers(etsects); | |
356 | ||
357 | spin_unlock_irqrestore(&etsects->lock, flags); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static int ptp_gianfar_enable(struct ptp_clock_info *ptp, | |
363 | struct ptp_clock_request *rq, int on) | |
364 | { | |
365 | struct etsects *etsects = container_of(ptp, struct etsects, caps); | |
366 | unsigned long flags; | |
367 | u32 bit, mask; | |
368 | ||
369 | switch (rq->type) { | |
370 | case PTP_CLK_REQ_EXTTS: | |
371 | switch (rq->extts.index) { | |
372 | case 0: | |
373 | bit = ETS1EN; | |
374 | break; | |
375 | case 1: | |
376 | bit = ETS2EN; | |
377 | break; | |
378 | default: | |
379 | return -EINVAL; | |
380 | } | |
381 | spin_lock_irqsave(&etsects->lock, flags); | |
382 | mask = gfar_read(&etsects->regs->tmr_temask); | |
383 | if (on) | |
384 | mask |= bit; | |
385 | else | |
386 | mask &= ~bit; | |
387 | gfar_write(&etsects->regs->tmr_temask, mask); | |
388 | spin_unlock_irqrestore(&etsects->lock, flags); | |
389 | return 0; | |
390 | ||
391 | case PTP_CLK_REQ_PPS: | |
392 | spin_lock_irqsave(&etsects->lock, flags); | |
393 | mask = gfar_read(&etsects->regs->tmr_temask); | |
394 | if (on) | |
395 | mask |= PP1EN; | |
396 | else | |
397 | mask &= ~PP1EN; | |
398 | gfar_write(&etsects->regs->tmr_temask, mask); | |
399 | spin_unlock_irqrestore(&etsects->lock, flags); | |
400 | return 0; | |
401 | ||
402 | default: | |
403 | break; | |
404 | } | |
405 | ||
406 | return -EOPNOTSUPP; | |
407 | } | |
408 | ||
409 | static struct ptp_clock_info ptp_gianfar_caps = { | |
410 | .owner = THIS_MODULE, | |
411 | .name = "gianfar clock", | |
412 | .max_adj = 512000, | |
cd4baaaa | 413 | .n_alarm = 0, |
c78275f3 RC |
414 | .n_ext_ts = N_EXT_TS, |
415 | .n_per_out = 0, | |
4986b4f0 | 416 | .n_pins = 0, |
c78275f3 RC |
417 | .pps = 1, |
418 | .adjfreq = ptp_gianfar_adjfreq, | |
419 | .adjtime = ptp_gianfar_adjtime, | |
d28fdf0f RC |
420 | .gettime64 = ptp_gianfar_gettime, |
421 | .settime64 = ptp_gianfar_settime, | |
c78275f3 RC |
422 | .enable = ptp_gianfar_enable, |
423 | }; | |
424 | ||
425 | /* OF device tree */ | |
426 | ||
427 | static int get_of_u32(struct device_node *node, char *str, u32 *val) | |
428 | { | |
429 | int plen; | |
430 | const u32 *prop = of_get_property(node, str, &plen); | |
431 | ||
432 | if (!prop || plen != sizeof(*prop)) | |
433 | return -1; | |
434 | *val = *prop; | |
435 | return 0; | |
436 | } | |
437 | ||
438 | static int gianfar_ptp_probe(struct platform_device *dev) | |
439 | { | |
440 | struct device_node *node = dev->dev.of_node; | |
441 | struct etsects *etsects; | |
d28fdf0f | 442 | struct timespec64 now; |
c78275f3 RC |
443 | int err = -ENOMEM; |
444 | u32 tmr_ctrl; | |
445 | unsigned long flags; | |
446 | ||
447 | etsects = kzalloc(sizeof(*etsects), GFP_KERNEL); | |
448 | if (!etsects) | |
449 | goto no_memory; | |
450 | ||
451 | err = -ENODEV; | |
452 | ||
453 | etsects->caps = ptp_gianfar_caps; | |
e58f6f4f AM |
454 | |
455 | if (get_of_u32(node, "fsl,cksel", &etsects->cksel)) | |
456 | etsects->cksel = DEFAULT_CKSEL; | |
c78275f3 RC |
457 | |
458 | if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) || | |
459 | get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) || | |
460 | get_of_u32(node, "fsl,tmr-add", &etsects->tmr_add) || | |
461 | get_of_u32(node, "fsl,tmr-fiper1", &etsects->tmr_fiper1) || | |
462 | get_of_u32(node, "fsl,tmr-fiper2", &etsects->tmr_fiper2) || | |
463 | get_of_u32(node, "fsl,max-adj", &etsects->caps.max_adj)) { | |
464 | pr_err("device tree node missing required elements\n"); | |
465 | goto no_node; | |
466 | } | |
467 | ||
468 | etsects->irq = platform_get_irq(dev, 0); | |
469 | ||
470 | if (etsects->irq == NO_IRQ) { | |
471 | pr_err("irq not in device tree\n"); | |
472 | goto no_node; | |
473 | } | |
474 | if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) { | |
475 | pr_err("request_irq failed\n"); | |
476 | goto no_node; | |
477 | } | |
478 | ||
479 | etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
480 | if (!etsects->rsrc) { | |
481 | pr_err("no resource\n"); | |
482 | goto no_resource; | |
483 | } | |
2b9c128e | 484 | if (request_resource(&iomem_resource, etsects->rsrc)) { |
c78275f3 RC |
485 | pr_err("resource busy\n"); |
486 | goto no_resource; | |
487 | } | |
488 | ||
489 | spin_lock_init(&etsects->lock); | |
490 | ||
491 | etsects->regs = ioremap(etsects->rsrc->start, | |
28f65c11 | 492 | resource_size(etsects->rsrc)); |
c78275f3 RC |
493 | if (!etsects->regs) { |
494 | pr_err("ioremap ptp registers failed\n"); | |
495 | goto no_ioremap; | |
496 | } | |
d28fdf0f | 497 | getnstimeofday64(&now); |
c78275f3 RC |
498 | ptp_gianfar_settime(&etsects->caps, &now); |
499 | ||
500 | tmr_ctrl = | |
501 | (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT | | |
502 | (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT; | |
503 | ||
504 | spin_lock_irqsave(&etsects->lock, flags); | |
505 | ||
506 | gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl); | |
507 | gfar_write(&etsects->regs->tmr_add, etsects->tmr_add); | |
508 | gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc); | |
509 | gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1); | |
510 | gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2); | |
511 | set_alarm(etsects); | |
cbc05660 | 512 | gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FS|RTPE|TE|FRD); |
c78275f3 RC |
513 | |
514 | spin_unlock_irqrestore(&etsects->lock, flags); | |
515 | ||
1ef76158 | 516 | etsects->clock = ptp_clock_register(&etsects->caps, &dev->dev); |
c78275f3 RC |
517 | if (IS_ERR(etsects->clock)) { |
518 | err = PTR_ERR(etsects->clock); | |
519 | goto no_clock; | |
520 | } | |
28889b7e | 521 | gfar_phc_index = ptp_clock_index(etsects->clock); |
c78275f3 | 522 | |
8513fbd8 | 523 | platform_set_drvdata(dev, etsects); |
c78275f3 RC |
524 | |
525 | return 0; | |
526 | ||
527 | no_clock: | |
e5f5e380 | 528 | iounmap(etsects->regs); |
c78275f3 RC |
529 | no_ioremap: |
530 | release_resource(etsects->rsrc); | |
531 | no_resource: | |
532 | free_irq(etsects->irq, etsects); | |
533 | no_node: | |
534 | kfree(etsects); | |
535 | no_memory: | |
536 | return err; | |
537 | } | |
538 | ||
539 | static int gianfar_ptp_remove(struct platform_device *dev) | |
540 | { | |
8513fbd8 | 541 | struct etsects *etsects = platform_get_drvdata(dev); |
c78275f3 RC |
542 | |
543 | gfar_write(&etsects->regs->tmr_temask, 0); | |
544 | gfar_write(&etsects->regs->tmr_ctrl, 0); | |
545 | ||
28889b7e | 546 | gfar_phc_index = -1; |
c78275f3 RC |
547 | ptp_clock_unregister(etsects->clock); |
548 | iounmap(etsects->regs); | |
549 | release_resource(etsects->rsrc); | |
550 | free_irq(etsects->irq, etsects); | |
551 | kfree(etsects); | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
94e5a2a8 | 556 | static const struct of_device_id match_table[] = { |
c78275f3 RC |
557 | { .compatible = "fsl,etsec-ptp" }, |
558 | {}, | |
559 | }; | |
23860063 | 560 | MODULE_DEVICE_TABLE(of, match_table); |
c78275f3 RC |
561 | |
562 | static struct platform_driver gianfar_ptp_driver = { | |
563 | .driver = { | |
564 | .name = "gianfar_ptp", | |
565 | .of_match_table = match_table, | |
c78275f3 RC |
566 | }, |
567 | .probe = gianfar_ptp_probe, | |
568 | .remove = gianfar_ptp_remove, | |
569 | }; | |
570 | ||
db62f684 | 571 | module_platform_driver(gianfar_ptp_driver); |
c78275f3 | 572 | |
c2ec3ff6 | 573 | MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); |
c78275f3 RC |
574 | MODULE_DESCRIPTION("PTP clock using the eTSEC"); |
575 | MODULE_LICENSE("GPL"); |