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net: hns: modify tcam table of mac uc-entry
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_main.c
CommitLineData
511e6bc0 1/*
2 * Copyright (c) 2014-2015 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
8413b3be 10#include <linux/acpi.h>
2e2591b1 11#include <linux/device.h>
511e6bc0 12#include <linux/init.h>
13#include <linux/interrupt.h>
2e2591b1
DH		 14#include <linux/kernel.h>
15#include <linux/module.h>
511e6bc0 16#include <linux/netdevice.h>
831d828b 17#include <linux/mfd/syscon.h>
511e6bc0 18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
e0180688 21#include <linux/of_platform.h>
2e2591b1 22#include <linux/platform_device.h>
119c7ad8
AB		 23#include <linux/vmalloc.h>
24
2e2591b1 25#include "hns_dsaf_mac.h"
511e6bc0 26#include "hns_dsaf_main.h"
511e6bc0 27#include "hns_dsaf_ppe.h"
2e2591b1 28#include "hns_dsaf_rcb.h"
a24274aa 29#include "hns_dsaf_misc.h"
511e6bc0 30
31const char *g_dsaf_mode_match[DSAF_MODE_MAX] = {
32 [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf",
33 [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss",
34 [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf",
89a44093 35 [DSAF_MODE_DISABLE_SP] = "single-port",
511e6bc0 36};
37
8413b3be
KY		 38static const struct acpi_device_id hns_dsaf_acpi_match[] = {
39 { "HISI00B1", 0 },
40 { "HISI00B2", 0 },
41 { },
42};
43MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match);
44
511e6bc0 45int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev)
46{
47 int ret, i;
48 u32 desc_num;
49 u32 buf_size;
422c3107 50 u32 reset_offset = 0;
831d828b 51 u32 res_idx = 0;
48189d6a 52 const char *mode_str;
831d828b
YZZ		 53 struct regmap *syscon;
54 struct resource *res;
453cafbc 55 struct device_node *np = dsaf_dev->dev->of_node, *np_temp;
831d828b 56 struct platform_device *pdev = to_platform_device(dsaf_dev->dev);
511e6bc0 57
8413b3be
KY		 58 if (dev_of_node(dsaf_dev->dev)) {
59 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1"))
60 dsaf_dev->dsaf_ver = AE_VERSION_1;
61 else
62 dsaf_dev->dsaf_ver = AE_VERSION_2;
63 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
64 if (acpi_dev_found(hns_dsaf_acpi_match[0].id))
65 dsaf_dev->dsaf_ver = AE_VERSION_1;
66 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id))
67 dsaf_dev->dsaf_ver = AE_VERSION_2;
68 else
69 return -ENXIO;
70 } else {
71 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n");
72 return -ENXIO;
73 }
511e6bc0 74
6162928c 75 ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str);
511e6bc0 76 if (ret) {
77 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret);
78 return ret;
79 }
80 for (i = 0; i < DSAF_MODE_MAX; i++) {
81 if (g_dsaf_mode_match[i] &&
82 !strcmp(mode_str, g_dsaf_mode_match[i]))
83 break;
84 }
85 if (i >= DSAF_MODE_MAX ||
86 i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) {
87 dev_err(dsaf_dev->dev,
88 "%s prs mode str fail!\n", dsaf_dev->ae_dev.name);
89 return -EINVAL;
90 }
91 dsaf_dev->dsaf_mode = (enum dsaf_mode)i;
92
93 if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE)
94 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE;
95 else
96 dsaf_dev->dsaf_en = HRD_DSAF_MODE;
97
98 if ((i == DSAF_MODE_ENABLE_16VM) ||
99 (i == DSAF_MODE_DISABLE_2PORT_8VM) ||
100 (i == DSAF_MODE_DISABLE_6PORT_2VM))
101 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE;
102 else
103 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE;
104
8413b3be 105 if (dev_of_node(dsaf_dev->dev)) {
453cafbc
PC		 106 np_temp = of_parse_phandle(np, "subctrl-syscon", 0);
107 syscon = syscon_node_to_regmap(np_temp);
108 of_node_put(np_temp);
8413b3be
KY		 109 if (IS_ERR_OR_NULL(syscon)) {
110 res = platform_get_resource(pdev, IORESOURCE_MEM,
111 res_idx++);
112 if (!res) {
113 dev_err(dsaf_dev->dev, "subctrl info is needed!\n");
114 return -ENOMEM;
115 }
511e6bc0 116
8413b3be
KY		 117 dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev,
118 res);
b3dc9350 119 if (IS_ERR(dsaf_dev->sc_base))
96329a18 120 return PTR_ERR(dsaf_dev->sc_base);
8413b3be
KY		 121
122 res = platform_get_resource(pdev, IORESOURCE_MEM,
123 res_idx++);
124 if (!res) {
125 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n");
126 return -ENOMEM;
127 }
128
129 dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev,
130 res);
b3dc9350 131 if (IS_ERR(dsaf_dev->sds_base))
96329a18 132 return PTR_ERR(dsaf_dev->sds_base);
8413b3be
KY		 133 } else {
134 dsaf_dev->sub_ctrl = syscon;
831d828b 135 }
511e6bc0 136 }
137
831d828b
YZZ		 138 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base");
139 if (!res) {
140 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++);
141 if (!res) {
142 dev_err(dsaf_dev->dev, "ppe-base info is needed!\n");
143 return -ENOMEM;
144 }
145 }
146 dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res);
b3dc9350 147 if (IS_ERR(dsaf_dev->ppe_base))
96329a18 148 return PTR_ERR(dsaf_dev->ppe_base);
831d828b
YZZ		 149 dsaf_dev->ppe_paddr = res->start;
150
151 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
152 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
153 "dsaf-base");
154 if (!res) {
155 res = platform_get_resource(pdev, IORESOURCE_MEM,
156 res_idx);
157 if (!res) {
158 dev_err(dsaf_dev->dev,
159 "dsaf-base info is needed!\n");
160 return -ENOMEM;
161 }
162 }
163 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res);
b3dc9350 164 if (IS_ERR(dsaf_dev->io_base))
96329a18 165 return PTR_ERR(dsaf_dev->io_base);
511e6bc0 166 }
167
6162928c 168 ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num);
511e6bc0 169 if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT ||
170 desc_num > HNS_DSAF_MAX_DESC_CNT) {
171 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n",
172 desc_num, ret);
f6c2df1e 173 return -EINVAL;
511e6bc0 174 }
175 dsaf_dev->desc_num = desc_num;
176
6162928c
KY		 177 ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset",
178 &reset_offset);
422c3107
YZZ		 179 if (ret < 0) {
180 dev_dbg(dsaf_dev->dev,
181 "get reset-field-offset fail, ret=%d!\r\n", ret);
182 }
183 dsaf_dev->reset_offset = reset_offset;
184
6162928c 185 ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size);
511e6bc0 186 if (ret < 0) {
187 dev_err(dsaf_dev->dev,
188 "get buf-size fail, ret=%d!\r\n", ret);
f6c2df1e 189 return ret;
511e6bc0 190 }
191 dsaf_dev->buf_size = buf_size;
192
193 dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size);
194 if (dsaf_dev->buf_size_type < 0) {
195 dev_err(dsaf_dev->dev,
196 "buf_size(%d) is wrong!\n", buf_size);
f6c2df1e 197 return -EINVAL;
511e6bc0 198 }
199
a24274aa
KY		 200 dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev);
201 if (!dsaf_dev->misc_op)
202 return -ENOMEM;
203
511e6bc0 204 if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL)))
205 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n");
206 else
207 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n");
208
209 return 0;
511e6bc0 210}
211
212/**
213 * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en
214 * @dsaf_id: dsa fabric id
215 */
216static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev)
217{
218 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
219}
220
221/**
222 * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce
223 * @dsaf_id: dsa fabric id
224 * @hns_dsaf_reg_cnt_clr_ce: config value
225 */
226static void
227hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce)
228{
229 dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
230 DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce);
231}
232
233/**
234 * hns_ppe_qid_cfg - config ppe qid
235 * @dsaf_id: dsa fabric id
236 * @pppe_qid_cfg: value array
237 */
238static void
239hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg)
240{
241 u32 i;
242
243 for (i = 0; i < DSAF_COMM_CHN; i++) {
244 dsaf_set_dev_field(dsaf_dev,
245 DSAF_PPE_QID_CFG_0_REG + 0x0004 * i,
246 DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S,
247 qid_cfg);
248 }
249}
250
4568637f 251static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev)
252{
253 u16 max_q_per_vf, max_vfn;
254 u32 q_id, q_num_per_port;
255 u32 i;
256
89a44093 257 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
4568637f 258 q_num_per_port = max_vfn * max_q_per_vf;
259
260 for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) {
261 dsaf_set_dev_field(dsaf_dev,
262 DSAF_MIX_DEF_QID_0_REG + 0x0004 * i,
263 0xff, 0, q_id);
264 q_id += q_num_per_port;
265 }
266}
267
68c222a6 268static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev)
269{
270 u16 max_q_per_vf, max_vfn;
271 u32 q_id, q_num_per_port;
272 u32 mac_id;
273
274 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
275 return;
276
89a44093 277 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
68c222a6 278 q_num_per_port = max_vfn * max_q_per_vf;
279
280 for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) {
281 dsaf_set_dev_field(dsaf_dev,
282 DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
283 DSAFV2_SERDES_LBK_QID_M,
284 DSAFV2_SERDES_LBK_QID_S,
285 q_id);
286 q_id += q_num_per_port;
287 }
288}
289
511e6bc0 290/**
291 * hns_dsaf_sw_port_type_cfg - cfg sw type
292 * @dsaf_id: dsa fabric id
293 * @psw_port_type: array
294 */
295static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev,
296 enum dsaf_sw_port_type port_type)
297{
298 u32 i;
299
300 for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
301 dsaf_set_dev_field(dsaf_dev,
302 DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i,
303 DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S,
304 port_type);
305 }
306}
307
308/**
309 * hns_dsaf_stp_port_type_cfg - cfg stp type
310 * @dsaf_id: dsa fabric id
311 * @pstp_port_type: array
312 */
313static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev,
314 enum dsaf_stp_port_type port_type)
315{
316 u32 i;
317
318 for (i = 0; i < DSAF_COMM_CHN; i++) {
319 dsaf_set_dev_field(dsaf_dev,
320 DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i,
321 DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S,
322 port_type);
323 }
324}
325
13ac695e
S		 326#define HNS_DSAF_SBM_NUM(dev) \
327 (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM)
511e6bc0 328/**
329 * hns_dsaf_sbm_cfg - config sbm
330 * @dsaf_id: dsa fabric id
331 */
332static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev)
333{
334 u32 o_sbm_cfg;
335 u32 i;
336
13ac695e 337 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
511e6bc0 338 o_sbm_cfg = dsaf_read_dev(dsaf_dev,
339 DSAF_SBM_CFG_REG_0_REG + 0x80 * i);
340 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1);
341 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0);
342 dsaf_write_dev(dsaf_dev,
343 DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg);
344 }
345}
346
347/**
348 * hns_dsaf_sbm_cfg_mib_en - config sbm
349 * @dsaf_id: dsa fabric id
350 */
351static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev)
352{
353 u32 sbm_cfg_mib_en;
354 u32 i;
355 u32 reg;
356 u32 read_cnt;
357
13ac695e
S		 358 /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */
359 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
360 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
361 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
362 }
363
364 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
511e6bc0 365 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
366 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
367 }
368
369 /* waitint for all sbm enable finished */
13ac695e 370 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
511e6bc0 371 read_cnt = 0;
372 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
373 do {
374 udelay(1);
375 sbm_cfg_mib_en = dsaf_get_dev_bit(
376 dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S);
377 read_cnt++;
378 } while (sbm_cfg_mib_en == 0 &&
379 read_cnt < DSAF_CFG_READ_CNT);
380
381 if (sbm_cfg_mib_en == 0) {
382 dev_err(dsaf_dev->dev,
383 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n",
384 dsaf_dev->ae_dev.name, i);
385 return -ENODEV;
386 }
387 }
388
389 return 0;
390}
391
392/**
393 * hns_dsaf_sbm_bp_wl_cfg - config sbm
394 * @dsaf_id: dsa fabric id
395 */
396static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
397{
13ac695e 398 u32 o_sbm_bp_cfg;
511e6bc0 399 u32 reg;
400 u32 i;
401
402 /* XGE */
403 for (i = 0; i < DSAF_XGE_NUM; i++) {
404 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
13ac695e
S		 405 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
406 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
511e6bc0 407 DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512);
13ac695e 408 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
511e6bc0 409 DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
13ac695e 410 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
511e6bc0 411 DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
13ac695e 412 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
511e6bc0 413
414 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
13ac695e
S		 415 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
416 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
511e6bc0 417 DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
13ac695e 418 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
511e6bc0 419 DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
13ac695e 420 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
511e6bc0 421
422 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
13ac695e
S		 423 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
424 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
511e6bc0 425 DSAF_SBM_CFG2_SET_BUF_NUM_S, 104);
13ac695e 426 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
511e6bc0 427 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128);
13ac695e 428 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
511e6bc0 429
430 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
13ac695e
S		 431 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
432 dsaf_set_field(o_sbm_bp_cfg,
511e6bc0 433 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
434 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
13ac695e 435 dsaf_set_field(o_sbm_bp_cfg,
511e6bc0 436 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
437 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
13ac695e 438 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
511e6bc0 439
440 /* for no enable pfc mode */
441 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
13ac695e
S		 442 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
443 dsaf_set_field(o_sbm_bp_cfg,
511e6bc0 444 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
445 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128);
13ac695e 446 dsaf_set_field(o_sbm_bp_cfg,
511e6bc0 447 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
448 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192);
13ac695e 449 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
511e6bc0 450 }
451
452 /* PPE */
453 for (i = 0; i < DSAF_COMM_CHN; i++) {
454 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
13ac695e
S		 455 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
456 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
511e6bc0 457 DSAF_SBM_CFG2_SET_BUF_NUM_S, 10);
13ac695e 458 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
511e6bc0 459 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12);
13ac695e 460 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
511e6bc0 461 }
462
463 /* RoCEE */
464 for (i = 0; i < DSAF_COMM_CHN; i++) {
465 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
13ac695e
S		 466 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
467 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
511e6bc0 468 DSAF_SBM_CFG2_SET_BUF_NUM_S, 2);
13ac695e 469 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
511e6bc0 470 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4);
13ac695e
S		 471 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
472 }
473}
474
475static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
476{
477 u32 o_sbm_bp_cfg;
478 u32 reg;
479 u32 i;
480
481 /* XGE */
482 for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) {
483 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
484 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
485 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
486 DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256);
487 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
488 DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
489 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
490 DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
491 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
492
493 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
494 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
495 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
496 DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
497 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
498 DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
499 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
500
501 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
502 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
503 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
504 DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104);
505 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
506 DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128);
507 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
508
509 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
510 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
511 dsaf_set_field(o_sbm_bp_cfg,
512 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
8ae7b8a5 513 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 48);
13ac695e
S		 514 dsaf_set_field(o_sbm_bp_cfg,
515 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
8ae7b8a5 516 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 80);
13ac695e
S		 517 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
518
519 /* for no enable pfc mode */
520 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
521 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
522 dsaf_set_field(o_sbm_bp_cfg,
523 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M,
8ae7b8a5 524 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 192);
13ac695e
S		 525 dsaf_set_field(o_sbm_bp_cfg,
526 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M,
8ae7b8a5 527 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 240);
13ac695e
S		 528 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
529 }
530
531 /* PPE */
8ae7b8a5
DH		 532 for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) {
533 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
534 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
535 dsaf_set_field(o_sbm_bp_cfg,
536 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M,
537 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2);
538 dsaf_set_field(o_sbm_bp_cfg,
539 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M,
540 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3);
541 dsaf_set_field(o_sbm_bp_cfg,
542 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M,
543 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52);
544 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
545 }
546
13ac695e
S		 547 /* RoCEE */
548 for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) {
549 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
550 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
8ae7b8a5
DH		 551 dsaf_set_field(o_sbm_bp_cfg,
552 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M,
553 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2);
554 dsaf_set_field(o_sbm_bp_cfg,
555 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M,
556 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4);
13ac695e 557 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
511e6bc0 558 }
559}
560
561/**
562 * hns_dsaf_voq_bp_all_thrd_cfg - voq
563 * @dsaf_id: dsa fabric id
564 */
565static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev)
566{
567 u32 voq_bp_all_thrd;
568 u32 i;
569
570 for (i = 0; i < DSAF_VOQ_NUM; i++) {
571 voq_bp_all_thrd = dsaf_read_dev(
572 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i);
573 if (i < DSAF_XGE_NUM) {
574 dsaf_set_field(voq_bp_all_thrd,
575 DSAF_VOQ_BP_ALL_DOWNTHRD_M,
576 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930);
577 dsaf_set_field(voq_bp_all_thrd,
578 DSAF_VOQ_BP_ALL_UPTHRD_M,
579 DSAF_VOQ_BP_ALL_UPTHRD_S, 950);
580 } else {
581 dsaf_set_field(voq_bp_all_thrd,
582 DSAF_VOQ_BP_ALL_DOWNTHRD_M,
583 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220);
584 dsaf_set_field(voq_bp_all_thrd,
585 DSAF_VOQ_BP_ALL_UPTHRD_M,
586 DSAF_VOQ_BP_ALL_UPTHRD_S, 230);
587 }
588 dsaf_write_dev(
589 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i,
590 voq_bp_all_thrd);
591 }
592}
593
153b1d48
KY		 594static void hns_dsaf_tbl_tcam_match_cfg(
595 struct dsaf_device *dsaf_dev,
596 struct dsaf_tbl_tcam_data *ptbl_tcam_data)
597{
598 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_L_REG,
599 ptbl_tcam_data->tbl_tcam_data_low);
600 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_H_REG,
601 ptbl_tcam_data->tbl_tcam_data_high);
602}
603
511e6bc0 604/**
605 * hns_dsaf_tbl_tcam_data_cfg - tbl
606 * @dsaf_id: dsa fabric id
607 * @ptbl_tcam_data: addr
608 */
609static void hns_dsaf_tbl_tcam_data_cfg(
610 struct dsaf_device *dsaf_dev,
611 struct dsaf_tbl_tcam_data *ptbl_tcam_data)
612{
613 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
614 ptbl_tcam_data->tbl_tcam_data_low);
615 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
616 ptbl_tcam_data->tbl_tcam_data_high);
617}
618
619/**
620 * dsaf_tbl_tcam_mcast_cfg - tbl
621 * @dsaf_id: dsa fabric id
622 * @ptbl_tcam_mcast: addr
623 */
624static void hns_dsaf_tbl_tcam_mcast_cfg(
625 struct dsaf_device *dsaf_dev,
626 struct dsaf_tbl_tcam_mcast_cfg *mcast)
627{
628 u32 mcast_cfg4;
629
630 mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
631 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S,
632 mcast->tbl_mcast_item_vld);
633 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S,
634 mcast->tbl_mcast_old_en);
635 dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
636 DSAF_TBL_MCAST_CFG4_VM128_112_S,
637 mcast->tbl_mcast_port_msk[4]);
638 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
639
640 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
641 mcast->tbl_mcast_port_msk[3]);
642
643 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
644 mcast->tbl_mcast_port_msk[2]);
645
646 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
647 mcast->tbl_mcast_port_msk[1]);
648
649 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
650 mcast->tbl_mcast_port_msk[0]);
651}
652
653/**
654 * hns_dsaf_tbl_tcam_ucast_cfg - tbl
655 * @dsaf_id: dsa fabric id
656 * @ptbl_tcam_ucast: addr
657 */
658static void hns_dsaf_tbl_tcam_ucast_cfg(
659 struct dsaf_device *dsaf_dev,
660 struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast)
661{
662 u32 ucast_cfg1;
663
664 ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
665 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S,
666 tbl_tcam_ucast->tbl_ucast_mac_discard);
667 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S,
668 tbl_tcam_ucast->tbl_ucast_item_vld);
669 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S,
670 tbl_tcam_ucast->tbl_ucast_old_en);
671 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S,
672 tbl_tcam_ucast->tbl_ucast_dvc);
673 dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
674 DSAF_TBL_UCAST_CFG1_OUT_PORT_S,
675 tbl_tcam_ucast->tbl_ucast_out_port);
676 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
677}
678
679/**
680 * hns_dsaf_tbl_line_cfg - tbl
681 * @dsaf_id: dsa fabric id
682 * @ptbl_lin: addr
683 */
684static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev,
685 struct dsaf_tbl_line_cfg *tbl_lin)
686{
687 u32 tbl_line;
688
689 tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG);
690 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S,
691 tbl_lin->tbl_line_mac_discard);
692 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S,
693 tbl_lin->tbl_line_dvc);
694 dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
695 DSAF_TBL_LINE_CFG_OUT_PORT_S,
696 tbl_lin->tbl_line_out_port);
697 dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
698}
699
700/**
701 * hns_dsaf_tbl_tcam_mcast_pul - tbl
702 * @dsaf_id: dsa fabric id
703 */
704static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev)
705{
706 u32 o_tbl_pul;
707
708 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
709 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
710 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
711 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
712 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
713}
714
715/**
716 * hns_dsaf_tbl_line_pul - tbl
717 * @dsaf_id: dsa fabric id
718 */
719static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev)
720{
721 u32 tbl_pul;
722
723 tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
724 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1);
725 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
726 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0);
727 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
728}
729
730/**
731 * hns_dsaf_tbl_tcam_data_mcast_pul - tbl
732 * @dsaf_id: dsa fabric id
733 */
734static void hns_dsaf_tbl_tcam_data_mcast_pul(
735 struct dsaf_device *dsaf_dev)
736{
737 u32 o_tbl_pul;
738
739 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
740 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
741 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
742 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
743 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
744 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
745 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
746}
747
748/**
749 * hns_dsaf_tbl_tcam_data_ucast_pul - tbl
750 * @dsaf_id: dsa fabric id
751 */
752static void hns_dsaf_tbl_tcam_data_ucast_pul(
753 struct dsaf_device *dsaf_dev)
754{
755 u32 o_tbl_pul;
756
757 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
758 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
759 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1);
760 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
761 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
762 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0);
763 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
764}
765
4568637f 766void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en)
767{
1f5fa2dd 768 if (AE_IS_VER1(dsaf_dev->dsaf_ver) && !HNS_DSAF_IS_DEBUG(dsaf_dev))
89a44093
YZZ		 769 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG,
770 DSAF_CFG_MIX_MODE_S, !!en);
4568637f 771}
772
511e6bc0 773/**
774 * hns_dsaf_tbl_stat_en - tbl
775 * @dsaf_id: dsa fabric id
776 * @ptbl_stat_en: addr
777 */
778static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev)
779{
780 u32 o_tbl_ctrl;
781
782 o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG);
783 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1);
784 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1);
785 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1);
786 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1);
787 dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
788}
789
790/**
791 * hns_dsaf_rocee_bp_en - rocee back press enable
792 * @dsaf_id: dsa fabric id
793 */
794static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
795{
6f80563c
QX		 796 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
797 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
798 DSAF_FC_XGE_TX_PAUSE_S, 1);
511e6bc0 799}
800
801/* set msk for dsaf exception irq*/
802static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev,
803 u32 chnn_num, u32 mask_set)
804{
805 dsaf_write_dev(dsaf_dev,
806 DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set);
807}
808
809static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev,
810 u32 chnn_num, u32 msk_set)
811{
812 dsaf_write_dev(dsaf_dev,
813 DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set);
814}
815
816static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev,
817 u32 chnn, u32 msk_set)
818{
819 dsaf_write_dev(dsaf_dev,
820 DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set);
821}
822
823static void
824hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set)
825{
826 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
827}
828
829/* clr dsaf exception irq*/
830static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev,
831 u32 chnn_num, u32 int_src)
832{
833 dsaf_write_dev(dsaf_dev,
834 DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src);
835}
836
837static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev,
838 u32 chnn, u32 int_src)
839{
840 dsaf_write_dev(dsaf_dev,
841 DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src);
842}
843
844static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev,
845 u32 chnn, u32 int_src)
846{
847 dsaf_write_dev(dsaf_dev,
848 DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src);
849}
850
851static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev,
852 u32 int_src)
853{
854 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
855}
856
857/**
858 * hns_dsaf_single_line_tbl_cfg - INT
859 * @dsaf_id: dsa fabric id
860 * @address:
861 * @ptbl_line:
862 */
863static void hns_dsaf_single_line_tbl_cfg(
864 struct dsaf_device *dsaf_dev,
865 u32 address, struct dsaf_tbl_line_cfg *ptbl_line)
866{
b7623816
DH		 867 spin_lock_bh(&dsaf_dev->tcam_lock);
868
511e6bc0 869 /*Write Addr*/
870 hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address);
871
872 /*Write Line*/
873 hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line);
874
875 /*Write Plus*/
876 hns_dsaf_tbl_line_pul(dsaf_dev);
b7623816
DH		 877
878 spin_unlock_bh(&dsaf_dev->tcam_lock);
511e6bc0 879}
880
881/**
882 * hns_dsaf_tcam_uc_cfg - INT
883 * @dsaf_id: dsa fabric id
884 * @address,
885 * @ptbl_tcam_data,
886 */
887static void hns_dsaf_tcam_uc_cfg(
888 struct dsaf_device *dsaf_dev, u32 address,
889 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
890 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
891{
b7623816
DH		 892 spin_lock_bh(&dsaf_dev->tcam_lock);
893
511e6bc0 894 /*Write Addr*/
895 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
896 /*Write Tcam Data*/
897 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
898 /*Write Tcam Ucast*/
899 hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast);
900 /*Write Plus*/
901 hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
b7623816
DH		 902
903 spin_unlock_bh(&dsaf_dev->tcam_lock);
511e6bc0 904}
905
906/**
153b1d48
KY		 907 * hns_dsaf_tcam_mc_cfg - cfg the tcam for mc
908 * @dsaf_dev: dsa fabric device struct pointer
909 * @address: tcam index
910 * @ptbl_tcam_data: tcam data struct pointer
911 * @ptbl_tcam_mcast: tcam mask struct pointer, it must be null for HNSv1
511e6bc0 912 */
913static void hns_dsaf_tcam_mc_cfg(
914 struct dsaf_device *dsaf_dev, u32 address,
915 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
153b1d48 916 struct dsaf_tbl_tcam_data *ptbl_tcam_mask,
511e6bc0 917 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
918{
b7623816
DH		 919 spin_lock_bh(&dsaf_dev->tcam_lock);
920
511e6bc0 921 /*Write Addr*/
922 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
923 /*Write Tcam Data*/
924 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
925 /*Write Tcam Mcast*/
926 hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast);
153b1d48
KY		 927 /* Write Match Data */
928 if (ptbl_tcam_mask)
929 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, ptbl_tcam_mask);
930
931 /* Write Puls */
511e6bc0 932 hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
b7623816
DH		 933
934 spin_unlock_bh(&dsaf_dev->tcam_lock);
511e6bc0 935}
936
937/**
938 * hns_dsaf_tcam_mc_invld - INT
939 * @dsaf_id: dsa fabric id
940 * @address
941 */
942static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address)
943{
b7623816
DH		 944 spin_lock_bh(&dsaf_dev->tcam_lock);
945
511e6bc0 946 /*Write Addr*/
947 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
948
949 /*write tcam mcast*/
950 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
951 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
952 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
953 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
954 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
955
956 /*Write Plus*/
957 hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev);
b7623816
DH		 958
959 spin_unlock_bh(&dsaf_dev->tcam_lock);
511e6bc0 960}
961
962/**
963 * hns_dsaf_tcam_uc_get - INT
964 * @dsaf_id: dsa fabric id
965 * @address
966 * @ptbl_tcam_data
967 * @ptbl_tcam_ucast
968 */
969static void hns_dsaf_tcam_uc_get(
970 struct dsaf_device *dsaf_dev, u32 address,
971 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
972 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
973{
974 u32 tcam_read_data0;
975 u32 tcam_read_data4;
976
b7623816
DH		 977 spin_lock_bh(&dsaf_dev->tcam_lock);
978
511e6bc0 979 /*Write Addr*/
980 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
981
982 /*read tcam item puls*/
983 hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
984
985 /*read tcam data*/
986 ptbl_tcam_data->tbl_tcam_data_high
511e6bc0 987 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
f56c1b3d
DH		 988 ptbl_tcam_data->tbl_tcam_data_low
989 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
511e6bc0 990
991 /*read tcam mcast*/
992 tcam_read_data0 = dsaf_read_dev(dsaf_dev,
993 DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
994 tcam_read_data4 = dsaf_read_dev(dsaf_dev,
995 DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
996
997 ptbl_tcam_ucast->tbl_ucast_item_vld
998 = dsaf_get_bit(tcam_read_data4,
999 DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1000 ptbl_tcam_ucast->tbl_ucast_old_en
1001 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1002 ptbl_tcam_ucast->tbl_ucast_mac_discard
1003 = dsaf_get_bit(tcam_read_data0,
1004 DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S);
1005 ptbl_tcam_ucast->tbl_ucast_out_port
1006 = dsaf_get_field(tcam_read_data0,
1007 DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
1008 DSAF_TBL_UCAST_CFG1_OUT_PORT_S);
1009 ptbl_tcam_ucast->tbl_ucast_dvc
1010 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S);
b7623816
DH		 1011
1012 spin_unlock_bh(&dsaf_dev->tcam_lock);
511e6bc0 1013}
1014
1015/**
1016 * hns_dsaf_tcam_mc_get - INT
1017 * @dsaf_id: dsa fabric id
1018 * @address
1019 * @ptbl_tcam_data
1020 * @ptbl_tcam_ucast
1021 */
1022static void hns_dsaf_tcam_mc_get(
1023 struct dsaf_device *dsaf_dev, u32 address,
1024 struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1025 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
1026{
1027 u32 data_tmp;
1028
b7623816
DH		 1029 spin_lock_bh(&dsaf_dev->tcam_lock);
1030
511e6bc0 1031 /*Write Addr*/
1032 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1033
1034 /*read tcam item puls*/
1035 hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1036
1037 /*read tcam data*/
1038 ptbl_tcam_data->tbl_tcam_data_high =
511e6bc0 1039 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
f56c1b3d
DH		 1040 ptbl_tcam_data->tbl_tcam_data_low =
1041 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
511e6bc0 1042
1043 /*read tcam mcast*/
1044 ptbl_tcam_mcast->tbl_mcast_port_msk[0] =
1045 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1046 ptbl_tcam_mcast->tbl_mcast_port_msk[1] =
1047 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
1048 ptbl_tcam_mcast->tbl_mcast_port_msk[2] =
1049 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
1050 ptbl_tcam_mcast->tbl_mcast_port_msk[3] =
1051 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
1052
1053 data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1054 ptbl_tcam_mcast->tbl_mcast_item_vld =
1055 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1056 ptbl_tcam_mcast->tbl_mcast_old_en =
1057 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1058 ptbl_tcam_mcast->tbl_mcast_port_msk[4] =
1059 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M,
1060 DSAF_TBL_MCAST_CFG4_VM128_112_S);
b7623816
DH		 1061
1062 spin_unlock_bh(&dsaf_dev->tcam_lock);
511e6bc0 1063}
1064
1065/**
1066 * hns_dsaf_tbl_line_init - INT
1067 * @dsaf_id: dsa fabric id
1068 */
1069static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev)
1070{
1071 u32 i;
1072 /* defaultly set all lineal mac table entry resulting discard */
1073 struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} };
1074
1075 for (i = 0; i < DSAF_LINE_SUM; i++)
1076 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line);
1077}
1078
1079/**
1080 * hns_dsaf_tbl_tcam_init - INT
1081 * @dsaf_id: dsa fabric id
1082 */
1083static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
1084{
1085 u32 i;
1086 struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} };
1087 struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} };
1088
1089 /*tcam tbl*/
1090 for (i = 0; i < DSAF_TCAM_SUM; i++)
1091 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast);
1092}
1093
1094/**
1095 * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg
1096 * @mac_cb: mac contrl block
1097 */
1098static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
5ada37b5 1099 int mac_id, int tc_en)
511e6bc0 1100{
5ada37b5
L		 1101 dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
1102}
1103
1104static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev,
1105 int mac_id, int tx_en, int rx_en)
1106{
1107 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1108 if (!tx_en || !rx_en)
1109 dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n");
1110
1111 return;
1112 }
1113
1114 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1115 DSAF_PFC_PAUSE_RX_EN_B, !!rx_en);
1116 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1117 DSAF_PFC_PAUSE_TX_EN_B, !!tx_en);
1118}
1119
1120int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1121 u32 en)
1122{
1123 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
14ae335a 1124 if (!en) {
5ada37b5 1125 dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n");
14ae335a
QX		 1126 return -EINVAL;
1127 }
5ada37b5
L		 1128 }
1129
1130 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1131 DSAF_MAC_PAUSE_RX_EN_B, !!en);
1132
1133 return 0;
1134}
1135
1136void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1137 u32 *en)
1138{
1139 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1140 *en = 1;
511e6bc0 1141 else
5ada37b5
L		 1142 *en = dsaf_get_dev_bit(dsaf_dev,
1143 DSAF_PAUSE_CFG_REG + mac_id * 4,
1144 DSAF_MAC_PAUSE_RX_EN_B);
511e6bc0 1145}
1146
1147/**
1148 * hns_dsaf_tbl_tcam_init - INT
1149 * @dsaf_id: dsa fabric id
1150 * @dsaf_mode
1151 */
1152static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
1153{
1154 u32 i;
1155 u32 o_dsaf_cfg;
5ada37b5 1156 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
511e6bc0 1157
1158 o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
1159 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
1160 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode);
1161 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0);
1162 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0);
1163 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0);
1164 dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
1165
1166 hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1);
1167 hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD);
1168
1169 /* set 22 queue per tx ppe engine, only used in switch mode */
1170 hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE);
1171
4568637f 1172 /* set promisc def queue id */
1173 hns_dsaf_mix_def_qid_cfg(dsaf_dev);
1174
68c222a6 1175 /* set inner loopback queue id */
1176 hns_dsaf_inner_qid_cfg(dsaf_dev);
1177
511e6bc0 1178 /* in non switch mode, set all port to access mode */
1179 hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
1180
1181 /*set dsaf pfc to 0 for parseing rx pause*/
5ada37b5 1182 for (i = 0; i < DSAF_COMM_CHN; i++) {
511e6bc0 1183 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
5ada37b5
L		 1184 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1);
1185 }
511e6bc0 1186
1187 /*msk and clr exception irqs */
1188 for (i = 0; i < DSAF_COMM_CHN; i++) {
1189 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful);
1190 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful);
1191 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful);
1192
1193 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful);
1194 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful);
1195 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful);
1196 }
1197 hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful);
1198 hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful);
1199}
1200
1201/**
1202 * hns_dsaf_inode_init - INT
1203 * @dsaf_id: dsa fabric id
1204 */
1205static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev)
1206{
1207 u32 reg;
1208 u32 tc_cfg;
1209 u32 i;
1210
1211 if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE)
1212 tc_cfg = HNS_DSAF_I4TC_CFG;
1213 else
1214 tc_cfg = HNS_DSAF_I8TC_CFG;
1215
13ac695e
S		 1216 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1217 for (i = 0; i < DSAF_INODE_NUM; i++) {
1218 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1219 dsaf_set_dev_field(dsaf_dev, reg,
1220 DSAF_INODE_IN_PORT_NUM_M,
1221 DSAF_INODE_IN_PORT_NUM_S,
1222 i % DSAF_XGE_NUM);
1223 }
1224 } else {
1225 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) {
1226 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1227 dsaf_set_dev_field(dsaf_dev, reg,
1228 DSAF_INODE_IN_PORT_NUM_M,
1229 DSAF_INODE_IN_PORT_NUM_S, 0);
1230 dsaf_set_dev_field(dsaf_dev, reg,
1231 DSAFV2_INODE_IN_PORT1_NUM_M,
1232 DSAFV2_INODE_IN_PORT1_NUM_S, 1);
1233 dsaf_set_dev_field(dsaf_dev, reg,
1234 DSAFV2_INODE_IN_PORT2_NUM_M,
1235 DSAFV2_INODE_IN_PORT2_NUM_S, 2);
1236 dsaf_set_dev_field(dsaf_dev, reg,
1237 DSAFV2_INODE_IN_PORT3_NUM_M,
1238 DSAFV2_INODE_IN_PORT3_NUM_S, 3);
1239 dsaf_set_dev_field(dsaf_dev, reg,
1240 DSAFV2_INODE_IN_PORT4_NUM_M,
1241 DSAFV2_INODE_IN_PORT4_NUM_S, 4);
1242 dsaf_set_dev_field(dsaf_dev, reg,
1243 DSAFV2_INODE_IN_PORT5_NUM_M,
1244 DSAFV2_INODE_IN_PORT5_NUM_S, 5);
1245 }
1246 }
511e6bc0 1247 for (i = 0; i < DSAF_INODE_NUM; i++) {
511e6bc0 1248 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i;
1249 dsaf_write_dev(dsaf_dev, reg, tc_cfg);
1250 }
1251}
1252
1253/**
1254 * hns_dsaf_sbm_init - INT
1255 * @dsaf_id: dsa fabric id
1256 */
1257static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev)
1258{
1259 u32 flag;
13ac695e 1260 u32 finish_msk;
511e6bc0 1261 u32 cnt = 0;
1262 int ret;
1263
13ac695e
S		 1264 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1265 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev);
1266 finish_msk = DSAF_SRAM_INIT_OVER_M;
1267 } else {
1268 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev);
1269 finish_msk = DSAFV2_SRAM_INIT_OVER_M;
1270 }
511e6bc0 1271
1272 /* enable sbm chanel, disable sbm chanel shcut function*/
1273 hns_dsaf_sbm_cfg(dsaf_dev);
1274
1275 /* enable sbm mib */
1276 ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev);
1277 if (ret) {
1278 dev_err(dsaf_dev->dev,
1279 "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n",
1280 dsaf_dev->ae_dev.name, ret);
1281 return ret;
1282 }
1283
1284 /* enable sbm initial link sram */
1285 hns_dsaf_sbm_link_sram_init_en(dsaf_dev);
1286
1287 do {
1288 usleep_range(200, 210);/*udelay(200);*/
13ac695e
S		 1289 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG,
1290 finish_msk, DSAF_SRAM_INIT_OVER_S);
511e6bc0 1291 cnt++;
13ac695e
S		 1292 } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) &&
1293 cnt < DSAF_CFG_READ_CNT);
511e6bc0 1294
13ac695e 1295 if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) {
511e6bc0 1296 dev_err(dsaf_dev->dev,
1297 "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n",
1298 dsaf_dev->ae_dev.name, flag, cnt);
1299 return -ENODEV;
1300 }
1301
1302 hns_dsaf_rocee_bp_en(dsaf_dev);
1303
1304 return 0;
1305}
1306
1307/**
1308 * hns_dsaf_tbl_init - INT
1309 * @dsaf_id: dsa fabric id
1310 */
1311static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev)
1312{
1313 hns_dsaf_tbl_stat_en(dsaf_dev);
1314
1315 hns_dsaf_tbl_tcam_init(dsaf_dev);
1316 hns_dsaf_tbl_line_init(dsaf_dev);
1317}
1318
1319/**
1320 * hns_dsaf_voq_init - INT
1321 * @dsaf_id: dsa fabric id
1322 */
1323static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev)
1324{
1325 hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev);
1326}
1327
1328/**
1329 * hns_dsaf_init_hw - init dsa fabric hardware
1330 * @dsaf_dev: dsa fabric device struct pointer
1331 */
1332static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev)
1333{
1334 int ret;
1335
1336 dev_dbg(dsaf_dev->dev,
1337 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name);
1338
a24274aa 1339 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
511e6bc0 1340 mdelay(10);
a24274aa 1341 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1);
511e6bc0 1342
1343 hns_dsaf_comm_init(dsaf_dev);
1344
1345 /*init XBAR_INODE*/
1346 hns_dsaf_inode_init(dsaf_dev);
1347
1348 /*init SBM*/
1349 ret = hns_dsaf_sbm_init(dsaf_dev);
1350 if (ret)
1351 return ret;
1352
1353 /*init TBL*/
1354 hns_dsaf_tbl_init(dsaf_dev);
1355
1356 /*init VOQ*/
1357 hns_dsaf_voq_init(dsaf_dev);
1358
1359 return 0;
1360}
1361
1362/**
1363 * hns_dsaf_remove_hw - uninit dsa fabric hardware
1364 * @dsaf_dev: dsa fabric device struct pointer
1365 */
1366static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev)
1367{
1368 /*reset*/
a24274aa 1369 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
511e6bc0 1370}
1371
1372/**
1373 * hns_dsaf_init - init dsa fabric
1374 * @dsaf_dev: dsa fabric device struct pointer
1375 * retuen 0 - success , negative --fail
1376 */
1377static int hns_dsaf_init(struct dsaf_device *dsaf_dev)
1378{
1379 struct dsaf_drv_priv *priv =
1380 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1381 u32 i;
1382 int ret;
1383
89a44093
YZZ		 1384 if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1385 return 0;
1386
1f5fa2dd
KY		 1387 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1388 dsaf_dev->tcam_max_num = DSAF_TCAM_SUM;
1389 else
1390 dsaf_dev->tcam_max_num =
1391 DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM;
1392
b7623816 1393 spin_lock_init(&dsaf_dev->tcam_lock);
511e6bc0 1394 ret = hns_dsaf_init_hw(dsaf_dev);
1395 if (ret)
1396 return ret;
1397
1398 /* malloc mem for tcam mac key(vlan+mac) */
1399 priv->soft_mac_tbl = vzalloc(sizeof(*priv->soft_mac_tbl)
1400 * DSAF_TCAM_SUM);
1401 if (!priv->soft_mac_tbl) {
1402 ret = -ENOMEM;
1403 goto remove_hw;
1404 }
1405
1406 /*all entry invall */
1407 for (i = 0; i < DSAF_TCAM_SUM; i++)
1408 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX;
1409
1410 return 0;
1411
1412remove_hw:
1413 hns_dsaf_remove_hw(dsaf_dev);
1414 return ret;
1415}
1416
1417/**
1418 * hns_dsaf_free - free dsa fabric
1419 * @dsaf_dev: dsa fabric device struct pointer
1420 */
1421static void hns_dsaf_free(struct dsaf_device *dsaf_dev)
1422{
1423 struct dsaf_drv_priv *priv =
1424 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1425
1426 hns_dsaf_remove_hw(dsaf_dev);
1427
1428 /* free all mac mem */
1429 vfree(priv->soft_mac_tbl);
1430 priv->soft_mac_tbl = NULL;
1431}
1432
1433/**
1434 * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry
1435 * @dsaf_dev: dsa fabric device struct pointer
1436 * @mac_key: mac entry struct pointer
1437 */
1438static u16 hns_dsaf_find_soft_mac_entry(
1439 struct dsaf_device *dsaf_dev,
1440 struct dsaf_drv_tbl_tcam_key *mac_key)
1441{
1442 struct dsaf_drv_priv *priv =
1443 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1444 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1445 u32 i;
1446
1447 soft_mac_entry = priv->soft_mac_tbl;
1f5fa2dd 1448 for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
511e6bc0 1449 /* invall tab entry */
1450 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) &&
1451 (soft_mac_entry->tcam_key.high.val == mac_key->high.val) &&
1452 (soft_mac_entry->tcam_key.low.val == mac_key->low.val))
1453 /* return find result --soft index */
1454 return soft_mac_entry->index;
1455
1456 soft_mac_entry++;
1457 }
1458 return DSAF_INVALID_ENTRY_IDX;
1459}
1460
1461/**
1462 * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry
1463 * @dsaf_dev: dsa fabric device struct pointer
1464 */
1465static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev)
1466{
1467 struct dsaf_drv_priv *priv =
1468 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1469 struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1470 u32 i;
1471
1472 soft_mac_entry = priv->soft_mac_tbl;
1f5fa2dd 1473 for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
511e6bc0 1474 /* inv all entry */
1475 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1476 /* return find result --soft index */
1477 return i;
1478
1479 soft_mac_entry++;
1480 }
1481 return DSAF_INVALID_ENTRY_IDX;
1482}
1483
1484/**
1485 * hns_dsaf_set_mac_key - set mac key
1486 * @dsaf_dev: dsa fabric device struct pointer
1487 * @mac_key: tcam key pointer
1488 * @vlan_id: vlan id
1489 * @in_port_num: input port num
1490 * @addr: mac addr
1491 */
1492static void hns_dsaf_set_mac_key(
1493 struct dsaf_device *dsaf_dev,
1494 struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num,
1495 u8 *addr)
1496{
1497 u8 port;
1498
1499 if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE)
1500 /*DSAF mode : in port id fixed 0*/
1501 port = 0;
1502 else
1503 /*non-dsaf mode*/
1504 port = in_port_num;
1505
1506 mac_key->high.bits.mac_0 = addr[0];
1507 mac_key->high.bits.mac_1 = addr[1];
1508 mac_key->high.bits.mac_2 = addr[2];
1509 mac_key->high.bits.mac_3 = addr[3];
1510 mac_key->low.bits.mac_4 = addr[4];
1511 mac_key->low.bits.mac_5 = addr[5];
5483bfcb
QX		 1512 dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_VLAN_M,
1513 DSAF_TBL_TCAM_KEY_VLAN_S, vlan_id);
1514 dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_PORT_M,
1515 DSAF_TBL_TCAM_KEY_PORT_S, port);
1516
1517 mac_key->low.bits.port_vlan = le16_to_cpu(mac_key->low.bits.port_vlan);
511e6bc0 1518}
1519
1520/**
1521 * hns_dsaf_set_mac_uc_entry - set mac uc-entry
1522 * @dsaf_dev: dsa fabric device struct pointer
1523 * @mac_entry: uc-mac entry
1524 */
1525int hns_dsaf_set_mac_uc_entry(
1526 struct dsaf_device *dsaf_dev,
1527 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1528{
1529 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1530 struct dsaf_drv_tbl_tcam_key mac_key;
1531 struct dsaf_tbl_tcam_ucast_cfg mac_data;
1532 struct dsaf_drv_priv *priv =
1533 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1534 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
c9c0b370 1535 struct dsaf_tbl_tcam_data tcam_data;
511e6bc0 1536
1537 /* mac addr check */
1538 if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1539 MAC_IS_BROADCAST(mac_entry->addr) ||
1540 MAC_IS_MULTICAST(mac_entry->addr)) {
98900a80
AS		 1541 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n",
1542 dsaf_dev->ae_dev.name, mac_entry->addr);
511e6bc0 1543 return -EINVAL;
1544 }
1545
1546 /* config key */
1547 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1548 mac_entry->in_port_num, mac_entry->addr);
1549
1550 /* entry ie exist? */
1551 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1552 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1553 /*if has not inv entry,find a empty entry */
1554 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1555 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1556 /* has not empty,return error */
1557 dev_err(dsaf_dev->dev,
1558 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1559 dsaf_dev->ae_dev.name,
1560 mac_key.high.val, mac_key.low.val);
1561 return -EINVAL;
1562 }
1563 }
1564
1565 dev_dbg(dsaf_dev->dev,
1566 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1567 dsaf_dev->ae_dev.name, mac_key.high.val,
1568 mac_key.low.val, entry_index);
1569
1570 /* config hardware entry */
1571 mac_data.tbl_ucast_item_vld = 1;
1572 mac_data.tbl_ucast_mac_discard = 0;
1573 mac_data.tbl_ucast_old_en = 0;
1574 /* default config dvc to 0 */
1575 mac_data.tbl_ucast_dvc = 0;
1576 mac_data.tbl_ucast_out_port = mac_entry->port_num;
c9c0b370
QX		 1577 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val);
1578 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val);
1579
1580 hns_dsaf_tcam_uc_cfg(dsaf_dev, entry_index, &tcam_data, &mac_data);
511e6bc0 1581
1582 /* config software entry */
1583 soft_mac_entry += entry_index;
1584 soft_mac_entry->index = entry_index;
1585 soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1586 soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1587
1588 return 0;
1589}
1590
1591/**
1592 * hns_dsaf_set_mac_mc_entry - set mac mc-entry
1593 * @dsaf_dev: dsa fabric device struct pointer
1594 * @mac_entry: mc-mac entry
1595 */
1596int hns_dsaf_set_mac_mc_entry(
1597 struct dsaf_device *dsaf_dev,
1598 struct dsaf_drv_mac_multi_dest_entry *mac_entry)
1599{
1600 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1601 struct dsaf_drv_tbl_tcam_key mac_key;
1602 struct dsaf_tbl_tcam_mcast_cfg mac_data;
1603 struct dsaf_drv_priv *priv =
1604 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1605 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1606 struct dsaf_drv_tbl_tcam_key tmp_mac_key;
1607
1608 /* mac addr check */
1609 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
98900a80
AS		 1610 dev_err(dsaf_dev->dev, "set uc %s Mac %pM err!\n",
1611 dsaf_dev->ae_dev.name, mac_entry->addr);
511e6bc0 1612 return -EINVAL;
1613 }
1614
1615 /*config key */
1616 hns_dsaf_set_mac_key(dsaf_dev, &mac_key,
1617 mac_entry->in_vlan_id,
1618 mac_entry->in_port_num, mac_entry->addr);
1619
1620 /* entry ie exist? */
1621 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1622 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1623 /*if hasnot, find enpty entry*/
1624 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1625 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1626 /*if hasnot empty, error*/
1627 dev_err(dsaf_dev->dev,
1628 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1629 dsaf_dev->ae_dev.name,
1630 mac_key.high.val, mac_key.low.val);
1631 return -EINVAL;
1632 }
1633
1634 /* config hardware entry */
1635 memset(mac_data.tbl_mcast_port_msk,
1636 0, sizeof(mac_data.tbl_mcast_port_msk));
1637 } else {
1638 /* config hardware entry */
1639 hns_dsaf_tcam_mc_get(
1640 dsaf_dev, entry_index,
1641 (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data);
1642 }
1643 mac_data.tbl_mcast_old_en = 0;
1644 mac_data.tbl_mcast_item_vld = 1;
1645 dsaf_set_field(mac_data.tbl_mcast_port_msk[0],
1646 0x3F, 0, mac_entry->port_mask[0]);
1647
1648 dev_dbg(dsaf_dev->dev,
1649 "set_uc_entry, %s key(%#x:%#x) entry_index%d\n",
1650 dsaf_dev->ae_dev.name, mac_key.high.val,
1651 mac_key.low.val, entry_index);
1652
1653 hns_dsaf_tcam_mc_cfg(
1654 dsaf_dev, entry_index,
153b1d48 1655 (struct dsaf_tbl_tcam_data *)(&mac_key), NULL, &mac_data);
511e6bc0 1656
1657 /* config software entry */
1658 soft_mac_entry += entry_index;
1659 soft_mac_entry->index = entry_index;
1660 soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1661 soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1662
1663 return 0;
1664}
1665
153b1d48
KY		 1666static void hns_dsaf_mc_mask_bit_clear(char *dst, const char *src)
1667{
1668 u16 *a = (u16 *)dst;
1669 const u16 *b = (const u16 *)src;
1670
1671 a[0] &= b[0];
1672 a[1] &= b[1];
1673 a[2] &= b[2];
1674}
1675
511e6bc0 1676/**
1677 * hns_dsaf_add_mac_mc_port - add mac mc-port
1678 * @dsaf_dev: dsa fabric device struct pointer
1679 * @mac_entry: mc-mac entry
1680 */
1681int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
1682 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1683{
1684 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1685 struct dsaf_drv_tbl_tcam_key mac_key;
153b1d48
KY		 1686 struct dsaf_drv_tbl_tcam_key mask_key;
1687 struct dsaf_tbl_tcam_data *pmask_key = NULL;
511e6bc0 1688 struct dsaf_tbl_tcam_mcast_cfg mac_data;
153b1d48 1689 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
511e6bc0 1690 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
153b1d48
KY		 1691 struct dsaf_tbl_tcam_data tcam_data;
1692 u8 mc_addr[ETH_ALEN];
1693 u8 *mc_mask;
511e6bc0 1694 int mskid;
1695
1696 /*chechk mac addr */
1697 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
98900a80
AS		 1698 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n",
1699 mac_entry->addr);
511e6bc0 1700 return -EINVAL;
1701 }
1702
153b1d48
KY		 1703 ether_addr_copy(mc_addr, mac_entry->addr);
1704 mc_mask = dsaf_dev->mac_cb[mac_entry->in_port_num]->mc_mask;
1705 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1706 /* prepare for key data setting */
1707 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1708
1709 /* config key mask */
1710 hns_dsaf_set_mac_key(dsaf_dev, &mask_key,
1711 0x0,
1712 0xff,
1713 mc_mask);
1714 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1715 }
1716
511e6bc0 1717 /*config key */
1718 hns_dsaf_set_mac_key(
1719 dsaf_dev, &mac_key, mac_entry->in_vlan_id,
153b1d48 1720 mac_entry->in_port_num, mc_addr);
511e6bc0 1721
1722 memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg));
1723
153b1d48 1724 /* check if the tcam is exist */
511e6bc0 1725 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1726 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1727 /*if hasnot , find a empty*/
1728 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1729 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1730 /*if hasnot empty, error*/
1731 dev_err(dsaf_dev->dev,
1732 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1733 dsaf_dev->ae_dev.name, mac_key.high.val,
1734 mac_key.low.val);
1735 return -EINVAL;
1736 }
1737 } else {
153b1d48
KY		 1738 /* if exist, add in */
1739 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data,
1740 &mac_data);
511e6bc0 1741 }
153b1d48 1742
511e6bc0 1743 /* config hardware entry */
1744 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1745 mskid = mac_entry->port_num;
1746 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1747 mskid = mac_entry->port_num -
1748 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1749 } else {
1750 dev_err(dsaf_dev->dev,
1751 "%s,pnum(%d)error,key(%#x:%#x)\n",
1752 dsaf_dev->ae_dev.name, mac_entry->port_num,
1753 mac_key.high.val, mac_key.low.val);
1754 return -EINVAL;
1755 }
1756 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1);
1757 mac_data.tbl_mcast_old_en = 0;
1758 mac_data.tbl_mcast_item_vld = 1;
1759
1760 dev_dbg(dsaf_dev->dev,
1761 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1762 dsaf_dev->ae_dev.name, mac_key.high.val,
1763 mac_key.low.val, entry_index);
1764
153b1d48
KY		 1765 tcam_data.tbl_tcam_data_high = mac_key.high.val;
1766 tcam_data.tbl_tcam_data_low = mac_key.low.val;
1767
1768 /* config mc entry with mask */
1769 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, &tcam_data,
1770 pmask_key, &mac_data);
511e6bc0 1771
1772 /*config software entry */
1773 soft_mac_entry += entry_index;
1774 soft_mac_entry->index = entry_index;
1775 soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1776 soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1777
1778 return 0;
1779}
1780
1781/**
1782 * hns_dsaf_del_mac_entry - del mac mc-port
1783 * @dsaf_dev: dsa fabric device struct pointer
1784 * @vlan_id: vlian id
1785 * @in_port_num: input port num
1786 * @addr : mac addr
1787 */
1788int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
1789 u8 in_port_num, u8 *addr)
1790{
1791 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1792 struct dsaf_drv_tbl_tcam_key mac_key;
1793 struct dsaf_drv_priv *priv =
1794 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1795 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1796
1797 /*check mac addr */
1798 if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) {
98900a80
AS		 1799 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n",
1800 addr);
511e6bc0 1801 return -EINVAL;
1802 }
1803
1804 /*config key */
1805 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr);
1806
1807 /*exist ?*/
1808 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1809 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1810 /*not exist, error */
1811 dev_err(dsaf_dev->dev,
1812 "del_mac_entry failed, %s Mac key(%#x:%#x)\n",
1813 dsaf_dev->ae_dev.name,
1814 mac_key.high.val, mac_key.low.val);
1815 return -EINVAL;
1816 }
1817 dev_dbg(dsaf_dev->dev,
1818 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1819 dsaf_dev->ae_dev.name, mac_key.high.val,
1820 mac_key.low.val, entry_index);
1821
1822 /*do del opt*/
1823 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1824
1825 /*del soft emtry */
1826 soft_mac_entry += entry_index;
1827 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1828
1829 return 0;
1830}
1831
1832/**
1833 * hns_dsaf_del_mac_mc_port - del mac mc- port
1834 * @dsaf_dev: dsa fabric device struct pointer
1835 * @mac_entry: mac entry
1836 */
1837int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
1838 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1839{
1840 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1841 struct dsaf_drv_tbl_tcam_key mac_key;
153b1d48 1842 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
511e6bc0 1843 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1844 u16 vlan_id;
1845 u8 in_port_num;
1846 struct dsaf_tbl_tcam_mcast_cfg mac_data;
153b1d48 1847 struct dsaf_tbl_tcam_data tcam_data;
511e6bc0 1848 int mskid;
1849 const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0};
153b1d48
KY		 1850 struct dsaf_drv_tbl_tcam_key mask_key;
1851 struct dsaf_tbl_tcam_data *pmask_key = NULL;
1852 u8 mc_addr[ETH_ALEN];
1853 u8 *mc_mask;
511e6bc0 1854
1855 if (!(void *)mac_entry) {
1856 dev_err(dsaf_dev->dev,
1857 "hns_dsaf_del_mac_mc_port mac_entry is NULL\n");
1858 return -EINVAL;
1859 }
1860
511e6bc0 1861 /*check mac addr */
1862 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
98900a80
AS		 1863 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n",
1864 mac_entry->addr);
511e6bc0 1865 return -EINVAL;
1866 }
1867
153b1d48
KY		 1868 /* always mask vlan_id field */
1869 ether_addr_copy(mc_addr, mac_entry->addr);
1870 mc_mask = dsaf_dev->mac_cb[mac_entry->in_port_num]->mc_mask;
511e6bc0 1871
153b1d48
KY		 1872 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1873 /* prepare for key data setting */
1874 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1875
1876 /* config key mask */
1877 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 0x00, 0xff, mc_addr);
1878
1879 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1880 }
1881
1882 /* get key info */
1883 vlan_id = mac_entry->in_vlan_id;
1884 in_port_num = mac_entry->in_port_num;
1885
1886 /* config key */
1887 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, mc_addr);
1888
1889 /* check if the tcam entry is exist */
511e6bc0 1890 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1891 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1892 /*find none */
1893 dev_err(dsaf_dev->dev,
1894 "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n",
1895 dsaf_dev->ae_dev.name,
1896 mac_key.high.val, mac_key.low.val);
1897 return -EINVAL;
1898 }
1899
1900 dev_dbg(dsaf_dev->dev,
1901 "del_mac_mc_port, %s key(%#x:%#x) index%d\n",
1902 dsaf_dev->ae_dev.name, mac_key.high.val,
1903 mac_key.low.val, entry_index);
1904
153b1d48
KY		 1905 /* read entry */
1906 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, &mac_data);
511e6bc0 1907
1908 /*del the port*/
1909 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1910 mskid = mac_entry->port_num;
1911 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1912 mskid = mac_entry->port_num -
1913 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1914 } else {
1915 dev_err(dsaf_dev->dev,
1916 "%s,pnum(%d)error,key(%#x:%#x)\n",
1917 dsaf_dev->ae_dev.name, mac_entry->port_num,
1918 mac_key.high.val, mac_key.low.val);
1919 return -EINVAL;
1920 }
1921 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0);
1922
1923 /*check non port, do del entry */
1924 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
1925 sizeof(mac_data.tbl_mcast_port_msk))) {
1926 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1927
1928 /* del soft entry */
1929 soft_mac_entry += entry_index;
1930 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
153b1d48
KY		 1931 } else { /* not zero, just del port, update */
1932 tcam_data.tbl_tcam_data_high = mac_key.high.val;
1933 tcam_data.tbl_tcam_data_low = mac_key.low.val;
1934
1935 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index,
1936 &tcam_data,
1937 pmask_key, &mac_data);
511e6bc0 1938 }
1939
1940 return 0;
1941}
1942
1943/**
1944 * hns_dsaf_get_mac_uc_entry - get mac uc entry
1945 * @dsaf_dev: dsa fabric device struct pointer
1946 * @mac_entry: mac entry
1947 */
1948int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev,
1949 struct dsaf_drv_mac_single_dest_entry *mac_entry)
1950{
1951 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1952 struct dsaf_drv_tbl_tcam_key mac_key;
1953
1954 struct dsaf_tbl_tcam_ucast_cfg mac_data;
c9c0b370 1955 struct dsaf_tbl_tcam_data tcam_data;
511e6bc0 1956
1957 /* check macaddr */
1958 if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1959 MAC_IS_BROADCAST(mac_entry->addr)) {
98900a80
AS		 1960 dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n",
1961 mac_entry->addr);
511e6bc0 1962 return -EINVAL;
1963 }
1964
1965 /*config key */
1966 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1967 mac_entry->in_port_num, mac_entry->addr);
1968
1969 /*check exist? */
1970 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1971 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1972 /*find none, error */
1973 dev_err(dsaf_dev->dev,
1974 "get_uc_entry failed, %s Mac key(%#x:%#x)\n",
1975 dsaf_dev->ae_dev.name,
1976 mac_key.high.val, mac_key.low.val);
1977 return -EINVAL;
1978 }
1979 dev_dbg(dsaf_dev->dev,
1980 "get_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1981 dsaf_dev->ae_dev.name, mac_key.high.val,
1982 mac_key.low.val, entry_index);
1983
c9c0b370
QX		 1984 /* read entry */
1985 hns_dsaf_tcam_uc_get(dsaf_dev, entry_index, &tcam_data, &mac_data);
1986
1987 mac_key.high.val = le32_to_cpu(tcam_data.tbl_tcam_data_high);
1988 mac_key.low.val = le32_to_cpu(tcam_data.tbl_tcam_data_low);
1989
511e6bc0 1990 mac_entry->port_num = mac_data.tbl_ucast_out_port;
1991
1992 return 0;
1993}
1994
1995/**
1996 * hns_dsaf_get_mac_mc_entry - get mac mc entry
1997 * @dsaf_dev: dsa fabric device struct pointer
1998 * @mac_entry: mac entry
1999 */
2000int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev,
2001 struct dsaf_drv_mac_multi_dest_entry *mac_entry)
2002{
2003 u16 entry_index = DSAF_INVALID_ENTRY_IDX;
2004 struct dsaf_drv_tbl_tcam_key mac_key;
2005
2006 struct dsaf_tbl_tcam_mcast_cfg mac_data;
2007
2008 /*check mac addr */
2009 if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
2010 MAC_IS_BROADCAST(mac_entry->addr)) {
98900a80
AS		 2011 dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n",
2012 mac_entry->addr);
511e6bc0 2013 return -EINVAL;
2014 }
2015
2016 /*config key */
2017 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
2018 mac_entry->in_port_num, mac_entry->addr);
2019
2020 /*check exist? */
2021 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2022 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
2023 /* find none, error */
2024 dev_err(dsaf_dev->dev,
2025 "get_mac_uc_entry failed, %s Mac key(%#x:%#x)\n",
2026 dsaf_dev->ae_dev.name, mac_key.high.val,
2027 mac_key.low.val);
2028 return -EINVAL;
2029 }
2030 dev_dbg(dsaf_dev->dev,
2031 "get_mac_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
2032 dsaf_dev->ae_dev.name, mac_key.high.val,
2033 mac_key.low.val, entry_index);
2034
2035 /*read entry */
2036 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index,
2037 (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
2038
2039 mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F;
2040 return 0;
2041}
2042
2043/**
2044 * hns_dsaf_get_mac_entry_by_index - get mac entry by tab index
2045 * @dsaf_dev: dsa fabric device struct pointer
2046 * @entry_index: tab entry index
2047 * @mac_entry: mac entry
2048 */
2049int hns_dsaf_get_mac_entry_by_index(
2050 struct dsaf_device *dsaf_dev,
2051 u16 entry_index, struct dsaf_drv_mac_multi_dest_entry *mac_entry)
2052{
2053 struct dsaf_drv_tbl_tcam_key mac_key;
2054
2055 struct dsaf_tbl_tcam_mcast_cfg mac_data;
2056 struct dsaf_tbl_tcam_ucast_cfg mac_uc_data;
153b1d48 2057 char mac_addr[ETH_ALEN] = {0};
511e6bc0 2058
1f5fa2dd 2059 if (entry_index >= dsaf_dev->tcam_max_num) {
511e6bc0 2060 /* find none, del error */
2061 dev_err(dsaf_dev->dev, "get_uc_entry failed, %s\n",
2062 dsaf_dev->ae_dev.name);
2063 return -EINVAL;
2064 }
2065
2066 /* mc entry, do read opt */
2067 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index,
2068 (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data);
2069
2070 mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F;
2071
2072 /***get mac addr*/
2073 mac_addr[0] = mac_key.high.bits.mac_0;
2074 mac_addr[1] = mac_key.high.bits.mac_1;
2075 mac_addr[2] = mac_key.high.bits.mac_2;
2076 mac_addr[3] = mac_key.high.bits.mac_3;
2077 mac_addr[4] = mac_key.low.bits.mac_4;
2078 mac_addr[5] = mac_key.low.bits.mac_5;
2079 /**is mc or uc*/
2080 if (MAC_IS_MULTICAST((u8 *)mac_addr) ||
2081 MAC_IS_L3_MULTICAST((u8 *)mac_addr)) {
2082 /**mc donot do*/
2083 } else {
2084 /*is not mc, just uc... */
2085 hns_dsaf_tcam_uc_get(dsaf_dev, entry_index,
2086 (struct dsaf_tbl_tcam_data *)&mac_key,
2087 &mac_uc_data);
2088 mac_entry->port_mask[0] = (1 << mac_uc_data.tbl_ucast_out_port);
2089 }
2090
2091 return 0;
2092}
2093
2094static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev,
2095 size_t sizeof_priv)
2096{
2097 struct dsaf_device *dsaf_dev;
2098
2099 dsaf_dev = devm_kzalloc(dev,
2100 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL);
2101 if (unlikely(!dsaf_dev)) {
2102 dsaf_dev = ERR_PTR(-ENOMEM);
2103 } else {
2104 dsaf_dev->dev = dev;
2105 dev_set_drvdata(dev, dsaf_dev);
2106 }
2107
2108 return dsaf_dev;
2109}
2110
2111/**
2112 * hns_dsaf_free_dev - free dev mem
2113 * @dev: struct device pointer
2114 */
2115static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev)
2116{
2117 (void)dev_set_drvdata(dsaf_dev->dev, NULL);
2118}
2119
2120/**
2121 * dsaf_pfc_unit_cnt - set pfc unit count
2122 * @dsaf_id: dsa fabric id
2123 * @pport_rate: value array
2124 * @pdsaf_pfc_unit_cnt: value array
2125 */
2126static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int mac_id,
2127 enum dsaf_port_rate_mode rate)
2128{
2129 u32 unit_cnt;
2130
2131 switch (rate) {
2132 case DSAF_PORT_RATE_10000:
2133 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2134 break;
2135 case DSAF_PORT_RATE_1000:
2136 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2137 break;
2138 case DSAF_PORT_RATE_2500:
2139 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2140 break;
2141 default:
2142 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2143 }
2144
2145 dsaf_set_dev_field(dsaf_dev,
2146 (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id),
2147 DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S,
2148 unit_cnt);
2149}
2150
2151/**
2152 * dsaf_port_work_rate_cfg - fifo
2153 * @dsaf_id: dsa fabric id
2154 * @xge_ge_work_mode
2155 */
2156void hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id,
2157 enum dsaf_port_rate_mode rate_mode)
2158{
2159 u32 port_work_mode;
2160
2161 port_work_mode = dsaf_read_dev(
2162 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id);
2163
2164 if (rate_mode == DSAF_PORT_RATE_10000)
2165 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1);
2166 else
2167 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0);
2168
2169 dsaf_write_dev(dsaf_dev,
2170 DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id,
2171 port_work_mode);
2172
2173 hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode);
2174}
2175
2176/**
2177 * hns_dsaf_fix_mac_mode - dsaf modify mac mode
2178 * @mac_cb: mac contrl block
2179 */
2180void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb)
2181{
2182 enum dsaf_port_rate_mode mode;
2183 struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
2184 int mac_id = mac_cb->mac_id;
2185
2186 if (mac_cb->mac_type != HNAE_PORT_SERVICE)
2187 return;
2188 if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII)
2189 mode = DSAF_PORT_RATE_10000;
2190 else
2191 mode = DSAF_PORT_RATE_1000;
2192
2193 hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode);
2194}
2195
379d3954
DH		 2196static u32 hns_dsaf_get_inode_prio_reg(int index)
2197{
2198 int base_index, offset;
2199 u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG;
2200
2201 base_index = (index + 1) / DSAF_REG_PER_ZONE;
2202 offset = (index + 1) % DSAF_REG_PER_ZONE;
2203
2204 return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index +
2205 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset;
2206}
2207
511e6bc0 2208void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
2209{
2210 struct dsaf_hw_stats *hw_stats
2211 = &dsaf_dev->hw_stats[node_num];
5ada37b5 2212 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
379d3954 2213 int i;
5ada37b5 2214 u32 reg_tmp;
511e6bc0 2215
2216 hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
2217 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2218 hw_stats->man_pkts += dsaf_read_dev(dsaf_dev,
2219 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num);
2220 hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev,
2221 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
2222 hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
2223 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
5ada37b5
L		 2224
2225 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2226 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2227 hw_stats->rx_pause_frame +=
2228 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num);
2229
511e6bc0 2230 hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
2231 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
2232 hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
2233 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num);
2234 hw_stats->crc_false += dsaf_read_dev(dsaf_dev,
2235 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2236 hw_stats->bp_drop += dsaf_read_dev(dsaf_dev,
2237 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2238 hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev,
2239 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2240 hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev,
2241 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2242
2243 hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
2244 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 0x80 * (u64)node_num);
2245 hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
2246 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 0x80 * (u64)node_num);
2247
379d3954
DH		 2248 /* pfc pause frame statistics stored in dsaf inode*/
2249 if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) {
2250 for (i = 0; i < DSAF_PRIO_NR; i++) {
2251 reg_tmp = hns_dsaf_get_inode_prio_reg(i);
2252 hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev,
2253 reg_tmp + 0x4 * (u64)node_num);
2254 hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev,
2255 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG +
2256 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i +
2257 0xF0 * (u64)node_num);
2258 }
2259 }
511e6bc0 2260 hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev,
2261 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num);
2262}
2263
2264/**
2265 *hns_dsaf_get_regs - dump dsaf regs
2266 *@dsaf_dev: dsaf device
2267 *@data:data for value of regs
2268 */
2269void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
2270{
2271 u32 i = 0;
2272 u32 j;
2273 u32 *p = data;
5ada37b5
L		 2274 u32 reg_tmp;
2275 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
511e6bc0 2276
2277 /* dsaf common registers */
2278 p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
2279 p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG);
2280 p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG);
2281 p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG);
2282 p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG);
2283 p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG);
2284 p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG);
2285 p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG);
2286 p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG);
2287
2288 p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4);
2289 p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4);
2290 p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2291 p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2292 p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2293 p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2294 p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4);
2295 p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4);
2296 p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2297 p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4);
2298 p[19] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4);
2299 p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2300 p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4);
2301 p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4);
2302 p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4);
2303
2304 for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2305 p[24 + i] = dsaf_read_dev(ddev,
2306 DSAF_SW_PORT_TYPE_0_REG + i * 4);
2307
2308 p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4);
2309
2310 for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2311 p[33 + i] = dsaf_read_dev(ddev,
2312 DSAF_PORT_DEF_VLAN_0_REG + i * 4);
2313
2314 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++)
2315 p[41 + i] = dsaf_read_dev(ddev,
2316 DSAF_VM_DEF_VLAN_0_REG + i * 4);
2317
2318 /* dsaf inode registers */
2319 p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG);
2320
2321 p[171] = dsaf_read_dev(ddev,
2322 DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80);
2323
2324 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2325 j = i * DSAF_COMM_CHN + port;
2326 p[172 + i] = dsaf_read_dev(ddev,
2327 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80);
2328 p[175 + i] = dsaf_read_dev(ddev,
2329 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80);
2330 p[178 + i] = dsaf_read_dev(ddev,
2331 DSAF_INODE_BP_STATUS_0_REG + j * 0x80);
2332 p[181 + i] = dsaf_read_dev(ddev,
2333 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80);
2334 p[184 + i] = dsaf_read_dev(ddev,
2335 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80);
2336 p[187 + i] = dsaf_read_dev(ddev,
2337 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
2338 p[190 + i] = dsaf_read_dev(ddev,
2339 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
5ada37b5
L		 2340 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2341 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2342 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80);
511e6bc0 2343 p[196 + i] = dsaf_read_dev(ddev,
2344 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
2345 p[199 + i] = dsaf_read_dev(ddev,
2346 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80);
2347 p[202 + i] = dsaf_read_dev(ddev,
2348 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80);
2349 p[205 + i] = dsaf_read_dev(ddev,
2350 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80);
2351 p[208 + i] = dsaf_read_dev(ddev,
2352 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80);
2353 p[211 + i] = dsaf_read_dev(ddev,
2354 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80);
2355 p[214 + i] = dsaf_read_dev(ddev,
2356 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80);
2357 p[217 + i] = dsaf_read_dev(ddev,
2358 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4);
2359 p[220 + i] = dsaf_read_dev(ddev,
2360 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
2361 p[223 + i] = dsaf_read_dev(ddev,
2362 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
2363 p[224 + i] = dsaf_read_dev(ddev,
2364 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
2365 }
2366
2367 p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
2368
2369 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2370 j = i * DSAF_COMM_CHN + port;
2371 p[228 + i] = dsaf_read_dev(ddev,
2372 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
2373 }
2374
2375 p[231] = dsaf_read_dev(ddev,
2376 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4);
2377
2378 /* dsaf inode registers */
13ac695e 2379 for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
511e6bc0 2380 j = i * DSAF_COMM_CHN + port;
2381 p[232 + i] = dsaf_read_dev(ddev,
2382 DSAF_SBM_CFG_REG_0_REG + j * 0x80);
2383 p[235 + i] = dsaf_read_dev(ddev,
2384 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
2385 p[238 + i] = dsaf_read_dev(ddev,
2386 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
2387 p[241 + i] = dsaf_read_dev(ddev,
2388 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
2389 p[244 + i] = dsaf_read_dev(ddev,
2390 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
2391 p[245 + i] = dsaf_read_dev(ddev,
2392 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
2393 p[248 + i] = dsaf_read_dev(ddev,
2394 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
2395 p[251 + i] = dsaf_read_dev(ddev,
2396 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
2397 p[254 + i] = dsaf_read_dev(ddev,
2398 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
2399 p[257 + i] = dsaf_read_dev(ddev,
2400 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
2401 p[260 + i] = dsaf_read_dev(ddev,
2402 DSAF_SBM_INER_ST_0_REG + j * 0x80);
2403 p[263 + i] = dsaf_read_dev(ddev,
2404 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
2405 p[266 + i] = dsaf_read_dev(ddev,
2406 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
2407 p[269 + i] = dsaf_read_dev(ddev,
2408 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
2409 p[272 + i] = dsaf_read_dev(ddev,
2410 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
2411 p[275 + i] = dsaf_read_dev(ddev,
2412 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
2413 p[278 + i] = dsaf_read_dev(ddev,
2414 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
2415 p[281 + i] = dsaf_read_dev(ddev,
2416 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
2417 p[284 + i] = dsaf_read_dev(ddev,
2418 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
2419 p[287 + i] = dsaf_read_dev(ddev,
2420 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
2421 p[290 + i] = dsaf_read_dev(ddev,
2422 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
2423 p[293 + i] = dsaf_read_dev(ddev,
2424 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
2425 p[296 + i] = dsaf_read_dev(ddev,
2426 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
2427 p[299 + i] = dsaf_read_dev(ddev,
2428 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
2429 p[302 + i] = dsaf_read_dev(ddev,
2430 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
2431 p[305 + i] = dsaf_read_dev(ddev,
2432 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
2433 p[308 + i] = dsaf_read_dev(ddev,
2434 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
2435 }
2436
2437 /* dsaf onode registers */
2438 for (i = 0; i < DSAF_XOD_NUM; i++) {
2439 p[311 + i] = dsaf_read_dev(ddev,
52613126 2440 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
511e6bc0 2441 p[319 + i] = dsaf_read_dev(ddev,
52613126 2442 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
511e6bc0 2443 p[327 + i] = dsaf_read_dev(ddev,
52613126 2444 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
511e6bc0 2445 p[335 + i] = dsaf_read_dev(ddev,
52613126 2446 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
511e6bc0 2447 p[343 + i] = dsaf_read_dev(ddev,
52613126 2448 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
511e6bc0 2449 p[351 + i] = dsaf_read_dev(ddev,
52613126 2450 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
511e6bc0 2451 }
2452
2453 p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
2454 p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
2455 p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
2456
2457 for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
2458 j = i * DSAF_COMM_CHN + port;
2459 p[362 + i] = dsaf_read_dev(ddev,
2460 DSAF_XOD_GNT_L_0_REG + j * 0x90);
2461 p[365 + i] = dsaf_read_dev(ddev,
2462 DSAF_XOD_GNT_H_0_REG + j * 0x90);
2463 p[368 + i] = dsaf_read_dev(ddev,
2464 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
2465 p[371 + i] = dsaf_read_dev(ddev,
2466 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
2467 p[374 + i] = dsaf_read_dev(ddev,
2468 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
2469 p[377 + i] = dsaf_read_dev(ddev,
2470 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
2471 p[380 + i] = dsaf_read_dev(ddev,
2472 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
2473 p[383 + i] = dsaf_read_dev(ddev,
2474 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
2475 p[386 + i] = dsaf_read_dev(ddev,
2476 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
2477 p[389 + i] = dsaf_read_dev(ddev,
2478 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
2479 }
2480
2481 p[392] = dsaf_read_dev(ddev,
2482 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
2483 p[393] = dsaf_read_dev(ddev,
2484 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
2485 p[394] = dsaf_read_dev(ddev,
2486 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
2487 p[395] = dsaf_read_dev(ddev,
2488 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
2489 p[396] = dsaf_read_dev(ddev,
2490 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
2491 p[397] = dsaf_read_dev(ddev,
2492 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
2493 p[398] = dsaf_read_dev(ddev,
2494 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
2495 p[399] = dsaf_read_dev(ddev,
2496 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
2497 p[400] = dsaf_read_dev(ddev,
2498 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
2499 p[401] = dsaf_read_dev(ddev,
2500 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
2501 p[402] = dsaf_read_dev(ddev,
2502 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
2503 p[403] = dsaf_read_dev(ddev,
2504 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
2505 p[404] = dsaf_read_dev(ddev,
2506 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
2507
2508 /* dsaf voq registers */
2509 for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
2510 j = (i * DSAF_COMM_CHN + port) * 0x90;
2511 p[405 + i] = dsaf_read_dev(ddev,
2512 DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
2513 p[408 + i] = dsaf_read_dev(ddev,
2514 DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
2515 p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
2516 p[414 + i] = dsaf_read_dev(ddev,
2517 DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
2518 p[417 + i] = dsaf_read_dev(ddev,
2519 DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
2520 p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
2521 p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
2522 p[426 + i] = dsaf_read_dev(ddev,
2523 DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
2524 p[429 + i] = dsaf_read_dev(ddev,
2525 DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
2526 p[432 + i] = dsaf_read_dev(ddev,
2527 DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
2528 p[435 + i] = dsaf_read_dev(ddev,
2529 DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
2530 p[438 + i] = dsaf_read_dev(ddev,
2531 DSAF_VOQ_BP_ALL_THRD_0_REG + j);
2532 }
2533
2534 /* dsaf tbl registers */
2535 p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
2536 p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
2537 p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
2538 p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
2539 p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
2540 p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
2541 p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
2542 p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
2543 p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
2544 p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
2545 p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
2546 p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
2547 p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
2548 p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
2549 p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
2550 p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
2551 p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
2552 p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
2553 p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
2554 p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
2555 p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
2556 p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
2557 p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
2558
2559 for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
2560 j = i * 0x8;
2561 p[464 + 2 * i] = dsaf_read_dev(ddev,
2562 DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
2563 p[465 + 2 * i] = dsaf_read_dev(ddev,
2564 DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
2565 }
2566
2567 p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
2568 p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
2569 p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
2570 p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
2571 p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
2572 p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
2573 p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
2574 p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
2575 p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
2576 p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
2577 p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
2578 p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
2579
2580 /* dsaf other registers */
2581 p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
2582 p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
2583 p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
2584 p[495] = dsaf_read_dev(ddev,
2585 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
2586 p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
2587 p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
2588
5ada37b5
L		 2589 if (!is_ver1)
2590 p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
2591
511e6bc0 2592 /* mark end of dsaf regs */
5ada37b5 2593 for (i = 499; i < 504; i++)
511e6bc0 2594 p[i] = 0xdddddddd;
2595}
2596
379d3954
DH		 2597static char *hns_dsaf_get_node_stats_strings(char *data, int node,
2598 struct dsaf_device *dsaf_dev)
511e6bc0 2599{
2600 char *buff = data;
379d3954
DH		 2601 int i;
2602 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
511e6bc0 2603
2604 snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node);
8ec98ba7 2605 buff += ETH_GSTRING_LEN;
511e6bc0 2606 snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node);
8ec98ba7 2607 buff += ETH_GSTRING_LEN;
511e6bc0 2608 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node);
8ec98ba7 2609 buff += ETH_GSTRING_LEN;
511e6bc0 2610 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node);
8ec98ba7 2611 buff += ETH_GSTRING_LEN;
511e6bc0 2612 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node);
8ec98ba7 2613 buff += ETH_GSTRING_LEN;
511e6bc0 2614 snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node);
8ec98ba7 2615 buff += ETH_GSTRING_LEN;
511e6bc0 2616 snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node);
8ec98ba7 2617 buff += ETH_GSTRING_LEN;
511e6bc0 2618 snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node);
8ec98ba7 2619 buff += ETH_GSTRING_LEN;
511e6bc0 2620 snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node);
8ec98ba7 2621 buff += ETH_GSTRING_LEN;
511e6bc0 2622 snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node);
8ec98ba7 2623 buff += ETH_GSTRING_LEN;
511e6bc0 2624 snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node);
8ec98ba7 2625 buff += ETH_GSTRING_LEN;
511e6bc0 2626 snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node);
8ec98ba7 2627 buff += ETH_GSTRING_LEN;
511e6bc0 2628 snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node);
8ec98ba7 2629 buff += ETH_GSTRING_LEN;
68fa1636 2630 if (node < DSAF_SERVICE_NW_NUM && !is_ver1) {
379d3954 2631 for (i = 0; i < DSAF_PRIO_NR; i++) {
45fc764e
DH		 2632 snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2633 ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts",
2634 node, i);
2635 snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2636 ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts",
2637 node, i);
8ec98ba7 2638 buff += ETH_GSTRING_LEN;
379d3954 2639 }
45fc764e 2640 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN;
379d3954 2641 }
511e6bc0 2642 snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node);
8ec98ba7 2643 buff += ETH_GSTRING_LEN;
511e6bc0 2644
2645 return buff;
2646}
2647
2648static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data,
2649 int node_num)
2650{
2651 u64 *p = data;
379d3954 2652 int i;
511e6bc0 2653 struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num];
379d3954 2654 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
511e6bc0 2655
2656 p[0] = hw_stats->pad_drop;
2657 p[1] = hw_stats->man_pkts;
2658 p[2] = hw_stats->rx_pkts;
2659 p[3] = hw_stats->rx_pkt_id;
2660 p[4] = hw_stats->rx_pause_frame;
2661 p[5] = hw_stats->release_buf_num;
2662 p[6] = hw_stats->sbm_drop;
2663 p[7] = hw_stats->crc_false;
2664 p[8] = hw_stats->bp_drop;
2665 p[9] = hw_stats->rslt_drop;
2666 p[10] = hw_stats->local_addr_false;
2667 p[11] = hw_stats->vlan_drop;
2668 p[12] = hw_stats->stp_drop;
68fa1636 2669 if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) {
379d3954 2670 for (i = 0; i < DSAF_PRIO_NR; i++) {
45fc764e
DH		 2671 p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i];
2672 p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i];
379d3954
DH		 2673 }
2674 p[29] = hw_stats->tx_pkts;
2675 return &p[30];
2676 }
511e6bc0 2677
379d3954 2678 p[13] = hw_stats->tx_pkts;
511e6bc0 2679 return &p[14];
2680}
2681
2682/**
2683 *hns_dsaf_get_stats - get dsaf statistic
2684 *@ddev: dsaf device
2685 *@data:statistic value
2686 *@port: port num
2687 */
2688void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port)
2689{
2690 u64 *p = data;
2691 int node_num = port;
2692
2693 /* for ge/xge node info */
2694 p = hns_dsaf_get_node_stats(ddev, p, node_num);
2695
2696 /* for ppe node info */
2697 node_num = port + DSAF_PPE_INODE_BASE;
2698 (void)hns_dsaf_get_node_stats(ddev, p, node_num);
2699}
2700
2701/**
2702 *hns_dsaf_get_sset_count - get dsaf string set count
2703 *@stringset: type of values in data
2704 *return dsaf string name count
2705 */
379d3954 2706int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset)
511e6bc0 2707{
379d3954 2708 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
511e6bc0 2709
379d3954
DH		 2710 if (stringset == ETH_SS_STATS) {
2711 if (is_ver1)
2712 return DSAF_STATIC_NUM;
2713 else
2714 return DSAF_V2_STATIC_NUM;
2715 }
511e6bc0 2716 return 0;
2717}
2718
2719/**
2720 *hns_dsaf_get_strings - get dsaf string set
2721 *@stringset:srting set index
2722 *@data:strings name value
2723 *@port:port index
2724 */
379d3954
DH		 2725void hns_dsaf_get_strings(int stringset, u8 *data, int port,
2726 struct dsaf_device *dsaf_dev)
511e6bc0 2727{
2728 char *buff = (char *)data;
2729 int node = port;
2730
2731 if (stringset != ETH_SS_STATS)
2732 return;
2733
2734 /* for ge/xge node info */
379d3954 2735 buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
511e6bc0 2736
2737 /* for ppe node info */
2738 node = port + DSAF_PPE_INODE_BASE;
379d3954 2739 (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
511e6bc0 2740}
2741
2742/**
2743 *hns_dsaf_get_sset_count - get dsaf regs count
2744 *return dsaf regs count
2745 */
2746int hns_dsaf_get_regs_count(void)
2747{
2748 return DSAF_DUMP_REGS_NUM;
2749}
2750
1f5fa2dd
KY		 2751/* Reserve the last TCAM entry for promisc support */
2752#define dsaf_promisc_tcam_entry(port) \
2753 (DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM + (port))
2754void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
2755 u32 port, bool enable)
2756{
2757 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2758 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
2759 u16 entry_index;
2760 struct dsaf_drv_tbl_tcam_key tbl_tcam_data, tbl_tcam_mask;
2761 struct dsaf_tbl_tcam_mcast_cfg mac_data = {0};
2762
2763 if ((AE_IS_VER1(dsaf_dev->dsaf_ver)) || HNS_DSAF_IS_DEBUG(dsaf_dev))
2764 return;
2765
2766 /* find the tcam entry index for promisc */
2767 entry_index = dsaf_promisc_tcam_entry(port);
2768
2769 /* config key mask */
2770 if (enable) {
2771 memset(&tbl_tcam_data, 0, sizeof(tbl_tcam_data));
2772 memset(&tbl_tcam_mask, 0, sizeof(tbl_tcam_mask));
5483bfcb
QX		 2773 dsaf_set_field(tbl_tcam_data.low.bits.port_vlan,
2774 DSAF_TBL_TCAM_KEY_PORT_M,
2775 DSAF_TBL_TCAM_KEY_PORT_S, port);
2776 dsaf_set_field(tbl_tcam_mask.low.bits.port_vlan,
2777 DSAF_TBL_TCAM_KEY_PORT_M,
2778 DSAF_TBL_TCAM_KEY_PORT_S, 0xf);
1f5fa2dd
KY		 2779
2780 /* SUB_QID */
2781 dsaf_set_bit(mac_data.tbl_mcast_port_msk[0],
2782 DSAF_SERVICE_NW_NUM, true);
2783 mac_data.tbl_mcast_item_vld = true; /* item_vld bit */
2784 } else {
2785 mac_data.tbl_mcast_item_vld = false; /* item_vld bit */
2786 }
2787
2788 dev_dbg(dsaf_dev->dev,
2789 "set_promisc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
2790 dsaf_dev->ae_dev.name, tbl_tcam_data.high.val,
2791 tbl_tcam_data.low.val, entry_index);
2792
2793 /* config promisc entry with mask */
2794 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index,
2795 (struct dsaf_tbl_tcam_data *)&tbl_tcam_data,
2796 (struct dsaf_tbl_tcam_data *)&tbl_tcam_mask,
2797 &mac_data);
2798
2799 /* config software entry */
2800 soft_mac_entry += entry_index;
2801 soft_mac_entry->index = enable ? entry_index : DSAF_INVALID_ENTRY_IDX;
2802}
2803
511e6bc0 2804/**
2805 * dsaf_probe - probo dsaf dev
2806 * @pdev: dasf platform device
2807 * retuen 0 - success , negative --fail
2808 */
2809static int hns_dsaf_probe(struct platform_device *pdev)
2810{
2811 struct dsaf_device *dsaf_dev;
2812 int ret;
2813
2814 dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv));
2815 if (IS_ERR(dsaf_dev)) {
2816 ret = PTR_ERR(dsaf_dev);
2817 dev_err(&pdev->dev,
2818 "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret);
2819 return ret;
2820 }
2821
2822 ret = hns_dsaf_get_cfg(dsaf_dev);
2823 if (ret)
2824 goto free_dev;
2825
2826 ret = hns_dsaf_init(dsaf_dev);
2827 if (ret)
f6c2df1e 2828 goto free_dev;
511e6bc0 2829
2830 ret = hns_mac_init(dsaf_dev);
2831 if (ret)
2832 goto uninit_dsaf;
2833
2834 ret = hns_ppe_init(dsaf_dev);
2835 if (ret)
2836 goto uninit_mac;
2837
2838 ret = hns_dsaf_ae_init(dsaf_dev);
2839 if (ret)
2840 goto uninit_ppe;
2841
2842 return 0;
2843
2844uninit_ppe:
2845 hns_ppe_uninit(dsaf_dev);
2846
2847uninit_mac:
2848 hns_mac_uninit(dsaf_dev);
2849
2850uninit_dsaf:
2851 hns_dsaf_free(dsaf_dev);
2852
511e6bc0 2853free_dev:
2854 hns_dsaf_free_dev(dsaf_dev);
2855
2856 return ret;
2857}
2858
2859/**
2860 * dsaf_remove - remove dsaf dev
2861 * @pdev: dasf platform device
2862 */
2863static int hns_dsaf_remove(struct platform_device *pdev)
2864{
2865 struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev);
2866
2867 hns_dsaf_ae_uninit(dsaf_dev);
2868
2869 hns_ppe_uninit(dsaf_dev);
2870
2871 hns_mac_uninit(dsaf_dev);
2872
2873 hns_dsaf_free(dsaf_dev);
2874
511e6bc0 2875 hns_dsaf_free_dev(dsaf_dev);
2876
2877 return 0;
2878}
2879
2880static const struct of_device_id g_dsaf_match[] = {
2881 {.compatible = "hisilicon,hns-dsaf-v1"},
2882 {.compatible = "hisilicon,hns-dsaf-v2"},
2883 {}
2884};
a7deb924 2885MODULE_DEVICE_TABLE(of, g_dsaf_match);
511e6bc0 2886
2887static struct platform_driver g_dsaf_driver = {
2888 .probe = hns_dsaf_probe,
2889 .remove = hns_dsaf_remove,
2890 .driver = {
2891 .name = DSAF_DRV_NAME,
2892 .of_match_table = g_dsaf_match,
8413b3be 2893 .acpi_match_table = hns_dsaf_acpi_match,
511e6bc0 2894 },
2895};
2896
2897module_platform_driver(g_dsaf_driver);
2898
e0180688 2899/**
2900 * hns_dsaf_roce_reset - reset dsaf and roce
2901 * @dsaf_fwnode: Pointer to framework node for the dasf
2902 * @enable: false - request reset , true - drop reset
2903 * retuen 0 - success , negative -fail
2904 */
d605916b 2905int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)
e0180688 2906{
2907 struct dsaf_device *dsaf_dev;
2908 struct platform_device *pdev;
2909 u32 mp;
2910 u32 sl;
2911 u32 credit;
2912 int i;
2913 const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
2914 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
2915 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
2916 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
2917 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
2918 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
2919 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
2920 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
2921 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
2922 };
2923 const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
2924 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
2925 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
2926 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
2927 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
2928 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
2929 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
2930 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
2931 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
2932 };
2933
d605916b
S		 2934 /* find the platform device corresponding to fwnode */
2935 if (is_of_node(dsaf_fwnode)) {
2936 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
2937 } else if (is_acpi_device_node(dsaf_fwnode)) {
2938 pdev = hns_dsaf_find_platform_device(dsaf_fwnode);
2939 } else {
2940 pr_err("fwnode is neither OF or ACPI type\n");
e0180688 2941 return -EINVAL;
2942 }
d605916b
S		 2943
2944 /* check if we were a success in fetching pdev */
2945 if (!pdev) {
2946 pr_err("couldn't find platform device for node\n");
2947 return -ENODEV;
2948 }
2949
2950 /* retrieve the dsaf_device from the driver data */
e0180688 2951 dsaf_dev = dev_get_drvdata(&pdev->dev);
d605916b
S		 2952 if (!dsaf_dev) {
2953 dev_err(&pdev->dev, "dsaf_dev is NULL\n");
2954 return -ENODEV;
2955 }
2956
2957 /* now, make sure we are running on compatible SoC */
e0180688 2958 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
2959 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
2960 dsaf_dev->ae_dev.name);
2961 return -ENODEV;
2962 }
2963
d605916b
S		 2964 /* do reset or de-reset according to the flag */
2965 if (!dereset) {
2966 /* reset rocee-channels in dsaf and rocee */
2967 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
2968 false);
2969 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);
e0180688 2970 } else {
d605916b 2971 /* configure dsaf tx roce correspond to port map and sl map */
e0180688 2972 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
2973 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
2974 dsaf_set_field(mp, 7 << i * 3, i * 3,
2975 port_map[i][DSAF_ROCE_6PORT_MODE]);
2976 dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
2977 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
2978
2979 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
2980 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
2981 dsaf_set_field(sl, 3 << i * 2, i * 2,
2982 sl_map[i][DSAF_ROCE_6PORT_MODE]);
2983 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
2984
d605916b
S		 2985 /* de-reset rocee-channels in dsaf and rocee */
2986 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
2987 true);
e0180688 2988 msleep(SRST_TIME_INTERVAL);
d605916b 2989 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);
e0180688 2990
d605916b 2991 /* enable dsaf channel rocee credit */
e0180688 2992 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
2993 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
2994 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
2995
2996 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
2997 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
2998 }
2999 return 0;
3000}
3001EXPORT_SYMBOL(hns_dsaf_roce_reset);
3002
511e6bc0 3003MODULE_LICENSE("GPL");
3004MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3005MODULE_DESCRIPTION("HNS DSAF driver");
3006MODULE_VERSION(DSAF_MOD_VERSION);
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