[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_main.h

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __HNS_DSAF_MAIN_H
#define __HNS_DSAF_MAIN_H
#include "hnae.h"

#include "hns_dsaf_reg.h"
#include "hns_dsaf_mac.h"

struct hns_mac_cb;

#define DSAF_DRV_NAME "hns_dsaf"
#define DSAF_MOD_VERSION "v1.0"
#define DSAF_DEVICE_NAME "dsaf"

#define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000

#define DSAF_BASE_INNER_PORT_NUM 127/* mac tbl qid*/

#define DSAF_MAX_CHIP_NUM 2  /*max 2 chips */

#define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22

#define HNS_DSAF_MAX_DESC_CNT 1024
#define HNS_DSAF_MIN_DESC_CNT 16

#define DSAF_INVALID_ENTRY_IDX 0xffff

#define DSAF_CFG_READ_CNT   30

#define DSAF_DUMP_REGS_NUM 504
#define DSAF_STATIC_NUM 28
#define DSAF_V2_STATIC_NUM	44
#define DSAF_PRIO_NR	8
#define DSAF_REG_PER_ZONE	3

#define DSAF_ROCE_CREDIT_CHN	8
#define DSAF_ROCE_CHAN_MODE	3

enum dsaf_roce_port_mode {
	DSAF_ROCE_6PORT_MODE,
	DSAF_ROCE_4PORT_MODE,
	DSAF_ROCE_2PORT_MODE,
	DSAF_ROCE_CHAN_MODE_NUM,
};

enum dsaf_roce_port_num {
	DSAF_ROCE_PORT_0,
	DSAF_ROCE_PORT_1,
	DSAF_ROCE_PORT_2,
	DSAF_ROCE_PORT_3,
	DSAF_ROCE_PORT_4,
	DSAF_ROCE_PORT_5,
};

enum dsaf_roce_qos_sl {
	DSAF_ROCE_SL_0,
	DSAF_ROCE_SL_1,
	DSAF_ROCE_SL_2,
	DSAF_ROCE_SL_3,
};

#define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
#define HNS_DSAF_IS_DEBUG(dev) (dev->dsaf_mode == DSAF_MODE_DISABLE_SP)

enum hal_dsaf_mode {
	HRD_DSAF_NO_DSAF_MODE	= 0x0,
	HRD_DSAF_MODE		= 0x1,
};

enum hal_dsaf_tc_mode {
	HRD_DSAF_4TC_MODE		= 0X0,
	HRD_DSAF_8TC_MODE		= 0X1,
};

struct dsaf_vm_def_vlan {
	u32 vm_def_vlan_id;
	u32 vm_def_vlan_cfi;
	u32 vm_def_vlan_pri;
};

struct dsaf_tbl_tcam_data {
	u32 tbl_tcam_data_high;
	u32 tbl_tcam_data_low;
};

#define DSAF_PORT_MSK_NUM \
	((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1)
struct dsaf_tbl_tcam_mcast_cfg {
	u8 tbl_mcast_old_en;
	u8 tbl_mcast_item_vld;
	u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM];
};

struct dsaf_tbl_tcam_ucast_cfg {
	u32 tbl_ucast_old_en;
	u32 tbl_ucast_item_vld;
	u32 tbl_ucast_mac_discard;
	u32 tbl_ucast_dvc;
	u32 tbl_ucast_out_port;
};

struct dsaf_tbl_line_cfg {
	u32 tbl_line_mac_discard;
	u32 tbl_line_dvc;
	u32 tbl_line_out_port;
};

enum dsaf_port_rate_mode {
	DSAF_PORT_RATE_1000 = 0,
	DSAF_PORT_RATE_2500,
	DSAF_PORT_RATE_10000
};

enum dsaf_stp_port_type {
	DSAF_STP_PORT_TYPE_DISCARD = 0,
	DSAF_STP_PORT_TYPE_BLOCK = 1,
	DSAF_STP_PORT_TYPE_LISTEN = 2,
	DSAF_STP_PORT_TYPE_LEARN = 3,
	DSAF_STP_PORT_TYPE_FORWARD = 4
};

enum dsaf_sw_port_type {
	DSAF_SW_PORT_TYPE_NON_VLAN = 0,
	DSAF_SW_PORT_TYPE_ACCESS = 1,
	DSAF_SW_PORT_TYPE_TRUNK = 2,
};

#define DSAF_SUB_BASE_SIZE                        (0x10000)

/* dsaf mode define */
enum dsaf_mode {
	DSAF_MODE_INVALID = 0,	/**< Invalid dsaf mode */
	DSAF_MODE_ENABLE_FIX,	/**< en DSAF-mode, fixed to queue*/
	DSAF_MODE_ENABLE_0VM,	/**< en DSAF-mode, support 0 VM */
	DSAF_MODE_ENABLE_8VM,	/**< en DSAF-mode, support 8 VM */
	DSAF_MODE_ENABLE_16VM,	/**< en DSAF-mode, support 16 VM */
	DSAF_MODE_ENABLE_32VM,	/**< en DSAF-mode, support 32 VM */
	DSAF_MODE_ENABLE_128VM,	/**< en DSAF-mode, support 128 VM */
	DSAF_MODE_ENABLE,		/**< before is enable DSAF mode*/
	DSAF_MODE_DISABLE_SP,	/* <non-dsaf, single port mode */
	DSAF_MODE_DISABLE_FIX,	/**< non-dasf, fixed to queue*/
	DSAF_MODE_DISABLE_2PORT_8VM,	/**< non-dasf, 2port 8VM */
	DSAF_MODE_DISABLE_2PORT_16VM,	/**< non-dasf, 2port 16VM */
	DSAF_MODE_DISABLE_2PORT_64VM,	/**< non-dasf, 2port 64VM */
	DSAF_MODE_DISABLE_6PORT_0VM,	/**< non-dasf, 6port 0VM */
	DSAF_MODE_DISABLE_6PORT_2VM,	/**< non-dasf, 6port 2VM */
	DSAF_MODE_DISABLE_6PORT_4VM,	/**< non-dasf, 6port 4VM */
	DSAF_MODE_DISABLE_6PORT_16VM,	/**< non-dasf, 6port 16VM */
	DSAF_MODE_MAX		/**< the last one, use as the num */
};

#define DSAF_DEST_PORT_NUM 256	/* DSAF max port num */
#define DSAF_WORD_BIT_CNT 32  /* the num bit of word */

/*mac entry, mc or uc entry*/
struct dsaf_drv_mac_single_dest_entry {
	/* mac addr, match the entry*/
	u8 addr[ETH_ALEN];
	u16 in_vlan_id; /* value of VlanId */

	/* the vld input port num, dsaf-mode fix 0, */
	/*	non-dasf is the entry whitch port vld*/
	u8 in_port_num;

	u8 port_num; /*output port num*/
	u8 rsv[6];
};

/*only mc entry*/
struct dsaf_drv_mac_multi_dest_entry {
	/* mac addr, match the entry*/
	u8 addr[ETH_ALEN];
	u16 in_vlan_id;
	/* this mac addr output port,*/
	/*	bit0-bit5 means Port0-Port5(1bit is vld)**/
	u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT];

	/* the vld input port num, dsaf-mode fix 0,*/
	/*	non-dasf is the entry whitch port vld*/
	u8 in_port_num;
	u8 rsv[7];
};

struct dsaf_hw_stats {
	u64 pad_drop;
	u64 man_pkts;
	u64 rx_pkts;
	u64 rx_pkt_id;
	u64 rx_pause_frame;
	u64 release_buf_num;
	u64 sbm_drop;
	u64 crc_false;
	u64 bp_drop;
	u64 rslt_drop;
	u64 local_addr_false;
	u64 vlan_drop;
	u64 stp_drop;
	u64 rx_pfc[DSAF_PRIO_NR];
	u64 tx_pfc[DSAF_PRIO_NR];
	u64 tx_pkts;
};

struct hnae_vf_cb {
	u8 port_index;
	struct hns_mac_cb *mac_cb;
	struct dsaf_device *dsaf_dev;
	struct hnae_handle  ae_handle; /* must be the last number */
};

struct dsaf_int_xge_src {
	u32    xid_xge_ecc_err_int_src;
	u32    xid_xge_fsm_timout_int_src;
	u32    sbm_xge_lnk_fsm_timout_int_src;
	u32    sbm_xge_lnk_ecc_2bit_int_src;
	u32    sbm_xge_mib_req_failed_int_src;
	u32    sbm_xge_mib_req_fsm_timout_int_src;
	u32    sbm_xge_mib_rels_fsm_timout_int_src;
	u32    sbm_xge_sram_ecc_2bit_int_src;
	u32    sbm_xge_mib_buf_sum_err_int_src;
	u32    sbm_xge_mib_req_extra_int_src;
	u32    sbm_xge_mib_rels_extra_int_src;
	u32    voq_xge_start_to_over_0_int_src;
	u32    voq_xge_start_to_over_1_int_src;
	u32    voq_xge_ecc_err_int_src;
};

struct dsaf_int_ppe_src {
	u32    xid_ppe_fsm_timout_int_src;
	u32    sbm_ppe_lnk_fsm_timout_int_src;
	u32    sbm_ppe_lnk_ecc_2bit_int_src;
	u32    sbm_ppe_mib_req_failed_int_src;
	u32    sbm_ppe_mib_req_fsm_timout_int_src;
	u32    sbm_ppe_mib_rels_fsm_timout_int_src;
	u32    sbm_ppe_sram_ecc_2bit_int_src;
	u32    sbm_ppe_mib_buf_sum_err_int_src;
	u32    sbm_ppe_mib_req_extra_int_src;
	u32    sbm_ppe_mib_rels_extra_int_src;
	u32    voq_ppe_start_to_over_0_int_src;
	u32    voq_ppe_ecc_err_int_src;
	u32    xod_ppe_fifo_rd_empty_int_src;
	u32    xod_ppe_fifo_wr_full_int_src;
};

struct dsaf_int_rocee_src {
	u32    xid_rocee_fsm_timout_int_src;
	u32    sbm_rocee_lnk_fsm_timout_int_src;
	u32    sbm_rocee_lnk_ecc_2bit_int_src;
	u32    sbm_rocee_mib_req_failed_int_src;
	u32    sbm_rocee_mib_req_fsm_timout_int_src;
	u32    sbm_rocee_mib_rels_fsm_timout_int_src;
	u32    sbm_rocee_sram_ecc_2bit_int_src;
	u32    sbm_rocee_mib_buf_sum_err_int_src;
	u32    sbm_rocee_mib_req_extra_int_src;
	u32    sbm_rocee_mib_rels_extra_int_src;
	u32    voq_rocee_start_to_over_0_int_src;
	u32    voq_rocee_ecc_err_int_src;
};

struct dsaf_int_tbl_src {
	u32    tbl_da0_mis_src;
	u32    tbl_da1_mis_src;
	u32    tbl_da2_mis_src;
	u32    tbl_da3_mis_src;
	u32    tbl_da4_mis_src;
	u32    tbl_da5_mis_src;
	u32    tbl_da6_mis_src;
	u32    tbl_da7_mis_src;
	u32    tbl_sa_mis_src;
	u32    tbl_old_sech_end_src;
	u32    lram_ecc_err1_src;
	u32    lram_ecc_err2_src;
	u32    tram_ecc_err1_src;
	u32    tram_ecc_err2_src;
	u32    tbl_ucast_bcast_xge0_src;
	u32    tbl_ucast_bcast_xge1_src;
	u32    tbl_ucast_bcast_xge2_src;
	u32    tbl_ucast_bcast_xge3_src;
	u32    tbl_ucast_bcast_xge4_src;
	u32    tbl_ucast_bcast_xge5_src;
	u32    tbl_ucast_bcast_ppe_src;
	u32    tbl_ucast_bcast_rocee_src;
};

struct dsaf_int_stat {
	struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN];
	struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN];
	struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN];
	struct dsaf_int_tbl_src dsaf_int_tbl_stat[1];

};

struct dsaf_misc_op {
	void (*cpld_set_led)(struct hns_mac_cb *mac_cb, int link_status,
			     u16 speed, int data);
	void (*cpld_reset_led)(struct hns_mac_cb *mac_cb);
	int (*cpld_set_led_id)(struct hns_mac_cb *mac_cb,
			       enum hnae_led_state status);
	/* reset series function, it will be reset if the dereset is 0 */
	void (*dsaf_reset)(struct dsaf_device *dsaf_dev, bool dereset);
	void (*xge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
	void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
	void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
	void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset);
	void (*hns_dsaf_srst_chns)(struct dsaf_device *dsaf_dev, u32 msk,
				   bool dereset);
	void (*hns_dsaf_roce_srst)(struct dsaf_device *dsaf_dev, bool dereset);

	phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb);
	int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt);

	int (*cfg_serdes_loopback)(struct hns_mac_cb *mac_cb, bool en);
};

/* Dsaf device struct define ,and mac ->  dsaf */
struct dsaf_device {
	struct device *dev;
	struct hnae_ae_dev ae_dev;

	u8 __iomem *sc_base;
	u8 __iomem *sds_base;
	u8 __iomem *ppe_base;
	u8 __iomem *io_base;
	struct regmap *sub_ctrl;
	phys_addr_t ppe_paddr;

	u32 desc_num; /*  desc num per queue*/
	u32 buf_size; /*  ring buffer size */
	u32 reset_offset; /* reset field offset in sub sysctrl */
	int buf_size_type; /* ring buffer size-type */
	enum dsaf_mode dsaf_mode;	 /* dsaf mode  */
	enum hal_dsaf_mode dsaf_en;
	enum hal_dsaf_tc_mode dsaf_tc_mode;
	u32 dsaf_ver;
	u16 tcam_max_num;	/* max TCAM entry for user except promisc */

	struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM];
	struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM];
	struct hns_mac_cb *mac_cb[DSAF_MAX_PORT_NUM];
	struct dsaf_misc_op *misc_op;

	struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM];
	struct dsaf_int_stat int_stat;
	/* make sure tcam table config spinlock */
	spinlock_t tcam_lock;
};

static inline void *hns_dsaf_dev_priv(const struct dsaf_device *dsaf_dev)
{
	return (void *)((u8 *)dsaf_dev + sizeof(*dsaf_dev));
}

#define DSAF_TBL_TCAM_KEY_PORT_S 0
#define DSAF_TBL_TCAM_KEY_PORT_M (((1ULL << 4) - 1) << 0)
#define DSAF_TBL_TCAM_KEY_VLAN_S 4
#define DSAF_TBL_TCAM_KEY_VLAN_M (((1ULL << 12) - 1) << 4)

struct dsaf_drv_tbl_tcam_key {
	union {
		struct {
			u8 mac_3;
			u8 mac_2;
			u8 mac_1;
			u8 mac_0;
		} bits;

		u32 val;
	} high;
	union {
		struct {
			u16 port_vlan;
			u8 mac_5;
			u8 mac_4;
		} bits;

		u32 val;
	} low;
};

struct dsaf_drv_soft_mac_tbl {
	struct dsaf_drv_tbl_tcam_key tcam_key;
	u16 index; /*the entry's index in tcam tab*/
};

struct dsaf_drv_priv {
	/* soft tab Mac key, for hardware tab*/
	struct dsaf_drv_soft_mac_tbl *soft_mac_tbl;
};

static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev,
					      u32 tab_tcam_addr)
{
	dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG,
			   DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S,
			   tab_tcam_addr);
}

static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev)
{
	u32 o_tbl_pul;

	o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
	dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1);
	dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
	dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0);
	dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
}

static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev,
					      u32 tab_line_addr)
{
	dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG,
			   DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S,
			   tab_line_addr);
}

static inline struct hnae_vf_cb *hns_ae_get_vf_cb(
	struct hnae_handle *handle)
{
	return container_of(handle, struct hnae_vf_cb, ae_handle);
}

int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev,
			      struct dsaf_drv_mac_single_dest_entry *mac_entry);
int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
			     struct dsaf_drv_mac_single_dest_entry *mac_entry);
int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
			   u8 in_port_num, u8 *addr);
int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
			     struct dsaf_drv_mac_single_dest_entry *mac_entry);
int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev,
			      struct dsaf_drv_mac_single_dest_entry *mac_entry);
int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev,
			      struct dsaf_drv_mac_multi_dest_entry *mac_entry);
int hns_dsaf_get_mac_entry_by_index(
	struct dsaf_device *dsaf_dev,
	u16 entry_index,
	struct dsaf_drv_mac_multi_dest_entry *mac_entry);

void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb);

int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev);
void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev);

void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num);

int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset);
void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port);
void hns_dsaf_get_strings(int stringset, u8 *data, int port,
			  struct dsaf_device *dsaf_dev);

void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data);
int hns_dsaf_get_regs_count(void);
void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en);
void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
			       u32 port, bool enable);

void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
				  u32 *en);
int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
				 u32 en);
int hns_dsaf_rm_mac_addr(
	struct dsaf_device *dsaf_dev,
	struct dsaf_drv_mac_single_dest_entry *mac_entry);

int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev,
			     u8 mac_id, u8 port_num);


#endif /* __HNS_DSAF_MAIN_H__ */
Commit	Line	Data
511e6bc0	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	#ifndef __HNS_DSAF_MAIN_H
	11	#define __HNS_DSAF_MAIN_H
	12	#include "hnae.h"
	13
	14	#include "hns_dsaf_reg.h"
	15	#include "hns_dsaf_mac.h"
	16
	17	struct hns_mac_cb;
	18
	19	#define DSAF_DRV_NAME "hns_dsaf"
	20	#define DSAF_MOD_VERSION "v1.0"
48189d6a	21	#define DSAF_DEVICE_NAME "dsaf"
511e6bc0	22
13ac695e	23	#define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000
511e6bc0	24
13ac695e	25	#define DSAF_BASE_INNER_PORT_NUM 127/* mac tbl qid*/
511e6bc0	26
13ac695e	27	#define DSAF_MAX_CHIP_NUM 2 /max 2 chips /
511e6bc0	28
13ac695e	29	#define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22
511e6bc0	30
13ac695e S	31	#define HNS_DSAF_MAX_DESC_CNT 1024
13ac695e S	32	#define HNS_DSAF_MIN_DESC_CNT 16
511e6bc0	33
13ac695e	34	#define DSAF_INVALID_ENTRY_IDX 0xffff
511e6bc0	35
13ac695e	36	#define DSAF_CFG_READ_CNT 30
511e6bc0	37
511e6bc0	38	#define DSAF_DUMP_REGS_NUM 504
511e6bc0	39	#define DSAF_STATIC_NUM 28
379d3954 DH	40	#define DSAF_V2_STATIC_NUM 44
	41	#define DSAF_PRIO_NR 8
	42	#define DSAF_REG_PER_ZONE 3
511e6bc0	43
e0180688	44	#define DSAF_ROCE_CREDIT_CHN 8
	45	#define DSAF_ROCE_CHAN_MODE 3
	46
	47	enum dsaf_roce_port_mode {
	48	DSAF_ROCE_6PORT_MODE,
	49	DSAF_ROCE_4PORT_MODE,
	50	DSAF_ROCE_2PORT_MODE,
	51	DSAF_ROCE_CHAN_MODE_NUM,
	52	};
	53
	54	enum dsaf_roce_port_num {
	55	DSAF_ROCE_PORT_0,
	56	DSAF_ROCE_PORT_1,
	57	DSAF_ROCE_PORT_2,
	58	DSAF_ROCE_PORT_3,
	59	DSAF_ROCE_PORT_4,
	60	DSAF_ROCE_PORT_5,
	61	};
	62
	63	enum dsaf_roce_qos_sl {
	64	DSAF_ROCE_SL_0,
	65	DSAF_ROCE_SL_1,
	66	DSAF_ROCE_SL_2,
	67	DSAF_ROCE_SL_3,
	68	};
	69
e4600d69	70	#define DSAF_STATS_READ(p, offset) (((u64 )((u8 *)(p) + (offset))))
89a44093	71	#define HNS_DSAF_IS_DEBUG(dev) (dev->dsaf_mode == DSAF_MODE_DISABLE_SP)
511e6bc0	72
	73	enum hal_dsaf_mode {
	74	HRD_DSAF_NO_DSAF_MODE = 0x0,
	75	HRD_DSAF_MODE = 0x1,
	76	};
	77
	78	enum hal_dsaf_tc_mode {
	79	HRD_DSAF_4TC_MODE = 0X0,
	80	HRD_DSAF_8TC_MODE = 0X1,
	81	};
	82
	83	struct dsaf_vm_def_vlan {
	84	u32 vm_def_vlan_id;
	85	u32 vm_def_vlan_cfi;
	86	u32 vm_def_vlan_pri;
	87	};
	88
	89	struct dsaf_tbl_tcam_data {
	90	u32 tbl_tcam_data_high;
	91	u32 tbl_tcam_data_low;
	92	};
	93
	94	#define DSAF_PORT_MSK_NUM \
	95	((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1)
	96	struct dsaf_tbl_tcam_mcast_cfg {
	97	u8 tbl_mcast_old_en;
	98	u8 tbl_mcast_item_vld;
	99	u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM];
	100	};
	101
	102	struct dsaf_tbl_tcam_ucast_cfg {
	103	u32 tbl_ucast_old_en;
	104	u32 tbl_ucast_item_vld;
	105	u32 tbl_ucast_mac_discard;
	106	u32 tbl_ucast_dvc;
	107	u32 tbl_ucast_out_port;
	108	};
	109
	110	struct dsaf_tbl_line_cfg {
	111	u32 tbl_line_mac_discard;
	112	u32 tbl_line_dvc;
	113	u32 tbl_line_out_port;
	114	};
	115
	116	enum dsaf_port_rate_mode {
	117	DSAF_PORT_RATE_1000 = 0,
	118	DSAF_PORT_RATE_2500,
	119	DSAF_PORT_RATE_10000
	120	};
	121
	122	enum dsaf_stp_port_type {
	123	DSAF_STP_PORT_TYPE_DISCARD = 0,
	124	DSAF_STP_PORT_TYPE_BLOCK = 1,
	125	DSAF_STP_PORT_TYPE_LISTEN = 2,
	126	DSAF_STP_PORT_TYPE_LEARN = 3,
	127	DSAF_STP_PORT_TYPE_FORWARD = 4
	128	};
	129
	130	enum dsaf_sw_port_type {
	131	DSAF_SW_PORT_TYPE_NON_VLAN = 0,
	132	DSAF_SW_PORT_TYPE_ACCESS = 1,
	133	DSAF_SW_PORT_TYPE_TRUNK = 2,
	134	};
	135
136	#define DSAF_SUB_BASE_SIZE (0x10000)
137
138	/* dsaf mode define */
139	enum dsaf_mode {
140	DSAF_MODE_INVALID = 0, /*< Invalid dsaf mode /
141	DSAF_MODE_ENABLE_FIX, /*< en DSAF-mode, fixed to queue/
142	DSAF_MODE_ENABLE_0VM, /*< en DSAF-mode, support 0 VM /
143	DSAF_MODE_ENABLE_8VM, /*< en DSAF-mode, support 8 VM /
144	DSAF_MODE_ENABLE_16VM, /*< en DSAF-mode, support 16 VM /
145	DSAF_MODE_ENABLE_32VM, /*< en DSAF-mode, support 32 VM /
146	DSAF_MODE_ENABLE_128VM, /*< en DSAF-mode, support 128 VM /
147	DSAF_MODE_ENABLE, /*< before is enable DSAF mode/
89a44093	148	DSAF_MODE_DISABLE_SP, /* <non-dsaf, single port mode */
511e6bc0	149	DSAF_MODE_DISABLE_FIX, /*< non-dasf, fixed to queue/
	150	DSAF_MODE_DISABLE_2PORT_8VM, /*< non-dasf, 2port 8VM /
	151	DSAF_MODE_DISABLE_2PORT_16VM, /*< non-dasf, 2port 16VM /
	152	DSAF_MODE_DISABLE_2PORT_64VM, /*< non-dasf, 2port 64VM /
	153	DSAF_MODE_DISABLE_6PORT_0VM, /*< non-dasf, 6port 0VM /
	154	DSAF_MODE_DISABLE_6PORT_2VM, /*< non-dasf, 6port 2VM /
	155	DSAF_MODE_DISABLE_6PORT_4VM, /*< non-dasf, 6port 4VM /
	156	DSAF_MODE_DISABLE_6PORT_16VM, /*< non-dasf, 6port 16VM /
	157	DSAF_MODE_MAX /*< the last one, use as the num /
	158	};
	159
	160	#define DSAF_DEST_PORT_NUM 256 /* DSAF max port num */
	161	#define DSAF_WORD_BIT_CNT 32 /* the num bit of word */
	162
	163	/mac entry, mc or uc entry/
	164	struct dsaf_drv_mac_single_dest_entry {
	165	/* mac addr, match the entry*/
153b1d48	166	u8 addr[ETH_ALEN];
511e6bc0	167	u16 in_vlan_id; /* value of VlanId */
	168
	169	/* the vld input port num, dsaf-mode fix 0, */
	170	/* non-dasf is the entry whitch port vld*/
	171	u8 in_port_num;
	172
	173	u8 port_num; /output port num/
	174	u8 rsv[6];
	175	};
	176
	177	/only mc entry/
	178	struct dsaf_drv_mac_multi_dest_entry {
	179	/* mac addr, match the entry*/
153b1d48	180	u8 addr[ETH_ALEN];
511e6bc0	181	u16 in_vlan_id;
	182	/* this mac addr output port,*/
	183	/* bit0-bit5 means Port0-Port5(1bit is vld)**/
	184	u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT];
	185
	186	/* the vld input port num, dsaf-mode fix 0,*/
	187	/* non-dasf is the entry whitch port vld*/
	188	u8 in_port_num;
	189	u8 rsv[7];
	190	};
	191
	192	struct dsaf_hw_stats {
	193	u64 pad_drop;
	194	u64 man_pkts;
	195	u64 rx_pkts;
	196	u64 rx_pkt_id;
	197	u64 rx_pause_frame;
	198	u64 release_buf_num;
	199	u64 sbm_drop;
	200	u64 crc_false;
	201	u64 bp_drop;
	202	u64 rslt_drop;
	203	u64 local_addr_false;
	204	u64 vlan_drop;
	205	u64 stp_drop;
379d3954 DH	206	u64 rx_pfc[DSAF_PRIO_NR];
379d3954 DH	207	u64 tx_pfc[DSAF_PRIO_NR];
511e6bc0	208	u64 tx_pkts;
	209	};
	210
	211	struct hnae_vf_cb {
	212	u8 port_index;
	213	struct hns_mac_cb *mac_cb;
	214	struct dsaf_device *dsaf_dev;
	215	struct hnae_handle ae_handle; /* must be the last number */
	216	};
	217
	218	struct dsaf_int_xge_src {
	219	u32 xid_xge_ecc_err_int_src;
	220	u32 xid_xge_fsm_timout_int_src;
	221	u32 sbm_xge_lnk_fsm_timout_int_src;
	222	u32 sbm_xge_lnk_ecc_2bit_int_src;
	223	u32 sbm_xge_mib_req_failed_int_src;
	224	u32 sbm_xge_mib_req_fsm_timout_int_src;
	225	u32 sbm_xge_mib_rels_fsm_timout_int_src;
	226	u32 sbm_xge_sram_ecc_2bit_int_src;
	227	u32 sbm_xge_mib_buf_sum_err_int_src;
	228	u32 sbm_xge_mib_req_extra_int_src;
	229	u32 sbm_xge_mib_rels_extra_int_src;
	230	u32 voq_xge_start_to_over_0_int_src;
	231	u32 voq_xge_start_to_over_1_int_src;
	232	u32 voq_xge_ecc_err_int_src;
	233	};
	234
	235	struct dsaf_int_ppe_src {
	236	u32 xid_ppe_fsm_timout_int_src;
	237	u32 sbm_ppe_lnk_fsm_timout_int_src;
	238	u32 sbm_ppe_lnk_ecc_2bit_int_src;
	239	u32 sbm_ppe_mib_req_failed_int_src;
	240	u32 sbm_ppe_mib_req_fsm_timout_int_src;
	241	u32 sbm_ppe_mib_rels_fsm_timout_int_src;
	242	u32 sbm_ppe_sram_ecc_2bit_int_src;
	243	u32 sbm_ppe_mib_buf_sum_err_int_src;
	244	u32 sbm_ppe_mib_req_extra_int_src;
	245	u32 sbm_ppe_mib_rels_extra_int_src;
	246	u32 voq_ppe_start_to_over_0_int_src;
	247	u32 voq_ppe_ecc_err_int_src;
	248	u32 xod_ppe_fifo_rd_empty_int_src;
	249	u32 xod_ppe_fifo_wr_full_int_src;
	250	};
	251
	252	struct dsaf_int_rocee_src {
	253	u32 xid_rocee_fsm_timout_int_src;
	254	u32 sbm_rocee_lnk_fsm_timout_int_src;
	255	u32 sbm_rocee_lnk_ecc_2bit_int_src;
	256	u32 sbm_rocee_mib_req_failed_int_src;
	257	u32 sbm_rocee_mib_req_fsm_timout_int_src;
	258	u32 sbm_rocee_mib_rels_fsm_timout_int_src;
	259	u32 sbm_rocee_sram_ecc_2bit_int_src;
	260	u32 sbm_rocee_mib_buf_sum_err_int_src;
	261	u32 sbm_rocee_mib_req_extra_int_src;
	262	u32 sbm_rocee_mib_rels_extra_int_src;
	263	u32 voq_rocee_start_to_over_0_int_src;
	264	u32 voq_rocee_ecc_err_int_src;
	265	};
	266
	267	struct dsaf_int_tbl_src {
	268	u32 tbl_da0_mis_src;
	269	u32 tbl_da1_mis_src;
	270	u32 tbl_da2_mis_src;
	271	u32 tbl_da3_mis_src;
272	u32 tbl_da4_mis_src;
273	u32 tbl_da5_mis_src;
274	u32 tbl_da6_mis_src;
275	u32 tbl_da7_mis_src;
276	u32 tbl_sa_mis_src;
277	u32 tbl_old_sech_end_src;
278	u32 lram_ecc_err1_src;
279	u32 lram_ecc_err2_src;
280	u32 tram_ecc_err1_src;
281	u32 tram_ecc_err2_src;
282	u32 tbl_ucast_bcast_xge0_src;
283	u32 tbl_ucast_bcast_xge1_src;
284	u32 tbl_ucast_bcast_xge2_src;
285	u32 tbl_ucast_bcast_xge3_src;
286	u32 tbl_ucast_bcast_xge4_src;
287	u32 tbl_ucast_bcast_xge5_src;
288	u32 tbl_ucast_bcast_ppe_src;
289	u32 tbl_ucast_bcast_rocee_src;
290	};
291
292	struct dsaf_int_stat {
293	struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN];
294	struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN];
295	struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN];
296	struct dsaf_int_tbl_src dsaf_int_tbl_stat[1];
297
298	};
299
a24274aa KY	300	struct dsaf_misc_op {
	301	void (cpld_set_led)(struct hns_mac_cb mac_cb, int link_status,
	302	u16 speed, int data);
	303	void (cpld_reset_led)(struct hns_mac_cb mac_cb);
	304	int (cpld_set_led_id)(struct hns_mac_cb mac_cb,
	305	enum hnae_led_state status);
d605916b	306	/* reset series function, it will be reset if the dereset is 0 */
a24274aa KY	307	void (dsaf_reset)(struct dsaf_device dsaf_dev, bool dereset);
a24274aa KY	308	void (xge_srst)(struct dsaf_device dsaf_dev, u32 port, bool dereset);
a24274aa KY	309	void (ge_srst)(struct dsaf_device dsaf_dev, u32 port, bool dereset);
	310	void (ppe_srst)(struct dsaf_device dsaf_dev, u32 port, bool dereset);
	311	void (ppe_comm_srst)(struct dsaf_device dsaf_dev, bool dereset);
d605916b S	312	void (hns_dsaf_srst_chns)(struct dsaf_device dsaf_dev, u32 msk,
	313	bool dereset);
	314	void (hns_dsaf_roce_srst)(struct dsaf_device dsaf_dev, bool dereset);
a24274aa KY	315
	316	phy_interface_t (get_phy_if)(struct hns_mac_cb mac_cb);
	317	int (get_sfp_prsnt)(struct hns_mac_cb mac_cb, int *sfp_prsnt);
	318
	319	int (cfg_serdes_loopback)(struct hns_mac_cb mac_cb, bool en);
	320	};
	321
511e6bc0	322	/* Dsaf device struct define ,and mac -> dsaf */
	323	struct dsaf_device {
	324	struct device *dev;
	325	struct hnae_ae_dev ae_dev;
	326
511e6bc0	327	u8 __iomem *sc_base;
	328	u8 __iomem *sds_base;
	329	u8 __iomem *ppe_base;
	330	u8 __iomem *io_base;
831d828b YZZ	331	struct regmap *sub_ctrl;
831d828b YZZ	332	phys_addr_t ppe_paddr;
511e6bc0	333
	334	u32 desc_num; /* desc num per queue*/
	335	u32 buf_size; /* ring buffer size */
422c3107	336	u32 reset_offset; /* reset field offset in sub sysctrl */
511e6bc0	337	int buf_size_type; /* ring buffer size-type */
	338	enum dsaf_mode dsaf_mode; /* dsaf mode */
	339	enum hal_dsaf_mode dsaf_en;
	340	enum hal_dsaf_tc_mode dsaf_tc_mode;
	341	u32 dsaf_ver;
1f5fa2dd	342	u16 tcam_max_num; /* max TCAM entry for user except promisc */
511e6bc0	343
	344	struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM];
	345	struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM];
831d828b	346	struct hns_mac_cb *mac_cb[DSAF_MAX_PORT_NUM];
a24274aa	347	struct dsaf_misc_op *misc_op;
511e6bc0	348
	349	struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM];
	350	struct dsaf_int_stat int_stat;
b7623816 DH	351	/* make sure tcam table config spinlock */
b7623816 DH	352	spinlock_t tcam_lock;
511e6bc0	353	};
	354
	355	static inline void hns_dsaf_dev_priv(const struct dsaf_device dsaf_dev)
	356	{
e4600d69	357	return (void )((u8 )dsaf_dev + sizeof(*dsaf_dev));
511e6bc0	358	}
511e6bc0	359
5483bfcb QX	360	#define DSAF_TBL_TCAM_KEY_PORT_S 0
	361	#define DSAF_TBL_TCAM_KEY_PORT_M (((1ULL << 4) - 1) << 0)
	362	#define DSAF_TBL_TCAM_KEY_VLAN_S 4
	363	#define DSAF_TBL_TCAM_KEY_VLAN_M (((1ULL << 12) - 1) << 4)
	364
511e6bc0	365	struct dsaf_drv_tbl_tcam_key {
	366	union {
	367	struct {
	368	u8 mac_3;
	369	u8 mac_2;
	370	u8 mac_1;
	371	u8 mac_0;
	372	} bits;
	373
	374	u32 val;
	375	} high;
	376	union {
	377	struct {
5483bfcb QX	378	u16 port_vlan;
	379	u8 mac_5;
	380	u8 mac_4;
511e6bc0	381	} bits;
	382
	383	u32 val;
	384	} low;
	385	};
	386
	387	struct dsaf_drv_soft_mac_tbl {
	388	struct dsaf_drv_tbl_tcam_key tcam_key;
	389	u16 index; /the entry's index in tcam tab/
	390	};
	391
	392	struct dsaf_drv_priv {
	393	/* soft tab Mac key, for hardware tab*/
	394	struct dsaf_drv_soft_mac_tbl *soft_mac_tbl;
	395	};
	396
	397	static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev,
	398	u32 tab_tcam_addr)
	399	{
	400	dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG,
	401	DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S,
	402	tab_tcam_addr);
	403	}
	404
	405	static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev)
	406	{
	407	u32 o_tbl_pul;
	408
	409	o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
	410	dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1);
	411	dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
	412	dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0);
	413	dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
	414	}
	415
	416	static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev,
	417	u32 tab_line_addr)
	418	{
	419	dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG,
	420	DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S,
	421	tab_line_addr);
	422	}
	423
511e6bc0	424	static inline struct hnae_vf_cb *hns_ae_get_vf_cb(
	425	struct hnae_handle *handle)
	426	{
	427	return container_of(handle, struct hnae_vf_cb, ae_handle);
	428	}
	429
	430	int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev,
	431	struct dsaf_drv_mac_single_dest_entry *mac_entry);
511e6bc0	432	int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
	433	struct dsaf_drv_mac_single_dest_entry *mac_entry);
	434	int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
	435	u8 in_port_num, u8 *addr);
	436	int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
	437	struct dsaf_drv_mac_single_dest_entry *mac_entry);
	438	int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev,
	439	struct dsaf_drv_mac_single_dest_entry *mac_entry);
	440	int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev,
	441	struct dsaf_drv_mac_multi_dest_entry *mac_entry);
	442	int hns_dsaf_get_mac_entry_by_index(
	443	struct dsaf_device *dsaf_dev,
	444	u16 entry_index,
	445	struct dsaf_drv_mac_multi_dest_entry *mac_entry);
	446
511e6bc0	447	void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb);
	448
	449	int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev);
	450	void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev);
	451
511e6bc0	452	void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num);
511e6bc0	453
379d3954	454	int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset);
511e6bc0	455	void hns_dsaf_get_stats(struct dsaf_device ddev, u64 data, int port);
379d3954 DH	456	void hns_dsaf_get_strings(int stringset, u8 *data, int port,
379d3954 DH	457	struct dsaf_device *dsaf_dev);
511e6bc0	458
	459	void hns_dsaf_get_regs(struct dsaf_device ddev, u32 port, void data);
	460	int hns_dsaf_get_regs_count(void);
4568637f	461	void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en);
1f5fa2dd KY	462	void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
1f5fa2dd KY	463	u32 port, bool enable);
5ada37b5 L	464
	465	void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
	466	u32 *en);
	467	int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
	468	u32 en);
66355f52 KY	469	int hns_dsaf_rm_mac_addr(
	470	struct dsaf_device *dsaf_dev,
	471	struct dsaf_drv_mac_single_dest_entry *mac_entry);
	472
ec2cafe6 KY	473	int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev,
	474	u8 mac_id, u8 port_num);
	475
511e6bc0	476
511e6bc0	477	#endif /* __HNS_DSAF_MAIN_H__ */