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511e6bc0 | 1 | /* |
2 | * Copyright (c) 2014-2015 Hisilicon Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
511e6bc0 | 10 | #include "hns_dsaf_mac.h" |
2e2591b1 | 11 | #include "hns_dsaf_misc.h" |
511e6bc0 | 12 | #include "hns_dsaf_ppe.h" |
2e2591b1 | 13 | #include "hns_dsaf_reg.h" |
511e6bc0 | 14 | |
f00ef863 KY |
15 | enum _dsm_op_index { |
16 | HNS_OP_RESET_FUNC = 0x1, | |
17 | HNS_OP_SERDES_LP_FUNC = 0x2, | |
18 | HNS_OP_LED_SET_FUNC = 0x3, | |
19 | HNS_OP_GET_PORT_TYPE_FUNC = 0x4, | |
20 | HNS_OP_GET_SFP_STAT_FUNC = 0x5, | |
21 | }; | |
22 | ||
23 | enum _dsm_rst_type { | |
24 | HNS_DSAF_RESET_FUNC = 0x1, | |
25 | HNS_PPE_RESET_FUNC = 0x2, | |
f00ef863 KY |
26 | HNS_XGE_RESET_FUNC = 0x4, |
27 | HNS_GE_RESET_FUNC = 0x5, | |
d605916b S |
28 | HNS_DSAF_CHN_RESET_FUNC = 0x6, |
29 | HNS_ROCE_RESET_FUNC = 0x7, | |
f00ef863 KY |
30 | }; |
31 | ||
b86a496a | 32 | static const guid_t hns_dsaf_acpi_dsm_guid = |
94116f81 AS |
33 | GUID_INIT(0x1A85AA1A, 0xE293, 0x415E, |
34 | 0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A); | |
f00ef863 | 35 | |
831d828b YZZ |
36 | static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val) |
37 | { | |
38 | if (dsaf_dev->sub_ctrl) | |
39 | dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val); | |
40 | else | |
41 | dsaf_write_reg(dsaf_dev->sc_base, reg, val); | |
42 | } | |
43 | ||
44 | static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg) | |
45 | { | |
46 | u32 ret; | |
47 | ||
48 | if (dsaf_dev->sub_ctrl) | |
49 | ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg); | |
50 | else | |
51 | ret = dsaf_read_reg(dsaf_dev->sc_base, reg); | |
52 | ||
53 | return ret; | |
54 | } | |
55 | ||
a24274aa KY |
56 | static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status, |
57 | u16 speed, int data) | |
511e6bc0 | 58 | { |
59 | int speed_reg = 0; | |
60 | u8 value; | |
61 | ||
62 | if (!mac_cb) { | |
63 | pr_err("sfp_led_opt mac_dev is null!\n"); | |
64 | return; | |
65 | } | |
31d4446d YZZ |
66 | if (!mac_cb->cpld_ctrl) { |
67 | dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n", | |
511e6bc0 | 68 | mac_cb->mac_id); |
69 | return; | |
70 | } | |
71 | ||
72 | if (speed == MAC_SPEED_10000) | |
73 | speed_reg = 1; | |
74 | ||
75 | value = mac_cb->cpld_led_value; | |
76 | ||
77 | if (link_status) { | |
78 | dsaf_set_bit(value, DSAF_LED_LINK_B, link_status); | |
79 | dsaf_set_field(value, DSAF_LED_SPEED_M, | |
80 | DSAF_LED_SPEED_S, speed_reg); | |
81 | dsaf_set_bit(value, DSAF_LED_DATA_B, data); | |
82 | ||
83 | if (value != mac_cb->cpld_led_value) { | |
31d4446d YZZ |
84 | dsaf_write_syscon(mac_cb->cpld_ctrl, |
85 | mac_cb->cpld_ctrl_reg, value); | |
511e6bc0 | 86 | mac_cb->cpld_led_value = value; |
87 | } | |
88 | } else { | |
d8a8371e DH |
89 | value = (mac_cb->cpld_led_value) & (0x1 << DSAF_LED_ANCHOR_B); |
90 | dsaf_write_syscon(mac_cb->cpld_ctrl, | |
91 | mac_cb->cpld_ctrl_reg, value); | |
92 | mac_cb->cpld_led_value = value; | |
511e6bc0 | 93 | } |
94 | } | |
95 | ||
a24274aa | 96 | static void cpld_led_reset(struct hns_mac_cb *mac_cb) |
511e6bc0 | 97 | { |
31d4446d | 98 | if (!mac_cb || !mac_cb->cpld_ctrl) |
511e6bc0 | 99 | return; |
100 | ||
31d4446d YZZ |
101 | dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg, |
102 | CPLD_LED_DEFAULT_VALUE); | |
511e6bc0 | 103 | mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE; |
104 | } | |
105 | ||
a24274aa KY |
106 | static int cpld_set_led_id(struct hns_mac_cb *mac_cb, |
107 | enum hnae_led_state status) | |
511e6bc0 | 108 | { |
109 | switch (status) { | |
110 | case HNAE_LED_ACTIVE: | |
31d4446d YZZ |
111 | mac_cb->cpld_led_value = |
112 | dsaf_read_syscon(mac_cb->cpld_ctrl, | |
113 | mac_cb->cpld_ctrl_reg); | |
511e6bc0 | 114 | dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B, |
115 | CPLD_LED_ON_VALUE); | |
31d4446d YZZ |
116 | dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg, |
117 | mac_cb->cpld_led_value); | |
d8a8371e | 118 | break; |
511e6bc0 | 119 | case HNAE_LED_INACTIVE: |
120 | dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B, | |
121 | CPLD_LED_DEFAULT_VALUE); | |
31d4446d YZZ |
122 | dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg, |
123 | mac_cb->cpld_led_value); | |
511e6bc0 | 124 | break; |
125 | default: | |
d8a8371e DH |
126 | dev_err(mac_cb->dev, "invalid led state: %d!", status); |
127 | return -EINVAL; | |
511e6bc0 | 128 | } |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | #define RESET_REQ_OR_DREQ 1 | |
134 | ||
f00ef863 KY |
135 | static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type, |
136 | u32 port_type, u32 port, u32 val) | |
137 | { | |
138 | union acpi_object *obj; | |
139 | union acpi_object obj_args[3], argv4; | |
140 | ||
141 | obj_args[0].integer.type = ACPI_TYPE_INTEGER; | |
142 | obj_args[0].integer.value = port_type; | |
143 | obj_args[1].integer.type = ACPI_TYPE_INTEGER; | |
144 | obj_args[1].integer.value = port; | |
145 | obj_args[2].integer.type = ACPI_TYPE_INTEGER; | |
146 | obj_args[2].integer.value = val; | |
147 | ||
148 | argv4.type = ACPI_TYPE_PACKAGE; | |
149 | argv4.package.count = 3; | |
150 | argv4.package.elements = obj_args; | |
151 | ||
152 | obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev), | |
94116f81 | 153 | &hns_dsaf_acpi_dsm_guid, 0, op_type, &argv4); |
f00ef863 KY |
154 | if (!obj) { |
155 | dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!", | |
156 | port_type, port); | |
157 | return; | |
158 | } | |
159 | ||
160 | ACPI_FREE(obj); | |
161 | } | |
162 | ||
a24274aa | 163 | static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset) |
511e6bc0 | 164 | { |
165 | u32 xbar_reg_addr; | |
166 | u32 nt_reg_addr; | |
167 | ||
a24274aa | 168 | if (!dereset) { |
511e6bc0 | 169 | xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG; |
170 | nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG; | |
171 | } else { | |
172 | xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG; | |
173 | nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG; | |
174 | } | |
175 | ||
831d828b YZZ |
176 | dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ); |
177 | dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ); | |
511e6bc0 | 178 | } |
179 | ||
f00ef863 KY |
180 | static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset) |
181 | { | |
182 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, | |
183 | HNS_DSAF_RESET_FUNC, | |
184 | 0, dereset); | |
185 | } | |
186 | ||
a24274aa KY |
187 | static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, |
188 | bool dereset) | |
511e6bc0 | 189 | { |
190 | u32 reg_val = 0; | |
191 | u32 reg_addr; | |
192 | ||
193 | if (port >= DSAF_XGE_NUM) | |
194 | return; | |
195 | ||
196 | reg_val |= RESET_REQ_OR_DREQ; | |
850bfa3b | 197 | reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off; |
511e6bc0 | 198 | |
a24274aa | 199 | if (!dereset) |
511e6bc0 | 200 | reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG; |
201 | else | |
202 | reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG; | |
203 | ||
831d828b | 204 | dsaf_write_sub(dsaf_dev, reg_addr, reg_val); |
511e6bc0 | 205 | } |
206 | ||
f00ef863 KY |
207 | static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev, |
208 | u32 port, bool dereset) | |
209 | { | |
210 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, | |
211 | HNS_XGE_RESET_FUNC, port, dereset); | |
212 | } | |
213 | ||
e0180688 | 214 | /** |
215 | * hns_dsaf_srst_chns - reset dsaf channels | |
216 | * @dsaf_dev: dsaf device struct pointer | |
217 | * @msk: xbar channels mask value: | |
218 | * bit0-5 for xge0-5 | |
219 | * bit6-11 for ppe0-5 | |
220 | * bit12-17 for roce0-5 | |
221 | * bit18-19 for com/dfx | |
222 | * @enable: false - request reset , true - drop reset | |
223 | */ | |
d605916b | 224 | void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool dereset) |
e0180688 | 225 | { |
226 | u32 reg_addr; | |
227 | ||
d605916b | 228 | if (!dereset) |
e0180688 | 229 | reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG; |
230 | else | |
231 | reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG; | |
232 | ||
233 | dsaf_write_sub(dsaf_dev, reg_addr, msk); | |
234 | } | |
235 | ||
d605916b S |
236 | /** |
237 | * hns_dsaf_srst_chns - reset dsaf channels | |
238 | * @dsaf_dev: dsaf device struct pointer | |
239 | * @msk: xbar channels mask value: | |
240 | * bit0-5 for xge0-5 | |
241 | * bit6-11 for ppe0-5 | |
242 | * bit12-17 for roce0-5 | |
243 | * bit18-19 for com/dfx | |
244 | * @enable: false - request reset , true - drop reset | |
245 | */ | |
246 | void | |
247 | hns_dsaf_srst_chns_acpi(struct dsaf_device *dsaf_dev, u32 msk, bool dereset) | |
e0180688 | 248 | { |
d605916b S |
249 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, |
250 | HNS_DSAF_CHN_RESET_FUNC, | |
251 | msk, dereset); | |
252 | } | |
253 | ||
254 | void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool dereset) | |
255 | { | |
256 | if (!dereset) { | |
e0180688 | 257 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_RESET_REQ_REG, 1); |
258 | } else { | |
259 | dsaf_write_sub(dsaf_dev, | |
260 | DSAF_SUB_SC_ROCEE_CLK_DIS_REG, 1); | |
261 | dsaf_write_sub(dsaf_dev, | |
262 | DSAF_SUB_SC_ROCEE_RESET_DREQ_REG, 1); | |
263 | msleep(20); | |
264 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_CLK_EN_REG, 1); | |
265 | } | |
266 | } | |
267 | ||
d605916b S |
268 | void hns_dsaf_roce_srst_acpi(struct dsaf_device *dsaf_dev, bool dereset) |
269 | { | |
270 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, | |
271 | HNS_ROCE_RESET_FUNC, 0, dereset); | |
272 | } | |
273 | ||
a24274aa KY |
274 | static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, |
275 | bool dereset) | |
511e6bc0 | 276 | { |
277 | u32 reg_val_1; | |
278 | u32 reg_val_2; | |
850bfa3b | 279 | u32 port_rst_off; |
511e6bc0 | 280 | |
281 | if (port >= DSAF_GE_NUM) | |
282 | return; | |
283 | ||
89a44093 | 284 | if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) { |
511e6bc0 | 285 | reg_val_1 = 0x1 << port; |
850bfa3b | 286 | port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off; |
13ac695e | 287 | /* there is difference between V1 and V2 in register.*/ |
d9fdb4ed DH |
288 | reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? |
289 | 0x1041041 : 0x2082082; | |
290 | reg_val_2 <<= port_rst_off; | |
511e6bc0 | 291 | |
a24274aa | 292 | if (!dereset) { |
831d828b | 293 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG, |
511e6bc0 | 294 | reg_val_1); |
295 | ||
831d828b | 296 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG, |
511e6bc0 | 297 | reg_val_2); |
298 | } else { | |
831d828b | 299 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG, |
511e6bc0 | 300 | reg_val_2); |
301 | ||
831d828b | 302 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG, |
511e6bc0 | 303 | reg_val_1); |
304 | } | |
305 | } else { | |
d9fdb4ed DH |
306 | reg_val_1 = 0x15540; |
307 | reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40; | |
0b03fd85 | 308 | |
d9fdb4ed DH |
309 | reg_val_1 <<= dsaf_dev->reset_offset; |
310 | reg_val_2 <<= dsaf_dev->reset_offset; | |
511e6bc0 | 311 | |
a24274aa | 312 | if (!dereset) { |
831d828b | 313 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG, |
511e6bc0 | 314 | reg_val_1); |
315 | ||
831d828b | 316 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG, |
511e6bc0 | 317 | reg_val_2); |
318 | } else { | |
831d828b | 319 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG, |
511e6bc0 | 320 | reg_val_1); |
321 | ||
831d828b | 322 | dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG, |
511e6bc0 | 323 | reg_val_2); |
324 | } | |
325 | } | |
326 | } | |
327 | ||
f00ef863 KY |
328 | static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev, |
329 | u32 port, bool dereset) | |
330 | { | |
331 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, | |
332 | HNS_GE_RESET_FUNC, port, dereset); | |
333 | } | |
334 | ||
a24274aa KY |
335 | static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, |
336 | bool dereset) | |
511e6bc0 | 337 | { |
338 | u32 reg_val = 0; | |
339 | u32 reg_addr; | |
340 | ||
850bfa3b | 341 | reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off; |
511e6bc0 | 342 | |
a24274aa | 343 | if (!dereset) |
511e6bc0 | 344 | reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG; |
345 | else | |
346 | reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG; | |
347 | ||
831d828b | 348 | dsaf_write_sub(dsaf_dev, reg_addr, reg_val); |
511e6bc0 | 349 | } |
350 | ||
f00ef863 KY |
351 | static void |
352 | hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset) | |
353 | { | |
354 | hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, | |
355 | HNS_PPE_RESET_FUNC, port, dereset); | |
356 | } | |
357 | ||
a24274aa | 358 | static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset) |
511e6bc0 | 359 | { |
511e6bc0 | 360 | u32 reg_val; |
361 | u32 reg_addr; | |
362 | ||
f00ef863 KY |
363 | if (!(dev_of_node(dsaf_dev->dev))) |
364 | return; | |
365 | ||
89a44093 | 366 | if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) { |
511e6bc0 | 367 | reg_val = RESET_REQ_OR_DREQ; |
a24274aa | 368 | if (!dereset) |
511e6bc0 | 369 | reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG; |
370 | else | |
371 | reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG; | |
372 | ||
373 | } else { | |
422c3107 | 374 | reg_val = 0x100 << dsaf_dev->reset_offset; |
511e6bc0 | 375 | |
a24274aa | 376 | if (!dereset) |
511e6bc0 | 377 | reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG; |
378 | else | |
379 | reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG; | |
380 | } | |
381 | ||
831d828b | 382 | dsaf_write_sub(dsaf_dev, reg_addr, reg_val); |
511e6bc0 | 383 | } |
384 | ||
385 | /** | |
386 | * hns_mac_get_sds_mode - get phy ifterface form serdes mode | |
387 | * @mac_cb: mac control block | |
388 | * retuen phy interface | |
389 | */ | |
a24274aa | 390 | static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb) |
511e6bc0 | 391 | { |
c1203fe7 SL |
392 | u32 mode; |
393 | u32 reg; | |
c1203fe7 | 394 | bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver); |
c1203fe7 | 395 | int mac_id = mac_cb->mac_id; |
0d768fc6 | 396 | phy_interface_t phy_if; |
511e6bc0 | 397 | |
0d768fc6 YZZ |
398 | if (is_ver1) { |
399 | if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) | |
400 | return PHY_INTERFACE_MODE_SGMII; | |
401 | ||
402 | if (mac_id >= 0 && mac_id <= 3) | |
403 | reg = HNS_MAC_HILINK4_REG; | |
511e6bc0 | 404 | else |
0d768fc6 YZZ |
405 | reg = HNS_MAC_HILINK3_REG; |
406 | } else{ | |
407 | if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3) | |
408 | reg = HNS_MAC_HILINK4V2_REG; | |
c1203fe7 | 409 | else |
0d768fc6 | 410 | reg = HNS_MAC_HILINK3V2_REG; |
511e6bc0 | 411 | } |
0d768fc6 YZZ |
412 | |
413 | mode = dsaf_read_sub(mac_cb->dsaf_dev, reg); | |
414 | if (dsaf_get_bit(mode, mac_cb->port_mode_off)) | |
415 | phy_if = PHY_INTERFACE_MODE_XGMII; | |
416 | else | |
417 | phy_if = PHY_INTERFACE_MODE_SGMII; | |
418 | ||
511e6bc0 | 419 | return phy_if; |
420 | } | |
421 | ||
f00ef863 KY |
422 | static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb) |
423 | { | |
424 | phy_interface_t phy_if = PHY_INTERFACE_MODE_NA; | |
425 | union acpi_object *obj; | |
426 | union acpi_object obj_args, argv4; | |
427 | ||
428 | obj_args.integer.type = ACPI_TYPE_INTEGER; | |
429 | obj_args.integer.value = mac_cb->mac_id; | |
430 | ||
431 | argv4.type = ACPI_TYPE_PACKAGE, | |
432 | argv4.package.count = 1, | |
433 | argv4.package.elements = &obj_args, | |
434 | ||
435 | obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev), | |
94116f81 | 436 | &hns_dsaf_acpi_dsm_guid, 0, |
f00ef863 KY |
437 | HNS_OP_GET_PORT_TYPE_FUNC, &argv4); |
438 | ||
439 | if (!obj || obj->type != ACPI_TYPE_INTEGER) | |
440 | return phy_if; | |
441 | ||
442 | phy_if = obj->integer.value ? | |
443 | PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII; | |
444 | ||
445 | dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if); | |
446 | ||
447 | ACPI_FREE(obj); | |
448 | ||
449 | return phy_if; | |
450 | } | |
451 | ||
31d4446d YZZ |
452 | int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt) |
453 | { | |
454 | if (!mac_cb->cpld_ctrl) | |
455 | return -ENODEV; | |
456 | ||
457 | *sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg | |
458 | + MAC_SFP_PORT_OFFSET); | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
b917078c DH |
463 | int hns_mac_get_sfp_prsnt_acpi(struct hns_mac_cb *mac_cb, int *sfp_prsnt) |
464 | { | |
465 | union acpi_object *obj; | |
466 | union acpi_object obj_args, argv4; | |
467 | ||
468 | obj_args.integer.type = ACPI_TYPE_INTEGER; | |
469 | obj_args.integer.value = mac_cb->mac_id; | |
470 | ||
471 | argv4.type = ACPI_TYPE_PACKAGE, | |
472 | argv4.package.count = 1, | |
473 | argv4.package.elements = &obj_args, | |
474 | ||
475 | obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev), | |
94116f81 | 476 | &hns_dsaf_acpi_dsm_guid, 0, |
b917078c DH |
477 | HNS_OP_GET_SFP_STAT_FUNC, &argv4); |
478 | ||
479 | if (!obj || obj->type != ACPI_TYPE_INTEGER) | |
480 | return -ENODEV; | |
481 | ||
482 | *sfp_prsnt = obj->integer.value; | |
483 | ||
484 | ACPI_FREE(obj); | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
511e6bc0 | 489 | /** |
490 | * hns_mac_config_sds_loopback - set loop back for serdes | |
491 | * @mac_cb: mac control block | |
492 | * retuen 0 == success | |
493 | */ | |
a24274aa | 494 | static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en) |
511e6bc0 | 495 | { |
511e6bc0 | 496 | const u8 lane_id[] = { |
497 | 0, /* mac 0 -> lane 0 */ | |
498 | 1, /* mac 1 -> lane 1 */ | |
499 | 2, /* mac 2 -> lane 2 */ | |
500 | 3, /* mac 3 -> lane 3 */ | |
501 | 2, /* mac 4 -> lane 2 */ | |
502 | 3, /* mac 5 -> lane 3 */ | |
503 | 0, /* mac 6 -> lane 0 */ | |
504 | 1 /* mac 7 -> lane 1 */ | |
505 | }; | |
506 | #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2) | |
507 | u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0); | |
508 | ||
509 | int sfp_prsnt; | |
510 | int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt); | |
511 | ||
652d39b0 | 512 | if (!mac_cb->phy_dev) { |
511e6bc0 | 513 | if (ret) |
514 | pr_info("please confirm sfp is present or not\n"); | |
515 | else | |
516 | if (!sfp_prsnt) | |
517 | pr_info("no sfp in this eth\n"); | |
518 | } | |
519 | ||
831d828b | 520 | if (mac_cb->serdes_ctrl) { |
89a6b1aa KY |
521 | u32 origin; |
522 | ||
523 | if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) { | |
524 | #define HILINK_ACCESS_SEL_CFG 0x40008 | |
525 | /* hilink4 & hilink3 use the same xge training and | |
526 | * xge u adaptor. There is a hilink access sel cfg | |
527 | * register to select which one to be configed | |
528 | */ | |
529 | if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) && | |
530 | (mac_cb->mac_id <= 3)) | |
531 | dsaf_write_syscon(mac_cb->serdes_ctrl, | |
532 | HILINK_ACCESS_SEL_CFG, 0); | |
533 | else | |
534 | dsaf_write_syscon(mac_cb->serdes_ctrl, | |
535 | HILINK_ACCESS_SEL_CFG, 3); | |
536 | } | |
537 | ||
538 | origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset); | |
831d828b | 539 | |
a24274aa | 540 | dsaf_set_field(origin, 1ull << 10, 10, en); |
831d828b YZZ |
541 | dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin); |
542 | } else { | |
89a6b1aa KY |
543 | u8 *base_addr = (u8 *)mac_cb->serdes_vaddr + |
544 | (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000); | |
a24274aa | 545 | dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en); |
831d828b | 546 | } |
511e6bc0 | 547 | |
548 | return 0; | |
549 | } | |
a24274aa | 550 | |
f00ef863 KY |
551 | static int |
552 | hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en) | |
553 | { | |
554 | union acpi_object *obj; | |
555 | union acpi_object obj_args[3], argv4; | |
556 | ||
557 | obj_args[0].integer.type = ACPI_TYPE_INTEGER; | |
558 | obj_args[0].integer.value = mac_cb->mac_id; | |
559 | obj_args[1].integer.type = ACPI_TYPE_INTEGER; | |
560 | obj_args[1].integer.value = !!en; | |
561 | ||
562 | argv4.type = ACPI_TYPE_PACKAGE; | |
563 | argv4.package.count = 2; | |
564 | argv4.package.elements = obj_args; | |
565 | ||
566 | obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev), | |
94116f81 | 567 | &hns_dsaf_acpi_dsm_guid, 0, |
f00ef863 KY |
568 | HNS_OP_SERDES_LP_FUNC, &argv4); |
569 | if (!obj) { | |
570 | dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!", | |
571 | mac_cb->mac_id); | |
572 | ||
573 | return -ENOTSUPP; | |
574 | } | |
575 | ||
576 | ACPI_FREE(obj); | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
a24274aa KY |
581 | struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev) |
582 | { | |
583 | struct dsaf_misc_op *misc_op; | |
584 | ||
585 | misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL); | |
586 | if (!misc_op) | |
587 | return NULL; | |
588 | ||
8413b3be KY |
589 | if (dev_of_node(dsaf_dev->dev)) { |
590 | misc_op->cpld_set_led = hns_cpld_set_led; | |
591 | misc_op->cpld_reset_led = cpld_led_reset; | |
592 | misc_op->cpld_set_led_id = cpld_set_led_id; | |
593 | ||
594 | misc_op->dsaf_reset = hns_dsaf_rst; | |
595 | misc_op->xge_srst = hns_dsaf_xge_srst_by_port; | |
8413b3be KY |
596 | misc_op->ge_srst = hns_dsaf_ge_srst_by_port; |
597 | misc_op->ppe_srst = hns_ppe_srst_by_port; | |
598 | misc_op->ppe_comm_srst = hns_ppe_com_srst; | |
d605916b S |
599 | misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns; |
600 | misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst; | |
8413b3be KY |
601 | |
602 | misc_op->get_phy_if = hns_mac_get_phy_if; | |
603 | misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt; | |
604 | ||
605 | misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback; | |
f00ef863 KY |
606 | } else if (is_acpi_node(dsaf_dev->dev->fwnode)) { |
607 | misc_op->cpld_set_led = hns_cpld_set_led; | |
608 | misc_op->cpld_reset_led = cpld_led_reset; | |
609 | misc_op->cpld_set_led_id = cpld_set_led_id; | |
610 | ||
611 | misc_op->dsaf_reset = hns_dsaf_rst_acpi; | |
612 | misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi; | |
f00ef863 KY |
613 | misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi; |
614 | misc_op->ppe_srst = hns_ppe_srst_by_port_acpi; | |
615 | misc_op->ppe_comm_srst = hns_ppe_com_srst; | |
d605916b S |
616 | misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns_acpi; |
617 | misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst_acpi; | |
f00ef863 KY |
618 | |
619 | misc_op->get_phy_if = hns_mac_get_phy_if_acpi; | |
b917078c | 620 | misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt_acpi; |
f00ef863 KY |
621 | |
622 | misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi; | |
623 | } else { | |
624 | devm_kfree(dsaf_dev->dev, (void *)misc_op); | |
625 | misc_op = NULL; | |
8413b3be | 626 | } |
a24274aa KY |
627 | |
628 | return (void *)misc_op; | |
629 | } | |
d605916b S |
630 | |
631 | static int hns_dsaf_dev_match(struct device *dev, void *fwnode) | |
632 | { | |
633 | return dev->fwnode == fwnode; | |
634 | } | |
635 | ||
636 | struct | |
637 | platform_device *hns_dsaf_find_platform_device(struct fwnode_handle *fwnode) | |
638 | { | |
639 | struct device *dev; | |
640 | ||
641 | dev = bus_find_device(&platform_bus_type, NULL, | |
642 | fwnode, hns_dsaf_dev_match); | |
643 | return dev ? to_platform_device(dev) : NULL; | |
644 | } |