[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_misc.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include "hns_dsaf_mac.h"
#include "hns_dsaf_misc.h"
#include "hns_dsaf_ppe.h"
#include "hns_dsaf_reg.h"

static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
{
	if (dsaf_dev->sub_ctrl)
		dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	else
		dsaf_write_reg(dsaf_dev->sc_base, reg, val);
}

static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
{
	u32 ret;

	if (dsaf_dev->sub_ctrl)
		ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	else
		ret = dsaf_read_reg(dsaf_dev->sc_base, reg);

	return ret;
}

void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
		      u16 speed, int data)
{
	int speed_reg = 0;
	u8 value;

	if (!mac_cb) {
		pr_err("sfp_led_opt mac_dev is null!\n");
		return;
	}
	if (!mac_cb->cpld_ctrl) {
		dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
			mac_cb->mac_id);
		return;
	}

	if (speed == MAC_SPEED_10000)
		speed_reg = 1;

	value = mac_cb->cpld_led_value;

	if (link_status) {
		dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
		dsaf_set_field(value, DSAF_LED_SPEED_M,
			       DSAF_LED_SPEED_S, speed_reg);
		dsaf_set_bit(value, DSAF_LED_DATA_B, data);

		if (value != mac_cb->cpld_led_value) {
			dsaf_write_syscon(mac_cb->cpld_ctrl,
					  mac_cb->cpld_ctrl_reg, value);
			mac_cb->cpld_led_value = value;
		}
	} else {
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  CPLD_LED_DEFAULT_VALUE);
		mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	}
}

void cpld_led_reset(struct hns_mac_cb *mac_cb)
{
	if (!mac_cb || !mac_cb->cpld_ctrl)
		return;

	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
			  CPLD_LED_DEFAULT_VALUE);
	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
}

int cpld_set_led_id(struct hns_mac_cb *mac_cb,
		    enum hnae_led_state status)
{
	switch (status) {
	case HNAE_LED_ACTIVE:
		mac_cb->cpld_led_value =
			dsaf_read_syscon(mac_cb->cpld_ctrl,
					 mac_cb->cpld_ctrl_reg);
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_ON_VALUE);
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  mac_cb->cpld_led_value);
		return 2;
	case HNAE_LED_INACTIVE:
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_DEFAULT_VALUE);
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  mac_cb->cpld_led_value);
		break;
	default:
		break;
	}

	return 0;
}

#define RESET_REQ_OR_DREQ 1

void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
{
	u32 xbar_reg_addr;
	u32 nt_reg_addr;

	if (!val) {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	} else {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
}

void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= RESET_REQ_OR_DREQ;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		reg_val |= 0x2082082 << port;
	else
		reg_val |= 0x2082082 << (dsaf_dev->reset_offset + 6);

	if (val == 0)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
				    u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		reg_val |= XGMAC_TRX_CORE_SRST_M << port;
	else
		reg_val |= XGMAC_TRX_CORE_SRST_M <<
			(dsaf_dev->reset_offset + 6);

	if (val == 0)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val_1;
	u32 reg_val_2;

	if (port >= DSAF_GE_NUM)
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val_1  = 0x1 << port;
		/* there is difference between V1 and V2 in register.*/
		if (AE_IS_VER1(dsaf_dev->dsaf_ver))
			reg_val_2  = 0x1041041 << port;
		else
			reg_val_2  = 0x2082082 << port;

		if (val == 0) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
				       reg_val_2);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);
		}
	} else {
		reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
		reg_val_2 = 0x100 << dsaf_dev->reset_offset;

		if (val == 0) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
				       reg_val_2);
		}
	}
}

void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		reg_val |= RESET_REQ_OR_DREQ << port;
	else
		reg_val |= RESET_REQ_OR_DREQ <<
			(dsaf_dev->reset_offset + 6);

	if (val == 0)
		reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
{
	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
	u32 reg_val;
	u32 reg_addr;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val = RESET_REQ_OR_DREQ;
		if (val == 0)
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;

	} else {
		reg_val = 0x100 << dsaf_dev->reset_offset;

		if (val == 0)
			reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

/**
 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
 * @mac_cb: mac control block
 * retuen phy interface
 */
phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
{
	u32 mode;
	u32 reg;
	u32 shift;
	u32 phy_offset;
	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
	int mac_id = mac_cb->mac_id;
	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;

	if (is_ver1 && HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
		phy_if = PHY_INTERFACE_MODE_SGMII;
	} else if (mac_id >= 0 && mac_id <= 3 &&
		   !HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
		reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG;
		mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
		/* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
		shift = is_ver1 ? 0 : mac_id;
		if (dsaf_get_bit(mode, shift))
			phy_if = PHY_INTERFACE_MODE_XGMII;
		else
			phy_if = PHY_INTERFACE_MODE_SGMII;
	} else {
		reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG;
		mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
		/* mac_id 4, 5,---> hilink3 lane 2, 3
		 * debug port 0(6), 1(7) ---> hilink3 lane 0, 1
		 */
		phy_offset = mac_cb->dsaf_dev->reset_offset - 1;
		shift = is_ver1 ? 0 : mac_id >= 4 ? mac_id - 2 : phy_offset;
		if (dsaf_get_bit(mode, shift))
			phy_if = PHY_INTERFACE_MODE_XGMII;
		else
			phy_if = PHY_INTERFACE_MODE_SGMII;
	}
	return phy_if;
}

int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
{
	if (!mac_cb->cpld_ctrl)
		return -ENODEV;

	*sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
					+ MAC_SFP_PORT_OFFSET);

	return 0;
}

/**
 * hns_mac_config_sds_loopback - set loop back for serdes
 * @mac_cb: mac control block
 * retuen 0 == success
 */
int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
{
	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
	 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
	 */
	u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
		       (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
	const u8 lane_id[] = {
		0,	/* mac 0 -> lane 0 */
		1,	/* mac 1 -> lane 1 */
		2,	/* mac 2 -> lane 2 */
		3,	/* mac 3 -> lane 3 */
		2,	/* mac 4 -> lane 2 */
		3,	/* mac 5 -> lane 3 */
		0,	/* mac 6 -> lane 0 */
		1	/* mac 7 -> lane 1 */
	};
#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);

	int sfp_prsnt;
	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);

	if (!mac_cb->phy_node) {
		if (ret)
			pr_info("please confirm sfp is present or not\n");
		else
			if (!sfp_prsnt)
				pr_info("no sfp in this eth\n");
	}

	if (mac_cb->serdes_ctrl) {
		u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);

		dsaf_set_field(origin, 1ull << 10, 10, !!en);
		dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
	} else {
		dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
	}

	return 0;
}
Commit	Line	Data
511e6bc0	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
511e6bc0	10	#include "hns_dsaf_mac.h"
2e2591b1	11	#include "hns_dsaf_misc.h"
511e6bc0	12	#include "hns_dsaf_ppe.h"
2e2591b1	13	#include "hns_dsaf_reg.h"
511e6bc0	14
831d828b YZZ	15	static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
	16	{
	17	if (dsaf_dev->sub_ctrl)
	18	dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	19	else
	20	dsaf_write_reg(dsaf_dev->sc_base, reg, val);
	21	}
	22
	23	static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
	24	{
	25	u32 ret;
	26
	27	if (dsaf_dev->sub_ctrl)
	28	ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	29	else
	30	ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
	31
	32	return ret;
	33	}
	34
511e6bc0	35	void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
	36	u16 speed, int data)
	37	{
	38	int speed_reg = 0;
	39	u8 value;
	40
	41	if (!mac_cb) {
	42	pr_err("sfp_led_opt mac_dev is null!\n");
	43	return;
	44	}
31d4446d YZZ	45	if (!mac_cb->cpld_ctrl) {
31d4446d YZZ	46	dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
511e6bc0	47	mac_cb->mac_id);
	48	return;
	49	}
	50
	51	if (speed == MAC_SPEED_10000)
	52	speed_reg = 1;
	53
	54	value = mac_cb->cpld_led_value;
	55
	56	if (link_status) {
	57	dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
	58	dsaf_set_field(value, DSAF_LED_SPEED_M,
	59	DSAF_LED_SPEED_S, speed_reg);
	60	dsaf_set_bit(value, DSAF_LED_DATA_B, data);
	61
	62	if (value != mac_cb->cpld_led_value) {
31d4446d YZZ	63	dsaf_write_syscon(mac_cb->cpld_ctrl,
31d4446d YZZ	64	mac_cb->cpld_ctrl_reg, value);
511e6bc0	65	mac_cb->cpld_led_value = value;
	66	}
	67	} else {
31d4446d YZZ	68	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	69	CPLD_LED_DEFAULT_VALUE);
511e6bc0	70	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	71	}
	72	}
	73
	74	void cpld_led_reset(struct hns_mac_cb *mac_cb)
	75	{
31d4446d	76	if (!mac_cb \|\| !mac_cb->cpld_ctrl)
511e6bc0	77	return;
511e6bc0	78
31d4446d YZZ	79	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	80	CPLD_LED_DEFAULT_VALUE);
511e6bc0	81	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	82	}
	83
	84	int cpld_set_led_id(struct hns_mac_cb *mac_cb,
	85	enum hnae_led_state status)
	86	{
	87	switch (status) {
	88	case HNAE_LED_ACTIVE:
31d4446d YZZ	89	mac_cb->cpld_led_value =
	90	dsaf_read_syscon(mac_cb->cpld_ctrl,
	91	mac_cb->cpld_ctrl_reg);
511e6bc0	92	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
511e6bc0	93	CPLD_LED_ON_VALUE);
31d4446d YZZ	94	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	95	mac_cb->cpld_led_value);
edc9b427	96	return 2;
511e6bc0	97	case HNAE_LED_INACTIVE:
	98	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
	99	CPLD_LED_DEFAULT_VALUE);
31d4446d YZZ	100	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	101	mac_cb->cpld_led_value);
511e6bc0	102	break;
	103	default:
	104	break;
	105	}
	106
	107	return 0;
	108	}
	109
	110	#define RESET_REQ_OR_DREQ 1
	111
	112	void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
	113	{
	114	u32 xbar_reg_addr;
	115	u32 nt_reg_addr;
	116
	117	if (!val) {
	118	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
	119	nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	120	} else {
	121	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
	122	nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	123	}
	124
831d828b YZZ	125	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
831d828b YZZ	126	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
511e6bc0	127	}
	128
	129	void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	130	{
	131	u32 reg_val = 0;
	132	u32 reg_addr;
	133
	134	if (port >= DSAF_XGE_NUM)
	135	return;
	136
	137	reg_val \|= RESET_REQ_OR_DREQ;
422c3107 YZZ	138
	139	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
	140	reg_val \|= 0x2082082 << port;
	141	else
	142	reg_val \|= 0x2082082 << (dsaf_dev->reset_offset + 6);
511e6bc0	143
	144	if (val == 0)
	145	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	146	else
	147	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	148
831d828b	149	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	150	}
	151
	152	void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
	153	u32 port, u32 val)
	154	{
	155	u32 reg_val = 0;
	156	u32 reg_addr;
	157
	158	if (port >= DSAF_XGE_NUM)
	159	return;
	160
422c3107 YZZ	161	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
	162	reg_val \|= XGMAC_TRX_CORE_SRST_M << port;
	163	else
	164	reg_val \|= XGMAC_TRX_CORE_SRST_M <<
	165	(dsaf_dev->reset_offset + 6);
511e6bc0	166
	167	if (val == 0)
	168	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	169	else
	170	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	171
831d828b	172	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	173	}
	174
	175	void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	176	{
	177	u32 reg_val_1;
	178	u32 reg_val_2;
	179
	180	if (port >= DSAF_GE_NUM)
	181	return;
	182
89a44093	183	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	184	reg_val_1 = 0x1 << port;
13ac695e S	185	/* there is difference between V1 and V2 in register.*/
	186	if (AE_IS_VER1(dsaf_dev->dsaf_ver))
	187	reg_val_2 = 0x1041041 << port;
	188	else
	189	reg_val_2 = 0x2082082 << port;
511e6bc0	190
511e6bc0	191	if (val == 0) {
831d828b	192	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	193	reg_val_1);
511e6bc0	194
831d828b	195	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
511e6bc0	196	reg_val_2);
511e6bc0	197	} else {
831d828b	198	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
511e6bc0	199	reg_val_2);
511e6bc0	200
831d828b	201	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	202	reg_val_1);
	203	}
	204	} else {
422c3107 YZZ	205	reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
422c3107 YZZ	206	reg_val_2 = 0x100 << dsaf_dev->reset_offset;
511e6bc0	207
511e6bc0	208	if (val == 0) {
831d828b	209	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	210	reg_val_1);
511e6bc0	211
831d828b	212	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
511e6bc0	213	reg_val_2);
511e6bc0	214	} else {
831d828b	215	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	216	reg_val_1);
511e6bc0	217
831d828b	218	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
511e6bc0	219	reg_val_2);
	220	}
	221	}
	222	}
	223
	224	void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	225	{
	226	u32 reg_val = 0;
	227	u32 reg_addr;
	228
422c3107 YZZ	229	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
	230	reg_val \|= RESET_REQ_OR_DREQ << port;
	231	else
	232	reg_val \|= RESET_REQ_OR_DREQ <<
	233	(dsaf_dev->reset_offset + 6);
511e6bc0	234
	235	if (val == 0)
	236	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	237	else
	238	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	239
831d828b	240	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	241	}
	242
	243	void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
	244	{
511e6bc0	245	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
	246	u32 reg_val;
	247	u32 reg_addr;
	248
89a44093	249	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	250	reg_val = RESET_REQ_OR_DREQ;
	251	if (val == 0)
	252	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
	253	else
	254	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
	255
	256	} else {
422c3107	257	reg_val = 0x100 << dsaf_dev->reset_offset;
511e6bc0	258
	259	if (val == 0)
	260	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	261	else
	262	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	263	}
	264
831d828b	265	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	266	}
	267
	268	/**
	269	* hns_mac_get_sds_mode - get phy ifterface form serdes mode
	270	* @mac_cb: mac control block
	271	* retuen phy interface
	272	*/
	273	phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
	274	{
c1203fe7 SL	275	u32 mode;
	276	u32 reg;
	277	u32 shift;
422c3107	278	u32 phy_offset;
c1203fe7	279	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
c1203fe7	280	int mac_id = mac_cb->mac_id;
511e6bc0	281	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
511e6bc0	282
422c3107	283	if (is_ver1 && HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
c1203fe7	284	phy_if = PHY_INTERFACE_MODE_SGMII;
422c3107 YZZ	285	} else if (mac_id >= 0 && mac_id <= 3 &&
422c3107 YZZ	286	!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
c1203fe7	287	reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG;
831d828b	288	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
c1203fe7 SL	289	/* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
	290	shift = is_ver1 ? 0 : mac_id;
	291	if (dsaf_get_bit(mode, shift))
511e6bc0	292	phy_if = PHY_INTERFACE_MODE_XGMII;
511e6bc0	293	else
c1203fe7	294	phy_if = PHY_INTERFACE_MODE_SGMII;
422c3107	295	} else {
c1203fe7	296	reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG;
831d828b	297	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
422c3107 YZZ	298	/* mac_id 4, 5,---> hilink3 lane 2, 3
	299	* debug port 0(6), 1(7) ---> hilink3 lane 0, 1
	300	*/
	301	phy_offset = mac_cb->dsaf_dev->reset_offset - 1;
	302	shift = is_ver1 ? 0 : mac_id >= 4 ? mac_id - 2 : phy_offset;
c1203fe7	303	if (dsaf_get_bit(mode, shift))
511e6bc0	304	phy_if = PHY_INTERFACE_MODE_XGMII;
c1203fe7 SL	305	else
c1203fe7 SL	306	phy_if = PHY_INTERFACE_MODE_SGMII;
511e6bc0	307	}
511e6bc0	308	return phy_if;
	309	}
	310
31d4446d YZZ	311	int hns_mac_get_sfp_prsnt(struct hns_mac_cb mac_cb, int sfp_prsnt)
	312	{
	313	if (!mac_cb->cpld_ctrl)
	314	return -ENODEV;
	315
	316	*sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
	317	+ MAC_SFP_PORT_OFFSET);
	318
	319	return 0;
	320	}
	321
511e6bc0	322	/**
	323	* hns_mac_config_sds_loopback - set loop back for serdes
	324	* @mac_cb: mac control block
	325	* retuen 0 == success
	326	*/
	327	int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
	328	{
	329	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
	330	* port 4-7 hilink3 base is serdes_vaddr + 0x00200000
	331	*/
	332	u8 base_addr = (u8 )mac_cb->serdes_vaddr +
	333	(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
	334	const u8 lane_id[] = {
	335	0, /* mac 0 -> lane 0 */
	336	1, /* mac 1 -> lane 1 */
	337	2, /* mac 2 -> lane 2 */
	338	3, /* mac 3 -> lane 3 */
	339	2, /* mac 4 -> lane 2 */
	340	3, /* mac 5 -> lane 3 */
	341	0, /* mac 6 -> lane 0 */
	342	1 /* mac 7 -> lane 1 */
	343	};
	344	#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	345	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
	346
	347	int sfp_prsnt;
	348	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
	349
	350	if (!mac_cb->phy_node) {
	351	if (ret)
	352	pr_info("please confirm sfp is present or not\n");
	353	else
	354	if (!sfp_prsnt)
	355	pr_info("no sfp in this eth\n");
	356	}
	357
831d828b YZZ	358	if (mac_cb->serdes_ctrl) {
	359	u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
	360
	361	dsaf_set_field(origin, 1ull << 10, 10, !!en);
	362	dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
	363	} else {
	364	dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
	365	}
511e6bc0	366
	367	return 0;
	368	}