[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_ppe.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>

#include "hns_dsaf_ppe.h"

void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value)
{
	dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
}

void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
			 const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
{
	u32 key_item;

	for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
		dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
			       rss_key[key_item]);
}

void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
			     const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
{
	int i;
	int reg_value;

	for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
		reg_value = dsaf_read_dev(ppe_cb,
					  PPEV2_INDRECTION_TBL_REG + i * 0x4);

		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
			       PPEV2_CFG_RSS_TBL_4N0_S,
			       rss_tab[i * 4 + 0] & 0x1F);
		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
			       PPEV2_CFG_RSS_TBL_4N1_S,
				rss_tab[i * 4 + 1] & 0x1F);
		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
			       PPEV2_CFG_RSS_TBL_4N2_S,
				rss_tab[i * 4 + 2] & 0x1F);
		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
			       PPEV2_CFG_RSS_TBL_4N3_S,
				rss_tab[i * 4 + 3] & 0x1F);
		dsaf_write_dev(
			ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
	}
}

static void __iomem *
hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common)
{
	return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET;
}

/**
 * hns_ppe_common_get_cfg - get ppe common config
 * @dsaf_dev: dasf device
 * comm_index: common index
 * retuen 0 - success , negative --fail
 */
static int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index)
{
	struct ppe_common_cb *ppe_common;
	int ppe_num;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM;
	else
		ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM;

	ppe_common = devm_kzalloc(dsaf_dev->dev, sizeof(*ppe_common) +
		ppe_num * sizeof(struct hns_ppe_cb), GFP_KERNEL);
	if (!ppe_common)
		return -ENOMEM;

	ppe_common->ppe_num = ppe_num;
	ppe_common->dsaf_dev = dsaf_dev;
	ppe_common->comm_index = comm_index;
	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
	else
		ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
	ppe_common->dev = dsaf_dev->dev;

	ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);

	dsaf_dev->ppe_common[comm_index] = ppe_common;

	return 0;
}

static void
hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index)
{
	dsaf_dev->ppe_common[comm_index] = NULL;
}

static void __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common,
					int ppe_idx)
{
	return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET;
}

static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
{
	u32 i;
	struct hns_ppe_cb *ppe_cb;
	u32 ppe_num = ppe_common->ppe_num;

	for (i = 0; i < ppe_num; i++) {
		ppe_cb = &ppe_common->ppe_cb[i];
		ppe_cb->dev = ppe_common->dev;
		ppe_cb->next = NULL;
		ppe_cb->ppe_common_cb = ppe_common;
		ppe_cb->index = i;
		ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
		ppe_cb->virq = 0;
	}
}

static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
{
	dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
			 PPE_CNT_CLR_CE_B, 1);
}

static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
{
	dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
}

/**
 * hns_ppe_checksum_hw - set ppe checksum caculate
 * @ppe_device: ppe device
 * @value: value
 */
static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value)
{
	dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
			   0xfffffff, 0, value);
}

static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
				 enum ppe_qid_mode qid_mdoe)
{
	dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
			   PPE_CFG_QID_MODE_CF_QID_MODE_M,
			   PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe);
}

/**
 * hns_ppe_set_qid - set ppe qid
 * @ppe_common: ppe common device
 * @qid: queue id
 */
static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
{
	u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);

	if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
			    PPE_CFG_QID_MODE_DEF_QID_S)) {
		dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
			       PPE_CFG_QID_MODE_DEF_QID_S, qid);
		dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
	}
}

/**
 * hns_ppe_set_port_mode - set port mode
 * @ppe_device: ppe device
 * @mode: port mode
 */
static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
				  enum ppe_port_mode mode)
{
	dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
}

/**
 * hns_ppe_common_init_hw - init ppe common device
 * @ppe_common: ppe common device
 *
 * Return 0 on success, negative on failure
 */
static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
{
	enum ppe_qid_mode qid_mode;
	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
	enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;

	dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 0);
	mdelay(100);
	dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 1);
	mdelay(100);

	if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
		switch (dsaf_mode) {
		case DSAF_MODE_ENABLE_FIX:
		case DSAF_MODE_DISABLE_FIX:
			qid_mode = PPE_QID_MODE0;
			hns_ppe_set_qid(ppe_common, 0);
			break;
		case DSAF_MODE_ENABLE_0VM:
		case DSAF_MODE_DISABLE_2PORT_64VM:
			qid_mode = PPE_QID_MODE3;
			break;
		case DSAF_MODE_ENABLE_8VM:
		case DSAF_MODE_DISABLE_2PORT_16VM:
			qid_mode = PPE_QID_MODE4;
			break;
		case DSAF_MODE_ENABLE_16VM:
		case DSAF_MODE_DISABLE_6PORT_0VM:
			qid_mode = PPE_QID_MODE5;
			break;
		case DSAF_MODE_ENABLE_32VM:
		case DSAF_MODE_DISABLE_6PORT_16VM:
			qid_mode = PPE_QID_MODE2;
			break;
		case DSAF_MODE_ENABLE_128VM:
		case DSAF_MODE_DISABLE_6PORT_4VM:
			qid_mode = PPE_QID_MODE1;
			break;
		case DSAF_MODE_DISABLE_2PORT_8VM:
			qid_mode = PPE_QID_MODE7;
			break;
		case DSAF_MODE_DISABLE_6PORT_2VM:
			qid_mode = PPE_QID_MODE6;
			break;
		default:
			dev_err(ppe_common->dev,
				"get ppe queue mode failed! dsaf_mode=%d\n",
				dsaf_mode);
			return -EINVAL;
		}
		hns_ppe_set_qid_mode(ppe_common, qid_mode);
	}

	dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
			 PPE_COMMON_CNT_CLR_CE_B, 1);

	return 0;
}

/*clr ppe exception irq*/
static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
{
	u32 clr_vlue = 0xfffffffful;
	u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
	u32 vld_msk = 0;

	/*only care bit 0,1,7*/
	dsaf_set_bit(vld_msk, 0, 1);
	dsaf_set_bit(vld_msk, 1, 1);
	dsaf_set_bit(vld_msk, 7, 1);

	/*clr sts**/
	dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);

	/*for some reserved bits, so set 0**/
	dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
}

/**
 * ppe_init_hw - init ppe
 * @ppe_cb: ppe device
 */
static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
{
	struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
	u32 port = ppe_cb->index;
	struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
	int i;

	/* get default RSS key */
	netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);

	dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
	mdelay(10);
	dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 1);

	/* clr and msk except irq*/
	hns_ppe_exc_irq_en(ppe_cb, 0);

	if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
		hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
		dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
	} else {
		hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
	}

	hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
	hns_ppe_cnt_clr_ce(ppe_cb);

	if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
		hns_ppe_set_vlan_strip(ppe_cb, 0);

		dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
			       HNS_PPEV2_MAX_FRAME_LEN);

		/* set default RSS key in h/w */
		hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);

		/* Set default indrection table in h/w */
		for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
			ppe_cb->rss_indir_table[i] = i;
		hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
	}
}

/**
 * ppe_uninit_hw - uninit ppe
 * @ppe_device: ppe device
 */
static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb)
{
	u32 port;

	if (ppe_cb->ppe_common_cb) {
		struct dsaf_device *dsaf_dev = ppe_cb->ppe_common_cb->dsaf_dev;

		port = ppe_cb->index;
		dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
	}
}

static void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
{
	u32 i;

	for (i = 0; i < ppe_common->ppe_num; i++) {
		if (ppe_common->dsaf_dev->mac_cb[i])
			hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
		memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
	}
}

void hns_ppe_uninit(struct dsaf_device *dsaf_dev)
{
	u32 i;

	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
		if (dsaf_dev->ppe_common[i])
			hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
		hns_rcb_common_free_cfg(dsaf_dev, i);
		hns_ppe_common_free_cfg(dsaf_dev, i);
	}
}

/**
 * hns_ppe_reset - reinit ppe/rcb hw
 * @dsaf_dev: dasf device
 * retuen void
 */
void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index)
{
	u32 i;
	int ret;
	struct ppe_common_cb *ppe_common;

	ppe_common = dsaf_dev->ppe_common[ppe_common_index];
	ret = hns_ppe_common_init_hw(ppe_common);
	if (ret)
		return;

	for (i = 0; i < ppe_common->ppe_num; i++) {
		/* We only need to initiate ppe when the port exists */
		if (dsaf_dev->mac_cb[i])
			hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
	}

	ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]);
	if (ret)
		return;

	hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]);
}

void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
{
	struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;

	hw_stats->rx_pkts_from_sw
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
	hw_stats->rx_pkts
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
	hw_stats->rx_drop_no_bd
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
	hw_stats->rx_alloc_buf_fail
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
	hw_stats->rx_alloc_buf_wait
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
	hw_stats->rx_drop_no_buf
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
	hw_stats->rx_err_fifo_full
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);

	hw_stats->tx_bd_form_rcb
		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
	hw_stats->tx_pkts_from_rcb
		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
	hw_stats->tx_pkts
		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
	hw_stats->tx_err_fifo_empty
		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
	hw_stats->tx_err_checksum
		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
}

int hns_ppe_get_sset_count(int stringset)
{
	if (stringset == ETH_SS_STATS)
		return ETH_PPE_STATIC_NUM;
	return 0;
}

int hns_ppe_get_regs_count(void)
{
	return ETH_PPE_DUMP_NUM;
}

/**
 * ppe_get_strings - get ppe srting
 * @ppe_device: ppe device
 * @stringset: string set type
 * @data: output string
 */
void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data)
{
	char *buff = (char *)data;
	int index = ppe_cb->index;

	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index);
	buff = buff + ETH_GSTRING_LEN;

	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index);
}

void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data)
{
	u64 *regs_buff = data;
	struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;

	regs_buff[0] = hw_stats->rx_pkts_from_sw;
	regs_buff[1] = hw_stats->rx_pkts;
	regs_buff[2] = hw_stats->rx_drop_no_bd;
	regs_buff[3] = hw_stats->rx_alloc_buf_fail;
	regs_buff[4] = hw_stats->rx_alloc_buf_wait;
	regs_buff[5] = hw_stats->rx_drop_no_buf;
	regs_buff[6] = hw_stats->rx_err_fifo_full;

	regs_buff[7] = hw_stats->tx_bd_form_rcb;
	regs_buff[8] = hw_stats->tx_pkts_from_rcb;
	regs_buff[9] = hw_stats->tx_pkts;
	regs_buff[10] = hw_stats->tx_err_fifo_empty;
	regs_buff[11] = hw_stats->tx_err_checksum;
}

/**
 * hns_ppe_init - init ppe device
 * @dsaf_dev: dasf device
 * retuen 0 - success , negative --fail
 */
int hns_ppe_init(struct dsaf_device *dsaf_dev)
{
	int ret;
	int i;

	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
		ret = hns_ppe_common_get_cfg(dsaf_dev, i);
		if (ret)
			goto get_cfg_fail;

		ret = hns_rcb_common_get_cfg(dsaf_dev, i);
		if (ret)
			goto get_cfg_fail;

		hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);

		ret = hns_rcb_get_cfg(dsaf_dev->rcb_common[i]);
		if (ret)
			goto get_cfg_fail;
	}

	for (i = 0; i < HNS_PPE_COM_NUM; i++)
		hns_ppe_reset_common(dsaf_dev, i);

	return 0;

get_cfg_fail:
	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
		hns_rcb_common_free_cfg(dsaf_dev, i);
		hns_ppe_common_free_cfg(dsaf_dev, i);
	}

	return ret;
}

void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data)
{
	struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
	u32 *regs = data;
	u32 i;
	u32 offset;

	/* ppe common registers */
	regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
	regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
	regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
	regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
	regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);

	for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) {
		offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i;
		regs[5 + i] = dsaf_read_dev(ppe_common, offset);
		offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i;
		regs[5 + i + DSAF_TOTAL_QUEUE_NUM]
				= dsaf_read_dev(ppe_common, offset);
		offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i;
		regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2]
				= dsaf_read_dev(ppe_common, offset);
		offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i;
		regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3]
				= dsaf_read_dev(ppe_common, offset);
	}

	/* mark end of ppe regs */
	for (i = 521; i < 524; i++)
		regs[i] = 0xeeeeeeee;

	/* ppe channel registers */
	regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG);
	regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG);
	regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG);
	regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG);
	regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG);
	regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG);
	regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG);
	regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG);

	regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG);
	regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG);
	regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG);
	regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG);
	regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG);
	regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG);
	regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG);

	regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG);
	regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG);
	regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG);
	regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG);

	regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG);
	regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG);

	/* ppe static */
	regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
	regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
	regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
	regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
	regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
	regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
	regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
	regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
	regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
	regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
	regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
	regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);

	regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG);
	regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG);
	regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG);
	regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG);
	regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG);
	regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG);
	regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG);
	regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG);
	regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG);
	regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG);
	regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG);
	regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG);
	regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG);
	regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG);

	/* mark end of ppe regs */
	for (i = 572; i < 576; i++)
		regs[i] = 0xeeeeeeee;
}
Commit	Line	Data
511e6bc0	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/netdevice.h>
	14	#include <linux/etherdevice.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_platform.h>
	19
	20	#include "hns_dsaf_ppe.h"
	21
64353af6 S	22	void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value)
	23	{
	24	dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
	25	}
	26
6bc0ce7d S	27	void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
	28	const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
	29	{
beecfe9e	30	u32 key_item;
6bc0ce7d S	31
	32	for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
	33	dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
	34	rss_key[key_item]);
	35	}
	36
	37	void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
	38	const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
	39	{
	40	int i;
	41	int reg_value;
	42
	43	for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
	44	reg_value = dsaf_read_dev(ppe_cb,
	45	PPEV2_INDRECTION_TBL_REG + i * 0x4);
	46
	47	dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
	48	PPEV2_CFG_RSS_TBL_4N0_S,
	49	rss_tab[i * 4 + 0] & 0x1F);
	50	dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
	51	PPEV2_CFG_RSS_TBL_4N1_S,
	52	rss_tab[i * 4 + 1] & 0x1F);
	53	dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
	54	PPEV2_CFG_RSS_TBL_4N2_S,
	55	rss_tab[i * 4 + 2] & 0x1F);
	56	dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
	57	PPEV2_CFG_RSS_TBL_4N3_S,
	58	rss_tab[i * 4 + 3] & 0x1F);
	59	dsaf_write_dev(
	60	ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
	61	}
	62	}
	63
831d828b YZZ	64	static void __iomem *
831d828b YZZ	65	hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common)
511e6bc0	66	{
831d828b	67	return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET;
511e6bc0	68	}
	69
	70	/**
	71	* hns_ppe_common_get_cfg - get ppe common config
	72	* @dsaf_dev: dasf device
	73	* comm_index: common index
	74	* retuen 0 - success , negative --fail
	75	*/
336a443b	76	static int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index)
511e6bc0	77	{
	78	struct ppe_common_cb *ppe_common;
	79	int ppe_num;
	80
89a44093	81	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
511e6bc0	82	ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM;
	83	else
	84	ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM;
	85
	86	ppe_common = devm_kzalloc(dsaf_dev->dev, sizeof(*ppe_common) +
	87	ppe_num * sizeof(struct hns_ppe_cb), GFP_KERNEL);
	88	if (!ppe_common)
	89	return -ENOMEM;
	90
	91	ppe_common->ppe_num = ppe_num;
	92	ppe_common->dsaf_dev = dsaf_dev;
	93	ppe_common->comm_index = comm_index;
89a44093	94	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
511e6bc0	95	ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
	96	else
	97	ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
	98	ppe_common->dev = dsaf_dev->dev;
	99
	100	ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);
	101
	102	dsaf_dev->ppe_common[comm_index] = ppe_common;
	103
	104	return 0;
	105	}
	106
336a443b Y	107	static void
336a443b Y	108	hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index)
511e6bc0	109	{
	110	dsaf_dev->ppe_common[comm_index] = NULL;
	111	}
	112
	113	static void __iomem hns_ppe_get_iobase(struct ppe_common_cb ppe_common,
	114	int ppe_idx)
	115	{
831d828b	116	return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET;
511e6bc0	117	}
	118
	119	static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
	120	{
	121	u32 i;
	122	struct hns_ppe_cb *ppe_cb;
	123	u32 ppe_num = ppe_common->ppe_num;
	124
	125	for (i = 0; i < ppe_num; i++) {
	126	ppe_cb = &ppe_common->ppe_cb[i];
	127	ppe_cb->dev = ppe_common->dev;
	128	ppe_cb->next = NULL;
	129	ppe_cb->ppe_common_cb = ppe_common;
	130	ppe_cb->index = i;
511e6bc0	131	ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
	132	ppe_cb->virq = 0;
	133	}
	134	}
	135
	136	static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
	137	{
	138	dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
	139	PPE_CNT_CLR_CE_B, 1);
	140	}
	141
8044f97e S	142	static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
	143	{
	144	dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
	145	}
	146
511e6bc0	147	/**
	148	* hns_ppe_checksum_hw - set ppe checksum caculate
	149	* @ppe_device: ppe device
	150	* @value: value
	151	*/
	152	static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value)
	153	{
	154	dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
	155	0xfffffff, 0, value);
	156	}
	157
	158	static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
	159	enum ppe_qid_mode qid_mdoe)
	160	{
	161	dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
	162	PPE_CFG_QID_MODE_CF_QID_MODE_M,
	163	PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe);
	164	}
	165
	166	/**
	167	* hns_ppe_set_qid - set ppe qid
	168	* @ppe_common: ppe common device
	169	* @qid: queue id
	170	*/
	171	static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
	172	{
	173	u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
	174
	175	if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
	176	PPE_CFG_QID_MODE_DEF_QID_S)) {
	177	dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
	178	PPE_CFG_QID_MODE_DEF_QID_S, qid);
	179	dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
	180	}
	181	}
	182
	183	/**
	184	* hns_ppe_set_port_mode - set port mode
	185	* @ppe_device: ppe device
	186	* @mode: port mode
	187	*/
	188	static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
	189	enum ppe_port_mode mode)
	190	{
	191	dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
	192	}
	193
	194	/**
	195	* hns_ppe_common_init_hw - init ppe common device
	196	* @ppe_common: ppe common device
	197	*
	198	* Return 0 on success, negative on failure
	199	*/
	200	static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
	201	{
	202	enum ppe_qid_mode qid_mode;
a24274aa KY	203	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
a24274aa KY	204	enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;
511e6bc0	205
a24274aa	206	dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 0);
511e6bc0	207	mdelay(100);
a24274aa	208	dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 1);
511e6bc0	209	mdelay(100);
	210
	211	if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
	212	switch (dsaf_mode) {
	213	case DSAF_MODE_ENABLE_FIX:
	214	case DSAF_MODE_DISABLE_FIX:
	215	qid_mode = PPE_QID_MODE0;
	216	hns_ppe_set_qid(ppe_common, 0);
	217	break;
	218	case DSAF_MODE_ENABLE_0VM:
	219	case DSAF_MODE_DISABLE_2PORT_64VM:
	220	qid_mode = PPE_QID_MODE3;
	221	break;
	222	case DSAF_MODE_ENABLE_8VM:
	223	case DSAF_MODE_DISABLE_2PORT_16VM:
	224	qid_mode = PPE_QID_MODE4;
	225	break;
	226	case DSAF_MODE_ENABLE_16VM:
	227	case DSAF_MODE_DISABLE_6PORT_0VM:
	228	qid_mode = PPE_QID_MODE5;
	229	break;
	230	case DSAF_MODE_ENABLE_32VM:
	231	case DSAF_MODE_DISABLE_6PORT_16VM:
	232	qid_mode = PPE_QID_MODE2;
	233	break;
	234	case DSAF_MODE_ENABLE_128VM:
	235	case DSAF_MODE_DISABLE_6PORT_4VM:
	236	qid_mode = PPE_QID_MODE1;
	237	break;
	238	case DSAF_MODE_DISABLE_2PORT_8VM:
	239	qid_mode = PPE_QID_MODE7;
	240	break;
	241	case DSAF_MODE_DISABLE_6PORT_2VM:
	242	qid_mode = PPE_QID_MODE6;
	243	break;
	244	default:
	245	dev_err(ppe_common->dev,
	246	"get ppe queue mode failed! dsaf_mode=%d\n",
	247	dsaf_mode);
	248	return -EINVAL;
	249	}
	250	hns_ppe_set_qid_mode(ppe_common, qid_mode);
	251	}
	252
	253	dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
	254	PPE_COMMON_CNT_CLR_CE_B, 1);
	255
	256	return 0;
	257	}
	258
	259	/clr ppe exception irq/
	260	static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
	261	{
	262	u32 clr_vlue = 0xfffffffful;
	263	u32 msk_vlue = en ? 0xfffffffful : 0; /1 is en, 0 is dis/
	264	u32 vld_msk = 0;
	265
	266	/only care bit 0,1,7/
	267	dsaf_set_bit(vld_msk, 0, 1);
	268	dsaf_set_bit(vld_msk, 1, 1);
	269	dsaf_set_bit(vld_msk, 7, 1);
	270
	271	/clr sts*/
	272	dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
273
274	/for some reserved bits, so set 0*/
275	dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
276	}
277
278	/**
279	* ppe_init_hw - init ppe
6bc0ce7d	280	* @ppe_cb: ppe device
511e6bc0	281	*/
	282	static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
	283	{
	284	struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
831d828b	285	u32 port = ppe_cb->index;
511e6bc0	286	struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
6bc0ce7d S	287	int i;
	288
	289	/* get default RSS key */
	290	netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);
511e6bc0	291
a24274aa	292	dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
511e6bc0	293	mdelay(10);
a24274aa	294	dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 1);
511e6bc0	295
	296	/* clr and msk except irq*/
	297	hns_ppe_exc_irq_en(ppe_cb, 0);
	298
5ada37b5	299	if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
511e6bc0	300	hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
5ada37b5 L	301	dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
5ada37b5 L	302	} else {
511e6bc0	303	hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
5ada37b5	304	}
6bc0ce7d	305
511e6bc0	306	hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
511e6bc0	307	hns_ppe_cnt_clr_ce(ppe_cb);
6bc0ce7d S	308
6bc0ce7d S	309	if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
8044f97e S	310	hns_ppe_set_vlan_strip(ppe_cb, 0);
8044f97e S	311
da3488bb KY	312	dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
	313	HNS_PPEV2_MAX_FRAME_LEN);
	314
6bc0ce7d S	315	/* set default RSS key in h/w */
	316	hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);
	317
	318	/* Set default indrection table in h/w */
	319	for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
	320	ppe_cb->rss_indir_table[i] = i;
	321	hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
	322	}
511e6bc0	323	}
	324
	325	/**
	326	* ppe_uninit_hw - uninit ppe
	327	* @ppe_device: ppe device
	328	*/
	329	static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb)
	330	{
	331	u32 port;
	332
	333	if (ppe_cb->ppe_common_cb) {
c234af58 CIK	334	struct dsaf_device *dsaf_dev = ppe_cb->ppe_common_cb->dsaf_dev;
c234af58 CIK	335
511e6bc0	336	port = ppe_cb->index;
a24274aa	337	dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
511e6bc0	338	}
	339	}
	340
336a443b	341	static void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
511e6bc0	342	{
	343	u32 i;
	344
	345	for (i = 0; i < ppe_common->ppe_num; i++) {
831d828b YZZ	346	if (ppe_common->dsaf_dev->mac_cb[i])
831d828b YZZ	347	hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
511e6bc0	348	memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
	349	}
	350	}
	351
	352	void hns_ppe_uninit(struct dsaf_device *dsaf_dev)
	353	{
	354	u32 i;
	355
	356	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
	357	if (dsaf_dev->ppe_common[i])
	358	hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
	359	hns_rcb_common_free_cfg(dsaf_dev, i);
	360	hns_ppe_common_free_cfg(dsaf_dev, i);
	361	}
	362	}
	363
	364	/**
	365	* hns_ppe_reset - reinit ppe/rcb hw
	366	* @dsaf_dev: dasf device
	367	* retuen void
	368	*/
	369	void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index)
	370	{
	371	u32 i;
	372	int ret;
	373	struct ppe_common_cb *ppe_common;
	374
	375	ppe_common = dsaf_dev->ppe_common[ppe_common_index];
	376	ret = hns_ppe_common_init_hw(ppe_common);
	377	if (ret)
	378	return;
	379
831d828b YZZ	380	for (i = 0; i < ppe_common->ppe_num; i++) {
	381	/* We only need to initiate ppe when the port exists */
	382	if (dsaf_dev->mac_cb[i])
	383	hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
	384	}
13ac695e	385
511e6bc0	386	ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]);
	387	if (ret)
	388	return;
	389
511e6bc0	390	hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]);
	391	}
	392
	393	void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
	394	{
	395	struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
	396
	397	hw_stats->rx_pkts_from_sw
	398	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
	399	hw_stats->rx_pkts
	400	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
	401	hw_stats->rx_drop_no_bd
	402	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
	403	hw_stats->rx_alloc_buf_fail
	404	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
	405	hw_stats->rx_alloc_buf_wait
	406	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
	407	hw_stats->rx_drop_no_buf
	408	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
	409	hw_stats->rx_err_fifo_full
	410	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
	411
	412	hw_stats->tx_bd_form_rcb
	413	+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
	414	hw_stats->tx_pkts_from_rcb
	415	+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
	416	hw_stats->tx_pkts
	417	+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
	418	hw_stats->tx_err_fifo_empty
	419	+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
	420	hw_stats->tx_err_checksum
	421	+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
	422	}
	423
	424	int hns_ppe_get_sset_count(int stringset)
	425	{
d61d263c	426	if (stringset == ETH_SS_STATS)
511e6bc0	427	return ETH_PPE_STATIC_NUM;
	428	return 0;
	429	}
	430
	431	int hns_ppe_get_regs_count(void)
	432	{
	433	return ETH_PPE_DUMP_NUM;
	434	}
	435
	436	/**
	437	* ppe_get_strings - get ppe srting
	438	* @ppe_device: ppe device
	439	* @stringset: string set type
	440	* @data: output string
	441	*/
	442	void hns_ppe_get_strings(struct hns_ppe_cb ppe_cb, int stringset, u8 data)
	443	{
	444	char buff = (char )data;
	445	int index = ppe_cb->index;
	446
	447	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index);
	448	buff = buff + ETH_GSTRING_LEN;
	449	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index);
	450	buff = buff + ETH_GSTRING_LEN;
	451	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index);
	452	buff = buff + ETH_GSTRING_LEN;
	453	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index);
	454	buff = buff + ETH_GSTRING_LEN;
	455	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index);
	456	buff = buff + ETH_GSTRING_LEN;
	457	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index);
	458	buff = buff + ETH_GSTRING_LEN;
	459	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index);
	460	buff = buff + ETH_GSTRING_LEN;
	461
	462	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index);
	463	buff = buff + ETH_GSTRING_LEN;
	464	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index);
	465	buff = buff + ETH_GSTRING_LEN;
	466	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index);
	467	buff = buff + ETH_GSTRING_LEN;
	468	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index);
	469	buff = buff + ETH_GSTRING_LEN;
	470	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index);
	471	}
	472
	473	void hns_ppe_get_stats(struct hns_ppe_cb ppe_cb, u64 data)
	474	{
	475	u64 *regs_buff = data;
	476	struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
	477
	478	regs_buff[0] = hw_stats->rx_pkts_from_sw;
	479	regs_buff[1] = hw_stats->rx_pkts;
	480	regs_buff[2] = hw_stats->rx_drop_no_bd;
	481	regs_buff[3] = hw_stats->rx_alloc_buf_fail;
	482	regs_buff[4] = hw_stats->rx_alloc_buf_wait;
	483	regs_buff[5] = hw_stats->rx_drop_no_buf;
	484	regs_buff[6] = hw_stats->rx_err_fifo_full;
	485
	486	regs_buff[7] = hw_stats->tx_bd_form_rcb;
	487	regs_buff[8] = hw_stats->tx_pkts_from_rcb;
	488	regs_buff[9] = hw_stats->tx_pkts;
	489	regs_buff[10] = hw_stats->tx_err_fifo_empty;
	490	regs_buff[11] = hw_stats->tx_err_checksum;
491	}
492
493	/**
494	* hns_ppe_init - init ppe device
495	* @dsaf_dev: dasf device
496	* retuen 0 - success , negative --fail
497	*/
498	int hns_ppe_init(struct dsaf_device *dsaf_dev)
499	{
511e6bc0	500	int ret;
a2185587	501	int i;
511e6bc0	502
	503	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
	504	ret = hns_ppe_common_get_cfg(dsaf_dev, i);
	505	if (ret)
a2185587	506	goto get_cfg_fail;
511e6bc0	507
	508	ret = hns_rcb_common_get_cfg(dsaf_dev, i);
	509	if (ret)
a2185587	510	goto get_cfg_fail;
511e6bc0	511
	512	hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);
	513
2fdd6baf	514	ret = hns_rcb_get_cfg(dsaf_dev->rcb_common[i]);
	515	if (ret)
	516	goto get_cfg_fail;
511e6bc0	517	}
	518
	519	for (i = 0; i < HNS_PPE_COM_NUM; i++)
	520	hns_ppe_reset_common(dsaf_dev, i);
	521
	522	return 0;
	523
a2185587 KY	524	get_cfg_fail:
	525	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
	526	hns_rcb_common_free_cfg(dsaf_dev, i);
	527	hns_ppe_common_free_cfg(dsaf_dev, i);
511e6bc0	528	}
a2185587	529
511e6bc0	530	return ret;
	531	}
	532
	533	void hns_ppe_get_regs(struct hns_ppe_cb ppe_cb, void data)
	534	{
	535	struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
	536	u32 *regs = data;
	537	u32 i;
	538	u32 offset;
	539
	540	/* ppe common registers */
	541	regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
	542	regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
	543	regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
	544	regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
	545	regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);
	546
	547	for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) {
	548	offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i;
	549	regs[5 + i] = dsaf_read_dev(ppe_common, offset);
	550	offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i;
	551	regs[5 + i + DSAF_TOTAL_QUEUE_NUM]
	552	= dsaf_read_dev(ppe_common, offset);
	553	offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i;
	554	regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2]
	555	= dsaf_read_dev(ppe_common, offset);
	556	offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i;
	557	regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3]
	558	= dsaf_read_dev(ppe_common, offset);
	559	}
	560
	561	/* mark end of ppe regs */
	562	for (i = 521; i < 524; i++)
	563	regs[i] = 0xeeeeeeee;
	564
	565	/* ppe channel registers */
	566	regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG);
	567	regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG);
	568	regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG);
	569	regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG);
	570	regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG);
	571	regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG);
	572	regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG);
	573	regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG);
	574
	575	regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG);
	576	regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG);
	577	regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG);
	578	regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG);
	579	regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG);
	580	regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG);
	581	regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG);
	582
	583	regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG);
	584	regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG);
	585	regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG);
	586	regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG);
	587
	588	regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG);
	589	regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG);
	590
	591	/* ppe static */
	592	regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
	593	regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
594	regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
595	regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
596	regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
597	regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
598	regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
599	regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
600	regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
601	regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
602	regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
603	regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
604
605	regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG);
606	regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG);
607	regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG);
608	regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG);
609	regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG);
610	regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG);
611	regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG);
612	regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG);
613	regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG);
614	regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG);
615	regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG);
616	regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG);
617	regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG);
618	regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG);
619
620	/* mark end of ppe regs */
621	for (i = 572; i < 576; i++)
622	regs[i] = 0xeeeeeeee;
623	}