[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_ppe.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>

#include "hns_dsaf_ppe.h"

void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value)
{
	dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
}

void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
			 const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
{
	u32 key_item;

	for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
		dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
			       rss_key[key_item]);
}

void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
			     const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
{
	int i;
	int reg_value;

	for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
		reg_value = dsaf_read_dev(ppe_cb,
					  PPEV2_INDRECTION_TBL_REG + i * 0x4);

		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
			       PPEV2_CFG_RSS_TBL_4N0_S,
			       rss_tab[i * 4 + 0] & 0x1F);
		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
			       PPEV2_CFG_RSS_TBL_4N1_S,
				rss_tab[i * 4 + 1] & 0x1F);
		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
			       PPEV2_CFG_RSS_TBL_4N2_S,
				rss_tab[i * 4 + 2] & 0x1F);
		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
			       PPEV2_CFG_RSS_TBL_4N3_S,
				rss_tab[i * 4 + 3] & 0x1F);
		dsaf_write_dev(
			ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
	}
}

static void __iomem *
hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common)
{
	return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET;
}

/**
 * hns_ppe_common_get_cfg - get ppe common config
 * @dsaf_dev: dasf device
 * comm_index: common index
 * retuen 0 - success , negative --fail
 */
int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index)
{
	struct ppe_common_cb *ppe_common;
	int ppe_num;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM;
	else
		ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM;

	ppe_common = devm_kzalloc(dsaf_dev->dev, sizeof(*ppe_common) +
		ppe_num * sizeof(struct hns_ppe_cb), GFP_KERNEL);
	if (!ppe_common)
		return -ENOMEM;

	ppe_common->ppe_num = ppe_num;
	ppe_common->dsaf_dev = dsaf_dev;
	ppe_common->comm_index = comm_index;
	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
	else
		ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
	ppe_common->dev = dsaf_dev->dev;

	ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);

	dsaf_dev->ppe_common[comm_index] = ppe_common;

	return 0;
}

void hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index)
{
	dsaf_dev->ppe_common[comm_index] = NULL;
}

static void __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common,
					int ppe_idx)
{

	return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET;
}

static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
{
	u32 i;
	struct hns_ppe_cb *ppe_cb;
	u32 ppe_num = ppe_common->ppe_num;

	for (i = 0; i < ppe_num; i++) {
		ppe_cb = &ppe_common->ppe_cb[i];
		ppe_cb->dev = ppe_common->dev;
		ppe_cb->next = NULL;
		ppe_cb->ppe_common_cb = ppe_common;
		ppe_cb->index = i;
		ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
		ppe_cb->virq = 0;
	}
}

static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
{
	dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
			 PPE_CNT_CLR_CE_B, 1);
}

static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
{
	dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
}

/**
 * hns_ppe_checksum_hw - set ppe checksum caculate
 * @ppe_device: ppe device
 * @value: value
 */
static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value)
{
	dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
			   0xfffffff, 0, value);
}

static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
				 enum ppe_qid_mode qid_mdoe)
{
	dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
			   PPE_CFG_QID_MODE_CF_QID_MODE_M,
			   PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe);
}

/**
 * hns_ppe_set_qid - set ppe qid
 * @ppe_common: ppe common device
 * @qid: queue id
 */
static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
{
	u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);

	if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
			    PPE_CFG_QID_MODE_DEF_QID_S)) {
		dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
			       PPE_CFG_QID_MODE_DEF_QID_S, qid);
		dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
	}
}

/**
 * hns_ppe_set_port_mode - set port mode
 * @ppe_device: ppe device
 * @mode: port mode
 */
static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
				  enum ppe_port_mode mode)
{
	dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
}

/**
 * hns_ppe_common_init_hw - init ppe common device
 * @ppe_common: ppe common device
 *
 * Return 0 on success, negative on failure
 */
static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
{
	enum ppe_qid_mode qid_mode;
	enum dsaf_mode dsaf_mode = ppe_common->dsaf_dev->dsaf_mode;

	hns_ppe_com_srst(ppe_common, 0);
	mdelay(100);
	hns_ppe_com_srst(ppe_common, 1);
	mdelay(100);

	if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
		switch (dsaf_mode) {
		case DSAF_MODE_ENABLE_FIX:
		case DSAF_MODE_DISABLE_FIX:
			qid_mode = PPE_QID_MODE0;
			hns_ppe_set_qid(ppe_common, 0);
			break;
		case DSAF_MODE_ENABLE_0VM:
		case DSAF_MODE_DISABLE_2PORT_64VM:
			qid_mode = PPE_QID_MODE3;
			break;
		case DSAF_MODE_ENABLE_8VM:
		case DSAF_MODE_DISABLE_2PORT_16VM:
			qid_mode = PPE_QID_MODE4;
			break;
		case DSAF_MODE_ENABLE_16VM:
		case DSAF_MODE_DISABLE_6PORT_0VM:
			qid_mode = PPE_QID_MODE5;
			break;
		case DSAF_MODE_ENABLE_32VM:
		case DSAF_MODE_DISABLE_6PORT_16VM:
			qid_mode = PPE_QID_MODE2;
			break;
		case DSAF_MODE_ENABLE_128VM:
		case DSAF_MODE_DISABLE_6PORT_4VM:
			qid_mode = PPE_QID_MODE1;
			break;
		case DSAF_MODE_DISABLE_2PORT_8VM:
			qid_mode = PPE_QID_MODE7;
			break;
		case DSAF_MODE_DISABLE_6PORT_2VM:
			qid_mode = PPE_QID_MODE6;
			break;
		default:
			dev_err(ppe_common->dev,
				"get ppe queue mode failed! dsaf_mode=%d\n",
				dsaf_mode);
			return -EINVAL;
		}
		hns_ppe_set_qid_mode(ppe_common, qid_mode);
	}

	dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
			 PPE_COMMON_CNT_CLR_CE_B, 1);

	return 0;
}

/*clr ppe exception irq*/
static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
{
	u32 clr_vlue = 0xfffffffful;
	u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
	u32 vld_msk = 0;

	/*only care bit 0,1,7*/
	dsaf_set_bit(vld_msk, 0, 1);
	dsaf_set_bit(vld_msk, 1, 1);
	dsaf_set_bit(vld_msk, 7, 1);

	/*clr sts**/
	dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);

	/*for some reserved bits, so set 0**/
	dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
}

/**
 * ppe_init_hw - init ppe
 * @ppe_cb: ppe device
 */
static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
{
	struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
	u32 port = ppe_cb->index;
	struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
	int i;

	/* get default RSS key */
	netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);

	hns_ppe_srst_by_port(dsaf_dev, port, 0);
	mdelay(10);
	hns_ppe_srst_by_port(dsaf_dev, port, 1);

	/* clr and msk except irq*/
	hns_ppe_exc_irq_en(ppe_cb, 0);

	if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
		hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
		dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
	} else {
		hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
	}

	hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
	hns_ppe_cnt_clr_ce(ppe_cb);

	if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
		hns_ppe_set_vlan_strip(ppe_cb, 0);

		dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
			       HNS_PPEV2_MAX_FRAME_LEN);

		/* set default RSS key in h/w */
		hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);

		/* Set default indrection table in h/w */
		for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
			ppe_cb->rss_indir_table[i] = i;
		hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
	}
}

/**
 * ppe_uninit_hw - uninit ppe
 * @ppe_device: ppe device
 */
static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb)
{
	u32 port;

	if (ppe_cb->ppe_common_cb) {
		port = ppe_cb->index;
		hns_ppe_srst_by_port(ppe_cb->ppe_common_cb->dsaf_dev, port, 0);
	}
}

void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
{
	u32 i;

	for (i = 0; i < ppe_common->ppe_num; i++) {
		if (ppe_common->dsaf_dev->mac_cb[i])
			hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
		memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
	}
}

void hns_ppe_uninit(struct dsaf_device *dsaf_dev)
{
	u32 i;

	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
		if (dsaf_dev->ppe_common[i])
			hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
		hns_rcb_common_free_cfg(dsaf_dev, i);
		hns_ppe_common_free_cfg(dsaf_dev, i);
	}
}

/**
 * hns_ppe_reset - reinit ppe/rcb hw
 * @dsaf_dev: dasf device
 * retuen void
 */
void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index)
{
	u32 i;
	int ret;
	struct ppe_common_cb *ppe_common;

	ppe_common = dsaf_dev->ppe_common[ppe_common_index];
	ret = hns_ppe_common_init_hw(ppe_common);
	if (ret)
		return;

	for (i = 0; i < ppe_common->ppe_num; i++) {
		/* We only need to initiate ppe when the port exists */
		if (dsaf_dev->mac_cb[i])
			hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
	}

	ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]);
	if (ret)
		return;

	hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]);
}

void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
{
	struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;

	hw_stats->rx_pkts_from_sw
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
	hw_stats->rx_pkts
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
	hw_stats->rx_drop_no_bd
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
	hw_stats->rx_alloc_buf_fail
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
	hw_stats->rx_alloc_buf_wait
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
	hw_stats->rx_drop_no_buf
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
	hw_stats->rx_err_fifo_full
		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);

	hw_stats->tx_bd_form_rcb
		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
	hw_stats->tx_pkts_from_rcb
		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
	hw_stats->tx_pkts
		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
	hw_stats->tx_err_fifo_empty
		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
	hw_stats->tx_err_checksum
		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
}

int hns_ppe_get_sset_count(int stringset)
{
	if (stringset == ETH_SS_STATS)
		return ETH_PPE_STATIC_NUM;
	return 0;
}

int hns_ppe_get_regs_count(void)
{
	return ETH_PPE_DUMP_NUM;
}

/**
 * ppe_get_strings - get ppe srting
 * @ppe_device: ppe device
 * @stringset: string set type
 * @data: output string
 */
void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data)
{
	char *buff = (char *)data;
	int index = ppe_cb->index;

	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index);
	buff = buff + ETH_GSTRING_LEN;

	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index);
	buff = buff + ETH_GSTRING_LEN;
	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index);
}

void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data)
{
	u64 *regs_buff = data;
	struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;

	regs_buff[0] = hw_stats->rx_pkts_from_sw;
	regs_buff[1] = hw_stats->rx_pkts;
	regs_buff[2] = hw_stats->rx_drop_no_bd;
	regs_buff[3] = hw_stats->rx_alloc_buf_fail;
	regs_buff[4] = hw_stats->rx_alloc_buf_wait;
	regs_buff[5] = hw_stats->rx_drop_no_buf;
	regs_buff[6] = hw_stats->rx_err_fifo_full;

	regs_buff[7] = hw_stats->tx_bd_form_rcb;
	regs_buff[8] = hw_stats->tx_pkts_from_rcb;
	regs_buff[9] = hw_stats->tx_pkts;
	regs_buff[10] = hw_stats->tx_err_fifo_empty;
	regs_buff[11] = hw_stats->tx_err_checksum;
}

/**
 * hns_ppe_init - init ppe device
 * @dsaf_dev: dasf device
 * retuen 0 - success , negative --fail
 */
int hns_ppe_init(struct dsaf_device *dsaf_dev)
{
	int i, k;
	int ret;

	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
		ret = hns_ppe_common_get_cfg(dsaf_dev, i);
		if (ret)
			goto get_ppe_cfg_fail;

		ret = hns_rcb_common_get_cfg(dsaf_dev, i);
		if (ret)
			goto get_rcb_cfg_fail;

		hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);

		hns_rcb_get_cfg(dsaf_dev->rcb_common[i]);
	}

	for (i = 0; i < HNS_PPE_COM_NUM; i++)
		hns_ppe_reset_common(dsaf_dev, i);

	return 0;

get_rcb_cfg_fail:
	hns_ppe_common_free_cfg(dsaf_dev, i);
get_ppe_cfg_fail:
	for (k = i - 1; k >= 0; k--) {
		hns_rcb_common_free_cfg(dsaf_dev, k);
		hns_ppe_common_free_cfg(dsaf_dev, k);
	}
	return ret;
}

void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data)
{
	struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
	u32 *regs = data;
	u32 i;
	u32 offset;

	/* ppe common registers */
	regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
	regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
	regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
	regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
	regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);

	for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) {
		offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i;
		regs[5 + i] = dsaf_read_dev(ppe_common, offset);
		offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i;
		regs[5 + i + DSAF_TOTAL_QUEUE_NUM]
				= dsaf_read_dev(ppe_common, offset);
		offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i;
		regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2]
				= dsaf_read_dev(ppe_common, offset);
		offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i;
		regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3]
				= dsaf_read_dev(ppe_common, offset);
	}

	/* mark end of ppe regs */
	for (i = 521; i < 524; i++)
		regs[i] = 0xeeeeeeee;

	/* ppe channel registers */
	regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG);
	regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG);
	regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG);
	regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG);
	regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG);
	regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG);
	regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG);
	regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG);

	regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG);
	regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG);
	regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG);
	regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG);
	regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG);
	regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG);
	regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG);

	regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG);
	regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG);
	regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG);
	regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG);

	regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG);
	regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG);

	/* ppe static */
	regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
	regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
	regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
	regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
	regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
	regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
	regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
	regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
	regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
	regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
	regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
	regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);

	regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG);
	regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG);
	regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG);
	regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG);
	regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG);
	regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG);
	regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG);
	regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG);
	regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG);
	regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG);
	regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG);
	regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG);
	regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG);
	regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG);

	/* mark end of ppe regs */
	for (i = 572; i < 576; i++)
		regs[i] = 0xeeeeeeee;
}
Commit	Line	Data
511e6bc0	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/netdevice.h>
	14	#include <linux/etherdevice.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
	18	#include <linux/of_platform.h>
	19
	20	#include "hns_dsaf_ppe.h"
	21
64353af6 S	22	void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value)
	23	{
	24	dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
	25	}
	26
6bc0ce7d S	27	void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
	28	const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
	29	{
beecfe9e	30	u32 key_item;
6bc0ce7d S	31
	32	for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
	33	dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
	34	rss_key[key_item]);
	35	}
	36
	37	void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
	38	const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
	39	{
	40	int i;
	41	int reg_value;
	42
	43	for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
	44	reg_value = dsaf_read_dev(ppe_cb,
	45	PPEV2_INDRECTION_TBL_REG + i * 0x4);
	46
	47	dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
	48	PPEV2_CFG_RSS_TBL_4N0_S,
	49	rss_tab[i * 4 + 0] & 0x1F);
	50	dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
	51	PPEV2_CFG_RSS_TBL_4N1_S,
	52	rss_tab[i * 4 + 1] & 0x1F);
	53	dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
	54	PPEV2_CFG_RSS_TBL_4N2_S,
	55	rss_tab[i * 4 + 2] & 0x1F);
	56	dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
	57	PPEV2_CFG_RSS_TBL_4N3_S,
	58	rss_tab[i * 4 + 3] & 0x1F);
	59	dsaf_write_dev(
	60	ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
	61	}
	62	}
	63
831d828b YZZ	64	static void __iomem *
831d828b YZZ	65	hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common)
511e6bc0	66	{
831d828b	67	return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET;
511e6bc0	68	}
	69
	70	/**
	71	* hns_ppe_common_get_cfg - get ppe common config
	72	* @dsaf_dev: dasf device
	73	* comm_index: common index
	74	* retuen 0 - success , negative --fail
	75	*/
	76	int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index)
	77	{
	78	struct ppe_common_cb *ppe_common;
	79	int ppe_num;
	80
89a44093	81	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
511e6bc0	82	ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM;
	83	else
	84	ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM;
	85
	86	ppe_common = devm_kzalloc(dsaf_dev->dev, sizeof(*ppe_common) +
	87	ppe_num * sizeof(struct hns_ppe_cb), GFP_KERNEL);
	88	if (!ppe_common)
	89	return -ENOMEM;
	90
	91	ppe_common->ppe_num = ppe_num;
	92	ppe_common->dsaf_dev = dsaf_dev;
	93	ppe_common->comm_index = comm_index;
89a44093	94	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
511e6bc0	95	ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
	96	else
	97	ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
	98	ppe_common->dev = dsaf_dev->dev;
	99
	100	ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);
	101
	102	dsaf_dev->ppe_common[comm_index] = ppe_common;
	103
	104	return 0;
	105	}
	106
	107	void hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index)
	108	{
	109	dsaf_dev->ppe_common[comm_index] = NULL;
	110	}
	111
	112	static void __iomem hns_ppe_get_iobase(struct ppe_common_cb ppe_common,
	113	int ppe_idx)
	114	{
511e6bc0	115
831d828b	116	return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET;
511e6bc0	117	}
	118
	119	static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
	120	{
	121	u32 i;
	122	struct hns_ppe_cb *ppe_cb;
	123	u32 ppe_num = ppe_common->ppe_num;
	124
	125	for (i = 0; i < ppe_num; i++) {
	126	ppe_cb = &ppe_common->ppe_cb[i];
	127	ppe_cb->dev = ppe_common->dev;
	128	ppe_cb->next = NULL;
	129	ppe_cb->ppe_common_cb = ppe_common;
	130	ppe_cb->index = i;
511e6bc0	131	ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
	132	ppe_cb->virq = 0;
	133	}
	134	}
	135
	136	static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
	137	{
	138	dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
	139	PPE_CNT_CLR_CE_B, 1);
	140	}
	141
8044f97e S	142	static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
	143	{
	144	dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
	145	}
	146
511e6bc0	147	/**
	148	* hns_ppe_checksum_hw - set ppe checksum caculate
	149	* @ppe_device: ppe device
	150	* @value: value
	151	*/
	152	static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value)
	153	{
	154	dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
	155	0xfffffff, 0, value);
	156	}
	157
	158	static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
	159	enum ppe_qid_mode qid_mdoe)
	160	{
	161	dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
	162	PPE_CFG_QID_MODE_CF_QID_MODE_M,
	163	PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe);
	164	}
	165
	166	/**
	167	* hns_ppe_set_qid - set ppe qid
	168	* @ppe_common: ppe common device
	169	* @qid: queue id
	170	*/
	171	static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
	172	{
	173	u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
	174
	175	if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
	176	PPE_CFG_QID_MODE_DEF_QID_S)) {
	177	dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
	178	PPE_CFG_QID_MODE_DEF_QID_S, qid);
	179	dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
	180	}
	181	}
	182
	183	/**
	184	* hns_ppe_set_port_mode - set port mode
	185	* @ppe_device: ppe device
	186	* @mode: port mode
	187	*/
	188	static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
	189	enum ppe_port_mode mode)
	190	{
	191	dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
	192	}
	193
	194	/**
	195	* hns_ppe_common_init_hw - init ppe common device
	196	* @ppe_common: ppe common device
	197	*
	198	* Return 0 on success, negative on failure
	199	*/
	200	static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
	201	{
	202	enum ppe_qid_mode qid_mode;
	203	enum dsaf_mode dsaf_mode = ppe_common->dsaf_dev->dsaf_mode;
	204
	205	hns_ppe_com_srst(ppe_common, 0);
	206	mdelay(100);
	207	hns_ppe_com_srst(ppe_common, 1);
	208	mdelay(100);
	209
	210	if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
211	switch (dsaf_mode) {
212	case DSAF_MODE_ENABLE_FIX:
213	case DSAF_MODE_DISABLE_FIX:
214	qid_mode = PPE_QID_MODE0;
215	hns_ppe_set_qid(ppe_common, 0);
216	break;
217	case DSAF_MODE_ENABLE_0VM:
218	case DSAF_MODE_DISABLE_2PORT_64VM:
219	qid_mode = PPE_QID_MODE3;
220	break;
221	case DSAF_MODE_ENABLE_8VM:
222	case DSAF_MODE_DISABLE_2PORT_16VM:
223	qid_mode = PPE_QID_MODE4;
224	break;
225	case DSAF_MODE_ENABLE_16VM:
226	case DSAF_MODE_DISABLE_6PORT_0VM:
227	qid_mode = PPE_QID_MODE5;
228	break;
229	case DSAF_MODE_ENABLE_32VM:
230	case DSAF_MODE_DISABLE_6PORT_16VM:
231	qid_mode = PPE_QID_MODE2;
232	break;
233	case DSAF_MODE_ENABLE_128VM:
234	case DSAF_MODE_DISABLE_6PORT_4VM:
235	qid_mode = PPE_QID_MODE1;
236	break;
237	case DSAF_MODE_DISABLE_2PORT_8VM:
238	qid_mode = PPE_QID_MODE7;
239	break;
240	case DSAF_MODE_DISABLE_6PORT_2VM:
241	qid_mode = PPE_QID_MODE6;
242	break;
243	default:
244	dev_err(ppe_common->dev,
245	"get ppe queue mode failed! dsaf_mode=%d\n",
246	dsaf_mode);
247	return -EINVAL;
248	}
249	hns_ppe_set_qid_mode(ppe_common, qid_mode);
250	}
251
252	dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
253	PPE_COMMON_CNT_CLR_CE_B, 1);
254
255	return 0;
256	}
257
258	/clr ppe exception irq/
259	static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
260	{
261	u32 clr_vlue = 0xfffffffful;
262	u32 msk_vlue = en ? 0xfffffffful : 0; /1 is en, 0 is dis/
263	u32 vld_msk = 0;
264
265	/only care bit 0,1,7/
266	dsaf_set_bit(vld_msk, 0, 1);
267	dsaf_set_bit(vld_msk, 1, 1);
268	dsaf_set_bit(vld_msk, 7, 1);
269
270	/clr sts*/
271	dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
272
273	/for some reserved bits, so set 0*/
274	dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
275	}
276
277	/**
278	* ppe_init_hw - init ppe
6bc0ce7d	279	* @ppe_cb: ppe device
511e6bc0	280	*/
	281	static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
	282	{
	283	struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
831d828b	284	u32 port = ppe_cb->index;
511e6bc0	285	struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
6bc0ce7d S	286	int i;
	287
	288	/* get default RSS key */
	289	netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);
511e6bc0	290
	291	hns_ppe_srst_by_port(dsaf_dev, port, 0);
	292	mdelay(10);
	293	hns_ppe_srst_by_port(dsaf_dev, port, 1);
	294
	295	/* clr and msk except irq*/
	296	hns_ppe_exc_irq_en(ppe_cb, 0);
	297
5ada37b5	298	if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
511e6bc0	299	hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
5ada37b5 L	300	dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
5ada37b5 L	301	} else {
511e6bc0	302	hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
5ada37b5	303	}
6bc0ce7d	304
511e6bc0	305	hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
511e6bc0	306	hns_ppe_cnt_clr_ce(ppe_cb);
6bc0ce7d S	307
6bc0ce7d S	308	if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
8044f97e S	309	hns_ppe_set_vlan_strip(ppe_cb, 0);
8044f97e S	310
da3488bb KY	311	dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
	312	HNS_PPEV2_MAX_FRAME_LEN);
	313
6bc0ce7d S	314	/* set default RSS key in h/w */
	315	hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);
	316
	317	/* Set default indrection table in h/w */
	318	for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
	319	ppe_cb->rss_indir_table[i] = i;
	320	hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
	321	}
511e6bc0	322	}
	323
	324	/**
	325	* ppe_uninit_hw - uninit ppe
	326	* @ppe_device: ppe device
	327	*/
	328	static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb)
	329	{
	330	u32 port;
	331
	332	if (ppe_cb->ppe_common_cb) {
	333	port = ppe_cb->index;
	334	hns_ppe_srst_by_port(ppe_cb->ppe_common_cb->dsaf_dev, port, 0);
	335	}
	336	}
	337
	338	void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
	339	{
	340	u32 i;
	341
	342	for (i = 0; i < ppe_common->ppe_num; i++) {
831d828b YZZ	343	if (ppe_common->dsaf_dev->mac_cb[i])
831d828b YZZ	344	hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
511e6bc0	345	memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
	346	}
	347	}
	348
	349	void hns_ppe_uninit(struct dsaf_device *dsaf_dev)
	350	{
	351	u32 i;
	352
	353	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
	354	if (dsaf_dev->ppe_common[i])
	355	hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
	356	hns_rcb_common_free_cfg(dsaf_dev, i);
	357	hns_ppe_common_free_cfg(dsaf_dev, i);
	358	}
	359	}
	360
	361	/**
	362	* hns_ppe_reset - reinit ppe/rcb hw
	363	* @dsaf_dev: dasf device
	364	* retuen void
	365	*/
	366	void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index)
	367	{
	368	u32 i;
	369	int ret;
	370	struct ppe_common_cb *ppe_common;
	371
	372	ppe_common = dsaf_dev->ppe_common[ppe_common_index];
	373	ret = hns_ppe_common_init_hw(ppe_common);
	374	if (ret)
	375	return;
	376
831d828b YZZ	377	for (i = 0; i < ppe_common->ppe_num; i++) {
	378	/* We only need to initiate ppe when the port exists */
	379	if (dsaf_dev->mac_cb[i])
	380	hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
	381	}
13ac695e	382
511e6bc0	383	ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]);
	384	if (ret)
	385	return;
	386
511e6bc0	387	hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]);
	388	}
	389
	390	void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
	391	{
	392	struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
	393
	394	hw_stats->rx_pkts_from_sw
	395	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
	396	hw_stats->rx_pkts
	397	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
	398	hw_stats->rx_drop_no_bd
	399	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
	400	hw_stats->rx_alloc_buf_fail
	401	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
	402	hw_stats->rx_alloc_buf_wait
	403	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
	404	hw_stats->rx_drop_no_buf
	405	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
	406	hw_stats->rx_err_fifo_full
	407	+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
	408
	409	hw_stats->tx_bd_form_rcb
	410	+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
	411	hw_stats->tx_pkts_from_rcb
	412	+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
	413	hw_stats->tx_pkts
	414	+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
	415	hw_stats->tx_err_fifo_empty
	416	+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
	417	hw_stats->tx_err_checksum
	418	+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
	419	}
	420
	421	int hns_ppe_get_sset_count(int stringset)
	422	{
	423	if (stringset == ETH_SS_STATS)
	424	return ETH_PPE_STATIC_NUM;
	425	return 0;
	426	}
	427
	428	int hns_ppe_get_regs_count(void)
	429	{
	430	return ETH_PPE_DUMP_NUM;
	431	}
	432
	433	/**
	434	* ppe_get_strings - get ppe srting
	435	* @ppe_device: ppe device
	436	* @stringset: string set type
	437	* @data: output string
	438	*/
	439	void hns_ppe_get_strings(struct hns_ppe_cb ppe_cb, int stringset, u8 data)
	440	{
	441	char buff = (char )data;
	442	int index = ppe_cb->index;
	443
	444	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index);
	445	buff = buff + ETH_GSTRING_LEN;
	446	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index);
	447	buff = buff + ETH_GSTRING_LEN;
	448	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index);
	449	buff = buff + ETH_GSTRING_LEN;
	450	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index);
451	buff = buff + ETH_GSTRING_LEN;
452	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index);
453	buff = buff + ETH_GSTRING_LEN;
454	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index);
455	buff = buff + ETH_GSTRING_LEN;
456	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index);
457	buff = buff + ETH_GSTRING_LEN;
458
459	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index);
460	buff = buff + ETH_GSTRING_LEN;
461	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index);
462	buff = buff + ETH_GSTRING_LEN;
463	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index);
464	buff = buff + ETH_GSTRING_LEN;
465	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index);
466	buff = buff + ETH_GSTRING_LEN;
467	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index);
468	}
469
470	void hns_ppe_get_stats(struct hns_ppe_cb ppe_cb, u64 data)
471	{
472	u64 *regs_buff = data;
473	struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
474
475	regs_buff[0] = hw_stats->rx_pkts_from_sw;
476	regs_buff[1] = hw_stats->rx_pkts;
477	regs_buff[2] = hw_stats->rx_drop_no_bd;
478	regs_buff[3] = hw_stats->rx_alloc_buf_fail;
479	regs_buff[4] = hw_stats->rx_alloc_buf_wait;
480	regs_buff[5] = hw_stats->rx_drop_no_buf;
481	regs_buff[6] = hw_stats->rx_err_fifo_full;
482
483	regs_buff[7] = hw_stats->tx_bd_form_rcb;
484	regs_buff[8] = hw_stats->tx_pkts_from_rcb;
485	regs_buff[9] = hw_stats->tx_pkts;
486	regs_buff[10] = hw_stats->tx_err_fifo_empty;
487	regs_buff[11] = hw_stats->tx_err_checksum;
488	}
489
490	/**
491	* hns_ppe_init - init ppe device
492	* @dsaf_dev: dasf device
493	* retuen 0 - success , negative --fail
494	*/
495	int hns_ppe_init(struct dsaf_device *dsaf_dev)
496	{
497	int i, k;
498	int ret;
499
500	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
501	ret = hns_ppe_common_get_cfg(dsaf_dev, i);
502	if (ret)
503	goto get_ppe_cfg_fail;
504
505	ret = hns_rcb_common_get_cfg(dsaf_dev, i);
506	if (ret)
507	goto get_rcb_cfg_fail;
508
509	hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);
510
511	hns_rcb_get_cfg(dsaf_dev->rcb_common[i]);
512	}
513
514	for (i = 0; i < HNS_PPE_COM_NUM; i++)
515	hns_ppe_reset_common(dsaf_dev, i);
516
517	return 0;
518
519	get_rcb_cfg_fail:
520	hns_ppe_common_free_cfg(dsaf_dev, i);
521	get_ppe_cfg_fail:
522	for (k = i - 1; k >= 0; k--) {
523	hns_rcb_common_free_cfg(dsaf_dev, k);
524	hns_ppe_common_free_cfg(dsaf_dev, k);
525	}
526	return ret;
527	}
528
529	void hns_ppe_get_regs(struct hns_ppe_cb ppe_cb, void data)
530	{
531	struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
532	u32 *regs = data;
533	u32 i;
534	u32 offset;
535
536	/* ppe common registers */
537	regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
538	regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
539	regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
540	regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
541	regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);
542
543	for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) {
544	offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i;
545	regs[5 + i] = dsaf_read_dev(ppe_common, offset);
546	offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i;
547	regs[5 + i + DSAF_TOTAL_QUEUE_NUM]
548	= dsaf_read_dev(ppe_common, offset);
549	offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i;
550	regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2]
551	= dsaf_read_dev(ppe_common, offset);
552	offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i;
553	regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3]
554	= dsaf_read_dev(ppe_common, offset);
555	}
556
557	/* mark end of ppe regs */
558	for (i = 521; i < 524; i++)
559	regs[i] = 0xeeeeeeee;
560
561	/* ppe channel registers */
562	regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG);
563	regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG);
564	regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG);
565	regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG);
566	regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG);
567	regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG);
568	regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG);
569	regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG);
570
571	regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG);
572	regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG);
573	regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG);
574	regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG);
575	regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG);
576	regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG);
577	regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG);
578
579	regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG);
580	regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG);
581	regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG);
582	regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG);
583
584	regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG);
585	regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG);
586
587	/* ppe static */
588	regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
589	regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
590	regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
591	regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
592	regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
593	regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
594	regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
595	regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
596	regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
597	regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
598	regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
599	regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
600
601	regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG);
602	regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG);
603	regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG);
604	regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG);
605	regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG);
606	regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG);
607	regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG);
608	regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG);
609	regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG);
610	regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG);
611	regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG);
612	regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG);
613	regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG);
614	regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG);
615
616	/* mark end of ppe regs */
617	for (i = 572; i < 576; i++)
618	regs[i] = 0xeeeeeeee;
619	}