]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - drivers/net/ethernet/hisilicon/hns3/hnae3.h
net: hns3: Add PCIe AER callback error_detected
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hnae3.h
CommitLineData
d71d8381
JS
1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
38caee9d
S
3
4#ifndef __HNAE3_H
5#define __HNAE3_H
6
7/* Names used in this framework:
8 * ae handle (handle):
9 * a set of queues provided by AE
10 * ring buffer queue (rbq):
11 * the channel between upper layer and the AE, can do tx and rx
12 * ring:
13 * a tx or rx channel within a rbq
14 * ring description (desc):
15 * an element in the ring with packet information
16 * buffer:
17 * a memory region referred by desc with the full packet payload
18 *
19 * "num" means a static number set as a parameter, "count" mean a dynamic
20 * number set while running
21 * "cb" means control block
22 */
23
24#include <linux/acpi.h>
cacde272 25#include <linux/dcbnl.h>
38caee9d
S
26#include <linux/delay.h>
27#include <linux/device.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
30#include <linux/pci.h>
31#include <linux/types.h>
32
3c7624d8
XW
33#define HNAE3_MOD_VERSION "1.0"
34
38caee9d
S
35/* Device IDs */
36#define HNAE3_DEV_ID_GE 0xA220
37#define HNAE3_DEV_ID_25GE 0xA221
38#define HNAE3_DEV_ID_25GE_RDMA 0xA222
39#define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223
40#define HNAE3_DEV_ID_50GE_RDMA 0xA224
41#define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225
42#define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226
43#define HNAE3_DEV_ID_100G_VF 0xA22E
44#define HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF 0xA22F
45
46#define HNAE3_CLASS_NAME_SIZE 16
47
48#define HNAE3_DEV_INITED_B 0x0
e92a0843 49#define HNAE3_DEV_SUPPORT_ROCE_B 0x1
2daf4a65 50#define HNAE3_DEV_SUPPORT_DCB_B 0x2
90b99b09
PL
51#define HNAE3_KNIC_CLIENT_INITED_B 0x3
52#define HNAE3_UNIC_CLIENT_INITED_B 0x4
53#define HNAE3_ROCE_CLIENT_INITED_B 0x5
d695964d 54#define HNAE3_DEV_SUPPORT_FD_B 0x6
2daf4a65
YL
55
56#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\
57 BIT(HNAE3_DEV_SUPPORT_ROCE_B))
e92a0843
YL
58
59#define hnae3_dev_roce_supported(hdev) \
e4e87715 60 hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
38caee9d 61
2daf4a65 62#define hnae3_dev_dcb_supported(hdev) \
e4e87715 63 hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
2daf4a65 64
d695964d
JS
65#define hnae3_dev_fd_supported(hdev) \
66 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B)
67
38caee9d
S
68#define ring_ptr_move_fw(ring, p) \
69 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num)
70#define ring_ptr_move_bw(ring, p) \
71 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)
72
73enum hns_desc_type {
74 DESC_TYPE_SKB,
75 DESC_TYPE_PAGE,
76};
77
78struct hnae3_handle;
79
80struct hnae3_queue {
81 void __iomem *io_base;
82 struct hnae3_ae_algo *ae_algo;
83 struct hnae3_handle *handle;
84 int tqp_index; /* index in a handle */
85 u32 buf_size; /* size for hnae_desc->addr, preset by AE */
86 u16 desc_num; /* total number of desc */
87};
88
89/*hnae3 loop mode*/
90enum hnae3_loop {
eb66d503 91 HNAE3_LOOP_APP,
4dc13b96
FL
92 HNAE3_LOOP_SERIAL_SERDES,
93 HNAE3_LOOP_PARALLEL_SERDES,
a7b687b3
FL
94 HNAE3_LOOP_PHY,
95 HNAE3_LOOP_NONE,
38caee9d
S
96};
97
98enum hnae3_client_type {
99 HNAE3_CLIENT_KNIC,
100 HNAE3_CLIENT_UNIC,
101 HNAE3_CLIENT_ROCE,
102};
103
104enum hnae3_dev_type {
105 HNAE3_DEV_KNIC,
106 HNAE3_DEV_UNIC,
107};
108
109/* mac media type */
110enum hnae3_media_type {
111 HNAE3_MEDIA_TYPE_UNKNOWN,
112 HNAE3_MEDIA_TYPE_FIBER,
113 HNAE3_MEDIA_TYPE_COPPER,
114 HNAE3_MEDIA_TYPE_BACKPLANE,
c136b884 115 HNAE3_MEDIA_TYPE_NONE,
38caee9d
S
116};
117
4ed340ab
L
118enum hnae3_reset_notify_type {
119 HNAE3_UP_CLIENT,
120 HNAE3_DOWN_CLIENT,
121 HNAE3_INIT_CLIENT,
122 HNAE3_UNINIT_CLIENT,
123};
124
125enum hnae3_reset_type {
6d4c3981 126 HNAE3_VF_RESET,
436667d2 127 HNAE3_VF_FULL_RESET,
4ed340ab
L
128 HNAE3_FUNC_RESET,
129 HNAE3_CORE_RESET,
130 HNAE3_GLOBAL_RESET,
131 HNAE3_IMP_RESET,
132 HNAE3_NONE_RESET,
133};
134
38caee9d
S
135struct hnae3_vector_info {
136 u8 __iomem *io_addr;
137 int vector;
138};
139
140#define HNAE3_RING_TYPE_B 0
141#define HNAE3_RING_TYPE_TX 0
142#define HNAE3_RING_TYPE_RX 1
11af96a4
FL
143#define HNAE3_RING_GL_IDX_S 0
144#define HNAE3_RING_GL_IDX_M GENMASK(1, 0)
145#define HNAE3_RING_GL_RX 0
146#define HNAE3_RING_GL_TX 1
38caee9d
S
147
148struct hnae3_ring_chain_node {
149 struct hnae3_ring_chain_node *next;
150 u32 tqp_index;
151 u32 flag;
11af96a4 152 u32 int_gl_idx;
38caee9d
S
153};
154
155#define HNAE3_IS_TX_RING(node) \
156 (((node)->flag & (1 << HNAE3_RING_TYPE_B)) == HNAE3_RING_TYPE_TX)
157
158struct hnae3_client_ops {
159 int (*init_instance)(struct hnae3_handle *handle);
160 void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
161 void (*link_status_change)(struct hnae3_handle *handle, bool state);
cacde272 162 int (*setup_tc)(struct hnae3_handle *handle, u8 tc);
4ed340ab
L
163 int (*reset_notify)(struct hnae3_handle *handle,
164 enum hnae3_reset_notify_type type);
38caee9d
S
165};
166
167#define HNAE3_CLIENT_NAME_LENGTH 16
168struct hnae3_client {
169 char name[HNAE3_CLIENT_NAME_LENGTH];
38caee9d
S
170 unsigned long state;
171 enum hnae3_client_type type;
172 const struct hnae3_client_ops *ops;
173 struct list_head node;
174};
175
176struct hnae3_ae_dev {
177 struct pci_dev *pdev;
178 const struct hnae3_ae_ops *ops;
179 struct list_head node;
180 u32 flag;
181 enum hnae3_dev_type dev_type;
6871af29 182 enum hnae3_reset_type reset_type;
38caee9d
S
183 void *priv;
184};
185
186/* This struct defines the operation on the handle.
187 *
188 * init_ae_dev(): (mandatory)
189 * Get PF configure from pci_dev and initialize PF hardware
190 * uninit_ae_dev()
191 * Disable PF device and release PF resource
192 * register_client
193 * Register client to ae_dev
194 * unregister_client()
195 * Unregister client from ae_dev
196 * start()
197 * Enable the hardware
198 * stop()
199 * Disable the hardware
200 * get_status()
201 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for
202 * non-ok
203 * get_ksettings_an_result()
204 * Get negotiation status,speed and duplex
205 * update_speed_duplex_h()
206 * Update hardware speed and duplex
207 * get_media_type()
208 * Get media type of MAC
209 * adjust_link()
210 * Adjust link status
211 * set_loopback()
212 * Set loopback
213 * set_promisc_mode
214 * Set promisc mode
215 * set_mtu()
216 * set mtu
217 * get_pauseparam()
218 * get tx and rx of pause frame use
219 * set_pauseparam()
220 * set tx and rx of pause frame use
221 * set_autoneg()
222 * set auto autonegotiation of pause frame use
223 * get_autoneg()
224 * get auto autonegotiation of pause frame use
225 * get_coalesce_usecs()
226 * get usecs to delay a TX interrupt after a packet is sent
227 * get_rx_max_coalesced_frames()
228 * get Maximum number of packets to be sent before a TX interrupt.
229 * set_coalesce_usecs()
230 * set usecs to delay a TX interrupt after a packet is sent
231 * set_coalesce_frames()
232 * set Maximum number of packets to be sent before a TX interrupt.
233 * get_mac_addr()
234 * get mac address
235 * set_mac_addr()
236 * set mac address
237 * add_uc_addr
238 * Add unicast addr to mac table
239 * rm_uc_addr
240 * Remove unicast addr from mac table
241 * set_mc_addr()
242 * Set multicast address
243 * add_mc_addr
244 * Add multicast address to mac table
245 * rm_mc_addr
246 * Remove multicast address from mac table
247 * update_stats()
248 * Update Old network device statistics
249 * get_ethtool_stats()
250 * Get ethtool network device statistics
251 * get_strings()
252 * Get a set of strings that describe the requested objects
253 * get_sset_count()
254 * Get number of strings that @get_strings will write
255 * update_led_status()
256 * Update the led status
257 * set_led_id()
258 * Set led id
259 * get_regs()
260 * Get regs dump
261 * get_regs_len()
262 * Get the len of the regs dump
263 * get_rss_key_size()
264 * Get rss key size
265 * get_rss_indir_size()
266 * Get rss indirection table size
267 * get_rss()
268 * Get rss table
269 * set_rss()
270 * Set rss table
271 * get_tc_size()
272 * Get tc size of handle
273 * get_vector()
274 * Get vector number and vector information
0d3e6631
YL
275 * put_vector()
276 * Put the vector in hdev
38caee9d
S
277 * map_ring_to_vector()
278 * Map rings to vector
279 * unmap_ring_from_vector()
280 * Unmap rings from vector
38caee9d
S
281 * reset_queue()
282 * Reset queue
283 * get_fw_version()
284 * Get firmware version
285 * get_mdix_mode()
286 * Get media typr of phy
391b5e93
JS
287 * enable_vlan_filter()
288 * Enable vlan filter
38caee9d
S
289 * set_vlan_filter()
290 * Set vlan filter config of Ports
291 * set_vf_vlan_filter()
292 * Set vlan filter config of vf
052ece6d
PL
293 * enable_hw_strip_rxvtag()
294 * Enable/disable hardware strip vlan tag of packets received
38caee9d
S
295 */
296struct hnae3_ae_ops {
297 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
298 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev);
299
300 int (*init_client_instance)(struct hnae3_client *client,
301 struct hnae3_ae_dev *ae_dev);
302 void (*uninit_client_instance)(struct hnae3_client *client,
303 struct hnae3_ae_dev *ae_dev);
304 int (*start)(struct hnae3_handle *handle);
305 void (*stop)(struct hnae3_handle *handle);
306 int (*get_status)(struct hnae3_handle *handle);
307 void (*get_ksettings_an_result)(struct hnae3_handle *handle,
308 u8 *auto_neg, u32 *speed, u8 *duplex);
309
310 int (*update_speed_duplex_h)(struct hnae3_handle *handle);
311 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
312 u8 duplex);
313
314 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type);
315 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex);
316 int (*set_loopback)(struct hnae3_handle *handle,
317 enum hnae3_loop loop_mode, bool en);
318
3b75c3df
PL
319 void (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc,
320 bool en_mc_pmc);
38caee9d
S
321 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu);
322
323 void (*get_pauseparam)(struct hnae3_handle *handle,
324 u32 *auto_neg, u32 *rx_en, u32 *tx_en);
325 int (*set_pauseparam)(struct hnae3_handle *handle,
326 u32 auto_neg, u32 rx_en, u32 tx_en);
327
328 int (*set_autoneg)(struct hnae3_handle *handle, bool enable);
329 int (*get_autoneg)(struct hnae3_handle *handle);
330
331 void (*get_coalesce_usecs)(struct hnae3_handle *handle,
332 u32 *tx_usecs, u32 *rx_usecs);
333 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle,
334 u32 *tx_frames, u32 *rx_frames);
335 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout);
336 int (*set_coalesce_frames)(struct hnae3_handle *handle,
337 u32 coalesce_frames);
338 void (*get_coalesce_range)(struct hnae3_handle *handle,
339 u32 *tx_frames_low, u32 *rx_frames_low,
340 u32 *tx_frames_high, u32 *rx_frames_high,
341 u32 *tx_usecs_low, u32 *rx_usecs_low,
342 u32 *tx_usecs_high, u32 *rx_usecs_high);
343
344 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p);
59098055
FL
345 int (*set_mac_addr)(struct hnae3_handle *handle, void *p,
346 bool is_first);
26483246
XW
347 int (*do_ioctl)(struct hnae3_handle *handle,
348 struct ifreq *ifr, int cmd);
38caee9d
S
349 int (*add_uc_addr)(struct hnae3_handle *handle,
350 const unsigned char *addr);
351 int (*rm_uc_addr)(struct hnae3_handle *handle,
352 const unsigned char *addr);
353 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr);
354 int (*add_mc_addr)(struct hnae3_handle *handle,
355 const unsigned char *addr);
356 int (*rm_mc_addr)(struct hnae3_handle *handle,
357 const unsigned char *addr);
38caee9d
S
358 void (*set_tso_stats)(struct hnae3_handle *handle, int enable);
359 void (*update_stats)(struct hnae3_handle *handle,
360 struct net_device_stats *net_stats);
361 void (*get_stats)(struct hnae3_handle *handle, u64 *data);
362
363 void (*get_strings)(struct hnae3_handle *handle,
364 u32 stringset, u8 *data);
365 int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
366
77b34110
FL
367 void (*get_regs)(struct hnae3_handle *handle, u32 *version,
368 void *data);
38caee9d
S
369 int (*get_regs_len)(struct hnae3_handle *handle);
370
371 u32 (*get_rss_key_size)(struct hnae3_handle *handle);
372 u32 (*get_rss_indir_size)(struct hnae3_handle *handle);
373 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key,
374 u8 *hfunc);
375 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir,
376 const u8 *key, const u8 hfunc);
f7db940a
L
377 int (*set_rss_tuple)(struct hnae3_handle *handle,
378 struct ethtool_rxnfc *cmd);
07d29954
L
379 int (*get_rss_tuple)(struct hnae3_handle *handle,
380 struct ethtool_rxnfc *cmd);
38caee9d
S
381
382 int (*get_tc_size)(struct hnae3_handle *handle);
383
384 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num,
385 struct hnae3_vector_info *vector_info);
0d3e6631 386 int (*put_vector)(struct hnae3_handle *handle, int vector_num);
38caee9d
S
387 int (*map_ring_to_vector)(struct hnae3_handle *handle,
388 int vector_num,
389 struct hnae3_ring_chain_node *vr_chain);
390 int (*unmap_ring_from_vector)(struct hnae3_handle *handle,
391 int vector_num,
392 struct hnae3_ring_chain_node *vr_chain);
393
38caee9d
S
394 void (*reset_queue)(struct hnae3_handle *handle, u16 queue_id);
395 u32 (*get_fw_version)(struct hnae3_handle *handle);
396 void (*get_mdix_mode)(struct hnae3_handle *handle,
397 u8 *tp_mdix_ctrl, u8 *tp_mdix);
398
391b5e93 399 void (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable);
38caee9d
S
400 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto,
401 u16 vlan_id, bool is_kill);
402 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,
403 u16 vlan, u8 qos, __be16 proto);
052ece6d 404 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);
6d4c3981 405 void (*reset_event)(struct hnae3_handle *handle);
482d2e9c
PL
406 void (*get_channels)(struct hnae3_handle *handle,
407 struct ethtool_channels *ch);
09f2af64 408 void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
0d43bf45 409 u16 *alloc_tqps, u16 *max_rss_size);
09f2af64 410 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num);
f34ffffd
PL
411 void (*get_flowctrl_adv)(struct hnae3_handle *handle,
412 u32 *flowctrl_adv);
07f8e940
JS
413 int (*set_led_id)(struct hnae3_handle *handle,
414 enum ethtool_phys_id_state status);
0979aa0b
FL
415 void (*get_link_mode)(struct hnae3_handle *handle,
416 unsigned long *supported,
417 unsigned long *advertising);
dd74f815
JS
418 int (*add_fd_entry)(struct hnae3_handle *handle,
419 struct ethtool_rxnfc *cmd);
420 int (*del_fd_entry)(struct hnae3_handle *handle,
421 struct ethtool_rxnfc *cmd);
6871af29
JS
422 void (*del_all_fd_entries)(struct hnae3_handle *handle,
423 bool clear_list);
05c2314f
JS
424 int (*get_fd_rule_cnt)(struct hnae3_handle *handle,
425 struct ethtool_rxnfc *cmd);
426 int (*get_fd_rule_info)(struct hnae3_handle *handle,
427 struct ethtool_rxnfc *cmd);
428 int (*get_fd_all_rules)(struct hnae3_handle *handle,
429 struct ethtool_rxnfc *cmd, u32 *rule_locs);
6871af29 430 int (*restore_fd_rules)(struct hnae3_handle *handle);
c17852a8 431 void (*enable_fd)(struct hnae3_handle *handle, bool enable);
5a9f0eac 432 pci_ers_result_t (*process_hw_error)(struct hnae3_ae_dev *ae_dev);
38caee9d
S
433};
434
cacde272
YL
435struct hnae3_dcb_ops {
436 /* IEEE 802.1Qaz std */
437 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *);
438 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);
439 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);
440 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);
441
442 /* DCBX configuration */
443 u8 (*getdcbx)(struct hnae3_handle *);
444 u8 (*setdcbx)(struct hnae3_handle *, u8);
445
446 int (*map_update)(struct hnae3_handle *);
30d240df 447 int (*setup_tc)(struct hnae3_handle *, u8, u8 *);
cacde272
YL
448};
449
38caee9d
S
450struct hnae3_ae_algo {
451 const struct hnae3_ae_ops *ops;
452 struct list_head node;
38caee9d
S
453 const struct pci_device_id *pdev_id_table;
454};
455
456#define HNAE3_INT_NAME_LEN (IFNAMSIZ + 16)
457#define HNAE3_ITR_COUNTDOWN_START 100
458
459struct hnae3_tc_info {
460 u16 tqp_offset; /* TQP offset from base TQP */
461 u16 tqp_count; /* Total TQPs */
38caee9d
S
462 u8 tc; /* TC index */
463 bool enable; /* If this TC is enable or not */
464};
465
466#define HNAE3_MAX_TC 8
c5795c53 467#define HNAE3_MAX_USER_PRIO 8
38caee9d
S
468struct hnae3_knic_private_info {
469 struct net_device *netdev; /* Set by KNIC client when init instance */
470 u16 rss_size; /* Allocated RSS queues */
471 u16 rx_buf_len;
472 u16 num_desc;
473
474 u8 num_tc; /* Total number of enabled TCs */
c5795c53 475 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */
38caee9d
S
476 struct hnae3_tc_info tc_info[HNAE3_MAX_TC]; /* Idx of array is HW TC */
477
478 u16 num_tqps; /* total number of TQPs in this handle */
479 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */
cacde272 480 const struct hnae3_dcb_ops *dcb_ops;
7e96adc4
FL
481
482 u16 int_rl_setting;
232fc64b 483 enum pkt_hash_types rss_type;
38caee9d
S
484};
485
486struct hnae3_roce_private_info {
487 struct net_device *netdev;
488 void __iomem *roce_io_base;
489 int base_vector;
490 int num_vectors;
491};
492
493struct hnae3_unic_private_info {
494 struct net_device *netdev;
495 u16 rx_buf_len;
496 u16 num_desc;
497 u16 num_tqps; /* total number of tqps in this handle */
498 struct hnae3_queue **tqp; /* array base of all TQPs of this instance */
499};
500
eb66d503 501#define HNAE3_SUPPORT_APP_LOOPBACK BIT(0)
424eb834 502#define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1)
4dc13b96 503#define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2)
424eb834 504#define HNAE3_SUPPORT_VF BIT(3)
4dc13b96 505#define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4)
38caee9d 506
c60edc17
JS
507#define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */
508#define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */
509#define HNAE3_BPE BIT(2) /* broadcast promisc enable */
510#define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */
511#define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */
512#define HNAE3_VLAN_FLTR BIT(5) /* enable vlan filter */
513#define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE)
514#define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)
515
38caee9d
S
516struct hnae3_handle {
517 struct hnae3_client *client;
518 struct pci_dev *pdev;
519 void *priv;
520 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */
521 u64 flags; /* Indicate the capabilities for this handle*/
522
6d4c3981
SM
523 unsigned long last_reset_time;
524 enum hnae3_reset_type reset_level;
525
38caee9d
S
526 union {
527 struct net_device *netdev; /* first member */
528 struct hnae3_knic_private_info kinfo;
529 struct hnae3_unic_private_info uinfo;
530 struct hnae3_roce_private_info rinfo;
531 };
532
533 u32 numa_node_mask; /* for multi-chip support */
c60edc17
JS
534
535 u8 netdev_flags;
38caee9d
S
536};
537
e4e87715 538#define hnae3_set_field(origin, mask, shift, val) \
38caee9d
S
539 do { \
540 (origin) &= (~(mask)); \
541 (origin) |= ((val) << (shift)) & (mask); \
542 } while (0)
e4e87715 543#define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
38caee9d 544
e4e87715
PL
545#define hnae3_set_bit(origin, shift, val) \
546 hnae3_set_field((origin), (0x1 << (shift)), (shift), (val))
547#define hnae3_get_bit(origin, shift) \
548 hnae3_get_field((origin), (0x1 << (shift)), (shift))
38caee9d 549
50fbc237 550void hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
38caee9d
S
551void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
552
553void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
854cf33a 554void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
38caee9d
S
555
556void hnae3_unregister_client(struct hnae3_client *client);
557int hnae3_register_client(struct hnae3_client *client);
d9f28fc2
JS
558
559void hnae3_set_client_init_flag(struct hnae3_client *client,
560 struct hnae3_ae_dev *ae_dev, int inited);
38caee9d 561#endif