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net: hns3: remove add/del_tunnel_udp in hns3_enet module
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
76ad4f0e
S		 1/*
2 * Copyright (c) 2016~2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/dma-mapping.h>
11#include <linux/etherdevice.h>
12#include <linux/interrupt.h>
13#include <linux/if_vlan.h>
14#include <linux/ip.h>
15#include <linux/ipv6.h>
16#include <linux/module.h>
17#include <linux/pci.h>
18#include <linux/skbuff.h>
19#include <linux/sctp.h>
20#include <linux/vermagic.h>
21#include <net/gre.h>
30d240df 22#include <net/pkt_cls.h>
76ad4f0e
S		 23#include <net/vxlan.h>
24
25#include "hnae3.h"
26#include "hns3_enet.h"
27
1db9b1bf 28static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 29const char hns3_driver_version[] = VERMAGIC_STRING;
30static const char hns3_driver_string[] =
31 "Hisilicon Ethernet Network Driver for Hip08 Family";
32static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
33static struct hnae3_client client;
34
35/* hns3_pci_tbl - PCI Device ID Table
36 *
37 * Last entry must be all 0s
38 *
39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
40 * Class, Class Mask, private data (not used) }
41 */
42static const struct pci_device_id hns3_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834
SM		 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
76ad4f0e
S		 57 /* required last entry */
58 {0, }
59};
60MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
61
62static irqreturn_t hns3_irq_handle(int irq, void *dev)
63{
64 struct hns3_enet_tqp_vector *tqp_vector = dev;
65
66 napi_schedule(&tqp_vector->napi);
67
68 return IRQ_HANDLED;
69}
70
71static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
72{
73 struct hns3_enet_tqp_vector *tqp_vectors;
74 unsigned int i;
75
76 for (i = 0; i < priv->vector_num; i++) {
77 tqp_vectors = &priv->tqp_vector[i];
78
79 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
80 continue;
81
82 /* release the irq resource */
83 free_irq(tqp_vectors->vector_irq, tqp_vectors);
84 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
85 }
86}
87
88static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
89{
90 struct hns3_enet_tqp_vector *tqp_vectors;
91 int txrx_int_idx = 0;
92 int rx_int_idx = 0;
93 int tx_int_idx = 0;
94 unsigned int i;
95 int ret;
96
97 for (i = 0; i < priv->vector_num; i++) {
98 tqp_vectors = &priv->tqp_vector[i];
99
100 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
101 continue;
102
103 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
104 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
105 "%s-%s-%d", priv->netdev->name, "TxRx",
106 txrx_int_idx++);
107 txrx_int_idx++;
108 } else if (tqp_vectors->rx_group.ring) {
109 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
110 "%s-%s-%d", priv->netdev->name, "Rx",
111 rx_int_idx++);
112 } else if (tqp_vectors->tx_group.ring) {
113 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
114 "%s-%s-%d", priv->netdev->name, "Tx",
115 tx_int_idx++);
116 } else {
117 /* Skip this unused q_vector */
118 continue;
119 }
120
121 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
122
123 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
124 tqp_vectors->name,
125 tqp_vectors);
126 if (ret) {
127 netdev_err(priv->netdev, "request irq(%d) fail\n",
128 tqp_vectors->vector_irq);
129 return ret;
130 }
131
132 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
133 }
134
135 return 0;
136}
137
138static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
139 u32 mask_en)
140{
141 writel(mask_en, tqp_vector->mask_addr);
142}
143
144static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
145{
146 napi_enable(&tqp_vector->napi);
147
148 /* enable vector */
149 hns3_mask_vector_irq(tqp_vector, 1);
150}
151
152static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
153{
154 /* disable vector */
155 hns3_mask_vector_irq(tqp_vector, 0);
156
157 disable_irq(tqp_vector->vector_irq);
158 napi_disable(&tqp_vector->napi);
159}
160
434776a5
FL		 161void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
162 u32 rl_value)
76ad4f0e 163{
434776a5
FL		 164 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
165
76ad4f0e
S		 166 /* this defines the configuration for RL (Interrupt Rate Limiter).
167 * Rl defines rate of interrupts i.e. number of interrupts-per-second
168 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
169 */
434776a5 170
9bc727a9
YL		 171 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
172 !tqp_vector->rx_group.coal.gl_adapt_enable)
434776a5
FL		 173 /* According to the hardware, the range of rl_reg is
174 * 0-59 and the unit is 4.
175 */
176 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
177
178 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
179}
180
181void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
182 u32 gl_value)
183{
184 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
185
186 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
187}
188
189void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
190 u32 gl_value)
191{
192 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
193
194 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 195}
196
5fd4789a
FL		 197static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
198 struct hns3_nic_priv *priv)
76ad4f0e 199{
5fd4789a
FL		 200 struct hnae3_handle *h = priv->ae_handle;
201
76ad4f0e
S		 202 /* initialize the configuration for interrupt coalescing.
203 * 1. GL (Interrupt Gap Limiter)
204 * 2. RL (Interrupt Rate Limiter)
205 */
206
5fd4789a 207 /* Default: enable interrupt coalescing self-adaptive and GL */
9bc727a9
YL		 208 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
209 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 210
9bc727a9
YL		 211 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
212 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 213
5fd4789a
FL		 214 /* Default: disable RL */
215 h->kinfo.int_rl_setting = 0;
5fd4789a 216
cd9d187b 217 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
9bc727a9
YL		 218 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
219 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 220}
221
dd38c726
YL		 222static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
223 struct hns3_nic_priv *priv)
224{
225 struct hnae3_handle *h = priv->ae_handle;
226
227 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 228 tqp_vector->tx_group.coal.int_gl);
dd38c726 229 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 230 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL		 231 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
232}
233
9df8f79a
YL		 234static int hns3_nic_set_real_num_queue(struct net_device *netdev)
235{
9780cb97 236 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 237 struct hnae3_knic_private_info *kinfo = &h->kinfo;
238 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
239 int ret;
240
241 ret = netif_set_real_num_tx_queues(netdev, queue_size);
242 if (ret) {
243 netdev_err(netdev,
244 "netif_set_real_num_tx_queues fail, ret=%d!\n",
245 ret);
246 return ret;
247 }
248
249 ret = netif_set_real_num_rx_queues(netdev, queue_size);
250 if (ret) {
251 netdev_err(netdev,
252 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
253 return ret;
254 }
255
256 return 0;
257}
258
678335a1
PL		 259static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
260{
261 u16 free_tqps, max_rss_size, max_tqps;
262
263 h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size);
264 max_tqps = h->kinfo.num_tc * max_rss_size;
265
266 return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps));
267}
268
76ad4f0e
S		 269static int hns3_nic_net_up(struct net_device *netdev)
270{
271 struct hns3_nic_priv *priv = netdev_priv(netdev);
272 struct hnae3_handle *h = priv->ae_handle;
273 int i, j;
274 int ret;
275
276 /* get irq resource for all vectors */
277 ret = hns3_nic_init_irq(priv);
278 if (ret) {
279 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
280 return ret;
281 }
282
283 /* enable the vectors */
284 for (i = 0; i < priv->vector_num; i++)
285 hns3_vector_enable(&priv->tqp_vector[i]);
286
287 /* start the ae_dev */
288 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
289 if (ret)
290 goto out_start_err;
291
b875cc37
JS		 292 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
293
76ad4f0e
S		 294 return 0;
295
296out_start_err:
297 for (j = i - 1; j >= 0; j--)
298 hns3_vector_disable(&priv->tqp_vector[j]);
299
300 hns3_nic_uninit_irq(priv);
301
302 return ret;
303}
304
305static int hns3_nic_net_open(struct net_device *netdev)
306{
f8fa222c 307 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 308 int ret;
309
310 netif_carrier_off(netdev);
311
9df8f79a
YL		 312 ret = hns3_nic_set_real_num_queue(netdev);
313 if (ret)
76ad4f0e 314 return ret;
76ad4f0e
S		 315
316 ret = hns3_nic_net_up(netdev);
317 if (ret) {
318 netdev_err(netdev,
319 "hns net up fail, ret=%d!\n", ret);
320 return ret;
321 }
322
6d4c3981 323 priv->ae_handle->last_reset_time = jiffies;
76ad4f0e
S		 324 return 0;
325}
326
327static void hns3_nic_net_down(struct net_device *netdev)
328{
329 struct hns3_nic_priv *priv = netdev_priv(netdev);
330 const struct hnae3_ae_ops *ops;
331 int i;
332
b875cc37
JS		 333 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
334 return;
335
76ad4f0e
S		 336 /* stop ae_dev */
337 ops = priv->ae_handle->ae_algo->ops;
338 if (ops->stop)
339 ops->stop(priv->ae_handle);
340
341 /* disable vectors */
342 for (i = 0; i < priv->vector_num; i++)
343 hns3_vector_disable(&priv->tqp_vector[i]);
344
345 /* free irq resources */
346 hns3_nic_uninit_irq(priv);
347}
348
349static int hns3_nic_net_stop(struct net_device *netdev)
350{
351 netif_tx_stop_all_queues(netdev);
352 netif_carrier_off(netdev);
353
354 hns3_nic_net_down(netdev);
355
356 return 0;
357}
358
76ad4f0e
S		 359static int hns3_nic_uc_sync(struct net_device *netdev,
360 const unsigned char *addr)
361{
9780cb97 362 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 363
364 if (h->ae_algo->ops->add_uc_addr)
365 return h->ae_algo->ops->add_uc_addr(h, addr);
366
367 return 0;
368}
369
370static int hns3_nic_uc_unsync(struct net_device *netdev,
371 const unsigned char *addr)
372{
9780cb97 373 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 374
375 if (h->ae_algo->ops->rm_uc_addr)
376 return h->ae_algo->ops->rm_uc_addr(h, addr);
377
378 return 0;
379}
380
381static int hns3_nic_mc_sync(struct net_device *netdev,
382 const unsigned char *addr)
383{
9780cb97 384 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 385
720a8478 386 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 387 return h->ae_algo->ops->add_mc_addr(h, addr);
388
389 return 0;
390}
391
392static int hns3_nic_mc_unsync(struct net_device *netdev,
393 const unsigned char *addr)
394{
9780cb97 395 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 396
720a8478 397 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 398 return h->ae_algo->ops->rm_mc_addr(h, addr);
399
400 return 0;
401}
402
1db9b1bf 403static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 404{
9780cb97 405 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 406
407 if (h->ae_algo->ops->set_promisc_mode) {
408 if (netdev->flags & IFF_PROMISC)
409 h->ae_algo->ops->set_promisc_mode(h, 1);
410 else
411 h->ae_algo->ops->set_promisc_mode(h, 0);
412 }
413 if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync))
414 netdev_err(netdev, "sync uc address fail\n");
415 if (netdev->flags & IFF_MULTICAST)
416 if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync))
417 netdev_err(netdev, "sync mc address fail\n");
418}
419
420static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
421 u16 *mss, u32 *type_cs_vlan_tso)
422{
423 u32 l4_offset, hdr_len;
424 union l3_hdr_info l3;
425 union l4_hdr_info l4;
426 u32 l4_paylen;
427 int ret;
428
429 if (!skb_is_gso(skb))
430 return 0;
431
432 ret = skb_cow_head(skb, 0);
433 if (ret)
434 return ret;
435
436 l3.hdr = skb_network_header(skb);
437 l4.hdr = skb_transport_header(skb);
438
439 /* Software should clear the IPv4's checksum field when tso is
440 * needed.
441 */
442 if (l3.v4->version == 4)
443 l3.v4->check = 0;
444
445 /* tunnel packet.*/
446 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
447 SKB_GSO_GRE_CSUM |
448 SKB_GSO_UDP_TUNNEL |
449 SKB_GSO_UDP_TUNNEL_CSUM)) {
450 if ((!(skb_shinfo(skb)->gso_type &
451 SKB_GSO_PARTIAL)) &&
452 (skb_shinfo(skb)->gso_type &
453 SKB_GSO_UDP_TUNNEL_CSUM)) {
454 /* Software should clear the udp's checksum
455 * field when tso is needed.
456 */
457 l4.udp->check = 0;
458 }
459 /* reset l3&l4 pointers from outer to inner headers */
460 l3.hdr = skb_inner_network_header(skb);
461 l4.hdr = skb_inner_transport_header(skb);
462
463 /* Software should clear the IPv4's checksum field when
464 * tso is needed.
465 */
466 if (l3.v4->version == 4)
467 l3.v4->check = 0;
468 }
469
470 /* normal or tunnel packet*/
471 l4_offset = l4.hdr - skb->data;
472 hdr_len = (l4.tcp->doff * 4) + l4_offset;
473
474 /* remove payload length from inner pseudo checksum when tso*/
475 l4_paylen = skb->len - l4_offset;
476 csum_replace_by_diff(&l4.tcp->check,
477 (__force __wsum)htonl(l4_paylen));
478
479 /* find the txbd field values */
480 *paylen = skb->len - hdr_len;
481 hnae_set_bit(*type_cs_vlan_tso,
482 HNS3_TXD_TSO_B, 1);
483
484 /* get MSS for TSO */
485 *mss = skb_shinfo(skb)->gso_size;
486
487 return 0;
488}
489
1898d4e4
S		 490static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
491 u8 *il4_proto)
76ad4f0e
S		 492{
493 union {
494 struct iphdr *v4;
495 struct ipv6hdr *v6;
496 unsigned char *hdr;
497 } l3;
498 unsigned char *l4_hdr;
499 unsigned char *exthdr;
500 u8 l4_proto_tmp;
501 __be16 frag_off;
502
503 /* find outer header point */
504 l3.hdr = skb_network_header(skb);
35f58fd7 505 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 506
507 if (skb->protocol == htons(ETH_P_IPV6)) {
508 exthdr = l3.hdr + sizeof(*l3.v6);
509 l4_proto_tmp = l3.v6->nexthdr;
510 if (l4_hdr != exthdr)
511 ipv6_skip_exthdr(skb, exthdr - skb->data,
512 &l4_proto_tmp, &frag_off);
513 } else if (skb->protocol == htons(ETH_P_IP)) {
514 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 515 } else {
516 return -EINVAL;
76ad4f0e
S		 517 }
518
519 *ol4_proto = l4_proto_tmp;
520
521 /* tunnel packet */
522 if (!skb->encapsulation) {
523 *il4_proto = 0;
1898d4e4 524 return 0;
76ad4f0e
S		 525 }
526
527 /* find inner header point */
528 l3.hdr = skb_inner_network_header(skb);
529 l4_hdr = skb_inner_transport_header(skb);
530
531 if (l3.v6->version == 6) {
532 exthdr = l3.hdr + sizeof(*l3.v6);
533 l4_proto_tmp = l3.v6->nexthdr;
534 if (l4_hdr != exthdr)
535 ipv6_skip_exthdr(skb, exthdr - skb->data,
536 &l4_proto_tmp, &frag_off);
537 } else if (l3.v4->version == 4) {
538 l4_proto_tmp = l3.v4->protocol;
539 }
540
541 *il4_proto = l4_proto_tmp;
1898d4e4
S		 542
543 return 0;
76ad4f0e
S		 544}
545
546static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
547 u8 il4_proto, u32 *type_cs_vlan_tso,
548 u32 *ol_type_vlan_len_msec)
549{
550 union {
551 struct iphdr *v4;
552 struct ipv6hdr *v6;
553 unsigned char *hdr;
554 } l3;
555 union {
556 struct tcphdr *tcp;
557 struct udphdr *udp;
558 struct gre_base_hdr *gre;
559 unsigned char *hdr;
560 } l4;
561 unsigned char *l2_hdr;
562 u8 l4_proto = ol4_proto;
563 u32 ol2_len;
564 u32 ol3_len;
565 u32 ol4_len;
566 u32 l2_len;
567 u32 l3_len;
568
569 l3.hdr = skb_network_header(skb);
570 l4.hdr = skb_transport_header(skb);
571
572 /* compute L2 header size for normal packet, defined in 2 Bytes */
573 l2_len = l3.hdr - skb->data;
574 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
575 HNS3_TXD_L2LEN_S, l2_len >> 1);
576
577 /* tunnel packet*/
578 if (skb->encapsulation) {
579 /* compute OL2 header size, defined in 2 Bytes */
580 ol2_len = l2_len;
581 hnae_set_field(*ol_type_vlan_len_msec,
582 HNS3_TXD_L2LEN_M,
583 HNS3_TXD_L2LEN_S, ol2_len >> 1);
584
585 /* compute OL3 header size, defined in 4 Bytes */
586 ol3_len = l4.hdr - l3.hdr;
587 hnae_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
588 HNS3_TXD_L3LEN_S, ol3_len >> 2);
589
590 /* MAC in UDP, MAC in GRE (0x6558)*/
591 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
592 /* switch MAC header ptr from outer to inner header.*/
593 l2_hdr = skb_inner_mac_header(skb);
594
595 /* compute OL4 header size, defined in 4 Bytes. */
596 ol4_len = l2_hdr - l4.hdr;
597 hnae_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_M,
598 HNS3_TXD_L4LEN_S, ol4_len >> 2);
599
600 /* switch IP header ptr from outer to inner header */
601 l3.hdr = skb_inner_network_header(skb);
602
603 /* compute inner l2 header size, defined in 2 Bytes. */
604 l2_len = l3.hdr - l2_hdr;
605 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
606 HNS3_TXD_L2LEN_S, l2_len >> 1);
607 } else {
608 /* skb packet types not supported by hardware,
609 * txbd len fild doesn't be filled.
610 */
611 return;
612 }
613
614 /* switch L4 header pointer from outer to inner */
615 l4.hdr = skb_inner_transport_header(skb);
616
617 l4_proto = il4_proto;
618 }
619
620 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
621 l3_len = l4.hdr - l3.hdr;
622 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
623 HNS3_TXD_L3LEN_S, l3_len >> 2);
624
625 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
626 switch (l4_proto) {
627 case IPPROTO_TCP:
628 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
629 HNS3_TXD_L4LEN_S, l4.tcp->doff);
630 break;
631 case IPPROTO_SCTP:
632 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
633 HNS3_TXD_L4LEN_S, (sizeof(struct sctphdr) >> 2));
634 break;
635 case IPPROTO_UDP:
636 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
637 HNS3_TXD_L4LEN_S, (sizeof(struct udphdr) >> 2));
638 break;
639 default:
640 /* skb packet types not supported by hardware,
641 * txbd len fild doesn't be filled.
642 */
643 return;
644 }
645}
646
647static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
648 u8 il4_proto, u32 *type_cs_vlan_tso,
649 u32 *ol_type_vlan_len_msec)
650{
651 union {
652 struct iphdr *v4;
653 struct ipv6hdr *v6;
654 unsigned char *hdr;
655 } l3;
656 u32 l4_proto = ol4_proto;
657
658 l3.hdr = skb_network_header(skb);
659
660 /* define OL3 type and tunnel type(OL4).*/
661 if (skb->encapsulation) {
662 /* define outer network header type.*/
663 if (skb->protocol == htons(ETH_P_IP)) {
664 if (skb_is_gso(skb))
665 hnae_set_field(*ol_type_vlan_len_msec,
666 HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
667 HNS3_OL3T_IPV4_CSUM);
668 else
669 hnae_set_field(*ol_type_vlan_len_msec,
670 HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
671 HNS3_OL3T_IPV4_NO_CSUM);
672
673 } else if (skb->protocol == htons(ETH_P_IPV6)) {
674 hnae_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
675 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
676 }
677
678 /* define tunnel type(OL4).*/
679 switch (l4_proto) {
680 case IPPROTO_UDP:
681 hnae_set_field(*ol_type_vlan_len_msec,
682 HNS3_TXD_TUNTYPE_M,
683 HNS3_TXD_TUNTYPE_S,
684 HNS3_TUN_MAC_IN_UDP);
685 break;
686 case IPPROTO_GRE:
687 hnae_set_field(*ol_type_vlan_len_msec,
688 HNS3_TXD_TUNTYPE_M,
689 HNS3_TXD_TUNTYPE_S,
690 HNS3_TUN_NVGRE);
691 break;
692 default:
693 /* drop the skb tunnel packet if hardware don't support,
694 * because hardware can't calculate csum when TSO.
695 */
696 if (skb_is_gso(skb))
697 return -EDOM;
698
699 /* the stack computes the IP header already,
700 * driver calculate l4 checksum when not TSO.
701 */
702 skb_checksum_help(skb);
703 return 0;
704 }
705
706 l3.hdr = skb_inner_network_header(skb);
707 l4_proto = il4_proto;
708 }
709
710 if (l3.v4->version == 4) {
711 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
712 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
713
714 /* the stack computes the IP header already, the only time we
715 * need the hardware to recompute it is in the case of TSO.
716 */
717 if (skb_is_gso(skb))
718 hnae_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
719
720 hnae_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
721 } else if (l3.v6->version == 6) {
722 hnae_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
723 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
724 hnae_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
725 }
726
727 switch (l4_proto) {
728 case IPPROTO_TCP:
729 hnae_set_field(*type_cs_vlan_tso,
730 HNS3_TXD_L4T_M,
731 HNS3_TXD_L4T_S,
732 HNS3_L4T_TCP);
733 break;
734 case IPPROTO_UDP:
735 hnae_set_field(*type_cs_vlan_tso,
736 HNS3_TXD_L4T_M,
737 HNS3_TXD_L4T_S,
738 HNS3_L4T_UDP);
739 break;
740 case IPPROTO_SCTP:
741 hnae_set_field(*type_cs_vlan_tso,
742 HNS3_TXD_L4T_M,
743 HNS3_TXD_L4T_S,
744 HNS3_L4T_SCTP);
745 break;
746 default:
747 /* drop the skb tunnel packet if hardware don't support,
748 * because hardware can't calculate csum when TSO.
749 */
750 if (skb_is_gso(skb))
751 return -EDOM;
752
753 /* the stack computes the IP header already,
754 * driver calculate l4 checksum when not TSO.
755 */
756 skb_checksum_help(skb);
757 return 0;
758 }
759
760 return 0;
761}
762
763static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
764{
765 /* Config bd buffer end */
766 hnae_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
3c8f5c03 767 HNS3_TXD_BDTYPE_S, 0);
76ad4f0e
S		 768 hnae_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
769 hnae_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
7036d26f 770 hnae_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
76ad4f0e
S		 771}
772
9699cffe
PL		 773static int hns3_fill_desc_vtags(struct sk_buff *skb,
774 struct hns3_enet_ring *tx_ring,
775 u32 *inner_vlan_flag,
776 u32 *out_vlan_flag,
777 u16 *inner_vtag,
778 u16 *out_vtag)
779{
780#define HNS3_TX_VLAN_PRIO_SHIFT 13
781
782 if (skb->protocol == htons(ETH_P_8021Q) &&
783 !(tx_ring->tqp->handle->kinfo.netdev->features &
784 NETIF_F_HW_VLAN_CTAG_TX)) {
785 /* When HW VLAN acceleration is turned off, and the stack
786 * sets the protocol to 802.1q, the driver just need to
787 * set the protocol to the encapsulated ethertype.
788 */
789 skb->protocol = vlan_get_protocol(skb);
790 return 0;
791 }
792
793 if (skb_vlan_tag_present(skb)) {
794 u16 vlan_tag;
795
796 vlan_tag = skb_vlan_tag_get(skb);
797 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
798
799 /* Based on hw strategy, use out_vtag in two layer tag case,
800 * and use inner_vtag in one tag case.
801 */
802 if (skb->protocol == htons(ETH_P_8021Q)) {
803 hnae_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
804 *out_vtag = vlan_tag;
805 } else {
806 hnae_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
807 *inner_vtag = vlan_tag;
808 }
809 } else if (skb->protocol == htons(ETH_P_8021Q)) {
810 struct vlan_ethhdr *vhdr;
811 int rc;
812
813 rc = skb_cow_head(skb, 0);
814 if (rc < 0)
815 return rc;
816 vhdr = (struct vlan_ethhdr *)skb->data;
817 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
818 << HNS3_TX_VLAN_PRIO_SHIFT);
819 }
820
821 skb->protocol = vlan_get_protocol(skb);
822 return 0;
823}
824
76ad4f0e
S		 825static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
826 int size, dma_addr_t dma, int frag_end,
827 enum hns_desc_type type)
828{
829 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
830 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
831 u32 ol_type_vlan_len_msec = 0;
832 u16 bdtp_fe_sc_vld_ra_ri = 0;
833 u32 type_cs_vlan_tso = 0;
834 struct sk_buff *skb;
9699cffe
PL		 835 u16 inner_vtag = 0;
836 u16 out_vtag = 0;
76ad4f0e
S		 837 u32 paylen = 0;
838 u16 mss = 0;
839 __be16 protocol;
840 u8 ol4_proto;
841 u8 il4_proto;
842 int ret;
843
844 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
845 desc_cb->priv = priv;
846 desc_cb->length = size;
847 desc_cb->dma = dma;
848 desc_cb->type = type;
849
850 /* now, fill the descriptor */
851 desc->addr = cpu_to_le64(dma);
852 desc->tx.send_size = cpu_to_le16((u16)size);
853 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
854 desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
855
856 if (type == DESC_TYPE_SKB) {
857 skb = (struct sk_buff *)priv;
a90bb9a5 858 paylen = skb->len;
76ad4f0e 859
9699cffe
PL		 860 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
861 &ol_type_vlan_len_msec,
862 &inner_vtag, &out_vtag);
863 if (unlikely(ret))
864 return ret;
865
76ad4f0e
S		 866 if (skb->ip_summed == CHECKSUM_PARTIAL) {
867 skb_reset_mac_len(skb);
868 protocol = skb->protocol;
869
1898d4e4
S		 870 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
871 if (ret)
872 return ret;
76ad4f0e
S		 873 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
874 &type_cs_vlan_tso,
875 &ol_type_vlan_len_msec);
876 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
877 &type_cs_vlan_tso,
878 &ol_type_vlan_len_msec);
879 if (ret)
880 return ret;
881
882 ret = hns3_set_tso(skb, &paylen, &mss,
883 &type_cs_vlan_tso);
884 if (ret)
885 return ret;
886 }
887
888 /* Set txbd */
889 desc->tx.ol_type_vlan_len_msec =
890 cpu_to_le32(ol_type_vlan_len_msec);
891 desc->tx.type_cs_vlan_tso_len =
892 cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 893 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 894 desc->tx.mss = cpu_to_le16(mss);
9699cffe
PL		 895 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
896 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
76ad4f0e
S		 897 }
898
899 /* move ring pointer to next.*/
900 ring_ptr_move_fw(ring, next_to_use);
901
902 return 0;
903}
904
905static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv,
906 int size, dma_addr_t dma, int frag_end,
907 enum hns_desc_type type)
908{
909 unsigned int frag_buf_num;
910 unsigned int k;
911 int sizeoflast;
912 int ret;
913
914 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
915 sizeoflast = size % HNS3_MAX_BD_SIZE;
916 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
917
918 /* When the frag size is bigger than hardware, split this frag */
919 for (k = 0; k < frag_buf_num; k++) {
920 ret = hns3_fill_desc(ring, priv,
921 (k == frag_buf_num - 1) ?
922 sizeoflast : HNS3_MAX_BD_SIZE,
923 dma + HNS3_MAX_BD_SIZE * k,
924 frag_end && (k == frag_buf_num - 1) ? 1 : 0,
925 (type == DESC_TYPE_SKB && !k) ?
926 DESC_TYPE_SKB : DESC_TYPE_PAGE);
927 if (ret)
928 return ret;
929 }
930
931 return 0;
932}
933
934static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
935 struct hns3_enet_ring *ring)
936{
937 struct sk_buff *skb = *out_skb;
938 struct skb_frag_struct *frag;
939 int bdnum_for_frag;
940 int frag_num;
941 int buf_num;
942 int size;
943 int i;
944
945 size = skb_headlen(skb);
946 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
947
948 frag_num = skb_shinfo(skb)->nr_frags;
949 for (i = 0; i < frag_num; i++) {
950 frag = &skb_shinfo(skb)->frags[i];
951 size = skb_frag_size(frag);
952 bdnum_for_frag =
953 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
954 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
955 return -ENOMEM;
956
957 buf_num += bdnum_for_frag;
958 }
959
960 if (buf_num > ring_space(ring))
961 return -EBUSY;
962
963 *bnum = buf_num;
964 return 0;
965}
966
967static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
968 struct hns3_enet_ring *ring)
969{
970 struct sk_buff *skb = *out_skb;
971 int buf_num;
972
973 /* No. of segments (plus a header) */
974 buf_num = skb_shinfo(skb)->nr_frags + 1;
975
976 if (buf_num > ring_space(ring))
977 return -EBUSY;
978
979 *bnum = buf_num;
980
981 return 0;
982}
983
984static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig)
985{
986 struct device *dev = ring_to_dev(ring);
987 unsigned int i;
988
989 for (i = 0; i < ring->desc_num; i++) {
990 /* check if this is where we started */
991 if (ring->next_to_use == next_to_use_orig)
992 break;
993
994 /* unmap the descriptor dma address */
995 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
996 dma_unmap_single(dev,
997 ring->desc_cb[ring->next_to_use].dma,
998 ring->desc_cb[ring->next_to_use].length,
999 DMA_TO_DEVICE);
1000 else
1001 dma_unmap_page(dev,
1002 ring->desc_cb[ring->next_to_use].dma,
1003 ring->desc_cb[ring->next_to_use].length,
1004 DMA_TO_DEVICE);
1005
1006 /* rollback one */
1007 ring_ptr_move_bw(ring, next_to_use);
1008 }
1009}
1010
d43e5aca 1011netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1012{
1013 struct hns3_nic_priv *priv = netdev_priv(netdev);
1014 struct hns3_nic_ring_data *ring_data =
1015 &tx_ring_data(priv, skb->queue_mapping);
1016 struct hns3_enet_ring *ring = ring_data->ring;
1017 struct device *dev = priv->dev;
1018 struct netdev_queue *dev_queue;
1019 struct skb_frag_struct *frag;
1020 int next_to_use_head;
1021 int next_to_use_frag;
1022 dma_addr_t dma;
1023 int buf_num;
1024 int seg_num;
1025 int size;
1026 int ret;
1027 int i;
1028
1029 /* Prefetch the data used later */
1030 prefetch(skb->data);
1031
1032 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1033 case -EBUSY:
1034 u64_stats_update_begin(&ring->syncp);
1035 ring->stats.tx_busy++;
1036 u64_stats_update_end(&ring->syncp);
1037
1038 goto out_net_tx_busy;
1039 case -ENOMEM:
1040 u64_stats_update_begin(&ring->syncp);
1041 ring->stats.sw_err_cnt++;
1042 u64_stats_update_end(&ring->syncp);
1043 netdev_err(netdev, "no memory to xmit!\n");
1044
1045 goto out_err_tx_ok;
1046 default:
1047 break;
1048 }
1049
1050 /* No. of segments (plus a header) */
1051 seg_num = skb_shinfo(skb)->nr_frags + 1;
1052 /* Fill the first part */
1053 size = skb_headlen(skb);
1054
1055 next_to_use_head = ring->next_to_use;
1056
1057 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1058 if (dma_mapping_error(dev, dma)) {
1059 netdev_err(netdev, "TX head DMA map failed\n");
1060 ring->stats.sw_err_cnt++;
1061 goto out_err_tx_ok;
1062 }
1063
1064 ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0,
1065 DESC_TYPE_SKB);
1066 if (ret)
1067 goto head_dma_map_err;
1068
1069 next_to_use_frag = ring->next_to_use;
1070 /* Fill the fragments */
1071 for (i = 1; i < seg_num; i++) {
1072 frag = &skb_shinfo(skb)->frags[i - 1];
1073 size = skb_frag_size(frag);
1074 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1075 if (dma_mapping_error(dev, dma)) {
1076 netdev_err(netdev, "TX frag(%d) DMA map failed\n", i);
1077 ring->stats.sw_err_cnt++;
1078 goto frag_dma_map_err;
1079 }
1080 ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma,
1081 seg_num - 1 == i ? 1 : 0,
1082 DESC_TYPE_PAGE);
1083
1084 if (ret)
1085 goto frag_dma_map_err;
1086 }
1087
1088 /* Complete translate all packets */
1089 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1090 netdev_tx_sent_queue(dev_queue, skb->len);
1091
1092 wmb(); /* Commit all data before submit */
1093
1094 hnae_queue_xmit(ring->tqp, buf_num);
1095
1096 return NETDEV_TX_OK;
1097
1098frag_dma_map_err:
1099 hns_nic_dma_unmap(ring, next_to_use_frag);
1100
1101head_dma_map_err:
1102 hns_nic_dma_unmap(ring, next_to_use_head);
1103
1104out_err_tx_ok:
1105 dev_kfree_skb_any(skb);
1106 return NETDEV_TX_OK;
1107
1108out_net_tx_busy:
1109 netif_stop_subqueue(netdev, ring_data->queue_index);
1110 smp_mb(); /* Commit all data before submit */
1111
1112 return NETDEV_TX_BUSY;
1113}
1114
1115static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1116{
9780cb97 1117 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1118 struct sockaddr *mac_addr = p;
1119 int ret;
1120
1121 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1122 return -EADDRNOTAVAIL;
1123
59098055 1124 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1125 if (ret) {
1126 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1127 return ret;
1128 }
1129
1130 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1131
1132 return 0;
1133}
1134
1135static int hns3_nic_set_features(struct net_device *netdev,
1136 netdev_features_t features)
1137{
181d454b 1138 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1139 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1140 struct hnae3_handle *h = priv->ae_handle;
052ece6d 1141 int ret;
76ad4f0e 1142
181d454b
JS		 1143 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
1144 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) {
1145 priv->ops.fill_desc = hns3_fill_desc_tso;
1146 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
1147 } else {
1148 priv->ops.fill_desc = hns3_fill_desc;
1149 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
1150 }
76ad4f0e
S		 1151 }
1152
bd368416
JS		 1153 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1154 h->ae_algo->ops->enable_vlan_filter) {
181d454b
JS		 1155 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1156 h->ae_algo->ops->enable_vlan_filter(h, true);
1157 else
1158 h->ae_algo->ops->enable_vlan_filter(h, false);
1159 }
391b5e93 1160
bd368416
JS		 1161 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1162 h->ae_algo->ops->enable_hw_strip_rxvtag) {
052ece6d
PL		 1163 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1164 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1165 else
1166 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1167
1168 if (ret)
1169 return ret;
1170 }
1171
76ad4f0e
S		 1172 netdev->features = features;
1173 return 0;
1174}
1175
6c88d9d7
PL		 1176static void hns3_nic_get_stats64(struct net_device *netdev,
1177 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1178{
1179 struct hns3_nic_priv *priv = netdev_priv(netdev);
1180 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1181 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e
S		 1182 struct hns3_enet_ring *ring;
1183 unsigned int start;
1184 unsigned int idx;
1185 u64 tx_bytes = 0;
1186 u64 rx_bytes = 0;
1187 u64 tx_pkts = 0;
1188 u64 rx_pkts = 0;
d2a5dca8
JS		 1189 u64 tx_drop = 0;
1190 u64 rx_drop = 0;
76ad4f0e 1191
b875cc37
JS		 1192 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1193 return;
1194
c5f65480
JS		 1195 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1196
76ad4f0e
S		 1197 for (idx = 0; idx < queue_num; idx++) {
1198 /* fetch the tx stats */
1199 ring = priv->ring_data[idx].ring;
1200 do {
d36d36ce 1201 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1202 tx_bytes += ring->stats.tx_bytes;
1203 tx_pkts += ring->stats.tx_pkts;
d2a5dca8
JS		 1204 tx_drop += ring->stats.tx_busy;
1205 tx_drop += ring->stats.sw_err_cnt;
76ad4f0e
S		 1206 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1207
1208 /* fetch the rx stats */
1209 ring = priv->ring_data[idx + queue_num].ring;
1210 do {
d36d36ce 1211 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1212 rx_bytes += ring->stats.rx_bytes;
1213 rx_pkts += ring->stats.rx_pkts;
d2a5dca8
JS		 1214 rx_drop += ring->stats.non_vld_descs;
1215 rx_drop += ring->stats.err_pkt_len;
1216 rx_drop += ring->stats.l2_err;
76ad4f0e
S		 1217 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1218 }
1219
1220 stats->tx_bytes = tx_bytes;
1221 stats->tx_packets = tx_pkts;
1222 stats->rx_bytes = rx_bytes;
1223 stats->rx_packets = rx_pkts;
1224
1225 stats->rx_errors = netdev->stats.rx_errors;
1226 stats->multicast = netdev->stats.multicast;
1227 stats->rx_length_errors = netdev->stats.rx_length_errors;
1228 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
1229 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1230
1231 stats->tx_errors = netdev->stats.tx_errors;
d2a5dca8
JS		 1232 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
1233 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
76ad4f0e
S		 1234 stats->collisions = netdev->stats.collisions;
1235 stats->rx_over_errors = netdev->stats.rx_over_errors;
1236 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1237 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1238 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1239 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1240 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1241 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1242 stats->tx_window_errors = netdev->stats.tx_window_errors;
1243 stats->rx_compressed = netdev->stats.rx_compressed;
1244 stats->tx_compressed = netdev->stats.tx_compressed;
1245}
1246
30d240df 1247static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1248{
30d240df 1249 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
9780cb97 1250 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 1251 struct hnae3_knic_private_info *kinfo = &h->kinfo;
30d240df
YL		 1252 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1253 u8 tc = mqprio_qopt->qopt.num_tc;
1254 u16 mode = mqprio_qopt->mode;
1255 u8 hw = mqprio_qopt->qopt.hw;
1256 bool if_running;
76ad4f0e
S		 1257 unsigned int i;
1258 int ret;
1259
30d240df
YL		 1260 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1261 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1262 return -EOPNOTSUPP;
1263
76ad4f0e
S		 1264 if (tc > HNAE3_MAX_TC)
1265 return -EINVAL;
1266
76ad4f0e
S		 1267 if (!netdev)
1268 return -EINVAL;
1269
30d240df
YL		 1270 if_running = netif_running(netdev);
1271 if (if_running) {
1272 hns3_nic_net_stop(netdev);
1273 msleep(100);
76ad4f0e
S		 1274 }
1275
30d240df
YL		 1276 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1277 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e 1278 if (ret)
30d240df
YL		 1279 goto out;
1280
1281 if (tc <= 1) {
1282 netdev_reset_tc(netdev);
1283 } else {
1284 ret = netdev_set_num_tc(netdev, tc);
1285 if (ret)
1286 goto out;
1287
1288 for (i = 0; i < HNAE3_MAX_TC; i++) {
1289 if (!kinfo->tc_info[i].enable)
1290 continue;
76ad4f0e 1291
76ad4f0e
S		 1292 netdev_set_tc_queue(netdev,
1293 kinfo->tc_info[i].tc,
1294 kinfo->tc_info[i].tqp_count,
1295 kinfo->tc_info[i].tqp_offset);
30d240df 1296 }
76ad4f0e
S		 1297 }
1298
30d240df
YL		 1299 ret = hns3_nic_set_real_num_queue(netdev);
1300
1301out:
1302 if (if_running)
1303 hns3_nic_net_open(netdev);
1304
1305 return ret;
76ad4f0e
S		 1306}
1307
2572ac53 1308static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1309 void *type_data)
76ad4f0e 1310{
575ed7d3 1311 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1312 return -EOPNOTSUPP;
76ad4f0e 1313
30d240df 1314 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1315}
1316
1317static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1318 __be16 proto, u16 vid)
1319{
9780cb97 1320 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1321 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1322 int ret = -EIO;
1323
1324 if (h->ae_algo->ops->set_vlan_filter)
1325 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1326
681ec399
YL		 1327 if (!ret)
1328 set_bit(vid, priv->active_vlans);
1329
76ad4f0e
S		 1330 return ret;
1331}
1332
1333static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1334 __be16 proto, u16 vid)
1335{
9780cb97 1336 struct hnae3_handle *h = hns3_get_handle(netdev);
681ec399 1337 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1338 int ret = -EIO;
1339
1340 if (h->ae_algo->ops->set_vlan_filter)
1341 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1342
681ec399
YL		 1343 if (!ret)
1344 clear_bit(vid, priv->active_vlans);
1345
76ad4f0e
S		 1346 return ret;
1347}
1348
681ec399
YL		 1349static void hns3_restore_vlan(struct net_device *netdev)
1350{
1351 struct hns3_nic_priv *priv = netdev_priv(netdev);
1352 u16 vid;
1353 int ret;
1354
1355 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1356 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
1357 if (ret)
1358 netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n",
1359 vid, ret);
1360 }
1361}
1362
76ad4f0e
S		 1363static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1364 u8 qos, __be16 vlan_proto)
1365{
9780cb97 1366 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1367 int ret = -EIO;
1368
1369 if (h->ae_algo->ops->set_vf_vlan_filter)
1370 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1371 qos, vlan_proto);
1372
1373 return ret;
1374}
1375
a8e8b7ff
S		 1376static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1377{
9780cb97 1378 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1379 bool if_running = netif_running(netdev);
1380 int ret;
1381
1382 if (!h->ae_algo->ops->set_mtu)
1383 return -EOPNOTSUPP;
1384
1385 /* if this was called with netdev up then bring netdevice down */
1386 if (if_running) {
1387 (void)hns3_nic_net_stop(netdev);
1388 msleep(100);
1389 }
1390
1391 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1392 if (ret) {
1393 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1394 ret);
1395 return ret;
1396 }
1397
5bad95a1
FL		 1398 netdev->mtu = new_mtu;
1399
a8e8b7ff
S		 1400 /* if the netdev was running earlier, bring it up again */
1401 if (if_running && hns3_nic_net_open(netdev))
1402 ret = -EINVAL;
1403
1404 return ret;
1405}
1406
f8fa222c
L		 1407static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1408{
1409 struct hns3_nic_priv *priv = netdev_priv(ndev);
1410 struct hns3_enet_ring *tx_ring = NULL;
1411 int timeout_queue = 0;
1412 int hw_head, hw_tail;
1413 int i;
1414
1415 /* Find the stopped queue the same way the stack does */
1416 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1417 struct netdev_queue *q;
1418 unsigned long trans_start;
1419
1420 q = netdev_get_tx_queue(ndev, i);
1421 trans_start = q->trans_start;
1422 if (netif_xmit_stopped(q) &&
1423 time_after(jiffies,
1424 (trans_start + ndev->watchdog_timeo))) {
1425 timeout_queue = i;
1426 break;
1427 }
1428 }
1429
1430 if (i == ndev->num_tx_queues) {
1431 netdev_info(ndev,
1432 "no netdev TX timeout queue found, timeout count: %llu\n",
1433 priv->tx_timeout_count);
1434 return false;
1435 }
1436
1437 tx_ring = priv->ring_data[timeout_queue].ring;
1438
1439 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1440 HNS3_RING_TX_RING_HEAD_REG);
1441 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1442 HNS3_RING_TX_RING_TAIL_REG);
1443 netdev_info(ndev,
1444 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1445 priv->tx_timeout_count,
1446 timeout_queue,
1447 tx_ring->next_to_use,
1448 tx_ring->next_to_clean,
1449 hw_head,
1450 hw_tail,
1451 readl(tx_ring->tqp_vector->mask_addr));
1452
1453 return true;
1454}
1455
1456static void hns3_nic_net_timeout(struct net_device *ndev)
1457{
1458 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1459 struct hnae3_handle *h = priv->ae_handle;
1460
1461 if (!hns3_get_tx_timeo_queue_info(ndev))
1462 return;
1463
1464 priv->tx_timeout_count++;
1465
6d4c3981 1466 if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo)))
f8fa222c
L		 1467 return;
1468
6d4c3981 1469 /* request the reset */
f8fa222c 1470 if (h->ae_algo->ops->reset_event)
6d4c3981 1471 h->ae_algo->ops->reset_event(h);
f8fa222c
L		 1472}
1473
76ad4f0e
S		 1474static const struct net_device_ops hns3_nic_netdev_ops = {
1475 .ndo_open = hns3_nic_net_open,
1476 .ndo_stop = hns3_nic_net_stop,
1477 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1478 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1479 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
a8e8b7ff 1480 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1481 .ndo_set_features = hns3_nic_set_features,
1482 .ndo_get_stats64 = hns3_nic_get_stats64,
1483 .ndo_setup_tc = hns3_nic_setup_tc,
1484 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1485 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1486 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1487 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1488};
1489
1490/* hns3_probe - Device initialization routine
1491 * @pdev: PCI device information struct
1492 * @ent: entry in hns3_pci_tbl
1493 *
1494 * hns3_probe initializes a PF identified by a pci_dev structure.
1495 * The OS initialization, configuring of the PF private structure,
1496 * and a hardware reset occur.
1497 *
1498 * Returns 0 on success, negative on failure
1499 */
1500static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1501{
1502 struct hnae3_ae_dev *ae_dev;
1503 int ret;
1504
1505 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1506 GFP_KERNEL);
1507 if (!ae_dev) {
1508 ret = -ENOMEM;
1509 return ret;
1510 }
1511
1512 ae_dev->pdev = pdev;
e92a0843 1513 ae_dev->flag = ent->driver_data;
76ad4f0e
S		 1514 ae_dev->dev_type = HNAE3_DEV_KNIC;
1515 pci_set_drvdata(pdev, ae_dev);
1516
1517 return hnae3_register_ae_dev(ae_dev);
1518}
1519
1520/* hns3_remove - Device removal routine
1521 * @pdev: PCI device information struct
1522 */
1523static void hns3_remove(struct pci_dev *pdev)
1524{
1525 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1526
1527 hnae3_unregister_ae_dev(ae_dev);
76ad4f0e
S		 1528}
1529
1530static struct pci_driver hns3_driver = {
1531 .name = hns3_driver_name,
1532 .id_table = hns3_pci_tbl,
1533 .probe = hns3_probe,
1534 .remove = hns3_remove,
1535};
1536
1537/* set default feature to hns3 */
1538static void hns3_set_default_feature(struct net_device *netdev)
1539{
1540 netdev->priv_flags |= IFF_UNICAST_FLT;
1541
1542 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1543 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1544 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1545 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1546 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1547
1548 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1549
1550 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1551
1552 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1553 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 1554 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1555 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1556 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1557 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1558 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1559
1560 netdev->vlan_features |=
1561 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1562 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1563 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1564 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1565 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1566
1567 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 1568 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1569 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1570 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1571 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1572 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1573}
1574
1575static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1576 struct hns3_desc_cb *cb)
1577{
1578 unsigned int order = hnae_page_order(ring);
1579 struct page *p;
1580
1581 p = dev_alloc_pages(order);
1582 if (!p)
1583 return -ENOMEM;
1584
1585 cb->priv = p;
1586 cb->page_offset = 0;
1587 cb->reuse_flag = 0;
1588 cb->buf = page_address(p);
1589 cb->length = hnae_page_size(ring);
1590 cb->type = DESC_TYPE_PAGE;
1591
76ad4f0e
S		 1592 return 0;
1593}
1594
1595static void hns3_free_buffer(struct hns3_enet_ring *ring,
1596 struct hns3_desc_cb *cb)
1597{
1598 if (cb->type == DESC_TYPE_SKB)
1599 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1600 else if (!HNAE3_IS_TX_RING(ring))
1601 put_page((struct page *)cb->priv);
1602 memset(cb, 0, sizeof(*cb));
1603}
1604
1605static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1606{
1607 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1608 cb->length, ring_to_dma_dir(ring));
1609
1610 if (dma_mapping_error(ring_to_dev(ring), cb->dma))
1611 return -EIO;
1612
1613 return 0;
1614}
1615
1616static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
1617 struct hns3_desc_cb *cb)
1618{
1619 if (cb->type == DESC_TYPE_SKB)
1620 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
1621 ring_to_dma_dir(ring));
1622 else
1623 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
1624 ring_to_dma_dir(ring));
1625}
1626
1627static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
1628{
1629 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
1630 ring->desc[i].addr = 0;
1631}
1632
1633static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
1634{
1635 struct hns3_desc_cb *cb = &ring->desc_cb[i];
1636
1637 if (!ring->desc_cb[i].dma)
1638 return;
1639
1640 hns3_buffer_detach(ring, i);
1641 hns3_free_buffer(ring, cb);
1642}
1643
1644static void hns3_free_buffers(struct hns3_enet_ring *ring)
1645{
1646 int i;
1647
1648 for (i = 0; i < ring->desc_num; i++)
1649 hns3_free_buffer_detach(ring, i);
1650}
1651
1652/* free desc along with its attached buffer */
1653static void hns3_free_desc(struct hns3_enet_ring *ring)
1654{
1655 hns3_free_buffers(ring);
1656
1657 dma_unmap_single(ring_to_dev(ring), ring->desc_dma_addr,
1658 ring->desc_num * sizeof(ring->desc[0]),
1659 DMA_BIDIRECTIONAL);
1660 ring->desc_dma_addr = 0;
1661 kfree(ring->desc);
1662 ring->desc = NULL;
1663}
1664
1665static int hns3_alloc_desc(struct hns3_enet_ring *ring)
1666{
1667 int size = ring->desc_num * sizeof(ring->desc[0]);
1668
1669 ring->desc = kzalloc(size, GFP_KERNEL);
1670 if (!ring->desc)
1671 return -ENOMEM;
1672
1673 ring->desc_dma_addr = dma_map_single(ring_to_dev(ring), ring->desc,
1674 size, DMA_BIDIRECTIONAL);
1675 if (dma_mapping_error(ring_to_dev(ring), ring->desc_dma_addr)) {
1676 ring->desc_dma_addr = 0;
1677 kfree(ring->desc);
1678 ring->desc = NULL;
1679 return -ENOMEM;
1680 }
1681
1682 return 0;
1683}
1684
1685static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
1686 struct hns3_desc_cb *cb)
1687{
1688 int ret;
1689
1690 ret = hns3_alloc_buffer(ring, cb);
1691 if (ret)
1692 goto out;
1693
1694 ret = hns3_map_buffer(ring, cb);
1695 if (ret)
1696 goto out_with_buf;
1697
1698 return 0;
1699
1700out_with_buf:
564883bb 1701 hns3_free_buffer(ring, cb);
76ad4f0e
S		 1702out:
1703 return ret;
1704}
1705
1706static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
1707{
1708 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
1709
1710 if (ret)
1711 return ret;
1712
1713 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
1714
1715 return 0;
1716}
1717
1718/* Allocate memory for raw pkg, and map with dma */
1719static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
1720{
1721 int i, j, ret;
1722
1723 for (i = 0; i < ring->desc_num; i++) {
1724 ret = hns3_alloc_buffer_attach(ring, i);
1725 if (ret)
1726 goto out_buffer_fail;
1727 }
1728
1729 return 0;
1730
1731out_buffer_fail:
1732 for (j = i - 1; j >= 0; j--)
1733 hns3_free_buffer_detach(ring, j);
1734 return ret;
1735}
1736
1737/* detach a in-used buffer and replace with a reserved one */
1738static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
1739 struct hns3_desc_cb *res_cb)
1740{
b9077428 1741 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 1742 ring->desc_cb[i] = *res_cb;
1743 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
1744}
1745
1746static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
1747{
1748 ring->desc_cb[i].reuse_flag = 0;
1749 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
1750 + ring->desc_cb[i].page_offset);
1751}
1752
1753static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
1754 int *pkts)
1755{
1756 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
1757
1758 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
1759 (*bytes) += desc_cb->length;
1760 /* desc_cb will be cleaned, after hnae_free_buffer_detach*/
1761 hns3_free_buffer_detach(ring, ring->next_to_clean);
1762
1763 ring_ptr_move_fw(ring, next_to_clean);
1764}
1765
1766static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
1767{
1768 int u = ring->next_to_use;
1769 int c = ring->next_to_clean;
1770
1771 if (unlikely(h > ring->desc_num))
1772 return 0;
1773
1774 return u > c ? (h > c && h <= u) : (h > c || h <= u);
1775}
1776
24e750c4 1777bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
76ad4f0e
S		 1778{
1779 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
1780 struct netdev_queue *dev_queue;
1781 int bytes, pkts;
1782 int head;
1783
1784 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
1785 rmb(); /* Make sure head is ready before touch any data */
1786
1787 if (is_ring_empty(ring) || head == ring->next_to_clean)
24e750c4 1788 return true; /* no data to poll */
76ad4f0e
S		 1789
1790 if (!is_valid_clean_head(ring, head)) {
1791 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
1792 ring->next_to_use, ring->next_to_clean);
1793
1794 u64_stats_update_begin(&ring->syncp);
1795 ring->stats.io_err_cnt++;
1796 u64_stats_update_end(&ring->syncp);
24e750c4 1797 return true;
76ad4f0e
S		 1798 }
1799
1800 bytes = 0;
1801 pkts = 0;
1802 while (head != ring->next_to_clean && budget) {
1803 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
1804 /* Issue prefetch for next Tx descriptor */
1805 prefetch(&ring->desc_cb[ring->next_to_clean]);
1806 budget--;
1807 }
1808
1809 ring->tqp_vector->tx_group.total_bytes += bytes;
1810 ring->tqp_vector->tx_group.total_packets += pkts;
1811
1812 u64_stats_update_begin(&ring->syncp);
1813 ring->stats.tx_bytes += bytes;
1814 ring->stats.tx_pkts += pkts;
1815 u64_stats_update_end(&ring->syncp);
1816
1817 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
1818 netdev_tx_completed_queue(dev_queue, pkts, bytes);
1819
1820 if (unlikely(pkts && netif_carrier_ok(netdev) &&
1821 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
1822 /* Make sure that anybody stopping the queue after this
1823 * sees the new next_to_clean.
1824 */
1825 smp_mb();
1826 if (netif_tx_queue_stopped(dev_queue)) {
1827 netif_tx_wake_queue(dev_queue);
1828 ring->stats.restart_queue++;
1829 }
1830 }
1831
1832 return !!budget;
1833}
1834
1835static int hns3_desc_unused(struct hns3_enet_ring *ring)
1836{
1837 int ntc = ring->next_to_clean;
1838 int ntu = ring->next_to_use;
1839
1840 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
1841}
1842
1843static void
1844hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
1845{
1846 struct hns3_desc_cb *desc_cb;
1847 struct hns3_desc_cb res_cbs;
1848 int i, ret;
1849
1850 for (i = 0; i < cleand_count; i++) {
1851 desc_cb = &ring->desc_cb[ring->next_to_use];
1852 if (desc_cb->reuse_flag) {
1853 u64_stats_update_begin(&ring->syncp);
1854 ring->stats.reuse_pg_cnt++;
1855 u64_stats_update_end(&ring->syncp);
1856
1857 hns3_reuse_buffer(ring, ring->next_to_use);
1858 } else {
1859 ret = hns3_reserve_buffer_map(ring, &res_cbs);
1860 if (ret) {
1861 u64_stats_update_begin(&ring->syncp);
1862 ring->stats.sw_err_cnt++;
1863 u64_stats_update_end(&ring->syncp);
1864
1865 netdev_err(ring->tqp->handle->kinfo.netdev,
1866 "hnae reserve buffer map failed.\n");
1867 break;
1868 }
1869 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
1870 }
1871
1872 ring_ptr_move_fw(ring, next_to_use);
1873 }
1874
1875 wmb(); /* Make all data has been write before submit */
1876 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
1877}
1878
1879/* hns3_nic_get_headlen - determine size of header for LRO/GRO
1880 * @data: pointer to the start of the headers
1881 * @max: total length of section to find headers in
1882 *
1883 * This function is meant to determine the length of headers that will
1884 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1885 * motivation of doing this is to only perform one pull for IPv4 TCP
1886 * packets so that we can do basic things like calculating the gso_size
1887 * based on the average data per packet.
1888 */
1889static unsigned int hns3_nic_get_headlen(unsigned char *data, u32 flag,
1890 unsigned int max_size)
1891{
1892 unsigned char *network;
1893 u8 hlen;
1894
1895 /* This should never happen, but better safe than sorry */
1896 if (max_size < ETH_HLEN)
1897 return max_size;
1898
1899 /* Initialize network frame pointer */
1900 network = data;
1901
1902 /* Set first protocol and move network header forward */
1903 network += ETH_HLEN;
1904
1905 /* Handle any vlan tag if present */
1906 if (hnae_get_field(flag, HNS3_RXD_VLAN_M, HNS3_RXD_VLAN_S)
1907 == HNS3_RX_FLAG_VLAN_PRESENT) {
1908 if ((typeof(max_size))(network - data) > (max_size - VLAN_HLEN))
1909 return max_size;
1910
1911 network += VLAN_HLEN;
1912 }
1913
1914 /* Handle L3 protocols */
1915 if (hnae_get_field(flag, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S)
1916 == HNS3_RX_FLAG_L3ID_IPV4) {
1917 if ((typeof(max_size))(network - data) >
1918 (max_size - sizeof(struct iphdr)))
1919 return max_size;
1920
1921 /* Access ihl as a u8 to avoid unaligned access on ia64 */
1922 hlen = (network[0] & 0x0F) << 2;
1923
1924 /* Verify hlen meets minimum size requirements */
1925 if (hlen < sizeof(struct iphdr))
1926 return network - data;
1927
1928 /* Record next protocol if header is present */
1929 } else if (hnae_get_field(flag, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S)
1930 == HNS3_RX_FLAG_L3ID_IPV6) {
1931 if ((typeof(max_size))(network - data) >
1932 (max_size - sizeof(struct ipv6hdr)))
1933 return max_size;
1934
1935 /* Record next protocol */
1936 hlen = sizeof(struct ipv6hdr);
1937 } else {
1938 return network - data;
1939 }
1940
1941 /* Relocate pointer to start of L4 header */
1942 network += hlen;
1943
1944 /* Finally sort out TCP/UDP */
1945 if (hnae_get_field(flag, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S)
1946 == HNS3_RX_FLAG_L4ID_TCP) {
1947 if ((typeof(max_size))(network - data) >
1948 (max_size - sizeof(struct tcphdr)))
1949 return max_size;
1950
1951 /* Access doff as a u8 to avoid unaligned access on ia64 */
1952 hlen = (network[12] & 0xF0) >> 2;
1953
1954 /* Verify hlen meets minimum size requirements */
1955 if (hlen < sizeof(struct tcphdr))
1956 return network - data;
1957
1958 network += hlen;
1959 } else if (hnae_get_field(flag, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S)
1960 == HNS3_RX_FLAG_L4ID_UDP) {
1961 if ((typeof(max_size))(network - data) >
1962 (max_size - sizeof(struct udphdr)))
1963 return max_size;
1964
1965 network += sizeof(struct udphdr);
1966 }
1967
1968 /* If everything has gone correctly network should be the
1969 * data section of the packet and will be the end of the header.
1970 * If not then it probably represents the end of the last recognized
1971 * header.
1972 */
1973 if ((typeof(max_size))(network - data) < max_size)
1974 return network - data;
1975 else
1976 return max_size;
1977}
1978
1979static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
1980 struct hns3_enet_ring *ring, int pull_len,
1981 struct hns3_desc_cb *desc_cb)
1982{
1983 struct hns3_desc *desc;
1984 int truesize, size;
1985 int last_offset;
1986 bool twobufs;
1987
1988 twobufs = ((PAGE_SIZE < 8192) &&
1989 hnae_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
1990
1991 desc = &ring->desc[ring->next_to_clean];
1992 size = le16_to_cpu(desc->rx.size);
1993
f8d291f0
PL		 1994 truesize = hnae_buf_size(ring);
1995
1996 if (!twobufs)
76ad4f0e 1997 last_offset = hnae_page_size(ring) - hnae_buf_size(ring);
76ad4f0e
S		 1998
1999 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2000 size - pull_len, truesize);
76ad4f0e
S		 2001
2002 /* Avoid re-using remote pages,flag default unreuse */
2003 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2004 return;
2005
2006 if (twobufs) {
2007 /* If we are only owner of page we can reuse it */
2008 if (likely(page_count(desc_cb->priv) == 1)) {
2009 /* Flip page offset to other buffer */
2010 desc_cb->page_offset ^= truesize;
2011
2012 desc_cb->reuse_flag = 1;
2013 /* bump ref count on page before it is given*/
2014 get_page(desc_cb->priv);
2015 }
2016 return;
2017 }
2018
2019 /* Move offset up to the next cache line */
2020 desc_cb->page_offset += truesize;
2021
2022 if (desc_cb->page_offset <= last_offset) {
2023 desc_cb->reuse_flag = 1;
2024 /* Bump ref count on page before it is given*/
2025 get_page(desc_cb->priv);
2026 }
2027}
2028
2029static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2030 struct hns3_desc *desc)
2031{
2032 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2033 int l3_type, l4_type;
2034 u32 bd_base_info;
2035 int ol4_type;
2036 u32 l234info;
2037
2038 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2039 l234info = le32_to_cpu(desc->rx.l234_info);
2040
2041 skb->ip_summed = CHECKSUM_NONE;
2042
2043 skb_checksum_none_assert(skb);
2044
2045 if (!(netdev->features & NETIF_F_RXCSUM))
2046 return;
2047
2048 /* check if hardware has done checksum */
2049 if (!hnae_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
2050 return;
2051
2052 if (unlikely(hnae_get_bit(l234info, HNS3_RXD_L3E_B) ||
2053 hnae_get_bit(l234info, HNS3_RXD_L4E_B) ||
2054 hnae_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2055 hnae_get_bit(l234info, HNS3_RXD_OL4E_B))) {
2056 netdev_err(netdev, "L3/L4 error pkt\n");
2057 u64_stats_update_begin(&ring->syncp);
2058 ring->stats.l3l4_csum_err++;
2059 u64_stats_update_end(&ring->syncp);
2060
2061 return;
2062 }
2063
2064 l3_type = hnae_get_field(l234info, HNS3_RXD_L3ID_M,
2065 HNS3_RXD_L3ID_S);
2066 l4_type = hnae_get_field(l234info, HNS3_RXD_L4ID_M,
2067 HNS3_RXD_L4ID_S);
2068
2069 ol4_type = hnae_get_field(l234info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
2070 switch (ol4_type) {
2071 case HNS3_OL4_TYPE_MAC_IN_UDP:
2072 case HNS3_OL4_TYPE_NVGRE:
2073 skb->csum_level = 1;
2074 case HNS3_OL4_TYPE_NO_TUN:
2075 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2076 if (l3_type == HNS3_L3_TYPE_IPV4 ||
2077 (l3_type == HNS3_L3_TYPE_IPV6 &&
2078 (l4_type == HNS3_L4_TYPE_UDP ||
2079 l4_type == HNS3_L4_TYPE_TCP ||
2080 l4_type == HNS3_L4_TYPE_SCTP)))
2081 skb->ip_summed = CHECKSUM_UNNECESSARY;
2082 break;
2083 }
2084}
2085
d43e5aca
YL		 2086static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2087{
2088 napi_gro_receive(&ring->tqp_vector->napi, skb);
2089}
2090
76ad4f0e
S		 2091static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2092 struct sk_buff **out_skb, int *out_bnum)
2093{
2094 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2095 struct hns3_desc_cb *desc_cb;
2096 struct hns3_desc *desc;
2097 struct sk_buff *skb;
2098 unsigned char *va;
2099 u32 bd_base_info;
2100 int pull_len;
2101 u32 l234info;
2102 int length;
2103 int bnum;
2104
2105 desc = &ring->desc[ring->next_to_clean];
2106 desc_cb = &ring->desc_cb[ring->next_to_clean];
2107
2108 prefetch(desc);
2109
2110 length = le16_to_cpu(desc->rx.pkt_len);
2111 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2112 l234info = le32_to_cpu(desc->rx.l234_info);
2113
2114 /* Check valid BD */
2115 if (!hnae_get_bit(bd_base_info, HNS3_RXD_VLD_B))
2116 return -EFAULT;
2117
2118 va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
2119
2120 /* Prefetch first cache line of first page
2121 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2122 * line size is 64B so need to prefetch twice to make it 128B. But in
2123 * actual we can have greater size of caches with 128B Level 1 cache
2124 * lines. In such a case, single fetch would suffice to cache in the
2125 * relevant part of the header.
2126 */
2127 prefetch(va);
2128#if L1_CACHE_BYTES < 128
2129 prefetch(va + L1_CACHE_BYTES);
2130#endif
2131
2132 skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2133 HNS3_RX_HEAD_SIZE);
2134 if (unlikely(!skb)) {
2135 netdev_err(netdev, "alloc rx skb fail\n");
2136
2137 u64_stats_update_begin(&ring->syncp);
2138 ring->stats.sw_err_cnt++;
2139 u64_stats_update_end(&ring->syncp);
2140
2141 return -ENOMEM;
2142 }
2143
2144 prefetchw(skb->data);
2145
9699cffe
PL		 2146 /* Based on hw strategy, the tag offloaded will be stored at
2147 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2148 * in one layer tag case.
2149 */
2150 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2151 u16 vlan_tag;
2152
2153 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2154 if (!(vlan_tag & VLAN_VID_MASK))
2155 vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2156 if (vlan_tag & VLAN_VID_MASK)
2157 __vlan_hwaccel_put_tag(skb,
2158 htons(ETH_P_8021Q),
2159 vlan_tag);
2160 }
2161
76ad4f0e
S		 2162 bnum = 1;
2163 if (length <= HNS3_RX_HEAD_SIZE) {
2164 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2165
2166 /* We can reuse buffer as-is, just make sure it is local */
2167 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2168 desc_cb->reuse_flag = 1;
2169 else /* This page cannot be reused so discard it */
2170 put_page(desc_cb->priv);
2171
2172 ring_ptr_move_fw(ring, next_to_clean);
2173 } else {
2174 u64_stats_update_begin(&ring->syncp);
2175 ring->stats.seg_pkt_cnt++;
2176 u64_stats_update_end(&ring->syncp);
2177
2178 pull_len = hns3_nic_get_headlen(va, l234info,
2179 HNS3_RX_HEAD_SIZE);
2180 memcpy(__skb_put(skb, pull_len), va,
2181 ALIGN(pull_len, sizeof(long)));
2182
2183 hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb);
2184 ring_ptr_move_fw(ring, next_to_clean);
2185
2186 while (!hnae_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2187 desc = &ring->desc[ring->next_to_clean];
2188 desc_cb = &ring->desc_cb[ring->next_to_clean];
2189 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2190 hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb);
2191 ring_ptr_move_fw(ring, next_to_clean);
2192 bnum++;
2193 }
2194 }
2195
2196 *out_bnum = bnum;
2197
2198 if (unlikely(!hnae_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
2199 netdev_err(netdev, "no valid bd,%016llx,%016llx\n",
2200 ((u64 *)desc)[0], ((u64 *)desc)[1]);
2201 u64_stats_update_begin(&ring->syncp);
2202 ring->stats.non_vld_descs++;
2203 u64_stats_update_end(&ring->syncp);
2204
2205 dev_kfree_skb_any(skb);
2206 return -EINVAL;
2207 }
2208
2209 if (unlikely((!desc->rx.pkt_len) ||
2210 hnae_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
2211 netdev_err(netdev, "truncated pkt\n");
2212 u64_stats_update_begin(&ring->syncp);
2213 ring->stats.err_pkt_len++;
2214 u64_stats_update_end(&ring->syncp);
2215
2216 dev_kfree_skb_any(skb);
2217 return -EFAULT;
2218 }
2219
2220 if (unlikely(hnae_get_bit(l234info, HNS3_RXD_L2E_B))) {
2221 netdev_err(netdev, "L2 error pkt\n");
2222 u64_stats_update_begin(&ring->syncp);
2223 ring->stats.l2_err++;
2224 u64_stats_update_end(&ring->syncp);
2225
2226 dev_kfree_skb_any(skb);
2227 return -EFAULT;
2228 }
2229
2230 u64_stats_update_begin(&ring->syncp);
2231 ring->stats.rx_pkts++;
2232 ring->stats.rx_bytes += skb->len;
2233 u64_stats_update_end(&ring->syncp);
2234
2235 ring->tqp_vector->rx_group.total_bytes += skb->len;
2236
2237 hns3_rx_checksum(ring, skb, desc);
2238 return 0;
2239}
2240
d43e5aca
YL		 2241int hns3_clean_rx_ring(
2242 struct hns3_enet_ring *ring, int budget,
2243 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2244{
2245#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2246 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2247 int recv_pkts, recv_bds, clean_count, err;
2248 int unused_count = hns3_desc_unused(ring);
2249 struct sk_buff *skb = NULL;
2250 int num, bnum = 0;
2251
2252 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2253 rmb(); /* Make sure num taken effect before the other data is touched */
2254
2255 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2256 num -= unused_count;
2257
2258 while (recv_pkts < budget && recv_bds < num) {
2259 /* Reuse or realloc buffers */
2260 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2261 hns3_nic_alloc_rx_buffers(ring,
2262 clean_count + unused_count);
2263 clean_count = 0;
2264 unused_count = hns3_desc_unused(ring);
2265 }
2266
2267 /* Poll one pkt */
2268 err = hns3_handle_rx_bd(ring, &skb, &bnum);
2269 if (unlikely(!skb)) /* This fault cannot be repaired */
2270 goto out;
2271
2272 recv_bds += bnum;
2273 clean_count += bnum;
2274 if (unlikely(err)) { /* Do jump the err */
2275 recv_pkts++;
2276 continue;
2277 }
2278
2279 /* Do update ip stack process */
2280 skb->protocol = eth_type_trans(skb, netdev);
d43e5aca 2281 rx_fn(ring, skb);
76ad4f0e
S		 2282
2283 recv_pkts++;
2284 }
2285
2286out:
2287 /* Make all data has been write before submit */
2288 if (clean_count + unused_count > 0)
2289 hns3_nic_alloc_rx_buffers(ring,
2290 clean_count + unused_count);
2291
2292 return recv_pkts;
2293}
2294
2295static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2296{
a95e1f86
FL		 2297 struct hns3_enet_tqp_vector *tqp_vector =
2298 ring_group->ring->tqp_vector;
76ad4f0e 2299 enum hns3_flow_level_range new_flow_level;
a95e1f86
FL		 2300 int packets_per_msecs;
2301 int bytes_per_msecs;
2302 u32 time_passed_ms;
76ad4f0e 2303 u16 new_int_gl;
76ad4f0e 2304
a95e1f86 2305 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies)
76ad4f0e
S		 2306 return false;
2307
2308 if (ring_group->total_packets == 0) {
9bc727a9
YL		 2309 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2310 ring_group->coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 2311 return true;
2312 }
2313
2314 /* Simple throttlerate management
2315 * 0-10MB/s lower (50000 ints/s)
2316 * 10-20MB/s middle (20000 ints/s)
2317 * 20-1249MB/s high (18000 ints/s)
2318 * > 40000pps ultra (8000 ints/s)
2319 */
9bc727a9
YL		 2320 new_flow_level = ring_group->coal.flow_level;
2321 new_int_gl = ring_group->coal.int_gl;
a95e1f86
FL		 2322 time_passed_ms =
2323 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2324
2325 if (!time_passed_ms)
2326 return false;
2327
2328 do_div(ring_group->total_packets, time_passed_ms);
2329 packets_per_msecs = ring_group->total_packets;
2330
2331 do_div(ring_group->total_bytes, time_passed_ms);
2332 bytes_per_msecs = ring_group->total_bytes;
2333
2334#define HNS3_RX_LOW_BYTE_RATE 10000
2335#define HNS3_RX_MID_BYTE_RATE 20000
76ad4f0e
S		 2336
2337 switch (new_flow_level) {
2338 case HNS3_FLOW_LOW:
a95e1f86 2339 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2340 new_flow_level = HNS3_FLOW_MID;
2341 break;
2342 case HNS3_FLOW_MID:
a95e1f86 2343 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2344 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 2345 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2346 new_flow_level = HNS3_FLOW_LOW;
2347 break;
2348 case HNS3_FLOW_HIGH:
2349 case HNS3_FLOW_ULTRA:
2350 default:
a95e1f86 2351 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2352 new_flow_level = HNS3_FLOW_MID;
2353 break;
2354 }
2355
a95e1f86
FL		 2356#define HNS3_RX_ULTRA_PACKET_RATE 40
2357
2358 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2359 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 2360 new_flow_level = HNS3_FLOW_ULTRA;
2361
2362 switch (new_flow_level) {
2363 case HNS3_FLOW_LOW:
2364 new_int_gl = HNS3_INT_GL_50K;
2365 break;
2366 case HNS3_FLOW_MID:
2367 new_int_gl = HNS3_INT_GL_20K;
2368 break;
2369 case HNS3_FLOW_HIGH:
2370 new_int_gl = HNS3_INT_GL_18K;
2371 break;
2372 case HNS3_FLOW_ULTRA:
2373 new_int_gl = HNS3_INT_GL_8K;
2374 break;
2375 default:
2376 break;
2377 }
2378
2379 ring_group->total_bytes = 0;
2380 ring_group->total_packets = 0;
9bc727a9
YL		 2381 ring_group->coal.flow_level = new_flow_level;
2382 if (new_int_gl != ring_group->coal.int_gl) {
2383 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 2384 return true;
2385 }
2386 return false;
2387}
2388
2389static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2390{
8b1ff1ea
FL		 2391 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2392 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2393 bool rx_update, tx_update;
2394
cd9d187b
FL		 2395 if (tqp_vector->int_adapt_down > 0) {
2396 tqp_vector->int_adapt_down--;
2397 return;
2398 }
2399
9bc727a9 2400 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 2401 rx_update = hns3_get_new_int_gl(rx_group);
2402 if (rx_update)
2403 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 2404 rx_group->coal.int_gl);
8b1ff1ea
FL		 2405 }
2406
9bc727a9 2407 if (tx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 2408 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2409 if (tx_update)
2410 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 2411 tx_group->coal.int_gl);
76ad4f0e 2412 }
cd9d187b 2413
a95e1f86 2414 tqp_vector->last_jiffies = jiffies;
cd9d187b 2415 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
76ad4f0e
S		 2416}
2417
2418static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2419{
2420 struct hns3_enet_ring *ring;
2421 int rx_pkt_total = 0;
2422
2423 struct hns3_enet_tqp_vector *tqp_vector =
2424 container_of(napi, struct hns3_enet_tqp_vector, napi);
2425 bool clean_complete = true;
2426 int rx_budget;
2427
2428 /* Since the actual Tx work is minimal, we can give the Tx a larger
2429 * budget and be more aggressive about cleaning up the Tx descriptors.
2430 */
2431 hns3_for_each_ring(ring, tqp_vector->tx_group) {
2432 if (!hns3_clean_tx_ring(ring, budget))
2433 clean_complete = false;
2434 }
2435
2436 /* make sure rx ring budget not smaller than 1 */
2437 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2438
2439 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 2440 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2441 hns3_rx_skb);
76ad4f0e
S		 2442
2443 if (rx_cleaned >= rx_budget)
2444 clean_complete = false;
2445
2446 rx_pkt_total += rx_cleaned;
2447 }
2448
2449 tqp_vector->rx_group.total_packets += rx_pkt_total;
2450
2451 if (!clean_complete)
2452 return budget;
2453
2454 napi_complete(napi);
2455 hns3_update_new_int_gl(tqp_vector);
2456 hns3_mask_vector_irq(tqp_vector, 1);
2457
2458 return rx_pkt_total;
2459}
2460
2461static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2462 struct hnae3_ring_chain_node *head)
2463{
2464 struct pci_dev *pdev = tqp_vector->handle->pdev;
2465 struct hnae3_ring_chain_node *cur_chain = head;
2466 struct hnae3_ring_chain_node *chain;
2467 struct hns3_enet_ring *tx_ring;
2468 struct hns3_enet_ring *rx_ring;
2469
2470 tx_ring = tqp_vector->tx_group.ring;
2471 if (tx_ring) {
2472 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
2473 hnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2474 HNAE3_RING_TYPE_TX);
11af96a4
FL		 2475 hnae_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2476 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 2477
2478 cur_chain->next = NULL;
2479
2480 while (tx_ring->next) {
2481 tx_ring = tx_ring->next;
2482
2483 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2484 GFP_KERNEL);
2485 if (!chain)
2486 return -ENOMEM;
2487
2488 cur_chain->next = chain;
2489 chain->tqp_index = tx_ring->tqp->tqp_index;
2490 hnae_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2491 HNAE3_RING_TYPE_TX);
11af96a4
FL		 2492 hnae_set_field(chain->int_gl_idx,
2493 HNAE3_RING_GL_IDX_M,
2494 HNAE3_RING_GL_IDX_S,
2495 HNAE3_RING_GL_TX);
76ad4f0e
S		 2496
2497 cur_chain = chain;
2498 }
2499 }
2500
2501 rx_ring = tqp_vector->rx_group.ring;
2502 if (!tx_ring && rx_ring) {
2503 cur_chain->next = NULL;
2504 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
2505 hnae_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2506 HNAE3_RING_TYPE_RX);
11af96a4
FL		 2507 hnae_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2508 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 2509
2510 rx_ring = rx_ring->next;
2511 }
2512
2513 while (rx_ring) {
2514 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
2515 if (!chain)
2516 return -ENOMEM;
2517
2518 cur_chain->next = chain;
2519 chain->tqp_index = rx_ring->tqp->tqp_index;
2520 hnae_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2521 HNAE3_RING_TYPE_RX);
11af96a4
FL		 2522 hnae_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2523 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
2524
76ad4f0e
S		 2525 cur_chain = chain;
2526
2527 rx_ring = rx_ring->next;
2528 }
2529
2530 return 0;
2531}
2532
2533static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2534 struct hnae3_ring_chain_node *head)
2535{
2536 struct pci_dev *pdev = tqp_vector->handle->pdev;
2537 struct hnae3_ring_chain_node *chain_tmp, *chain;
2538
2539 chain = head->next;
2540
2541 while (chain) {
2542 chain_tmp = chain->next;
2543 devm_kfree(&pdev->dev, chain);
2544 chain = chain_tmp;
2545 }
2546}
2547
2548static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
2549 struct hns3_enet_ring *ring)
2550{
2551 ring->next = group->ring;
2552 group->ring = ring;
2553
2554 group->count++;
2555}
2556
2557static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
2558{
2559 struct hnae3_ring_chain_node vector_ring_chain;
2560 struct hnae3_handle *h = priv->ae_handle;
2561 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 2562 int ret = 0;
2563 u16 i;
2564
dd38c726
YL		 2565 for (i = 0; i < priv->vector_num; i++) {
2566 tqp_vector = &priv->tqp_vector[i];
2567 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
2568 tqp_vector->num_tqps = 0;
2569 }
76ad4f0e 2570
dd38c726
YL		 2571 for (i = 0; i < h->kinfo.num_tqps; i++) {
2572 u16 vector_i = i % priv->vector_num;
2573 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 2574
2575 tqp_vector = &priv->tqp_vector[vector_i];
2576
2577 hns3_add_ring_to_group(&tqp_vector->tx_group,
2578 priv->ring_data[i].ring);
2579
2580 hns3_add_ring_to_group(&tqp_vector->rx_group,
2581 priv->ring_data[i + tqp_num].ring);
2582
76ad4f0e
S		 2583 priv->ring_data[i].ring->tqp_vector = tqp_vector;
2584 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
dd38c726 2585 tqp_vector->num_tqps++;
76ad4f0e
S		 2586 }
2587
dd38c726 2588 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 2589 tqp_vector = &priv->tqp_vector[i];
2590
2591 tqp_vector->rx_group.total_bytes = 0;
2592 tqp_vector->rx_group.total_packets = 0;
2593 tqp_vector->tx_group.total_bytes = 0;
2594 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 2595 tqp_vector->handle = h;
2596
2597 ret = hns3_get_vector_ring_chain(tqp_vector,
2598 &vector_ring_chain);
2599 if (ret)
dd38c726 2600 return ret;
76ad4f0e
S		 2601
2602 ret = h->ae_algo->ops->map_ring_to_vector(h,
2603 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 2604
2605 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2606
dd38c726
YL		 2607 if (ret)
2608 return ret;
2609
76ad4f0e
S		 2610 netif_napi_add(priv->netdev, &tqp_vector->napi,
2611 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
2612 }
2613
dd38c726
YL		 2614 return 0;
2615}
2616
2617static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
2618{
2619 struct hnae3_handle *h = priv->ae_handle;
2620 struct hns3_enet_tqp_vector *tqp_vector;
2621 struct hnae3_vector_info *vector;
2622 struct pci_dev *pdev = h->pdev;
2623 u16 tqp_num = h->kinfo.num_tqps;
2624 u16 vector_num;
2625 int ret = 0;
2626 u16 i;
2627
2628 /* RSS size, cpu online and vector_num should be the same */
2629 /* Should consider 2p/4p later */
2630 vector_num = min_t(u16, num_online_cpus(), tqp_num);
2631 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
2632 GFP_KERNEL);
2633 if (!vector)
2634 return -ENOMEM;
2635
2636 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
2637
2638 priv->vector_num = vector_num;
2639 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
2640 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
2641 GFP_KERNEL);
2642 if (!priv->tqp_vector) {
2643 ret = -ENOMEM;
2644 goto out;
2645 }
2646
2647 for (i = 0; i < priv->vector_num; i++) {
2648 tqp_vector = &priv->tqp_vector[i];
2649 tqp_vector->idx = i;
2650 tqp_vector->mask_addr = vector[i].io_addr;
2651 tqp_vector->vector_irq = vector[i].vector;
2652 hns3_vector_gl_rl_init(tqp_vector, priv);
2653 }
2654
76ad4f0e
S		 2655out:
2656 devm_kfree(&pdev->dev, vector);
2657 return ret;
2658}
2659
dd38c726
YL		 2660static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
2661{
2662 group->ring = NULL;
2663 group->count = 0;
2664}
2665
76ad4f0e
S		 2666static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
2667{
2668 struct hnae3_ring_chain_node vector_ring_chain;
2669 struct hnae3_handle *h = priv->ae_handle;
2670 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 2671 int i, ret;
2672
2673 for (i = 0; i < priv->vector_num; i++) {
2674 tqp_vector = &priv->tqp_vector[i];
2675
2676 ret = hns3_get_vector_ring_chain(tqp_vector,
2677 &vector_ring_chain);
2678 if (ret)
2679 return ret;
2680
2681 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
2682 tqp_vector->vector_irq, &vector_ring_chain);
2683 if (ret)
2684 return ret;
2685
0d3e6631
YL		 2686 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
2687 if (ret)
2688 return ret;
2689
76ad4f0e
S		 2690 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2691
2692 if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) {
2693 (void)irq_set_affinity_hint(
2694 priv->tqp_vector[i].vector_irq,
2695 NULL);
ae064e61 2696 free_irq(priv->tqp_vector[i].vector_irq,
2697 &priv->tqp_vector[i]);
76ad4f0e
S		 2698 }
2699
2700 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
dd38c726
YL		 2701 hns3_clear_ring_group(&tqp_vector->rx_group);
2702 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 2703 netif_napi_del(&priv->tqp_vector[i].napi);
2704 }
2705
dd38c726
YL		 2706 return 0;
2707}
2708
2709static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
2710{
2711 struct hnae3_handle *h = priv->ae_handle;
2712 struct pci_dev *pdev = h->pdev;
2713 int i, ret;
2714
2715 for (i = 0; i < priv->vector_num; i++) {
2716 struct hns3_enet_tqp_vector *tqp_vector;
2717
2718 tqp_vector = &priv->tqp_vector[i];
2719 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
2720 if (ret)
2721 return ret;
2722 }
76ad4f0e 2723
dd38c726 2724 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 2725 return 0;
2726}
2727
2728static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
2729 int ring_type)
2730{
2731 struct hns3_nic_ring_data *ring_data = priv->ring_data;
2732 int queue_num = priv->ae_handle->kinfo.num_tqps;
2733 struct pci_dev *pdev = priv->ae_handle->pdev;
2734 struct hns3_enet_ring *ring;
2735
2736 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
2737 if (!ring)
2738 return -ENOMEM;
2739
2740 if (ring_type == HNAE3_RING_TYPE_TX) {
2741 ring_data[q->tqp_index].ring = ring;
66b44730 2742 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 2743 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
2744 } else {
2745 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 2746 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 2747 ring->io_base = q->io_base;
2748 }
2749
2750 hnae_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
2751
76ad4f0e
S		 2752 ring->tqp = q;
2753 ring->desc = NULL;
2754 ring->desc_cb = NULL;
2755 ring->dev = priv->dev;
2756 ring->desc_dma_addr = 0;
2757 ring->buf_size = q->buf_size;
2758 ring->desc_num = q->desc_num;
2759 ring->next_to_use = 0;
2760 ring->next_to_clean = 0;
2761
2762 return 0;
2763}
2764
2765static int hns3_queue_to_ring(struct hnae3_queue *tqp,
2766 struct hns3_nic_priv *priv)
2767{
2768 int ret;
2769
2770 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
2771 if (ret)
2772 return ret;
2773
2774 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
2775 if (ret)
2776 return ret;
2777
2778 return 0;
2779}
2780
2781static int hns3_get_ring_config(struct hns3_nic_priv *priv)
2782{
2783 struct hnae3_handle *h = priv->ae_handle;
2784 struct pci_dev *pdev = h->pdev;
2785 int i, ret;
2786
2787 priv->ring_data = devm_kzalloc(&pdev->dev, h->kinfo.num_tqps *
2788 sizeof(*priv->ring_data) * 2,
2789 GFP_KERNEL);
2790 if (!priv->ring_data)
2791 return -ENOMEM;
2792
2793 for (i = 0; i < h->kinfo.num_tqps; i++) {
2794 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
2795 if (ret)
2796 goto err;
2797 }
2798
2799 return 0;
2800err:
2801 devm_kfree(&pdev->dev, priv->ring_data);
2802 return ret;
2803}
2804
09f2af64
PL		 2805static void hns3_put_ring_config(struct hns3_nic_priv *priv)
2806{
2807 struct hnae3_handle *h = priv->ae_handle;
2808 int i;
2809
2810 for (i = 0; i < h->kinfo.num_tqps; i++) {
2811 devm_kfree(priv->dev, priv->ring_data[i].ring);
2812 devm_kfree(priv->dev,
2813 priv->ring_data[i + h->kinfo.num_tqps].ring);
2814 }
2815 devm_kfree(priv->dev, priv->ring_data);
2816}
2817
76ad4f0e
S		 2818static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
2819{
2820 int ret;
2821
2822 if (ring->desc_num <= 0 || ring->buf_size <= 0)
2823 return -EINVAL;
2824
2825 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
2826 GFP_KERNEL);
2827 if (!ring->desc_cb) {
2828 ret = -ENOMEM;
2829 goto out;
2830 }
2831
2832 ret = hns3_alloc_desc(ring);
2833 if (ret)
2834 goto out_with_desc_cb;
2835
2836 if (!HNAE3_IS_TX_RING(ring)) {
2837 ret = hns3_alloc_ring_buffers(ring);
2838 if (ret)
2839 goto out_with_desc;
2840 }
2841
2842 return 0;
2843
2844out_with_desc:
2845 hns3_free_desc(ring);
2846out_with_desc_cb:
2847 kfree(ring->desc_cb);
2848 ring->desc_cb = NULL;
2849out:
2850 return ret;
2851}
2852
2853static void hns3_fini_ring(struct hns3_enet_ring *ring)
2854{
2855 hns3_free_desc(ring);
2856 kfree(ring->desc_cb);
2857 ring->desc_cb = NULL;
2858 ring->next_to_clean = 0;
2859 ring->next_to_use = 0;
2860}
2861
1db9b1bf 2862static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 2863{
2864 int bd_size_type;
2865
2866 switch (buf_size) {
2867 case 512:
2868 bd_size_type = HNS3_BD_SIZE_512_TYPE;
2869 break;
2870 case 1024:
2871 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
2872 break;
2873 case 2048:
2874 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
2875 break;
2876 case 4096:
2877 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
2878 break;
2879 default:
2880 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
2881 }
2882
2883 return bd_size_type;
2884}
2885
2886static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
2887{
2888 dma_addr_t dma = ring->desc_dma_addr;
2889 struct hnae3_queue *q = ring->tqp;
2890
2891 if (!HNAE3_IS_TX_RING(ring)) {
2892 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
2893 (u32)dma);
2894 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
2895 (u32)((dma >> 31) >> 1));
2896
2897 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
2898 hns3_buf_size2type(ring->buf_size));
2899 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
2900 ring->desc_num / 8 - 1);
2901
2902 } else {
2903 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
2904 (u32)dma);
2905 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
2906 (u32)((dma >> 31) >> 1));
2907
2908 hns3_write_dev(q, HNS3_RING_TX_RING_BD_LEN_REG,
2909 hns3_buf_size2type(ring->buf_size));
2910 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
2911 ring->desc_num / 8 - 1);
2912 }
2913}
2914
5668abda 2915int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 2916{
2917 struct hnae3_handle *h = priv->ae_handle;
2918 int ring_num = h->kinfo.num_tqps * 2;
2919 int i, j;
2920 int ret;
2921
2922 for (i = 0; i < ring_num; i++) {
2923 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
2924 if (ret) {
2925 dev_err(priv->dev,
2926 "Alloc ring memory fail! ret=%d\n", ret);
2927 goto out_when_alloc_ring_memory;
2928 }
2929
2930 hns3_init_ring_hw(priv->ring_data[i].ring);
2931
2932 u64_stats_init(&priv->ring_data[i].ring->syncp);
2933 }
2934
2935 return 0;
2936
2937out_when_alloc_ring_memory:
2938 for (j = i - 1; j >= 0; j--)
ee83f776 2939 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 2940
2941 return -ENOMEM;
2942}
2943
5668abda 2944int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 2945{
2946 struct hnae3_handle *h = priv->ae_handle;
2947 int i;
2948
2949 for (i = 0; i < h->kinfo.num_tqps; i++) {
2950 if (h->ae_algo->ops->reset_queue)
2951 h->ae_algo->ops->reset_queue(h, i);
2952
2953 hns3_fini_ring(priv->ring_data[i].ring);
2954 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
2955 }
76ad4f0e
S		 2956 return 0;
2957}
2958
2959/* Set mac addr if it is configured. or leave it to the AE driver */
f09555ff 2960static void hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 2961{
2962 struct hns3_nic_priv *priv = netdev_priv(netdev);
2963 struct hnae3_handle *h = priv->ae_handle;
2964 u8 mac_addr_temp[ETH_ALEN];
2965
f09555ff 2966 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 2967 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
2968 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
2969 }
2970
2971 /* Check if the MAC address is valid, if not get a random one */
2972 if (!is_valid_ether_addr(netdev->dev_addr)) {
2973 eth_hw_addr_random(netdev);
2974 dev_warn(priv->dev, "using random MAC address %pM\n",
2975 netdev->dev_addr);
76ad4f0e 2976 }
139e8792
L		 2977
2978 if (h->ae_algo->ops->set_mac_addr)
59098055 2979 h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 2980
76ad4f0e
S		 2981}
2982
2983static void hns3_nic_set_priv_ops(struct net_device *netdev)
2984{
2985 struct hns3_nic_priv *priv = netdev_priv(netdev);
2986
2987 if ((netdev->features & NETIF_F_TSO) ||
2988 (netdev->features & NETIF_F_TSO6)) {
2989 priv->ops.fill_desc = hns3_fill_desc_tso;
2990 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
2991 } else {
2992 priv->ops.fill_desc = hns3_fill_desc;
2993 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
2994 }
2995}
2996
2997static int hns3_client_init(struct hnae3_handle *handle)
2998{
2999 struct pci_dev *pdev = handle->pdev;
3000 struct hns3_nic_priv *priv;
3001 struct net_device *netdev;
3002 int ret;
3003
3004 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv),
678335a1 3005 hns3_get_max_available_channels(handle));
76ad4f0e
S		 3006 if (!netdev)
3007 return -ENOMEM;
3008
3009 priv = netdev_priv(netdev);
3010 priv->dev = &pdev->dev;
3011 priv->netdev = netdev;
3012 priv->ae_handle = handle;
6d4c3981
SM		 3013 priv->ae_handle->reset_level = HNAE3_NONE_RESET;
3014 priv->ae_handle->last_reset_time = jiffies;
f8fa222c 3015 priv->tx_timeout_count = 0;
76ad4f0e
S		 3016
3017 handle->kinfo.netdev = netdev;
3018 handle->priv = (void *)priv;
3019
f09555ff 3020 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3021
3022 hns3_set_default_feature(netdev);
3023
3024 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3025 netdev->priv_flags |= IFF_UNICAST_FLT;
3026 netdev->netdev_ops = &hns3_nic_netdev_ops;
3027 SET_NETDEV_DEV(netdev, &pdev->dev);
3028 hns3_ethtool_set_ops(netdev);
3029 hns3_nic_set_priv_ops(netdev);
3030
3031 /* Carrier off reporting is important to ethtool even BEFORE open */
3032 netif_carrier_off(netdev);
3033
3034 ret = hns3_get_ring_config(priv);
3035 if (ret) {
3036 ret = -ENOMEM;
3037 goto out_get_ring_cfg;
3038 }
3039
dd38c726
YL		 3040 ret = hns3_nic_alloc_vector_data(priv);
3041 if (ret) {
3042 ret = -ENOMEM;
3043 goto out_alloc_vector_data;
3044 }
3045
76ad4f0e
S		 3046 ret = hns3_nic_init_vector_data(priv);
3047 if (ret) {
3048 ret = -ENOMEM;
3049 goto out_init_vector_data;
3050 }
3051
3052 ret = hns3_init_all_ring(priv);
3053 if (ret) {
3054 ret = -ENOMEM;
3055 goto out_init_ring_data;
3056 }
3057
3058 ret = register_netdev(netdev);
3059 if (ret) {
3060 dev_err(priv->dev, "probe register netdev fail!\n");
3061 goto out_reg_netdev_fail;
3062 }
3063
986743db
YL		 3064 hns3_dcbnl_setup(handle);
3065
a8e8b7ff
S		 3066 /* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */
3067 netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
3068
76ad4f0e
S		 3069 return ret;
3070
3071out_reg_netdev_fail:
3072out_init_ring_data:
3073 (void)hns3_nic_uninit_vector_data(priv);
76ad4f0e 3074out_init_vector_data:
dd38c726
YL		 3075 hns3_nic_dealloc_vector_data(priv);
3076out_alloc_vector_data:
3077 priv->ring_data = NULL;
76ad4f0e
S		 3078out_get_ring_cfg:
3079 priv->ae_handle = NULL;
3080 free_netdev(netdev);
3081 return ret;
3082}
3083
3084static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3085{
3086 struct net_device *netdev = handle->kinfo.netdev;
3087 struct hns3_nic_priv *priv = netdev_priv(netdev);
3088 int ret;
3089
3090 if (netdev->reg_state != NETREG_UNINITIALIZED)
3091 unregister_netdev(netdev);
3092
3093 ret = hns3_nic_uninit_vector_data(priv);
3094 if (ret)
3095 netdev_err(netdev, "uninit vector error\n");
3096
dd38c726
YL		 3097 ret = hns3_nic_dealloc_vector_data(priv);
3098 if (ret)
3099 netdev_err(netdev, "dealloc vector error\n");
3100
76ad4f0e
S		 3101 ret = hns3_uninit_all_ring(priv);
3102 if (ret)
3103 netdev_err(netdev, "uninit ring error\n");
3104
ec777890
YL		 3105 hns3_put_ring_config(priv);
3106
76ad4f0e
S		 3107 priv->ring_data = NULL;
3108
3109 free_netdev(netdev);
3110}
3111
3112static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3113{
3114 struct net_device *netdev = handle->kinfo.netdev;
3115
3116 if (!netdev)
3117 return;
3118
3119 if (linkup) {
3120 netif_carrier_on(netdev);
3121 netif_tx_wake_all_queues(netdev);
3122 netdev_info(netdev, "link up\n");
3123 } else {
3124 netif_carrier_off(netdev);
3125 netif_tx_stop_all_queues(netdev);
3126 netdev_info(netdev, "link down\n");
3127 }
3128}
3129
9df8f79a
YL		 3130static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3131{
3132 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3133 struct net_device *ndev = kinfo->netdev;
075cfdd6 3134 bool if_running;
9df8f79a
YL		 3135 int ret;
3136 u8 i;
3137
3138 if (tc > HNAE3_MAX_TC)
3139 return -EINVAL;
3140
3141 if (!ndev)
3142 return -ENODEV;
3143
075cfdd6
CIK		 3144 if_running = netif_running(ndev);
3145
9df8f79a
YL		 3146 ret = netdev_set_num_tc(ndev, tc);
3147 if (ret)
3148 return ret;
3149
3150 if (if_running) {
3151 (void)hns3_nic_net_stop(ndev);
3152 msleep(100);
3153 }
3154
3155 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3156 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3157 if (ret)
3158 goto err_out;
3159
3160 if (tc <= 1) {
3161 netdev_reset_tc(ndev);
3162 goto out;
3163 }
3164
3165 for (i = 0; i < HNAE3_MAX_TC; i++) {
3166 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3167
3168 if (tc_info->enable)
3169 netdev_set_tc_queue(ndev,
3170 tc_info->tc,
3171 tc_info->tqp_count,
3172 tc_info->tqp_offset);
3173 }
3174
3175 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
3176 netdev_set_prio_tc_map(ndev, i,
3177 kinfo->prio_tc[i]);
3178 }
3179
3180out:
3181 ret = hns3_nic_set_real_num_queue(ndev);
3182
3183err_out:
3184 if (if_running)
3185 (void)hns3_nic_net_open(ndev);
3186
3187 return ret;
3188}
3189
bb6b94a8
L		 3190static void hns3_recover_hw_addr(struct net_device *ndev)
3191{
3192 struct netdev_hw_addr_list *list;
3193 struct netdev_hw_addr *ha, *tmp;
3194
3195 /* go through and sync uc_addr entries to the device */
3196 list = &ndev->uc;
3197 list_for_each_entry_safe(ha, tmp, &list->list, list)
3198 hns3_nic_uc_sync(ndev, ha->addr);
3199
3200 /* go through and sync mc_addr entries to the device */
3201 list = &ndev->mc;
3202 list_for_each_entry_safe(ha, tmp, &list->list, list)
3203 hns3_nic_mc_sync(ndev, ha->addr);
3204}
3205
3206static void hns3_drop_skb_data(struct hns3_enet_ring *ring, struct sk_buff *skb)
3207{
3208 dev_kfree_skb_any(skb);
3209}
3210
3211static void hns3_clear_all_ring(struct hnae3_handle *h)
3212{
3213 struct net_device *ndev = h->kinfo.netdev;
3214 struct hns3_nic_priv *priv = netdev_priv(ndev);
3215 u32 i;
3216
3217 for (i = 0; i < h->kinfo.num_tqps; i++) {
3218 struct netdev_queue *dev_queue;
3219 struct hns3_enet_ring *ring;
3220
3221 ring = priv->ring_data[i].ring;
3222 hns3_clean_tx_ring(ring, ring->desc_num);
3223 dev_queue = netdev_get_tx_queue(ndev,
3224 priv->ring_data[i].queue_index);
3225 netdev_tx_reset_queue(dev_queue);
3226
3227 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3228 hns3_clean_rx_ring(ring, ring->desc_num, hns3_drop_skb_data);
3229 }
3230}
3231
3232static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3233{
3234 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3235 struct net_device *ndev = kinfo->netdev;
3236
3237 if (!netif_running(ndev))
3238 return -EIO;
3239
3240 return hns3_nic_net_stop(ndev);
3241}
3242
3243static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
3244{
3245 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
bb6b94a8
L		 3246 int ret = 0;
3247
3248 if (netif_running(kinfo->netdev)) {
3249 ret = hns3_nic_net_up(kinfo->netdev);
3250 if (ret) {
3251 netdev_err(kinfo->netdev,
3252 "hns net up fail, ret=%d!\n", ret);
3253 return ret;
3254 }
6d4c3981 3255 handle->last_reset_time = jiffies;
bb6b94a8
L		 3256 }
3257
3258 return ret;
3259}
3260
3261static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
3262{
3263 struct net_device *netdev = handle->kinfo.netdev;
3264 struct hns3_nic_priv *priv = netdev_priv(netdev);
3265 int ret;
3266
f09555ff 3267 hns3_init_mac_addr(netdev, false);
bb6b94a8
L		 3268 hns3_nic_set_rx_mode(netdev);
3269 hns3_recover_hw_addr(netdev);
3270
681ec399
YL		 3271 /* Hardware table is only clear when pf resets */
3272 if (!(handle->flags & HNAE3_SUPPORT_VF))
3273 hns3_restore_vlan(netdev);
3274
bb6b94a8
L		 3275 /* Carrier off reporting is important to ethtool even BEFORE open */
3276 netif_carrier_off(netdev);
3277
3278 ret = hns3_get_ring_config(priv);
3279 if (ret)
3280 return ret;
3281
3282 ret = hns3_nic_init_vector_data(priv);
3283 if (ret)
3284 return ret;
3285
3286 ret = hns3_init_all_ring(priv);
3287 if (ret) {
3288 hns3_nic_uninit_vector_data(priv);
3289 priv->ring_data = NULL;
3290 }
3291
3292 return ret;
3293}
3294
3295static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
3296{
3297 struct net_device *netdev = handle->kinfo.netdev;
3298 struct hns3_nic_priv *priv = netdev_priv(netdev);
3299 int ret;
3300
3301 hns3_clear_all_ring(handle);
3302
3303 ret = hns3_nic_uninit_vector_data(priv);
3304 if (ret) {
3305 netdev_err(netdev, "uninit vector error\n");
3306 return ret;
3307 }
3308
3309 ret = hns3_uninit_all_ring(priv);
3310 if (ret)
3311 netdev_err(netdev, "uninit ring error\n");
3312
ec777890
YL		 3313 hns3_put_ring_config(priv);
3314
bb6b94a8
L		 3315 priv->ring_data = NULL;
3316
3317 return ret;
3318}
3319
3320static int hns3_reset_notify(struct hnae3_handle *handle,
3321 enum hnae3_reset_notify_type type)
3322{
3323 int ret = 0;
3324
3325 switch (type) {
3326 case HNAE3_UP_CLIENT:
e1586241
SM		 3327 ret = hns3_reset_notify_up_enet(handle);
3328 break;
bb6b94a8
L		 3329 case HNAE3_DOWN_CLIENT:
3330 ret = hns3_reset_notify_down_enet(handle);
3331 break;
3332 case HNAE3_INIT_CLIENT:
3333 ret = hns3_reset_notify_init_enet(handle);
3334 break;
3335 case HNAE3_UNINIT_CLIENT:
3336 ret = hns3_reset_notify_uninit_enet(handle);
3337 break;
3338 default:
3339 break;
3340 }
3341
3342 return ret;
3343}
3344
7a242b23
YL		 3345static void hns3_restore_coal(struct hns3_nic_priv *priv,
3346 struct hns3_enet_coalesce *tx,
3347 struct hns3_enet_coalesce *rx)
3348{
3349 u16 vector_num = priv->vector_num;
3350 int i;
3351
3352 for (i = 0; i < vector_num; i++) {
3353 memcpy(&priv->tqp_vector[i].tx_group.coal, tx,
3354 sizeof(struct hns3_enet_coalesce));
3355 memcpy(&priv->tqp_vector[i].rx_group.coal, rx,
3356 sizeof(struct hns3_enet_coalesce));
3357 }
3358}
3359
3360static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num,
3361 struct hns3_enet_coalesce *tx,
3362 struct hns3_enet_coalesce *rx)
09f2af64
PL		 3363{
3364 struct hns3_nic_priv *priv = netdev_priv(netdev);
3365 struct hnae3_handle *h = hns3_get_handle(netdev);
3366 int ret;
3367
3368 ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
3369 if (ret)
3370 return ret;
3371
3372 ret = hns3_get_ring_config(priv);
3373 if (ret)
3374 return ret;
3375
dd38c726
YL		 3376 ret = hns3_nic_alloc_vector_data(priv);
3377 if (ret)
3378 goto err_alloc_vector;
3379
7a242b23
YL		 3380 hns3_restore_coal(priv, tx, rx);
3381
09f2af64
PL		 3382 ret = hns3_nic_init_vector_data(priv);
3383 if (ret)
3384 goto err_uninit_vector;
3385
3386 ret = hns3_init_all_ring(priv);
3387 if (ret)
3388 goto err_put_ring;
3389
3390 return 0;
3391
3392err_put_ring:
3393 hns3_put_ring_config(priv);
3394err_uninit_vector:
3395 hns3_nic_uninit_vector_data(priv);
dd38c726
YL		 3396err_alloc_vector:
3397 hns3_nic_dealloc_vector_data(priv);
09f2af64
PL		 3398 return ret;
3399}
3400
3401static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num)
3402{
3403 return (new_tqp_num / num_tc) * num_tc;
3404}
3405
3406int hns3_set_channels(struct net_device *netdev,
3407 struct ethtool_channels *ch)
3408{
3409 struct hns3_nic_priv *priv = netdev_priv(netdev);
3410 struct hnae3_handle *h = hns3_get_handle(netdev);
3411 struct hnae3_knic_private_info *kinfo = &h->kinfo;
7a242b23 3412 struct hns3_enet_coalesce tx_coal, rx_coal;
09f2af64
PL		 3413 bool if_running = netif_running(netdev);
3414 u32 new_tqp_num = ch->combined_count;
3415 u16 org_tqp_num;
3416 int ret;
3417
3418 if (ch->rx_count || ch->tx_count)
3419 return -EINVAL;
3420
678335a1 3421 if (new_tqp_num > hns3_get_max_available_channels(h) ||
09f2af64
PL		 3422 new_tqp_num < kinfo->num_tc) {
3423 dev_err(&netdev->dev,
3424 "Change tqps fail, the tqp range is from %d to %d",
3425 kinfo->num_tc,
678335a1 3426 hns3_get_max_available_channels(h));
09f2af64
PL		 3427 return -EINVAL;
3428 }
3429
3430 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num);
3431 if (kinfo->num_tqps == new_tqp_num)
3432 return 0;
3433
3434 if (if_running)
20e4bf98 3435 hns3_nic_net_stop(netdev);
09f2af64
PL		 3436
3437 hns3_clear_all_ring(h);
3438
3439 ret = hns3_nic_uninit_vector_data(priv);
3440 if (ret) {
3441 dev_err(&netdev->dev,
3442 "Unbind vector with tqp fail, nothing is changed");
3443 goto open_netdev;
3444 }
3445
7a242b23
YL		 3446 /* Changing the tqp num may also change the vector num,
3447 * ethtool only support setting and querying one coal
3448 * configuation for now, so save the vector 0' coal
3449 * configuation here in order to restore it.
3450 */
3451 memcpy(&tx_coal, &priv->tqp_vector[0].tx_group.coal,
3452 sizeof(struct hns3_enet_coalesce));
3453 memcpy(&rx_coal, &priv->tqp_vector[0].rx_group.coal,
3454 sizeof(struct hns3_enet_coalesce));
3455
dd38c726
YL		 3456 hns3_nic_dealloc_vector_data(priv);
3457
09f2af64 3458 hns3_uninit_all_ring(priv);
ec777890 3459 hns3_put_ring_config(priv);
09f2af64
PL		 3460
3461 org_tqp_num = h->kinfo.num_tqps;
7a242b23 3462 ret = hns3_modify_tqp_num(netdev, new_tqp_num, &tx_coal, &rx_coal);
09f2af64 3463 if (ret) {
7a242b23
YL		 3464 ret = hns3_modify_tqp_num(netdev, org_tqp_num,
3465 &tx_coal, &rx_coal);
09f2af64
PL		 3466 if (ret) {
3467 /* If revert to old tqp failed, fatal error occurred */
3468 dev_err(&netdev->dev,
3469 "Revert to old tqp num fail, ret=%d", ret);
3470 return ret;
3471 }
3472 dev_info(&netdev->dev,
3473 "Change tqp num fail, Revert to old tqp num");
3474 }
3475
3476open_netdev:
3477 if (if_running)
20e4bf98 3478 hns3_nic_net_open(netdev);
09f2af64
PL		 3479
3480 return ret;
3481}
3482
1db9b1bf 3483static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 3484 .init_instance = hns3_client_init,
3485 .uninit_instance = hns3_client_uninit,
3486 .link_status_change = hns3_link_status_change,
9df8f79a 3487 .setup_tc = hns3_client_setup_tc,
bb6b94a8 3488 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 3489};
3490
3491/* hns3_init_module - Driver registration routine
3492 * hns3_init_module is the first routine called when the driver is
3493 * loaded. All it does is register with the PCI subsystem.
3494 */
3495static int __init hns3_init_module(void)
3496{
3497 int ret;
3498
3499 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
3500 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
3501
3502 client.type = HNAE3_CLIENT_KNIC;
3503 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
3504 hns3_driver_name);
3505
3506 client.ops = &client_ops;
3507
3508 ret = hnae3_register_client(&client);
3509 if (ret)
3510 return ret;
3511
3512 ret = pci_register_driver(&hns3_driver);
3513 if (ret)
3514 hnae3_unregister_client(&client);
3515
3516 return ret;
3517}
3518module_init(hns3_init_module);
3519
3520/* hns3_exit_module - Driver exit cleanup routine
3521 * hns3_exit_module is called just before the driver is removed
3522 * from memory.
3523 */
3524static void __exit hns3_exit_module(void)
3525{
3526 pci_unregister_driver(&hns3_driver);
3527 hnae3_unregister_client(&client);
3528}
3529module_exit(hns3_exit_module);
3530
3531MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
3532MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3533MODULE_LICENSE("GPL");
3534MODULE_ALIAS("pci:hns-nic");
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