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net: hns3: clear pci private data when unload hns3 driver
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
ef57c40f
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
7#include <linux/if_vlan.h>
8#include <linux/ip.h>
9#include <linux/ipv6.h>
10#include <linux/module.h>
11#include <linux/pci.h>
538d8ba0 12#include <linux/aer.h>
76ad4f0e
S		 13#include <linux/skbuff.h>
14#include <linux/sctp.h>
15#include <linux/vermagic.h>
16#include <net/gre.h>
30d240df 17#include <net/pkt_cls.h>
5337b725 18#include <net/tcp.h>
76ad4f0e
S		 19#include <net/vxlan.h>
20
21#include "hnae3.h"
22#include "hns3_enet.h"
23
e32a805a
FL		 24static void hns3_clear_all_ring(struct hnae3_handle *h);
25static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
2c794374 26static void hns3_remove_hw_addr(struct net_device *netdev);
e32a805a 27
1db9b1bf 28static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 29const char hns3_driver_version[] = VERMAGIC_STRING;
30static const char hns3_driver_string[] =
31 "Hisilicon Ethernet Network Driver for Hip08 Family";
32static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
33static struct hnae3_client client;
34
35/* hns3_pci_tbl - PCI Device ID Table
36 *
37 * Last entry must be all 0s
38 *
39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
40 * Class, Class Mask, private data (not used) }
41 */
42static const struct pci_device_id hns3_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
a9c89a3f 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
f4e4e86c
JS		 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 58 /* required last entry */
59 {0, }
60};
61MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
62
5a8b1a40 63static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 64{
5a8b1a40 65 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e
S		 66
67 napi_schedule(&tqp_vector->napi);
68
69 return IRQ_HANDLED;
70}
71
15040788
PL		 72/* This callback function is used to set affinity changes to the irq affinity
73 * masks when the irq_set_affinity_notifier function is used.
74 */
75static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify,
76 const cpumask_t *mask)
77{
78 struct hns3_enet_tqp_vector *tqp_vectors =
79 container_of(notify, struct hns3_enet_tqp_vector,
80 affinity_notify);
81
82 tqp_vectors->affinity_mask = *mask;
83}
84
85static void hns3_nic_irq_affinity_release(struct kref *ref)
86{
87}
88
76ad4f0e
S		 89static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
90{
91 struct hns3_enet_tqp_vector *tqp_vectors;
92 unsigned int i;
93
94 for (i = 0; i < priv->vector_num; i++) {
95 tqp_vectors = &priv->tqp_vector[i];
96
97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
98 continue;
99
15040788
PL		 100 /* clear the affinity notifier and affinity mask */
101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL);
102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
103
76ad4f0e
S		 104 /* release the irq resource */
105 free_irq(tqp_vectors->vector_irq, tqp_vectors);
106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
107 }
108}
109
110static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
111{
112 struct hns3_enet_tqp_vector *tqp_vectors;
113 int txrx_int_idx = 0;
114 int rx_int_idx = 0;
115 int tx_int_idx = 0;
116 unsigned int i;
117 int ret;
118
119 for (i = 0; i < priv->vector_num; i++) {
120 tqp_vectors = &priv->tqp_vector[i];
121
122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
123 continue;
124
125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
127 "%s-%s-%d", priv->netdev->name, "TxRx",
128 txrx_int_idx++);
129 txrx_int_idx++;
130 } else if (tqp_vectors->rx_group.ring) {
131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
132 "%s-%s-%d", priv->netdev->name, "Rx",
133 rx_int_idx++);
134 } else if (tqp_vectors->tx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
136 "%s-%s-%d", priv->netdev->name, "Tx",
137 tx_int_idx++);
138 } else {
139 /* Skip this unused q_vector */
140 continue;
141 }
142
143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
144
145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
146 tqp_vectors->name,
147 tqp_vectors);
148 if (ret) {
149 netdev_err(priv->netdev, "request irq(%d) fail\n",
150 tqp_vectors->vector_irq);
151 return ret;
152 }
153
15040788
PL		 154 tqp_vectors->affinity_notify.notify =
155 hns3_nic_irq_affinity_notify;
156 tqp_vectors->affinity_notify.release =
157 hns3_nic_irq_affinity_release;
158 irq_set_affinity_notifier(tqp_vectors->vector_irq,
159 &tqp_vectors->affinity_notify);
160 irq_set_affinity_hint(tqp_vectors->vector_irq,
161 &tqp_vectors->affinity_mask);
162
76ad4f0e
S		 163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
164 }
165
166 return 0;
167}
168
169static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
170 u32 mask_en)
171{
172 writel(mask_en, tqp_vector->mask_addr);
173}
174
175static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
176{
177 napi_enable(&tqp_vector->napi);
178
179 /* enable vector */
180 hns3_mask_vector_irq(tqp_vector, 1);
181}
182
183static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
184{
185 /* disable vector */
186 hns3_mask_vector_irq(tqp_vector, 0);
187
188 disable_irq(tqp_vector->vector_irq);
189 napi_disable(&tqp_vector->napi);
190}
191
5acd0356
FL		 192void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
193 u32 rl_value)
76ad4f0e 194{
5acd0356
FL		 195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
196
76ad4f0e
S		 197 /* this defines the configuration for RL (Interrupt Rate Limiter).
198 * Rl defines rate of interrupts i.e. number of interrupts-per-second
199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
200 */
5acd0356 201
d420d2de
YL		 202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
203 !tqp_vector->rx_group.coal.gl_adapt_enable)
5acd0356
FL		 204 /* According to the hardware, the range of rl_reg is
205 * 0-59 and the unit is 4.
206 */
207 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
208
209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
210}
211
212void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
213 u32 gl_value)
214{
215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
216
217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
218}
219
220void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
221 u32 gl_value)
222{
223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
224
225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 226}
227
2b27decc
FL		 228static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
229 struct hns3_nic_priv *priv)
76ad4f0e
S		 230{
231 /* initialize the configuration for interrupt coalescing.
232 * 1. GL (Interrupt Gap Limiter)
233 * 2. RL (Interrupt Rate Limiter)
234 */
235
2b27decc 236 /* Default: enable interrupt coalescing self-adaptive and GL */
d420d2de
YL		 237 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
238 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
2b27decc 239
d420d2de
YL		 240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
2b27decc 242
d420d2de
YL		 243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 245}
246
6cbd6d33
YL		 247static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
248 struct hns3_nic_priv *priv)
249{
250 struct hnae3_handle *h = priv->ae_handle;
251
252 hns3_set_vector_coalesce_tx_gl(tqp_vector,
d420d2de 253 tqp_vector->tx_group.coal.int_gl);
6cbd6d33 254 hns3_set_vector_coalesce_rx_gl(tqp_vector,
d420d2de 255 tqp_vector->rx_group.coal.int_gl);
6cbd6d33
YL		 256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
257}
258
9df8f79a
YL		 259static int hns3_nic_set_real_num_queue(struct net_device *netdev)
260{
9780cb97 261 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 262 struct hnae3_knic_private_info *kinfo = &h->kinfo;
263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
7e114e7d
YL		 264 int i, ret;
265
266 if (kinfo->num_tc <= 1) {
267 netdev_reset_tc(netdev);
268 } else {
269 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
270 if (ret) {
271 netdev_err(netdev,
272 "netdev_set_num_tc fail, ret=%d!\n", ret);
273 return ret;
274 }
275
276 for (i = 0; i < HNAE3_MAX_TC; i++) {
277 if (!kinfo->tc_info[i].enable)
278 continue;
279
280 netdev_set_tc_queue(netdev,
281 kinfo->tc_info[i].tc,
282 kinfo->tc_info[i].tqp_count,
283 kinfo->tc_info[i].tqp_offset);
284 }
285 }
9df8f79a
YL		 286
287 ret = netif_set_real_num_tx_queues(netdev, queue_size);
288 if (ret) {
289 netdev_err(netdev,
290 "netif_set_real_num_tx_queues fail, ret=%d!\n",
291 ret);
292 return ret;
293 }
294
295 ret = netif_set_real_num_rx_queues(netdev, queue_size);
296 if (ret) {
297 netdev_err(netdev,
298 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
299 return ret;
300 }
301
302 return 0;
303}
304
2d7187ce
PL		 305static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
306{
08ca3d58 307 u16 alloc_tqps, max_rss_size, rss_size;
2d7187ce 308
08ca3d58
HT		 309 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
310 rss_size = alloc_tqps / h->kinfo.num_tc;
2d7187ce 311
08ca3d58 312 return min_t(u16, rss_size, max_rss_size);
2d7187ce
PL		 313}
314
2b5251b7
HT		 315static void hns3_tqp_enable(struct hnae3_queue *tqp)
316{
317 u32 rcb_reg;
318
319 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
320 rcb_reg |= BIT(HNS3_RING_EN_B);
321 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
322}
323
324static void hns3_tqp_disable(struct hnae3_queue *tqp)
325{
326 u32 rcb_reg;
327
328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
329 rcb_reg &= ~BIT(HNS3_RING_EN_B);
330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
331}
332
76ad4f0e
S		 333static int hns3_nic_net_up(struct net_device *netdev)
334{
335 struct hns3_nic_priv *priv = netdev_priv(netdev);
336 struct hnae3_handle *h = priv->ae_handle;
337 int i, j;
338 int ret;
339
e32a805a
FL		 340 ret = hns3_nic_reset_all_ring(h);
341 if (ret)
342 return ret;
343
76ad4f0e
S		 344 /* get irq resource for all vectors */
345 ret = hns3_nic_init_irq(priv);
346 if (ret) {
347 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
348 return ret;
349 }
350
351 /* enable the vectors */
352 for (i = 0; i < priv->vector_num; i++)
353 hns3_vector_enable(&priv->tqp_vector[i]);
354
2b5251b7
HT		 355 /* enable rcb */
356 for (j = 0; j < h->kinfo.num_tqps; j++)
357 hns3_tqp_enable(h->kinfo.tqp[j]);
358
76ad4f0e
S		 359 /* start the ae_dev */
360 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
361 if (ret)
362 goto out_start_err;
363
a3083abb
JS		 364 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
365
76ad4f0e
S		 366 return 0;
367
368out_start_err:
2b5251b7
HT		 369 while (j--)
370 hns3_tqp_disable(h->kinfo.tqp[j]);
371
76ad4f0e
S		 372 for (j = i - 1; j >= 0; j--)
373 hns3_vector_disable(&priv->tqp_vector[j]);
374
375 hns3_nic_uninit_irq(priv);
376
377 return ret;
378}
379
380static int hns3_nic_net_open(struct net_device *netdev)
381{
fad0e9d8 382 struct hns3_nic_priv *priv = netdev_priv(netdev);
7e114e7d
YL		 383 struct hnae3_handle *h = hns3_get_handle(netdev);
384 struct hnae3_knic_private_info *kinfo;
385 int i, ret;
76ad4f0e 386
3a11f446
HT		 387 if (hns3_nic_resetting(netdev))
388 return -EBUSY;
389
76ad4f0e
S		 390 netif_carrier_off(netdev);
391
9df8f79a
YL		 392 ret = hns3_nic_set_real_num_queue(netdev);
393 if (ret)
76ad4f0e 394 return ret;
76ad4f0e
S		 395
396 ret = hns3_nic_net_up(netdev);
397 if (ret) {
398 netdev_err(netdev,
399 "hns net up fail, ret=%d!\n", ret);
400 return ret;
401 }
402
7e114e7d
YL		 403 kinfo = &h->kinfo;
404 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
405 netdev_set_prio_tc_map(netdev, i,
406 kinfo->prio_tc[i]);
407 }
408
fad0e9d8
JS		 409 if (h->ae_algo->ops->set_timer_task)
410 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
411
76ad4f0e
S		 412 return 0;
413}
414
415static void hns3_nic_net_down(struct net_device *netdev)
416{
417 struct hns3_nic_priv *priv = netdev_priv(netdev);
2b5251b7 418 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 419 const struct hnae3_ae_ops *ops;
420 int i;
421
e32a805a
FL		 422 /* disable vectors */
423 for (i = 0; i < priv->vector_num; i++)
424 hns3_vector_disable(&priv->tqp_vector[i]);
425
2b5251b7
HT		 426 /* disable rcb */
427 for (i = 0; i < h->kinfo.num_tqps; i++)
428 hns3_tqp_disable(h->kinfo.tqp[i]);
429
76ad4f0e
S		 430 /* stop ae_dev */
431 ops = priv->ae_handle->ae_algo->ops;
432 if (ops->stop)
433 ops->stop(priv->ae_handle);
434
76ad4f0e
S		 435 /* free irq resources */
436 hns3_nic_uninit_irq(priv);
e32a805a
FL		 437
438 hns3_clear_all_ring(priv->ae_handle);
76ad4f0e
S		 439}
440
441static int hns3_nic_net_stop(struct net_device *netdev)
442{
f22463fd 443 struct hns3_nic_priv *priv = netdev_priv(netdev);
fad0e9d8 444 struct hnae3_handle *h = hns3_get_handle(netdev);
f22463fd
HT		 445
446 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
447 return 0;
448
fad0e9d8
JS		 449 if (h->ae_algo->ops->set_timer_task)
450 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
451
76ad4f0e
S		 452 netif_tx_stop_all_queues(netdev);
453 netif_carrier_off(netdev);
454
455 hns3_nic_net_down(netdev);
456
457 return 0;
458}
459
76ad4f0e
S		 460static int hns3_nic_uc_sync(struct net_device *netdev,
461 const unsigned char *addr)
462{
9780cb97 463 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 464
465 if (h->ae_algo->ops->add_uc_addr)
466 return h->ae_algo->ops->add_uc_addr(h, addr);
467
468 return 0;
469}
470
471static int hns3_nic_uc_unsync(struct net_device *netdev,
472 const unsigned char *addr)
473{
9780cb97 474 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 475
476 if (h->ae_algo->ops->rm_uc_addr)
477 return h->ae_algo->ops->rm_uc_addr(h, addr);
478
479 return 0;
480}
481
482static int hns3_nic_mc_sync(struct net_device *netdev,
483 const unsigned char *addr)
484{
9780cb97 485 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 486
720a8478 487 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 488 return h->ae_algo->ops->add_mc_addr(h, addr);
489
490 return 0;
491}
492
493static int hns3_nic_mc_unsync(struct net_device *netdev,
494 const unsigned char *addr)
495{
9780cb97 496 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 497
720a8478 498 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 499 return h->ae_algo->ops->rm_mc_addr(h, addr);
500
501 return 0;
502}
503
1e3653db
JS		 504static u8 hns3_get_netdev_flags(struct net_device *netdev)
505{
506 u8 flags = 0;
507
508 if (netdev->flags & IFF_PROMISC) {
509 flags = HNAE3_USER_UPE | HNAE3_USER_MPE;
510 } else {
511 flags |= HNAE3_VLAN_FLTR;
512 if (netdev->flags & IFF_ALLMULTI)
513 flags |= HNAE3_USER_MPE;
514 }
515
516 return flags;
517}
518
1db9b1bf 519static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 520{
9780cb97 521 struct hnae3_handle *h = hns3_get_handle(netdev);
1e3653db
JS		 522 u8 new_flags;
523 int ret;
76ad4f0e 524
1e3653db
JS		 525 new_flags = hns3_get_netdev_flags(netdev);
526
527 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
528 if (ret) {
76ad4f0e 529 netdev_err(netdev, "sync uc address fail\n");
1e3653db
JS		 530 if (ret == -ENOSPC)
531 new_flags |= HNAE3_OVERFLOW_UPE;
532 }
533
a832d8b5 534 if (netdev->flags & IFF_MULTICAST) {
1e3653db
JS		 535 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
536 hns3_nic_mc_unsync);
537 if (ret) {
76ad4f0e 538 netdev_err(netdev, "sync mc address fail\n");
1e3653db
JS		 539 if (ret == -ENOSPC)
540 new_flags |= HNAE3_OVERFLOW_MPE;
541 }
542 }
543
544 hns3_update_promisc_mode(netdev, new_flags);
545 /* User mode Promisc mode enable and vlan filtering is disabled to
546 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
547 * vlan fitering is enabled
548 */
549 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
550 h->netdev_flags = new_flags;
551}
552
abe62a63 553int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
1e3653db
JS		 554{
555 struct hns3_nic_priv *priv = netdev_priv(netdev);
556 struct hnae3_handle *h = priv->ae_handle;
557
558 if (h->ae_algo->ops->set_promisc_mode) {
abe62a63
HT		 559 return h->ae_algo->ops->set_promisc_mode(h,
560 promisc_flags & HNAE3_UPE,
561 promisc_flags & HNAE3_MPE);
1e3653db 562 }
abe62a63
HT		 563
564 return 0;
1e3653db
JS		 565}
566
567void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
568{
569 struct hns3_nic_priv *priv = netdev_priv(netdev);
570 struct hnae3_handle *h = priv->ae_handle;
571 bool last_state;
572
573 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
574 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
575 if (enable != last_state) {
576 netdev_info(netdev,
577 "%s vlan filter\n",
578 enable ? "enable" : "disable");
579 h->ae_algo->ops->enable_vlan_filter(h, enable);
580 }
a832d8b5 581 }
76ad4f0e
S		 582}
583
584static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
585 u16 *mss, u32 *type_cs_vlan_tso)
586{
587 u32 l4_offset, hdr_len;
588 union l3_hdr_info l3;
589 union l4_hdr_info l4;
590 u32 l4_paylen;
591 int ret;
592
593 if (!skb_is_gso(skb))
594 return 0;
595
596 ret = skb_cow_head(skb, 0);
597 if (ret)
598 return ret;
599
600 l3.hdr = skb_network_header(skb);
601 l4.hdr = skb_transport_header(skb);
602
603 /* Software should clear the IPv4's checksum field when tso is
604 * needed.
605 */
606 if (l3.v4->version == 4)
607 l3.v4->check = 0;
608
609 /* tunnel packet.*/
610 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
611 SKB_GSO_GRE_CSUM |
612 SKB_GSO_UDP_TUNNEL |
613 SKB_GSO_UDP_TUNNEL_CSUM)) {
614 if ((!(skb_shinfo(skb)->gso_type &
615 SKB_GSO_PARTIAL)) &&
616 (skb_shinfo(skb)->gso_type &
617 SKB_GSO_UDP_TUNNEL_CSUM)) {
618 /* Software should clear the udp's checksum
619 * field when tso is needed.
620 */
621 l4.udp->check = 0;
622 }
623 /* reset l3&l4 pointers from outer to inner headers */
624 l3.hdr = skb_inner_network_header(skb);
625 l4.hdr = skb_inner_transport_header(skb);
626
627 /* Software should clear the IPv4's checksum field when
628 * tso is needed.
629 */
630 if (l3.v4->version == 4)
631 l3.v4->check = 0;
632 }
633
634 /* normal or tunnel packet*/
635 l4_offset = l4.hdr - skb->data;
636 hdr_len = (l4.tcp->doff * 4) + l4_offset;
637
638 /* remove payload length from inner pseudo checksum when tso*/
639 l4_paylen = skb->len - l4_offset;
640 csum_replace_by_diff(&l4.tcp->check,
641 (__force __wsum)htonl(l4_paylen));
642
643 /* find the txbd field values */
644 *paylen = skb->len - hdr_len;
ccc23ef3
PL		 645 hnae3_set_bit(*type_cs_vlan_tso,
646 HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 647
648 /* get MSS for TSO */
649 *mss = skb_shinfo(skb)->gso_size;
650
651 return 0;
652}
653
1898d4e4
S		 654static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
655 u8 *il4_proto)
76ad4f0e
S		 656{
657 union {
658 struct iphdr *v4;
659 struct ipv6hdr *v6;
660 unsigned char *hdr;
661 } l3;
662 unsigned char *l4_hdr;
663 unsigned char *exthdr;
664 u8 l4_proto_tmp;
665 __be16 frag_off;
666
667 /* find outer header point */
668 l3.hdr = skb_network_header(skb);
c82a5497 669 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 670
671 if (skb->protocol == htons(ETH_P_IPV6)) {
672 exthdr = l3.hdr + sizeof(*l3.v6);
673 l4_proto_tmp = l3.v6->nexthdr;
674 if (l4_hdr != exthdr)
675 ipv6_skip_exthdr(skb, exthdr - skb->data,
676 &l4_proto_tmp, &frag_off);
677 } else if (skb->protocol == htons(ETH_P_IP)) {
678 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 679 } else {
680 return -EINVAL;
76ad4f0e
S		 681 }
682
683 *ol4_proto = l4_proto_tmp;
684
685 /* tunnel packet */
686 if (!skb->encapsulation) {
687 *il4_proto = 0;
1898d4e4 688 return 0;
76ad4f0e
S		 689 }
690
691 /* find inner header point */
692 l3.hdr = skb_inner_network_header(skb);
693 l4_hdr = skb_inner_transport_header(skb);
694
695 if (l3.v6->version == 6) {
696 exthdr = l3.hdr + sizeof(*l3.v6);
697 l4_proto_tmp = l3.v6->nexthdr;
698 if (l4_hdr != exthdr)
699 ipv6_skip_exthdr(skb, exthdr - skb->data,
700 &l4_proto_tmp, &frag_off);
701 } else if (l3.v4->version == 4) {
702 l4_proto_tmp = l3.v4->protocol;
703 }
704
705 *il4_proto = l4_proto_tmp;
1898d4e4
S		 706
707 return 0;
76ad4f0e
S		 708}
709
710static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
711 u8 il4_proto, u32 *type_cs_vlan_tso,
712 u32 *ol_type_vlan_len_msec)
713{
714 union {
715 struct iphdr *v4;
716 struct ipv6hdr *v6;
717 unsigned char *hdr;
718 } l3;
719 union {
720 struct tcphdr *tcp;
721 struct udphdr *udp;
722 struct gre_base_hdr *gre;
723 unsigned char *hdr;
724 } l4;
725 unsigned char *l2_hdr;
726 u8 l4_proto = ol4_proto;
727 u32 ol2_len;
728 u32 ol3_len;
729 u32 ol4_len;
730 u32 l2_len;
731 u32 l3_len;
732
733 l3.hdr = skb_network_header(skb);
734 l4.hdr = skb_transport_header(skb);
735
736 /* compute L2 header size for normal packet, defined in 2 Bytes */
737 l2_len = l3.hdr - skb->data;
ccc23ef3
PL		 738 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
739 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 740
741 /* tunnel packet*/
742 if (skb->encapsulation) {
743 /* compute OL2 header size, defined in 2 Bytes */
744 ol2_len = l2_len;
ccc23ef3
PL		 745 hnae3_set_field(*ol_type_vlan_len_msec,
746 HNS3_TXD_L2LEN_M,
747 HNS3_TXD_L2LEN_S, ol2_len >> 1);
76ad4f0e
S		 748
749 /* compute OL3 header size, defined in 4 Bytes */
750 ol3_len = l4.hdr - l3.hdr;
ccc23ef3
PL		 751 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
752 HNS3_TXD_L3LEN_S, ol3_len >> 2);
76ad4f0e
S		 753
754 /* MAC in UDP, MAC in GRE (0x6558)*/
755 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
756 /* switch MAC header ptr from outer to inner header.*/
757 l2_hdr = skb_inner_mac_header(skb);
758
759 /* compute OL4 header size, defined in 4 Bytes. */
760 ol4_len = l2_hdr - l4.hdr;
ccc23ef3
PL		 761 hnae3_set_field(*ol_type_vlan_len_msec,
762 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
763 ol4_len >> 2);
76ad4f0e
S		 764
765 /* switch IP header ptr from outer to inner header */
766 l3.hdr = skb_inner_network_header(skb);
767
768 /* compute inner l2 header size, defined in 2 Bytes. */
769 l2_len = l3.hdr - l2_hdr;
ccc23ef3
PL		 770 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
771 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 772 } else {
773 /* skb packet types not supported by hardware,
774 * txbd len fild doesn't be filled.
775 */
776 return;
777 }
778
779 /* switch L4 header pointer from outer to inner */
780 l4.hdr = skb_inner_transport_header(skb);
781
782 l4_proto = il4_proto;
783 }
784
785 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
786 l3_len = l4.hdr - l3.hdr;
ccc23ef3
PL		 787 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
788 HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e
S		 789
790 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
791 switch (l4_proto) {
792 case IPPROTO_TCP:
ccc23ef3
PL		 793 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
794 HNS3_TXD_L4LEN_S, l4.tcp->doff);
76ad4f0e
S		 795 break;
796 case IPPROTO_SCTP:
ccc23ef3
PL		 797 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
798 HNS3_TXD_L4LEN_S,
799 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 800 break;
801 case IPPROTO_UDP:
ccc23ef3
PL		 802 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
803 HNS3_TXD_L4LEN_S,
804 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 805 break;
806 default:
807 /* skb packet types not supported by hardware,
808 * txbd len fild doesn't be filled.
809 */
810 return;
811 }
812}
813
cfdd6e86
YL		 814/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
815 * and it is udp packet, which has a dest port as the IANA assigned.
816 * the hardware is expected to do the checksum offload, but the
817 * hardware will not do the checksum offload when udp dest port is
818 * 4789.
819 */
820static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
821{
822#define IANA_VXLAN_PORT 4789
823 union {
824 struct tcphdr *tcp;
825 struct udphdr *udp;
826 struct gre_base_hdr *gre;
827 unsigned char *hdr;
828 } l4;
829
830 l4.hdr = skb_transport_header(skb);
831
832 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
833 return false;
834
835 skb_checksum_help(skb);
836
837 return true;
838}
839
76ad4f0e
S		 840static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
841 u8 il4_proto, u32 *type_cs_vlan_tso,
842 u32 *ol_type_vlan_len_msec)
843{
844 union {
845 struct iphdr *v4;
846 struct ipv6hdr *v6;
847 unsigned char *hdr;
848 } l3;
849 u32 l4_proto = ol4_proto;
850
851 l3.hdr = skb_network_header(skb);
852
853 /* define OL3 type and tunnel type(OL4).*/
854 if (skb->encapsulation) {
855 /* define outer network header type.*/
856 if (skb->protocol == htons(ETH_P_IP)) {
857 if (skb_is_gso(skb))
ccc23ef3
PL		 858 hnae3_set_field(*ol_type_vlan_len_msec,
859 HNS3_TXD_OL3T_M,
860 HNS3_TXD_OL3T_S,
861 HNS3_OL3T_IPV4_CSUM);
76ad4f0e 862 else
ccc23ef3
PL		 863 hnae3_set_field(*ol_type_vlan_len_msec,
864 HNS3_TXD_OL3T_M,
865 HNS3_TXD_OL3T_S,
866 HNS3_OL3T_IPV4_NO_CSUM);
76ad4f0e
S		 867
868 } else if (skb->protocol == htons(ETH_P_IPV6)) {
ccc23ef3
PL		 869 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
870 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
76ad4f0e
S		 871 }
872
873 /* define tunnel type(OL4).*/
874 switch (l4_proto) {
875 case IPPROTO_UDP:
ccc23ef3
PL		 876 hnae3_set_field(*ol_type_vlan_len_msec,
877 HNS3_TXD_TUNTYPE_M,
878 HNS3_TXD_TUNTYPE_S,
879 HNS3_TUN_MAC_IN_UDP);
76ad4f0e
S		 880 break;
881 case IPPROTO_GRE:
ccc23ef3
PL		 882 hnae3_set_field(*ol_type_vlan_len_msec,
883 HNS3_TXD_TUNTYPE_M,
884 HNS3_TXD_TUNTYPE_S,
885 HNS3_TUN_NVGRE);
76ad4f0e
S		 886 break;
887 default:
888 /* drop the skb tunnel packet if hardware don't support,
889 * because hardware can't calculate csum when TSO.
890 */
891 if (skb_is_gso(skb))
892 return -EDOM;
893
894 /* the stack computes the IP header already,
895 * driver calculate l4 checksum when not TSO.
896 */
897 skb_checksum_help(skb);
898 return 0;
899 }
900
901 l3.hdr = skb_inner_network_header(skb);
902 l4_proto = il4_proto;
903 }
904
905 if (l3.v4->version == 4) {
ccc23ef3
PL		 906 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
907 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
76ad4f0e
S		 908
909 /* the stack computes the IP header already, the only time we
910 * need the hardware to recompute it is in the case of TSO.
911 */
912 if (skb_is_gso(skb))
ccc23ef3 913 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 914 } else if (l3.v6->version == 6) {
ccc23ef3
PL		 915 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
916 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
76ad4f0e
S		 917 }
918
919 switch (l4_proto) {
920 case IPPROTO_TCP:
79fa1b6a 921 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 922 hnae3_set_field(*type_cs_vlan_tso,
923 HNS3_TXD_L4T_M,
924 HNS3_TXD_L4T_S,
925 HNS3_L4T_TCP);
76ad4f0e
S		 926 break;
927 case IPPROTO_UDP:
cfdd6e86
YL		 928 if (hns3_tunnel_csum_bug(skb))
929 break;
930
79fa1b6a 931 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 932 hnae3_set_field(*type_cs_vlan_tso,
933 HNS3_TXD_L4T_M,
934 HNS3_TXD_L4T_S,
935 HNS3_L4T_UDP);
76ad4f0e
S		 936 break;
937 case IPPROTO_SCTP:
79fa1b6a 938 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 939 hnae3_set_field(*type_cs_vlan_tso,
940 HNS3_TXD_L4T_M,
941 HNS3_TXD_L4T_S,
942 HNS3_L4T_SCTP);
76ad4f0e
S		 943 break;
944 default:
945 /* drop the skb tunnel packet if hardware don't support,
946 * because hardware can't calculate csum when TSO.
947 */
948 if (skb_is_gso(skb))
949 return -EDOM;
950
951 /* the stack computes the IP header already,
952 * driver calculate l4 checksum when not TSO.
953 */
954 skb_checksum_help(skb);
955 return 0;
956 }
957
958 return 0;
959}
960
961static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
962{
963 /* Config bd buffer end */
ccc23ef3
PL		 964 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
965 HNS3_TXD_BDTYPE_S, 0);
966 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
967 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
968 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
76ad4f0e
S		 969}
970
1fdd8dc5
PL		 971static int hns3_fill_desc_vtags(struct sk_buff *skb,
972 struct hns3_enet_ring *tx_ring,
973 u32 *inner_vlan_flag,
974 u32 *out_vlan_flag,
975 u16 *inner_vtag,
976 u16 *out_vtag)
977{
978#define HNS3_TX_VLAN_PRIO_SHIFT 13
979
980 if (skb->protocol == htons(ETH_P_8021Q) &&
981 !(tx_ring->tqp->handle->kinfo.netdev->features &
982 NETIF_F_HW_VLAN_CTAG_TX)) {
983 /* When HW VLAN acceleration is turned off, and the stack
984 * sets the protocol to 802.1q, the driver just need to
985 * set the protocol to the encapsulated ethertype.
986 */
987 skb->protocol = vlan_get_protocol(skb);
988 return 0;
989 }
990
991 if (skb_vlan_tag_present(skb)) {
992 u16 vlan_tag;
993
994 vlan_tag = skb_vlan_tag_get(skb);
995 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
996
997 /* Based on hw strategy, use out_vtag in two layer tag case,
998 * and use inner_vtag in one tag case.
999 */
1000 if (skb->protocol == htons(ETH_P_8021Q)) {
ccc23ef3 1001 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
1fdd8dc5
PL		 1002 *out_vtag = vlan_tag;
1003 } else {
ccc23ef3 1004 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
1fdd8dc5
PL		 1005 *inner_vtag = vlan_tag;
1006 }
1007 } else if (skb->protocol == htons(ETH_P_8021Q)) {
1008 struct vlan_ethhdr *vhdr;
1009 int rc;
1010
1011 rc = skb_cow_head(skb, 0);
1012 if (rc < 0)
1013 return rc;
1014 vhdr = (struct vlan_ethhdr *)skb->data;
1015 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1016 << HNS3_TX_VLAN_PRIO_SHIFT);
1017 }
1018
1019 skb->protocol = vlan_get_protocol(skb);
1020 return 0;
1021}
1022
76ad4f0e 1023static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
91040825 1024 int size, int frag_end, enum hns_desc_type type)
76ad4f0e
S		 1025{
1026 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1027 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
91040825 1028 struct device *dev = ring_to_dev(ring);
76ad4f0e
S		 1029 u32 ol_type_vlan_len_msec = 0;
1030 u16 bdtp_fe_sc_vld_ra_ri = 0;
91040825 1031 struct skb_frag_struct *frag;
13491411 1032 unsigned int frag_buf_num;
76ad4f0e
S		 1033 u32 type_cs_vlan_tso = 0;
1034 struct sk_buff *skb;
1fdd8dc5
PL		 1035 u16 inner_vtag = 0;
1036 u16 out_vtag = 0;
13491411
FL		 1037 unsigned int k;
1038 int sizeoflast;
76ad4f0e 1039 u32 paylen = 0;
91040825 1040 dma_addr_t dma;
76ad4f0e 1041 u16 mss = 0;
76ad4f0e
S		 1042 u8 ol4_proto;
1043 u8 il4_proto;
1044 int ret;
1045
76ad4f0e
S		 1046 if (type == DESC_TYPE_SKB) {
1047 skb = (struct sk_buff *)priv;
a90bb9a5 1048 paylen = skb->len;
76ad4f0e 1049
1fdd8dc5
PL		 1050 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1051 &ol_type_vlan_len_msec,
1052 &inner_vtag, &out_vtag);
1053 if (unlikely(ret))
1054 return ret;
1055
76ad4f0e
S		 1056 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1057 skb_reset_mac_len(skb);
76ad4f0e 1058
1898d4e4
S		 1059 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1060 if (ret)
1061 return ret;
76ad4f0e
S		 1062 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
1063 &type_cs_vlan_tso,
1064 &ol_type_vlan_len_msec);
1065 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
1066 &type_cs_vlan_tso,
1067 &ol_type_vlan_len_msec);
1068 if (ret)
1069 return ret;
1070
1071 ret = hns3_set_tso(skb, &paylen, &mss,
1072 &type_cs_vlan_tso);
1073 if (ret)
1074 return ret;
1075 }
1076
1077 /* Set txbd */
1078 desc->tx.ol_type_vlan_len_msec =
1079 cpu_to_le32(ol_type_vlan_len_msec);
1080 desc->tx.type_cs_vlan_tso_len =
1081 cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 1082 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 1083 desc->tx.mss = cpu_to_le16(mss);
1fdd8dc5
PL		 1084 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1085 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
91040825
PL		 1086
1087 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1088 } else {
1089 frag = (struct skb_frag_struct *)priv;
1090 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1091 }
1092
1093 if (dma_mapping_error(ring->dev, dma)) {
1094 ring->stats.sw_err_cnt++;
1095 return -ENOMEM;
76ad4f0e
S		 1096 }
1097
6a3bff0d
FL		 1098 desc_cb->length = size;
1099
13491411
FL		 1100 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1101 sizeoflast = size % HNS3_MAX_BD_SIZE;
1102 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1103
1104 /* When frag size is bigger than hardware limit, split this frag */
1105 for (k = 0; k < frag_buf_num; k++) {
1106 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1107 desc_cb->priv = priv;
13491411
FL		 1108 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1109 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1110 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1111
1112 /* now, fill the descriptor */
1113 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
6a3bff0d
FL		 1114 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1115 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
13491411
FL		 1116 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1117 frag_end && (k == frag_buf_num - 1) ?
1118 1 : 0);
1119 desc->tx.bdtp_fe_sc_vld_ra_ri =
1120 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1121
1122 /* move ring pointer to next.*/
1123 ring_ptr_move_fw(ring, next_to_use);
1124
1125 desc_cb = &ring->desc_cb[ring->next_to_use];
1126 desc = &ring->desc[ring->next_to_use];
1127 }
76ad4f0e
S		 1128
1129 return 0;
1130}
1131
76ad4f0e
S		 1132static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1133 struct hns3_enet_ring *ring)
1134{
1135 struct sk_buff *skb = *out_skb;
1136 struct skb_frag_struct *frag;
1137 int bdnum_for_frag;
1138 int frag_num;
1139 int buf_num;
1140 int size;
1141 int i;
1142
1143 size = skb_headlen(skb);
1144 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1145
1146 frag_num = skb_shinfo(skb)->nr_frags;
1147 for (i = 0; i < frag_num; i++) {
1148 frag = &skb_shinfo(skb)->frags[i];
1149 size = skb_frag_size(frag);
1150 bdnum_for_frag =
1151 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1152 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1153 return -ENOMEM;
1154
1155 buf_num += bdnum_for_frag;
1156 }
1157
1158 if (buf_num > ring_space(ring))
1159 return -EBUSY;
1160
1161 *bnum = buf_num;
1162 return 0;
1163}
1164
1165static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1166 struct hns3_enet_ring *ring)
1167{
1168 struct sk_buff *skb = *out_skb;
1169 int buf_num;
1170
1171 /* No. of segments (plus a header) */
1172 buf_num = skb_shinfo(skb)->nr_frags + 1;
1173
91a2f02f 1174 if (unlikely(ring_space(ring) < buf_num))
76ad4f0e
S		 1175 return -EBUSY;
1176
1177 *bnum = buf_num;
1178
1179 return 0;
1180}
1181
fc09d03d 1182static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1183{
1184 struct device *dev = ring_to_dev(ring);
1185 unsigned int i;
1186
1187 for (i = 0; i < ring->desc_num; i++) {
1188 /* check if this is where we started */
1189 if (ring->next_to_use == next_to_use_orig)
1190 break;
1191
1192 /* unmap the descriptor dma address */
1193 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1194 dma_unmap_single(dev,
1195 ring->desc_cb[ring->next_to_use].dma,
1196 ring->desc_cb[ring->next_to_use].length,
1197 DMA_TO_DEVICE);
6a3bff0d 1198 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1199 dma_unmap_page(dev,
1200 ring->desc_cb[ring->next_to_use].dma,
1201 ring->desc_cb[ring->next_to_use].length,
1202 DMA_TO_DEVICE);
1203
6a3bff0d
FL		 1204 ring->desc_cb[ring->next_to_use].length = 0;
1205
76ad4f0e
S		 1206 /* rollback one */
1207 ring_ptr_move_bw(ring, next_to_use);
1208 }
1209}
1210
d43e5aca 1211netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1212{
1213 struct hns3_nic_priv *priv = netdev_priv(netdev);
1214 struct hns3_nic_ring_data *ring_data =
1215 &tx_ring_data(priv, skb->queue_mapping);
1216 struct hns3_enet_ring *ring = ring_data->ring;
76ad4f0e
S		 1217 struct netdev_queue *dev_queue;
1218 struct skb_frag_struct *frag;
1219 int next_to_use_head;
1220 int next_to_use_frag;
76ad4f0e
S		 1221 int buf_num;
1222 int seg_num;
1223 int size;
1224 int ret;
1225 int i;
1226
1227 /* Prefetch the data used later */
1228 prefetch(skb->data);
1229
1230 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1231 case -EBUSY:
1232 u64_stats_update_begin(&ring->syncp);
1233 ring->stats.tx_busy++;
1234 u64_stats_update_end(&ring->syncp);
1235
1236 goto out_net_tx_busy;
1237 case -ENOMEM:
1238 u64_stats_update_begin(&ring->syncp);
1239 ring->stats.sw_err_cnt++;
1240 u64_stats_update_end(&ring->syncp);
1241 netdev_err(netdev, "no memory to xmit!\n");
1242
1243 goto out_err_tx_ok;
1244 default:
1245 break;
1246 }
1247
1248 /* No. of segments (plus a header) */
1249 seg_num = skb_shinfo(skb)->nr_frags + 1;
1250 /* Fill the first part */
1251 size = skb_headlen(skb);
1252
1253 next_to_use_head = ring->next_to_use;
1254
91040825
PL		 1255 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1256 DESC_TYPE_SKB);
76ad4f0e 1257 if (ret)
fc09d03d 1258 goto head_fill_err;
76ad4f0e
S		 1259
1260 next_to_use_frag = ring->next_to_use;
1261 /* Fill the fragments */
1262 for (i = 1; i < seg_num; i++) {
1263 frag = &skb_shinfo(skb)->frags[i - 1];
1264 size = skb_frag_size(frag);
91040825
PL		 1265
1266 ret = priv->ops.fill_desc(ring, frag, size,
1267 seg_num - 1 == i ? 1 : 0,
1268 DESC_TYPE_PAGE);
76ad4f0e
S		 1269
1270 if (ret)
fc09d03d 1271 goto frag_fill_err;
76ad4f0e
S		 1272 }
1273
1274 /* Complete translate all packets */
1275 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1276 netdev_tx_sent_queue(dev_queue, skb->len);
1277
1278 wmb(); /* Commit all data before submit */
1279
ccc23ef3 1280 hnae3_queue_xmit(ring->tqp, buf_num);
76ad4f0e
S		 1281
1282 return NETDEV_TX_OK;
1283
fc09d03d
FL		 1284frag_fill_err:
1285 hns3_clear_desc(ring, next_to_use_frag);
76ad4f0e 1286
fc09d03d
FL		 1287head_fill_err:
1288 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1289
1290out_err_tx_ok:
1291 dev_kfree_skb_any(skb);
1292 return NETDEV_TX_OK;
1293
1294out_net_tx_busy:
1295 netif_stop_subqueue(netdev, ring_data->queue_index);
1296 smp_mb(); /* Commit all data before submit */
1297
1298 return NETDEV_TX_BUSY;
1299}
1300
1301static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1302{
9780cb97 1303 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1304 struct sockaddr *mac_addr = p;
1305 int ret;
1306
1307 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1308 return -EADDRNOTAVAIL;
1309
f37fc980
JS		 1310 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1311 netdev_info(netdev, "already using mac address %pM\n",
1312 mac_addr->sa_data);
1313 return 0;
1314 }
1315
3cbf5e2d 1316 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1317 if (ret) {
1318 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1319 return ret;
1320 }
1321
1322 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1323
1324 return 0;
1325}
1326
a185d723
XW		 1327static int hns3_nic_do_ioctl(struct net_device *netdev,
1328 struct ifreq *ifr, int cmd)
1329{
1330 struct hnae3_handle *h = hns3_get_handle(netdev);
1331
1332 if (!netif_running(netdev))
1333 return -EINVAL;
1334
1335 if (!h->ae_algo->ops->do_ioctl)
1336 return -EOPNOTSUPP;
1337
1338 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1339}
1340
76ad4f0e
S		 1341static int hns3_nic_set_features(struct net_device *netdev,
1342 netdev_features_t features)
1343{
21b6fd34 1344 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1345 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f9a7732 1346 struct hnae3_handle *h = priv->ae_handle;
5f9a7732 1347 int ret;
76ad4f0e 1348
21b6fd34 1349 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
e4c38d6e 1350 if (features & (NETIF_F_TSO | NETIF_F_TSO6))
21b6fd34 1351 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
e4c38d6e 1352 else
21b6fd34 1353 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
76ad4f0e
S		 1354 }
1355
88576b4b
JS		 1356 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1357 h->ae_algo->ops->enable_vlan_filter) {
21b6fd34
JS		 1358 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1359 h->ae_algo->ops->enable_vlan_filter(h, true);
1360 else
1361 h->ae_algo->ops->enable_vlan_filter(h, false);
1362 }
d818396d 1363
88576b4b
JS		 1364 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1365 h->ae_algo->ops->enable_hw_strip_rxvtag) {
5f9a7732
PL		 1366 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1367 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1368 else
1369 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1370
1371 if (ret)
1372 return ret;
1373 }
1374
d1f04a80
JS		 1375 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1376 if (features & NETIF_F_NTUPLE)
1377 h->ae_algo->ops->enable_fd(h, true);
1378 else
1379 h->ae_algo->ops->enable_fd(h, false);
1380 }
1381
76ad4f0e
S		 1382 netdev->features = features;
1383 return 0;
1384}
1385
9596f6f0
PL		 1386static void hns3_nic_get_stats64(struct net_device *netdev,
1387 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1388{
1389 struct hns3_nic_priv *priv = netdev_priv(netdev);
1390 int queue_num = priv->ae_handle->kinfo.num_tqps;
7a5d2a39 1391 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e
S		 1392 struct hns3_enet_ring *ring;
1393 unsigned int start;
1394 unsigned int idx;
1395 u64 tx_bytes = 0;
1396 u64 rx_bytes = 0;
1397 u64 tx_pkts = 0;
1398 u64 rx_pkts = 0;
0a83231f
JS		 1399 u64 tx_drop = 0;
1400 u64 rx_drop = 0;
76ad4f0e 1401
a3083abb
JS		 1402 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1403 return;
1404
7a5d2a39
JS		 1405 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1406
76ad4f0e
S		 1407 for (idx = 0; idx < queue_num; idx++) {
1408 /* fetch the tx stats */
1409 ring = priv->ring_data[idx].ring;
1410 do {
d36d36ce 1411 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1412 tx_bytes += ring->stats.tx_bytes;
1413 tx_pkts += ring->stats.tx_pkts;
0a83231f
JS		 1414 tx_drop += ring->stats.tx_busy;
1415 tx_drop += ring->stats.sw_err_cnt;
76ad4f0e
S		 1416 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1417
1418 /* fetch the rx stats */
1419 ring = priv->ring_data[idx + queue_num].ring;
1420 do {
d36d36ce 1421 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1422 rx_bytes += ring->stats.rx_bytes;
1423 rx_pkts += ring->stats.rx_pkts;
0a83231f
JS		 1424 rx_drop += ring->stats.non_vld_descs;
1425 rx_drop += ring->stats.err_pkt_len;
1426 rx_drop += ring->stats.l2_err;
76ad4f0e
S		 1427 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1428 }
1429
1430 stats->tx_bytes = tx_bytes;
1431 stats->tx_packets = tx_pkts;
1432 stats->rx_bytes = rx_bytes;
1433 stats->rx_packets = rx_pkts;
1434
1435 stats->rx_errors = netdev->stats.rx_errors;
1436 stats->multicast = netdev->stats.multicast;
1437 stats->rx_length_errors = netdev->stats.rx_length_errors;
1438 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
1439 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1440
1441 stats->tx_errors = netdev->stats.tx_errors;
0a83231f
JS		 1442 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
1443 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
76ad4f0e
S		 1444 stats->collisions = netdev->stats.collisions;
1445 stats->rx_over_errors = netdev->stats.rx_over_errors;
1446 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1447 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1448 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1449 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1450 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1451 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1452 stats->tx_window_errors = netdev->stats.tx_window_errors;
1453 stats->rx_compressed = netdev->stats.rx_compressed;
1454 stats->tx_compressed = netdev->stats.tx_compressed;
1455}
1456
30d240df 1457static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1458{
30d240df 1459 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
9780cb97 1460 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 1461 struct hnae3_knic_private_info *kinfo = &h->kinfo;
30d240df
YL		 1462 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1463 u8 tc = mqprio_qopt->qopt.num_tc;
1464 u16 mode = mqprio_qopt->mode;
1465 u8 hw = mqprio_qopt->qopt.hw;
1466 bool if_running;
76ad4f0e
S		 1467 int ret;
1468
30d240df
YL		 1469 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1470 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1471 return -EOPNOTSUPP;
1472
76ad4f0e
S		 1473 if (tc > HNAE3_MAX_TC)
1474 return -EINVAL;
1475
76ad4f0e
S		 1476 if (!netdev)
1477 return -EINVAL;
1478
30d240df
YL		 1479 if_running = netif_running(netdev);
1480 if (if_running) {
1481 hns3_nic_net_stop(netdev);
1482 msleep(100);
76ad4f0e
S		 1483 }
1484
30d240df
YL		 1485 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1486 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e 1487 if (ret)
30d240df
YL		 1488 goto out;
1489
30d240df
YL		 1490 ret = hns3_nic_set_real_num_queue(netdev);
1491
1492out:
1493 if (if_running)
1494 hns3_nic_net_open(netdev);
1495
1496 return ret;
76ad4f0e
S		 1497}
1498
2572ac53 1499static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1500 void *type_data)
76ad4f0e 1501{
575ed7d3 1502 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1503 return -EOPNOTSUPP;
76ad4f0e 1504
30d240df 1505 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1506}
1507
1508static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1509 __be16 proto, u16 vid)
1510{
9780cb97 1511 struct hnae3_handle *h = hns3_get_handle(netdev);
103ce052 1512 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1513 int ret = -EIO;
1514
1515 if (h->ae_algo->ops->set_vlan_filter)
1516 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1517
103ce052
YL		 1518 if (!ret)
1519 set_bit(vid, priv->active_vlans);
1520
76ad4f0e
S		 1521 return ret;
1522}
1523
1524static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1525 __be16 proto, u16 vid)
1526{
9780cb97 1527 struct hnae3_handle *h = hns3_get_handle(netdev);
103ce052 1528 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1529 int ret = -EIO;
1530
1531 if (h->ae_algo->ops->set_vlan_filter)
1532 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1533
103ce052
YL		 1534 if (!ret)
1535 clear_bit(vid, priv->active_vlans);
1536
76ad4f0e
S		 1537 return ret;
1538}
1539
abe62a63 1540static int hns3_restore_vlan(struct net_device *netdev)
103ce052
YL		 1541{
1542 struct hns3_nic_priv *priv = netdev_priv(netdev);
abe62a63 1543 int ret = 0;
103ce052 1544 u16 vid;
103ce052
YL		 1545
1546 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1547 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
abe62a63
HT		 1548 if (ret) {
1549 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n",
1550 vid, ret);
1551 return ret;
1552 }
103ce052 1553 }
abe62a63
HT		 1554
1555 return ret;
103ce052
YL		 1556}
1557
76ad4f0e
S		 1558static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1559 u8 qos, __be16 vlan_proto)
1560{
9780cb97 1561 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1562 int ret = -EIO;
1563
1564 if (h->ae_algo->ops->set_vf_vlan_filter)
1565 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1566 qos, vlan_proto);
1567
1568 return ret;
1569}
1570
a8e8b7ff
S		 1571static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1572{
9780cb97 1573 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1574 int ret;
1575
1576 if (!h->ae_algo->ops->set_mtu)
1577 return -EOPNOTSUPP;
1578
a8e8b7ff 1579 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
6a2953dd 1580 if (ret)
a8e8b7ff
S		 1581 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1582 ret);
6a2953dd
YL		 1583 else
1584 netdev->mtu = new_mtu;
fe6362f9 1585
a8e8b7ff
S		 1586 return ret;
1587}
1588
f8fa222c
L		 1589static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1590{
1591 struct hns3_nic_priv *priv = netdev_priv(ndev);
1592 struct hns3_enet_ring *tx_ring = NULL;
1593 int timeout_queue = 0;
1594 int hw_head, hw_tail;
1595 int i;
1596
1597 /* Find the stopped queue the same way the stack does */
1598 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1599 struct netdev_queue *q;
1600 unsigned long trans_start;
1601
1602 q = netdev_get_tx_queue(ndev, i);
1603 trans_start = q->trans_start;
1604 if (netif_xmit_stopped(q) &&
1605 time_after(jiffies,
1606 (trans_start + ndev->watchdog_timeo))) {
1607 timeout_queue = i;
1608 break;
1609 }
1610 }
1611
1612 if (i == ndev->num_tx_queues) {
1613 netdev_info(ndev,
1614 "no netdev TX timeout queue found, timeout count: %llu\n",
1615 priv->tx_timeout_count);
1616 return false;
1617 }
1618
1619 tx_ring = priv->ring_data[timeout_queue].ring;
1620
1621 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1622 HNS3_RING_TX_RING_HEAD_REG);
1623 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1624 HNS3_RING_TX_RING_TAIL_REG);
1625 netdev_info(ndev,
1626 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1627 priv->tx_timeout_count,
1628 timeout_queue,
1629 tx_ring->next_to_use,
1630 tx_ring->next_to_clean,
1631 hw_head,
1632 hw_tail,
1633 readl(tx_ring->tqp_vector->mask_addr));
1634
1635 return true;
1636}
1637
1638static void hns3_nic_net_timeout(struct net_device *ndev)
1639{
1640 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1641 struct hnae3_handle *h = priv->ae_handle;
1642
1643 if (!hns3_get_tx_timeo_queue_info(ndev))
1644 return;
1645
1646 priv->tx_timeout_count++;
1647
1a2f7bf2
HT		 1648 /* request the reset, and let the hclge to determine
1649 * which reset level should be done
1650 */
f8fa222c 1651 if (h->ae_algo->ops->reset_event)
538d8ba0 1652 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 1653}
1654
76ad4f0e
S		 1655static const struct net_device_ops hns3_nic_netdev_ops = {
1656 .ndo_open = hns3_nic_net_open,
1657 .ndo_stop = hns3_nic_net_stop,
1658 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1659 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1660 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
a185d723 1661 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1662 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1663 .ndo_set_features = hns3_nic_set_features,
1664 .ndo_get_stats64 = hns3_nic_get_stats64,
1665 .ndo_setup_tc = hns3_nic_setup_tc,
1666 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1667 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1668 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1669 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1670};
1671
bc59f827
FL		 1672static bool hns3_is_phys_func(struct pci_dev *pdev)
1673{
1674 u32 dev_id = pdev->device;
1675
1676 switch (dev_id) {
1677 case HNAE3_DEV_ID_GE:
1678 case HNAE3_DEV_ID_25GE:
1679 case HNAE3_DEV_ID_25GE_RDMA:
1680 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1681 case HNAE3_DEV_ID_50GE_RDMA:
1682 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1683 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1684 return true;
1685 case HNAE3_DEV_ID_100G_VF:
1686 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1687 return false;
1688 default:
1689 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1690 dev_id);
1691 }
1692
1693 return false;
1694}
1695
bc59f827
FL		 1696static void hns3_disable_sriov(struct pci_dev *pdev)
1697{
1698 /* If our VFs are assigned we cannot shut down SR-IOV
1699 * without causing issues, so just leave the hardware
1700 * available but disabled
1701 */
1702 if (pci_vfs_assigned(pdev)) {
1703 dev_warn(&pdev->dev,
1704 "disabling driver while VFs are assigned\n");
1705 return;
1706 }
1707
1708 pci_disable_sriov(pdev);
1709}
1710
10a954bc
JS		 1711static void hns3_get_dev_capability(struct pci_dev *pdev,
1712 struct hnae3_ae_dev *ae_dev)
1713{
73f88b00 1714 if (pdev->revision >= 0x21) {
10a954bc 1715 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
73f88b00
PL		 1716 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1717 }
10a954bc
JS		 1718}
1719
76ad4f0e
S		 1720/* hns3_probe - Device initialization routine
1721 * @pdev: PCI device information struct
1722 * @ent: entry in hns3_pci_tbl
1723 *
1724 * hns3_probe initializes a PF identified by a pci_dev structure.
1725 * The OS initialization, configuring of the PF private structure,
1726 * and a hardware reset occur.
1727 *
1728 * Returns 0 on success, negative on failure
1729 */
1730static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1731{
1732 struct hnae3_ae_dev *ae_dev;
1733 int ret;
1734
1735 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1736 GFP_KERNEL);
1737 if (!ae_dev) {
1738 ret = -ENOMEM;
1739 return ret;
1740 }
1741
1742 ae_dev->pdev = pdev;
e92a0843 1743 ae_dev->flag = ent->driver_data;
76ad4f0e 1744 ae_dev->dev_type = HNAE3_DEV_KNIC;
7ce98982 1745 ae_dev->reset_type = HNAE3_NONE_RESET;
10a954bc 1746 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S		 1747 pci_set_drvdata(pdev, ae_dev);
1748
fb919349 1749 hnae3_register_ae_dev(ae_dev);
bc59f827 1750
bc59f827 1751 return 0;
76ad4f0e
S		 1752}
1753
1754/* hns3_remove - Device removal routine
1755 * @pdev: PCI device information struct
1756 */
1757static void hns3_remove(struct pci_dev *pdev)
1758{
1759 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1760
bc59f827
FL		 1761 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1762 hns3_disable_sriov(pdev);
1763
76ad4f0e 1764 hnae3_unregister_ae_dev(ae_dev);
142e1137 1765 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 1766}
1767
cfeff578
PL		 1768/**
1769 * hns3_pci_sriov_configure
1770 * @pdev: pointer to a pci_dev structure
1771 * @num_vfs: number of VFs to allocate
1772 *
1773 * Enable or change the number of VFs. Called when the user updates the number
1774 * of VFs in sysfs.
1775 **/
baff3ed7 1776static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
cfeff578
PL		 1777{
1778 int ret;
1779
1780 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1781 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1782 return -EINVAL;
1783 }
1784
1785 if (num_vfs) {
1786 ret = pci_enable_sriov(pdev, num_vfs);
1787 if (ret)
1788 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
baff3ed7
SM		 1789 else
1790 return num_vfs;
cfeff578
PL		 1791 } else if (!pci_vfs_assigned(pdev)) {
1792 pci_disable_sriov(pdev);
1793 } else {
1794 dev_warn(&pdev->dev,
1795 "Unable to free VFs because some are assigned to VMs.\n");
1796 }
1797
1798 return 0;
1799}
1800
4f043c3e
YL		 1801static void hns3_shutdown(struct pci_dev *pdev)
1802{
1803 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1804
1805 hnae3_unregister_ae_dev(ae_dev);
1806 devm_kfree(&pdev->dev, ae_dev);
1807 pci_set_drvdata(pdev, NULL);
1808
1809 if (system_state == SYSTEM_POWER_OFF)
1810 pci_set_power_state(pdev, PCI_D3hot);
1811}
1812
00bb612a
SJ		 1813static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1814 pci_channel_state_t state)
1815{
1816 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1817 pci_ers_result_t ret;
1818
1819 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1820
1821 if (state == pci_channel_io_perm_failure)
1822 return PCI_ERS_RESULT_DISCONNECT;
1823
1824 if (!ae_dev) {
1825 dev_err(&pdev->dev,
1826 "Can't recover - error happened during device init\n");
1827 return PCI_ERS_RESULT_NONE;
1828 }
1829
af72a21f
SJ		 1830 if (ae_dev->ops->handle_hw_ras_error)
1831 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
00bb612a
SJ		 1832 else
1833 return PCI_ERS_RESULT_NONE;
1834
1835 return ret;
1836}
1837
538d8ba0
SJ		 1838static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1839{
1840 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1841 struct device *dev = &pdev->dev;
1842
1843 dev_info(dev, "requesting reset due to PCI error\n");
1844
1845 /* request the reset */
1846 if (ae_dev->ops->reset_event) {
1847 ae_dev->ops->reset_event(pdev, NULL);
1848 return PCI_ERS_RESULT_RECOVERED;
1849 }
1850
1851 return PCI_ERS_RESULT_DISCONNECT;
1852}
1853
26977990
HT		 1854static void hns3_reset_prepare(struct pci_dev *pdev)
1855{
1856 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1857
1858 dev_info(&pdev->dev, "hns3 flr prepare\n");
1859 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1860 ae_dev->ops->flr_prepare(ae_dev);
1861}
1862
1863static void hns3_reset_done(struct pci_dev *pdev)
1864{
1865 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1866
1867 dev_info(&pdev->dev, "hns3 flr done\n");
1868 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
1869 ae_dev->ops->flr_done(ae_dev);
1870}
1871
00bb612a
SJ		 1872static const struct pci_error_handlers hns3_err_handler = {
1873 .error_detected = hns3_error_detected,
538d8ba0 1874 .slot_reset = hns3_slot_reset,
26977990
HT		 1875 .reset_prepare = hns3_reset_prepare,
1876 .reset_done = hns3_reset_done,
00bb612a
SJ		 1877};
1878
76ad4f0e
S		 1879static struct pci_driver hns3_driver = {
1880 .name = hns3_driver_name,
1881 .id_table = hns3_pci_tbl,
1882 .probe = hns3_probe,
1883 .remove = hns3_remove,
4f043c3e 1884 .shutdown = hns3_shutdown,
cfeff578 1885 .sriov_configure = hns3_pci_sriov_configure,
00bb612a 1886 .err_handler = &hns3_err_handler,
76ad4f0e
S		 1887};
1888
1889/* set default feature to hns3 */
1890static void hns3_set_default_feature(struct net_device *netdev)
1891{
a4c378bb
PL		 1892 struct hnae3_handle *h = hns3_get_handle(netdev);
1893 struct pci_dev *pdev = h->pdev;
1894
76ad4f0e
S		 1895 netdev->priv_flags |= IFF_UNICAST_FLT;
1896
1897 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1898 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1899 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1900 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
0361a8bc 1901 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1902
1903 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1904
1905 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1906
1907 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1908 NETIF_F_HW_VLAN_CTAG_FILTER |
5f9a7732 1909 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1910 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1911 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1912 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
0361a8bc 1913 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1914
1915 netdev->vlan_features |=
1916 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1917 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1918 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1919 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
0361a8bc 1920 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1921
1922 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3849d494 1923 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1924 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1925 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1926 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
0361a8bc 1927 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
a4c378bb 1928
d1f04a80 1929 if (pdev->revision >= 0x21) {
a4c378bb 1930 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d1f04a80
JS		 1931
1932 if (!(h->flags & HNAE3_SUPPORT_VF)) {
1933 netdev->hw_features |= NETIF_F_NTUPLE;
1934 netdev->features |= NETIF_F_NTUPLE;
1935 }
1936 }
76ad4f0e
S		 1937}
1938
1939static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1940 struct hns3_desc_cb *cb)
1941{
ccc23ef3 1942 unsigned int order = hnae3_page_order(ring);
76ad4f0e
S		 1943 struct page *p;
1944
1945 p = dev_alloc_pages(order);
1946 if (!p)
1947 return -ENOMEM;
1948
1949 cb->priv = p;
1950 cb->page_offset = 0;
1951 cb->reuse_flag = 0;
1952 cb->buf = page_address(p);
ccc23ef3 1953 cb->length = hnae3_page_size(ring);
76ad4f0e
S		 1954 cb->type = DESC_TYPE_PAGE;
1955
76ad4f0e
S		 1956 return 0;
1957}
1958
1959static void hns3_free_buffer(struct hns3_enet_ring *ring,
1960 struct hns3_desc_cb *cb)
1961{
1962 if (cb->type == DESC_TYPE_SKB)
1963 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1964 else if (!HNAE3_IS_TX_RING(ring))
1965 put_page((struct page *)cb->priv);
1966 memset(cb, 0, sizeof(*cb));
1967}
1968
1969static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1970{
1971 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1972 cb->length, ring_to_dma_dir(ring));
1973
39bbc873 1974 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 1975 return -EIO;
1976
1977 return 0;
1978}
1979
1980static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
1981 struct hns3_desc_cb *cb)
1982{
1983 if (cb->type == DESC_TYPE_SKB)
1984 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
1985 ring_to_dma_dir(ring));
6a3bff0d 1986 else if (cb->length)
76ad4f0e
S		 1987 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
1988 ring_to_dma_dir(ring));
1989}
1990
1991static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
1992{
1993 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
1994 ring->desc[i].addr = 0;
1995}
1996
1997static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
1998{
1999 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2000
2001 if (!ring->desc_cb[i].dma)
2002 return;
2003
2004 hns3_buffer_detach(ring, i);
2005 hns3_free_buffer(ring, cb);
2006}
2007
2008static void hns3_free_buffers(struct hns3_enet_ring *ring)
2009{
2010 int i;
2011
2012 for (i = 0; i < ring->desc_num; i++)
2013 hns3_free_buffer_detach(ring, i);
2014}
2015
2016/* free desc along with its attached buffer */
2017static void hns3_free_desc(struct hns3_enet_ring *ring)
2018{
d61c1a80
HT		 2019 int size = ring->desc_num * sizeof(ring->desc[0]);
2020
76ad4f0e
S		 2021 hns3_free_buffers(ring);
2022
d61c1a80
HT		 2023 if (ring->desc) {
2024 dma_free_coherent(ring_to_dev(ring), size,
2025 ring->desc, ring->desc_dma_addr);
2026 ring->desc = NULL;
2027 }
76ad4f0e
S		 2028}
2029
2030static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2031{
2032 int size = ring->desc_num * sizeof(ring->desc[0]);
2033
d61c1a80
HT		 2034 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size,
2035 &ring->desc_dma_addr,
2036 GFP_KERNEL);
76ad4f0e
S		 2037 if (!ring->desc)
2038 return -ENOMEM;
2039
76ad4f0e
S		 2040 return 0;
2041}
2042
2043static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2044 struct hns3_desc_cb *cb)
2045{
2046 int ret;
2047
2048 ret = hns3_alloc_buffer(ring, cb);
2049 if (ret)
2050 goto out;
2051
2052 ret = hns3_map_buffer(ring, cb);
2053 if (ret)
2054 goto out_with_buf;
2055
2056 return 0;
2057
2058out_with_buf:
564883bb 2059 hns3_free_buffer(ring, cb);
76ad4f0e
S		 2060out:
2061 return ret;
2062}
2063
2064static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2065{
2066 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2067
2068 if (ret)
2069 return ret;
2070
2071 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2072
2073 return 0;
2074}
2075
2076/* Allocate memory for raw pkg, and map with dma */
2077static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2078{
2079 int i, j, ret;
2080
2081 for (i = 0; i < ring->desc_num; i++) {
2082 ret = hns3_alloc_buffer_attach(ring, i);
2083 if (ret)
2084 goto out_buffer_fail;
2085 }
2086
2087 return 0;
2088
2089out_buffer_fail:
2090 for (j = i - 1; j >= 0; j--)
2091 hns3_free_buffer_detach(ring, j);
2092 return ret;
2093}
2094
2095/* detach a in-used buffer and replace with a reserved one */
2096static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2097 struct hns3_desc_cb *res_cb)
2098{
b9077428 2099 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2100 ring->desc_cb[i] = *res_cb;
2101 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
4169a686 2102 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2103}
2104
2105static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2106{
2107 ring->desc_cb[i].reuse_flag = 0;
2108 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
2109 + ring->desc_cb[i].page_offset);
4169a686 2110 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2111}
2112
1f9c1dcb
YL		 2113static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2114 int *bytes, int *pkts)
76ad4f0e 2115{
a41def26
YL		 2116 int ntc = ring->next_to_clean;
2117 struct hns3_desc_cb *desc_cb;
76ad4f0e 2118
1f9c1dcb
YL		 2119 while (head != ntc) {
2120 desc_cb = &ring->desc_cb[ntc];
2121 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2122 (*bytes) += desc_cb->length;
2123 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2124 hns3_free_buffer_detach(ring, ntc);
76ad4f0e 2125
1f9c1dcb
YL		 2126 if (++ntc == ring->desc_num)
2127 ntc = 0;
2128
2129 /* Issue prefetch for next Tx descriptor */
2130 prefetch(&ring->desc_cb[ntc]);
2131 }
a41def26
YL		 2132
2133 /* This smp_store_release() pairs with smp_load_acquire() in
2134 * ring_space called by hns3_nic_net_xmit.
2135 */
2136 smp_store_release(&ring->next_to_clean, ntc);
76ad4f0e
S		 2137}
2138
2139static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2140{
2141 int u = ring->next_to_use;
2142 int c = ring->next_to_clean;
2143
2144 if (unlikely(h > ring->desc_num))
2145 return 0;
2146
2147 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2148}
2149
6a38a95f 2150void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 2151{
2152 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
c3e4287e 2153 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2154 struct netdev_queue *dev_queue;
2155 int bytes, pkts;
2156 int head;
2157
2158 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2159 rmb(); /* Make sure head is ready before touch any data */
2160
2161 if (is_ring_empty(ring) || head == ring->next_to_clean)
6a38a95f 2162 return; /* no data to poll */
76ad4f0e 2163
2ea8667b 2164 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S		 2165 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2166 ring->next_to_use, ring->next_to_clean);
2167
2168 u64_stats_update_begin(&ring->syncp);
2169 ring->stats.io_err_cnt++;
2170 u64_stats_update_end(&ring->syncp);
6a38a95f 2171 return;
76ad4f0e
S		 2172 }
2173
2174 bytes = 0;
2175 pkts = 0;
1f9c1dcb 2176 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
76ad4f0e
S		 2177
2178 ring->tqp_vector->tx_group.total_bytes += bytes;
2179 ring->tqp_vector->tx_group.total_packets += pkts;
2180
2181 u64_stats_update_begin(&ring->syncp);
2182 ring->stats.tx_bytes += bytes;
2183 ring->stats.tx_pkts += pkts;
2184 u64_stats_update_end(&ring->syncp);
2185
2186 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2187 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2188
2189 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2190 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2191 /* Make sure that anybody stopping the queue after this
2192 * sees the new next_to_clean.
2193 */
2194 smp_mb();
c3e4287e
JS		 2195 if (netif_tx_queue_stopped(dev_queue) &&
2196 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2197 netif_tx_wake_queue(dev_queue);
2198 ring->stats.restart_queue++;
2199 }
2200 }
76ad4f0e
S		 2201}
2202
2203static int hns3_desc_unused(struct hns3_enet_ring *ring)
2204{
2205 int ntc = ring->next_to_clean;
2206 int ntu = ring->next_to_use;
2207
2208 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2209}
2210
2211static void
2212hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2213{
2214 struct hns3_desc_cb *desc_cb;
2215 struct hns3_desc_cb res_cbs;
2216 int i, ret;
2217
2218 for (i = 0; i < cleand_count; i++) {
2219 desc_cb = &ring->desc_cb[ring->next_to_use];
2220 if (desc_cb->reuse_flag) {
2221 u64_stats_update_begin(&ring->syncp);
2222 ring->stats.reuse_pg_cnt++;
2223 u64_stats_update_end(&ring->syncp);
2224
2225 hns3_reuse_buffer(ring, ring->next_to_use);
2226 } else {
2227 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2228 if (ret) {
2229 u64_stats_update_begin(&ring->syncp);
2230 ring->stats.sw_err_cnt++;
2231 u64_stats_update_end(&ring->syncp);
2232
2233 netdev_err(ring->tqp->handle->kinfo.netdev,
2234 "hnae reserve buffer map failed.\n");
2235 break;
2236 }
2237 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2238 }
2239
2240 ring_ptr_move_fw(ring, next_to_use);
2241 }
2242
2243 wmb(); /* Make all data has been write before submit */
2244 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2245}
2246
76ad4f0e
S		 2247static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2248 struct hns3_enet_ring *ring, int pull_len,
2249 struct hns3_desc_cb *desc_cb)
2250{
2251 struct hns3_desc *desc;
e56a15b7
HT		 2252 u32 truesize;
2253 int size;
76ad4f0e
S		 2254 int last_offset;
2255 bool twobufs;
2256
2257 twobufs = ((PAGE_SIZE < 8192) &&
ccc23ef3 2258 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
76ad4f0e
S		 2259
2260 desc = &ring->desc[ring->next_to_clean];
2261 size = le16_to_cpu(desc->rx.size);
2262
ccc23ef3 2263 truesize = hnae3_buf_size(ring);
885a882a
PL		 2264
2265 if (!twobufs)
ccc23ef3 2266 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
76ad4f0e
S		 2267
2268 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
885a882a 2269 size - pull_len, truesize);
76ad4f0e
S		 2270
2271 /* Avoid re-using remote pages,flag default unreuse */
2272 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2273 return;
2274
2275 if (twobufs) {
2276 /* If we are only owner of page we can reuse it */
2277 if (likely(page_count(desc_cb->priv) == 1)) {
2278 /* Flip page offset to other buffer */
2279 desc_cb->page_offset ^= truesize;
2280
2281 desc_cb->reuse_flag = 1;
2282 /* bump ref count on page before it is given*/
2283 get_page(desc_cb->priv);
2284 }
2285 return;
2286 }
2287
2288 /* Move offset up to the next cache line */
2289 desc_cb->page_offset += truesize;
2290
2291 if (desc_cb->page_offset <= last_offset) {
2292 desc_cb->reuse_flag = 1;
2293 /* Bump ref count on page before it is given*/
2294 get_page(desc_cb->priv);
2295 }
2296}
2297
2298static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2299 struct hns3_desc *desc)
2300{
2301 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2302 int l3_type, l4_type;
2303 u32 bd_base_info;
2304 int ol4_type;
2305 u32 l234info;
2306
2307 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2308 l234info = le32_to_cpu(desc->rx.l234_info);
2309
2310 skb->ip_summed = CHECKSUM_NONE;
2311
2312 skb_checksum_none_assert(skb);
2313
2314 if (!(netdev->features & NETIF_F_RXCSUM))
2315 return;
2316
5337b725
PL		 2317 /* We MUST enable hardware checksum before enabling hardware GRO */
2318 if (skb_shinfo(skb)->gso_size) {
2319 skb->ip_summed = CHECKSUM_UNNECESSARY;
2320 return;
2321 }
2322
76ad4f0e 2323 /* check if hardware has done checksum */
ccc23ef3 2324 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
76ad4f0e
S		 2325 return;
2326
ccc23ef3
PL		 2327 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2328 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2329 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2330 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
76ad4f0e
S		 2331 u64_stats_update_begin(&ring->syncp);
2332 ring->stats.l3l4_csum_err++;
2333 u64_stats_update_end(&ring->syncp);
2334
2335 return;
2336 }
2337
ccc23ef3
PL		 2338 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2339 HNS3_RXD_L3ID_S);
2340 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2341 HNS3_RXD_L4ID_S);
76ad4f0e 2342
ccc23ef3
PL		 2343 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2344 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2345 switch (ol4_type) {
2346 case HNS3_OL4_TYPE_MAC_IN_UDP:
2347 case HNS3_OL4_TYPE_NVGRE:
2348 skb->csum_level = 1;
64061deb 2349 /* fall through */
76ad4f0e
S		 2350 case HNS3_OL4_TYPE_NO_TUN:
2351 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
ffa051fa
PL		 2352 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2353 l3_type == HNS3_L3_TYPE_IPV6) &&
2354 (l4_type == HNS3_L4_TYPE_UDP ||
2355 l4_type == HNS3_L4_TYPE_TCP ||
2356 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2357 skb->ip_summed = CHECKSUM_UNNECESSARY;
2358 break;
085920ba
JS		 2359 default:
2360 break;
76ad4f0e
S		 2361 }
2362}
2363
d43e5aca
YL		 2364static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2365{
4110bcf6
PL		 2366 if (skb_has_frag_list(skb))
2367 napi_gro_flush(&ring->tqp_vector->napi, false);
2368
d43e5aca
YL		 2369 napi_gro_receive(&ring->tqp_vector->napi, skb);
2370}
2371
34456a7c
JS		 2372static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2373 struct hns3_desc *desc, u32 l234info,
2374 u16 *vlan_tag)
1e8f8bd3
PL		 2375{
2376 struct pci_dev *pdev = ring->tqp->handle->pdev;
1e8f8bd3
PL		 2377
2378 if (pdev->revision == 0x20) {
34456a7c
JS		 2379 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2380 if (!(*vlan_tag & VLAN_VID_MASK))
2381 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
1e8f8bd3 2382
34456a7c 2383 return (*vlan_tag != 0);
1e8f8bd3
PL		 2384 }
2385
2386#define HNS3_STRP_OUTER_VLAN 0x1
2387#define HNS3_STRP_INNER_VLAN 0x2
2388
ccc23ef3
PL		 2389 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2390 HNS3_RXD_STRP_TAGP_S)) {
1e8f8bd3 2391 case HNS3_STRP_OUTER_VLAN:
34456a7c
JS		 2392 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2393 return true;
1e8f8bd3 2394 case HNS3_STRP_INNER_VLAN:
34456a7c
JS		 2395 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2396 return true;
1e8f8bd3 2397 default:
34456a7c 2398 return false;
1e8f8bd3 2399 }
1e8f8bd3
PL		 2400}
2401
72b50a78
PL		 2402static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length,
2403 unsigned char *va)
2404{
2405#define HNS3_NEED_ADD_FRAG 1
2406 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2407 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2408 struct sk_buff *skb;
2409
2410 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2411 skb = ring->skb;
2412 if (unlikely(!skb)) {
2413 netdev_err(netdev, "alloc rx skb fail\n");
2414
2415 u64_stats_update_begin(&ring->syncp);
2416 ring->stats.sw_err_cnt++;
2417 u64_stats_update_end(&ring->syncp);
2418
2419 return -ENOMEM;
2420 }
2421
2422 prefetchw(skb->data);
2423
2424 ring->pending_buf = 1;
4110bcf6
PL		 2425 ring->frag_num = 0;
2426 ring->tail_skb = NULL;
72b50a78
PL		 2427 if (length <= HNS3_RX_HEAD_SIZE) {
2428 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2429
2430 /* We can reuse buffer as-is, just make sure it is local */
2431 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2432 desc_cb->reuse_flag = 1;
2433 else /* This page cannot be reused so discard it */
2434 put_page(desc_cb->priv);
2435
2436 ring_ptr_move_fw(ring, next_to_clean);
2437 return 0;
2438 }
2439 u64_stats_update_begin(&ring->syncp);
2440 ring->stats.seg_pkt_cnt++;
2441 u64_stats_update_end(&ring->syncp);
2442
2443 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2444 __skb_put(skb, ring->pull_len);
4110bcf6 2445 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
72b50a78
PL		 2446 desc_cb);
2447 ring_ptr_move_fw(ring, next_to_clean);
2448
2449 return HNS3_NEED_ADD_FRAG;
2450}
2451
2452static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2453 struct sk_buff **out_skb, bool pending)
2454{
2455 struct sk_buff *skb = *out_skb;
4110bcf6
PL		 2456 struct sk_buff *head_skb = *out_skb;
2457 struct sk_buff *new_skb;
72b50a78
PL		 2458 struct hns3_desc_cb *desc_cb;
2459 struct hns3_desc *pre_desc;
2460 u32 bd_base_info;
2461 int pre_bd;
2462
2463 /* if there is pending bd, the SW param next_to_clean has moved
2464 * to next and the next is NULL
2465 */
2466 if (pending) {
2467 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2468 ring->desc_num;
2469 pre_desc = &ring->desc[pre_bd];
2470 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2471 } else {
2472 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2473 }
2474
2475 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2476 desc = &ring->desc[ring->next_to_clean];
2477 desc_cb = &ring->desc_cb[ring->next_to_clean];
2478 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2ed550c5
JS		 2479 /* make sure HW write desc complete */
2480 dma_rmb();
72b50a78
PL		 2481 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))
2482 return -ENXIO;
2483
4110bcf6
PL		 2484 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2485 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2486 HNS3_RX_HEAD_SIZE);
2487 if (unlikely(!new_skb)) {
2488 netdev_err(ring->tqp->handle->kinfo.netdev,
2489 "alloc rx skb frag fail\n");
2490 return -ENXIO;
2491 }
2492 ring->frag_num = 0;
2493
2494 if (ring->tail_skb) {
2495 ring->tail_skb->next = new_skb;
2496 ring->tail_skb = new_skb;
2497 } else {
2498 skb_shinfo(skb)->frag_list = new_skb;
2499 ring->tail_skb = new_skb;
2500 }
2501 }
2502
2503 if (ring->tail_skb) {
2504 head_skb->truesize += hnae3_buf_size(ring);
2505 head_skb->data_len += le16_to_cpu(desc->rx.size);
2506 head_skb->len += le16_to_cpu(desc->rx.size);
2507 skb = ring->tail_skb;
2508 }
2509
2510 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
72b50a78
PL		 2511 ring_ptr_move_fw(ring, next_to_clean);
2512 ring->pending_buf++;
2513 }
2514
2515 return 0;
2516}
2517
5337b725
PL		 2518static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info,
2519 u32 bd_base_info)
2520{
2521 u16 gro_count;
2522 u32 l3_type;
2523
2524 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M,
2525 HNS3_RXD_GRO_COUNT_S);
2526 /* if there is no HW GRO, do not set gro params */
2527 if (!gro_count)
2528 return;
2529
2530 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
2531 * to skb_shinfo(skb)->gso_segs
2532 */
2533 NAPI_GRO_CB(skb)->count = gro_count;
2534
2535 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2536 HNS3_RXD_L3ID_S);
2537 if (l3_type == HNS3_L3_TYPE_IPV4)
2538 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2539 else if (l3_type == HNS3_L3_TYPE_IPV6)
2540 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2541 else
2542 return;
2543
2544 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2545 HNS3_RXD_GRO_SIZE_M,
2546 HNS3_RXD_GRO_SIZE_S);
2547 if (skb_shinfo(skb)->gso_size)
2548 tcp_gro_complete(skb);
2549}
2550
8e4c877d
PL		 2551static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2552 struct sk_buff *skb)
2553{
8e4c877d
PL		 2554 struct hnae3_handle *handle = ring->tqp->handle;
2555 enum pkt_hash_types rss_type;
023a793f
PL		 2556 struct hns3_desc *desc;
2557 int last_bd;
2558
2559 /* When driver handle the rss type, ring->next_to_clean indicates the
2560 * first descriptor of next packet, need -1 here.
2561 */
2562 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num;
2563 desc = &ring->desc[last_bd];
8e4c877d
PL		 2564
2565 if (le32_to_cpu(desc->rx.rss_hash))
2566 rss_type = handle->kinfo.rss_type;
2567 else
2568 rss_type = PKT_HASH_TYPE_NONE;
2569
2570 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type);
2571}
2572
76ad4f0e 2573static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
72b50a78 2574 struct sk_buff **out_skb)
76ad4f0e
S		 2575{
2576 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
72b50a78 2577 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 2578 struct hns3_desc_cb *desc_cb;
2579 struct hns3_desc *desc;
76ad4f0e 2580 u32 bd_base_info;
76ad4f0e
S		 2581 u32 l234info;
2582 int length;
72b50a78 2583 int ret;
76ad4f0e
S		 2584
2585 desc = &ring->desc[ring->next_to_clean];
2586 desc_cb = &ring->desc_cb[ring->next_to_clean];
2587
2588 prefetch(desc);
2589
ca61f05e 2590 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2591 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 2592
2593 /* Check valid BD */
ccc23ef3 2594 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
72b50a78 2595 return -ENXIO;
76ad4f0e 2596
72b50a78
PL		 2597 if (!skb)
2598 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
76ad4f0e
S		 2599
2600 /* Prefetch first cache line of first page
2601 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2602 * line size is 64B so need to prefetch twice to make it 128B. But in
2603 * actual we can have greater size of caches with 128B Level 1 cache
2604 * lines. In such a case, single fetch would suffice to cache in the
2605 * relevant part of the header.
2606 */
72b50a78 2607 prefetch(ring->va);
76ad4f0e 2608#if L1_CACHE_BYTES < 128
72b50a78 2609 prefetch(ring->va + L1_CACHE_BYTES);
76ad4f0e
S		 2610#endif
2611
72b50a78
PL		 2612 if (!skb) {
2613 ret = hns3_alloc_skb(ring, length, ring->va);
2614 *out_skb = skb = ring->skb;
76ad4f0e 2615
72b50a78
PL		 2616 if (ret < 0) /* alloc buffer fail */
2617 return ret;
2618 if (ret > 0) { /* need add frag */
2619 ret = hns3_add_frag(ring, desc, &skb, false);
2620 if (ret)
2621 return ret;
76ad4f0e 2622
72b50a78
PL		 2623 /* As the head data may be changed when GRO enable, copy
2624 * the head data in after other data rx completed
2625 */
2626 memcpy(skb->data, ring->va,
2627 ALIGN(ring->pull_len, sizeof(long)));
2628 }
76ad4f0e 2629 } else {
72b50a78
PL		 2630 ret = hns3_add_frag(ring, desc, &skb, true);
2631 if (ret)
2632 return ret;
76ad4f0e 2633
72b50a78
PL		 2634 /* As the head data may be changed when GRO enable, copy
2635 * the head data in after other data rx completed
2636 */
2637 memcpy(skb->data, ring->va,
2638 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e
S		 2639 }
2640
928d369a 2641 l234info = le32_to_cpu(desc->rx.l234_info);
72b50a78 2642 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
928d369a 2643
ca61f05e
PL		 2644 /* Based on hw strategy, the tag offloaded will be stored at
2645 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2646 * in one layer tag case.
2647 */
2648 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2649 u16 vlan_tag;
2650
34456a7c 2651 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
ca61f05e
PL		 2652 __vlan_hwaccel_put_tag(skb,
2653 htons(ETH_P_8021Q),
2654 vlan_tag);
2655 }
2656
ccc23ef3 2657 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
76ad4f0e
S		 2658 u64_stats_update_begin(&ring->syncp);
2659 ring->stats.non_vld_descs++;
2660 u64_stats_update_end(&ring->syncp);
2661
2662 dev_kfree_skb_any(skb);
2663 return -EINVAL;
2664 }
2665
2666 if (unlikely((!desc->rx.pkt_len) ||
ccc23ef3 2667 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
76ad4f0e
S		 2668 u64_stats_update_begin(&ring->syncp);
2669 ring->stats.err_pkt_len++;
2670 u64_stats_update_end(&ring->syncp);
2671
2672 dev_kfree_skb_any(skb);
2673 return -EFAULT;
2674 }
2675
ccc23ef3 2676 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
76ad4f0e
S		 2677 u64_stats_update_begin(&ring->syncp);
2678 ring->stats.l2_err++;
2679 u64_stats_update_end(&ring->syncp);
2680
2681 dev_kfree_skb_any(skb);
2682 return -EFAULT;
2683 }
2684
2685 u64_stats_update_begin(&ring->syncp);
2686 ring->stats.rx_pkts++;
2687 ring->stats.rx_bytes += skb->len;
2688 u64_stats_update_end(&ring->syncp);
2689
2690 ring->tqp_vector->rx_group.total_bytes += skb->len;
2691
5337b725
PL		 2692 /* This is needed in order to enable forwarding support */
2693 hns3_set_gro_param(skb, l234info, bd_base_info);
2694
76ad4f0e 2695 hns3_rx_checksum(ring, skb, desc);
72b50a78 2696 *out_skb = skb;
8e4c877d
PL		 2697 hns3_set_rx_skb_rss_type(ring, skb);
2698
76ad4f0e
S		 2699 return 0;
2700}
2701
d43e5aca
YL		 2702int hns3_clean_rx_ring(
2703 struct hns3_enet_ring *ring, int budget,
2704 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2705{
2706#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2707 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2708 int recv_pkts, recv_bds, clean_count, err;
72b50a78
PL		 2709 int unused_count = hns3_desc_unused(ring) - ring->pending_buf;
2710 struct sk_buff *skb = ring->skb;
2711 int num;
76ad4f0e
S		 2712
2713 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2714 rmb(); /* Make sure num taken effect before the other data is touched */
2715
2716 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2717 num -= unused_count;
2718
2719 while (recv_pkts < budget && recv_bds < num) {
2720 /* Reuse or realloc buffers */
2721 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2722 hns3_nic_alloc_rx_buffers(ring,
2723 clean_count + unused_count);
2724 clean_count = 0;
72b50a78
PL		 2725 unused_count = hns3_desc_unused(ring) -
2726 ring->pending_buf;
76ad4f0e
S		 2727 }
2728
2729 /* Poll one pkt */
72b50a78 2730 err = hns3_handle_rx_bd(ring, &skb);
76ad4f0e
S		 2731 if (unlikely(!skb)) /* This fault cannot be repaired */
2732 goto out;
2733
72b50a78
PL		 2734 if (err == -ENXIO) { /* Do not get FE for the packet */
2735 goto out;
2736 } else if (unlikely(err)) { /* Do jump the err */
2737 recv_bds += ring->pending_buf;
2738 clean_count += ring->pending_buf;
2739 ring->skb = NULL;
2740 ring->pending_buf = 0;
76ad4f0e
S		 2741 continue;
2742 }
2743
2744 /* Do update ip stack process */
2745 skb->protocol = eth_type_trans(skb, netdev);
d43e5aca 2746 rx_fn(ring, skb);
72b50a78
PL		 2747 recv_bds += ring->pending_buf;
2748 clean_count += ring->pending_buf;
2749 ring->skb = NULL;
2750 ring->pending_buf = 0;
76ad4f0e
S		 2751
2752 recv_pkts++;
2753 }
2754
2755out:
2756 /* Make all data has been write before submit */
2757 if (clean_count + unused_count > 0)
2758 hns3_nic_alloc_rx_buffers(ring,
2759 clean_count + unused_count);
2760
2761 return recv_pkts;
2762}
2763
2764static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2765{
50477f37
FL		 2766 struct hns3_enet_tqp_vector *tqp_vector =
2767 ring_group->ring->tqp_vector;
76ad4f0e 2768 enum hns3_flow_level_range new_flow_level;
50477f37
FL		 2769 int packets_per_msecs;
2770 int bytes_per_msecs;
2771 u32 time_passed_ms;
76ad4f0e 2772 u16 new_int_gl;
76ad4f0e 2773
3f58e29e 2774 if (!tqp_vector->last_jiffies)
76ad4f0e
S		 2775 return false;
2776
2777 if (ring_group->total_packets == 0) {
d420d2de
YL		 2778 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2779 ring_group->coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 2780 return true;
2781 }
2782
2783 /* Simple throttlerate management
2784 * 0-10MB/s lower (50000 ints/s)
2785 * 10-20MB/s middle (20000 ints/s)
2786 * 20-1249MB/s high (18000 ints/s)
2787 * > 40000pps ultra (8000 ints/s)
2788 */
d420d2de
YL		 2789 new_flow_level = ring_group->coal.flow_level;
2790 new_int_gl = ring_group->coal.int_gl;
50477f37
FL		 2791 time_passed_ms =
2792 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2793
2794 if (!time_passed_ms)
2795 return false;
2796
2797 do_div(ring_group->total_packets, time_passed_ms);
2798 packets_per_msecs = ring_group->total_packets;
2799
2800 do_div(ring_group->total_bytes, time_passed_ms);
2801 bytes_per_msecs = ring_group->total_bytes;
2802
2803#define HNS3_RX_LOW_BYTE_RATE 10000
2804#define HNS3_RX_MID_BYTE_RATE 20000
76ad4f0e
S		 2805
2806 switch (new_flow_level) {
2807 case HNS3_FLOW_LOW:
50477f37 2808 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2809 new_flow_level = HNS3_FLOW_MID;
2810 break;
2811 case HNS3_FLOW_MID:
50477f37 2812 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2813 new_flow_level = HNS3_FLOW_HIGH;
50477f37 2814 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2815 new_flow_level = HNS3_FLOW_LOW;
2816 break;
2817 case HNS3_FLOW_HIGH:
2818 case HNS3_FLOW_ULTRA:
2819 default:
50477f37 2820 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2821 new_flow_level = HNS3_FLOW_MID;
2822 break;
2823 }
2824
50477f37
FL		 2825#define HNS3_RX_ULTRA_PACKET_RATE 40
2826
2827 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2828 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 2829 new_flow_level = HNS3_FLOW_ULTRA;
2830
2831 switch (new_flow_level) {
2832 case HNS3_FLOW_LOW:
2833 new_int_gl = HNS3_INT_GL_50K;
2834 break;
2835 case HNS3_FLOW_MID:
2836 new_int_gl = HNS3_INT_GL_20K;
2837 break;
2838 case HNS3_FLOW_HIGH:
2839 new_int_gl = HNS3_INT_GL_18K;
2840 break;
2841 case HNS3_FLOW_ULTRA:
2842 new_int_gl = HNS3_INT_GL_8K;
2843 break;
2844 default:
2845 break;
2846 }
2847
2848 ring_group->total_bytes = 0;
2849 ring_group->total_packets = 0;
d420d2de
YL		 2850 ring_group->coal.flow_level = new_flow_level;
2851 if (new_int_gl != ring_group->coal.int_gl) {
2852 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 2853 return true;
2854 }
2855 return false;
2856}
2857
2858static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2859{
dc114fce
FL		 2860 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2861 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2862 bool rx_update, tx_update;
2863
9c46bc10
PL		 2864 /* update param every 1000ms */
2865 if (time_before(jiffies,
2866 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
3f97bd23 2867 return;
3f97bd23 2868
d420d2de 2869 if (rx_group->coal.gl_adapt_enable) {
dc114fce
FL		 2870 rx_update = hns3_get_new_int_gl(rx_group);
2871 if (rx_update)
2872 hns3_set_vector_coalesce_rx_gl(tqp_vector,
d420d2de 2873 rx_group->coal.int_gl);
dc114fce
FL		 2874 }
2875
d420d2de 2876 if (tx_group->coal.gl_adapt_enable) {
dc114fce
FL		 2877 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2878 if (tx_update)
2879 hns3_set_vector_coalesce_tx_gl(tqp_vector,
d420d2de 2880 tx_group->coal.int_gl);
76ad4f0e 2881 }
3f97bd23 2882
50477f37 2883 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 2884}
2885
2886static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2887{
f22463fd 2888 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 2889 struct hns3_enet_ring *ring;
2890 int rx_pkt_total = 0;
2891
2892 struct hns3_enet_tqp_vector *tqp_vector =
2893 container_of(napi, struct hns3_enet_tqp_vector, napi);
2894 bool clean_complete = true;
2895 int rx_budget;
2896
f22463fd
HT		 2897 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
2898 napi_complete(napi);
2899 return 0;
2900 }
2901
76ad4f0e
S		 2902 /* Since the actual Tx work is minimal, we can give the Tx a larger
2903 * budget and be more aggressive about cleaning up the Tx descriptors.
2904 */
6a38a95f
PL		 2905 hns3_for_each_ring(ring, tqp_vector->tx_group)
2906 hns3_clean_tx_ring(ring);
76ad4f0e
S		 2907
2908 /* make sure rx ring budget not smaller than 1 */
2909 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2910
2911 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 2912 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2913 hns3_rx_skb);
76ad4f0e
S		 2914
2915 if (rx_cleaned >= rx_budget)
2916 clean_complete = false;
2917
2918 rx_pkt_total += rx_cleaned;
2919 }
2920
2921 tqp_vector->rx_group.total_packets += rx_pkt_total;
2922
2923 if (!clean_complete)
2924 return budget;
2925
be1c4048
HT		 2926 if (napi_complete(napi) &&
2927 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
f22463fd
HT		 2928 hns3_update_new_int_gl(tqp_vector);
2929 hns3_mask_vector_irq(tqp_vector, 1);
2930 }
76ad4f0e
S		 2931
2932 return rx_pkt_total;
2933}
2934
2935static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2936 struct hnae3_ring_chain_node *head)
2937{
2938 struct pci_dev *pdev = tqp_vector->handle->pdev;
2939 struct hnae3_ring_chain_node *cur_chain = head;
2940 struct hnae3_ring_chain_node *chain;
2941 struct hns3_enet_ring *tx_ring;
2942 struct hns3_enet_ring *rx_ring;
2943
2944 tx_ring = tqp_vector->tx_group.ring;
2945 if (tx_ring) {
2946 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
ccc23ef3
PL		 2947 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2948 HNAE3_RING_TYPE_TX);
2949 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2950 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 2951
2952 cur_chain->next = NULL;
2953
2954 while (tx_ring->next) {
2955 tx_ring = tx_ring->next;
2956
2957 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2958 GFP_KERNEL);
2959 if (!chain)
1129d424 2960 goto err_free_chain;
76ad4f0e
S		 2961
2962 cur_chain->next = chain;
2963 chain->tqp_index = tx_ring->tqp->tqp_index;
ccc23ef3
PL		 2964 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2965 HNAE3_RING_TYPE_TX);
2966 hnae3_set_field(chain->int_gl_idx,
2967 HNAE3_RING_GL_IDX_M,
2968 HNAE3_RING_GL_IDX_S,
2969 HNAE3_RING_GL_TX);
76ad4f0e
S		 2970
2971 cur_chain = chain;
2972 }
2973 }
2974
2975 rx_ring = tqp_vector->rx_group.ring;
2976 if (!tx_ring && rx_ring) {
2977 cur_chain->next = NULL;
2978 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
ccc23ef3
PL		 2979 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2980 HNAE3_RING_TYPE_RX);
2981 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2982 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 2983
2984 rx_ring = rx_ring->next;
2985 }
2986
2987 while (rx_ring) {
2988 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
2989 if (!chain)
1129d424 2990 goto err_free_chain;
76ad4f0e
S		 2991
2992 cur_chain->next = chain;
2993 chain->tqp_index = rx_ring->tqp->tqp_index;
ccc23ef3
PL		 2994 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2995 HNAE3_RING_TYPE_RX);
2996 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2997 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
f230c6c5 2998
76ad4f0e
S		 2999 cur_chain = chain;
3000
3001 rx_ring = rx_ring->next;
3002 }
3003
3004 return 0;
1129d424
HT		 3005
3006err_free_chain:
3007 cur_chain = head->next;
3008 while (cur_chain) {
3009 chain = cur_chain->next;
cc8e7db2 3010 devm_kfree(&pdev->dev, cur_chain);
1129d424
HT		 3011 cur_chain = chain;
3012 }
cc8e7db2 3013 head->next = NULL;
1129d424
HT		 3014
3015 return -ENOMEM;
76ad4f0e
S		 3016}
3017
3018static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3019 struct hnae3_ring_chain_node *head)
3020{
3021 struct pci_dev *pdev = tqp_vector->handle->pdev;
3022 struct hnae3_ring_chain_node *chain_tmp, *chain;
3023
3024 chain = head->next;
3025
3026 while (chain) {
3027 chain_tmp = chain->next;
3028 devm_kfree(&pdev->dev, chain);
3029 chain = chain_tmp;
3030 }
3031}
3032
3033static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3034 struct hns3_enet_ring *ring)
3035{
3036 ring->next = group->ring;
3037 group->ring = ring;
3038
3039 group->count++;
3040}
3041
15040788
PL		 3042static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3043{
3044 struct pci_dev *pdev = priv->ae_handle->pdev;
3045 struct hns3_enet_tqp_vector *tqp_vector;
3046 int num_vectors = priv->vector_num;
3047 int numa_node;
3048 int vector_i;
3049
3050 numa_node = dev_to_node(&pdev->dev);
3051
3052 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3053 tqp_vector = &priv->tqp_vector[vector_i];
3054 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3055 &tqp_vector->affinity_mask);
3056 }
3057}
3058
76ad4f0e
S		 3059static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3060{
3061 struct hnae3_ring_chain_node vector_ring_chain;
3062 struct hnae3_handle *h = priv->ae_handle;
3063 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3064 int ret = 0;
3c424930 3065 int i;
76ad4f0e 3066
15040788
PL		 3067 hns3_nic_set_cpumask(priv);
3068
6cbd6d33
YL		 3069 for (i = 0; i < priv->vector_num; i++) {
3070 tqp_vector = &priv->tqp_vector[i];
3071 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3072 tqp_vector->num_tqps = 0;
3073 }
76ad4f0e 3074
6cbd6d33
YL		 3075 for (i = 0; i < h->kinfo.num_tqps; i++) {
3076 u16 vector_i = i % priv->vector_num;
3077 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3078
3079 tqp_vector = &priv->tqp_vector[vector_i];
3080
3081 hns3_add_ring_to_group(&tqp_vector->tx_group,
3082 priv->ring_data[i].ring);
3083
3084 hns3_add_ring_to_group(&tqp_vector->rx_group,
3085 priv->ring_data[i + tqp_num].ring);
3086
76ad4f0e
S		 3087 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3088 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
6cbd6d33 3089 tqp_vector->num_tqps++;
76ad4f0e
S		 3090 }
3091
6cbd6d33 3092 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3093 tqp_vector = &priv->tqp_vector[i];
3094
3095 tqp_vector->rx_group.total_bytes = 0;
3096 tqp_vector->rx_group.total_packets = 0;
3097 tqp_vector->tx_group.total_bytes = 0;
3098 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3099 tqp_vector->handle = h;
3100
3101 ret = hns3_get_vector_ring_chain(tqp_vector,
3102 &vector_ring_chain);
3103 if (ret)
cc8e7db2 3104 goto map_ring_fail;
76ad4f0e
S		 3105
3106 ret = h->ae_algo->ops->map_ring_to_vector(h,
3107 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3108
3109 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3110
6cbd6d33 3111 if (ret)
3c424930 3112 goto map_ring_fail;
6cbd6d33 3113
76ad4f0e
S		 3114 netif_napi_add(priv->netdev, &tqp_vector->napi,
3115 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3116 }
3117
6cbd6d33 3118 return 0;
3c424930
HT		 3119
3120map_ring_fail:
3121 while (i--)
3122 netif_napi_del(&priv->tqp_vector[i].napi);
3123
3124 return ret;
6cbd6d33
YL		 3125}
3126
3127static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3128{
f56424b6
JS		 3129#define HNS3_VECTOR_PF_MAX_NUM 64
3130
6cbd6d33
YL		 3131 struct hnae3_handle *h = priv->ae_handle;
3132 struct hns3_enet_tqp_vector *tqp_vector;
3133 struct hnae3_vector_info *vector;
3134 struct pci_dev *pdev = h->pdev;
3135 u16 tqp_num = h->kinfo.num_tqps;
3136 u16 vector_num;
3137 int ret = 0;
3138 u16 i;
3139
3140 /* RSS size, cpu online and vector_num should be the same */
3141 /* Should consider 2p/4p later */
3142 vector_num = min_t(u16, num_online_cpus(), tqp_num);
f56424b6
JS		 3143 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3144
6cbd6d33
YL		 3145 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3146 GFP_KERNEL);
3147 if (!vector)
3148 return -ENOMEM;
3149
3150 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3151
3152 priv->vector_num = vector_num;
3153 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3154 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3155 GFP_KERNEL);
3156 if (!priv->tqp_vector) {
3157 ret = -ENOMEM;
3158 goto out;
3159 }
3160
3161 for (i = 0; i < priv->vector_num; i++) {
3162 tqp_vector = &priv->tqp_vector[i];
3163 tqp_vector->idx = i;
3164 tqp_vector->mask_addr = vector[i].io_addr;
3165 tqp_vector->vector_irq = vector[i].vector;
3166 hns3_vector_gl_rl_init(tqp_vector, priv);
3167 }
3168
76ad4f0e
S		 3169out:
3170 devm_kfree(&pdev->dev, vector);
3171 return ret;
3172}
3173
6cbd6d33
YL		 3174static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3175{
3176 group->ring = NULL;
3177 group->count = 0;
3178}
3179
76ad4f0e
S		 3180static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3181{
3182 struct hnae3_ring_chain_node vector_ring_chain;
3183 struct hnae3_handle *h = priv->ae_handle;
3184 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 3185 int i, ret;
3186
3187 for (i = 0; i < priv->vector_num; i++) {
3188 tqp_vector = &priv->tqp_vector[i];
3189
3190 ret = hns3_get_vector_ring_chain(tqp_vector,
3191 &vector_ring_chain);
3192 if (ret)
3193 return ret;
3194
3195 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
3196 tqp_vector->vector_irq, &vector_ring_chain);
3197 if (ret)
3198 return ret;
3199
3200 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3201
32a9b305
HT		 3202 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
3203 irq_set_affinity_notifier(tqp_vector->vector_irq,
3204 NULL);
3205 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3206 free_irq(tqp_vector->vector_irq, tqp_vector);
3207 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
76ad4f0e
S		 3208 }
3209
3210 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
6cbd6d33
YL		 3211 hns3_clear_ring_group(&tqp_vector->rx_group);
3212 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3213 netif_napi_del(&priv->tqp_vector[i].napi);
3214 }
3215
6cbd6d33
YL		 3216 return 0;
3217}
3218
3219static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3220{
3221 struct hnae3_handle *h = priv->ae_handle;
3222 struct pci_dev *pdev = h->pdev;
3223 int i, ret;
3224
3225 for (i = 0; i < priv->vector_num; i++) {
3226 struct hns3_enet_tqp_vector *tqp_vector;
3227
3228 tqp_vector = &priv->tqp_vector[i];
3229 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3230 if (ret)
3231 return ret;
3232 }
76ad4f0e 3233
6cbd6d33 3234 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3235 return 0;
3236}
3237
3238static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3239 int ring_type)
3240{
3241 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3242 int queue_num = priv->ae_handle->kinfo.num_tqps;
3243 struct pci_dev *pdev = priv->ae_handle->pdev;
3244 struct hns3_enet_ring *ring;
3245
3246 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3247 if (!ring)
3248 return -ENOMEM;
3249
3250 if (ring_type == HNAE3_RING_TYPE_TX) {
3251 ring_data[q->tqp_index].ring = ring;
66b44730 3252 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 3253 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3254 } else {
3255 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 3256 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 3257 ring->io_base = q->io_base;
3258 }
3259
ccc23ef3 3260 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3261
76ad4f0e
S		 3262 ring->tqp = q;
3263 ring->desc = NULL;
3264 ring->desc_cb = NULL;
3265 ring->dev = priv->dev;
3266 ring->desc_dma_addr = 0;
3267 ring->buf_size = q->buf_size;
3268 ring->desc_num = q->desc_num;
3269 ring->next_to_use = 0;
3270 ring->next_to_clean = 0;
3271
3272 return 0;
3273}
3274
3275static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3276 struct hns3_nic_priv *priv)
3277{
3278 int ret;
3279
3280 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3281 if (ret)
3282 return ret;
3283
3284 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
1129d424
HT		 3285 if (ret) {
3286 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
76ad4f0e 3287 return ret;
1129d424 3288 }
76ad4f0e
S		 3289
3290 return 0;
3291}
3292
3293static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3294{
3295 struct hnae3_handle *h = priv->ae_handle;
3296 struct pci_dev *pdev = h->pdev;
3297 int i, ret;
3298
3299 priv->ring_data = devm_kzalloc(&pdev->dev, h->kinfo.num_tqps *
3300 sizeof(*priv->ring_data) * 2,
3301 GFP_KERNEL);
3302 if (!priv->ring_data)
3303 return -ENOMEM;
3304
3305 for (i = 0; i < h->kinfo.num_tqps; i++) {
3306 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3307 if (ret)
3308 goto err;
3309 }
3310
3311 return 0;
3312err:
1129d424
HT		 3313 while (i--) {
3314 devm_kfree(priv->dev, priv->ring_data[i].ring);
3315 devm_kfree(priv->dev,
3316 priv->ring_data[i + h->kinfo.num_tqps].ring);
3317 }
3318
76ad4f0e
S		 3319 devm_kfree(&pdev->dev, priv->ring_data);
3320 return ret;
3321}
3322
f1f779ce
PL		 3323static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3324{
3325 struct hnae3_handle *h = priv->ae_handle;
3326 int i;
3327
3328 for (i = 0; i < h->kinfo.num_tqps; i++) {
3329 devm_kfree(priv->dev, priv->ring_data[i].ring);
3330 devm_kfree(priv->dev,
3331 priv->ring_data[i + h->kinfo.num_tqps].ring);
3332 }
3333 devm_kfree(priv->dev, priv->ring_data);
3334}
3335
76ad4f0e
S		 3336static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3337{
3338 int ret;
3339
3340 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3341 return -EINVAL;
3342
3343 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
3344 GFP_KERNEL);
3345 if (!ring->desc_cb) {
3346 ret = -ENOMEM;
3347 goto out;
3348 }
3349
3350 ret = hns3_alloc_desc(ring);
3351 if (ret)
3352 goto out_with_desc_cb;
3353
3354 if (!HNAE3_IS_TX_RING(ring)) {
3355 ret = hns3_alloc_ring_buffers(ring);
3356 if (ret)
3357 goto out_with_desc;
3358 }
3359
3360 return 0;
3361
3362out_with_desc:
3363 hns3_free_desc(ring);
3364out_with_desc_cb:
3365 kfree(ring->desc_cb);
3366 ring->desc_cb = NULL;
3367out:
3368 return ret;
3369}
3370
3371static void hns3_fini_ring(struct hns3_enet_ring *ring)
3372{
3373 hns3_free_desc(ring);
3374 kfree(ring->desc_cb);
3375 ring->desc_cb = NULL;
3376 ring->next_to_clean = 0;
3377 ring->next_to_use = 0;
3378}
3379
1db9b1bf 3380static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3381{
3382 int bd_size_type;
3383
3384 switch (buf_size) {
3385 case 512:
3386 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3387 break;
3388 case 1024:
3389 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3390 break;
3391 case 2048:
3392 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3393 break;
3394 case 4096:
3395 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3396 break;
3397 default:
3398 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3399 }
3400
3401 return bd_size_type;
3402}
3403
3404static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3405{
3406 dma_addr_t dma = ring->desc_dma_addr;
3407 struct hnae3_queue *q = ring->tqp;
3408
3409 if (!HNAE3_IS_TX_RING(ring)) {
3410 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3411 (u32)dma);
3412 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3413 (u32)((dma >> 31) >> 1));
3414
3415 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3416 hns3_buf_size2type(ring->buf_size));
3417 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3418 ring->desc_num / 8 - 1);
3419
3420 } else {
3421 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3422 (u32)dma);
3423 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3424 (u32)((dma >> 31) >> 1));
3425
76ad4f0e
S		 3426 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3427 ring->desc_num / 8 - 1);
3428 }
3429}
3430
fe46c859
YL		 3431static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3432{
3433 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3434 int i;
3435
3436 for (i = 0; i < HNAE3_MAX_TC; i++) {
3437 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3438 int j;
3439
3440 if (!tc_info->enable)
3441 continue;
3442
3443 for (j = 0; j < tc_info->tqp_count; j++) {
3444 struct hnae3_queue *q;
3445
3446 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3447 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3448 tc_info->tc);
3449 }
3450 }
3451}
3452
5668abda 3453int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3454{
3455 struct hnae3_handle *h = priv->ae_handle;
3456 int ring_num = h->kinfo.num_tqps * 2;
3457 int i, j;
3458 int ret;
3459
3460 for (i = 0; i < ring_num; i++) {
3461 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3462 if (ret) {
3463 dev_err(priv->dev,
3464 "Alloc ring memory fail! ret=%d\n", ret);
3465 goto out_when_alloc_ring_memory;
3466 }
3467
76ad4f0e
S		 3468 u64_stats_init(&priv->ring_data[i].ring->syncp);
3469 }
3470
3471 return 0;
3472
3473out_when_alloc_ring_memory:
3474 for (j = i - 1; j >= 0; j--)
ee83f776 3475 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 3476
3477 return -ENOMEM;
3478}
3479
5668abda 3480int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3481{
3482 struct hnae3_handle *h = priv->ae_handle;
3483 int i;
3484
3485 for (i = 0; i < h->kinfo.num_tqps; i++) {
76ad4f0e
S		 3486 hns3_fini_ring(priv->ring_data[i].ring);
3487 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3488 }
76ad4f0e
S		 3489 return 0;
3490}
3491
3492/* Set mac addr if it is configured. or leave it to the AE driver */
abe62a63 3493static int hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 3494{
3495 struct hns3_nic_priv *priv = netdev_priv(netdev);
3496 struct hnae3_handle *h = priv->ae_handle;
3497 u8 mac_addr_temp[ETH_ALEN];
abe62a63 3498 int ret = 0;
76ad4f0e 3499
edf76c8e 3500 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 3501 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3502 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3503 }
3504
3505 /* Check if the MAC address is valid, if not get a random one */
3506 if (!is_valid_ether_addr(netdev->dev_addr)) {
3507 eth_hw_addr_random(netdev);
3508 dev_warn(priv->dev, "using random MAC address %pM\n",
3509 netdev->dev_addr);
76ad4f0e 3510 }
139e8792
L		 3511
3512 if (h->ae_algo->ops->set_mac_addr)
abe62a63 3513 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3514
abe62a63 3515 return ret;
76ad4f0e
S		 3516}
3517
7ce98982
JS		 3518static int hns3_restore_fd_rules(struct net_device *netdev)
3519{
3520 struct hnae3_handle *h = hns3_get_handle(netdev);
3521 int ret = 0;
3522
3523 if (h->ae_algo->ops->restore_fd_rules)
3524 ret = h->ae_algo->ops->restore_fd_rules(h);
3525
3526 return ret;
3527}
3528
3529static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3530{
3531 struct hnae3_handle *h = hns3_get_handle(netdev);
3532
3533 if (h->ae_algo->ops->del_all_fd_entries)
3534 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3535}
3536
76ad4f0e
S		 3537static void hns3_nic_set_priv_ops(struct net_device *netdev)
3538{
3539 struct hns3_nic_priv *priv = netdev_priv(netdev);
3540
e4c38d6e 3541 priv->ops.fill_desc = hns3_fill_desc;
76ad4f0e 3542 if ((netdev->features & NETIF_F_TSO) ||
e4c38d6e 3543 (netdev->features & NETIF_F_TSO6))
76ad4f0e 3544 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
e4c38d6e 3545 else
76ad4f0e 3546 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
76ad4f0e
S		 3547}
3548
337460de
YL		 3549static int hns3_client_start(struct hnae3_handle *handle)
3550{
3551 if (!handle->ae_algo->ops->client_start)
3552 return 0;
3553
3554 return handle->ae_algo->ops->client_start(handle);
3555}
3556
3557static void hns3_client_stop(struct hnae3_handle *handle)
3558{
3559 if (!handle->ae_algo->ops->client_stop)
3560 return;
3561
3562 handle->ae_algo->ops->client_stop(handle);
3563}
3564
76ad4f0e
S		 3565static int hns3_client_init(struct hnae3_handle *handle)
3566{
3567 struct pci_dev *pdev = handle->pdev;
08ca3d58 3568 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 3569 struct hns3_nic_priv *priv;
3570 struct net_device *netdev;
3571 int ret;
3572
08ca3d58
HT		 3573 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3574 &max_rss_size);
3575 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 3576 if (!netdev)
3577 return -ENOMEM;
3578
3579 priv = netdev_priv(netdev);
3580 priv->dev = &pdev->dev;
3581 priv->netdev = netdev;
3582 priv->ae_handle = handle;
f8fa222c 3583 priv->tx_timeout_count = 0;
76ad4f0e
S		 3584
3585 handle->kinfo.netdev = netdev;
3586 handle->priv = (void *)priv;
3587
edf76c8e 3588 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3589
3590 hns3_set_default_feature(netdev);
3591
3592 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3593 netdev->priv_flags |= IFF_UNICAST_FLT;
3594 netdev->netdev_ops = &hns3_nic_netdev_ops;
3595 SET_NETDEV_DEV(netdev, &pdev->dev);
3596 hns3_ethtool_set_ops(netdev);
3597 hns3_nic_set_priv_ops(netdev);
3598
3599 /* Carrier off reporting is important to ethtool even BEFORE open */
3600 netif_carrier_off(netdev);
3601
3602 ret = hns3_get_ring_config(priv);
3603 if (ret) {
3604 ret = -ENOMEM;
3605 goto out_get_ring_cfg;
3606 }
3607
6cbd6d33
YL		 3608 ret = hns3_nic_alloc_vector_data(priv);
3609 if (ret) {
3610 ret = -ENOMEM;
3611 goto out_alloc_vector_data;
3612 }
3613
76ad4f0e
S		 3614 ret = hns3_nic_init_vector_data(priv);
3615 if (ret) {
3616 ret = -ENOMEM;
3617 goto out_init_vector_data;
3618 }
3619
3620 ret = hns3_init_all_ring(priv);
3621 if (ret) {
3622 ret = -ENOMEM;
3623 goto out_init_ring_data;
3624 }
3625
3626 ret = register_netdev(netdev);
3627 if (ret) {
3628 dev_err(priv->dev, "probe register netdev fail!\n");
3629 goto out_reg_netdev_fail;
3630 }
3631
337460de
YL		 3632 ret = hns3_client_start(handle);
3633 if (ret) {
3634 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
3635 goto out_reg_netdev_fail;
3636 }
3637
986743db
YL		 3638 hns3_dcbnl_setup(handle);
3639
a9556d8c 3640 hns3_dbg_init(handle);
3641
bd975002 3642 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
4ee09281 3643 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 3644
352285f1
HT		 3645 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3646
76ad4f0e
S		 3647 return ret;
3648
3649out_reg_netdev_fail:
3650out_init_ring_data:
3651 (void)hns3_nic_uninit_vector_data(priv);
76ad4f0e 3652out_init_vector_data:
6cbd6d33
YL		 3653 hns3_nic_dealloc_vector_data(priv);
3654out_alloc_vector_data:
3655 priv->ring_data = NULL;
76ad4f0e
S		 3656out_get_ring_cfg:
3657 priv->ae_handle = NULL;
3658 free_netdev(netdev);
3659 return ret;
3660}
3661
3662static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3663{
3664 struct net_device *netdev = handle->kinfo.netdev;
3665 struct hns3_nic_priv *priv = netdev_priv(netdev);
3666 int ret;
3667
337460de
YL		 3668 hns3_client_stop(handle);
3669
2c794374
JS		 3670 hns3_remove_hw_addr(netdev);
3671
76ad4f0e
S		 3672 if (netdev->reg_state != NETREG_UNINITIALIZED)
3673 unregister_netdev(netdev);
3674
352285f1
HT		 3675 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3676 netdev_warn(netdev, "already uninitialized\n");
3677 goto out_netdev_free;
3678 }
3679
c27ad61b
JS		 3680 hns3_del_all_fd_rules(netdev, true);
3681
e32a805a
FL		 3682 hns3_force_clear_all_rx_ring(handle);
3683
76ad4f0e
S		 3684 ret = hns3_nic_uninit_vector_data(priv);
3685 if (ret)
3686 netdev_err(netdev, "uninit vector error\n");
3687
6cbd6d33
YL		 3688 ret = hns3_nic_dealloc_vector_data(priv);
3689 if (ret)
3690 netdev_err(netdev, "dealloc vector error\n");
3691
76ad4f0e
S		 3692 ret = hns3_uninit_all_ring(priv);
3693 if (ret)
3694 netdev_err(netdev, "uninit ring error\n");
3695
a2ddee8c
YL		 3696 hns3_put_ring_config(priv);
3697
a9556d8c 3698 hns3_dbg_uninit(handle);
3699
76ad4f0e
S		 3700 priv->ring_data = NULL;
3701
352285f1 3702out_netdev_free:
76ad4f0e
S		 3703 free_netdev(netdev);
3704}
3705
3706static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3707{
3708 struct net_device *netdev = handle->kinfo.netdev;
3709
3710 if (!netdev)
3711 return;
3712
3713 if (linkup) {
3714 netif_carrier_on(netdev);
3715 netif_tx_wake_all_queues(netdev);
3716 netdev_info(netdev, "link up\n");
3717 } else {
3718 netif_carrier_off(netdev);
3719 netif_tx_stop_all_queues(netdev);
3720 netdev_info(netdev, "link down\n");
3721 }
3722}
3723
9df8f79a
YL		 3724static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3725{
3726 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3727 struct net_device *ndev = kinfo->netdev;
075cfdd6 3728 bool if_running;
9df8f79a 3729 int ret;
9df8f79a
YL		 3730
3731 if (tc > HNAE3_MAX_TC)
3732 return -EINVAL;
3733
3734 if (!ndev)
3735 return -ENODEV;
3736
075cfdd6
CIK		 3737 if_running = netif_running(ndev);
3738
9df8f79a
YL		 3739 if (if_running) {
3740 (void)hns3_nic_net_stop(ndev);
3741 msleep(100);
3742 }
3743
3744 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3745 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3746 if (ret)
3747 goto err_out;
3748
9df8f79a
YL		 3749 ret = hns3_nic_set_real_num_queue(ndev);
3750
3751err_out:
3752 if (if_running)
3753 (void)hns3_nic_net_open(ndev);
3754
3755 return ret;
3756}
3757
abe62a63 3758static int hns3_recover_hw_addr(struct net_device *ndev)
bb6b94a8
L		 3759{
3760 struct netdev_hw_addr_list *list;
3761 struct netdev_hw_addr *ha, *tmp;
abe62a63 3762 int ret = 0;
bb6b94a8
L		 3763
3764 /* go through and sync uc_addr entries to the device */
3765 list = &ndev->uc;
abe62a63
HT		 3766 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3767 ret = hns3_nic_uc_sync(ndev, ha->addr);
3768 if (ret)
3769 return ret;
3770 }
bb6b94a8
L		 3771
3772 /* go through and sync mc_addr entries to the device */
3773 list = &ndev->mc;
abe62a63
HT		 3774 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3775 ret = hns3_nic_mc_sync(ndev, ha->addr);
3776 if (ret)
3777 return ret;
3778 }
3779
3780 return ret;
bb6b94a8
L		 3781}
3782
2c794374
JS		 3783static void hns3_remove_hw_addr(struct net_device *netdev)
3784{
3785 struct netdev_hw_addr_list *list;
3786 struct netdev_hw_addr *ha, *tmp;
3787
3788 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
3789
3790 /* go through and unsync uc_addr entries to the device */
3791 list = &netdev->uc;
3792 list_for_each_entry_safe(ha, tmp, &list->list, list)
3793 hns3_nic_uc_unsync(netdev, ha->addr);
3794
3795 /* go through and unsync mc_addr entries to the device */
3796 list = &netdev->mc;
3797 list_for_each_entry_safe(ha, tmp, &list->list, list)
3798 if (ha->refcount > 1)
3799 hns3_nic_mc_unsync(netdev, ha->addr);
3800}
3801
82172ec9 3802static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 3803{
82172ec9 3804 while (ring->next_to_clean != ring->next_to_use) {
e32a805a 3805 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
82172ec9
YL		 3806 hns3_free_buffer_detach(ring, ring->next_to_clean);
3807 ring_ptr_move_fw(ring, next_to_clean);
3808 }
3809}
3810
e32a805a
FL		 3811static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3812{
3813 struct hns3_desc_cb res_cbs;
3814 int ret;
3815
3816 while (ring->next_to_use != ring->next_to_clean) {
3817 /* When a buffer is not reused, it's memory has been
3818 * freed in hns3_handle_rx_bd or will be freed by
3819 * stack, so we need to replace the buffer here.
3820 */
3821 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3822 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3823 if (ret) {
3824 u64_stats_update_begin(&ring->syncp);
3825 ring->stats.sw_err_cnt++;
3826 u64_stats_update_end(&ring->syncp);
3827 /* if alloc new buffer fail, exit directly
3828 * and reclear in up flow.
3829 */
3830 netdev_warn(ring->tqp->handle->kinfo.netdev,
3831 "reserve buffer map failed, ret = %d\n",
3832 ret);
3833 return ret;
3834 }
3835 hns3_replace_buffer(ring, ring->next_to_use,
3836 &res_cbs);
3837 }
3838 ring_ptr_move_fw(ring, next_to_use);
3839 }
3840
3841 return 0;
3842}
3843
3844static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
82172ec9 3845{
82172ec9
YL		 3846 while (ring->next_to_use != ring->next_to_clean) {
3847 /* When a buffer is not reused, it's memory has been
3848 * freed in hns3_handle_rx_bd or will be freed by
3849 * stack, so only need to unmap the buffer here.
3850 */
3851 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3852 hns3_unmap_buffer(ring,
3853 &ring->desc_cb[ring->next_to_use]);
3854 ring->desc_cb[ring->next_to_use].dma = 0;
3855 }
3856
3857 ring_ptr_move_fw(ring, next_to_use);
3858 }
bb6b94a8
L		 3859}
3860
e32a805a
FL		 3861static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3862{
3863 struct net_device *ndev = h->kinfo.netdev;
3864 struct hns3_nic_priv *priv = netdev_priv(ndev);
3865 struct hns3_enet_ring *ring;
3866 u32 i;
3867
3868 for (i = 0; i < h->kinfo.num_tqps; i++) {
3869 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3870 hns3_force_clear_rx_ring(ring);
3871 }
3872}
3873
bb6b94a8
L		 3874static void hns3_clear_all_ring(struct hnae3_handle *h)
3875{
3876 struct net_device *ndev = h->kinfo.netdev;
3877 struct hns3_nic_priv *priv = netdev_priv(ndev);
3878 u32 i;
3879
3880 for (i = 0; i < h->kinfo.num_tqps; i++) {
3881 struct netdev_queue *dev_queue;
3882 struct hns3_enet_ring *ring;
3883
3884 ring = priv->ring_data[i].ring;
82172ec9 3885 hns3_clear_tx_ring(ring);
bb6b94a8
L		 3886 dev_queue = netdev_get_tx_queue(ndev,
3887 priv->ring_data[i].queue_index);
3888 netdev_tx_reset_queue(dev_queue);
3889
3890 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
e32a805a
FL		 3891 /* Continue to clear other rings even if clearing some
3892 * rings failed.
3893 */
82172ec9 3894 hns3_clear_rx_ring(ring);
bb6b94a8
L		 3895 }
3896}
3897
e32a805a
FL		 3898int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3899{
3900 struct net_device *ndev = h->kinfo.netdev;
3901 struct hns3_nic_priv *priv = netdev_priv(ndev);
3902 struct hns3_enet_ring *rx_ring;
3903 int i, j;
3904 int ret;
3905
3906 for (i = 0; i < h->kinfo.num_tqps; i++) {
abe62a63
HT		 3907 ret = h->ae_algo->ops->reset_queue(h, i);
3908 if (ret)
3909 return ret;
3910
e32a805a
FL		 3911 hns3_init_ring_hw(priv->ring_data[i].ring);
3912
3913 /* We need to clear tx ring here because self test will
3914 * use the ring and will not run down before up
3915 */
3916 hns3_clear_tx_ring(priv->ring_data[i].ring);
3917 priv->ring_data[i].ring->next_to_clean = 0;
3918 priv->ring_data[i].ring->next_to_use = 0;
3919
3920 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3921 hns3_init_ring_hw(rx_ring);
3922 ret = hns3_clear_rx_ring(rx_ring);
3923 if (ret)
3924 return ret;
3925
3926 /* We can not know the hardware head and tail when this
3927 * function is called in reset flow, so we reuse all desc.
3928 */
3929 for (j = 0; j < rx_ring->desc_num; j++)
3930 hns3_reuse_buffer(rx_ring, j);
3931
3932 rx_ring->next_to_clean = 0;
3933 rx_ring->next_to_use = 0;
3934 }
3935
fe46c859
YL		 3936 hns3_init_tx_ring_tc(priv);
3937
e32a805a
FL		 3938 return 0;
3939}
3940
0378eccc
HT		 3941static void hns3_store_coal(struct hns3_nic_priv *priv)
3942{
3943 /* ethtool only support setting and querying one coal
3944 * configuation for now, so save the vector 0' coal
3945 * configuation here in order to restore it.
3946 */
3947 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
3948 sizeof(struct hns3_enet_coalesce));
3949 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
3950 sizeof(struct hns3_enet_coalesce));
3951}
3952
3953static void hns3_restore_coal(struct hns3_nic_priv *priv)
3954{
3955 u16 vector_num = priv->vector_num;
3956 int i;
3957
3958 for (i = 0; i < vector_num; i++) {
3959 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
3960 sizeof(struct hns3_enet_coalesce));
3961 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
3962 sizeof(struct hns3_enet_coalesce));
3963 }
3964}
3965
bb6b94a8
L		 3966static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3967{
7e68177b 3968 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
bb6b94a8
L		 3969 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3970 struct net_device *ndev = kinfo->netdev;
3a11f446
HT		 3971 struct hns3_nic_priv *priv = netdev_priv(ndev);
3972
3973 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
3974 return 0;
bb6b94a8 3975
7e68177b
HT		 3976 /* it is cumbersome for hardware to pick-and-choose entries for deletion
3977 * from table space. Hence, for function reset software intervention is
3978 * required to delete the entries
3979 */
3980 if (hns3_dev_ongoing_func_reset(ae_dev)) {
3981 hns3_remove_hw_addr(ndev);
3982 hns3_del_all_fd_rules(ndev, false);
3983 }
3984
bb6b94a8 3985 if (!netif_running(ndev))
196b8760 3986 return 0;
bb6b94a8
L		 3987
3988 return hns3_nic_net_stop(ndev);
3989}
3990
3991static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
3992{
3993 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3a11f446 3994 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 3995 int ret = 0;
3996
ac2dca6b
HT		 3997 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
3998
bb6b94a8 3999 if (netif_running(kinfo->netdev)) {
ac2dca6b 4000 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4001 if (ret) {
ac2dca6b 4002 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8
L		 4003 netdev_err(kinfo->netdev,
4004 "hns net up fail, ret=%d!\n", ret);
4005 return ret;
4006 }
bb6b94a8
L		 4007 }
4008
4009 return ret;
4010}
4011
4012static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4013{
4014 struct net_device *netdev = handle->kinfo.netdev;
4015 struct hns3_nic_priv *priv = netdev_priv(netdev);
ad94a397 4016 bool vlan_filter_enable;
bb6b94a8
L		 4017 int ret;
4018
abe62a63
HT		 4019 ret = hns3_init_mac_addr(netdev, false);
4020 if (ret)
4021 return ret;
4022
4023 ret = hns3_recover_hw_addr(netdev);
4024 if (ret)
4025 return ret;
4026
4027 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4028 if (ret)
4029 return ret;
4030
ad94a397
JS		 4031 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4032 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4033
103ce052 4034 /* Hardware table is only clear when pf resets */
abe62a63
HT		 4035 if (!(handle->flags & HNAE3_SUPPORT_VF)) {
4036 ret = hns3_restore_vlan(netdev);
8eb0e623
HT		 4037 if (ret)
4038 return ret;
abe62a63 4039 }
103ce052 4040
abe62a63
HT		 4041 ret = hns3_restore_fd_rules(netdev);
4042 if (ret)
4043 return ret;
7ce98982 4044
bb6b94a8
L		 4045 /* Carrier off reporting is important to ethtool even BEFORE open */
4046 netif_carrier_off(netdev);
4047
1c92981c
HT		 4048 ret = hns3_nic_alloc_vector_data(priv);
4049 if (ret)
4050 return ret;
4051
0378eccc
HT		 4052 hns3_restore_coal(priv);
4053
bb6b94a8
L		 4054 ret = hns3_nic_init_vector_data(priv);
4055 if (ret)
1c92981c 4056 goto err_dealloc_vector;
bb6b94a8
L		 4057
4058 ret = hns3_init_all_ring(priv);
1c92981c
HT		 4059 if (ret)
4060 goto err_uninit_vector;
bb6b94a8 4061
352285f1
HT		 4062 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4063
1c92981c
HT		 4064 return ret;
4065
4066err_uninit_vector:
4067 hns3_nic_uninit_vector_data(priv);
4068 priv->ring_data = NULL;
4069err_dealloc_vector:
4070 hns3_nic_dealloc_vector_data(priv);
4071
bb6b94a8
L		 4072 return ret;
4073}
4074
4075static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4076{
4077 struct net_device *netdev = handle->kinfo.netdev;
4078 struct hns3_nic_priv *priv = netdev_priv(netdev);
4079 int ret;
4080
352285f1
HT		 4081 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4082 netdev_warn(netdev, "already uninitialized\n");
4083 return 0;
4084 }
4085
e32a805a 4086 hns3_force_clear_all_rx_ring(handle);
bb6b94a8
L		 4087
4088 ret = hns3_nic_uninit_vector_data(priv);
4089 if (ret) {
4090 netdev_err(netdev, "uninit vector error\n");
4091 return ret;
4092 }
4093
0378eccc
HT		 4094 hns3_store_coal(priv);
4095
1c92981c
HT		 4096 ret = hns3_nic_dealloc_vector_data(priv);
4097 if (ret)
4098 netdev_err(netdev, "dealloc vector error\n");
4099
bb6b94a8
L		 4100 ret = hns3_uninit_all_ring(priv);
4101 if (ret)
4102 netdev_err(netdev, "uninit ring error\n");
4103
352285f1
HT		 4104 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
4105
bb6b94a8
L		 4106 return ret;
4107}
4108
4109static int hns3_reset_notify(struct hnae3_handle *handle,
4110 enum hnae3_reset_notify_type type)
4111{
4112 int ret = 0;
4113
4114 switch (type) {
4115 case HNAE3_UP_CLIENT:
741e1778
SM		 4116 ret = hns3_reset_notify_up_enet(handle);
4117 break;
bb6b94a8
L		 4118 case HNAE3_DOWN_CLIENT:
4119 ret = hns3_reset_notify_down_enet(handle);
4120 break;
4121 case HNAE3_INIT_CLIENT:
4122 ret = hns3_reset_notify_init_enet(handle);
4123 break;
4124 case HNAE3_UNINIT_CLIENT:
4125 ret = hns3_reset_notify_uninit_enet(handle);
4126 break;
4127 default:
4128 break;
4129 }
4130
4131 return ret;
4132}
4133
0378eccc 4134static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num)
f1f779ce
PL		 4135{
4136 struct hns3_nic_priv *priv = netdev_priv(netdev);
4137 struct hnae3_handle *h = hns3_get_handle(netdev);
4138 int ret;
4139
4140 ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
4141 if (ret)
4142 return ret;
4143
4144 ret = hns3_get_ring_config(priv);
4145 if (ret)
4146 return ret;
4147
6cbd6d33
YL		 4148 ret = hns3_nic_alloc_vector_data(priv);
4149 if (ret)
4150 goto err_alloc_vector;
4151
0378eccc 4152 hns3_restore_coal(priv);
351dad5e 4153
f1f779ce
PL		 4154 ret = hns3_nic_init_vector_data(priv);
4155 if (ret)
4156 goto err_uninit_vector;
4157
4158 ret = hns3_init_all_ring(priv);
4159 if (ret)
4160 goto err_put_ring;
4161
4162 return 0;
4163
4164err_put_ring:
4165 hns3_put_ring_config(priv);
4166err_uninit_vector:
4167 hns3_nic_uninit_vector_data(priv);
6cbd6d33
YL		 4168err_alloc_vector:
4169 hns3_nic_dealloc_vector_data(priv);
f1f779ce
PL		 4170 return ret;
4171}
4172
4173static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num)
4174{
4175 return (new_tqp_num / num_tc) * num_tc;
4176}
4177
4178int hns3_set_channels(struct net_device *netdev,
4179 struct ethtool_channels *ch)
4180{
4181 struct hns3_nic_priv *priv = netdev_priv(netdev);
4182 struct hnae3_handle *h = hns3_get_handle(netdev);
4183 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4184 bool if_running = netif_running(netdev);
4185 u32 new_tqp_num = ch->combined_count;
4186 u16 org_tqp_num;
4187 int ret;
4188
4189 if (ch->rx_count || ch->tx_count)
4190 return -EINVAL;
4191
2d7187ce 4192 if (new_tqp_num > hns3_get_max_available_channels(h) ||
f1f779ce
PL		 4193 new_tqp_num < kinfo->num_tc) {
4194 dev_err(&netdev->dev,
4195 "Change tqps fail, the tqp range is from %d to %d",
4196 kinfo->num_tc,
2d7187ce 4197 hns3_get_max_available_channels(h));
f1f779ce
PL		 4198 return -EINVAL;
4199 }
4200
4201 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num);
4202 if (kinfo->num_tqps == new_tqp_num)
4203 return 0;
4204
4205 if (if_running)
41efd6b1 4206 hns3_nic_net_stop(netdev);
f1f779ce 4207
f1f779ce
PL		 4208 ret = hns3_nic_uninit_vector_data(priv);
4209 if (ret) {
4210 dev_err(&netdev->dev,
4211 "Unbind vector with tqp fail, nothing is changed");
4212 goto open_netdev;
4213 }
4214
0378eccc 4215 hns3_store_coal(priv);
351dad5e 4216
6cbd6d33
YL		 4217 hns3_nic_dealloc_vector_data(priv);
4218
f1f779ce 4219 hns3_uninit_all_ring(priv);
a2ddee8c 4220 hns3_put_ring_config(priv);
f1f779ce
PL		 4221
4222 org_tqp_num = h->kinfo.num_tqps;
0378eccc 4223 ret = hns3_modify_tqp_num(netdev, new_tqp_num);
f1f779ce 4224 if (ret) {
0378eccc 4225 ret = hns3_modify_tqp_num(netdev, org_tqp_num);
f1f779ce
PL		 4226 if (ret) {
4227 /* If revert to old tqp failed, fatal error occurred */
4228 dev_err(&netdev->dev,
4229 "Revert to old tqp num fail, ret=%d", ret);
4230 return ret;
4231 }
4232 dev_info(&netdev->dev,
4233 "Change tqp num fail, Revert to old tqp num");
4234 }
4235
4236open_netdev:
4237 if (if_running)
41efd6b1 4238 hns3_nic_net_open(netdev);
f1f779ce
PL		 4239
4240 return ret;
4241}
4242
1db9b1bf 4243static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4244 .init_instance = hns3_client_init,
4245 .uninit_instance = hns3_client_uninit,
4246 .link_status_change = hns3_link_status_change,
9df8f79a 4247 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4248 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 4249};
4250
4251/* hns3_init_module - Driver registration routine
4252 * hns3_init_module is the first routine called when the driver is
4253 * loaded. All it does is register with the PCI subsystem.
4254 */
4255static int __init hns3_init_module(void)
4256{
4257 int ret;
4258
4259 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4260 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4261
4262 client.type = HNAE3_CLIENT_KNIC;
4263 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4264 hns3_driver_name);
4265
4266 client.ops = &client_ops;
4267
dadc9935
XW		 4268 INIT_LIST_HEAD(&client.node);
4269
a9556d8c 4270 hns3_dbg_register_debugfs(hns3_driver_name);
4271
76ad4f0e
S		 4272 ret = hnae3_register_client(&client);
4273 if (ret)
a9556d8c 4274 goto err_reg_client;
76ad4f0e
S		 4275
4276 ret = pci_register_driver(&hns3_driver);
4277 if (ret)
a9556d8c 4278 goto err_reg_driver;
76ad4f0e
S		 4279
4280 return ret;
a9556d8c 4281
4282err_reg_driver:
4283 hnae3_unregister_client(&client);
4284err_reg_client:
4285 hns3_dbg_unregister_debugfs();
4286 return ret;
76ad4f0e
S		 4287}
4288module_init(hns3_init_module);
4289
4290/* hns3_exit_module - Driver exit cleanup routine
4291 * hns3_exit_module is called just before the driver is removed
4292 * from memory.
4293 */
4294static void __exit hns3_exit_module(void)
4295{
4296 pci_unregister_driver(&hns3_driver);
4297 hnae3_unregister_client(&client);
a9556d8c 4298 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4299}
4300module_exit(hns3_exit_module);
4301
4302MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4303MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4304MODULE_LICENSE("GPL");
4305MODULE_ALIAS("pci:hns-nic");
4786ad87 4306MODULE_VERSION(HNS3_MOD_VERSION);
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