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Merge tag 'for-5.16/block-2021-10-29' of git://git.kernel.dk/linux-block
[mirror_ubuntu-kernels.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
ffab9691
JS		 7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
76ad4f0e 10#include <linux/if_vlan.h>
e99a308d 11#include <linux/irq.h>
76ad4f0e
S		 12#include <linux/ip.h>
13#include <linux/ipv6.h>
14#include <linux/module.h>
15#include <linux/pci.h>
6ae4e733 16#include <linux/aer.h>
76ad4f0e
S		 17#include <linux/skbuff.h>
18#include <linux/sctp.h>
76ad4f0e 19#include <net/gre.h>
e2ee1c5a 20#include <net/ip6_checksum.h>
30d240df 21#include <net/pkt_cls.h>
a6d53b97 22#include <net/tcp.h>
76ad4f0e 23#include <net/vxlan.h>
a156998f 24#include <net/geneve.h>
76ad4f0e
S		 25
26#include "hnae3.h"
27#include "hns3_enet.h"
698a8954
YL		 28/* All hns3 tracepoints are defined by the include below, which
29 * must be included exactly once across the whole kernel with
30 * CREATE_TRACE_POINTS defined
31 */
32#define CREATE_TRACE_POINTS
33#include "hns3_trace.h"
76ad4f0e 34
9393eb50 35#define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
5f543a54 36#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 37
b20d7fe5
YL		 38#define hns3_rl_err(fmt, ...) \
39 do { \
40 if (net_ratelimit()) \
41 netdev_err(fmt, ##__VA_ARGS__); \
42 } while (0)
43
f96315f2 44static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
7b763f3f 45
1db9b1bf 46static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 47static const char hns3_driver_string[] =
48 "Hisilicon Ethernet Network Driver for Hip08 Family";
49static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
50static struct hnae3_client client;
51
bb87be87
YL		 52static int debug = -1;
53module_param(debug, int, 0);
54MODULE_PARM_DESC(debug, " Network interface message level setting");
55
907676b1
YL		 56static unsigned int tx_spare_buf_size;
57module_param(tx_spare_buf_size, uint, 0400);
58MODULE_PARM_DESC(tx_spare_buf_size, "Size used to allocate tx spare buffer");
59
7459775e
YL		 60static unsigned int tx_sgl = 1;
61module_param(tx_sgl, uint, 0600);
62MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
63
f7ec554b
YL		 64static bool page_pool_enabled = true;
65module_param(page_pool_enabled, bool, 0400);
66
7459775e
YL		 67#define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
68 sizeof(struct sg_table))
c74e5035 69#define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
7459775e
YL		 70 dma_get_cache_alignment())
71
bb87be87
YL		 72#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
73 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
74
eb977d99
YL		 75#define HNS3_INNER_VLAN_TAG 1
76#define HNS3_OUTER_VLAN_TAG 2
77
36c67349 78#define HNS3_MIN_TX_LEN 33U
d18e8118 79#define HNS3_MIN_TUN_PKT_LEN 65U
36c67349 80
76ad4f0e
S		 81/* hns3_pci_tbl - PCI Device ID Table
82 *
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
88static const struct pci_device_id hns3_pci_tbl[] = {
89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 91 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 92 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 93 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 94 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 95 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 96 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 97 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 98 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 99 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 100 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
ae6f010c
GH		 101 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
102 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
c155e22b
GH		 103 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
104 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
07acf909 105 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e 106 /* required last entry */
7f2d4b7f 107 {0,}
76ad4f0e
S		 108};
109MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
110
79664077
HT		 111#define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t) \
112 { ptype, \
113 l, \
114 CHECKSUM_##s, \
115 HNS3_L3_TYPE_##t, \
116 1 }
117
118#define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
119 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0 }
120
121static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
122 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
123 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP),
124 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP),
125 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP),
126 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL),
127 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL),
128 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL),
129 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM),
130 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL),
131 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
132 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
133 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
134 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
135 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
136 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
137 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
138 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL),
139 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4),
140 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4),
141 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4),
142 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4),
143 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4),
144 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4),
145 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4),
146 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4),
147 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4),
148 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
150 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
151 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL),
152 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL),
153 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4),
154 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4),
155 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4),
156 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4),
157 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4),
158 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4),
159 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4),
160 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
161 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6),
162 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6),
163 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6),
164 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6),
165 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6),
166 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6),
167 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6),
168 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
169 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
170 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
171 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
172 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
173 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
174 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
175 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
177 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
178 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
179 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
180 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
181 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
182 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
183 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
232 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
233 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6),
234 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6),
235 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6),
236 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6),
237 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6),
238 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6),
239 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6),
240 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6),
241 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6),
242 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
244 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
245 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL),
246 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL),
247 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4),
248 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4),
249 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4),
250 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4),
251 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4),
252 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4),
253 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4),
254 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
255 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6),
256 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6),
257 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6),
258 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6),
259 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6),
260 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6),
261 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6),
262 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
263 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
264 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
265 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
266 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
267 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
268 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
269 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
271 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
272 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
273 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
274 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
275 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
276 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
277 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
377 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
378};
379
380#define HNS3_INVALID_PTYPE \
381 ARRAY_SIZE(hns3_rx_ptype_tbl)
382
ef0c5009 383static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 384{
ef0c5009 385 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 386
fb00331b 387 napi_schedule_irqoff(&tqp_vector->napi);
307ea4ce 388 tqp_vector->event_cnt++;
76ad4f0e
S		 389
390 return IRQ_HANDLED;
391}
392
393static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
394{
395 struct hns3_enet_tqp_vector *tqp_vectors;
396 unsigned int i;
397
398 for (i = 0; i < priv->vector_num; i++) {
399 tqp_vectors = &priv->tqp_vector[i];
400
401 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
402 continue;
403
ffab9691 404 /* clear the affinity mask */
874bff0b
PL		 405 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
406
76ad4f0e
S		 407 /* release the irq resource */
408 free_irq(tqp_vectors->vector_irq, tqp_vectors);
409 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
410 }
411}
412
413static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
414{
415 struct hns3_enet_tqp_vector *tqp_vectors;
416 int txrx_int_idx = 0;
417 int rx_int_idx = 0;
418 int tx_int_idx = 0;
419 unsigned int i;
420 int ret;
421
422 for (i = 0; i < priv->vector_num; i++) {
423 tqp_vectors = &priv->tqp_vector[i];
424
425 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
426 continue;
427
428 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
5bffde62
YL		 429 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
430 "%s-%s-%s-%d", hns3_driver_name,
431 pci_name(priv->ae_handle->pdev),
432 "TxRx", txrx_int_idx++);
76ad4f0e
S		 433 txrx_int_idx++;
434 } else if (tqp_vectors->rx_group.ring) {
5bffde62
YL		 435 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
436 "%s-%s-%s-%d", hns3_driver_name,
437 pci_name(priv->ae_handle->pdev),
438 "Rx", rx_int_idx++);
76ad4f0e 439 } else if (tqp_vectors->tx_group.ring) {
5bffde62
YL		 440 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
441 "%s-%s-%s-%d", hns3_driver_name,
442 pci_name(priv->ae_handle->pdev),
443 "Tx", tx_int_idx++);
76ad4f0e
S		 444 } else {
445 /* Skip this unused q_vector */
446 continue;
447 }
448
449 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
450
e99a308d 451 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
76ad4f0e 452 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
9b2f3477 453 tqp_vectors->name, tqp_vectors);
76ad4f0e
S		 454 if (ret) {
455 netdev_err(priv->netdev, "request irq(%d) fail\n",
456 tqp_vectors->vector_irq);
d547ecdc 457 hns3_nic_uninit_irq(priv);
76ad4f0e
S		 458 return ret;
459 }
460
874bff0b
PL		 461 irq_set_affinity_hint(tqp_vectors->vector_irq,
462 &tqp_vectors->affinity_mask);
463
76ad4f0e
S		 464 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
465 }
466
467 return 0;
468}
469
470static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
471 u32 mask_en)
472{
473 writel(mask_en, tqp_vector->mask_addr);
474}
475
476static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
477{
478 napi_enable(&tqp_vector->napi);
08a10068 479 enable_irq(tqp_vector->vector_irq);
76ad4f0e
S		 480
481 /* enable vector */
482 hns3_mask_vector_irq(tqp_vector, 1);
483}
484
485static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
486{
487 /* disable vector */
488 hns3_mask_vector_irq(tqp_vector, 0);
489
490 disable_irq(tqp_vector->vector_irq);
491 napi_disable(&tqp_vector->napi);
307ea4ce
HT		 492 cancel_work_sync(&tqp_vector->rx_group.dim.work);
493 cancel_work_sync(&tqp_vector->tx_group.dim.work);
76ad4f0e
S		 494}
495
434776a5
FL		 496void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
497 u32 rl_value)
76ad4f0e 498{
434776a5
FL		 499 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
500
76ad4f0e
S		 501 /* this defines the configuration for RL (Interrupt Rate Limiter).
502 * Rl defines rate of interrupts i.e. number of interrupts-per-second
503 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
504 */
de25bcc4
HT		 505 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
506 !tqp_vector->rx_group.coal.adapt_enable)
434776a5
FL		 507 /* According to the hardware, the range of rl_reg is
508 * 0-59 and the unit is 4.
509 */
510 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
511
512 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
513}
514
515void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
516 u32 gl_value)
517{
5ac84b02 518 u32 new_val;
434776a5 519
5ac84b02
HT		 520 if (tqp_vector->rx_group.coal.unit_1us)
521 new_val = gl_value | HNS3_INT_GL_1US;
522 else
523 new_val = hns3_gl_usec_to_reg(gl_value);
524
525 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
434776a5
FL		 526}
527
528void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
529 u32 gl_value)
530{
5ac84b02
HT		 531 u32 new_val;
532
533 if (tqp_vector->tx_group.coal.unit_1us)
534 new_val = gl_value | HNS3_INT_GL_1US;
535 else
536 new_val = hns3_gl_usec_to_reg(gl_value);
434776a5 537
5ac84b02 538 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 539}
540
91bfae25
HT		 541void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
542 u32 ql_value)
76ad4f0e 543{
91bfae25
HT		 544 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
545}
546
547void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
548 u32 ql_value)
549{
550 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
551}
552
553static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
554 struct hns3_nic_priv *priv)
555{
556 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
557 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
558 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
73a13d8d
HT		 559 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
560 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
91bfae25 561
73a13d8d
HT		 562 tx_coal->adapt_enable = ptx_coal->adapt_enable;
563 rx_coal->adapt_enable = prx_coal->adapt_enable;
91bfae25 564
73a13d8d
HT		 565 tx_coal->int_gl = ptx_coal->int_gl;
566 rx_coal->int_gl = prx_coal->int_gl;
5fd4789a 567
73a13d8d
HT		 568 rx_coal->flow_level = prx_coal->flow_level;
569 tx_coal->flow_level = ptx_coal->flow_level;
5fd4789a 570
5ac84b02
HT		 571 /* device version above V3(include V3), GL can configure 1us
572 * unit, so uses 1us unit.
573 */
574 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
575 tx_coal->unit_1us = 1;
576 rx_coal->unit_1us = 1;
577 }
578
91bfae25
HT		 579 if (ae_dev->dev_specs.int_ql_max) {
580 tx_coal->ql_enable = 1;
581 rx_coal->ql_enable = 1;
582 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
583 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
73a13d8d
HT		 584 tx_coal->int_ql = ptx_coal->int_ql;
585 rx_coal->int_ql = prx_coal->int_ql;
91bfae25 586 }
76ad4f0e
S		 587}
588
91bfae25
HT		 589static void
590hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
591 struct hns3_nic_priv *priv)
dd38c726 592{
91bfae25
HT		 593 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
594 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
dd38c726
YL		 595 struct hnae3_handle *h = priv->ae_handle;
596
91bfae25
HT		 597 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
598 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
dd38c726 599 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
91bfae25
HT		 600
601 if (tx_coal->ql_enable)
602 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
603
604 if (rx_coal->ql_enable)
605 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
dd38c726
YL		 606}
607
9df8f79a
YL		 608static int hns3_nic_set_real_num_queue(struct net_device *netdev)
609{
9780cb97 610 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a 611 struct hnae3_knic_private_info *kinfo = &h->kinfo;
35244430 612 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5a5c9091 613 unsigned int queue_size = kinfo->num_tqps;
a75a8efa
YL		 614 int i, ret;
615
5a5c9091 616 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
a75a8efa
YL		 617 netdev_reset_tc(netdev);
618 } else {
35244430 619 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
a75a8efa
YL		 620 if (ret) {
621 netdev_err(netdev,
622 "netdev_set_num_tc fail, ret=%d!\n", ret);
623 return ret;
624 }
625
a8e76fef 626 for (i = 0; i < tc_info->num_tc; i++)
35244430
JS		 627 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
628 tc_info->tqp_offset[i]);
a75a8efa 629 }
9df8f79a
YL		 630
631 ret = netif_set_real_num_tx_queues(netdev, queue_size);
632 if (ret) {
633 netdev_err(netdev,
9b2f3477 634 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
9df8f79a
YL		 635 return ret;
636 }
637
638 ret = netif_set_real_num_rx_queues(netdev, queue_size);
639 if (ret) {
640 netdev_err(netdev,
641 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
642 return ret;
643 }
644
645 return 0;
646}
647
77e91848 648u16 hns3_get_max_available_channels(struct hnae3_handle *h)
678335a1 649{
0d43bf45 650 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 651
0d43bf45 652 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
35244430 653 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
678335a1 654
0d43bf45 655 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 656}
657
8df0fa91
HT		 658static void hns3_tqp_enable(struct hnae3_queue *tqp)
659{
660 u32 rcb_reg;
661
662 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
663 rcb_reg |= BIT(HNS3_RING_EN_B);
664 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
665}
666
667static void hns3_tqp_disable(struct hnae3_queue *tqp)
668{
669 u32 rcb_reg;
670
671 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
672 rcb_reg &= ~BIT(HNS3_RING_EN_B);
673 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
674}
675
ffab9691
JS		 676static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
677{
678#ifdef CONFIG_RFS_ACCEL
679 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
680 netdev->rx_cpu_rmap = NULL;
681#endif
682}
683
684static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
685{
686#ifdef CONFIG_RFS_ACCEL
687 struct hns3_nic_priv *priv = netdev_priv(netdev);
688 struct hns3_enet_tqp_vector *tqp_vector;
689 int i, ret;
690
691 if (!netdev->rx_cpu_rmap) {
692 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
693 if (!netdev->rx_cpu_rmap)
694 return -ENOMEM;
695 }
696
697 for (i = 0; i < priv->vector_num; i++) {
698 tqp_vector = &priv->tqp_vector[i];
699 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
700 tqp_vector->vector_irq);
701 if (ret) {
702 hns3_free_rx_cpu_rmap(netdev);
703 return ret;
704 }
705 }
706#endif
707 return 0;
708}
709
76ad4f0e
S		 710static int hns3_nic_net_up(struct net_device *netdev)
711{
712 struct hns3_nic_priv *priv = netdev_priv(netdev);
713 struct hnae3_handle *h = priv->ae_handle;
714 int i, j;
715 int ret;
716
7b763f3f
FL		 717 ret = hns3_nic_reset_all_ring(h);
718 if (ret)
719 return ret;
720
b7b585c2
JS		 721 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
722
76ad4f0e
S		 723 /* enable the vectors */
724 for (i = 0; i < priv->vector_num; i++)
725 hns3_vector_enable(&priv->tqp_vector[i]);
726
8df0fa91
HT		 727 /* enable rcb */
728 for (j = 0; j < h->kinfo.num_tqps; j++)
729 hns3_tqp_enable(h->kinfo.tqp[j]);
730
76ad4f0e
S		 731 /* start the ae_dev */
732 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
08a10068
YL		 733 if (ret) {
734 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
735 while (j--)
736 hns3_tqp_disable(h->kinfo.tqp[j]);
8df0fa91 737
08a10068
YL		 738 for (j = i - 1; j >= 0; j--)
739 hns3_vector_disable(&priv->tqp_vector[j]);
740 }
76ad4f0e 741
76ad4f0e
S		 742 return ret;
743}
744
2a73ac3e
YL		 745static void hns3_config_xps(struct hns3_nic_priv *priv)
746{
747 int i;
748
749 for (i = 0; i < priv->vector_num; i++) {
750 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
751 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
752
753 while (ring) {
754 int ret;
755
756 ret = netif_set_xps_queue(priv->netdev,
757 &tqp_vector->affinity_mask,
758 ring->tqp->tqp_index);
759 if (ret)
760 netdev_warn(priv->netdev,
761 "set xps queue failed: %d", ret);
762
763 ring = ring->next;
764 }
765 }
766}
767
76ad4f0e
S		 768static int hns3_nic_net_open(struct net_device *netdev)
769{
8cdb992f 770 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 771 struct hnae3_handle *h = hns3_get_handle(netdev);
772 struct hnae3_knic_private_info *kinfo;
773 int i, ret;
76ad4f0e 774
257e4f29
HT		 775 if (hns3_nic_resetting(netdev))
776 return -EBUSY;
777
5b09e88e
JS		 778 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
779 netdev_warn(netdev, "net open repeatedly!\n");
780 return 0;
781 }
782
76ad4f0e
S		 783 netif_carrier_off(netdev);
784
9df8f79a
YL		 785 ret = hns3_nic_set_real_num_queue(netdev);
786 if (ret)
76ad4f0e 787 return ret;
76ad4f0e
S		 788
789 ret = hns3_nic_net_up(netdev);
790 if (ret) {
9b2f3477 791 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
76ad4f0e
S		 792 return ret;
793 }
794
a75a8efa 795 kinfo = &h->kinfo;
9b2f3477 796 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
35244430 797 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
a75a8efa 798
8cdb992f
JS		 799 if (h->ae_algo->ops->set_timer_task)
800 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
801
2a73ac3e 802 hns3_config_xps(priv);
1c822948
YL		 803
804 netif_dbg(h, drv, netdev, "net open\n");
805
76ad4f0e
S		 806 return 0;
807}
808
f96315f2
HT		 809static void hns3_reset_tx_queue(struct hnae3_handle *h)
810{
811 struct net_device *ndev = h->kinfo.netdev;
812 struct hns3_nic_priv *priv = netdev_priv(ndev);
813 struct netdev_queue *dev_queue;
814 u32 i;
815
816 for (i = 0; i < h->kinfo.num_tqps; i++) {
817 dev_queue = netdev_get_tx_queue(ndev,
5f06b903 818 priv->ring[i].queue_index);
f96315f2
HT		 819 netdev_tx_reset_queue(dev_queue);
820 }
821}
822
76ad4f0e
S		 823static void hns3_nic_net_down(struct net_device *netdev)
824{
825 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 826 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 827 const struct hnae3_ae_ops *ops;
828 int i;
829
7b763f3f
FL		 830 /* disable vectors */
831 for (i = 0; i < priv->vector_num; i++)
832 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 833
834 /* disable rcb */
835 for (i = 0; i < h->kinfo.num_tqps; i++)
836 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 837
76ad4f0e
S		 838 /* stop ae_dev */
839 ops = priv->ae_handle->ae_algo->ops;
840 if (ops->stop)
841 ops->stop(priv->ae_handle);
842
3a30964a
YL		 843 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
844 * during reset process, because driver may not be able
845 * to disable the ring through firmware when downing the netdev.
846 */
847 if (!hns3_nic_resetting(netdev))
f96315f2
HT		 848 hns3_clear_all_ring(priv->ae_handle, false);
849
850 hns3_reset_tx_queue(priv->ae_handle);
76ad4f0e
S		 851}
852
853static int hns3_nic_net_stop(struct net_device *netdev)
854{
ff0699e0 855 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 856 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 857
858 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
859 return 0;
860
1c822948
YL		 861 netif_dbg(h, drv, netdev, "net stop\n");
862
8cdb992f
JS		 863 if (h->ae_algo->ops->set_timer_task)
864 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
865
76ad4f0e 866 netif_carrier_off(netdev);
b416e872 867 netif_tx_disable(netdev);
76ad4f0e
S		 868
869 hns3_nic_net_down(netdev);
870
871 return 0;
872}
873
76ad4f0e
S		 874static int hns3_nic_uc_sync(struct net_device *netdev,
875 const unsigned char *addr)
876{
9780cb97 877 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 878
879 if (h->ae_algo->ops->add_uc_addr)
880 return h->ae_algo->ops->add_uc_addr(h, addr);
881
882 return 0;
883}
884
885static int hns3_nic_uc_unsync(struct net_device *netdev,
886 const unsigned char *addr)
887{
9780cb97 888 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 889
ee4bcd3b
JS		 890 /* need ignore the request of removing device address, because
891 * we store the device address and other addresses of uc list
892 * in the function's mac filter list.
893 */
894 if (ether_addr_equal(addr, netdev->dev_addr))
895 return 0;
896
76ad4f0e
S		 897 if (h->ae_algo->ops->rm_uc_addr)
898 return h->ae_algo->ops->rm_uc_addr(h, addr);
899
900 return 0;
901}
902
903static int hns3_nic_mc_sync(struct net_device *netdev,
904 const unsigned char *addr)
905{
9780cb97 906 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 907
720a8478 908 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 909 return h->ae_algo->ops->add_mc_addr(h, addr);
910
911 return 0;
912}
913
914static int hns3_nic_mc_unsync(struct net_device *netdev,
915 const unsigned char *addr)
916{
9780cb97 917 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 918
720a8478 919 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 920 return h->ae_algo->ops->rm_mc_addr(h, addr);
921
922 return 0;
923}
924
c60edc17
JS		 925static u8 hns3_get_netdev_flags(struct net_device *netdev)
926{
927 u8 flags = 0;
928
2ba30662 929 if (netdev->flags & IFF_PROMISC)
28673b33 930 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
2ba30662
JS		 931 else if (netdev->flags & IFF_ALLMULTI)
932 flags = HNAE3_USER_MPE;
c60edc17
JS		 933
934 return flags;
935}
936
1db9b1bf 937static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 938{
9780cb97 939 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17 940 u8 new_flags;
76ad4f0e 941
c60edc17
JS		 942 new_flags = hns3_get_netdev_flags(netdev);
943
c631c696
JS		 944 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
945 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
c60edc17 946
c60edc17 947 /* User mode Promisc mode enable and vlan filtering is disabled to
c631c696 948 * let all packets in.
c60edc17 949 */
c60edc17 950 h->netdev_flags = new_flags;
c631c696
JS		 951 hns3_request_update_promisc_mode(h);
952}
953
954void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
955{
956 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
957
958 if (ops->request_update_promisc_mode)
959 ops->request_update_promisc_mode(handle);
c60edc17
JS		 960}
961
907676b1
YL		 962static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
963{
964 struct hns3_tx_spare *tx_spare = ring->tx_spare;
965 u32 ntc, ntu;
966
967 /* This smp_load_acquire() pairs with smp_store_release() in
968 * hns3_tx_spare_update() called in tx desc cleaning process.
969 */
970 ntc = smp_load_acquire(&tx_spare->last_to_clean);
971 ntu = tx_spare->next_to_use;
972
973 if (ntc > ntu)
974 return ntc - ntu - 1;
975
976 /* The free tx buffer is divided into two part, so pick the
977 * larger one.
978 */
38b99e1e 979 return max(ntc, tx_spare->len - ntu) - 1;
907676b1
YL		 980}
981
982static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
983{
984 struct hns3_tx_spare *tx_spare = ring->tx_spare;
985
986 if (!tx_spare ||
987 tx_spare->last_to_clean == tx_spare->next_to_clean)
988 return;
989
990 /* This smp_store_release() pairs with smp_load_acquire() in
991 * hns3_tx_spare_space() called in xmit process.
992 */
993 smp_store_release(&tx_spare->last_to_clean,
994 tx_spare->next_to_clean);
995}
996
997static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
998 struct sk_buff *skb,
999 u32 space)
1000{
1001 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1002 skb_headlen(skb);
1003
1004 if (len > ring->tx_copybreak)
1005 return false;
1006
1007 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1008 u64_stats_update_begin(&ring->syncp);
1009 ring->stats.tx_spare_full++;
1010 u64_stats_update_end(&ring->syncp);
1011 return false;
1012 }
1013
1014 return true;
1015}
1016
7459775e
YL		 1017static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1018 struct sk_buff *skb,
1019 u32 space)
1020{
1021 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1022 (!skb_has_frag_list(skb) &&
1023 skb_shinfo(skb)->nr_frags < tx_sgl))
1024 return false;
1025
1026 if (space < HNS3_MAX_SGL_SIZE) {
1027 u64_stats_update_begin(&ring->syncp);
1028 ring->stats.tx_spare_full++;
1029 u64_stats_update_end(&ring->syncp);
1030 return false;
1031 }
1032
1033 return true;
1034}
1035
907676b1
YL		 1036static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1037{
1038 struct hns3_tx_spare *tx_spare;
1039 struct page *page;
1a00197b 1040 u32 alloc_size;
907676b1
YL		 1041 dma_addr_t dma;
1042 int order;
1043
1a00197b
HT		 1044 alloc_size = tx_spare_buf_size ? tx_spare_buf_size :
1045 ring->tqp->handle->kinfo.tx_spare_buf_size;
1046 if (!alloc_size)
907676b1
YL		 1047 return;
1048
1a00197b 1049 order = get_order(alloc_size);
907676b1
YL		 1050 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1051 GFP_KERNEL);
1052 if (!tx_spare) {
1053 /* The driver still work without the tx spare buffer */
1054 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1055 return;
1056 }
1057
1058 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1059 GFP_KERNEL, order);
1060 if (!page) {
1061 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1062 devm_kfree(ring_to_dev(ring), tx_spare);
1063 return;
1064 }
1065
1066 dma = dma_map_page(ring_to_dev(ring), page, 0,
1067 PAGE_SIZE << order, DMA_TO_DEVICE);
1068 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1069 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1070 put_page(page);
1071 devm_kfree(ring_to_dev(ring), tx_spare);
1072 return;
1073 }
1074
1075 tx_spare->dma = dma;
1076 tx_spare->buf = page_address(page);
1077 tx_spare->len = PAGE_SIZE << order;
1078 ring->tx_spare = tx_spare;
1079}
1080
1081/* Use hns3_tx_spare_space() to make sure there is enough buffer
1082 * before calling below function to allocate tx buffer.
1083 */
1084static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1085 unsigned int size, dma_addr_t *dma,
1086 u32 *cb_len)
1087{
1088 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1089 u32 ntu = tx_spare->next_to_use;
1090
1091 size = ALIGN(size, dma_get_cache_alignment());
1092 *cb_len = size;
1093
1094 /* Tx spare buffer wraps back here because the end of
1095 * freed tx buffer is not enough.
1096 */
1097 if (ntu + size > tx_spare->len) {
1098 *cb_len += (tx_spare->len - ntu);
1099 ntu = 0;
1100 }
1101
1102 tx_spare->next_to_use = ntu + size;
1103 if (tx_spare->next_to_use == tx_spare->len)
1104 tx_spare->next_to_use = 0;
1105
1106 *dma = tx_spare->dma + ntu;
1107
1108 return tx_spare->buf + ntu;
1109}
1110
1111static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1112{
1113 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1114
1115 if (len > tx_spare->next_to_use) {
1116 len -= tx_spare->next_to_use;
1117 tx_spare->next_to_use = tx_spare->len - len;
1118 } else {
1119 tx_spare->next_to_use -= len;
1120 }
1121}
1122
1123static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1124 struct hns3_desc_cb *cb)
1125{
1126 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1127 u32 ntc = tx_spare->next_to_clean;
1128 u32 len = cb->length;
1129
1130 tx_spare->next_to_clean += len;
1131
1132 if (tx_spare->next_to_clean >= tx_spare->len) {
1133 tx_spare->next_to_clean -= tx_spare->len;
1134
1135 if (tx_spare->next_to_clean) {
1136 ntc = 0;
1137 len = tx_spare->next_to_clean;
1138 }
1139 }
1140
1141 /* This tx spare buffer is only really reclaimed after calling
1142 * hns3_tx_spare_update(), so it is still safe to use the info in
7459775e
YL		 1143 * the tx buffer to do the dma sync or sg unmapping after
1144 * tx_spare->next_to_clean is moved forword.
907676b1
YL		 1145 */
1146 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1147 dma_addr_t dma = tx_spare->dma + ntc;
1148
1149 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1150 DMA_TO_DEVICE);
7459775e
YL		 1151 } else {
1152 struct sg_table *sgt = tx_spare->buf + ntc;
1153
1154 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1155 DMA_TO_DEVICE);
907676b1
YL		 1156 }
1157}
1158
3e281621 1159static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
811c0830 1160 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
76ad4f0e
S		 1161{
1162 u32 l4_offset, hdr_len;
1163 union l3_hdr_info l3;
1164 union l4_hdr_info l4;
1165 u32 l4_paylen;
1166 int ret;
1167
1168 if (!skb_is_gso(skb))
1169 return 0;
1170
1171 ret = skb_cow_head(skb, 0);
8ae10cfb 1172 if (unlikely(ret < 0))
76ad4f0e
S		 1173 return ret;
1174
1175 l3.hdr = skb_network_header(skb);
1176 l4.hdr = skb_transport_header(skb);
1177
1178 /* Software should clear the IPv4's checksum field when tso is
1179 * needed.
1180 */
1181 if (l3.v4->version == 4)
1182 l3.v4->check = 0;
1183
9b2f3477 1184 /* tunnel packet */
76ad4f0e
S		 1185 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1186 SKB_GSO_GRE_CSUM |
3e281621
HT		 1187 SKB_GSO_UDP_TUNNEL |
1188 SKB_GSO_UDP_TUNNEL_CSUM)) {
76ad4f0e
S		 1189 /* reset l3&l4 pointers from outer to inner headers */
1190 l3.hdr = skb_inner_network_header(skb);
1191 l4.hdr = skb_inner_transport_header(skb);
1192
1193 /* Software should clear the IPv4's checksum field when
1194 * tso is needed.
1195 */
1196 if (l3.v4->version == 4)
1197 l3.v4->check = 0;
1198 }
1199
9b2f3477 1200 /* normal or tunnel packet */
76ad4f0e 1201 l4_offset = l4.hdr - skb->data;
76ad4f0e 1202
9b2f3477 1203 /* remove payload length from inner pseudo checksum when tso */
76ad4f0e 1204 l4_paylen = skb->len - l4_offset;
0692cfe9
HT		 1205
1206 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1207 hdr_len = sizeof(*l4.udp) + l4_offset;
1208 csum_replace_by_diff(&l4.udp->check,
1209 (__force __wsum)htonl(l4_paylen));
1210 } else {
1211 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1212 csum_replace_by_diff(&l4.tcp->check,
1213 (__force __wsum)htonl(l4_paylen));
1214 }
76ad4f0e 1215
811c0830
YL		 1216 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1217
76ad4f0e 1218 /* find the txbd field values */
3e281621 1219 *paylen_fdop_ol4cs = skb->len - hdr_len;
cde4ffad 1220 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e 1221
3e281621
HT		 1222 /* offload outer UDP header checksum */
1223 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1224 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1225
76ad4f0e
S		 1226 /* get MSS for TSO */
1227 *mss = skb_shinfo(skb)->gso_size;
1228
698a8954
YL		 1229 trace_hns3_tso(skb);
1230
76ad4f0e
S		 1231 return 0;
1232}
1233
1898d4e4
S		 1234static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1235 u8 *il4_proto)
76ad4f0e 1236{
1a6e552d 1237 union l3_hdr_info l3;
76ad4f0e
S		 1238 unsigned char *l4_hdr;
1239 unsigned char *exthdr;
1240 u8 l4_proto_tmp;
1241 __be16 frag_off;
1242
1243 /* find outer header point */
1244 l3.hdr = skb_network_header(skb);
35f58fd7 1245 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 1246
1247 if (skb->protocol == htons(ETH_P_IPV6)) {
1248 exthdr = l3.hdr + sizeof(*l3.v6);
1249 l4_proto_tmp = l3.v6->nexthdr;
1250 if (l4_hdr != exthdr)
1251 ipv6_skip_exthdr(skb, exthdr - skb->data,
1252 &l4_proto_tmp, &frag_off);
1253 } else if (skb->protocol == htons(ETH_P_IP)) {
1254 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 1255 } else {
1256 return -EINVAL;
76ad4f0e
S		 1257 }
1258
1259 *ol4_proto = l4_proto_tmp;
1260
1261 /* tunnel packet */
1262 if (!skb->encapsulation) {
1263 *il4_proto = 0;
1898d4e4 1264 return 0;
76ad4f0e
S		 1265 }
1266
1267 /* find inner header point */
1268 l3.hdr = skb_inner_network_header(skb);
1269 l4_hdr = skb_inner_transport_header(skb);
1270
1271 if (l3.v6->version == 6) {
1272 exthdr = l3.hdr + sizeof(*l3.v6);
1273 l4_proto_tmp = l3.v6->nexthdr;
1274 if (l4_hdr != exthdr)
1275 ipv6_skip_exthdr(skb, exthdr - skb->data,
1276 &l4_proto_tmp, &frag_off);
1277 } else if (l3.v4->version == 4) {
1278 l4_proto_tmp = l3.v4->protocol;
1279 }
1280
1281 *il4_proto = l4_proto_tmp;
1898d4e4
S		 1282
1283 return 0;
76ad4f0e
S		 1284}
1285
3db084d2
YL		 1286/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1287 * and it is udp packet, which has a dest port as the IANA assigned.
1288 * the hardware is expected to do the checksum offload, but the
1289 * hardware will not do the checksum offload when udp dest port is
905416f1 1290 * 4789, 4790 or 6081.
3db084d2
YL		 1291 */
1292static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1293{
ade36cce
HT		 1294 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1295 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
1a6e552d 1296 union l4_hdr_info l4;
3db084d2 1297
ade36cce
HT		 1298 /* device version above V3(include V3), the hardware can
1299 * do this checksum offload.
1300 */
1301 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1302 return false;
1303
3db084d2
YL		 1304 l4.hdr = skb_transport_header(skb);
1305
bea96410 1306 if (!(!skb->encapsulation &&
a156998f 1307 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
905416f1
HC		 1308 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1309 l4.udp->dest == htons(4790))))
3db084d2
YL		 1310 return false;
1311
3db084d2
YL		 1312 return true;
1313}
1314
757cd1e4
YL		 1315static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1316 u32 *ol_type_vlan_len_msec)
76ad4f0e 1317{
757cd1e4
YL		 1318 u32 l2_len, l3_len, l4_len;
1319 unsigned char *il2_hdr;
1a6e552d 1320 union l3_hdr_info l3;
757cd1e4 1321 union l4_hdr_info l4;
76ad4f0e
S		 1322
1323 l3.hdr = skb_network_header(skb);
757cd1e4 1324 l4.hdr = skb_transport_header(skb);
76ad4f0e 1325
757cd1e4
YL		 1326 /* compute OL2 header size, defined in 2 Bytes */
1327 l2_len = l3.hdr - skb->data;
1328 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1329
1330 /* compute OL3 header size, defined in 4 Bytes */
1331 l3_len = l4.hdr - l3.hdr;
1332 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 1333
757cd1e4 1334 il2_hdr = skb_inner_mac_header(skb);
9b2f3477 1335 /* compute OL4 header size, defined in 4 Bytes */
757cd1e4
YL		 1336 l4_len = il2_hdr - l4.hdr;
1337 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1338
1339 /* define outer network header type */
1340 if (skb->protocol == htons(ETH_P_IP)) {
1341 if (skb_is_gso(skb))
cde4ffad 1342 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 1343 HNS3_TXD_OL3T_S,
1344 HNS3_OL3T_IPV4_CSUM);
1345 else
cde4ffad 1346 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 1347 HNS3_TXD_OL3T_S,
1348 HNS3_OL3T_IPV4_NO_CSUM);
757cd1e4
YL		 1349 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1350 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1351 HNS3_OL3T_IPV6);
1352 }
1353
1354 if (ol4_proto == IPPROTO_UDP)
1355 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1356 HNS3_TUN_MAC_IN_UDP);
1357 else if (ol4_proto == IPPROTO_GRE)
1358 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1359 HNS3_TUN_NVGRE);
1360}
1361
1362static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1363 u8 il4_proto, u32 *type_cs_vlan_tso,
1364 u32 *ol_type_vlan_len_msec)
1365{
c264ed44 1366 unsigned char *l2_hdr = skb->data;
757cd1e4
YL		 1367 u32 l4_proto = ol4_proto;
1368 union l4_hdr_info l4;
1369 union l3_hdr_info l3;
1370 u32 l2_len, l3_len;
1371
1372 l4.hdr = skb_transport_header(skb);
1373 l3.hdr = skb_network_header(skb);
1374
1375 /* handle encapsulation skb */
1376 if (skb->encapsulation) {
1377 /* If this is a not UDP/GRE encapsulation skb */
1378 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S		 1379 /* drop the skb tunnel packet if hardware don't support,
1380 * because hardware can't calculate csum when TSO.
1381 */
1382 if (skb_is_gso(skb))
1383 return -EDOM;
1384
1385 /* the stack computes the IP header already,
1386 * driver calculate l4 checksum when not TSO.
1387 */
9bb5a495 1388 return skb_checksum_help(skb);
76ad4f0e
S		 1389 }
1390
757cd1e4
YL		 1391 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1392
1393 /* switch to inner header */
1394 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 1395 l3.hdr = skb_inner_network_header(skb);
757cd1e4 1396 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S		 1397 l4_proto = il4_proto;
1398 }
1399
1400 if (l3.v4->version == 4) {
cde4ffad
YL		 1401 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1402 HNS3_L3T_IPV4);
76ad4f0e
S		 1403
1404 /* the stack computes the IP header already, the only time we
1405 * need the hardware to recompute it is in the case of TSO.
1406 */
1407 if (skb_is_gso(skb))
cde4ffad 1408 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 1409 } else if (l3.v6->version == 6) {
cde4ffad
YL		 1410 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1411 HNS3_L3T_IPV6);
76ad4f0e
S		 1412 }
1413
757cd1e4
YL		 1414 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1415 l2_len = l3.hdr - l2_hdr;
1416 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1417
1418 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1419 l3_len = l4.hdr - l3.hdr;
1420 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1421
1422 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S		 1423 switch (l4_proto) {
1424 case IPPROTO_TCP:
cde4ffad
YL		 1425 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1426 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1427 HNS3_L4T_TCP);
757cd1e4
YL		 1428 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1429 l4.tcp->doff);
76ad4f0e
S		 1430 break;
1431 case IPPROTO_UDP:
d18e8118
YM		 1432 if (hns3_tunnel_csum_bug(skb)) {
1433 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1434
1435 return ret ? ret : skb_checksum_help(skb);
1436 }
3db084d2 1437
cde4ffad
YL		 1438 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1439 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1440 HNS3_L4T_UDP);
757cd1e4
YL		 1441 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1442 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 1443 break;
1444 case IPPROTO_SCTP:
cde4ffad
YL		 1445 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1446 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1447 HNS3_L4T_SCTP);
757cd1e4
YL		 1448 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1449 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 1450 break;
1451 default:
1452 /* drop the skb tunnel packet if hardware don't support,
1453 * because hardware can't calculate csum when TSO.
1454 */
1455 if (skb_is_gso(skb))
1456 return -EDOM;
1457
1458 /* the stack computes the IP header already,
1459 * driver calculate l4 checksum when not TSO.
1460 */
9bb5a495 1461 return skb_checksum_help(skb);
76ad4f0e
S		 1462 }
1463
1464 return 0;
1465}
1466
eb977d99
YL		 1467static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1468 struct sk_buff *skb)
9699cffe 1469{
44e626f7 1470 struct hnae3_handle *handle = tx_ring->tqp->handle;
592b0179 1471 struct hnae3_ae_dev *ae_dev;
eb977d99
YL		 1472 struct vlan_ethhdr *vhdr;
1473 int rc;
1474
1475 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1476 skb_vlan_tag_present(skb)))
1477 return 0;
44e626f7 1478
592b0179
GL		 1479 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1480 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1481 * will cause RAS error.
44e626f7 1482 */
592b0179 1483 ae_dev = pci_get_drvdata(handle->pdev);
44e626f7 1484 if (unlikely(skb_vlan_tagged_multi(skb) &&
592b0179 1485 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
44e626f7
JS		 1486 handle->port_base_vlan_state ==
1487 HNAE3_PORT_BASE_VLAN_ENABLE))
1488 return -EINVAL;
1489
9699cffe 1490 if (skb->protocol == htons(ETH_P_8021Q) &&
eb977d99 1491 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
9699cffe
PL		 1492 /* When HW VLAN acceleration is turned off, and the stack
1493 * sets the protocol to 802.1q, the driver just need to
1494 * set the protocol to the encapsulated ethertype.
1495 */
1496 skb->protocol = vlan_get_protocol(skb);
1497 return 0;
1498 }
1499
1500 if (skb_vlan_tag_present(skb)) {
9699cffe
PL		 1501 /* Based on hw strategy, use out_vtag in two layer tag case,
1502 * and use inner_vtag in one tag case.
1503 */
eb977d99
YL		 1504 if (skb->protocol == htons(ETH_P_8021Q) &&
1505 handle->port_base_vlan_state ==
1506 HNAE3_PORT_BASE_VLAN_DISABLE)
1507 rc = HNS3_OUTER_VLAN_TAG;
1508 else
1509 rc = HNS3_INNER_VLAN_TAG;
1510
1511 skb->protocol = vlan_get_protocol(skb);
1512 return rc;
9699cffe
PL		 1513 }
1514
eb977d99
YL		 1515 rc = skb_cow_head(skb, 0);
1516 if (unlikely(rc < 0))
1517 return rc;
1518
1519 vhdr = (struct vlan_ethhdr *)skb->data;
1520 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1521 & VLAN_PRIO_MASK);
1522
9699cffe
PL		 1523 skb->protocol = vlan_get_protocol(skb);
1524 return 0;
1525}
1526
66d52f3b
HT		 1527/* check if the hardware is capable of checksum offloading */
1528static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1529{
1530 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1531
1532 /* Kindly note, due to backward compatibility of the TX descriptor,
1533 * HW checksum of the non-IP packets and GSO packets is handled at
1534 * different place in the following code
1535 */
b9046e88 1536 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
66d52f3b
HT		 1537 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1538 return false;
1539
1540 return true;
1541}
1542
eb977d99 1543static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
811c0830
YL		 1544 struct sk_buff *skb, struct hns3_desc *desc,
1545 struct hns3_desc_cb *desc_cb)
eb977d99
YL		 1546{
1547 u32 ol_type_vlan_len_msec = 0;
3e281621 1548 u32 paylen_ol4cs = skb->len;
eb977d99 1549 u32 type_cs_vlan_tso = 0;
66d52f3b 1550 u16 mss_hw_csum = 0;
eb977d99
YL		 1551 u16 inner_vtag = 0;
1552 u16 out_vtag = 0;
eb977d99
YL		 1553 int ret;
1554
1555 ret = hns3_handle_vtags(ring, skb);
1556 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1557 u64_stats_update_begin(&ring->syncp);
1558 ring->stats.tx_vlan_err++;
1559 u64_stats_update_end(&ring->syncp);
eb977d99
YL		 1560 return ret;
1561 } else if (ret == HNS3_INNER_VLAN_TAG) {
1562 inner_vtag = skb_vlan_tag_get(skb);
1563 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1564 VLAN_PRIO_MASK;
1565 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1566 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1567 out_vtag = skb_vlan_tag_get(skb);
1568 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1569 VLAN_PRIO_MASK;
1570 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1571 1);
1572 }
1573
811c0830
YL		 1574 desc_cb->send_bytes = skb->len;
1575
eb977d99
YL		 1576 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1577 u8 ol4_proto, il4_proto;
1578
66d52f3b
HT		 1579 if (hns3_check_hw_tx_csum(skb)) {
1580 /* set checksum start and offset, defined in 2 Bytes */
1581 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1582 skb_checksum_start_offset(skb) >> 1);
1583 hns3_set_field(ol_type_vlan_len_msec,
1584 HNS3_TXD_CSUM_OFFSET_S,
1585 skb->csum_offset >> 1);
1586 mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1587 goto out_hw_tx_csum;
1588 }
1589
eb977d99
YL		 1590 skb_reset_mac_len(skb);
1591
1592 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
8ae10cfb 1593 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1594 u64_stats_update_begin(&ring->syncp);
1595 ring->stats.tx_l4_proto_err++;
1596 u64_stats_update_end(&ring->syncp);
eb977d99 1597 return ret;
b20d7fe5 1598 }
eb977d99
YL		 1599
1600 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1601 &type_cs_vlan_tso,
1602 &ol_type_vlan_len_msec);
8ae10cfb 1603 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1604 u64_stats_update_begin(&ring->syncp);
1605 ring->stats.tx_l2l3l4_err++;
1606 u64_stats_update_end(&ring->syncp);
eb977d99 1607 return ret;
b20d7fe5 1608 }
eb977d99 1609
3e281621 1610 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum,
811c0830 1611 &type_cs_vlan_tso, &desc_cb->send_bytes);
8ae10cfb 1612 if (unlikely(ret < 0)) {
b20d7fe5
YL		 1613 u64_stats_update_begin(&ring->syncp);
1614 ring->stats.tx_tso_err++;
1615 u64_stats_update_end(&ring->syncp);
eb977d99 1616 return ret;
b20d7fe5 1617 }
eb977d99
YL		 1618 }
1619
66d52f3b 1620out_hw_tx_csum:
eb977d99
YL		 1621 /* Set txbd */
1622 desc->tx.ol_type_vlan_len_msec =
1623 cpu_to_le32(ol_type_vlan_len_msec);
1624 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
3e281621 1625 desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs);
66d52f3b 1626 desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum);
eb977d99
YL		 1627 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1628 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1629
1630 return 0;
1631}
1632
8677d78c
YL		 1633static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1634 unsigned int size)
76ad4f0e 1635{
8ae10cfb
YL		 1636#define HNS3_LIKELY_BD_NUM 1
1637
76ad4f0e 1638 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1e8a7977 1639 unsigned int frag_buf_num;
47e7b13b 1640 int k, sizeoflast;
bcdb12b7 1641
ceca4a5e 1642 if (likely(size <= HNS3_MAX_BD_SIZE)) {
ceca4a5e
YL		 1643 desc->addr = cpu_to_le64(dma);
1644 desc->tx.send_size = cpu_to_le16(size);
ceca4a5e 1645 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1646 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
ceca4a5e 1647
698a8954 1648 trace_hns3_tx_desc(ring, ring->next_to_use);
ceca4a5e 1649 ring_ptr_move_fw(ring, next_to_use);
8ae10cfb 1650 return HNS3_LIKELY_BD_NUM;
ceca4a5e
YL		 1651 }
1652
5f543a54 1653 frag_buf_num = hns3_tx_bd_count(size);
48ae74c9 1654 sizeoflast = size % HNS3_MAX_BD_SIZE;
1e8a7977
FL		 1655 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1656
1657 /* When frag size is bigger than hardware limit, split this frag */
1658 for (k = 0; k < frag_buf_num; k++) {
1e8a7977
FL		 1659 /* now, fill the descriptor */
1660 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7 1661 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
9b2f3477 1662 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977 1663 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1664 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1e8a7977 1665
698a8954 1666 trace_hns3_tx_desc(ring, ring->next_to_use);
9b2f3477 1667 /* move ring pointer to next */
1e8a7977
FL		 1668 ring_ptr_move_fw(ring, next_to_use);
1669
1e8a7977
FL		 1670 desc = &ring->desc[ring->next_to_use];
1671 }
76ad4f0e 1672
8ae10cfb 1673 return frag_buf_num;
76ad4f0e
S		 1674}
1675
8677d78c
YL		 1676static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1677 unsigned int type)
1678{
1679 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1680 struct device *dev = ring_to_dev(ring);
1681 unsigned int size;
1682 dma_addr_t dma;
1683
1684 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1685 struct sk_buff *skb = (struct sk_buff *)priv;
1686
1687 size = skb_headlen(skb);
1688 if (!size)
1689 return 0;
1690
1691 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
907676b1
YL		 1692 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1693 /* Head data has been filled in hns3_handle_tx_bounce(),
1694 * just return 0 here.
1695 */
1696 return 0;
8677d78c
YL		 1697 } else {
1698 skb_frag_t *frag = (skb_frag_t *)priv;
1699
1700 size = skb_frag_size(frag);
1701 if (!size)
1702 return 0;
1703
1704 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1705 }
1706
1707 if (unlikely(dma_mapping_error(dev, dma))) {
1708 u64_stats_update_begin(&ring->syncp);
1709 ring->stats.sw_err_cnt++;
1710 u64_stats_update_end(&ring->syncp);
1711 return -ENOMEM;
1712 }
1713
1714 desc_cb->priv = priv;
1715 desc_cb->length = size;
1716 desc_cb->dma = dma;
1717 desc_cb->type = type;
1718
1719 return hns3_fill_desc(ring, dma, size);
1720}
1721
8ae10cfb
YL		 1722static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1723 unsigned int bd_num)
76ad4f0e 1724{
8ae10cfb 1725 unsigned int size;
42611b70 1726 int i;
76ad4f0e 1727
8ae10cfb
YL		 1728 size = skb_headlen(skb);
1729 while (size > HNS3_MAX_BD_SIZE) {
1730 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1731 size -= HNS3_MAX_BD_SIZE;
1732
1733 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1734 return bd_num;
1735 }
76ad4f0e 1736
8ae10cfb
YL		 1737 if (size) {
1738 bd_size[bd_num++] = size;
1739 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1740 return bd_num;
1741 }
76ad4f0e 1742
3d5f3741 1743 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
d7840976 1744 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8ae10cfb
YL		 1745 size = skb_frag_size(frag);
1746 if (!size)
1747 continue;
1748
1749 while (size > HNS3_MAX_BD_SIZE) {
1750 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1751 size -= HNS3_MAX_BD_SIZE;
1752
1753 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1754 return bd_num;
1755 }
1756
1757 bd_size[bd_num++] = size;
1758 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1759 return bd_num;
1760 }
1761
1762 return bd_num;
1763}
1764
fd665b3d 1765static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
d5d5e019
YL		 1766 u8 max_non_tso_bd_num, unsigned int bd_num,
1767 unsigned int recursion_level)
8ae10cfb 1768{
d5d5e019
YL		 1769#define HNS3_MAX_RECURSION_LEVEL 24
1770
8ae10cfb 1771 struct sk_buff *frag_skb;
8ae10cfb
YL		 1772
1773 /* If the total len is within the max bd limit */
d5d5e019
YL		 1774 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1775 !skb_has_frag_list(skb) &&
fd665b3d 1776 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
8ae10cfb
YL		 1777 return skb_shinfo(skb)->nr_frags + 1U;
1778
d5d5e019
YL		 1779 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1780 return UINT_MAX;
8ae10cfb
YL		 1781
1782 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
8ae10cfb
YL		 1783 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1784 return bd_num;
1785
1786 skb_walk_frags(skb, frag_skb) {
d5d5e019
YL		 1787 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1788 bd_num, recursion_level + 1);
8ae10cfb
YL		 1789 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1790 return bd_num;
3d5f3741 1791 }
76ad4f0e 1792
3d5f3741 1793 return bd_num;
76ad4f0e
S		 1794}
1795
db4970aa
YL		 1796static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1797{
1798 if (!skb->encapsulation)
1799 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1800
1801 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1802}
1803
fd665b3d
HT		 1804/* HW need every continuous max_non_tso_bd_num buffer data to be larger
1805 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1806 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1807 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1808 * than MSS except the last max_non_tso_bd_num - 1 frags.
db4970aa 1809 */
8ae10cfb 1810static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
fd665b3d 1811 unsigned int bd_num, u8 max_non_tso_bd_num)
db4970aa 1812{
db4970aa
YL		 1813 unsigned int tot_len = 0;
1814 int i;
1815
fd665b3d 1816 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
8ae10cfb 1817 tot_len += bd_size[i];
db4970aa 1818
fd665b3d
HT		 1819 /* ensure the first max_non_tso_bd_num frags is greater than
1820 * mss + header
1821 */
1822 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
8ae10cfb 1823 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
db4970aa
YL		 1824 return true;
1825
fd665b3d
HT		 1826 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1827 * than mss except the last one.
8ae10cfb 1828 */
fd665b3d 1829 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
8ae10cfb 1830 tot_len -= bd_size[i];
fd665b3d 1831 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
db4970aa
YL		 1832
1833 if (tot_len < skb_shinfo(skb)->gso_size)
1834 return true;
1835 }
1836
1837 return false;
1838}
1839
698a8954
YL		 1840void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1841{
9d8d5a36 1842 int i;
698a8954
YL		 1843
1844 for (i = 0; i < MAX_SKB_FRAGS; i++)
1845 size[i] = skb_frag_size(&shinfo->frags[i]);
1846}
1847
d5d5e019
YL		 1848static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1849 struct sk_buff *skb,
d5d5e019
YL		 1850 unsigned int bd_num)
1851{
1852 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1853 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1854 */
1855 if (bd_num == UINT_MAX) {
1856 u64_stats_update_begin(&ring->syncp);
1857 ring->stats.over_max_recursion++;
1858 u64_stats_update_end(&ring->syncp);
1859 return -ENOMEM;
1860 }
1861
1862 /* The skb->len has exceeded the hw limitation, linearization
1863 * will not help.
1864 */
1865 if (skb->len > HNS3_MAX_TSO_SIZE ||
adfb7b49 1866 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
d5d5e019
YL		 1867 u64_stats_update_begin(&ring->syncp);
1868 ring->stats.hw_limitation++;
1869 u64_stats_update_end(&ring->syncp);
1870 return -ENOMEM;
1871 }
1872
1873 if (__skb_linearize(skb)) {
1874 u64_stats_update_begin(&ring->syncp);
1875 ring->stats.sw_err_cnt++;
1876 u64_stats_update_end(&ring->syncp);
1877 return -ENOMEM;
1878 }
1879
1880 return 0;
1881}
1882
3d5f3741 1883static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
2a597eff 1884 struct net_device *netdev,
d1a37ded 1885 struct sk_buff *skb)
76ad4f0e 1886{
2a597eff 1887 struct hns3_nic_priv *priv = netdev_priv(netdev);
fd665b3d 1888 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
8ae10cfb 1889 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
42611b70 1890 unsigned int bd_num;
76ad4f0e 1891
d5d5e019 1892 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
fd665b3d 1893 if (unlikely(bd_num > max_non_tso_bd_num)) {
8ae10cfb 1894 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
fd665b3d
HT		 1895 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1896 max_non_tso_bd_num)) {
6ad595bc 1897 trace_hns3_over_max_bd(skb);
db4970aa 1898 goto out;
698a8954 1899 }
db4970aa 1900
adfb7b49 1901 if (hns3_skb_linearize(ring, skb, bd_num))
51e8439f 1902 return -ENOMEM;
3d5f3741 1903
d1a37ded 1904 bd_num = hns3_tx_bd_count(skb->len);
42611b70 1905
3d5f3741
YL		 1906 u64_stats_update_begin(&ring->syncp);
1907 ring->stats.tx_copy++;
1908 u64_stats_update_end(&ring->syncp);
51e8439f
PL		 1909 }
1910
db4970aa 1911out:
2a597eff
YL		 1912 if (likely(ring_space(ring) >= bd_num))
1913 return bd_num;
76ad4f0e 1914
2a597eff
YL		 1915 netif_stop_subqueue(netdev, ring->queue_index);
1916 smp_mb(); /* Memory barrier before checking ring_space */
1917
1918 /* Start queue in case hns3_clean_tx_ring has just made room
1919 * available and has not seen the queue stopped state performed
1920 * by netif_stop_subqueue above.
1921 */
1922 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1923 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1924 netif_start_subqueue(netdev, ring->queue_index);
1925 return bd_num;
1926 }
1927
d5d5e019
YL		 1928 u64_stats_update_begin(&ring->syncp);
1929 ring->stats.tx_busy++;
1930 u64_stats_update_end(&ring->syncp);
1931
2a597eff 1932 return -EBUSY;
76ad4f0e
S		 1933}
1934
ba3f808f 1935static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1936{
1937 struct device *dev = ring_to_dev(ring);
1938 unsigned int i;
1939
1940 for (i = 0; i < ring->desc_num; i++) {
8ceca59f 1941 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
26f1ccdf 1942 struct hns3_desc_cb *desc_cb;
8ceca59f
YL		 1943
1944 memset(desc, 0, sizeof(*desc));
1945
76ad4f0e
S		 1946 /* check if this is where we started */
1947 if (ring->next_to_use == next_to_use_orig)
1948 break;
1949
aa9d22dd
YL		 1950 /* rollback one */
1951 ring_ptr_move_bw(ring, next_to_use);
1952
26f1ccdf
YL		 1953 desc_cb = &ring->desc_cb[ring->next_to_use];
1954
1955 if (!desc_cb->dma)
8ceca59f
YL		 1956 continue;
1957
76ad4f0e 1958 /* unmap the descriptor dma address */
26f1ccdf
YL		 1959 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
1960 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
1961 DMA_TO_DEVICE);
907676b1
YL		 1962 else if (desc_cb->type &
1963 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
1964 hns3_tx_spare_rollback(ring, desc_cb->length);
26f1ccdf
YL		 1965 else if (desc_cb->length)
1966 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
76ad4f0e
S		 1967 DMA_TO_DEVICE);
1968
26f1ccdf
YL		 1969 desc_cb->length = 0;
1970 desc_cb->dma = 0;
1971 desc_cb->type = DESC_TYPE_UNKNOWN;
76ad4f0e
S		 1972 }
1973}
1974
8ae10cfb 1975static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
26f1ccdf 1976 struct sk_buff *skb, unsigned int type)
8ae10cfb 1977{
d5d5e019 1978 struct sk_buff *frag_skb;
8ae10cfb
YL		 1979 int i, ret, bd_num = 0;
1980
8677d78c
YL		 1981 ret = hns3_map_and_fill_desc(ring, skb, type);
1982 if (unlikely(ret < 0))
1983 return ret;
8ae10cfb 1984
8677d78c 1985 bd_num += ret;
8ae10cfb
YL		 1986
1987 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1988 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1989
8677d78c 1990 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
8ae10cfb
YL		 1991 if (unlikely(ret < 0))
1992 return ret;
1993
1994 bd_num += ret;
1995 }
1996
d5d5e019
YL		 1997 skb_walk_frags(skb, frag_skb) {
1998 ret = hns3_fill_skb_to_desc(ring, frag_skb,
1999 DESC_TYPE_FRAGLIST_SKB);
2000 if (unlikely(ret < 0))
2001 return ret;
2002
2003 bd_num += ret;
2004 }
2005
8ae10cfb
YL		 2006 return bd_num;
2007}
2008
f6061a05
YL		 2009static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2010 bool doorbell)
2011{
2012 ring->pending_buf += num;
2013
2014 if (!doorbell) {
2015 u64_stats_update_begin(&ring->syncp);
2016 ring->stats.tx_more++;
2017 u64_stats_update_end(&ring->syncp);
2018 return;
2019 }
2020
2021 if (!ring->pending_buf)
2022 return;
2023
48ee56fd
YL		 2024 writel(ring->pending_buf,
2025 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
f6061a05 2026 ring->pending_buf = 0;
20d06ca2 2027 WRITE_ONCE(ring->last_to_use, ring->next_to_use);
f6061a05
YL		 2028}
2029
0bf5eb78
HT		 2030static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2031 struct hns3_desc *desc)
2032{
2033 struct hnae3_handle *h = hns3_get_handle(netdev);
2034
2035 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2036 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2037 return;
2038
2039 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2040}
2041
907676b1
YL		 2042static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2043 struct sk_buff *skb)
2044{
2045 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2046 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2047 unsigned int size = skb_headlen(skb);
2048 dma_addr_t dma;
2049 int bd_num = 0;
2050 u32 cb_len;
2051 void *buf;
2052 int ret;
2053
2054 if (skb->len <= ring->tx_copybreak) {
2055 size = skb->len;
2056 type = DESC_TYPE_BOUNCE_ALL;
2057 }
2058
2059 /* hns3_can_use_tx_bounce() is called to ensure the below
2060 * function can always return the tx buffer.
2061 */
2062 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2063
2064 ret = skb_copy_bits(skb, 0, buf, size);
2065 if (unlikely(ret < 0)) {
2066 hns3_tx_spare_rollback(ring, cb_len);
2067 u64_stats_update_begin(&ring->syncp);
2068 ring->stats.copy_bits_err++;
2069 u64_stats_update_end(&ring->syncp);
2070 return ret;
2071 }
2072
2073 desc_cb->priv = skb;
2074 desc_cb->length = cb_len;
2075 desc_cb->dma = dma;
2076 desc_cb->type = type;
2077
2078 bd_num += hns3_fill_desc(ring, dma, size);
2079
2080 if (type == DESC_TYPE_BOUNCE_HEAD) {
2081 ret = hns3_fill_skb_to_desc(ring, skb,
2082 DESC_TYPE_BOUNCE_HEAD);
2083 if (unlikely(ret < 0))
2084 return ret;
2085
2086 bd_num += ret;
2087 }
2088
2089 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2090 DMA_TO_DEVICE);
2091
2092 u64_stats_update_begin(&ring->syncp);
2093 ring->stats.tx_bounce++;
2094 u64_stats_update_end(&ring->syncp);
2095 return bd_num;
2096}
2097
7459775e
YL		 2098static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2099 struct sk_buff *skb)
2100{
2101 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2102 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2103 struct sg_table *sgt;
2104 int i, bd_num = 0;
2105 dma_addr_t dma;
2106 u32 cb_len;
2107 int nents;
2108
2109 if (skb_has_frag_list(skb))
2110 nfrag = HNS3_MAX_TSO_BD_NUM;
2111
2112 /* hns3_can_use_tx_sgl() is called to ensure the below
2113 * function can always return the tx buffer.
2114 */
2115 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2116 &dma, &cb_len);
2117
2118 /* scatterlist follows by the sg table */
2119 sgt->sgl = (struct scatterlist *)(sgt + 1);
2120 sg_init_table(sgt->sgl, nfrag);
2121 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2122 if (unlikely(nents < 0)) {
2123 hns3_tx_spare_rollback(ring, cb_len);
2124 u64_stats_update_begin(&ring->syncp);
2125 ring->stats.skb2sgl_err++;
2126 u64_stats_update_end(&ring->syncp);
2127 return -ENOMEM;
2128 }
2129
2130 sgt->orig_nents = nents;
2131 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2132 DMA_TO_DEVICE);
2133 if (unlikely(!sgt->nents)) {
2134 hns3_tx_spare_rollback(ring, cb_len);
2135 u64_stats_update_begin(&ring->syncp);
2136 ring->stats.map_sg_err++;
2137 u64_stats_update_end(&ring->syncp);
2138 return -ENOMEM;
2139 }
2140
2141 desc_cb->priv = skb;
2142 desc_cb->length = cb_len;
2143 desc_cb->dma = dma;
2144 desc_cb->type = DESC_TYPE_SGL_SKB;
2145
2146 for (i = 0; i < sgt->nents; i++)
2147 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2148 sg_dma_len(sgt->sgl + i));
2149
2150 u64_stats_update_begin(&ring->syncp);
2151 ring->stats.tx_sgl++;
2152 u64_stats_update_end(&ring->syncp);
2153
2154 return bd_num;
2155}
2156
907676b1
YL		 2157static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2158 struct sk_buff *skb)
2159{
2160 u32 space;
2161
2162 if (!ring->tx_spare)
2163 goto out;
2164
2165 space = hns3_tx_spare_space(ring);
2166
7459775e
YL		 2167 if (hns3_can_use_tx_sgl(ring, skb, space))
2168 return hns3_handle_tx_sgl(ring, skb);
2169
907676b1
YL		 2170 if (hns3_can_use_tx_bounce(ring, skb, space))
2171 return hns3_handle_tx_bounce(ring, skb);
2172
2173out:
2174 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2175}
2176
d43e5aca 2177netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 2178{
2179 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f06b903 2180 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
811c0830 2181 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
76ad4f0e 2182 struct netdev_queue *dev_queue;
8ae10cfb 2183 int pre_ntu, next_to_use_head;
f6061a05 2184 bool doorbell;
76ad4f0e 2185 int ret;
76ad4f0e 2186
36c67349 2187 /* Hardware can only handle short frames above 32 bytes */
f6061a05
YL		 2188 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2189 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
97b9e5c1
YL		 2190
2191 u64_stats_update_begin(&ring->syncp);
2192 ring->stats.sw_err_cnt++;
2193 u64_stats_update_end(&ring->syncp);
2194
36c67349 2195 return NETDEV_TX_OK;
f6061a05 2196 }
36c67349 2197
76ad4f0e
S		 2198 /* Prefetch the data used later */
2199 prefetch(skb->data);
2200
d1a37ded 2201 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
8ae10cfb
YL		 2202 if (unlikely(ret <= 0)) {
2203 if (ret == -EBUSY) {
f6061a05 2204 hns3_tx_doorbell(ring, 0, true);
2a597eff 2205 return NETDEV_TX_BUSY;
3d5f3741 2206 }
76ad4f0e 2207
8ae10cfb 2208 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
76ad4f0e 2209 goto out_err_tx_ok;
76ad4f0e
S		 2210 }
2211
76ad4f0e
S		 2212 next_to_use_head = ring->next_to_use;
2213
811c0830
YL		 2214 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2215 desc_cb);
cfdaeba5
YL		 2216 if (unlikely(ret < 0))
2217 goto fill_err;
2218
d5d5e019
YL		 2219 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2220 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2221 * need to be notified to the hw.
2222 */
907676b1 2223 ret = hns3_handle_desc_filling(ring, skb);
d5d5e019 2224 if (unlikely(ret <= 0))
aa9d22dd 2225 goto fill_err;
76ad4f0e 2226
8ae10cfb
YL		 2227 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2228 (ring->desc_num - 1);
0bf5eb78
HT		 2229
2230 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2231 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2232
8ae10cfb
YL		 2233 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2234 cpu_to_le16(BIT(HNS3_TXD_FE_B));
698a8954 2235 trace_hns3_tx_desc(ring, pre_ntu);
76ad4f0e 2236
0bf5eb78
HT		 2237 skb_tx_timestamp(skb);
2238
76ad4f0e 2239 /* Complete translate all packets */
5f06b903 2240 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
811c0830 2241 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
f6061a05 2242 netdev_xmit_more());
d5d5e019 2243 hns3_tx_doorbell(ring, ret, doorbell);
76ad4f0e
S		 2244
2245 return NETDEV_TX_OK;
2246
aa9d22dd 2247fill_err:
ba3f808f 2248 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 2249
2250out_err_tx_ok:
2251 dev_kfree_skb_any(skb);
f6061a05 2252 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
76ad4f0e 2253 return NETDEV_TX_OK;
76ad4f0e
S		 2254}
2255
2256static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2257{
9780cb97 2258 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2259 struct sockaddr *mac_addr = p;
2260 int ret;
2261
2262 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2263 return -EADDRNOTAVAIL;
2264
5ec2a51e
JS		 2265 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2266 netdev_info(netdev, "already using mac address %pM\n",
2267 mac_addr->sa_data);
2268 return 0;
2269 }
2270
8e6de441
HT		 2271 /* For VF device, if there is a perm_addr, then the user will not
2272 * be allowed to change the address.
2273 */
2274 if (!hns3_is_phys_func(h->pdev) &&
2275 !is_zero_ether_addr(netdev->perm_addr)) {
2276 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
2277 netdev->perm_addr, mac_addr->sa_data);
2278 return -EPERM;
2279 }
2280
59098055 2281 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 2282 if (ret) {
2283 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2284 return ret;
2285 }
2286
2287 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
2288
2289 return 0;
2290}
2291
26483246
XW		 2292static int hns3_nic_do_ioctl(struct net_device *netdev,
2293 struct ifreq *ifr, int cmd)
2294{
2295 struct hnae3_handle *h = hns3_get_handle(netdev);
2296
2297 if (!netif_running(netdev))
2298 return -EINVAL;
2299
2300 if (!h->ae_algo->ops->do_ioctl)
2301 return -EOPNOTSUPP;
2302
2303 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2304}
2305
76ad4f0e
S		 2306static int hns3_nic_set_features(struct net_device *netdev,
2307 netdev_features_t features)
2308{
181d454b 2309 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 2310 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 2311 struct hnae3_handle *h = priv->ae_handle;
1731be4c 2312 bool enable;
052ece6d 2313 int ret;
76ad4f0e 2314
5c9f6b39 2315 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL		 2316 enable = !!(features & NETIF_F_GRO_HW);
2317 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL		 2318 if (ret)
2319 return ret;
2320 }
2321
bd368416
JS		 2322 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2323 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL		 2324 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2325 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL		 2326 if (ret)
2327 return ret;
2328 }
2329
c17852a8 2330 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL		 2331 enable = !!(features & NETIF_F_NTUPLE);
2332 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS		 2333 }
2334
0205ec04
JS		 2335 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2336 h->ae_algo->ops->cls_flower_active(h)) {
2337 netdev_err(netdev,
2338 "there are offloaded TC filters active, cannot disable HW TC offload");
2339 return -EINVAL;
2340 }
2341
2ba30662
JS		 2342 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2343 h->ae_algo->ops->enable_vlan_filter) {
2344 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2345 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2346 if (ret)
2347 return ret;
2348 }
2349
76ad4f0e
S		 2350 netdev->features = features;
2351 return 0;
2352}
2353
2a7556bb
YL		 2354static netdev_features_t hns3_features_check(struct sk_buff *skb,
2355 struct net_device *dev,
2356 netdev_features_t features)
2357{
2358#define HNS3_MAX_HDR_LEN 480U
2359#define HNS3_MAX_L4_HDR_LEN 60U
2360
2361 size_t len;
2362
2363 if (skb->ip_summed != CHECKSUM_PARTIAL)
2364 return features;
2365
2366 if (skb->encapsulation)
2367 len = skb_inner_transport_header(skb) - skb->data;
2368 else
2369 len = skb_transport_header(skb) - skb->data;
2370
2371 /* Assume L4 is 60 byte as TCP is the only protocol with a
2372 * a flexible value, and it's max len is 60 bytes.
2373 */
2374 len += HNS3_MAX_L4_HDR_LEN;
2375
2376 /* Hardware only supports checksum on the skb with a max header
2377 * len of 480 bytes.
2378 */
2379 if (len > HNS3_MAX_HDR_LEN)
2380 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2381
2382 return features;
2383}
2384
6c88d9d7
PL		 2385static void hns3_nic_get_stats64(struct net_device *netdev,
2386 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 2387{
2388 struct hns3_nic_priv *priv = netdev_priv(netdev);
2389 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 2390 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 2391 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 2392 u64 rx_length_errors = 0;
2393 u64 rx_crc_errors = 0;
2394 u64 rx_multicast = 0;
76ad4f0e 2395 unsigned int start;
d3ec4ef6
JS		 2396 u64 tx_errors = 0;
2397 u64 rx_errors = 0;
76ad4f0e
S		 2398 unsigned int idx;
2399 u64 tx_bytes = 0;
2400 u64 rx_bytes = 0;
2401 u64 tx_pkts = 0;
2402 u64 rx_pkts = 0;
d2a5dca8
JS		 2403 u64 tx_drop = 0;
2404 u64 rx_drop = 0;
76ad4f0e 2405
b875cc37
JS		 2406 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2407 return;
2408
c5f65480
JS		 2409 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
2410
76ad4f0e
S		 2411 for (idx = 0; idx < queue_num; idx++) {
2412 /* fetch the tx stats */
5f06b903 2413 ring = &priv->ring[idx];
76ad4f0e 2414 do {
d36d36ce 2415 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 2416 tx_bytes += ring->stats.tx_bytes;
2417 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 2418 tx_drop += ring->stats.sw_err_cnt;
b20d7fe5
YL		 2419 tx_drop += ring->stats.tx_vlan_err;
2420 tx_drop += ring->stats.tx_l4_proto_err;
2421 tx_drop += ring->stats.tx_l2l3l4_err;
2422 tx_drop += ring->stats.tx_tso_err;
d5d5e019
YL		 2423 tx_drop += ring->stats.over_max_recursion;
2424 tx_drop += ring->stats.hw_limitation;
907676b1 2425 tx_drop += ring->stats.copy_bits_err;
7459775e
YL		 2426 tx_drop += ring->stats.skb2sgl_err;
2427 tx_drop += ring->stats.map_sg_err;
d3ec4ef6 2428 tx_errors += ring->stats.sw_err_cnt;
b20d7fe5
YL		 2429 tx_errors += ring->stats.tx_vlan_err;
2430 tx_errors += ring->stats.tx_l4_proto_err;
2431 tx_errors += ring->stats.tx_l2l3l4_err;
2432 tx_errors += ring->stats.tx_tso_err;
d5d5e019
YL		 2433 tx_errors += ring->stats.over_max_recursion;
2434 tx_errors += ring->stats.hw_limitation;
907676b1 2435 tx_errors += ring->stats.copy_bits_err;
7459775e
YL		 2436 tx_errors += ring->stats.skb2sgl_err;
2437 tx_errors += ring->stats.map_sg_err;
76ad4f0e
S		 2438 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2439
2440 /* fetch the rx stats */
5f06b903 2441 ring = &priv->ring[idx + queue_num];
76ad4f0e 2442 do {
d36d36ce 2443 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 2444 rx_bytes += ring->stats.rx_bytes;
2445 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 2446 rx_drop += ring->stats.l2_err;
d3ec4ef6 2447 rx_errors += ring->stats.l2_err;
8b552079 2448 rx_errors += ring->stats.l3l4_csum_err;
d3ec4ef6 2449 rx_crc_errors += ring->stats.l2_err;
d3ec4ef6
JS		 2450 rx_multicast += ring->stats.rx_multicast;
2451 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 2452 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
2453 }
2454
2455 stats->tx_bytes = tx_bytes;
2456 stats->tx_packets = tx_pkts;
2457 stats->rx_bytes = rx_bytes;
2458 stats->rx_packets = rx_pkts;
2459
d3ec4ef6
JS		 2460 stats->rx_errors = rx_errors;
2461 stats->multicast = rx_multicast;
2462 stats->rx_length_errors = rx_length_errors;
2463 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 2464 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2465
d3ec4ef6
JS		 2466 stats->tx_errors = tx_errors;
2467 stats->rx_dropped = rx_drop;
2468 stats->tx_dropped = tx_drop;
76ad4f0e
S		 2469 stats->collisions = netdev->stats.collisions;
2470 stats->rx_over_errors = netdev->stats.rx_over_errors;
2471 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2472 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2473 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2474 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2475 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2476 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2477 stats->tx_window_errors = netdev->stats.tx_window_errors;
2478 stats->rx_compressed = netdev->stats.rx_compressed;
2479 stats->tx_compressed = netdev->stats.tx_compressed;
2480}
2481
30d240df 2482static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 2483{
30d240df 2484 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
75718800 2485 struct hnae3_knic_private_info *kinfo;
30d240df
YL		 2486 u8 tc = mqprio_qopt->qopt.num_tc;
2487 u16 mode = mqprio_qopt->mode;
2488 u8 hw = mqprio_qopt->qopt.hw;
75718800 2489 struct hnae3_handle *h;
76ad4f0e 2490
30d240df
YL		 2491 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2492 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2493 return -EOPNOTSUPP;
2494
76ad4f0e
S		 2495 if (tc > HNAE3_MAX_TC)
2496 return -EINVAL;
2497
76ad4f0e
S		 2498 if (!netdev)
2499 return -EINVAL;
2500
75718800
YL		 2501 h = hns3_get_handle(netdev);
2502 kinfo = &h->kinfo;
2503
1c822948
YL		 2504 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2505
1cce5eb6 2506 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
5a5c9091 2507 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
76ad4f0e
S		 2508}
2509
0205ec04
JS		 2510static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2511 struct flow_cls_offload *flow)
2512{
2513 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid);
2514 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2515
2516 switch (flow->command) {
2517 case FLOW_CLS_REPLACE:
2518 if (h->ae_algo->ops->add_cls_flower)
2519 return h->ae_algo->ops->add_cls_flower(h, flow, tc);
2520 break;
2521 case FLOW_CLS_DESTROY:
2522 if (h->ae_algo->ops->del_cls_flower)
2523 return h->ae_algo->ops->del_cls_flower(h, flow);
2524 break;
2525 default:
2526 break;
2527 }
2528
2529 return -EOPNOTSUPP;
2530}
2531
2532static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2533 void *cb_priv)
2534{
2535 struct hns3_nic_priv *priv = cb_priv;
2536
2537 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2538 return -EOPNOTSUPP;
2539
2540 switch (type) {
2541 case TC_SETUP_CLSFLOWER:
2542 return hns3_setup_tc_cls_flower(priv, type_data);
2543 default:
2544 return -EOPNOTSUPP;
2545 }
2546}
2547
2548static LIST_HEAD(hns3_block_cb_list);
2549
2572ac53 2550static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 2551 void *type_data)
76ad4f0e 2552{
0205ec04
JS		 2553 struct hns3_nic_priv *priv = netdev_priv(dev);
2554 int ret;
2555
2556 switch (type) {
2557 case TC_SETUP_QDISC_MQPRIO:
2558 ret = hns3_setup_tc(dev, type_data);
2559 break;
2560 case TC_SETUP_BLOCK:
2561 ret = flow_block_cb_setup_simple(type_data,
2562 &hns3_block_cb_list,
2563 hns3_setup_tc_block_cb,
2564 priv, priv, true);
2565 break;
2566 default:
38cf0426 2567 return -EOPNOTSUPP;
0205ec04 2568 }
76ad4f0e 2569
0205ec04 2570 return ret;
76ad4f0e
S		 2571}
2572
2573static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2574 __be16 proto, u16 vid)
2575{
9780cb97 2576 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2577 int ret = -EIO;
2578
2579 if (h->ae_algo->ops->set_vlan_filter)
2580 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2581
2582 return ret;
2583}
2584
2585static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2586 __be16 proto, u16 vid)
2587{
9780cb97 2588 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2589 int ret = -EIO;
2590
2591 if (h->ae_algo->ops->set_vlan_filter)
2592 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2593
7fa6be4f 2594 return ret;
681ec399
YL		 2595}
2596
76ad4f0e
S		 2597static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2598 u8 qos, __be16 vlan_proto)
2599{
9780cb97 2600 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 2601 int ret = -EIO;
2602
1c822948 2603 netif_dbg(h, drv, netdev,
39edaf24
GL		 2604 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2605 vf, vlan, qos, ntohs(vlan_proto));
1c822948 2606
76ad4f0e
S		 2607 if (h->ae_algo->ops->set_vf_vlan_filter)
2608 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
9b2f3477 2609 qos, vlan_proto);
76ad4f0e
S		 2610
2611 return ret;
2612}
2613
22044f95
JS		 2614static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2615{
2616 struct hnae3_handle *handle = hns3_get_handle(netdev);
2617
2618 if (hns3_nic_resetting(netdev))
2619 return -EBUSY;
2620
2621 if (!handle->ae_algo->ops->set_vf_spoofchk)
2622 return -EOPNOTSUPP;
2623
2624 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2625}
2626
e196ec75
JS		 2627static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2628{
2629 struct hnae3_handle *handle = hns3_get_handle(netdev);
2630
2631 if (!handle->ae_algo->ops->set_vf_trust)
2632 return -EOPNOTSUPP;
2633
2634 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2635}
2636
a8e8b7ff
S		 2637static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2638{
9780cb97 2639 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 2640 int ret;
2641
6ff7ed80
HT		 2642 if (hns3_nic_resetting(netdev))
2643 return -EBUSY;
2644
a8e8b7ff
S		 2645 if (!h->ae_algo->ops->set_mtu)
2646 return -EOPNOTSUPP;
2647
1c822948
YL		 2648 netif_dbg(h, drv, netdev,
2649 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2650
a8e8b7ff 2651 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 2652 if (ret)
a8e8b7ff
S		 2653 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2654 ret);
93d8daf4
YL		 2655 else
2656 netdev->mtu = new_mtu;
5bad95a1 2657
a8e8b7ff
S		 2658 return ret;
2659}
2660
f8fa222c
L		 2661static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
2662{
2663 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 2664 struct hnae3_handle *h = hns3_get_handle(ndev);
0bfdf286 2665 struct hns3_enet_ring *tx_ring;
e511c97d 2666 struct napi_struct *napi;
f8fa222c
L		 2667 int timeout_queue = 0;
2668 int hw_head, hw_tail;
e511c97d
JS		 2669 int fbd_num, fbd_oft;
2670 int ebd_num, ebd_oft;
2671 int bd_num, bd_err;
2672 int ring_en, tc;
f8fa222c
L		 2673 int i;
2674
2675 /* Find the stopped queue the same way the stack does */
fa6c4084 2676 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 2677 struct netdev_queue *q;
2678 unsigned long trans_start;
2679
2680 q = netdev_get_tx_queue(ndev, i);
2681 trans_start = q->trans_start;
2682 if (netif_xmit_stopped(q) &&
2683 time_after(jiffies,
2684 (trans_start + ndev->watchdog_timeo))) {
2685 timeout_queue = i;
647522a5
YL		 2686 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2687 q->state,
2688 jiffies_to_msecs(jiffies - trans_start));
f8fa222c
L		 2689 break;
2690 }
2691 }
2692
2693 if (i == ndev->num_tx_queues) {
2694 netdev_info(ndev,
2695 "no netdev TX timeout queue found, timeout count: %llu\n",
2696 priv->tx_timeout_count);
2697 return false;
2698 }
2699
beab694a
JS		 2700 priv->tx_timeout_count++;
2701
5f06b903 2702 tx_ring = &priv->ring[timeout_queue];
e511c97d
JS		 2703 napi = &tx_ring->tqp_vector->napi;
2704
2705 netdev_info(ndev,
2706 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2707 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2708 tx_ring->next_to_clean, napi->state);
2709
2710 netdev_info(ndev,
20d06ca2 2711 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
e511c97d 2712 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
20d06ca2 2713 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
e511c97d
JS		 2714
2715 netdev_info(ndev,
f6061a05
YL		 2716 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2717 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
e511c97d
JS		 2718 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2719
2720 /* When mac received many pause frames continuous, it's unable to send
2721 * packets, which may cause tx timeout
2722 */
615466ce
YM		 2723 if (h->ae_algo->ops->get_mac_stats) {
2724 struct hns3_mac_stats mac_stats;
e511c97d 2725
615466ce 2726 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
e511c97d 2727 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
615466ce 2728 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
e511c97d 2729 }
f8fa222c
L		 2730
2731 hw_head = readl_relaxed(tx_ring->tqp->io_base +
2732 HNS3_RING_TX_RING_HEAD_REG);
2733 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
2734 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS		 2735 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
2736 HNS3_RING_TX_RING_FBDNUM_REG);
2737 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
2738 HNS3_RING_TX_RING_OFFSET_REG);
2739 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
2740 HNS3_RING_TX_RING_EBDNUM_REG);
2741 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
2742 HNS3_RING_TX_RING_EBD_OFFSET_REG);
2743 bd_num = readl_relaxed(tx_ring->tqp->io_base +
2744 HNS3_RING_TX_RING_BD_NUM_REG);
2745 bd_err = readl_relaxed(tx_ring->tqp->io_base +
2746 HNS3_RING_TX_RING_BD_ERR_REG);
2747 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
2748 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
2749
f8fa222c 2750 netdev_info(ndev,
e511c97d
JS		 2751 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2752 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 2753 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS		 2754 netdev_info(ndev,
2755 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2756 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L		 2757
2758 return true;
2759}
2760
0290bd29 2761static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
f8fa222c
L		 2762{
2763 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 2764 struct hnae3_handle *h = priv->ae_handle;
2765
2766 if (!hns3_get_tx_timeo_queue_info(ndev))
2767 return;
2768
0742ed7c
HT		 2769 /* request the reset, and let the hclge to determine
2770 * which reset level should be done
2771 */
f8fa222c 2772 if (h->ae_algo->ops->reset_event)
6ae4e733 2773 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 2774}
2775
d93ed94f
JS		 2776#ifdef CONFIG_RFS_ACCEL
2777static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2778 u16 rxq_index, u32 flow_id)
2779{
2780 struct hnae3_handle *h = hns3_get_handle(dev);
2781 struct flow_keys fkeys;
2782
2783 if (!h->ae_algo->ops->add_arfs_entry)
2784 return -EOPNOTSUPP;
2785
2786 if (skb->encapsulation)
2787 return -EPROTONOSUPPORT;
2788
2789 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2790 return -EPROTONOSUPPORT;
2791
2792 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2793 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2794 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2795 fkeys.basic.ip_proto != IPPROTO_UDP))
2796 return -EPROTONOSUPPORT;
2797
2798 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2799}
2800#endif
2801
6430f744
YM		 2802static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2803 struct ifla_vf_info *ivf)
2804{
2805 struct hnae3_handle *h = hns3_get_handle(ndev);
2806
2807 if (!h->ae_algo->ops->get_vf_config)
2808 return -EOPNOTSUPP;
2809
2810 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2811}
2812
2813static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2814 int link_state)
2815{
2816 struct hnae3_handle *h = hns3_get_handle(ndev);
2817
2818 if (!h->ae_algo->ops->set_vf_link_state)
2819 return -EOPNOTSUPP;
2820
2821 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2822}
2823
ee9e4424
YL		 2824static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2825 int min_tx_rate, int max_tx_rate)
2826{
2827 struct hnae3_handle *h = hns3_get_handle(ndev);
2828
2829 if (!h->ae_algo->ops->set_vf_rate)
2830 return -EOPNOTSUPP;
2831
2832 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
2833 false);
2834}
2835
8e6de441
HT		 2836static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
2837{
2838 struct hnae3_handle *h = hns3_get_handle(netdev);
2839
2840 if (!h->ae_algo->ops->set_vf_mac)
2841 return -EOPNOTSUPP;
2842
2843 if (is_multicast_ether_addr(mac)) {
2844 netdev_err(netdev,
2845 "Invalid MAC:%pM specified. Could not set MAC\n",
2846 mac);
2847 return -EINVAL;
2848 }
2849
2850 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
2851}
2852
76ad4f0e
S		 2853static const struct net_device_ops hns3_nic_netdev_ops = {
2854 .ndo_open = hns3_nic_net_open,
2855 .ndo_stop = hns3_nic_net_stop,
2856 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 2857 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 2858 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
a7605370 2859 .ndo_eth_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 2860 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e 2861 .ndo_set_features = hns3_nic_set_features,
2a7556bb 2862 .ndo_features_check = hns3_features_check,
76ad4f0e
S		 2863 .ndo_get_stats64 = hns3_nic_get_stats64,
2864 .ndo_setup_tc = hns3_nic_setup_tc,
2865 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 2866 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
2867 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
2868 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
22044f95 2869 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
e196ec75 2870 .ndo_set_vf_trust = hns3_set_vf_trust,
d93ed94f
JS		 2871#ifdef CONFIG_RFS_ACCEL
2872 .ndo_rx_flow_steer = hns3_rx_flow_steer,
2873#endif
6430f744
YM		 2874 .ndo_get_vf_config = hns3_nic_get_vf_config,
2875 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
ee9e4424 2876 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
8e6de441 2877 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
76ad4f0e
S		 2878};
2879
97afd47b 2880bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL		 2881{
2882 u32 dev_id = pdev->device;
2883
2884 switch (dev_id) {
2885 case HNAE3_DEV_ID_GE:
2886 case HNAE3_DEV_ID_25GE:
2887 case HNAE3_DEV_ID_25GE_RDMA:
2888 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2889 case HNAE3_DEV_ID_50GE_RDMA:
2890 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2891 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
ae6f010c 2892 case HNAE3_DEV_ID_200G_RDMA:
2312e050 2893 return true;
c155e22b
GH		 2894 case HNAE3_DEV_ID_VF:
2895 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
2312e050
FL		 2896 return false;
2897 default:
adcf738b 2898 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2312e050
FL		 2899 dev_id);
2900 }
2901
2902 return false;
2903}
2904
2312e050
FL		 2905static void hns3_disable_sriov(struct pci_dev *pdev)
2906{
2907 /* If our VFs are assigned we cannot shut down SR-IOV
2908 * without causing issues, so just leave the hardware
2909 * available but disabled
2910 */
2911 if (pci_vfs_assigned(pdev)) {
2912 dev_warn(&pdev->dev,
2913 "disabling driver while VFs are assigned\n");
2914 return;
2915 }
2916
2917 pci_disable_sriov(pdev);
2918}
2919
76ad4f0e
S		 2920/* hns3_probe - Device initialization routine
2921 * @pdev: PCI device information struct
2922 * @ent: entry in hns3_pci_tbl
2923 *
2924 * hns3_probe initializes a PF identified by a pci_dev structure.
2925 * The OS initialization, configuring of the PF private structure,
2926 * and a hardware reset occur.
2927 *
2928 * Returns 0 on success, negative on failure
2929 */
2930static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2931{
2932 struct hnae3_ae_dev *ae_dev;
2933 int ret;
2934
9b2f3477 2935 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
60df7e91
HT		 2936 if (!ae_dev)
2937 return -ENOMEM;
76ad4f0e
S		 2938
2939 ae_dev->pdev = pdev;
e92a0843 2940 ae_dev->flag = ent->driver_data;
76ad4f0e
S		 2941 pci_set_drvdata(pdev, ae_dev);
2942
74354140 2943 ret = hnae3_register_ae_dev(ae_dev);
674a1357 2944 if (ret)
74354140 2945 pci_set_drvdata(pdev, NULL);
2312e050 2946
74354140 2947 return ret;
76ad4f0e
S		 2948}
2949
2950/* hns3_remove - Device removal routine
2951 * @pdev: PCI device information struct
2952 */
2953static void hns3_remove(struct pci_dev *pdev)
2954{
2955 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2956
2312e050
FL		 2957 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2958 hns3_disable_sriov(pdev);
2959
76ad4f0e 2960 hnae3_unregister_ae_dev(ae_dev);
ac864c23 2961 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 2962}
2963
fa8d82e8
PL		 2964/**
2965 * hns3_pci_sriov_configure
2966 * @pdev: pointer to a pci_dev structure
2967 * @num_vfs: number of VFs to allocate
2968 *
2969 * Enable or change the number of VFs. Called when the user updates the number
2970 * of VFs in sysfs.
2971 **/
743e1a84 2972static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 2973{
2974 int ret;
2975
2976 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2977 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2978 return -EINVAL;
2979 }
2980
2981 if (num_vfs) {
2982 ret = pci_enable_sriov(pdev, num_vfs);
2983 if (ret)
2984 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 2985 else
2986 return num_vfs;
fa8d82e8
PL		 2987 } else if (!pci_vfs_assigned(pdev)) {
2988 pci_disable_sriov(pdev);
2989 } else {
2990 dev_warn(&pdev->dev,
2991 "Unable to free VFs because some are assigned to VMs.\n");
2992 }
2993
2994 return 0;
2995}
2996
ce2c1d2e
YL		 2997static void hns3_shutdown(struct pci_dev *pdev)
2998{
2999 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3000
3001 hnae3_unregister_ae_dev(ae_dev);
ce2c1d2e
YL		 3002 pci_set_drvdata(pdev, NULL);
3003
3004 if (system_state == SYSTEM_POWER_OFF)
3005 pci_set_power_state(pdev, PCI_D3hot);
3006}
3007
715c58e9
JZ		 3008static int __maybe_unused hns3_suspend(struct device *dev)
3009{
3010 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3011
d0494135 3012 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
715c58e9 3013 dev_info(dev, "Begin to suspend.\n");
d0494135 3014 if (ae_dev->ops && ae_dev->ops->reset_prepare)
715c58e9
JZ		 3015 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3016 }
3017
3018 return 0;
3019}
3020
3021static int __maybe_unused hns3_resume(struct device *dev)
3022{
3023 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3024
d0494135 3025 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
715c58e9 3026 dev_info(dev, "Begin to resume.\n");
d0494135 3027 if (ae_dev->ops && ae_dev->ops->reset_done)
715c58e9
JZ		 3028 ae_dev->ops->reset_done(ae_dev);
3029 }
3030
3031 return 0;
3032}
3033
5a9f0eac
SJ		 3034static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3035 pci_channel_state_t state)
3036{
3037 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3038 pci_ers_result_t ret;
3039
c5aaf176 3040 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
5a9f0eac
SJ		 3041
3042 if (state == pci_channel_io_perm_failure)
3043 return PCI_ERS_RESULT_DISCONNECT;
3044
661262bc 3045 if (!ae_dev || !ae_dev->ops) {
5a9f0eac 3046 dev_err(&pdev->dev,
661262bc 3047 "Can't recover - error happened before device initialized\n");
5a9f0eac
SJ		 3048 return PCI_ERS_RESULT_NONE;
3049 }
3050
381c356e
SJ		 3051 if (ae_dev->ops->handle_hw_ras_error)
3052 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 3053 else
3054 return PCI_ERS_RESULT_NONE;
3055
3056 return ret;
3057}
3058
6ae4e733
SJ		 3059static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3060{
3061 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
ad9bf545 3062 const struct hnae3_ae_ops *ops;
123297b7 3063 enum hnae3_reset_type reset_type;
6ae4e733
SJ		 3064 struct device *dev = &pdev->dev;
3065
661262bc
WL		 3066 if (!ae_dev || !ae_dev->ops)
3067 return PCI_ERS_RESULT_NONE;
3068
ad9bf545 3069 ops = ae_dev->ops;
6ae4e733 3070 /* request the reset */
fa17c708
GH		 3071 if (ops->reset_event && ops->get_reset_level &&
3072 ops->set_default_reset_request) {
9d5e67d1 3073 if (ae_dev->hw_err_reset_req) {
123297b7
SJ		 3074 reset_type = ops->get_reset_level(ae_dev,
3075 &ae_dev->hw_err_reset_req);
3076 ops->set_default_reset_request(ae_dev, reset_type);
3077 dev_info(dev, "requesting reset due to PCI error\n");
3078 ops->reset_event(pdev, NULL);
3079 }
69b51bbb 3080
6ae4e733
SJ		 3081 return PCI_ERS_RESULT_RECOVERED;
3082 }
3083
3084 return PCI_ERS_RESULT_DISCONNECT;
3085}
3086
6b9a97ee
HT		 3087static void hns3_reset_prepare(struct pci_dev *pdev)
3088{
3089 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3090
8de91e92 3091 dev_info(&pdev->dev, "FLR prepare\n");
bb1890d5
JZ		 3092 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3093 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
6b9a97ee
HT		 3094}
3095
3096static void hns3_reset_done(struct pci_dev *pdev)
3097{
3098 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3099
8de91e92 3100 dev_info(&pdev->dev, "FLR done\n");
bb1890d5
JZ		 3101 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3102 ae_dev->ops->reset_done(ae_dev);
6b9a97ee
HT		 3103}
3104
5a9f0eac
SJ		 3105static const struct pci_error_handlers hns3_err_handler = {
3106 .error_detected = hns3_error_detected,
6ae4e733 3107 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 3108 .reset_prepare = hns3_reset_prepare,
3109 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 3110};
3111
715c58e9
JZ		 3112static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3113
76ad4f0e
S		 3114static struct pci_driver hns3_driver = {
3115 .name = hns3_driver_name,
3116 .id_table = hns3_pci_tbl,
3117 .probe = hns3_probe,
3118 .remove = hns3_remove,
ce2c1d2e 3119 .shutdown = hns3_shutdown,
715c58e9 3120 .driver.pm = &hns3_pm_ops,
fa8d82e8 3121 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 3122 .err_handler = &hns3_err_handler,
76ad4f0e
S		 3123};
3124
3125/* set default feature to hns3 */
3126static void hns3_set_default_feature(struct net_device *netdev)
3127{
3e85af6a
PL		 3128 struct hnae3_handle *h = hns3_get_handle(netdev);
3129 struct pci_dev *pdev = h->pdev;
295ba232 3130 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3e85af6a 3131
76ad4f0e
S		 3132 netdev->priv_flags |= IFF_UNICAST_FLT;
3133
76ad4f0e
S		 3134 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
3135
66d52f3b 3136 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 3137 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 3138 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3139 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3140 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
57e72c12 3141 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
76ad4f0e 3142
295ba232 3143 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
5c9f6b39 3144 netdev->features |= NETIF_F_GRO_HW;
c17852a8 3145
dc9b5ce0 3146 if (!(h->flags & HNAE3_SUPPORT_VF))
c17852a8 3147 netdev->features |= NETIF_F_NTUPLE;
c17852a8 3148 }
0692cfe9 3149
dc9b5ce0 3150 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
0692cfe9 3151 netdev->features |= NETIF_F_GSO_UDP_L4;
66d52f3b 3152
dc9b5ce0 3153 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
66d52f3b 3154 netdev->features |= NETIF_F_HW_CSUM;
dc9b5ce0 3155 else
66d52f3b 3156 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3e281621 3157
dc9b5ce0 3158 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3e281621 3159 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
0205ec04 3160
dc9b5ce0 3161 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
0205ec04 3162 netdev->features |= NETIF_F_HW_TC;
2ba30662 3163
dc9b5ce0
JS		 3164 netdev->hw_features |= netdev->features;
3165 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3166 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3167
3168 netdev->vlan_features |= netdev->features &
3169 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3170 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3171 NETIF_F_HW_TC);
3172
3173 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
76ad4f0e
S		 3174}
3175
3176static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3177 struct hns3_desc_cb *cb)
3178{
dbba6da0 3179 unsigned int order = hns3_page_order(ring);
76ad4f0e
S		 3180 struct page *p;
3181
93188e96
YL		 3182 if (ring->page_pool) {
3183 p = page_pool_dev_alloc_frag(ring->page_pool,
3184 &cb->page_offset,
3185 hns3_buf_size(ring));
3186 if (unlikely(!p))
3187 return -ENOMEM;
3188
3189 cb->priv = p;
3190 cb->buf = page_address(p);
3191 cb->dma = page_pool_get_dma_addr(p);
3192 cb->type = DESC_TYPE_PP_FRAG;
3193 cb->reuse_flag = 0;
3194 return 0;
3195 }
3196
76ad4f0e
S		 3197 p = dev_alloc_pages(order);
3198 if (!p)
3199 return -ENOMEM;
3200
3201 cb->priv = p;
3202 cb->page_offset = 0;
3203 cb->reuse_flag = 0;
3204 cb->buf = page_address(p);
dbba6da0 3205 cb->length = hns3_page_size(ring);
76ad4f0e 3206 cb->type = DESC_TYPE_PAGE;
aeda9bf8
YL		 3207 page_ref_add(p, USHRT_MAX - 1);
3208 cb->pagecnt_bias = USHRT_MAX;
76ad4f0e 3209
76ad4f0e
S		 3210 return 0;
3211}
3212
3213static void hns3_free_buffer(struct hns3_enet_ring *ring,
619ae331 3214 struct hns3_desc_cb *cb, int budget)
76ad4f0e 3215{
907676b1 3216 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
7459775e 3217 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
619ae331 3218 napi_consume_skb(cb->priv, budget);
93188e96
YL		 3219 else if (!HNAE3_IS_TX_RING(ring)) {
3220 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3221 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3222 else if (cb->type & DESC_TYPE_PP_FRAG)
3223 page_pool_put_full_page(ring->page_pool, cb->priv,
3224 false);
3225 }
76ad4f0e
S		 3226 memset(cb, 0, sizeof(*cb));
3227}
3228
3229static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3230{
3231 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3232 cb->length, ring_to_dma_dir(ring));
3233
2211f4e1 3234 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 3235 return -EIO;
3236
3237 return 0;
3238}
3239
3240static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3241 struct hns3_desc_cb *cb)
3242{
26f1ccdf 3243 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
76ad4f0e
S		 3244 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3245 ring_to_dma_dir(ring));
907676b1 3246 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
76ad4f0e
S		 3247 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3248 ring_to_dma_dir(ring));
7459775e
YL		 3249 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3250 DESC_TYPE_SGL_SKB))
907676b1 3251 hns3_tx_spare_reclaim_cb(ring, cb);
76ad4f0e
S		 3252}
3253
3254static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3255{
3256 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3257 ring->desc[i].addr = 0;
9f9f0f19 3258 ring->desc_cb[i].refill = 0;
76ad4f0e
S		 3259}
3260
619ae331
YL		 3261static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3262 int budget)
76ad4f0e
S		 3263{
3264 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3265
3266 if (!ring->desc_cb[i].dma)
3267 return;
3268
3269 hns3_buffer_detach(ring, i);
619ae331 3270 hns3_free_buffer(ring, cb, budget);
76ad4f0e
S		 3271}
3272
3273static void hns3_free_buffers(struct hns3_enet_ring *ring)
3274{
3275 int i;
3276
3277 for (i = 0; i < ring->desc_num; i++)
619ae331 3278 hns3_free_buffer_detach(ring, i, 0);
76ad4f0e
S		 3279}
3280
3281/* free desc along with its attached buffer */
3282static void hns3_free_desc(struct hns3_enet_ring *ring)
3283{
024cc792
HT		 3284 int size = ring->desc_num * sizeof(ring->desc[0]);
3285
76ad4f0e
S		 3286 hns3_free_buffers(ring);
3287
024cc792
HT		 3288 if (ring->desc) {
3289 dma_free_coherent(ring_to_dev(ring), size,
3290 ring->desc, ring->desc_dma_addr);
3291 ring->desc = NULL;
3292 }
76ad4f0e
S		 3293}
3294
3295static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3296{
3297 int size = ring->desc_num * sizeof(ring->desc[0]);
3298
750afb08
LC		 3299 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3300 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 3301 if (!ring->desc)
3302 return -ENOMEM;
3303
76ad4f0e
S		 3304 return 0;
3305}
3306
4d2cad32 3307static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
76ad4f0e
S		 3308 struct hns3_desc_cb *cb)
3309{
3310 int ret;
3311
3312 ret = hns3_alloc_buffer(ring, cb);
93188e96 3313 if (ret || ring->page_pool)
76ad4f0e
S		 3314 goto out;
3315
3316 ret = hns3_map_buffer(ring, cb);
3317 if (ret)
3318 goto out_with_buf;
3319
3320 return 0;
3321
3322out_with_buf:
619ae331 3323 hns3_free_buffer(ring, cb, 0);
76ad4f0e
S		 3324out:
3325 return ret;
3326}
3327
4d2cad32 3328static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
76ad4f0e 3329{
4d2cad32 3330 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 3331
3332 if (ret)
3333 return ret;
3334
93188e96
YL		 3335 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3336 ring->desc_cb[i].page_offset);
9f9f0f19 3337 ring->desc_cb[i].refill = 1;
76ad4f0e
S		 3338
3339 return 0;
3340}
3341
3342/* Allocate memory for raw pkg, and map with dma */
3343static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3344{
3345 int i, j, ret;
3346
3347 for (i = 0; i < ring->desc_num; i++) {
4d2cad32 3348 ret = hns3_alloc_and_attach_buffer(ring, i);
76ad4f0e
S		 3349 if (ret)
3350 goto out_buffer_fail;
3351 }
3352
3353 return 0;
3354
3355out_buffer_fail:
3356 for (j = i - 1; j >= 0; j--)
619ae331 3357 hns3_free_buffer_detach(ring, j, 0);
76ad4f0e
S		 3358 return ret;
3359}
3360
9b2f3477 3361/* detach a in-used buffer and replace with a reserved one */
76ad4f0e
S		 3362static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3363 struct hns3_desc_cb *res_cb)
3364{
b9077428 3365 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e 3366 ring->desc_cb[i] = *res_cb;
9f9f0f19 3367 ring->desc_cb[i].refill = 1;
93188e96
YL		 3368 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3369 ring->desc_cb[i].page_offset);
7d0b130c 3370 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 3371}
3372
3373static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3374{
3375 ring->desc_cb[i].reuse_flag = 0;
9f9f0f19 3376 ring->desc_cb[i].refill = 1;
9b2f3477
WL		 3377 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3378 ring->desc_cb[i].page_offset);
7d0b130c 3379 ring->desc[i].rx.bd_base_info = 0;
c2a2e127
BS		 3380
3381 dma_sync_single_for_device(ring_to_dev(ring),
3382 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3383 hns3_buf_size(ring),
3384 DMA_FROM_DEVICE);
76ad4f0e
S		 3385}
3386
20d06ca2 3387static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
619ae331 3388 int *bytes, int *pkts, int budget)
76ad4f0e 3389{
20d06ca2
YL		 3390 /* pair with ring->last_to_use update in hns3_tx_doorbell(),
3391 * smp_store_release() is not used in hns3_tx_doorbell() because
3392 * the doorbell operation already have the needed barrier operation.
3393 */
3394 int ltu = smp_load_acquire(&ring->last_to_use);
26cda2f1
YL		 3395 int ntc = ring->next_to_clean;
3396 struct hns3_desc_cb *desc_cb;
20d06ca2
YL		 3397 bool reclaimed = false;
3398 struct hns3_desc *desc;
3399
3400 while (ltu != ntc) {
3401 desc = &ring->desc[ntc];
3402
3403 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3404 BIT(HNS3_TXD_VLD_B))
3405 break;
76ad4f0e 3406
ce74370c 3407 desc_cb = &ring->desc_cb[ntc];
811c0830 3408
907676b1 3409 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
7459775e
YL		 3410 DESC_TYPE_BOUNCE_HEAD |
3411 DESC_TYPE_SGL_SKB)) {
811c0830
YL		 3412 (*pkts)++;
3413 (*bytes) += desc_cb->send_bytes;
3414 }
3415
ce74370c 3416 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
619ae331 3417 hns3_free_buffer_detach(ring, ntc, budget);
76ad4f0e 3418
ce74370c
YL		 3419 if (++ntc == ring->desc_num)
3420 ntc = 0;
3421
3422 /* Issue prefetch for next Tx descriptor */
3423 prefetch(&ring->desc_cb[ntc]);
20d06ca2 3424 reclaimed = true;
ce74370c 3425 }
26cda2f1 3426
20d06ca2
YL		 3427 if (unlikely(!reclaimed))
3428 return false;
3429
26cda2f1
YL		 3430 /* This smp_store_release() pairs with smp_load_acquire() in
3431 * ring_space called by hns3_nic_net_xmit.
3432 */
3433 smp_store_release(&ring->next_to_clean, ntc);
907676b1
YL		 3434
3435 hns3_tx_spare_update(ring);
3436
20d06ca2 3437 return true;
76ad4f0e
S		 3438}
3439
619ae331 3440void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
76ad4f0e 3441{
c8711956 3442 struct net_device *netdev = ring_to_netdev(ring);
7a810110 3443 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 3444 struct netdev_queue *dev_queue;
3445 int bytes, pkts;
76ad4f0e
S		 3446
3447 bytes = 0;
3448 pkts = 0;
20d06ca2 3449
619ae331 3450 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
20d06ca2 3451 return;
76ad4f0e
S		 3452
3453 ring->tqp_vector->tx_group.total_bytes += bytes;
3454 ring->tqp_vector->tx_group.total_packets += pkts;
3455
3456 u64_stats_update_begin(&ring->syncp);
3457 ring->stats.tx_bytes += bytes;
3458 ring->stats.tx_pkts += pkts;
3459 u64_stats_update_end(&ring->syncp);
3460
3461 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3462 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3463
2a597eff 3464 if (unlikely(netif_carrier_ok(netdev) &&
8ae10cfb 3465 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
76ad4f0e
S		 3466 /* Make sure that anybody stopping the queue after this
3467 * sees the new next_to_clean.
3468 */
3469 smp_mb();
7a810110
JS		 3470 if (netif_tx_queue_stopped(dev_queue) &&
3471 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 3472 netif_tx_wake_queue(dev_queue);
3473 ring->stats.restart_queue++;
3474 }
3475 }
76ad4f0e
S		 3476}
3477
3478static int hns3_desc_unused(struct hns3_enet_ring *ring)
3479{
3480 int ntc = ring->next_to_clean;
3481 int ntu = ring->next_to_use;
3482
9f9f0f19
YL		 3483 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3484 return ring->desc_num;
3485
76ad4f0e
S		 3486 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3487}
3488
68752b24
YL		 3489/* Return true if there is any allocation failure */
3490static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
9b2f3477 3491 int cleand_count)
76ad4f0e
S		 3492{
3493 struct hns3_desc_cb *desc_cb;
3494 struct hns3_desc_cb res_cbs;
3495 int i, ret;
3496
3497 for (i = 0; i < cleand_count; i++) {
3498 desc_cb = &ring->desc_cb[ring->next_to_use];
3499 if (desc_cb->reuse_flag) {
3500 u64_stats_update_begin(&ring->syncp);
3501 ring->stats.reuse_pg_cnt++;
3502 u64_stats_update_end(&ring->syncp);
3503
3504 hns3_reuse_buffer(ring, ring->next_to_use);
3505 } else {
4d2cad32 3506 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
76ad4f0e
S		 3507 if (ret) {
3508 u64_stats_update_begin(&ring->syncp);
3509 ring->stats.sw_err_cnt++;
3510 u64_stats_update_end(&ring->syncp);
3511
c8711956 3512 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5
YL		 3513 "alloc rx buffer failed: %d\n",
3514 ret);
68752b24
YL		 3515
3516 writel(i, ring->tqp->io_base +
3517 HNS3_RING_RX_RING_HEAD_REG);
3518 return true;
76ad4f0e
S		 3519 }
3520 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL		 3521
3522 u64_stats_update_begin(&ring->syncp);
3523 ring->stats.non_reuse_pg++;
3524 u64_stats_update_end(&ring->syncp);
76ad4f0e
S		 3525 }
3526
3527 ring_ptr_move_fw(ring, next_to_use);
3528 }
3529
48ee56fd 3530 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
68752b24 3531 return false;
76ad4f0e
S		 3532}
3533
aeda9bf8
YL		 3534static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3535{
fa7711b8 3536 return page_count(cb->priv) == cb->pagecnt_bias;
aeda9bf8
YL		 3537}
3538
76ad4f0e
S		 3539static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3540 struct hns3_enet_ring *ring, int pull_len,
3541 struct hns3_desc_cb *desc_cb)
3542{
389ca146 3543 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
fa7711b8 3544 u32 frag_offset = desc_cb->page_offset + pull_len;
389ca146 3545 int size = le16_to_cpu(desc->rx.size);
dbba6da0 3546 u32 truesize = hns3_buf_size(ring);
fa7711b8 3547 u32 frag_size = size - pull_len;
96104500 3548 bool reused;
76ad4f0e 3549
93188e96
YL		 3550 if (ring->page_pool) {
3551 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3552 frag_size, truesize);
3553 return;
3554 }
3555
fa7711b8
YL		 3556 /* Avoid re-using remote or pfmem page */
3557 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3558 goto out;
76ad4f0e 3559
96104500
YL		 3560 reused = hns3_can_reuse_page(desc_cb);
3561
3562 /* Rx page can be reused when:
3563 * 1. Rx page is only owned by the driver when page_offset
3564 * is zero, which means 0 @ truesize will be used by
3565 * stack after skb_add_rx_frag() is called, and the rest
3566 * of rx page can be reused by driver.
3567 * Or
3568 * 2. Rx page is only owned by the driver when page_offset
3569 * is non-zero, which means page_offset @ truesize will
3570 * be used by stack after skb_add_rx_frag() is called,
3571 * and 0 @ truesize can be reused by driver.
389ca146 3572 */
96104500
YL		 3573 if ((!desc_cb->page_offset && reused) ||
3574 ((desc_cb->page_offset + truesize + truesize) <=
3575 hns3_page_size(ring) && desc_cb->page_offset)) {
fa7711b8 3576 desc_cb->page_offset += truesize;
389ca146 3577 desc_cb->reuse_flag = 1;
96104500
YL		 3578 } else if (desc_cb->page_offset && reused) {
3579 desc_cb->page_offset = 0;
3580 desc_cb->reuse_flag = 1;
99f6b5fb
YL		 3581 } else if (frag_size <= ring->rx_copybreak) {
3582 void *frag = napi_alloc_frag(frag_size);
3583
3584 if (unlikely(!frag)) {
3585 u64_stats_update_begin(&ring->syncp);
3586 ring->stats.frag_alloc_err++;
3587 u64_stats_update_end(&ring->syncp);
3588
3589 hns3_rl_err(ring_to_netdev(ring),
3590 "failed to allocate rx frag\n");
3591 goto out;
3592 }
3593
3594 desc_cb->reuse_flag = 1;
3595 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3596 skb_add_rx_frag(skb, i, virt_to_page(frag),
3597 offset_in_page(frag), frag_size, frag_size);
3598
3599 u64_stats_update_begin(&ring->syncp);
3600 ring->stats.frag_alloc++;
3601 u64_stats_update_end(&ring->syncp);
3602 return;
aeda9bf8
YL		 3603 }
3604
fa7711b8
YL		 3605out:
3606 desc_cb->pagecnt_bias--;
3607
aeda9bf8
YL		 3608 if (unlikely(!desc_cb->pagecnt_bias)) {
3609 page_ref_add(desc_cb->priv, USHRT_MAX);
3610 desc_cb->pagecnt_bias = USHRT_MAX;
76ad4f0e 3611 }
fa7711b8
YL		 3612
3613 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3614 frag_size, truesize);
3615
3616 if (unlikely(!desc_cb->reuse_flag))
3617 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
76ad4f0e
S		 3618}
3619
e2ee1c5a 3620static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
d474d88f
YL		 3621{
3622 __be16 type = skb->protocol;
3623 struct tcphdr *th;
3624 int depth = 0;
3625
e2ee1c5a 3626 while (eth_type_vlan(type)) {
d474d88f
YL		 3627 struct vlan_hdr *vh;
3628
3629 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3630 return -EFAULT;
3631
3632 vh = (struct vlan_hdr *)(skb->data + depth);
3633 type = vh->h_vlan_encapsulated_proto;
3634 depth += VLAN_HLEN;
3635 }
3636
e2ee1c5a
YL		 3637 skb_set_network_header(skb, depth);
3638
d474d88f 3639 if (type == htons(ETH_P_IP)) {
e2ee1c5a
YL		 3640 const struct iphdr *iph = ip_hdr(skb);
3641
d474d88f 3642 depth += sizeof(struct iphdr);
e2ee1c5a
YL		 3643 skb_set_transport_header(skb, depth);
3644 th = tcp_hdr(skb);
3645 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3646 iph->daddr, 0);
d474d88f 3647 } else if (type == htons(ETH_P_IPV6)) {
e2ee1c5a
YL		 3648 const struct ipv6hdr *iph = ipv6_hdr(skb);
3649
d474d88f 3650 depth += sizeof(struct ipv6hdr);
e2ee1c5a
YL		 3651 skb_set_transport_header(skb, depth);
3652 th = tcp_hdr(skb);
3653 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3654 &iph->daddr, 0);
d474d88f 3655 } else {
b20d7fe5
YL		 3656 hns3_rl_err(skb->dev,
3657 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3658 be16_to_cpu(type), depth);
d474d88f
YL		 3659 return -EFAULT;
3660 }
3661
d474d88f
YL		 3662 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3663 if (th->cwr)
3664 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3665
e2ee1c5a
YL		 3666 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3667 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
d474d88f 3668
e2ee1c5a
YL		 3669 skb->csum_start = (unsigned char *)th - skb->head;
3670 skb->csum_offset = offsetof(struct tcphdr, check);
3671 skb->ip_summed = CHECKSUM_PARTIAL;
698a8954
YL		 3672
3673 trace_hns3_gro(skb);
3674
d474d88f
YL		 3675 return 0;
3676}
3677
1ddc028a
HT		 3678static bool hns3_checksum_complete(struct hns3_enet_ring *ring,
3679 struct sk_buff *skb, u32 ptype, u16 csum)
4b2fe769 3680{
1ddc028a
HT		 3681 if (ptype == HNS3_INVALID_PTYPE ||
3682 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3683 return false;
4b2fe769
HT		 3684
3685 u64_stats_update_begin(&ring->syncp);
3686 ring->stats.csum_complete++;
3687 u64_stats_update_end(&ring->syncp);
3688 skb->ip_summed = CHECKSUM_COMPLETE;
1ddc028a
HT		 3689 skb->csum = csum_unfold((__force __sum16)csum);
3690
3691 return true;
4b2fe769
HT		 3692}
3693
79664077
HT		 3694static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3695 u32 ol_info, u32 ptype)
76ad4f0e 3696{
76ad4f0e 3697 int l3_type, l4_type;
76ad4f0e 3698 int ol4_type;
76ad4f0e 3699
79664077
HT		 3700 if (ptype != HNS3_INVALID_PTYPE) {
3701 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3702 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
76ad4f0e
S		 3703
3704 return;
3705 }
3706
39c38824 3707 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 3708 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 3709 switch (ol4_type) {
3710 case HNS3_OL4_TYPE_MAC_IN_UDP:
3711 case HNS3_OL4_TYPE_NVGRE:
3712 skb->csum_level = 1;
df561f66 3713 fallthrough;
76ad4f0e 3714 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL		 3715 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3716 HNS3_RXD_L3ID_S);
3717 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3718 HNS3_RXD_L4ID_S);
76ad4f0e 3719 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 3720 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3721 l3_type == HNS3_L3_TYPE_IPV6) &&
3722 (l4_type == HNS3_L4_TYPE_UDP ||
3723 l4_type == HNS3_L4_TYPE_TCP ||
3724 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 3725 skb->ip_summed = CHECKSUM_UNNECESSARY;
3726 break;
fa7a4bd5
JS		 3727 default:
3728 break;
76ad4f0e
S		 3729 }
3730}
3731
79664077 3732static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
1ddc028a
HT		 3733 u32 l234info, u32 bd_base_info, u32 ol_info,
3734 u16 csum)
79664077
HT		 3735{
3736 struct net_device *netdev = ring_to_netdev(ring);
3737 struct hns3_nic_priv *priv = netdev_priv(netdev);
3738 u32 ptype = HNS3_INVALID_PTYPE;
3739
3740 skb->ip_summed = CHECKSUM_NONE;
3741
3742 skb_checksum_none_assert(skb);
3743
3744 if (!(netdev->features & NETIF_F_RXCSUM))
3745 return;
3746
3747 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3748 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3749 HNS3_RXD_PTYPE_S);
3750
1ddc028a 3751 if (hns3_checksum_complete(ring, skb, ptype, csum))
79664077 3752 return;
79664077
HT		 3753
3754 /* check if hardware has done checksum */
3755 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
3756 return;
3757
3758 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
3759 BIT(HNS3_RXD_OL3E_B) |
3760 BIT(HNS3_RXD_OL4E_B)))) {
3761 u64_stats_update_begin(&ring->syncp);
3762 ring->stats.l3l4_csum_err++;
3763 u64_stats_update_end(&ring->syncp);
3764
3765 return;
3766 }
3767
3768 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
3769}
3770
d43e5aca
YL		 3771static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
3772{
81ae0e04
PL		 3773 if (skb_has_frag_list(skb))
3774 napi_gro_flush(&ring->tqp_vector->napi, false);
3775
d43e5aca
YL		 3776 napi_gro_receive(&ring->tqp_vector->napi, skb);
3777}
3778
701a6d6a
JS		 3779static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
3780 struct hns3_desc *desc, u32 l234info,
3781 u16 *vlan_tag)
5b5455a9 3782{
44e626f7 3783 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 3784 struct pci_dev *pdev = ring->tqp->handle->pdev;
295ba232 3785 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5b5455a9 3786
295ba232 3787 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
701a6d6a
JS		 3788 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3789 if (!(*vlan_tag & VLAN_VID_MASK))
3790 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 3791
701a6d6a 3792 return (*vlan_tag != 0);
5b5455a9
PL		 3793 }
3794
3795#define HNS3_STRP_OUTER_VLAN 0x1
3796#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 3797#define HNS3_STRP_BOTH 0x3
5b5455a9 3798
44e626f7
JS		 3799 /* Hardware always insert VLAN tag into RX descriptor when
3800 * remove the tag from packet, driver needs to determine
3801 * reporting which tag to stack.
3802 */
e4e87715
PL		 3803 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
3804 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 3805 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS		 3806 if (handle->port_base_vlan_state !=
3807 HNAE3_PORT_BASE_VLAN_DISABLE)
3808 return false;
3809
701a6d6a
JS		 3810 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3811 return true;
5b5455a9 3812 case HNS3_STRP_INNER_VLAN:
44e626f7
JS		 3813 if (handle->port_base_vlan_state !=
3814 HNAE3_PORT_BASE_VLAN_DISABLE)
3815 return false;
3816
701a6d6a 3817 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS		 3818 return true;
3819 case HNS3_STRP_BOTH:
3820 if (handle->port_base_vlan_state ==
3821 HNAE3_PORT_BASE_VLAN_DISABLE)
3822 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
3823 else
3824 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
3825
701a6d6a 3826 return true;
5b5455a9 3827 default:
701a6d6a 3828 return false;
5b5455a9 3829 }
5b5455a9
PL		 3830}
3831
8c30e194
YL		 3832static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
3833{
3834 ring->desc[ring->next_to_clean].rx.bd_base_info &=
3835 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
9f9f0f19 3836 ring->desc_cb[ring->next_to_clean].refill = 0;
8c30e194
YL		 3837 ring->next_to_clean += 1;
3838
3839 if (unlikely(ring->next_to_clean == ring->desc_num))
3840 ring->next_to_clean = 0;
3841}
3842
b9a8f883 3843static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
e5597095
PL		 3844 unsigned char *va)
3845{
e5597095 3846 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
c8711956 3847 struct net_device *netdev = ring_to_netdev(ring);
e5597095
PL		 3848 struct sk_buff *skb;
3849
3850 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
3851 skb = ring->skb;
3852 if (unlikely(!skb)) {
b20d7fe5 3853 hns3_rl_err(netdev, "alloc rx skb fail\n");
e5597095
PL		 3854
3855 u64_stats_update_begin(&ring->syncp);
3856 ring->stats.sw_err_cnt++;
3857 u64_stats_update_end(&ring->syncp);
3858
3859 return -ENOMEM;
3860 }
3861
698a8954 3862 trace_hns3_rx_desc(ring);
e5597095
PL		 3863 prefetchw(skb->data);
3864
3865 ring->pending_buf = 1;
81ae0e04
PL		 3866 ring->frag_num = 0;
3867 ring->tail_skb = NULL;
e5597095
PL		 3868 if (length <= HNS3_RX_HEAD_SIZE) {
3869 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
3870
a79afa78
AL		 3871 /* We can reuse buffer as-is, just make sure it is reusable */
3872 if (dev_page_is_reusable(desc_cb->priv))
e5597095 3873 desc_cb->reuse_flag = 1;
93188e96
YL		 3874 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
3875 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
3876 false);
e5597095 3877 else /* This page cannot be reused so discard it */
aeda9bf8
YL		 3878 __page_frag_cache_drain(desc_cb->priv,
3879 desc_cb->pagecnt_bias);
e5597095 3880
8c30e194 3881 hns3_rx_ring_move_fw(ring);
e5597095
PL		 3882 return 0;
3883 }
93188e96
YL		 3884
3885 if (ring->page_pool)
3886 skb_mark_for_recycle(skb);
3887
e5597095
PL		 3888 u64_stats_update_begin(&ring->syncp);
3889 ring->stats.seg_pkt_cnt++;
3890 u64_stats_update_end(&ring->syncp);
3891
c43f1255 3892 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 3893 __skb_put(skb, ring->pull_len);
81ae0e04 3894 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095 3895 desc_cb);
8c30e194 3896 hns3_rx_ring_move_fw(ring);
e5597095 3897
b2598318 3898 return 0;
e5597095
PL		 3899}
3900
b2598318 3901static int hns3_add_frag(struct hns3_enet_ring *ring)
e5597095 3902{
d35bced8
YL		 3903 struct sk_buff *skb = ring->skb;
3904 struct sk_buff *head_skb = skb;
81ae0e04 3905 struct sk_buff *new_skb;
e5597095 3906 struct hns3_desc_cb *desc_cb;
b2598318 3907 struct hns3_desc *desc;
e5597095 3908 u32 bd_base_info;
e5597095 3909
b2598318 3910 do {
e5597095
PL		 3911 desc = &ring->desc[ring->next_to_clean];
3912 desc_cb = &ring->desc_cb[ring->next_to_clean];
3913 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS		 3914 /* make sure HW write desc complete */
3915 dma_rmb();
e8149933 3916 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL		 3917 return -ENXIO;
3918
81ae0e04 3919 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
7fda3a93 3920 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
81ae0e04 3921 if (unlikely(!new_skb)) {
c8711956 3922 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5 3923 "alloc rx fraglist skb fail\n");
81ae0e04
PL		 3924 return -ENXIO;
3925 }
93188e96
YL		 3926
3927 if (ring->page_pool)
3928 skb_mark_for_recycle(new_skb);
3929
81ae0e04
PL		 3930 ring->frag_num = 0;
3931
3932 if (ring->tail_skb) {
3933 ring->tail_skb->next = new_skb;
3934 ring->tail_skb = new_skb;
3935 } else {
3936 skb_shinfo(skb)->frag_list = new_skb;
3937 ring->tail_skb = new_skb;
3938 }
3939 }
3940
3941 if (ring->tail_skb) {
dbba6da0 3942 head_skb->truesize += hns3_buf_size(ring);
81ae0e04
PL		 3943 head_skb->data_len += le16_to_cpu(desc->rx.size);
3944 head_skb->len += le16_to_cpu(desc->rx.size);
3945 skb = ring->tail_skb;
3946 }
3947
c2a2e127
BS		 3948 dma_sync_single_for_cpu(ring_to_dev(ring),
3949 desc_cb->dma + desc_cb->page_offset,
3950 hns3_buf_size(ring),
3951 DMA_FROM_DEVICE);
3952
81ae0e04 3953 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
698a8954 3954 trace_hns3_rx_desc(ring);
8c30e194 3955 hns3_rx_ring_move_fw(ring);
e5597095 3956 ring->pending_buf++;
b2598318 3957 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
e5597095
PL		 3958
3959 return 0;
3960}
3961
d474d88f
YL		 3962static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
3963 struct sk_buff *skb, u32 l234info,
1ddc028a 3964 u32 bd_base_info, u32 ol_info, u16 csum)
a6d53b97 3965{
79664077
HT		 3966 struct net_device *netdev = ring_to_netdev(ring);
3967 struct hns3_nic_priv *priv = netdev_priv(netdev);
a6d53b97
PL		 3968 u32 l3_type;
3969
e2ee1c5a
YL		 3970 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
3971 HNS3_RXD_GRO_SIZE_M,
3972 HNS3_RXD_GRO_SIZE_S);
a6d53b97 3973 /* if there is no HW GRO, do not set gro params */
e2ee1c5a 3974 if (!skb_shinfo(skb)->gso_size) {
1ddc028a
HT		 3975 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
3976 csum);
d474d88f
YL		 3977 return 0;
3978 }
a6d53b97 3979
e2ee1c5a
YL		 3980 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
3981 HNS3_RXD_GRO_COUNT_M,
3982 HNS3_RXD_GRO_COUNT_S);
a6d53b97 3983
79664077
HT		 3984 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
3985 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3986 HNS3_RXD_PTYPE_S);
3987
3988 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
3989 } else {
3990 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3991 HNS3_RXD_L3ID_S);
3992 }
3993
a6d53b97
PL		 3994 if (l3_type == HNS3_L3_TYPE_IPV4)
3995 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
3996 else if (l3_type == HNS3_L3_TYPE_IPV6)
3997 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
3998 else
d474d88f 3999 return -EFAULT;
a6d53b97 4000
e2ee1c5a 4001 return hns3_gro_complete(skb, l234info);
a6d53b97
PL		 4002}
4003
232fc64b 4004static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 4005 struct sk_buff *skb, u32 rss_hash)
232fc64b 4006{
232fc64b
PL		 4007 struct hnae3_handle *handle = ring->tqp->handle;
4008 enum pkt_hash_types rss_type;
4009
ea485867 4010 if (rss_hash)
232fc64b
PL		 4011 rss_type = handle->kinfo.rss_type;
4012 else
4013 rss_type = PKT_HASH_TYPE_NONE;
4014
ea485867 4015 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL		 4016}
4017
ea485867 4018static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e 4019{
c8711956 4020 struct net_device *netdev = ring_to_netdev(ring);
c376fa1a 4021 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 4022 u32 bd_base_info, l234info, ol_info;
ea485867 4023 struct hns3_desc *desc;
d474d88f 4024 unsigned int len;
ea485867 4025 int pre_ntc, ret;
1ddc028a 4026 u16 csum;
ea485867
YL		 4027
4028 /* bdinfo handled below is only valid on the last BD of the
4029 * current packet, and ring->next_to_clean indicates the first
4030 * descriptor of next packet, so need - 1 below.
4031 */
4032 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4033 (ring->desc_num - 1);
4034 desc = &ring->desc[pre_ntc];
4035 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4036 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 4037 ol_info = le32_to_cpu(desc->rx.ol_info);
1ddc028a 4038 csum = le16_to_cpu(desc->csum);
d474d88f 4039
0bf5eb78
HT		 4040 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4041 struct hnae3_handle *h = hns3_get_handle(netdev);
4042 u32 nsec = le32_to_cpu(desc->ts_nsec);
4043 u32 sec = le32_to_cpu(desc->ts_sec);
4044
4045 if (h->ae_algo->ops->get_rx_hwts)
4046 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4047 }
4048
d474d88f
YL		 4049 /* Based on hw strategy, the tag offloaded will be stored at
4050 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4051 * in one layer tag case.
4052 */
4053 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4054 u16 vlan_tag;
4055
4056 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4057 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4058 vlan_tag);
4059 }
4060
d474d88f
YL		 4061 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4062 BIT(HNS3_RXD_L2E_B))))) {
4063 u64_stats_update_begin(&ring->syncp);
4064 if (l234info & BIT(HNS3_RXD_L2E_B))
4065 ring->stats.l2_err++;
4066 else
4067 ring->stats.err_pkt_len++;
4068 u64_stats_update_end(&ring->syncp);
4069
4070 return -EFAULT;
4071 }
4072
4073 len = skb->len;
4074
4075 /* Do update ip stack process */
4076 skb->protocol = eth_type_trans(skb, netdev);
4077
4078 /* This is needed in order to enable forwarding support */
39c38824 4079 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
1ddc028a 4080 bd_base_info, ol_info, csum);
d474d88f
YL		 4081 if (unlikely(ret)) {
4082 u64_stats_update_begin(&ring->syncp);
4083 ring->stats.rx_err_cnt++;
4084 u64_stats_update_end(&ring->syncp);
4085 return ret;
4086 }
4087
4088 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4089 HNS3_RXD_DMAC_S);
4090
4091 u64_stats_update_begin(&ring->syncp);
4092 ring->stats.rx_pkts++;
4093 ring->stats.rx_bytes += len;
4094
4095 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4096 ring->stats.rx_multicast++;
4097
4098 u64_stats_update_end(&ring->syncp);
4099
4100 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL		 4101
4102 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL		 4103 return 0;
4104}
4105
d35bced8 4106static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
d474d88f 4107{
e5597095 4108 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 4109 struct hns3_desc_cb *desc_cb;
4110 struct hns3_desc *desc;
b9a8f883 4111 unsigned int length;
76ad4f0e 4112 u32 bd_base_info;
e5597095 4113 int ret;
76ad4f0e
S		 4114
4115 desc = &ring->desc[ring->next_to_clean];
4116 desc_cb = &ring->desc_cb[ring->next_to_clean];
4117
4118 prefetch(desc);
4119
8c30e194
YL		 4120 if (!skb) {
4121 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
8c30e194
YL		 4122 /* Check valid BD */
4123 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4124 return -ENXIO;
4125
4126 dma_rmb();
4127 length = le16_to_cpu(desc->rx.size);
76ad4f0e 4128
cb0e3e61 4129 ring->va = desc_cb->buf + desc_cb->page_offset;
76ad4f0e 4130
c2a2e127
BS		 4131 dma_sync_single_for_cpu(ring_to_dev(ring),
4132 desc_cb->dma + desc_cb->page_offset,
4133 hns3_buf_size(ring),
4134 DMA_FROM_DEVICE);
c2a2e127 4135
8c30e194
YL		 4136 /* Prefetch first cache line of first page.
4137 * Idea is to cache few bytes of the header of the packet.
4138 * Our L1 Cache line size is 64B so need to prefetch twice to make
4139 * it 128B. But in actual we can have greater size of caches with
4140 * 128B Level 1 cache lines. In such a case, single fetch would
4141 * suffice to cache in the relevant part of the header.
4142 */
4143 net_prefetch(ring->va);
76ad4f0e 4144
e5597095 4145 ret = hns3_alloc_skb(ring, length, ring->va);
d35bced8 4146 skb = ring->skb;
76ad4f0e 4147
e5597095
PL		 4148 if (ret < 0) /* alloc buffer fail */
4149 return ret;
b2598318
YL		 4150 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4151 ret = hns3_add_frag(ring);
e5597095
PL		 4152 if (ret)
4153 return ret;
e5597095 4154 }
76ad4f0e 4155 } else {
b2598318 4156 ret = hns3_add_frag(ring);
e5597095
PL		 4157 if (ret)
4158 return ret;
b2598318 4159 }
76ad4f0e 4160
b2598318
YL		 4161 /* As the head data may be changed when GRO enable, copy
4162 * the head data in after other data rx completed
4163 */
4164 if (skb->len > HNS3_RX_HEAD_SIZE)
e5597095
PL		 4165 memcpy(skb->data, ring->va,
4166 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e 4167
ea485867 4168 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 4169 if (unlikely(ret)) {
76ad4f0e 4170 dev_kfree_skb_any(skb);
d474d88f 4171 return ret;
76ad4f0e
S		 4172 }
4173
d93ed94f 4174 skb_record_rx_queue(skb, ring->tqp->tqp_index);
76ad4f0e
S		 4175 return 0;
4176}
4177
9b2f3477
WL		 4178int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4179 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 4180{
4181#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
63380a1a 4182 int unused_count = hns3_desc_unused(ring);
68752b24 4183 bool failure = false;
a4ee7624 4184 int recv_pkts = 0;
8c30e194 4185 int err;
76ad4f0e 4186
63380a1a 4187 unused_count -= ring->pending_buf;
76ad4f0e 4188
8c30e194 4189 while (recv_pkts < budget) {
76ad4f0e 4190 /* Reuse or realloc buffers */
a4ee7624 4191 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
68752b24
YL		 4192 failure = failure ||
4193 hns3_nic_alloc_rx_buffers(ring, unused_count);
4194 unused_count = 0;
76ad4f0e
S		 4195 }
4196
4197 /* Poll one pkt */
d35bced8
YL		 4198 err = hns3_handle_rx_bd(ring);
4199 /* Do not get FE for the packet or failed to alloc skb */
4200 if (unlikely(!ring->skb || err == -ENXIO)) {
76ad4f0e 4201 goto out;
d35bced8
YL		 4202 } else if (likely(!err)) {
4203 rx_fn(ring, ring->skb);
4204 recv_pkts++;
76ad4f0e
S		 4205 }
4206
a4ee7624 4207 unused_count += ring->pending_buf;
e5597095
PL		 4208 ring->skb = NULL;
4209 ring->pending_buf = 0;
76ad4f0e
S		 4210 }
4211
4212out:
68752b24 4213 return failure ? budget : recv_pkts;
76ad4f0e
S		 4214}
4215
307ea4ce 4216static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
76ad4f0e 4217{
307ea4ce
HT		 4218 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4219 struct dim_sample sample = {};
4a43caf5 4220
307ea4ce
HT		 4221 if (!rx_group->coal.adapt_enable)
4222 return;
76ad4f0e 4223
307ea4ce
HT		 4224 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4225 rx_group->total_bytes, &sample);
4226 net_dim(&rx_group->dim, sample);
76ad4f0e
S		 4227}
4228
307ea4ce 4229static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
76ad4f0e 4230{
8b1ff1ea 4231 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
307ea4ce 4232 struct dim_sample sample = {};
8b1ff1ea 4233
307ea4ce 4234 if (!tx_group->coal.adapt_enable)
cd9d187b 4235 return;
cd9d187b 4236
307ea4ce
HT		 4237 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4238 tx_group->total_bytes, &sample);
4239 net_dim(&tx_group->dim, sample);
76ad4f0e
S		 4240}
4241
4242static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4243{
ff0699e0 4244 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 4245 struct hns3_enet_ring *ring;
4246 int rx_pkt_total = 0;
4247
4248 struct hns3_enet_tqp_vector *tqp_vector =
4249 container_of(napi, struct hns3_enet_tqp_vector, napi);
4250 bool clean_complete = true;
ceca4a5e 4251 int rx_budget = budget;
76ad4f0e 4252
ff0699e0
HT		 4253 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4254 napi_complete(napi);
4255 return 0;
4256 }
4257
76ad4f0e
S		 4258 /* Since the actual Tx work is minimal, we can give the Tx a larger
4259 * budget and be more aggressive about cleaning up the Tx descriptors.
4260 */
799997a3 4261 hns3_for_each_ring(ring, tqp_vector->tx_group)
619ae331 4262 hns3_clean_tx_ring(ring, budget);
76ad4f0e
S		 4263
4264 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL		 4265 if (tqp_vector->num_tqps > 1)
4266 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S		 4267
4268 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 4269 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4270 hns3_rx_skb);
76ad4f0e
S		 4271 if (rx_cleaned >= rx_budget)
4272 clean_complete = false;
4273
4274 rx_pkt_total += rx_cleaned;
4275 }
4276
4277 tqp_vector->rx_group.total_packets += rx_pkt_total;
4278
4279 if (!clean_complete)
4280 return budget;
4281
531eba0f
HT		 4282 if (napi_complete(napi) &&
4283 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
307ea4ce
HT		 4284 hns3_update_rx_int_coalesce(tqp_vector);
4285 hns3_update_tx_int_coalesce(tqp_vector);
4286
ff0699e0
HT		 4287 hns3_mask_vector_irq(tqp_vector, 1);
4288 }
76ad4f0e
S		 4289
4290 return rx_pkt_total;
4291}
4292
4293static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4294 struct hnae3_ring_chain_node *head)
4295{
4296 struct pci_dev *pdev = tqp_vector->handle->pdev;
4297 struct hnae3_ring_chain_node *cur_chain = head;
4298 struct hnae3_ring_chain_node *chain;
4299 struct hns3_enet_ring *tx_ring;
4300 struct hns3_enet_ring *rx_ring;
4301
4302 tx_ring = tqp_vector->tx_group.ring;
4303 if (tx_ring) {
4304 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 4305 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
4306 HNAE3_RING_TYPE_TX);
4307 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4308 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 4309
4310 cur_chain->next = NULL;
4311
4312 while (tx_ring->next) {
4313 tx_ring = tx_ring->next;
4314
4315 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
4316 GFP_KERNEL);
4317 if (!chain)
73b907a0 4318 goto err_free_chain;
76ad4f0e
S		 4319
4320 cur_chain->next = chain;
4321 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 4322 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4323 HNAE3_RING_TYPE_TX);
4324 hnae3_set_field(chain->int_gl_idx,
4325 HNAE3_RING_GL_IDX_M,
4326 HNAE3_RING_GL_IDX_S,
4327 HNAE3_RING_GL_TX);
76ad4f0e
S		 4328
4329 cur_chain = chain;
4330 }
4331 }
4332
4333 rx_ring = tqp_vector->rx_group.ring;
4334 if (!tx_ring && rx_ring) {
4335 cur_chain->next = NULL;
4336 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 4337 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
4338 HNAE3_RING_TYPE_RX);
4339 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4340 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 4341
4342 rx_ring = rx_ring->next;
4343 }
4344
4345 while (rx_ring) {
4346 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4347 if (!chain)
73b907a0 4348 goto err_free_chain;
76ad4f0e
S		 4349
4350 cur_chain->next = chain;
4351 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 4352 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4353 HNAE3_RING_TYPE_RX);
4354 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
4355 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 4356
76ad4f0e
S		 4357 cur_chain = chain;
4358
4359 rx_ring = rx_ring->next;
4360 }
4361
4362 return 0;
73b907a0
HT		 4363
4364err_free_chain:
4365 cur_chain = head->next;
4366 while (cur_chain) {
4367 chain = cur_chain->next;
cda69d24 4368 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 4369 cur_chain = chain;
4370 }
cda69d24 4371 head->next = NULL;
73b907a0
HT		 4372
4373 return -ENOMEM;
76ad4f0e
S		 4374}
4375
4376static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4377 struct hnae3_ring_chain_node *head)
4378{
4379 struct pci_dev *pdev = tqp_vector->handle->pdev;
4380 struct hnae3_ring_chain_node *chain_tmp, *chain;
4381
4382 chain = head->next;
4383
4384 while (chain) {
4385 chain_tmp = chain->next;
4386 devm_kfree(&pdev->dev, chain);
4387 chain = chain_tmp;
4388 }
4389}
4390
4391static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4392 struct hns3_enet_ring *ring)
4393{
4394 ring->next = group->ring;
4395 group->ring = ring;
4396
4397 group->count++;
4398}
4399
874bff0b
PL		 4400static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4401{
4402 struct pci_dev *pdev = priv->ae_handle->pdev;
4403 struct hns3_enet_tqp_vector *tqp_vector;
4404 int num_vectors = priv->vector_num;
4405 int numa_node;
4406 int vector_i;
4407
4408 numa_node = dev_to_node(&pdev->dev);
4409
4410 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4411 tqp_vector = &priv->tqp_vector[vector_i];
4412 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4413 &tqp_vector->affinity_mask);
4414 }
4415}
4416
307ea4ce
HT		 4417static void hns3_rx_dim_work(struct work_struct *work)
4418{
4419 struct dim *dim = container_of(work, struct dim, work);
4420 struct hns3_enet_ring_group *group = container_of(dim,
4421 struct hns3_enet_ring_group, dim);
4422 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4423 struct dim_cq_moder cur_moder =
4424 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4425
4426 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4427 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4428
4429 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4430 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4431 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4432 }
4433
4434 dim->state = DIM_START_MEASURE;
4435}
4436
4437static void hns3_tx_dim_work(struct work_struct *work)
4438{
4439 struct dim *dim = container_of(work, struct dim, work);
4440 struct hns3_enet_ring_group *group = container_of(dim,
4441 struct hns3_enet_ring_group, dim);
4442 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4443 struct dim_cq_moder cur_moder =
4444 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4445
4446 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4447 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4448
4449 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4450 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4451 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4452 }
4453
4454 dim->state = DIM_START_MEASURE;
4455}
4456
4457static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4458{
4459 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
307ea4ce 4460 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
307ea4ce
HT		 4461}
4462
76ad4f0e
S		 4463static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4464{
76ad4f0e
S		 4465 struct hnae3_handle *h = priv->ae_handle;
4466 struct hns3_enet_tqp_vector *tqp_vector;
9d8d5a36 4467 int ret;
ece4bf46 4468 int i;
76ad4f0e 4469
874bff0b
PL		 4470 hns3_nic_set_cpumask(priv);
4471
dd38c726
YL		 4472 for (i = 0; i < priv->vector_num; i++) {
4473 tqp_vector = &priv->tqp_vector[i];
91bfae25 4474 hns3_vector_coalesce_init_hw(tqp_vector, priv);
dd38c726 4475 tqp_vector->num_tqps = 0;
307ea4ce 4476 hns3_nic_init_dim(tqp_vector);
dd38c726 4477 }
76ad4f0e 4478
dd38c726
YL		 4479 for (i = 0; i < h->kinfo.num_tqps; i++) {
4480 u16 vector_i = i % priv->vector_num;
4481 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 4482
4483 tqp_vector = &priv->tqp_vector[vector_i];
4484
4485 hns3_add_ring_to_group(&tqp_vector->tx_group,
5f06b903 4486 &priv->ring[i]);
76ad4f0e
S		 4487
4488 hns3_add_ring_to_group(&tqp_vector->rx_group,
5f06b903 4489 &priv->ring[i + tqp_num]);
76ad4f0e 4490
5f06b903
YL		 4491 priv->ring[i].tqp_vector = tqp_vector;
4492 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
dd38c726 4493 tqp_vector->num_tqps++;
76ad4f0e
S		 4494 }
4495
dd38c726 4496 for (i = 0; i < priv->vector_num; i++) {
d392ecd1
SM		 4497 struct hnae3_ring_chain_node vector_ring_chain;
4498
76ad4f0e
S		 4499 tqp_vector = &priv->tqp_vector[i];
4500
4501 tqp_vector->rx_group.total_bytes = 0;
4502 tqp_vector->rx_group.total_packets = 0;
4503 tqp_vector->tx_group.total_bytes = 0;
4504 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 4505 tqp_vector->handle = h;
4506
4507 ret = hns3_get_vector_ring_chain(tqp_vector,
4508 &vector_ring_chain);
4509 if (ret)
cda69d24 4510 goto map_ring_fail;
76ad4f0e
S		 4511
4512 ret = h->ae_algo->ops->map_ring_to_vector(h,
4513 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 4514
4515 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
4516
dd38c726 4517 if (ret)
ece4bf46 4518 goto map_ring_fail;
dd38c726 4519
76ad4f0e
S		 4520 netif_napi_add(priv->netdev, &tqp_vector->napi,
4521 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
4522 }
4523
dd38c726 4524 return 0;
ece4bf46
HT		 4525
4526map_ring_fail:
4527 while (i--)
4528 netif_napi_del(&priv->tqp_vector[i].napi);
4529
4530 return ret;
dd38c726
YL		 4531}
4532
73a13d8d
HT		 4533static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4534{
4535 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
4536 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4537 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4538
4539 /* initialize the configuration for interrupt coalescing.
4540 * 1. GL (Interrupt Gap Limiter)
4541 * 2. RL (Interrupt Rate Limiter)
4542 * 3. QL (Interrupt Quantity Limiter)
4543 *
4544 * Default: enable interrupt coalescing self-adaptive and GL
4545 */
4546 tx_coal->adapt_enable = 1;
4547 rx_coal->adapt_enable = 1;
4548
4549 tx_coal->int_gl = HNS3_INT_GL_50K;
4550 rx_coal->int_gl = HNS3_INT_GL_50K;
4551
4552 rx_coal->flow_level = HNS3_FLOW_LOW;
4553 tx_coal->flow_level = HNS3_FLOW_LOW;
4554
4555 if (ae_dev->dev_specs.int_ql_max) {
4556 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4557 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4558 }
4559}
4560
dd38c726
YL		 4561static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4562{
4563 struct hnae3_handle *h = priv->ae_handle;
4564 struct hns3_enet_tqp_vector *tqp_vector;
4565 struct hnae3_vector_info *vector;
4566 struct pci_dev *pdev = h->pdev;
4567 u16 tqp_num = h->kinfo.num_tqps;
4568 u16 vector_num;
4569 int ret = 0;
4570 u16 i;
4571
4572 /* RSS size, cpu online and vector_num should be the same */
4573 /* Should consider 2p/4p later */
4574 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610 4575
dd38c726
YL		 4576 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4577 GFP_KERNEL);
4578 if (!vector)
4579 return -ENOMEM;
4580
9b2f3477 4581 /* save the actual available vector number */
dd38c726
YL		 4582 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4583
4584 priv->vector_num = vector_num;
4585 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4586 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4587 GFP_KERNEL);
4588 if (!priv->tqp_vector) {
4589 ret = -ENOMEM;
4590 goto out;
4591 }
4592
4593 for (i = 0; i < priv->vector_num; i++) {
4594 tqp_vector = &priv->tqp_vector[i];
4595 tqp_vector->idx = i;
4596 tqp_vector->mask_addr = vector[i].io_addr;
4597 tqp_vector->vector_irq = vector[i].vector;
91bfae25 4598 hns3_vector_coalesce_init(tqp_vector, priv);
dd38c726
YL		 4599 }
4600
76ad4f0e
S		 4601out:
4602 devm_kfree(&pdev->dev, vector);
4603 return ret;
4604}
4605
dd38c726
YL		 4606static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4607{
4608 group->ring = NULL;
4609 group->count = 0;
4610}
4611
e2152785 4612static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S		 4613{
4614 struct hnae3_ring_chain_node vector_ring_chain;
4615 struct hnae3_handle *h = priv->ae_handle;
4616 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 4617 int i;
76ad4f0e
S		 4618
4619 for (i = 0; i < priv->vector_num; i++) {
4620 tqp_vector = &priv->tqp_vector[i];
4621
2c9dd668
HT		 4622 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4623 continue;
4624
ff7dfcdd
HT		 4625 /* Since the mapping can be overwritten, when fail to get the
4626 * chain between vector and ring, we should go on to deal with
4627 * the remaining options.
4628 */
4629 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
4630 dev_warn(priv->dev, "failed to get ring chain\n");
76ad4f0e 4631
e2152785 4632 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 4633 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 4634
4635 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
4636
dd38c726
YL		 4637 hns3_clear_ring_group(&tqp_vector->rx_group);
4638 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 4639 netif_napi_del(&priv->tqp_vector[i].napi);
4640 }
dd38c726
YL		 4641}
4642
08a10068 4643static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
dd38c726
YL		 4644{
4645 struct hnae3_handle *h = priv->ae_handle;
4646 struct pci_dev *pdev = h->pdev;
4647 int i, ret;
4648
4649 for (i = 0; i < priv->vector_num; i++) {
4650 struct hns3_enet_tqp_vector *tqp_vector;
4651
4652 tqp_vector = &priv->tqp_vector[i];
4653 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4654 if (ret)
08a10068 4655 return;
dd38c726 4656 }
76ad4f0e 4657
dd38c726 4658 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 4659}
4660
5f06b903
YL		 4661static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4662 unsigned int ring_type)
76ad4f0e 4663{
76ad4f0e 4664 int queue_num = priv->ae_handle->kinfo.num_tqps;
76ad4f0e 4665 struct hns3_enet_ring *ring;
c0425944 4666 int desc_num;
76ad4f0e 4667
76ad4f0e 4668 if (ring_type == HNAE3_RING_TYPE_TX) {
5f06b903 4669 ring = &priv->ring[q->tqp_index];
c0425944 4670 desc_num = priv->ae_handle->kinfo.num_tx_desc;
5f06b903 4671 ring->queue_index = q->tqp_index;
907676b1
YL		 4672 ring->tx_copybreak = priv->tx_copybreak;
4673 ring->last_to_use = 0;
76ad4f0e 4674 } else {
5f06b903 4675 ring = &priv->ring[q->tqp_index + queue_num];
c0425944 4676 desc_num = priv->ae_handle->kinfo.num_rx_desc;
5f06b903 4677 ring->queue_index = q->tqp_index;
99f6b5fb 4678 ring->rx_copybreak = priv->rx_copybreak;
76ad4f0e
S		 4679 }
4680
e4e87715 4681 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 4682
76ad4f0e
S		 4683 ring->tqp = q;
4684 ring->desc = NULL;
4685 ring->desc_cb = NULL;
4686 ring->dev = priv->dev;
4687 ring->desc_dma_addr = 0;
4688 ring->buf_size = q->buf_size;
2c9dd668 4689 ring->desc_num = desc_num;
76ad4f0e
S		 4690 ring->next_to_use = 0;
4691 ring->next_to_clean = 0;
76ad4f0e
S		 4692}
4693
5f06b903
YL		 4694static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4695 struct hns3_nic_priv *priv)
76ad4f0e 4696{
5f06b903
YL		 4697 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4698 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
76ad4f0e
S		 4699}
4700
4701static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4702{
4703 struct hnae3_handle *h = priv->ae_handle;
4704 struct pci_dev *pdev = h->pdev;
5f06b903 4705 int i;
76ad4f0e 4706
5f06b903
YL		 4707 priv->ring = devm_kzalloc(&pdev->dev,
4708 array3_size(h->kinfo.num_tqps,
4709 sizeof(*priv->ring), 2),
4710 GFP_KERNEL);
4711 if (!priv->ring)
76ad4f0e
S		 4712 return -ENOMEM;
4713
5f06b903
YL		 4714 for (i = 0; i < h->kinfo.num_tqps; i++)
4715 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
76ad4f0e
S		 4716
4717 return 0;
76ad4f0e
S		 4718}
4719
09f2af64
PL		 4720static void hns3_put_ring_config(struct hns3_nic_priv *priv)
4721{
5f06b903 4722 if (!priv->ring)
7b8f622e
HT		 4723 return;
4724
5f06b903
YL		 4725 devm_kfree(priv->dev, priv->ring);
4726 priv->ring = NULL;
09f2af64
PL		 4727}
4728
93188e96
YL		 4729static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
4730{
4731 struct page_pool_params pp_params = {
4732 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG |
4733 PP_FLAG_DMA_SYNC_DEV,
4734 .order = hns3_page_order(ring),
4735 .pool_size = ring->desc_num * hns3_buf_size(ring) /
4736 (PAGE_SIZE << hns3_page_order(ring)),
4737 .nid = dev_to_node(ring_to_dev(ring)),
4738 .dev = ring_to_dev(ring),
4739 .dma_dir = DMA_FROM_DEVICE,
4740 .offset = 0,
4741 .max_len = PAGE_SIZE << hns3_page_order(ring),
4742 };
4743
4744 ring->page_pool = page_pool_create(&pp_params);
4745 if (IS_ERR(ring->page_pool)) {
4746 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
4747 PTR_ERR(ring->page_pool));
4748 ring->page_pool = NULL;
4749 }
4750}
4751
76ad4f0e
S		 4752static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
4753{
4754 int ret;
4755
4756 if (ring->desc_num <= 0 || ring->buf_size <= 0)
4757 return -EINVAL;
4758
77296bf6
YL		 4759 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
4760 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S		 4761 if (!ring->desc_cb) {
4762 ret = -ENOMEM;
4763 goto out;
4764 }
4765
4766 ret = hns3_alloc_desc(ring);
4767 if (ret)
4768 goto out_with_desc_cb;
4769
4770 if (!HNAE3_IS_TX_RING(ring)) {
f7ec554b
YL		 4771 if (page_pool_enabled)
4772 hns3_alloc_page_pool(ring);
93188e96 4773
76ad4f0e
S		 4774 ret = hns3_alloc_ring_buffers(ring);
4775 if (ret)
4776 goto out_with_desc;
907676b1
YL		 4777 } else {
4778 hns3_init_tx_spare_buffer(ring);
76ad4f0e
S		 4779 }
4780
4781 return 0;
4782
4783out_with_desc:
4784 hns3_free_desc(ring);
4785out_with_desc_cb:
77296bf6 4786 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 4787 ring->desc_cb = NULL;
4788out:
4789 return ret;
4790}
4791
a723fb8e 4792void hns3_fini_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 4793{
4794 hns3_free_desc(ring);
77296bf6 4795 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 4796 ring->desc_cb = NULL;
4797 ring->next_to_clean = 0;
4798 ring->next_to_use = 0;
20d06ca2 4799 ring->last_to_use = 0;
ac574b80 4800 ring->pending_buf = 0;
907676b1 4801 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
ac574b80
PL		 4802 dev_kfree_skb_any(ring->skb);
4803 ring->skb = NULL;
907676b1
YL		 4804 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
4805 struct hns3_tx_spare *tx_spare = ring->tx_spare;
4806
4807 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
4808 DMA_TO_DEVICE);
4809 free_pages((unsigned long)tx_spare->buf,
4810 get_order(tx_spare->len));
4811 devm_kfree(ring_to_dev(ring), tx_spare);
4812 ring->tx_spare = NULL;
ac574b80 4813 }
93188e96
YL		 4814
4815 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
4816 page_pool_destroy(ring->page_pool);
4817 ring->page_pool = NULL;
4818 }
76ad4f0e
S		 4819}
4820
1db9b1bf 4821static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 4822{
4823 int bd_size_type;
4824
4825 switch (buf_size) {
4826 case 512:
4827 bd_size_type = HNS3_BD_SIZE_512_TYPE;
4828 break;
4829 case 1024:
4830 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
4831 break;
4832 case 2048:
4833 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4834 break;
4835 case 4096:
4836 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
4837 break;
4838 default:
4839 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
4840 }
4841
4842 return bd_size_type;
4843}
4844
4845static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
4846{
4847 dma_addr_t dma = ring->desc_dma_addr;
4848 struct hnae3_queue *q = ring->tqp;
4849
4850 if (!HNAE3_IS_TX_RING(ring)) {
9b2f3477 4851 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
76ad4f0e
S		 4852 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
4853 (u32)((dma >> 31) >> 1));
4854
4855 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
4856 hns3_buf_size2type(ring->buf_size));
4857 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
4858 ring->desc_num / 8 - 1);
76ad4f0e
S		 4859 } else {
4860 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
4861 (u32)dma);
4862 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
4863 (u32)((dma >> 31) >> 1));
4864
76ad4f0e
S		 4865 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
4866 ring->desc_num / 8 - 1);
4867 }
4868}
4869
1c772154
YL		 4870static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
4871{
4872 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
35244430 4873 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
1c772154
YL		 4874 int i;
4875
a8e76fef 4876 for (i = 0; i < tc_info->num_tc; i++) {
1c772154
YL		 4877 int j;
4878
35244430 4879 for (j = 0; j < tc_info->tqp_count[i]; j++) {
1c772154
YL		 4880 struct hnae3_queue *q;
4881
35244430
JS		 4882 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
4883 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
1c772154
YL		 4884 }
4885 }
4886}
4887
5668abda 4888int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 4889{
4890 struct hnae3_handle *h = priv->ae_handle;
4891 int ring_num = h->kinfo.num_tqps * 2;
4892 int i, j;
4893 int ret;
4894
4895 for (i = 0; i < ring_num; i++) {
5f06b903 4896 ret = hns3_alloc_ring_memory(&priv->ring[i]);
76ad4f0e
S		 4897 if (ret) {
4898 dev_err(priv->dev,
4899 "Alloc ring memory fail! ret=%d\n", ret);
4900 goto out_when_alloc_ring_memory;
4901 }
4902
5f06b903 4903 u64_stats_init(&priv->ring[i].syncp);
76ad4f0e
S		 4904 }
4905
4906 return 0;
4907
4908out_when_alloc_ring_memory:
4909 for (j = i - 1; j >= 0; j--)
5f06b903 4910 hns3_fini_ring(&priv->ring[j]);
76ad4f0e
S		 4911
4912 return -ENOMEM;
4913}
4914
64749c9c 4915static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 4916{
4917 struct hnae3_handle *h = priv->ae_handle;
4918 int i;
4919
4920 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903
YL		 4921 hns3_fini_ring(&priv->ring[i]);
4922 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
76ad4f0e 4923 }
76ad4f0e
S		 4924}
4925
4926/* Set mac addr if it is configured. or leave it to the AE driver */
8e6de441 4927static int hns3_init_mac_addr(struct net_device *netdev)
76ad4f0e
S		 4928{
4929 struct hns3_nic_priv *priv = netdev_priv(netdev);
4930 struct hnae3_handle *h = priv->ae_handle;
4931 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 4932 int ret = 0;
76ad4f0e 4933
8e6de441 4934 if (h->ae_algo->ops->get_mac_addr)
76ad4f0e 4935 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
76ad4f0e
S		 4936
4937 /* Check if the MAC address is valid, if not get a random one */
8e6de441 4938 if (!is_valid_ether_addr(mac_addr_temp)) {
76ad4f0e
S		 4939 eth_hw_addr_random(netdev);
4940 dev_warn(priv->dev, "using random MAC address %pM\n",
4941 netdev->dev_addr);
ee4bcd3b 4942 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
8e6de441
HT		 4943 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
4944 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
ee4bcd3b
JS		 4945 } else {
4946 return 0;
76ad4f0e 4947 }
139e8792
L		 4948
4949 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 4950 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 4951
7fa6be4f 4952 return ret;
76ad4f0e
S		 4953}
4954
c8a8045b
HT		 4955static int hns3_init_phy(struct net_device *netdev)
4956{
4957 struct hnae3_handle *h = hns3_get_handle(netdev);
4958 int ret = 0;
4959
4960 if (h->ae_algo->ops->mac_connect_phy)
4961 ret = h->ae_algo->ops->mac_connect_phy(h);
4962
4963 return ret;
4964}
4965
4966static void hns3_uninit_phy(struct net_device *netdev)
4967{
4968 struct hnae3_handle *h = hns3_get_handle(netdev);
4969
4970 if (h->ae_algo->ops->mac_disconnect_phy)
4971 h->ae_algo->ops->mac_disconnect_phy(h);
4972}
4973
a6d818e3
YL		 4974static int hns3_client_start(struct hnae3_handle *handle)
4975{
4976 if (!handle->ae_algo->ops->client_start)
4977 return 0;
4978
4979 return handle->ae_algo->ops->client_start(handle);
4980}
4981
4982static void hns3_client_stop(struct hnae3_handle *handle)
4983{
4984 if (!handle->ae_algo->ops->client_stop)
4985 return;
4986
4987 handle->ae_algo->ops->client_stop(handle);
4988}
4989
bb87be87
YL		 4990static void hns3_info_show(struct hns3_nic_priv *priv)
4991{
4992 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
4993
4994 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
adcf738b
GL		 4995 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
4996 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
4997 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
4998 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
4999 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5000 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
35244430
JS		 5001 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5002 kinfo->tc_info.num_tc);
adcf738b 5003 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
bb87be87
YL		 5004}
5005
9f0c6f4b
YM		 5006static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5007 enum dim_cq_period_mode mode, bool is_tx)
5008{
5009 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
5010 struct hnae3_handle *handle = priv->ae_handle;
5011 int i;
5012
5013 if (is_tx) {
5014 priv->tx_cqe_mode = mode;
5015
5016 for (i = 0; i < priv->vector_num; i++)
5017 priv->tqp_vector[i].tx_group.dim.mode = mode;
5018 } else {
5019 priv->rx_cqe_mode = mode;
5020
5021 for (i = 0; i < priv->vector_num; i++)
5022 priv->tqp_vector[i].rx_group.dim.mode = mode;
5023 }
5024
5025 /* only device version above V3(include V3), GL can switch CQ/EQ
5026 * period mode.
5027 */
5028 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
5029 u32 new_mode;
5030 u64 reg;
5031
5032 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5033 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5034 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5035
5036 writel(new_mode, handle->kinfo.io_base + reg);
5037 }
5038}
5039
cce1689e
YM		 5040void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5041 enum dim_cq_period_mode tx_mode,
5042 enum dim_cq_period_mode rx_mode)
9f0c6f4b
YM		 5043{
5044 hns3_set_cq_period_mode(priv, tx_mode, true);
5045 hns3_set_cq_period_mode(priv, rx_mode, false);
5046}
5047
c511dfff
HT		 5048static void hns3_state_init(struct hnae3_handle *handle)
5049{
5050 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
5051 struct net_device *netdev = handle->kinfo.netdev;
5052 struct hns3_nic_priv *priv = netdev_priv(netdev);
5053
5054 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5055
5056 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5057 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5058
5059 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5060 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5061
5062 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5063 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5064}
5065
76ad4f0e
S		 5066static int hns3_client_init(struct hnae3_handle *handle)
5067{
5068 struct pci_dev *pdev = handle->pdev;
fd665b3d 5069 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
0d43bf45 5070 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 5071 struct hns3_nic_priv *priv;
5072 struct net_device *netdev;
5073 int ret;
5074
0d43bf45
HT		 5075 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5076 &max_rss_size);
5077 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 5078 if (!netdev)
5079 return -ENOMEM;
5080
5081 priv = netdev_priv(netdev);
5082 priv->dev = &pdev->dev;
5083 priv->netdev = netdev;
5084 priv->ae_handle = handle;
f8fa222c 5085 priv->tx_timeout_count = 0;
fd665b3d 5086 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
b7b585c2 5087 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 5088
bb87be87
YL		 5089 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5090
76ad4f0e
S		 5091 handle->kinfo.netdev = netdev;
5092 handle->priv = (void *)priv;
5093
8e6de441 5094 hns3_init_mac_addr(netdev);
76ad4f0e
S		 5095
5096 hns3_set_default_feature(netdev);
5097
5098 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5099 netdev->priv_flags |= IFF_UNICAST_FLT;
5100 netdev->netdev_ops = &hns3_nic_netdev_ops;
5101 SET_NETDEV_DEV(netdev, &pdev->dev);
5102 hns3_ethtool_set_ops(netdev);
76ad4f0e
S		 5103
5104 /* Carrier off reporting is important to ethtool even BEFORE open */
5105 netif_carrier_off(netdev);
5106
5107 ret = hns3_get_ring_config(priv);
5108 if (ret) {
5109 ret = -ENOMEM;
5110 goto out_get_ring_cfg;
5111 }
5112
73a13d8d
HT		 5113 hns3_nic_init_coal_cfg(priv);
5114
dd38c726
YL		 5115 ret = hns3_nic_alloc_vector_data(priv);
5116 if (ret) {
5117 ret = -ENOMEM;
5118 goto out_alloc_vector_data;
5119 }
5120
76ad4f0e
S		 5121 ret = hns3_nic_init_vector_data(priv);
5122 if (ret) {
5123 ret = -ENOMEM;
5124 goto out_init_vector_data;
5125 }
5126
5127 ret = hns3_init_all_ring(priv);
5128 if (ret) {
5129 ret = -ENOMEM;
5f06b903 5130 goto out_init_ring;
76ad4f0e
S		 5131 }
5132
9f0c6f4b
YM		 5133 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5134 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5135
c8a8045b
HT		 5136 ret = hns3_init_phy(netdev);
5137 if (ret)
5138 goto out_init_phy;
5139
08a10068
YL		 5140 /* the device can work without cpu rmap, only aRFS needs it */
5141 ret = hns3_set_rx_cpu_rmap(netdev);
5142 if (ret)
5143 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5144
5145 ret = hns3_nic_init_irq(priv);
5146 if (ret) {
5147 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5148 hns3_free_rx_cpu_rmap(netdev);
5149 goto out_init_irq_fail;
5150 }
5151
a6d818e3
YL		 5152 ret = hns3_client_start(handle);
5153 if (ret) {
5154 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
bf6de231 5155 goto out_client_start;
a6d818e3
YL		 5156 }
5157
986743db
YL		 5158 hns3_dcbnl_setup(handle);
5159
5e69ea7e
YM		 5160 ret = hns3_dbg_init(handle);
5161 if (ret) {
5162 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5163 ret);
5164 goto out_client_start;
5165 }
b2292360 5166
e070c8b9 5167 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
a8e8b7ff 5168
c511dfff 5169 hns3_state_init(handle);
5e7414cd 5170
a289a7e5
JS		 5171 ret = register_netdev(netdev);
5172 if (ret) {
5173 dev_err(priv->dev, "probe register netdev fail!\n");
5174 goto out_reg_netdev_fail;
5175 }
5176
bb87be87
YL		 5177 if (netif_msg_drv(handle))
5178 hns3_info_show(priv);
5179
76ad4f0e
S		 5180 return ret;
5181
a289a7e5
JS		 5182out_reg_netdev_fail:
5183 hns3_dbg_uninit(handle);
18655128 5184out_client_start:
08a10068
YL		 5185 hns3_free_rx_cpu_rmap(netdev);
5186 hns3_nic_uninit_irq(priv);
5187out_init_irq_fail:
c8a8045b
HT		 5188 hns3_uninit_phy(netdev);
5189out_init_phy:
5190 hns3_uninit_all_ring(priv);
5f06b903 5191out_init_ring:
e2152785 5192 hns3_nic_uninit_vector_data(priv);
76ad4f0e 5193out_init_vector_data:
dd38c726
YL		 5194 hns3_nic_dealloc_vector_data(priv);
5195out_alloc_vector_data:
5f06b903 5196 priv->ring = NULL;
76ad4f0e
S		 5197out_get_ring_cfg:
5198 priv->ae_handle = NULL;
5199 free_netdev(netdev);
5200 return ret;
5201}
5202
5203static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5204{
5205 struct net_device *netdev = handle->kinfo.netdev;
5206 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 5207
5208 if (netdev->reg_state != NETREG_UNINITIALIZED)
5209 unregister_netdev(netdev);
5210
eb32c896
HT		 5211 hns3_client_stop(handle);
5212
0d2f68c7
HT		 5213 hns3_uninit_phy(netdev);
5214
814da63c
HT		 5215 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5216 netdev_warn(netdev, "already uninitialized\n");
5217 goto out_netdev_free;
5218 }
5219
08a10068
YL		 5220 hns3_free_rx_cpu_rmap(netdev);
5221
5222 hns3_nic_uninit_irq(priv);
5223
f96315f2 5224 hns3_clear_all_ring(handle, true);
7b763f3f 5225
e2152785 5226 hns3_nic_uninit_vector_data(priv);
76ad4f0e 5227
08a10068 5228 hns3_nic_dealloc_vector_data(priv);
dd38c726 5229
64749c9c 5230 hns3_uninit_all_ring(priv);
76ad4f0e 5231
ec777890
YL		 5232 hns3_put_ring_config(priv);
5233
814da63c 5234out_netdev_free:
e22b5e72 5235 hns3_dbg_uninit(handle);
76ad4f0e
S		 5236 free_netdev(netdev);
5237}
5238
5239static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5240{
5241 struct net_device *netdev = handle->kinfo.netdev;
5242
5243 if (!netdev)
5244 return;
5245
5246 if (linkup) {
76ad4f0e 5247 netif_tx_wake_all_queues(netdev);
a7e90ee5 5248 netif_carrier_on(netdev);
bb87be87
YL		 5249 if (netif_msg_link(handle))
5250 netdev_info(netdev, "link up\n");
76ad4f0e
S		 5251 } else {
5252 netif_carrier_off(netdev);
5253 netif_tx_stop_all_queues(netdev);
bb87be87
YL		 5254 if (netif_msg_link(handle))
5255 netdev_info(netdev, "link down\n");
76ad4f0e
S		 5256 }
5257}
5258
beebca3a 5259static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 5260{
beebca3a 5261 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 5262 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
619ae331 5263 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
beebca3a
YL		 5264 ring_ptr_move_fw(ring, next_to_clean);
5265 }
f6061a05
YL		 5266
5267 ring->pending_buf = 0;
beebca3a
YL		 5268}
5269
7b763f3f
FL		 5270static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5271{
5272 struct hns3_desc_cb res_cbs;
5273 int ret;
5274
5275 while (ring->next_to_use != ring->next_to_clean) {
5276 /* When a buffer is not reused, it's memory has been
5277 * freed in hns3_handle_rx_bd or will be freed by
5278 * stack, so we need to replace the buffer here.
5279 */
5280 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4d2cad32 5281 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
7b763f3f
FL		 5282 if (ret) {
5283 u64_stats_update_begin(&ring->syncp);
5284 ring->stats.sw_err_cnt++;
5285 u64_stats_update_end(&ring->syncp);
5286 /* if alloc new buffer fail, exit directly
5287 * and reclear in up flow.
5288 */
c8711956 5289 netdev_warn(ring_to_netdev(ring),
7b763f3f
FL		 5290 "reserve buffer map failed, ret = %d\n",
5291 ret);
5292 return ret;
5293 }
9b2f3477 5294 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
7b763f3f
FL		 5295 }
5296 ring_ptr_move_fw(ring, next_to_use);
5297 }
5298
cc5ff6e9
PL		 5299 /* Free the pending skb in rx ring */
5300 if (ring->skb) {
5301 dev_kfree_skb_any(ring->skb);
5302 ring->skb = NULL;
5303 ring->pending_buf = 0;
5304 }
5305
7b763f3f
FL		 5306 return 0;
5307}
5308
5309static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 5310{
beebca3a
YL		 5311 while (ring->next_to_use != ring->next_to_clean) {
5312 /* When a buffer is not reused, it's memory has been
5313 * freed in hns3_handle_rx_bd or will be freed by
5314 * stack, so only need to unmap the buffer here.
5315 */
5316 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5317 hns3_unmap_buffer(ring,
5318 &ring->desc_cb[ring->next_to_use]);
5319 ring->desc_cb[ring->next_to_use].dma = 0;
5320 }
5321
5322 ring_ptr_move_fw(ring, next_to_use);
5323 }
bb6b94a8
L		 5324}
5325
f96315f2 5326static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
bb6b94a8
L		 5327{
5328 struct net_device *ndev = h->kinfo.netdev;
5329 struct hns3_nic_priv *priv = netdev_priv(ndev);
5330 u32 i;
5331
5332 for (i = 0; i < h->kinfo.num_tqps; i++) {
bb6b94a8
L		 5333 struct hns3_enet_ring *ring;
5334
5f06b903 5335 ring = &priv->ring[i];
beebca3a 5336 hns3_clear_tx_ring(ring);
bb6b94a8 5337
5f06b903 5338 ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 5339 /* Continue to clear other rings even if clearing some
5340 * rings failed.
5341 */
f96315f2
HT		 5342 if (force)
5343 hns3_force_clear_rx_ring(ring);
5344 else
5345 hns3_clear_rx_ring(ring);
bb6b94a8
L		 5346 }
5347}
5348
7b763f3f
FL		 5349int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5350{
5351 struct net_device *ndev = h->kinfo.netdev;
5352 struct hns3_nic_priv *priv = netdev_priv(ndev);
5353 struct hns3_enet_ring *rx_ring;
5354 int i, j;
5355 int ret;
5356
8fa86551
YM		 5357 ret = h->ae_algo->ops->reset_queue(h);
5358 if (ret)
5359 return ret;
7fa6be4f 5360
8fa86551 5361 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903 5362 hns3_init_ring_hw(&priv->ring[i]);
7b763f3f
FL		 5363
5364 /* We need to clear tx ring here because self test will
5365 * use the ring and will not run down before up
5366 */
5f06b903
YL		 5367 hns3_clear_tx_ring(&priv->ring[i]);
5368 priv->ring[i].next_to_clean = 0;
5369 priv->ring[i].next_to_use = 0;
20d06ca2 5370 priv->ring[i].last_to_use = 0;
7b763f3f 5371
5f06b903 5372 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL		 5373 hns3_init_ring_hw(rx_ring);
5374 ret = hns3_clear_rx_ring(rx_ring);
5375 if (ret)
5376 return ret;
5377
5378 /* We can not know the hardware head and tail when this
5379 * function is called in reset flow, so we reuse all desc.
5380 */
5381 for (j = 0; j < rx_ring->desc_num; j++)
5382 hns3_reuse_buffer(rx_ring, j);
5383
5384 rx_ring->next_to_clean = 0;
5385 rx_ring->next_to_use = 0;
5386 }
5387
1c772154
YL		 5388 hns3_init_tx_ring_tc(priv);
5389
7b763f3f
FL		 5390 return 0;
5391}
5392
bb6b94a8
L		 5393static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5394{
5395 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5396 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 5397 struct hns3_nic_priv *priv = netdev_priv(ndev);
5398
5399 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5400 return 0;
bb6b94a8
L		 5401
5402 if (!netif_running(ndev))
6b1385cc 5403 return 0;
bb6b94a8
L		 5404
5405 return hns3_nic_net_stop(ndev);
5406}
5407
5408static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5409{
5410 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 5411 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 5412 int ret = 0;
5413
b4047aac
JS		 5414 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5415 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5416 return -EFAULT;
5417 }
5418
e8884027
HT		 5419 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5420
bb6b94a8 5421 if (netif_running(kinfo->netdev)) {
e8884027 5422 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 5423 if (ret) {
e8884027 5424 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8 5425 netdev_err(kinfo->netdev,
9b2f3477 5426 "net up fail, ret=%d!\n", ret);
bb6b94a8
L		 5427 return ret;
5428 }
bb6b94a8
L		 5429 }
5430
5431 return ret;
5432}
5433
5434static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5435{
5436 struct net_device *netdev = handle->kinfo.netdev;
5437 struct hns3_nic_priv *priv = netdev_priv(netdev);
5438 int ret;
5439
bb6b94a8
L		 5440 /* Carrier off reporting is important to ethtool even BEFORE open */
5441 netif_carrier_off(netdev);
5442
2c9dd668 5443 ret = hns3_get_ring_config(priv);
862d969a
HT		 5444 if (ret)
5445 return ret;
5446
2c9dd668
HT		 5447 ret = hns3_nic_alloc_vector_data(priv);
5448 if (ret)
5449 goto err_put_ring;
5450
bb6b94a8
L		 5451 ret = hns3_nic_init_vector_data(priv);
5452 if (ret)
862d969a 5453 goto err_dealloc_vector;
bb6b94a8
L		 5454
5455 ret = hns3_init_all_ring(priv);
862d969a
HT		 5456 if (ret)
5457 goto err_uninit_vector;
bb6b94a8 5458
9f0c6f4b
YM		 5459 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5460
08a10068
YL		 5461 /* the device can work without cpu rmap, only aRFS needs it */
5462 ret = hns3_set_rx_cpu_rmap(netdev);
5463 if (ret)
5464 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5465
5466 ret = hns3_nic_init_irq(priv);
5467 if (ret) {
5468 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5469 hns3_free_rx_cpu_rmap(netdev);
5470 goto err_init_irq_fail;
5471 }
5472
ee4bcd3b
JS		 5473 if (!hns3_is_phys_func(handle->pdev))
5474 hns3_init_mac_addr(netdev);
5475
cd513a69
HT		 5476 ret = hns3_client_start(handle);
5477 if (ret) {
5478 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
08a10068 5479 goto err_client_start_fail;
cd513a69
HT		 5480 }
5481
814da63c
HT		 5482 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5483
862d969a
HT		 5484 return ret;
5485
08a10068
YL		 5486err_client_start_fail:
5487 hns3_free_rx_cpu_rmap(netdev);
5488 hns3_nic_uninit_irq(priv);
5489err_init_irq_fail:
cd513a69 5490 hns3_uninit_all_ring(priv);
862d969a
HT		 5491err_uninit_vector:
5492 hns3_nic_uninit_vector_data(priv);
862d969a
HT		 5493err_dealloc_vector:
5494 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 5495err_put_ring:
5496 hns3_put_ring_config(priv);
862d969a 5497
bb6b94a8
L		 5498 return ret;
5499}
5500
5501static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5502{
5503 struct net_device *netdev = handle->kinfo.netdev;
5504 struct hns3_nic_priv *priv = netdev_priv(netdev);
bb6b94a8 5505
1eeb3367 5506 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT		 5507 netdev_warn(netdev, "already uninitialized\n");
5508 return 0;
5509 }
5510
08a10068
YL		 5511 hns3_free_rx_cpu_rmap(netdev);
5512 hns3_nic_uninit_irq(priv);
f96315f2
HT		 5513 hns3_clear_all_ring(handle, true);
5514 hns3_reset_tx_queue(priv->ae_handle);
bb6b94a8 5515
e2152785 5516 hns3_nic_uninit_vector_data(priv);
bb6b94a8 5517
08a10068 5518 hns3_nic_dealloc_vector_data(priv);
862d969a 5519
64749c9c 5520 hns3_uninit_all_ring(priv);
bb6b94a8 5521
2c9dd668 5522 hns3_put_ring_config(priv);
2c9dd668 5523
205238f4 5524 return 0;
bb6b94a8
L		 5525}
5526
5527static int hns3_reset_notify(struct hnae3_handle *handle,
5528 enum hnae3_reset_notify_type type)
5529{
5530 int ret = 0;
5531
5532 switch (type) {
5533 case HNAE3_UP_CLIENT:
e1586241
SM		 5534 ret = hns3_reset_notify_up_enet(handle);
5535 break;
bb6b94a8
L		 5536 case HNAE3_DOWN_CLIENT:
5537 ret = hns3_reset_notify_down_enet(handle);
5538 break;
5539 case HNAE3_INIT_CLIENT:
5540 ret = hns3_reset_notify_init_enet(handle);
5541 break;
5542 case HNAE3_UNINIT_CLIENT:
5543 ret = hns3_reset_notify_uninit_enet(handle);
5544 break;
5545 default:
5546 break;
5547 }
5548
5549 return ret;
5550}
5551
3a5a5f06
PL		 5552static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5553 bool rxfh_configured)
5554{
5555 int ret;
5556
5557 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5558 rxfh_configured);
5559 if (ret) {
5560 dev_err(&handle->pdev->dev,
5561 "Change tqp num(%u) fail.\n", new_tqp_num);
5562 return ret;
5563 }
5564
5565 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5566 if (ret)
5567 return ret;
5568
5569 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5570 if (ret)
5571 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5572
5573 return ret;
5574}
5575
09f2af64
PL		 5576int hns3_set_channels(struct net_device *netdev,
5577 struct ethtool_channels *ch)
5578{
09f2af64
PL		 5579 struct hnae3_handle *h = hns3_get_handle(netdev);
5580 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 5581 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 5582 u32 new_tqp_num = ch->combined_count;
5583 u16 org_tqp_num;
5584 int ret;
5585
44950d28
JS		 5586 if (hns3_nic_resetting(netdev))
5587 return -EBUSY;
5588
09f2af64
PL		 5589 if (ch->rx_count || ch->tx_count)
5590 return -EINVAL;
5591
5a5c9091
JS		 5592 if (kinfo->tc_info.mqprio_active) {
5593 dev_err(&netdev->dev,
5594 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5595 return -EINVAL;
5596 }
5597
678335a1 5598 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 5599 new_tqp_num < 1) {
09f2af64 5600 dev_err(&netdev->dev,
adcf738b 5601 "Change tqps fail, the tqp range is from 1 to %u",
678335a1 5602 hns3_get_max_available_channels(h));
09f2af64
PL		 5603 return -EINVAL;
5604 }
5605
c78b5b6c 5606 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 5607 return 0;
5608
1c822948
YL		 5609 netif_dbg(h, drv, netdev,
5610 "set channels: tqp_num=%u, rxfh=%d\n",
5611 new_tqp_num, rxfh_configured);
5612
65749f73
HT		 5613 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5614 if (ret)
5615 return ret;
dd38c726 5616
65749f73
HT		 5617 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5618 if (ret)
5619 return ret;
09f2af64
PL		 5620
5621 org_tqp_num = h->kinfo.num_tqps;
3a5a5f06 5622 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
09f2af64 5623 if (ret) {
3a5a5f06
PL		 5624 int ret1;
5625
5626 netdev_warn(netdev,
5627 "Change channels fail, revert to old value\n");
5628 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5629 if (ret1) {
5630 netdev_err(netdev,
5631 "revert to old channel fail\n");
5632 return ret1;
09f2af64 5633 }
3a5a5f06 5634
65749f73 5635 return ret;
3a5a5f06 5636 }
09f2af64 5637
3a5a5f06 5638 return 0;
09f2af64
PL		 5639}
5640
a83d2961
WL		 5641static const struct hns3_hw_error_info hns3_hw_err[] = {
5642 { .type = HNAE3_PPU_POISON_ERROR,
5643 .msg = "PPU poison" },
5644 { .type = HNAE3_CMDQ_ECC_ERROR,
5645 .msg = "IMP CMDQ error" },
5646 { .type = HNAE3_IMP_RD_POISON_ERROR,
5647 .msg = "IMP RD poison" },
6cd131dd
YM		 5648 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
5649 .msg = "ROCEE AXI RESP error" },
a83d2961
WL		 5650};
5651
5652static void hns3_process_hw_error(struct hnae3_handle *handle,
5653 enum hnae3_hw_error_type type)
5654{
5655 int i;
5656
5657 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
5658 if (hns3_hw_err[i].type == type) {
5659 dev_err(&handle->pdev->dev, "Detected %s!\n",
5660 hns3_hw_err[i].msg);
5661 break;
5662 }
5663 }
5664}
5665
1db9b1bf 5666static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 5667 .init_instance = hns3_client_init,
5668 .uninit_instance = hns3_client_uninit,
5669 .link_status_change = hns3_link_status_change,
bb6b94a8 5670 .reset_notify = hns3_reset_notify,
a83d2961 5671 .process_hw_error = hns3_process_hw_error,
76ad4f0e
S		 5672};
5673
5674/* hns3_init_module - Driver registration routine
5675 * hns3_init_module is the first routine called when the driver is
5676 * loaded. All it does is register with the PCI subsystem.
5677 */
5678static int __init hns3_init_module(void)
5679{
5680 int ret;
5681
5682 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
5683 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
5684
5685 client.type = HNAE3_CLIENT_KNIC;
cdc37385 5686 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
76ad4f0e
S		 5687 hns3_driver_name);
5688
5689 client.ops = &client_ops;
5690
13562d1f
XW		 5691 INIT_LIST_HEAD(&client.node);
5692
b2292360 5693 hns3_dbg_register_debugfs(hns3_driver_name);
5694
76ad4f0e
S		 5695 ret = hnae3_register_client(&client);
5696 if (ret)
b2292360 5697 goto err_reg_client;
76ad4f0e
S		 5698
5699 ret = pci_register_driver(&hns3_driver);
5700 if (ret)
b2292360 5701 goto err_reg_driver;
76ad4f0e
S		 5702
5703 return ret;
b2292360 5704
5705err_reg_driver:
5706 hnae3_unregister_client(&client);
5707err_reg_client:
5708 hns3_dbg_unregister_debugfs();
5709 return ret;
76ad4f0e
S		 5710}
5711module_init(hns3_init_module);
5712
5713/* hns3_exit_module - Driver exit cleanup routine
5714 * hns3_exit_module is called just before the driver is removed
5715 * from memory.
5716 */
5717static void __exit hns3_exit_module(void)
5718{
5719 pci_unregister_driver(&hns3_driver);
5720 hnae3_unregister_client(&client);
b2292360 5721 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 5722}
5723module_exit(hns3_exit_module);
5724
5725MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
5726MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5727MODULE_LICENSE("GPL");
5728MODULE_ALIAS("pci:hns-nic");
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