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net: hns3: pad the short frame before sending to the hardware
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
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1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
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3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
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7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
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10#include <linux/if_vlan.h>
11#include <linux/ip.h>
12#include <linux/ipv6.h>
13#include <linux/module.h>
14#include <linux/pci.h>
6ae4e733 15#include <linux/aer.h>
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16#include <linux/skbuff.h>
17#include <linux/sctp.h>
18#include <linux/vermagic.h>
19#include <net/gre.h>
e2ee1c5a 20#include <net/ip6_checksum.h>
30d240df 21#include <net/pkt_cls.h>
a6d53b97 22#include <net/tcp.h>
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23#include <net/vxlan.h>
24
25#include "hnae3.h"
26#include "hns3_enet.h"
27
cde4ffad 28#define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
5f543a54 29#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 30
f96315f2 31static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
f05e2109 32static void hns3_remove_hw_addr(struct net_device *netdev);
7b763f3f 33
1db9b1bf 34static const char hns3_driver_name[] = "hns3";
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35const char hns3_driver_version[] = VERMAGIC_STRING;
36static const char hns3_driver_string[] =
37 "Hisilicon Ethernet Network Driver for Hip08 Family";
38static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
39static struct hnae3_client client;
40
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YL
41static int debug = -1;
42module_param(debug, int, 0);
43MODULE_PARM_DESC(debug, " Network interface message level setting");
44
45#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
46 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
47
39d592aa
YL
48#define HNS3_MIN_TX_LEN 33U
49
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50/* hns3_pci_tbl - PCI Device ID Table
51 *
52 * Last entry must be all 0s
53 *
54 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
55 * Class, Class Mask, private data (not used) }
56 */
57static const struct pci_device_id hns3_pci_tbl[] = {
58 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
59 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 60 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 61 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 62 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 63 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 64 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 65 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 66 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 67 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 68 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 69 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834 70 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
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71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
72 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
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73 /* required last entry */
74 {0, }
75};
76MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
77
ef0c5009 78static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 79{
ef0c5009 80 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 81
fb00331b 82 napi_schedule_irqoff(&tqp_vector->napi);
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83
84 return IRQ_HANDLED;
85}
86
87static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
88{
89 struct hns3_enet_tqp_vector *tqp_vectors;
90 unsigned int i;
91
92 for (i = 0; i < priv->vector_num; i++) {
93 tqp_vectors = &priv->tqp_vector[i];
94
95 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
96 continue;
97
ffab9691 98 /* clear the affinity mask */
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PL
99 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
100
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101 /* release the irq resource */
102 free_irq(tqp_vectors->vector_irq, tqp_vectors);
103 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
104 }
105}
106
107static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
108{
109 struct hns3_enet_tqp_vector *tqp_vectors;
110 int txrx_int_idx = 0;
111 int rx_int_idx = 0;
112 int tx_int_idx = 0;
113 unsigned int i;
114 int ret;
115
116 for (i = 0; i < priv->vector_num; i++) {
117 tqp_vectors = &priv->tqp_vector[i];
118
119 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
120 continue;
121
122 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
123 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
124 "%s-%s-%d", priv->netdev->name, "TxRx",
125 txrx_int_idx++);
126 txrx_int_idx++;
127 } else if (tqp_vectors->rx_group.ring) {
128 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
129 "%s-%s-%d", priv->netdev->name, "Rx",
130 rx_int_idx++);
131 } else if (tqp_vectors->tx_group.ring) {
132 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
133 "%s-%s-%d", priv->netdev->name, "Tx",
134 tx_int_idx++);
135 } else {
136 /* Skip this unused q_vector */
137 continue;
138 }
139
140 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
141
142 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
9b2f3477 143 tqp_vectors->name, tqp_vectors);
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144 if (ret) {
145 netdev_err(priv->netdev, "request irq(%d) fail\n",
146 tqp_vectors->vector_irq);
d547ecdc 147 hns3_nic_uninit_irq(priv);
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148 return ret;
149 }
150
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PL
151 irq_set_affinity_hint(tqp_vectors->vector_irq,
152 &tqp_vectors->affinity_mask);
153
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154 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
155 }
156
157 return 0;
158}
159
160static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
161 u32 mask_en)
162{
163 writel(mask_en, tqp_vector->mask_addr);
164}
165
166static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
167{
168 napi_enable(&tqp_vector->napi);
169
170 /* enable vector */
171 hns3_mask_vector_irq(tqp_vector, 1);
172}
173
174static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
175{
176 /* disable vector */
177 hns3_mask_vector_irq(tqp_vector, 0);
178
179 disable_irq(tqp_vector->vector_irq);
180 napi_disable(&tqp_vector->napi);
181}
182
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183void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
184 u32 rl_value)
76ad4f0e 185{
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FL
186 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
187
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188 /* this defines the configuration for RL (Interrupt Rate Limiter).
189 * Rl defines rate of interrupts i.e. number of interrupts-per-second
190 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
191 */
434776a5 192
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193 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
194 !tqp_vector->rx_group.coal.gl_adapt_enable)
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195 /* According to the hardware, the range of rl_reg is
196 * 0-59 and the unit is 4.
197 */
198 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
199
200 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
201}
202
203void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
204 u32 gl_value)
205{
206 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
207
208 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
209}
210
211void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
212 u32 gl_value)
213{
214 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
215
216 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
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217}
218
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FL
219static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
220 struct hns3_nic_priv *priv)
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221{
222 /* initialize the configuration for interrupt coalescing.
223 * 1. GL (Interrupt Gap Limiter)
224 * 2. RL (Interrupt Rate Limiter)
225 */
226
5fd4789a 227 /* Default: enable interrupt coalescing self-adaptive and GL */
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228 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
229 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 230
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231 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
232 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 233
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234 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
235 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
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236}
237
dd38c726
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238static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
239 struct hns3_nic_priv *priv)
240{
241 struct hnae3_handle *h = priv->ae_handle;
242
243 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 244 tqp_vector->tx_group.coal.int_gl);
dd38c726 245 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 246 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL
247 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
248}
249
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250static int hns3_nic_set_real_num_queue(struct net_device *netdev)
251{
9780cb97 252 struct hnae3_handle *h = hns3_get_handle(netdev);
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253 struct hnae3_knic_private_info *kinfo = &h->kinfo;
254 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
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255 int i, ret;
256
257 if (kinfo->num_tc <= 1) {
258 netdev_reset_tc(netdev);
259 } else {
260 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
261 if (ret) {
262 netdev_err(netdev,
263 "netdev_set_num_tc fail, ret=%d!\n", ret);
264 return ret;
265 }
266
267 for (i = 0; i < HNAE3_MAX_TC; i++) {
268 if (!kinfo->tc_info[i].enable)
269 continue;
270
271 netdev_set_tc_queue(netdev,
272 kinfo->tc_info[i].tc,
273 kinfo->tc_info[i].tqp_count,
274 kinfo->tc_info[i].tqp_offset);
275 }
276 }
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YL
277
278 ret = netif_set_real_num_tx_queues(netdev, queue_size);
279 if (ret) {
280 netdev_err(netdev,
9b2f3477 281 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
9df8f79a
YL
282 return ret;
283 }
284
285 ret = netif_set_real_num_rx_queues(netdev, queue_size);
286 if (ret) {
287 netdev_err(netdev,
288 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
289 return ret;
290 }
291
292 return 0;
293}
294
678335a1
PL
295static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
296{
0d43bf45 297 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 298
0d43bf45
HT
299 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
300 rss_size = alloc_tqps / h->kinfo.num_tc;
678335a1 301
0d43bf45 302 return min_t(u16, rss_size, max_rss_size);
678335a1
PL
303}
304
8df0fa91
HT
305static void hns3_tqp_enable(struct hnae3_queue *tqp)
306{
307 u32 rcb_reg;
308
309 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
310 rcb_reg |= BIT(HNS3_RING_EN_B);
311 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
312}
313
314static void hns3_tqp_disable(struct hnae3_queue *tqp)
315{
316 u32 rcb_reg;
317
318 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
319 rcb_reg &= ~BIT(HNS3_RING_EN_B);
320 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
321}
322
ffab9691
JS
323static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
324{
325#ifdef CONFIG_RFS_ACCEL
326 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
327 netdev->rx_cpu_rmap = NULL;
328#endif
329}
330
331static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
332{
333#ifdef CONFIG_RFS_ACCEL
334 struct hns3_nic_priv *priv = netdev_priv(netdev);
335 struct hns3_enet_tqp_vector *tqp_vector;
336 int i, ret;
337
338 if (!netdev->rx_cpu_rmap) {
339 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
340 if (!netdev->rx_cpu_rmap)
341 return -ENOMEM;
342 }
343
344 for (i = 0; i < priv->vector_num; i++) {
345 tqp_vector = &priv->tqp_vector[i];
346 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
347 tqp_vector->vector_irq);
348 if (ret) {
349 hns3_free_rx_cpu_rmap(netdev);
350 return ret;
351 }
352 }
353#endif
354 return 0;
355}
356
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357static int hns3_nic_net_up(struct net_device *netdev)
358{
359 struct hns3_nic_priv *priv = netdev_priv(netdev);
360 struct hnae3_handle *h = priv->ae_handle;
361 int i, j;
362 int ret;
363
7b763f3f
FL
364 ret = hns3_nic_reset_all_ring(h);
365 if (ret)
366 return ret;
367
ffab9691
JS
368 /* the device can work without cpu rmap, only aRFS needs it */
369 ret = hns3_set_rx_cpu_rmap(netdev);
370 if (ret)
371 netdev_warn(netdev, "set rx cpu rmap fail, ret=%d!\n", ret);
372
76ad4f0e
S
373 /* get irq resource for all vectors */
374 ret = hns3_nic_init_irq(priv);
375 if (ret) {
9b2f3477 376 netdev_err(netdev, "init irq failed! ret=%d\n", ret);
ffab9691 377 goto free_rmap;
76ad4f0e
S
378 }
379
b7b585c2
JS
380 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
381
76ad4f0e
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382 /* enable the vectors */
383 for (i = 0; i < priv->vector_num; i++)
384 hns3_vector_enable(&priv->tqp_vector[i]);
385
8df0fa91
HT
386 /* enable rcb */
387 for (j = 0; j < h->kinfo.num_tqps; j++)
388 hns3_tqp_enable(h->kinfo.tqp[j]);
389
76ad4f0e
S
390 /* start the ae_dev */
391 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
392 if (ret)
393 goto out_start_err;
394
395 return 0;
396
397out_start_err:
b7b585c2 398 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
8df0fa91
HT
399 while (j--)
400 hns3_tqp_disable(h->kinfo.tqp[j]);
401
76ad4f0e
S
402 for (j = i - 1; j >= 0; j--)
403 hns3_vector_disable(&priv->tqp_vector[j]);
404
405 hns3_nic_uninit_irq(priv);
ffab9691
JS
406free_rmap:
407 hns3_free_rx_cpu_rmap(netdev);
76ad4f0e
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408 return ret;
409}
410
2a73ac3e
YL
411static void hns3_config_xps(struct hns3_nic_priv *priv)
412{
413 int i;
414
415 for (i = 0; i < priv->vector_num; i++) {
416 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
417 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
418
419 while (ring) {
420 int ret;
421
422 ret = netif_set_xps_queue(priv->netdev,
423 &tqp_vector->affinity_mask,
424 ring->tqp->tqp_index);
425 if (ret)
426 netdev_warn(priv->netdev,
427 "set xps queue failed: %d", ret);
428
429 ring = ring->next;
430 }
431 }
432}
433
76ad4f0e
S
434static int hns3_nic_net_open(struct net_device *netdev)
435{
8cdb992f 436 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL
437 struct hnae3_handle *h = hns3_get_handle(netdev);
438 struct hnae3_knic_private_info *kinfo;
439 int i, ret;
76ad4f0e 440
257e4f29
HT
441 if (hns3_nic_resetting(netdev))
442 return -EBUSY;
443
76ad4f0e
S
444 netif_carrier_off(netdev);
445
9df8f79a
YL
446 ret = hns3_nic_set_real_num_queue(netdev);
447 if (ret)
76ad4f0e 448 return ret;
76ad4f0e
S
449
450 ret = hns3_nic_net_up(netdev);
451 if (ret) {
9b2f3477 452 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
76ad4f0e
S
453 return ret;
454 }
455
a75a8efa 456 kinfo = &h->kinfo;
9b2f3477
WL
457 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
458 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
a75a8efa 459
8cdb992f
JS
460 if (h->ae_algo->ops->set_timer_task)
461 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
462
2a73ac3e 463 hns3_config_xps(priv);
76ad4f0e
S
464 return 0;
465}
466
f96315f2
HT
467static void hns3_reset_tx_queue(struct hnae3_handle *h)
468{
469 struct net_device *ndev = h->kinfo.netdev;
470 struct hns3_nic_priv *priv = netdev_priv(ndev);
471 struct netdev_queue *dev_queue;
472 u32 i;
473
474 for (i = 0; i < h->kinfo.num_tqps; i++) {
475 dev_queue = netdev_get_tx_queue(ndev,
476 priv->ring_data[i].queue_index);
477 netdev_tx_reset_queue(dev_queue);
478 }
479}
480
76ad4f0e
S
481static void hns3_nic_net_down(struct net_device *netdev)
482{
483 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 484 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
485 const struct hnae3_ae_ops *ops;
486 int i;
487
7b763f3f
FL
488 /* disable vectors */
489 for (i = 0; i < priv->vector_num; i++)
490 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT
491
492 /* disable rcb */
493 for (i = 0; i < h->kinfo.num_tqps; i++)
494 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 495
76ad4f0e
S
496 /* stop ae_dev */
497 ops = priv->ae_handle->ae_algo->ops;
498 if (ops->stop)
499 ops->stop(priv->ae_handle);
500
ffab9691
JS
501 hns3_free_rx_cpu_rmap(netdev);
502
76ad4f0e
S
503 /* free irq resources */
504 hns3_nic_uninit_irq(priv);
7b763f3f 505
3a30964a
YL
506 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
507 * during reset process, because driver may not be able
508 * to disable the ring through firmware when downing the netdev.
509 */
510 if (!hns3_nic_resetting(netdev))
f96315f2
HT
511 hns3_clear_all_ring(priv->ae_handle, false);
512
513 hns3_reset_tx_queue(priv->ae_handle);
76ad4f0e
S
514}
515
516static int hns3_nic_net_stop(struct net_device *netdev)
517{
ff0699e0 518 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 519 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT
520
521 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
522 return 0;
523
8cdb992f
JS
524 if (h->ae_algo->ops->set_timer_task)
525 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
526
76ad4f0e
S
527 netif_tx_stop_all_queues(netdev);
528 netif_carrier_off(netdev);
529
530 hns3_nic_net_down(netdev);
531
532 return 0;
533}
534
76ad4f0e
S
535static int hns3_nic_uc_sync(struct net_device *netdev,
536 const unsigned char *addr)
537{
9780cb97 538 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
539
540 if (h->ae_algo->ops->add_uc_addr)
541 return h->ae_algo->ops->add_uc_addr(h, addr);
542
543 return 0;
544}
545
546static int hns3_nic_uc_unsync(struct net_device *netdev,
547 const unsigned char *addr)
548{
9780cb97 549 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
550
551 if (h->ae_algo->ops->rm_uc_addr)
552 return h->ae_algo->ops->rm_uc_addr(h, addr);
553
554 return 0;
555}
556
557static int hns3_nic_mc_sync(struct net_device *netdev,
558 const unsigned char *addr)
559{
9780cb97 560 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 561
720a8478 562 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S
563 return h->ae_algo->ops->add_mc_addr(h, addr);
564
565 return 0;
566}
567
568static int hns3_nic_mc_unsync(struct net_device *netdev,
569 const unsigned char *addr)
570{
9780cb97 571 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 572
720a8478 573 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S
574 return h->ae_algo->ops->rm_mc_addr(h, addr);
575
576 return 0;
577}
578
c60edc17
JS
579static u8 hns3_get_netdev_flags(struct net_device *netdev)
580{
581 u8 flags = 0;
582
583 if (netdev->flags & IFF_PROMISC) {
28673b33 584 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
c60edc17
JS
585 } else {
586 flags |= HNAE3_VLAN_FLTR;
587 if (netdev->flags & IFF_ALLMULTI)
588 flags |= HNAE3_USER_MPE;
589 }
590
591 return flags;
592}
593
1db9b1bf 594static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 595{
9780cb97 596 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17
JS
597 u8 new_flags;
598 int ret;
76ad4f0e 599
c60edc17
JS
600 new_flags = hns3_get_netdev_flags(netdev);
601
602 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
603 if (ret) {
76ad4f0e 604 netdev_err(netdev, "sync uc address fail\n");
c60edc17
JS
605 if (ret == -ENOSPC)
606 new_flags |= HNAE3_OVERFLOW_UPE;
607 }
608
40cca1c5 609 if (netdev->flags & IFF_MULTICAST) {
c60edc17
JS
610 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
611 hns3_nic_mc_unsync);
612 if (ret) {
76ad4f0e 613 netdev_err(netdev, "sync mc address fail\n");
c60edc17
JS
614 if (ret == -ENOSPC)
615 new_flags |= HNAE3_OVERFLOW_MPE;
616 }
617 }
618
c60edc17
JS
619 /* User mode Promisc mode enable and vlan filtering is disabled to
620 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
621 * vlan fitering is enabled
622 */
623 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
624 h->netdev_flags = new_flags;
28673b33 625 hns3_update_promisc_mode(netdev, new_flags);
c60edc17
JS
626}
627
7fa6be4f 628int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
c60edc17
JS
629{
630 struct hns3_nic_priv *priv = netdev_priv(netdev);
631 struct hnae3_handle *h = priv->ae_handle;
632
633 if (h->ae_algo->ops->set_promisc_mode) {
7fa6be4f
HT
634 return h->ae_algo->ops->set_promisc_mode(h,
635 promisc_flags & HNAE3_UPE,
636 promisc_flags & HNAE3_MPE);
c60edc17 637 }
7fa6be4f
HT
638
639 return 0;
c60edc17
JS
640}
641
642void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
643{
644 struct hns3_nic_priv *priv = netdev_priv(netdev);
645 struct hnae3_handle *h = priv->ae_handle;
646 bool last_state;
647
648 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
649 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
650 if (enable != last_state) {
651 netdev_info(netdev,
652 "%s vlan filter\n",
653 enable ? "enable" : "disable");
654 h->ae_algo->ops->enable_vlan_filter(h, enable);
655 }
40cca1c5 656 }
76ad4f0e
S
657}
658
659static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
660 u16 *mss, u32 *type_cs_vlan_tso)
661{
662 u32 l4_offset, hdr_len;
663 union l3_hdr_info l3;
664 union l4_hdr_info l4;
665 u32 l4_paylen;
666 int ret;
667
668 if (!skb_is_gso(skb))
669 return 0;
670
671 ret = skb_cow_head(skb, 0);
0cccebac 672 if (unlikely(ret))
76ad4f0e
S
673 return ret;
674
675 l3.hdr = skb_network_header(skb);
676 l4.hdr = skb_transport_header(skb);
677
678 /* Software should clear the IPv4's checksum field when tso is
679 * needed.
680 */
681 if (l3.v4->version == 4)
682 l3.v4->check = 0;
683
9b2f3477 684 /* tunnel packet */
76ad4f0e
S
685 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
686 SKB_GSO_GRE_CSUM |
687 SKB_GSO_UDP_TUNNEL |
688 SKB_GSO_UDP_TUNNEL_CSUM)) {
689 if ((!(skb_shinfo(skb)->gso_type &
690 SKB_GSO_PARTIAL)) &&
691 (skb_shinfo(skb)->gso_type &
692 SKB_GSO_UDP_TUNNEL_CSUM)) {
693 /* Software should clear the udp's checksum
694 * field when tso is needed.
695 */
696 l4.udp->check = 0;
697 }
698 /* reset l3&l4 pointers from outer to inner headers */
699 l3.hdr = skb_inner_network_header(skb);
700 l4.hdr = skb_inner_transport_header(skb);
701
702 /* Software should clear the IPv4's checksum field when
703 * tso is needed.
704 */
705 if (l3.v4->version == 4)
706 l3.v4->check = 0;
707 }
708
9b2f3477 709 /* normal or tunnel packet */
76ad4f0e 710 l4_offset = l4.hdr - skb->data;
3fe13ed9 711 hdr_len = (l4.tcp->doff << 2) + l4_offset;
76ad4f0e 712
9b2f3477 713 /* remove payload length from inner pseudo checksum when tso */
76ad4f0e
S
714 l4_paylen = skb->len - l4_offset;
715 csum_replace_by_diff(&l4.tcp->check,
716 (__force __wsum)htonl(l4_paylen));
717
718 /* find the txbd field values */
719 *paylen = skb->len - hdr_len;
cde4ffad 720 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e
S
721
722 /* get MSS for TSO */
723 *mss = skb_shinfo(skb)->gso_size;
724
725 return 0;
726}
727
1898d4e4
S
728static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
729 u8 *il4_proto)
76ad4f0e 730{
1a6e552d 731 union l3_hdr_info l3;
76ad4f0e
S
732 unsigned char *l4_hdr;
733 unsigned char *exthdr;
734 u8 l4_proto_tmp;
735 __be16 frag_off;
736
737 /* find outer header point */
738 l3.hdr = skb_network_header(skb);
35f58fd7 739 l4_hdr = skb_transport_header(skb);
76ad4f0e
S
740
741 if (skb->protocol == htons(ETH_P_IPV6)) {
742 exthdr = l3.hdr + sizeof(*l3.v6);
743 l4_proto_tmp = l3.v6->nexthdr;
744 if (l4_hdr != exthdr)
745 ipv6_skip_exthdr(skb, exthdr - skb->data,
746 &l4_proto_tmp, &frag_off);
747 } else if (skb->protocol == htons(ETH_P_IP)) {
748 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S
749 } else {
750 return -EINVAL;
76ad4f0e
S
751 }
752
753 *ol4_proto = l4_proto_tmp;
754
755 /* tunnel packet */
756 if (!skb->encapsulation) {
757 *il4_proto = 0;
1898d4e4 758 return 0;
76ad4f0e
S
759 }
760
761 /* find inner header point */
762 l3.hdr = skb_inner_network_header(skb);
763 l4_hdr = skb_inner_transport_header(skb);
764
765 if (l3.v6->version == 6) {
766 exthdr = l3.hdr + sizeof(*l3.v6);
767 l4_proto_tmp = l3.v6->nexthdr;
768 if (l4_hdr != exthdr)
769 ipv6_skip_exthdr(skb, exthdr - skb->data,
770 &l4_proto_tmp, &frag_off);
771 } else if (l3.v4->version == 4) {
772 l4_proto_tmp = l3.v4->protocol;
773 }
774
775 *il4_proto = l4_proto_tmp;
1898d4e4
S
776
777 return 0;
76ad4f0e
S
778}
779
3db084d2
YL
780/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
781 * and it is udp packet, which has a dest port as the IANA assigned.
782 * the hardware is expected to do the checksum offload, but the
783 * hardware will not do the checksum offload when udp dest port is
784 * 4789.
785 */
786static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
787{
1a6e552d 788 union l4_hdr_info l4;
3db084d2
YL
789
790 l4.hdr = skb_transport_header(skb);
791
bea96410
MS
792 if (!(!skb->encapsulation &&
793 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
3db084d2
YL
794 return false;
795
796 skb_checksum_help(skb);
797
798 return true;
799}
800
757cd1e4
YL
801static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
802 u32 *ol_type_vlan_len_msec)
76ad4f0e 803{
757cd1e4
YL
804 u32 l2_len, l3_len, l4_len;
805 unsigned char *il2_hdr;
1a6e552d 806 union l3_hdr_info l3;
757cd1e4 807 union l4_hdr_info l4;
76ad4f0e
S
808
809 l3.hdr = skb_network_header(skb);
757cd1e4 810 l4.hdr = skb_transport_header(skb);
76ad4f0e 811
757cd1e4
YL
812 /* compute OL2 header size, defined in 2 Bytes */
813 l2_len = l3.hdr - skb->data;
814 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
815
816 /* compute OL3 header size, defined in 4 Bytes */
817 l3_len = l4.hdr - l3.hdr;
818 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 819
757cd1e4 820 il2_hdr = skb_inner_mac_header(skb);
9b2f3477 821 /* compute OL4 header size, defined in 4 Bytes */
757cd1e4
YL
822 l4_len = il2_hdr - l4.hdr;
823 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
824
825 /* define outer network header type */
826 if (skb->protocol == htons(ETH_P_IP)) {
827 if (skb_is_gso(skb))
cde4ffad 828 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL
829 HNS3_TXD_OL3T_S,
830 HNS3_OL3T_IPV4_CSUM);
831 else
cde4ffad 832 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL
833 HNS3_TXD_OL3T_S,
834 HNS3_OL3T_IPV4_NO_CSUM);
835
836 } else if (skb->protocol == htons(ETH_P_IPV6)) {
837 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
838 HNS3_OL3T_IPV6);
839 }
840
841 if (ol4_proto == IPPROTO_UDP)
842 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
843 HNS3_TUN_MAC_IN_UDP);
844 else if (ol4_proto == IPPROTO_GRE)
845 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
846 HNS3_TUN_NVGRE);
847}
848
849static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
850 u8 il4_proto, u32 *type_cs_vlan_tso,
851 u32 *ol_type_vlan_len_msec)
852{
c264ed44 853 unsigned char *l2_hdr = skb->data;
757cd1e4
YL
854 u32 l4_proto = ol4_proto;
855 union l4_hdr_info l4;
856 union l3_hdr_info l3;
857 u32 l2_len, l3_len;
858
859 l4.hdr = skb_transport_header(skb);
860 l3.hdr = skb_network_header(skb);
861
862 /* handle encapsulation skb */
863 if (skb->encapsulation) {
864 /* If this is a not UDP/GRE encapsulation skb */
865 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S
866 /* drop the skb tunnel packet if hardware don't support,
867 * because hardware can't calculate csum when TSO.
868 */
869 if (skb_is_gso(skb))
870 return -EDOM;
871
872 /* the stack computes the IP header already,
873 * driver calculate l4 checksum when not TSO.
874 */
875 skb_checksum_help(skb);
876 return 0;
877 }
878
757cd1e4
YL
879 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
880
881 /* switch to inner header */
882 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 883 l3.hdr = skb_inner_network_header(skb);
757cd1e4 884 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S
885 l4_proto = il4_proto;
886 }
887
888 if (l3.v4->version == 4) {
cde4ffad
YL
889 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
890 HNS3_L3T_IPV4);
76ad4f0e
S
891
892 /* the stack computes the IP header already, the only time we
893 * need the hardware to recompute it is in the case of TSO.
894 */
895 if (skb_is_gso(skb))
cde4ffad 896 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 897 } else if (l3.v6->version == 6) {
cde4ffad
YL
898 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
899 HNS3_L3T_IPV6);
76ad4f0e
S
900 }
901
757cd1e4
YL
902 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
903 l2_len = l3.hdr - l2_hdr;
904 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
905
906 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
907 l3_len = l4.hdr - l3.hdr;
908 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
909
910 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S
911 switch (l4_proto) {
912 case IPPROTO_TCP:
cde4ffad
YL
913 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
914 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
915 HNS3_L4T_TCP);
757cd1e4
YL
916 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
917 l4.tcp->doff);
76ad4f0e
S
918 break;
919 case IPPROTO_UDP:
3db084d2
YL
920 if (hns3_tunnel_csum_bug(skb))
921 break;
922
cde4ffad
YL
923 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
924 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
925 HNS3_L4T_UDP);
757cd1e4
YL
926 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
927 (sizeof(struct udphdr) >> 2));
76ad4f0e
S
928 break;
929 case IPPROTO_SCTP:
cde4ffad
YL
930 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
931 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
932 HNS3_L4T_SCTP);
757cd1e4
YL
933 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
934 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S
935 break;
936 default:
937 /* drop the skb tunnel packet if hardware don't support,
938 * because hardware can't calculate csum when TSO.
939 */
940 if (skb_is_gso(skb))
941 return -EDOM;
942
943 /* the stack computes the IP header already,
944 * driver calculate l4 checksum when not TSO.
945 */
946 skb_checksum_help(skb);
947 return 0;
948 }
949
950 return 0;
951}
952
953static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
954{
955 /* Config bd buffer end */
b9a8f883
YL
956 if (!!frag_end)
957 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, 1U);
958 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1U);
76ad4f0e
S
959}
960
9699cffe
PL
961static int hns3_fill_desc_vtags(struct sk_buff *skb,
962 struct hns3_enet_ring *tx_ring,
963 u32 *inner_vlan_flag,
964 u32 *out_vlan_flag,
965 u16 *inner_vtag,
966 u16 *out_vtag)
967{
968#define HNS3_TX_VLAN_PRIO_SHIFT 13
969
44e626f7
JS
970 struct hnae3_handle *handle = tx_ring->tqp->handle;
971
972 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
973 * header is allowed in skb, otherwise it will cause RAS error.
974 */
975 if (unlikely(skb_vlan_tagged_multi(skb) &&
976 handle->port_base_vlan_state ==
977 HNAE3_PORT_BASE_VLAN_ENABLE))
978 return -EINVAL;
979
9699cffe
PL
980 if (skb->protocol == htons(ETH_P_8021Q) &&
981 !(tx_ring->tqp->handle->kinfo.netdev->features &
982 NETIF_F_HW_VLAN_CTAG_TX)) {
983 /* When HW VLAN acceleration is turned off, and the stack
984 * sets the protocol to 802.1q, the driver just need to
985 * set the protocol to the encapsulated ethertype.
986 */
987 skb->protocol = vlan_get_protocol(skb);
988 return 0;
989 }
990
991 if (skb_vlan_tag_present(skb)) {
992 u16 vlan_tag;
993
994 vlan_tag = skb_vlan_tag_get(skb);
995 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
996
997 /* Based on hw strategy, use out_vtag in two layer tag case,
998 * and use inner_vtag in one tag case.
999 */
1000 if (skb->protocol == htons(ETH_P_8021Q)) {
44e626f7
JS
1001 if (handle->port_base_vlan_state ==
1002 HNAE3_PORT_BASE_VLAN_DISABLE){
1003 hns3_set_field(*out_vlan_flag,
1004 HNS3_TXD_OVLAN_B, 1);
1005 *out_vtag = vlan_tag;
1006 } else {
1007 hns3_set_field(*inner_vlan_flag,
1008 HNS3_TXD_VLAN_B, 1);
1009 *inner_vtag = vlan_tag;
1010 }
9699cffe 1011 } else {
cde4ffad 1012 hns3_set_field(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
9699cffe
PL
1013 *inner_vtag = vlan_tag;
1014 }
1015 } else if (skb->protocol == htons(ETH_P_8021Q)) {
1016 struct vlan_ethhdr *vhdr;
1017 int rc;
1018
1019 rc = skb_cow_head(skb, 0);
0cccebac 1020 if (unlikely(rc < 0))
9699cffe
PL
1021 return rc;
1022 vhdr = (struct vlan_ethhdr *)skb->data;
1023 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1024 << HNS3_TX_VLAN_PRIO_SHIFT);
1025 }
1026
1027 skb->protocol = vlan_get_protocol(skb);
1028 return 0;
1029}
1030
76ad4f0e 1031static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
ebaf1908
WL
1032 unsigned int size, int frag_end,
1033 enum hns_desc_type type)
76ad4f0e
S
1034{
1035 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1036 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1037 struct device *dev = ring_to_dev(ring);
5188f218 1038 struct skb_frag_struct *frag;
1e8a7977 1039 unsigned int frag_buf_num;
47e7b13b 1040 int k, sizeoflast;
5188f218 1041 dma_addr_t dma;
76ad4f0e 1042
76ad4f0e 1043 if (type == DESC_TYPE_SKB) {
47e7b13b
YL
1044 struct sk_buff *skb = (struct sk_buff *)priv;
1045 u32 ol_type_vlan_len_msec = 0;
1046 u32 type_cs_vlan_tso = 0;
1047 u32 paylen = skb->len;
1048 u16 inner_vtag = 0;
1049 u16 out_vtag = 0;
1050 u16 mss = 0;
1051 int ret;
76ad4f0e 1052
9699cffe
PL
1053 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1054 &ol_type_vlan_len_msec,
1055 &inner_vtag, &out_vtag);
1056 if (unlikely(ret))
1057 return ret;
1058
76ad4f0e 1059 if (skb->ip_summed == CHECKSUM_PARTIAL) {
47e7b13b
YL
1060 u8 ol4_proto, il4_proto;
1061
76ad4f0e 1062 skb_reset_mac_len(skb);
76ad4f0e 1063
1898d4e4 1064 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
0cccebac 1065 if (unlikely(ret))
1898d4e4 1066 return ret;
757cd1e4
YL
1067
1068 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1069 &type_cs_vlan_tso,
1070 &ol_type_vlan_len_msec);
0cccebac 1071 if (unlikely(ret))
76ad4f0e
S
1072 return ret;
1073
1074 ret = hns3_set_tso(skb, &paylen, &mss,
1075 &type_cs_vlan_tso);
0cccebac 1076 if (unlikely(ret))
76ad4f0e
S
1077 return ret;
1078 }
1079
1080 /* Set txbd */
1081 desc->tx.ol_type_vlan_len_msec =
1082 cpu_to_le32(ol_type_vlan_len_msec);
9b2f3477 1083 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 1084 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 1085 desc->tx.mss = cpu_to_le16(mss);
9699cffe
PL
1086 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1087 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
5188f218
PL
1088
1089 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1090 } else {
1091 frag = (struct skb_frag_struct *)priv;
1092 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1093 }
1094
845e0d1d 1095 if (unlikely(dma_mapping_error(dev, dma))) {
5188f218
PL
1096 ring->stats.sw_err_cnt++;
1097 return -ENOMEM;
76ad4f0e
S
1098 }
1099
bcdb12b7
FL
1100 desc_cb->length = size;
1101
ceca4a5e
YL
1102 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1103 u16 bdtp_fe_sc_vld_ra_ri = 0;
1104
1105 desc_cb->priv = priv;
1106 desc_cb->dma = dma;
1107 desc_cb->type = type;
1108 desc->addr = cpu_to_le64(dma);
1109 desc->tx.send_size = cpu_to_le16(size);
1110 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
1111 desc->tx.bdtp_fe_sc_vld_ra_ri =
1112 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1113
1114 ring_ptr_move_fw(ring, next_to_use);
1115 return 0;
1116 }
1117
5f543a54 1118 frag_buf_num = hns3_tx_bd_count(size);
3fe13ed9 1119 sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1e8a7977
FL
1120 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1121
1122 /* When frag size is bigger than hardware limit, split this frag */
1123 for (k = 0; k < frag_buf_num; k++) {
ceca4a5e
YL
1124 u16 bdtp_fe_sc_vld_ra_ri = 0;
1125
1e8a7977
FL
1126 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1127 desc_cb->priv = priv;
1e8a7977
FL
1128 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1129 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
9b2f3477 1130 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1e8a7977
FL
1131
1132 /* now, fill the descriptor */
1133 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7 1134 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
9b2f3477 1135 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977
FL
1136 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1137 frag_end && (k == frag_buf_num - 1) ?
1138 1 : 0);
1139 desc->tx.bdtp_fe_sc_vld_ra_ri =
1140 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1141
9b2f3477 1142 /* move ring pointer to next */
1e8a7977
FL
1143 ring_ptr_move_fw(ring, next_to_use);
1144
1145 desc_cb = &ring->desc_cb[ring->next_to_use];
1146 desc = &ring->desc[ring->next_to_use];
1147 }
76ad4f0e
S
1148
1149 return 0;
1150}
1151
3d5f3741 1152static int hns3_nic_bd_num(struct sk_buff *skb)
76ad4f0e 1153{
3d5f3741
YL
1154 int size = skb_headlen(skb);
1155 int i, bd_num;
76ad4f0e 1156
3d5f3741
YL
1157 /* if the total len is within the max bd limit */
1158 if (likely(skb->len <= HNS3_MAX_BD_SIZE))
1159 return skb_shinfo(skb)->nr_frags + 1;
76ad4f0e 1160
3d5f3741 1161 bd_num = hns3_tx_bd_count(size);
76ad4f0e 1162
3d5f3741
YL
1163 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1164 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1165 int frag_bd_num;
76ad4f0e 1166
3d5f3741
YL
1167 size = skb_frag_size(frag);
1168 frag_bd_num = hns3_tx_bd_count(size);
1169
1170 if (unlikely(frag_bd_num > HNS3_MAX_BD_PER_FRAG))
51e8439f 1171 return -ENOMEM;
51e8439f 1172
3d5f3741
YL
1173 bd_num += frag_bd_num;
1174 }
76ad4f0e 1175
3d5f3741 1176 return bd_num;
76ad4f0e
S
1177}
1178
db4970aa
YL
1179static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1180{
1181 if (!skb->encapsulation)
1182 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1183
1184 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1185}
1186
1187/* HW need every continuous 8 buffer data to be larger than MSS,
1188 * we simplify it by ensuring skb_headlen + the first continuous
1189 * 7 frags to to be larger than gso header len + mss, and the remaining
1190 * continuous 7 frags to be larger than MSS except the last 7 frags.
1191 */
1192static bool hns3_skb_need_linearized(struct sk_buff *skb)
1193{
1194 int bd_limit = HNS3_MAX_BD_PER_FRAG - 1;
1195 unsigned int tot_len = 0;
1196 int i;
1197
1198 for (i = 0; i < bd_limit; i++)
1199 tot_len += skb_frag_size(&skb_shinfo(skb)->frags[i]);
1200
1201 /* ensure headlen + the first 7 frags is greater than mss + header
1202 * and the first 7 frags is greater than mss.
1203 */
1204 if (((tot_len + skb_headlen(skb)) < (skb_shinfo(skb)->gso_size +
1205 hns3_gso_hdr_len(skb))) || (tot_len < skb_shinfo(skb)->gso_size))
1206 return true;
1207
1208 /* ensure the remaining continuous 7 buffer is greater than mss */
1209 for (i = 0; i < (skb_shinfo(skb)->nr_frags - bd_limit - 1); i++) {
1210 tot_len -= skb_frag_size(&skb_shinfo(skb)->frags[i]);
1211 tot_len += skb_frag_size(&skb_shinfo(skb)->frags[i + bd_limit]);
1212
1213 if (tot_len < skb_shinfo(skb)->gso_size)
1214 return true;
1215 }
1216
1217 return false;
1218}
1219
3d5f3741
YL
1220static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1221 struct sk_buff **out_skb)
76ad4f0e
S
1222{
1223 struct sk_buff *skb = *out_skb;
3d5f3741 1224 int bd_num;
76ad4f0e 1225
3d5f3741
YL
1226 bd_num = hns3_nic_bd_num(skb);
1227 if (bd_num < 0)
1228 return bd_num;
1229
1230 if (unlikely(bd_num > HNS3_MAX_BD_PER_FRAG)) {
1231 struct sk_buff *new_skb;
76ad4f0e 1232
db4970aa
YL
1233 if (skb_is_gso(skb) && !hns3_skb_need_linearized(skb))
1234 goto out;
1235
3d5f3741
YL
1236 bd_num = hns3_tx_bd_count(skb->len);
1237 if (unlikely(ring_space(ring) < bd_num))
51e8439f
PL
1238 return -EBUSY;
1239 /* manual split the send packet */
1240 new_skb = skb_copy(skb, GFP_ATOMIC);
1241 if (!new_skb)
1242 return -ENOMEM;
1243 dev_kfree_skb_any(skb);
1244 *out_skb = new_skb;
3d5f3741
YL
1245
1246 u64_stats_update_begin(&ring->syncp);
1247 ring->stats.tx_copy++;
1248 u64_stats_update_end(&ring->syncp);
51e8439f
PL
1249 }
1250
db4970aa 1251out:
3d5f3741 1252 if (unlikely(ring_space(ring) < bd_num))
76ad4f0e
S
1253 return -EBUSY;
1254
3d5f3741 1255 return bd_num;
76ad4f0e
S
1256}
1257
ba3f808f 1258static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S
1259{
1260 struct device *dev = ring_to_dev(ring);
1261 unsigned int i;
1262
1263 for (i = 0; i < ring->desc_num; i++) {
1264 /* check if this is where we started */
1265 if (ring->next_to_use == next_to_use_orig)
1266 break;
1267
aa9d22dd
YL
1268 /* rollback one */
1269 ring_ptr_move_bw(ring, next_to_use);
1270
76ad4f0e
S
1271 /* unmap the descriptor dma address */
1272 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1273 dma_unmap_single(dev,
1274 ring->desc_cb[ring->next_to_use].dma,
1275 ring->desc_cb[ring->next_to_use].length,
1276 DMA_TO_DEVICE);
bcdb12b7 1277 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S
1278 dma_unmap_page(dev,
1279 ring->desc_cb[ring->next_to_use].dma,
1280 ring->desc_cb[ring->next_to_use].length,
1281 DMA_TO_DEVICE);
1282
bcdb12b7 1283 ring->desc_cb[ring->next_to_use].length = 0;
aa9d22dd 1284 ring->desc_cb[ring->next_to_use].dma = 0;
76ad4f0e
S
1285 }
1286}
1287
d43e5aca 1288netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S
1289{
1290 struct hns3_nic_priv *priv = netdev_priv(netdev);
1291 struct hns3_nic_ring_data *ring_data =
1292 &tx_ring_data(priv, skb->queue_mapping);
1293 struct hns3_enet_ring *ring = ring_data->ring;
76ad4f0e
S
1294 struct netdev_queue *dev_queue;
1295 struct skb_frag_struct *frag;
1296 int next_to_use_head;
76ad4f0e
S
1297 int buf_num;
1298 int seg_num;
1299 int size;
1300 int ret;
1301 int i;
1302
39d592aa
YL
1303 /* Hardware can only handle short frames above 32 bytes */
1304 if (skb_put_padto(skb, HNS3_MIN_TX_LEN))
1305 return NETDEV_TX_OK;
1306
76ad4f0e
S
1307 /* Prefetch the data used later */
1308 prefetch(skb->data);
1309
3d5f3741
YL
1310 buf_num = hns3_nic_maybe_stop_tx(ring, &skb);
1311 if (unlikely(buf_num <= 0)) {
1312 if (buf_num == -EBUSY) {
1313 u64_stats_update_begin(&ring->syncp);
1314 ring->stats.tx_busy++;
1315 u64_stats_update_end(&ring->syncp);
1316 goto out_net_tx_busy;
1317 } else if (buf_num == -ENOMEM) {
1318 u64_stats_update_begin(&ring->syncp);
1319 ring->stats.sw_err_cnt++;
1320 u64_stats_update_end(&ring->syncp);
1321 }
76ad4f0e 1322
3d5f3741
YL
1323 if (net_ratelimit())
1324 netdev_err(netdev, "xmit error: %d!\n", buf_num);
76ad4f0e
S
1325
1326 goto out_err_tx_ok;
76ad4f0e
S
1327 }
1328
1329 /* No. of segments (plus a header) */
1330 seg_num = skb_shinfo(skb)->nr_frags + 1;
1331 /* Fill the first part */
1332 size = skb_headlen(skb);
1333
1334 next_to_use_head = ring->next_to_use;
1335
d40fa7ee
YL
1336 ret = hns3_fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1337 DESC_TYPE_SKB);
0cccebac 1338 if (unlikely(ret))
aa9d22dd 1339 goto fill_err;
76ad4f0e 1340
76ad4f0e
S
1341 /* Fill the fragments */
1342 for (i = 1; i < seg_num; i++) {
1343 frag = &skb_shinfo(skb)->frags[i - 1];
1344 size = skb_frag_size(frag);
5188f218 1345
d40fa7ee
YL
1346 ret = hns3_fill_desc(ring, frag, size,
1347 seg_num - 1 == i ? 1 : 0,
1348 DESC_TYPE_PAGE);
76ad4f0e 1349
0cccebac 1350 if (unlikely(ret))
aa9d22dd 1351 goto fill_err;
76ad4f0e
S
1352 }
1353
1354 /* Complete translate all packets */
1355 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1356 netdev_tx_sent_queue(dev_queue, skb->len);
1357
1358 wmb(); /* Commit all data before submit */
1359
e4e87715 1360 hnae3_queue_xmit(ring->tqp, buf_num);
76ad4f0e
S
1361
1362 return NETDEV_TX_OK;
1363
aa9d22dd 1364fill_err:
ba3f808f 1365 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S
1366
1367out_err_tx_ok:
1368 dev_kfree_skb_any(skb);
1369 return NETDEV_TX_OK;
1370
1371out_net_tx_busy:
1372 netif_stop_subqueue(netdev, ring_data->queue_index);
1373 smp_mb(); /* Commit all data before submit */
1374
1375 return NETDEV_TX_BUSY;
1376}
1377
1378static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1379{
9780cb97 1380 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
1381 struct sockaddr *mac_addr = p;
1382 int ret;
1383
1384 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1385 return -EADDRNOTAVAIL;
1386
5ec2a51e
JS
1387 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1388 netdev_info(netdev, "already using mac address %pM\n",
1389 mac_addr->sa_data);
1390 return 0;
1391 }
1392
59098055 1393 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S
1394 if (ret) {
1395 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1396 return ret;
1397 }
1398
1399 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1400
1401 return 0;
1402}
1403
26483246
XW
1404static int hns3_nic_do_ioctl(struct net_device *netdev,
1405 struct ifreq *ifr, int cmd)
1406{
1407 struct hnae3_handle *h = hns3_get_handle(netdev);
1408
1409 if (!netif_running(netdev))
1410 return -EINVAL;
1411
1412 if (!h->ae_algo->ops->do_ioctl)
1413 return -EOPNOTSUPP;
1414
1415 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1416}
1417
76ad4f0e
S
1418static int hns3_nic_set_features(struct net_device *netdev,
1419 netdev_features_t features)
1420{
181d454b 1421 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1422 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1423 struct hnae3_handle *h = priv->ae_handle;
1731be4c 1424 bool enable;
052ece6d 1425 int ret;
76ad4f0e 1426
5c9f6b39 1427 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL
1428 enable = !!(features & NETIF_F_GRO_HW);
1429 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL
1430 if (ret)
1431 return ret;
1432 }
1433
bd368416
JS
1434 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1435 h->ae_algo->ops->enable_vlan_filter) {
1731be4c
YL
1436 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
1437 h->ae_algo->ops->enable_vlan_filter(h, enable);
181d454b 1438 }
391b5e93 1439
bd368416
JS
1440 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1441 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL
1442 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1443 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL
1444 if (ret)
1445 return ret;
1446 }
1447
c17852a8 1448 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL
1449 enable = !!(features & NETIF_F_NTUPLE);
1450 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS
1451 }
1452
76ad4f0e
S
1453 netdev->features = features;
1454 return 0;
1455}
1456
6c88d9d7
PL
1457static void hns3_nic_get_stats64(struct net_device *netdev,
1458 struct rtnl_link_stats64 *stats)
76ad4f0e
S
1459{
1460 struct hns3_nic_priv *priv = netdev_priv(netdev);
1461 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1462 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 1463 struct hns3_enet_ring *ring;
d3ec4ef6
JS
1464 u64 rx_length_errors = 0;
1465 u64 rx_crc_errors = 0;
1466 u64 rx_multicast = 0;
76ad4f0e 1467 unsigned int start;
d3ec4ef6
JS
1468 u64 tx_errors = 0;
1469 u64 rx_errors = 0;
76ad4f0e
S
1470 unsigned int idx;
1471 u64 tx_bytes = 0;
1472 u64 rx_bytes = 0;
1473 u64 tx_pkts = 0;
1474 u64 rx_pkts = 0;
d2a5dca8
JS
1475 u64 tx_drop = 0;
1476 u64 rx_drop = 0;
76ad4f0e 1477
b875cc37
JS
1478 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1479 return;
1480
c5f65480
JS
1481 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1482
76ad4f0e
S
1483 for (idx = 0; idx < queue_num; idx++) {
1484 /* fetch the tx stats */
1485 ring = priv->ring_data[idx].ring;
1486 do {
d36d36ce 1487 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S
1488 tx_bytes += ring->stats.tx_bytes;
1489 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 1490 tx_drop += ring->stats.sw_err_cnt;
d3ec4ef6 1491 tx_errors += ring->stats.sw_err_cnt;
76ad4f0e
S
1492 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1493
1494 /* fetch the rx stats */
1495 ring = priv->ring_data[idx + queue_num].ring;
1496 do {
d36d36ce 1497 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S
1498 rx_bytes += ring->stats.rx_bytes;
1499 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 1500 rx_drop += ring->stats.l2_err;
d3ec4ef6 1501 rx_errors += ring->stats.l2_err;
8b552079 1502 rx_errors += ring->stats.l3l4_csum_err;
d3ec4ef6 1503 rx_crc_errors += ring->stats.l2_err;
d3ec4ef6
JS
1504 rx_multicast += ring->stats.rx_multicast;
1505 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S
1506 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1507 }
1508
1509 stats->tx_bytes = tx_bytes;
1510 stats->tx_packets = tx_pkts;
1511 stats->rx_bytes = rx_bytes;
1512 stats->rx_packets = rx_pkts;
1513
d3ec4ef6
JS
1514 stats->rx_errors = rx_errors;
1515 stats->multicast = rx_multicast;
1516 stats->rx_length_errors = rx_length_errors;
1517 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S
1518 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1519
d3ec4ef6
JS
1520 stats->tx_errors = tx_errors;
1521 stats->rx_dropped = rx_drop;
1522 stats->tx_dropped = tx_drop;
76ad4f0e
S
1523 stats->collisions = netdev->stats.collisions;
1524 stats->rx_over_errors = netdev->stats.rx_over_errors;
1525 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1526 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1527 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1528 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1529 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1530 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1531 stats->tx_window_errors = netdev->stats.tx_window_errors;
1532 stats->rx_compressed = netdev->stats.rx_compressed;
1533 stats->tx_compressed = netdev->stats.tx_compressed;
1534}
1535
30d240df 1536static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1537{
30d240df 1538 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
30d240df 1539 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
75718800 1540 struct hnae3_knic_private_info *kinfo;
30d240df
YL
1541 u8 tc = mqprio_qopt->qopt.num_tc;
1542 u16 mode = mqprio_qopt->mode;
1543 u8 hw = mqprio_qopt->qopt.hw;
75718800 1544 struct hnae3_handle *h;
76ad4f0e 1545
30d240df
YL
1546 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1547 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1548 return -EOPNOTSUPP;
1549
76ad4f0e
S
1550 if (tc > HNAE3_MAX_TC)
1551 return -EINVAL;
1552
76ad4f0e
S
1553 if (!netdev)
1554 return -EINVAL;
1555
75718800
YL
1556 h = hns3_get_handle(netdev);
1557 kinfo = &h->kinfo;
1558
1cce5eb6 1559 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
30d240df 1560 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e
S
1561}
1562
2572ac53 1563static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1564 void *type_data)
76ad4f0e 1565{
575ed7d3 1566 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1567 return -EOPNOTSUPP;
76ad4f0e 1568
30d240df 1569 return hns3_setup_tc(dev, type_data);
76ad4f0e
S
1570}
1571
1572static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1573 __be16 proto, u16 vid)
1574{
9780cb97 1575 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
1576 int ret = -EIO;
1577
1578 if (h->ae_algo->ops->set_vlan_filter)
1579 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1580
1581 return ret;
1582}
1583
1584static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1585 __be16 proto, u16 vid)
1586{
9780cb97 1587 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
1588 int ret = -EIO;
1589
1590 if (h->ae_algo->ops->set_vlan_filter)
1591 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1592
7fa6be4f 1593 return ret;
681ec399
YL
1594}
1595
76ad4f0e
S
1596static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1597 u8 qos, __be16 vlan_proto)
1598{
9780cb97 1599 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
1600 int ret = -EIO;
1601
1602 if (h->ae_algo->ops->set_vf_vlan_filter)
1603 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
9b2f3477 1604 qos, vlan_proto);
76ad4f0e
S
1605
1606 return ret;
1607}
1608
a8e8b7ff
S
1609static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1610{
9780cb97 1611 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S
1612 int ret;
1613
6ff7ed80
HT
1614 if (hns3_nic_resetting(netdev))
1615 return -EBUSY;
1616
a8e8b7ff
S
1617 if (!h->ae_algo->ops->set_mtu)
1618 return -EOPNOTSUPP;
1619
a8e8b7ff 1620 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1621 if (ret)
a8e8b7ff
S
1622 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1623 ret);
93d8daf4
YL
1624 else
1625 netdev->mtu = new_mtu;
5bad95a1 1626
a8e8b7ff
S
1627 return ret;
1628}
1629
f8fa222c
L
1630static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1631{
1632 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 1633 struct hnae3_handle *h = hns3_get_handle(ndev);
f8fa222c 1634 struct hns3_enet_ring *tx_ring = NULL;
e511c97d 1635 struct napi_struct *napi;
f8fa222c
L
1636 int timeout_queue = 0;
1637 int hw_head, hw_tail;
e511c97d
JS
1638 int fbd_num, fbd_oft;
1639 int ebd_num, ebd_oft;
1640 int bd_num, bd_err;
1641 int ring_en, tc;
f8fa222c
L
1642 int i;
1643
1644 /* Find the stopped queue the same way the stack does */
fa6c4084 1645 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L
1646 struct netdev_queue *q;
1647 unsigned long trans_start;
1648
1649 q = netdev_get_tx_queue(ndev, i);
1650 trans_start = q->trans_start;
1651 if (netif_xmit_stopped(q) &&
1652 time_after(jiffies,
1653 (trans_start + ndev->watchdog_timeo))) {
1654 timeout_queue = i;
be64fadc
YL
1655 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1656 q->state,
1657 jiffies_to_msecs(jiffies - trans_start));
f8fa222c
L
1658 break;
1659 }
1660 }
1661
1662 if (i == ndev->num_tx_queues) {
1663 netdev_info(ndev,
1664 "no netdev TX timeout queue found, timeout count: %llu\n",
1665 priv->tx_timeout_count);
1666 return false;
1667 }
1668
beab694a
JS
1669 priv->tx_timeout_count++;
1670
f8fa222c 1671 tx_ring = priv->ring_data[timeout_queue].ring;
e511c97d
JS
1672 napi = &tx_ring->tqp_vector->napi;
1673
1674 netdev_info(ndev,
1675 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1676 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1677 tx_ring->next_to_clean, napi->state);
1678
1679 netdev_info(ndev,
1680 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1681 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1682 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1683
1684 netdev_info(ndev,
1685 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1686 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1687 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1688
1689 /* When mac received many pause frames continuous, it's unable to send
1690 * packets, which may cause tx timeout
1691 */
1692 if (h->ae_algo->ops->update_stats &&
1693 h->ae_algo->ops->get_mac_pause_stats) {
1694 u64 tx_pause_cnt, rx_pause_cnt;
1695
1696 h->ae_algo->ops->update_stats(h, &ndev->stats);
1697 h->ae_algo->ops->get_mac_pause_stats(h, &tx_pause_cnt,
1698 &rx_pause_cnt);
1699 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1700 tx_pause_cnt, rx_pause_cnt);
1701 }
f8fa222c
L
1702
1703 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1704 HNS3_RING_TX_RING_HEAD_REG);
1705 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1706 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS
1707 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1708 HNS3_RING_TX_RING_FBDNUM_REG);
1709 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1710 HNS3_RING_TX_RING_OFFSET_REG);
1711 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1712 HNS3_RING_TX_RING_EBDNUM_REG);
1713 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1714 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1715 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1716 HNS3_RING_TX_RING_BD_NUM_REG);
1717 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1718 HNS3_RING_TX_RING_BD_ERR_REG);
1719 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1720 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1721
f8fa222c 1722 netdev_info(ndev,
e511c97d
JS
1723 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1724 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 1725 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS
1726 netdev_info(ndev,
1727 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1728 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L
1729
1730 return true;
1731}
1732
1733static void hns3_nic_net_timeout(struct net_device *ndev)
1734{
1735 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L
1736 struct hnae3_handle *h = priv->ae_handle;
1737
1738 if (!hns3_get_tx_timeo_queue_info(ndev))
1739 return;
1740
0742ed7c
HT
1741 /* request the reset, and let the hclge to determine
1742 * which reset level should be done
1743 */
f8fa222c 1744 if (h->ae_algo->ops->reset_event)
6ae4e733 1745 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L
1746}
1747
d93ed94f
JS
1748#ifdef CONFIG_RFS_ACCEL
1749static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1750 u16 rxq_index, u32 flow_id)
1751{
1752 struct hnae3_handle *h = hns3_get_handle(dev);
1753 struct flow_keys fkeys;
1754
1755 if (!h->ae_algo->ops->add_arfs_entry)
1756 return -EOPNOTSUPP;
1757
1758 if (skb->encapsulation)
1759 return -EPROTONOSUPPORT;
1760
1761 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1762 return -EPROTONOSUPPORT;
1763
1764 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1765 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1766 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1767 fkeys.basic.ip_proto != IPPROTO_UDP))
1768 return -EPROTONOSUPPORT;
1769
1770 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1771}
1772#endif
1773
76ad4f0e
S
1774static const struct net_device_ops hns3_nic_netdev_ops = {
1775 .ndo_open = hns3_nic_net_open,
1776 .ndo_stop = hns3_nic_net_stop,
1777 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1778 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1779 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 1780 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1781 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S
1782 .ndo_set_features = hns3_nic_set_features,
1783 .ndo_get_stats64 = hns3_nic_get_stats64,
1784 .ndo_setup_tc = hns3_nic_setup_tc,
1785 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S
1786 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1787 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1788 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
d93ed94f
JS
1789#ifdef CONFIG_RFS_ACCEL
1790 .ndo_rx_flow_steer = hns3_rx_flow_steer,
1791#endif
1792
76ad4f0e
S
1793};
1794
97afd47b 1795bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL
1796{
1797 u32 dev_id = pdev->device;
1798
1799 switch (dev_id) {
1800 case HNAE3_DEV_ID_GE:
1801 case HNAE3_DEV_ID_25GE:
1802 case HNAE3_DEV_ID_25GE_RDMA:
1803 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1804 case HNAE3_DEV_ID_50GE_RDMA:
1805 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1806 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1807 return true;
1808 case HNAE3_DEV_ID_100G_VF:
1809 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1810 return false;
1811 default:
1812 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1813 dev_id);
1814 }
1815
1816 return false;
1817}
1818
2312e050
FL
1819static void hns3_disable_sriov(struct pci_dev *pdev)
1820{
1821 /* If our VFs are assigned we cannot shut down SR-IOV
1822 * without causing issues, so just leave the hardware
1823 * available but disabled
1824 */
1825 if (pci_vfs_assigned(pdev)) {
1826 dev_warn(&pdev->dev,
1827 "disabling driver while VFs are assigned\n");
1828 return;
1829 }
1830
1831 pci_disable_sriov(pdev);
1832}
1833
d695964d
JS
1834static void hns3_get_dev_capability(struct pci_dev *pdev,
1835 struct hnae3_ae_dev *ae_dev)
1836{
b26a6fea 1837 if (pdev->revision >= 0x21) {
d695964d 1838 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
b26a6fea
PL
1839 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1840 }
d695964d
JS
1841}
1842
76ad4f0e
S
1843/* hns3_probe - Device initialization routine
1844 * @pdev: PCI device information struct
1845 * @ent: entry in hns3_pci_tbl
1846 *
1847 * hns3_probe initializes a PF identified by a pci_dev structure.
1848 * The OS initialization, configuring of the PF private structure,
1849 * and a hardware reset occur.
1850 *
1851 * Returns 0 on success, negative on failure
1852 */
1853static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1854{
1855 struct hnae3_ae_dev *ae_dev;
1856 int ret;
1857
9b2f3477 1858 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
76ad4f0e
S
1859 if (!ae_dev) {
1860 ret = -ENOMEM;
1861 return ret;
1862 }
1863
1864 ae_dev->pdev = pdev;
e92a0843 1865 ae_dev->flag = ent->driver_data;
6871af29 1866 ae_dev->reset_type = HNAE3_NONE_RESET;
d695964d 1867 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S
1868 pci_set_drvdata(pdev, ae_dev);
1869
74354140
HT
1870 ret = hnae3_register_ae_dev(ae_dev);
1871 if (ret) {
1872 devm_kfree(&pdev->dev, ae_dev);
1873 pci_set_drvdata(pdev, NULL);
1874 }
2312e050 1875
74354140 1876 return ret;
76ad4f0e
S
1877}
1878
1879/* hns3_remove - Device removal routine
1880 * @pdev: PCI device information struct
1881 */
1882static void hns3_remove(struct pci_dev *pdev)
1883{
1884 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1885
2312e050
FL
1886 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1887 hns3_disable_sriov(pdev);
1888
76ad4f0e 1889 hnae3_unregister_ae_dev(ae_dev);
ac864c23 1890 pci_set_drvdata(pdev, NULL);
76ad4f0e
S
1891}
1892
fa8d82e8
PL
1893/**
1894 * hns3_pci_sriov_configure
1895 * @pdev: pointer to a pci_dev structure
1896 * @num_vfs: number of VFs to allocate
1897 *
1898 * Enable or change the number of VFs. Called when the user updates the number
1899 * of VFs in sysfs.
1900 **/
743e1a84 1901static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL
1902{
1903 int ret;
1904
1905 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1906 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1907 return -EINVAL;
1908 }
1909
1910 if (num_vfs) {
1911 ret = pci_enable_sriov(pdev, num_vfs);
1912 if (ret)
1913 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM
1914 else
1915 return num_vfs;
fa8d82e8
PL
1916 } else if (!pci_vfs_assigned(pdev)) {
1917 pci_disable_sriov(pdev);
1918 } else {
1919 dev_warn(&pdev->dev,
1920 "Unable to free VFs because some are assigned to VMs.\n");
1921 }
1922
1923 return 0;
1924}
1925
ce2c1d2e
YL
1926static void hns3_shutdown(struct pci_dev *pdev)
1927{
1928 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1929
1930 hnae3_unregister_ae_dev(ae_dev);
1931 devm_kfree(&pdev->dev, ae_dev);
1932 pci_set_drvdata(pdev, NULL);
1933
1934 if (system_state == SYSTEM_POWER_OFF)
1935 pci_set_power_state(pdev, PCI_D3hot);
1936}
1937
5a9f0eac
SJ
1938static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1939 pci_channel_state_t state)
1940{
1941 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1942 pci_ers_result_t ret;
1943
1944 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1945
1946 if (state == pci_channel_io_perm_failure)
1947 return PCI_ERS_RESULT_DISCONNECT;
1948
661262bc 1949 if (!ae_dev || !ae_dev->ops) {
5a9f0eac 1950 dev_err(&pdev->dev,
661262bc 1951 "Can't recover - error happened before device initialized\n");
5a9f0eac
SJ
1952 return PCI_ERS_RESULT_NONE;
1953 }
1954
381c356e
SJ
1955 if (ae_dev->ops->handle_hw_ras_error)
1956 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ
1957 else
1958 return PCI_ERS_RESULT_NONE;
1959
1960 return ret;
1961}
1962
6ae4e733
SJ
1963static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1964{
1965 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
ad9bf545 1966 const struct hnae3_ae_ops *ops;
123297b7 1967 enum hnae3_reset_type reset_type;
6ae4e733
SJ
1968 struct device *dev = &pdev->dev;
1969
661262bc
WL
1970 if (!ae_dev || !ae_dev->ops)
1971 return PCI_ERS_RESULT_NONE;
1972
ad9bf545 1973 ops = ae_dev->ops;
6ae4e733 1974 /* request the reset */
123297b7 1975 if (ops->reset_event) {
9d5e67d1 1976 if (ae_dev->hw_err_reset_req) {
123297b7
SJ
1977 reset_type = ops->get_reset_level(ae_dev,
1978 &ae_dev->hw_err_reset_req);
1979 ops->set_default_reset_request(ae_dev, reset_type);
1980 dev_info(dev, "requesting reset due to PCI error\n");
1981 ops->reset_event(pdev, NULL);
1982 }
69b51bbb 1983
6ae4e733
SJ
1984 return PCI_ERS_RESULT_RECOVERED;
1985 }
1986
1987 return PCI_ERS_RESULT_DISCONNECT;
1988}
1989
6b9a97ee
HT
1990static void hns3_reset_prepare(struct pci_dev *pdev)
1991{
1992 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1993
1994 dev_info(&pdev->dev, "hns3 flr prepare\n");
1995 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1996 ae_dev->ops->flr_prepare(ae_dev);
1997}
1998
1999static void hns3_reset_done(struct pci_dev *pdev)
2000{
2001 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2002
2003 dev_info(&pdev->dev, "hns3 flr done\n");
2004 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2005 ae_dev->ops->flr_done(ae_dev);
2006}
2007
5a9f0eac
SJ
2008static const struct pci_error_handlers hns3_err_handler = {
2009 .error_detected = hns3_error_detected,
6ae4e733 2010 .slot_reset = hns3_slot_reset,
6b9a97ee
HT
2011 .reset_prepare = hns3_reset_prepare,
2012 .reset_done = hns3_reset_done,
5a9f0eac
SJ
2013};
2014
76ad4f0e
S
2015static struct pci_driver hns3_driver = {
2016 .name = hns3_driver_name,
2017 .id_table = hns3_pci_tbl,
2018 .probe = hns3_probe,
2019 .remove = hns3_remove,
ce2c1d2e 2020 .shutdown = hns3_shutdown,
fa8d82e8 2021 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 2022 .err_handler = &hns3_err_handler,
76ad4f0e
S
2023};
2024
2025/* set default feature to hns3 */
2026static void hns3_set_default_feature(struct net_device *netdev)
2027{
3e85af6a
PL
2028 struct hnae3_handle *h = hns3_get_handle(netdev);
2029 struct pci_dev *pdev = h->pdev;
2030
76ad4f0e
S
2031 netdev->priv_flags |= IFF_UNICAST_FLT;
2032
2033 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2034 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2035 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2036 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2037 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S
2038
2039 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
2040
2041 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2042
2043 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2044 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 2045 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S
2046 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2047 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2048 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2049 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S
2050
2051 netdev->vlan_features |=
2052 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2053 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2054 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2055 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2056 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S
2057
2058 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 2059 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S
2060 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2061 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2062 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2063 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
3e85af6a 2064
c17852a8 2065 if (pdev->revision >= 0x21) {
77af09c6 2066 netdev->hw_features |= NETIF_F_GRO_HW;
5c9f6b39 2067 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS
2068
2069 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2070 netdev->hw_features |= NETIF_F_NTUPLE;
2071 netdev->features |= NETIF_F_NTUPLE;
2072 }
2073 }
76ad4f0e
S
2074}
2075
2076static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2077 struct hns3_desc_cb *cb)
2078{
e4e87715 2079 unsigned int order = hnae3_page_order(ring);
76ad4f0e
S
2080 struct page *p;
2081
2082 p = dev_alloc_pages(order);
2083 if (!p)
2084 return -ENOMEM;
2085
2086 cb->priv = p;
2087 cb->page_offset = 0;
2088 cb->reuse_flag = 0;
2089 cb->buf = page_address(p);
e4e87715 2090 cb->length = hnae3_page_size(ring);
76ad4f0e
S
2091 cb->type = DESC_TYPE_PAGE;
2092
76ad4f0e
S
2093 return 0;
2094}
2095
2096static void hns3_free_buffer(struct hns3_enet_ring *ring,
2097 struct hns3_desc_cb *cb)
2098{
2099 if (cb->type == DESC_TYPE_SKB)
2100 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2101 else if (!HNAE3_IS_TX_RING(ring))
2102 put_page((struct page *)cb->priv);
2103 memset(cb, 0, sizeof(*cb));
2104}
2105
2106static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2107{
2108 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2109 cb->length, ring_to_dma_dir(ring));
2110
2211f4e1 2111 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S
2112 return -EIO;
2113
2114 return 0;
2115}
2116
2117static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2118 struct hns3_desc_cb *cb)
2119{
2120 if (cb->type == DESC_TYPE_SKB)
2121 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2122 ring_to_dma_dir(ring));
bcdb12b7 2123 else if (cb->length)
76ad4f0e
S
2124 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2125 ring_to_dma_dir(ring));
2126}
2127
2128static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2129{
2130 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2131 ring->desc[i].addr = 0;
2132}
2133
2134static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2135{
2136 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2137
2138 if (!ring->desc_cb[i].dma)
2139 return;
2140
2141 hns3_buffer_detach(ring, i);
2142 hns3_free_buffer(ring, cb);
2143}
2144
2145static void hns3_free_buffers(struct hns3_enet_ring *ring)
2146{
2147 int i;
2148
2149 for (i = 0; i < ring->desc_num; i++)
2150 hns3_free_buffer_detach(ring, i);
2151}
2152
2153/* free desc along with its attached buffer */
2154static void hns3_free_desc(struct hns3_enet_ring *ring)
2155{
024cc792
HT
2156 int size = ring->desc_num * sizeof(ring->desc[0]);
2157
76ad4f0e
S
2158 hns3_free_buffers(ring);
2159
024cc792
HT
2160 if (ring->desc) {
2161 dma_free_coherent(ring_to_dev(ring), size,
2162 ring->desc, ring->desc_dma_addr);
2163 ring->desc = NULL;
2164 }
76ad4f0e
S
2165}
2166
2167static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2168{
2169 int size = ring->desc_num * sizeof(ring->desc[0]);
2170
750afb08
LC
2171 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2172 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S
2173 if (!ring->desc)
2174 return -ENOMEM;
2175
76ad4f0e
S
2176 return 0;
2177}
2178
2179static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2180 struct hns3_desc_cb *cb)
2181{
2182 int ret;
2183
2184 ret = hns3_alloc_buffer(ring, cb);
2185 if (ret)
2186 goto out;
2187
2188 ret = hns3_map_buffer(ring, cb);
2189 if (ret)
2190 goto out_with_buf;
2191
2192 return 0;
2193
2194out_with_buf:
564883bb 2195 hns3_free_buffer(ring, cb);
76ad4f0e
S
2196out:
2197 return ret;
2198}
2199
2200static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2201{
2202 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2203
2204 if (ret)
2205 return ret;
2206
2207 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2208
2209 return 0;
2210}
2211
2212/* Allocate memory for raw pkg, and map with dma */
2213static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2214{
2215 int i, j, ret;
2216
2217 for (i = 0; i < ring->desc_num; i++) {
2218 ret = hns3_alloc_buffer_attach(ring, i);
2219 if (ret)
2220 goto out_buffer_fail;
2221 }
2222
2223 return 0;
2224
2225out_buffer_fail:
2226 for (j = i - 1; j >= 0; j--)
2227 hns3_free_buffer_detach(ring, j);
2228 return ret;
2229}
2230
9b2f3477 2231/* detach a in-used buffer and replace with a reserved one */
76ad4f0e
S
2232static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2233 struct hns3_desc_cb *res_cb)
2234{
b9077428 2235 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S
2236 ring->desc_cb[i] = *res_cb;
2237 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2238 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S
2239}
2240
2241static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2242{
2243 ring->desc_cb[i].reuse_flag = 0;
9b2f3477
WL
2244 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2245 ring->desc_cb[i].page_offset);
7d0b130c 2246 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S
2247}
2248
ce74370c
YL
2249static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2250 int *bytes, int *pkts)
76ad4f0e 2251{
26cda2f1
YL
2252 int ntc = ring->next_to_clean;
2253 struct hns3_desc_cb *desc_cb;
76ad4f0e 2254
ce74370c
YL
2255 while (head != ntc) {
2256 desc_cb = &ring->desc_cb[ntc];
2257 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2258 (*bytes) += desc_cb->length;
2259 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2260 hns3_free_buffer_detach(ring, ntc);
76ad4f0e 2261
ce74370c
YL
2262 if (++ntc == ring->desc_num)
2263 ntc = 0;
2264
2265 /* Issue prefetch for next Tx descriptor */
2266 prefetch(&ring->desc_cb[ntc]);
2267 }
26cda2f1
YL
2268
2269 /* This smp_store_release() pairs with smp_load_acquire() in
2270 * ring_space called by hns3_nic_net_xmit.
2271 */
2272 smp_store_release(&ring->next_to_clean, ntc);
76ad4f0e
S
2273}
2274
2275static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2276{
2277 int u = ring->next_to_use;
2278 int c = ring->next_to_clean;
2279
2280 if (unlikely(h > ring->desc_num))
2281 return 0;
2282
2283 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2284}
2285
799997a3 2286void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e
S
2287{
2288 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
7a810110 2289 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S
2290 struct netdev_queue *dev_queue;
2291 int bytes, pkts;
2292 int head;
2293
2294 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2295 rmb(); /* Make sure head is ready before touch any data */
2296
2297 if (is_ring_empty(ring) || head == ring->next_to_clean)
799997a3 2298 return; /* no data to poll */
76ad4f0e 2299
0e6084aa 2300 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S
2301 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2302 ring->next_to_use, ring->next_to_clean);
2303
2304 u64_stats_update_begin(&ring->syncp);
2305 ring->stats.io_err_cnt++;
2306 u64_stats_update_end(&ring->syncp);
799997a3 2307 return;
76ad4f0e
S
2308 }
2309
2310 bytes = 0;
2311 pkts = 0;
ce74370c 2312 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
76ad4f0e
S
2313
2314 ring->tqp_vector->tx_group.total_bytes += bytes;
2315 ring->tqp_vector->tx_group.total_packets += pkts;
2316
2317 u64_stats_update_begin(&ring->syncp);
2318 ring->stats.tx_bytes += bytes;
2319 ring->stats.tx_pkts += pkts;
2320 u64_stats_update_end(&ring->syncp);
2321
2322 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2323 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2324
2325 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2326 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2327 /* Make sure that anybody stopping the queue after this
2328 * sees the new next_to_clean.
2329 */
2330 smp_mb();
7a810110
JS
2331 if (netif_tx_queue_stopped(dev_queue) &&
2332 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S
2333 netif_tx_wake_queue(dev_queue);
2334 ring->stats.restart_queue++;
2335 }
2336 }
76ad4f0e
S
2337}
2338
2339static int hns3_desc_unused(struct hns3_enet_ring *ring)
2340{
2341 int ntc = ring->next_to_clean;
2342 int ntu = ring->next_to_use;
2343
2344 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2345}
2346
9b2f3477
WL
2347static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2348 int cleand_count)
76ad4f0e
S
2349{
2350 struct hns3_desc_cb *desc_cb;
2351 struct hns3_desc_cb res_cbs;
2352 int i, ret;
2353
2354 for (i = 0; i < cleand_count; i++) {
2355 desc_cb = &ring->desc_cb[ring->next_to_use];
2356 if (desc_cb->reuse_flag) {
2357 u64_stats_update_begin(&ring->syncp);
2358 ring->stats.reuse_pg_cnt++;
2359 u64_stats_update_end(&ring->syncp);
2360
2361 hns3_reuse_buffer(ring, ring->next_to_use);
2362 } else {
2363 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2364 if (ret) {
2365 u64_stats_update_begin(&ring->syncp);
2366 ring->stats.sw_err_cnt++;
2367 u64_stats_update_end(&ring->syncp);
2368
2369 netdev_err(ring->tqp->handle->kinfo.netdev,
2370 "hnae reserve buffer map failed.\n");
2371 break;
2372 }
2373 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL
2374
2375 u64_stats_update_begin(&ring->syncp);
2376 ring->stats.non_reuse_pg++;
2377 u64_stats_update_end(&ring->syncp);
76ad4f0e
S
2378 }
2379
2380 ring_ptr_move_fw(ring, next_to_use);
2381 }
2382
2383 wmb(); /* Make all data has been write before submit */
2384 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2385}
2386
76ad4f0e
S
2387static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2388 struct hns3_enet_ring *ring, int pull_len,
2389 struct hns3_desc_cb *desc_cb)
2390{
389ca146
YL
2391 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2392 int size = le16_to_cpu(desc->rx.size);
2393 u32 truesize = hnae3_buf_size(ring);
76ad4f0e
S
2394
2395 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2396 size - pull_len, truesize);
76ad4f0e 2397
389ca146
YL
2398 /* Avoid re-using remote pages, or the stack is still using the page
2399 * when page_offset rollback to zero, flag default unreuse
2400 */
d5970dc7 2401 if (unlikely(page_to_nid(desc_cb->priv) != numa_mem_id()) ||
389ca146 2402 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
76ad4f0e 2403 return;
76ad4f0e
S
2404
2405 /* Move offset up to the next cache line */
2406 desc_cb->page_offset += truesize;
2407
389ca146 2408 if (desc_cb->page_offset + truesize <= hnae3_page_size(ring)) {
76ad4f0e 2409 desc_cb->reuse_flag = 1;
9b2f3477 2410 /* Bump ref count on page before it is given */
76ad4f0e 2411 get_page(desc_cb->priv);
389ca146
YL
2412 } else if (page_count(desc_cb->priv) == 1) {
2413 desc_cb->reuse_flag = 1;
2414 desc_cb->page_offset = 0;
2415 get_page(desc_cb->priv);
76ad4f0e
S
2416 }
2417}
2418
e2ee1c5a 2419static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
d474d88f
YL
2420{
2421 __be16 type = skb->protocol;
2422 struct tcphdr *th;
2423 int depth = 0;
2424
e2ee1c5a 2425 while (eth_type_vlan(type)) {
d474d88f
YL
2426 struct vlan_hdr *vh;
2427
2428 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2429 return -EFAULT;
2430
2431 vh = (struct vlan_hdr *)(skb->data + depth);
2432 type = vh->h_vlan_encapsulated_proto;
2433 depth += VLAN_HLEN;
2434 }
2435
e2ee1c5a
YL
2436 skb_set_network_header(skb, depth);
2437
d474d88f 2438 if (type == htons(ETH_P_IP)) {
e2ee1c5a
YL
2439 const struct iphdr *iph = ip_hdr(skb);
2440
d474d88f 2441 depth += sizeof(struct iphdr);
e2ee1c5a
YL
2442 skb_set_transport_header(skb, depth);
2443 th = tcp_hdr(skb);
2444 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2445 iph->daddr, 0);
d474d88f 2446 } else if (type == htons(ETH_P_IPV6)) {
e2ee1c5a
YL
2447 const struct ipv6hdr *iph = ipv6_hdr(skb);
2448
d474d88f 2449 depth += sizeof(struct ipv6hdr);
e2ee1c5a
YL
2450 skb_set_transport_header(skb, depth);
2451 th = tcp_hdr(skb);
2452 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2453 &iph->daddr, 0);
d474d88f
YL
2454 } else {
2455 netdev_err(skb->dev,
2456 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2457 be16_to_cpu(type), depth);
2458 return -EFAULT;
2459 }
2460
d474d88f
YL
2461 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2462 if (th->cwr)
2463 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2464
e2ee1c5a
YL
2465 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2466 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
d474d88f 2467
e2ee1c5a
YL
2468 skb->csum_start = (unsigned char *)th - skb->head;
2469 skb->csum_offset = offsetof(struct tcphdr, check);
2470 skb->ip_summed = CHECKSUM_PARTIAL;
d474d88f
YL
2471 return 0;
2472}
2473
76ad4f0e 2474static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
39c38824 2475 u32 l234info, u32 bd_base_info, u32 ol_info)
76ad4f0e
S
2476{
2477 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2478 int l3_type, l4_type;
76ad4f0e 2479 int ol4_type;
76ad4f0e
S
2480
2481 skb->ip_summed = CHECKSUM_NONE;
2482
2483 skb_checksum_none_assert(skb);
2484
2485 if (!(netdev->features & NETIF_F_RXCSUM))
2486 return;
2487
2488 /* check if hardware has done checksum */
e8149933 2489 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
76ad4f0e
S
2490 return;
2491
f4772dee
DC
2492 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2493 BIT(HNS3_RXD_OL3E_B) |
e8149933 2494 BIT(HNS3_RXD_OL4E_B)))) {
76ad4f0e
S
2495 u64_stats_update_begin(&ring->syncp);
2496 ring->stats.l3l4_csum_err++;
2497 u64_stats_update_end(&ring->syncp);
2498
2499 return;
2500 }
2501
39c38824 2502 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 2503 HNS3_RXD_OL4ID_S);
76ad4f0e
S
2504 switch (ol4_type) {
2505 case HNS3_OL4_TYPE_MAC_IN_UDP:
2506 case HNS3_OL4_TYPE_NVGRE:
2507 skb->csum_level = 1;
be44b3af 2508 /* fall through */
76ad4f0e 2509 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL
2510 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2511 HNS3_RXD_L3ID_S);
2512 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2513 HNS3_RXD_L4ID_S);
2514
76ad4f0e 2515 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL
2516 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2517 l3_type == HNS3_L3_TYPE_IPV6) &&
2518 (l4_type == HNS3_L4_TYPE_UDP ||
2519 l4_type == HNS3_L4_TYPE_TCP ||
2520 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S
2521 skb->ip_summed = CHECKSUM_UNNECESSARY;
2522 break;
fa7a4bd5
JS
2523 default:
2524 break;
76ad4f0e
S
2525 }
2526}
2527
d43e5aca
YL
2528static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2529{
81ae0e04
PL
2530 if (skb_has_frag_list(skb))
2531 napi_gro_flush(&ring->tqp_vector->napi, false);
2532
d43e5aca
YL
2533 napi_gro_receive(&ring->tqp_vector->napi, skb);
2534}
2535
701a6d6a
JS
2536static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2537 struct hns3_desc *desc, u32 l234info,
2538 u16 *vlan_tag)
5b5455a9 2539{
44e626f7 2540 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 2541 struct pci_dev *pdev = ring->tqp->handle->pdev;
5b5455a9
PL
2542
2543 if (pdev->revision == 0x20) {
701a6d6a
JS
2544 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2545 if (!(*vlan_tag & VLAN_VID_MASK))
2546 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 2547
701a6d6a 2548 return (*vlan_tag != 0);
5b5455a9
PL
2549 }
2550
2551#define HNS3_STRP_OUTER_VLAN 0x1
2552#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 2553#define HNS3_STRP_BOTH 0x3
5b5455a9 2554
44e626f7
JS
2555 /* Hardware always insert VLAN tag into RX descriptor when
2556 * remove the tag from packet, driver needs to determine
2557 * reporting which tag to stack.
2558 */
e4e87715
PL
2559 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2560 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 2561 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS
2562 if (handle->port_base_vlan_state !=
2563 HNAE3_PORT_BASE_VLAN_DISABLE)
2564 return false;
2565
701a6d6a
JS
2566 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2567 return true;
5b5455a9 2568 case HNS3_STRP_INNER_VLAN:
44e626f7
JS
2569 if (handle->port_base_vlan_state !=
2570 HNAE3_PORT_BASE_VLAN_DISABLE)
2571 return false;
2572
701a6d6a 2573 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS
2574 return true;
2575 case HNS3_STRP_BOTH:
2576 if (handle->port_base_vlan_state ==
2577 HNAE3_PORT_BASE_VLAN_DISABLE)
2578 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2579 else
2580 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2581
701a6d6a 2582 return true;
5b5455a9 2583 default:
701a6d6a 2584 return false;
5b5455a9 2585 }
5b5455a9
PL
2586}
2587
b9a8f883 2588static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
e5597095
PL
2589 unsigned char *va)
2590{
2591#define HNS3_NEED_ADD_FRAG 1
2592 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2593 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2594 struct sk_buff *skb;
2595
2596 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2597 skb = ring->skb;
2598 if (unlikely(!skb)) {
2599 netdev_err(netdev, "alloc rx skb fail\n");
2600
2601 u64_stats_update_begin(&ring->syncp);
2602 ring->stats.sw_err_cnt++;
2603 u64_stats_update_end(&ring->syncp);
2604
2605 return -ENOMEM;
2606 }
2607
2608 prefetchw(skb->data);
2609
2610 ring->pending_buf = 1;
81ae0e04
PL
2611 ring->frag_num = 0;
2612 ring->tail_skb = NULL;
e5597095
PL
2613 if (length <= HNS3_RX_HEAD_SIZE) {
2614 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2615
2616 /* We can reuse buffer as-is, just make sure it is local */
d5970dc7 2617 if (likely(page_to_nid(desc_cb->priv) == numa_mem_id()))
e5597095
PL
2618 desc_cb->reuse_flag = 1;
2619 else /* This page cannot be reused so discard it */
2620 put_page(desc_cb->priv);
2621
2622 ring_ptr_move_fw(ring, next_to_clean);
2623 return 0;
2624 }
2625 u64_stats_update_begin(&ring->syncp);
2626 ring->stats.seg_pkt_cnt++;
2627 u64_stats_update_end(&ring->syncp);
2628
c43f1255 2629 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 2630 __skb_put(skb, ring->pull_len);
81ae0e04 2631 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095
PL
2632 desc_cb);
2633 ring_ptr_move_fw(ring, next_to_clean);
2634
2635 return HNS3_NEED_ADD_FRAG;
2636}
2637
2638static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2639 struct sk_buff **out_skb, bool pending)
2640{
2641 struct sk_buff *skb = *out_skb;
81ae0e04
PL
2642 struct sk_buff *head_skb = *out_skb;
2643 struct sk_buff *new_skb;
e5597095
PL
2644 struct hns3_desc_cb *desc_cb;
2645 struct hns3_desc *pre_desc;
2646 u32 bd_base_info;
2647 int pre_bd;
2648
2649 /* if there is pending bd, the SW param next_to_clean has moved
2650 * to next and the next is NULL
2651 */
2652 if (pending) {
2653 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
9b2f3477 2654 ring->desc_num;
e5597095
PL
2655 pre_desc = &ring->desc[pre_bd];
2656 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2657 } else {
2658 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2659 }
2660
e8149933 2661 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
e5597095
PL
2662 desc = &ring->desc[ring->next_to_clean];
2663 desc_cb = &ring->desc_cb[ring->next_to_clean];
2664 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS
2665 /* make sure HW write desc complete */
2666 dma_rmb();
e8149933 2667 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL
2668 return -ENXIO;
2669
81ae0e04
PL
2670 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2671 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2672 HNS3_RX_HEAD_SIZE);
2673 if (unlikely(!new_skb)) {
2674 netdev_err(ring->tqp->handle->kinfo.netdev,
2675 "alloc rx skb frag fail\n");
2676 return -ENXIO;
2677 }
2678 ring->frag_num = 0;
2679
2680 if (ring->tail_skb) {
2681 ring->tail_skb->next = new_skb;
2682 ring->tail_skb = new_skb;
2683 } else {
2684 skb_shinfo(skb)->frag_list = new_skb;
2685 ring->tail_skb = new_skb;
2686 }
2687 }
2688
2689 if (ring->tail_skb) {
2690 head_skb->truesize += hnae3_buf_size(ring);
2691 head_skb->data_len += le16_to_cpu(desc->rx.size);
2692 head_skb->len += le16_to_cpu(desc->rx.size);
2693 skb = ring->tail_skb;
2694 }
2695
2696 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
e5597095
PL
2697 ring_ptr_move_fw(ring, next_to_clean);
2698 ring->pending_buf++;
2699 }
2700
2701 return 0;
2702}
2703
d474d88f
YL
2704static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2705 struct sk_buff *skb, u32 l234info,
39c38824 2706 u32 bd_base_info, u32 ol_info)
a6d53b97 2707{
a6d53b97
PL
2708 u32 l3_type;
2709
e2ee1c5a
YL
2710 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2711 HNS3_RXD_GRO_SIZE_M,
2712 HNS3_RXD_GRO_SIZE_S);
a6d53b97 2713 /* if there is no HW GRO, do not set gro params */
e2ee1c5a 2714 if (!skb_shinfo(skb)->gso_size) {
39c38824 2715 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
d474d88f
YL
2716 return 0;
2717 }
a6d53b97 2718
e2ee1c5a
YL
2719 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2720 HNS3_RXD_GRO_COUNT_M,
2721 HNS3_RXD_GRO_COUNT_S);
a6d53b97 2722
9b2f3477 2723 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
a6d53b97
PL
2724 if (l3_type == HNS3_L3_TYPE_IPV4)
2725 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2726 else if (l3_type == HNS3_L3_TYPE_IPV6)
2727 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2728 else
d474d88f 2729 return -EFAULT;
a6d53b97 2730
e2ee1c5a 2731 return hns3_gro_complete(skb, l234info);
a6d53b97
PL
2732}
2733
232fc64b 2734static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 2735 struct sk_buff *skb, u32 rss_hash)
232fc64b 2736{
232fc64b
PL
2737 struct hnae3_handle *handle = ring->tqp->handle;
2738 enum pkt_hash_types rss_type;
2739
ea485867 2740 if (rss_hash)
232fc64b
PL
2741 rss_type = handle->kinfo.rss_type;
2742 else
2743 rss_type = PKT_HASH_TYPE_NONE;
2744
ea485867 2745 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL
2746}
2747
ea485867 2748static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e
S
2749{
2750 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
c376fa1a 2751 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 2752 u32 bd_base_info, l234info, ol_info;
ea485867 2753 struct hns3_desc *desc;
d474d88f 2754 unsigned int len;
ea485867
YL
2755 int pre_ntc, ret;
2756
2757 /* bdinfo handled below is only valid on the last BD of the
2758 * current packet, and ring->next_to_clean indicates the first
2759 * descriptor of next packet, so need - 1 below.
2760 */
2761 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2762 (ring->desc_num - 1);
2763 desc = &ring->desc[pre_ntc];
2764 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2765 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 2766 ol_info = le32_to_cpu(desc->rx.ol_info);
d474d88f
YL
2767
2768 /* Based on hw strategy, the tag offloaded will be stored at
2769 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2770 * in one layer tag case.
2771 */
2772 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2773 u16 vlan_tag;
2774
2775 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2776 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2777 vlan_tag);
2778 }
2779
d474d88f
YL
2780 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
2781 BIT(HNS3_RXD_L2E_B))))) {
2782 u64_stats_update_begin(&ring->syncp);
2783 if (l234info & BIT(HNS3_RXD_L2E_B))
2784 ring->stats.l2_err++;
2785 else
2786 ring->stats.err_pkt_len++;
2787 u64_stats_update_end(&ring->syncp);
2788
2789 return -EFAULT;
2790 }
2791
2792 len = skb->len;
2793
2794 /* Do update ip stack process */
2795 skb->protocol = eth_type_trans(skb, netdev);
2796
2797 /* This is needed in order to enable forwarding support */
39c38824
YL
2798 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
2799 bd_base_info, ol_info);
d474d88f
YL
2800 if (unlikely(ret)) {
2801 u64_stats_update_begin(&ring->syncp);
2802 ring->stats.rx_err_cnt++;
2803 u64_stats_update_end(&ring->syncp);
2804 return ret;
2805 }
2806
2807 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
2808 HNS3_RXD_DMAC_S);
2809
2810 u64_stats_update_begin(&ring->syncp);
2811 ring->stats.rx_pkts++;
2812 ring->stats.rx_bytes += len;
2813
2814 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
2815 ring->stats.rx_multicast++;
2816
2817 u64_stats_update_end(&ring->syncp);
2818
2819 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL
2820
2821 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL
2822 return 0;
2823}
2824
2825static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2826 struct sk_buff **out_skb)
2827{
e5597095 2828 struct sk_buff *skb = ring->skb;
76ad4f0e
S
2829 struct hns3_desc_cb *desc_cb;
2830 struct hns3_desc *desc;
b9a8f883 2831 unsigned int length;
76ad4f0e 2832 u32 bd_base_info;
e5597095 2833 int ret;
76ad4f0e
S
2834
2835 desc = &ring->desc[ring->next_to_clean];
2836 desc_cb = &ring->desc_cb[ring->next_to_clean];
2837
2838 prefetch(desc);
2839
846fcc83 2840 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2841 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S
2842
2843 /* Check valid BD */
e8149933 2844 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
e5597095 2845 return -ENXIO;
76ad4f0e 2846
e5597095
PL
2847 if (!skb)
2848 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
76ad4f0e
S
2849
2850 /* Prefetch first cache line of first page
2851 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2852 * line size is 64B so need to prefetch twice to make it 128B. But in
2853 * actual we can have greater size of caches with 128B Level 1 cache
2854 * lines. In such a case, single fetch would suffice to cache in the
2855 * relevant part of the header.
2856 */
e5597095 2857 prefetch(ring->va);
76ad4f0e 2858#if L1_CACHE_BYTES < 128
e5597095 2859 prefetch(ring->va + L1_CACHE_BYTES);
76ad4f0e
S
2860#endif
2861
e5597095
PL
2862 if (!skb) {
2863 ret = hns3_alloc_skb(ring, length, ring->va);
2864 *out_skb = skb = ring->skb;
76ad4f0e 2865
e5597095
PL
2866 if (ret < 0) /* alloc buffer fail */
2867 return ret;
2868 if (ret > 0) { /* need add frag */
2869 ret = hns3_add_frag(ring, desc, &skb, false);
2870 if (ret)
2871 return ret;
76ad4f0e 2872
e5597095
PL
2873 /* As the head data may be changed when GRO enable, copy
2874 * the head data in after other data rx completed
2875 */
2876 memcpy(skb->data, ring->va,
2877 ALIGN(ring->pull_len, sizeof(long)));
2878 }
76ad4f0e 2879 } else {
e5597095
PL
2880 ret = hns3_add_frag(ring, desc, &skb, true);
2881 if (ret)
2882 return ret;
76ad4f0e 2883
e5597095
PL
2884 /* As the head data may be changed when GRO enable, copy
2885 * the head data in after other data rx completed
2886 */
2887 memcpy(skb->data, ring->va,
2888 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e
S
2889 }
2890
ea485867 2891 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 2892 if (unlikely(ret)) {
76ad4f0e 2893 dev_kfree_skb_any(skb);
d474d88f 2894 return ret;
76ad4f0e
S
2895 }
2896
d93ed94f 2897 skb_record_rx_queue(skb, ring->tqp->tqp_index);
e5597095 2898 *out_skb = skb;
232fc64b 2899
76ad4f0e
S
2900 return 0;
2901}
2902
9b2f3477
WL
2903int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
2904 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S
2905{
2906#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
76ad4f0e 2907 int recv_pkts, recv_bds, clean_count, err;
63380a1a 2908 int unused_count = hns3_desc_unused(ring);
e5597095
PL
2909 struct sk_buff *skb = ring->skb;
2910 int num;
76ad4f0e
S
2911
2912 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2913 rmb(); /* Make sure num taken effect before the other data is touched */
2914
2915 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2916 num -= unused_count;
63380a1a 2917 unused_count -= ring->pending_buf;
76ad4f0e
S
2918
2919 while (recv_pkts < budget && recv_bds < num) {
2920 /* Reuse or realloc buffers */
2921 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2922 hns3_nic_alloc_rx_buffers(ring,
2923 clean_count + unused_count);
2924 clean_count = 0;
e5597095
PL
2925 unused_count = hns3_desc_unused(ring) -
2926 ring->pending_buf;
76ad4f0e
S
2927 }
2928
2929 /* Poll one pkt */
e5597095 2930 err = hns3_handle_rx_bd(ring, &skb);
76ad4f0e
S
2931 if (unlikely(!skb)) /* This fault cannot be repaired */
2932 goto out;
2933
e5597095
PL
2934 if (err == -ENXIO) { /* Do not get FE for the packet */
2935 goto out;
2936 } else if (unlikely(err)) { /* Do jump the err */
2937 recv_bds += ring->pending_buf;
2938 clean_count += ring->pending_buf;
2939 ring->skb = NULL;
2940 ring->pending_buf = 0;
76ad4f0e
S
2941 continue;
2942 }
2943
d43e5aca 2944 rx_fn(ring, skb);
e5597095
PL
2945 recv_bds += ring->pending_buf;
2946 clean_count += ring->pending_buf;
2947 ring->skb = NULL;
2948 ring->pending_buf = 0;
76ad4f0e
S
2949
2950 recv_pkts++;
2951 }
2952
2953out:
2954 /* Make all data has been write before submit */
2955 if (clean_count + unused_count > 0)
9b2f3477 2956 hns3_nic_alloc_rx_buffers(ring, clean_count + unused_count);
76ad4f0e
S
2957
2958 return recv_pkts;
2959}
2960
4a43caf5 2961static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
76ad4f0e 2962{
4a43caf5
YL
2963#define HNS3_RX_LOW_BYTE_RATE 10000
2964#define HNS3_RX_MID_BYTE_RATE 20000
2965#define HNS3_RX_ULTRA_PACKET_RATE 40
2966
76ad4f0e 2967 enum hns3_flow_level_range new_flow_level;
4a43caf5
YL
2968 struct hns3_enet_tqp_vector *tqp_vector;
2969 int packets_per_msecs, bytes_per_msecs;
a95e1f86 2970 u32 time_passed_ms;
76ad4f0e 2971
4a43caf5 2972 tqp_vector = ring_group->ring->tqp_vector;
a95e1f86
FL
2973 time_passed_ms =
2974 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
a95e1f86
FL
2975 if (!time_passed_ms)
2976 return false;
2977
2978 do_div(ring_group->total_packets, time_passed_ms);
2979 packets_per_msecs = ring_group->total_packets;
2980
2981 do_div(ring_group->total_bytes, time_passed_ms);
2982 bytes_per_msecs = ring_group->total_bytes;
2983
4a43caf5 2984 new_flow_level = ring_group->coal.flow_level;
76ad4f0e 2985
4a43caf5
YL
2986 /* Simple throttlerate management
2987 * 0-10MB/s lower (50000 ints/s)
2988 * 10-20MB/s middle (20000 ints/s)
2989 * 20-1249MB/s high (18000 ints/s)
2990 * > 40000pps ultra (8000 ints/s)
2991 */
76ad4f0e
S
2992 switch (new_flow_level) {
2993 case HNS3_FLOW_LOW:
a95e1f86 2994 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S
2995 new_flow_level = HNS3_FLOW_MID;
2996 break;
2997 case HNS3_FLOW_MID:
a95e1f86 2998 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2999 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 3000 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S
3001 new_flow_level = HNS3_FLOW_LOW;
3002 break;
3003 case HNS3_FLOW_HIGH:
3004 case HNS3_FLOW_ULTRA:
3005 default:
a95e1f86 3006 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S
3007 new_flow_level = HNS3_FLOW_MID;
3008 break;
3009 }
3010
a95e1f86
FL
3011 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3012 &tqp_vector->rx_group == ring_group)
76ad4f0e
S
3013 new_flow_level = HNS3_FLOW_ULTRA;
3014
4a43caf5
YL
3015 ring_group->total_bytes = 0;
3016 ring_group->total_packets = 0;
3017 ring_group->coal.flow_level = new_flow_level;
3018
3019 return true;
3020}
3021
3022static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3023{
3024 struct hns3_enet_tqp_vector *tqp_vector;
3025 u16 new_int_gl;
3026
3027 if (!ring_group->ring)
3028 return false;
3029
3030 tqp_vector = ring_group->ring->tqp_vector;
3031 if (!tqp_vector->last_jiffies)
3032 return false;
3033
3034 if (ring_group->total_packets == 0) {
3035 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3036 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3037 return true;
3038 }
3039
3040 if (!hns3_get_new_flow_lvl(ring_group))
3041 return false;
3042
3043 new_int_gl = ring_group->coal.int_gl;
3044 switch (ring_group->coal.flow_level) {
76ad4f0e
S
3045 case HNS3_FLOW_LOW:
3046 new_int_gl = HNS3_INT_GL_50K;
3047 break;
3048 case HNS3_FLOW_MID:
3049 new_int_gl = HNS3_INT_GL_20K;
3050 break;
3051 case HNS3_FLOW_HIGH:
3052 new_int_gl = HNS3_INT_GL_18K;
3053 break;
3054 case HNS3_FLOW_ULTRA:
3055 new_int_gl = HNS3_INT_GL_8K;
3056 break;
3057 default:
3058 break;
3059 }
3060
9bc727a9
YL
3061 if (new_int_gl != ring_group->coal.int_gl) {
3062 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S
3063 return true;
3064 }
3065 return false;
3066}
3067
3068static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3069{
8b1ff1ea
FL
3070 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3071 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3072 bool rx_update, tx_update;
3073
7445565c
PL
3074 /* update param every 1000ms */
3075 if (time_before(jiffies,
3076 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 3077 return;
cd9d187b 3078
9bc727a9 3079 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL
3080 rx_update = hns3_get_new_int_gl(rx_group);
3081 if (rx_update)
3082 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 3083 rx_group->coal.int_gl);
8b1ff1ea
FL
3084 }
3085
9bc727a9 3086 if (tx_group->coal.gl_adapt_enable) {
9e50dc11 3087 tx_update = hns3_get_new_int_gl(tx_group);
8b1ff1ea
FL
3088 if (tx_update)
3089 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 3090 tx_group->coal.int_gl);
76ad4f0e 3091 }
cd9d187b 3092
a95e1f86 3093 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S
3094}
3095
3096static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3097{
ff0699e0 3098 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S
3099 struct hns3_enet_ring *ring;
3100 int rx_pkt_total = 0;
3101
3102 struct hns3_enet_tqp_vector *tqp_vector =
3103 container_of(napi, struct hns3_enet_tqp_vector, napi);
3104 bool clean_complete = true;
ceca4a5e 3105 int rx_budget = budget;
76ad4f0e 3106
ff0699e0
HT
3107 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3108 napi_complete(napi);
3109 return 0;
3110 }
3111
76ad4f0e
S
3112 /* Since the actual Tx work is minimal, we can give the Tx a larger
3113 * budget and be more aggressive about cleaning up the Tx descriptors.
3114 */
799997a3
PL
3115 hns3_for_each_ring(ring, tqp_vector->tx_group)
3116 hns3_clean_tx_ring(ring);
76ad4f0e
S
3117
3118 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL
3119 if (tqp_vector->num_tqps > 1)
3120 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S
3121
3122 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL
3123 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3124 hns3_rx_skb);
76ad4f0e
S
3125
3126 if (rx_cleaned >= rx_budget)
3127 clean_complete = false;
3128
3129 rx_pkt_total += rx_cleaned;
3130 }
3131
3132 tqp_vector->rx_group.total_packets += rx_pkt_total;
3133
3134 if (!clean_complete)
3135 return budget;
3136
531eba0f
HT
3137 if (napi_complete(napi) &&
3138 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT
3139 hns3_update_new_int_gl(tqp_vector);
3140 hns3_mask_vector_irq(tqp_vector, 1);
3141 }
76ad4f0e
S
3142
3143 return rx_pkt_total;
3144}
3145
3146static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3147 struct hnae3_ring_chain_node *head)
3148{
3149 struct pci_dev *pdev = tqp_vector->handle->pdev;
3150 struct hnae3_ring_chain_node *cur_chain = head;
3151 struct hnae3_ring_chain_node *chain;
3152 struct hns3_enet_ring *tx_ring;
3153 struct hns3_enet_ring *rx_ring;
3154
3155 tx_ring = tqp_vector->tx_group.ring;
3156 if (tx_ring) {
3157 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL
3158 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3159 HNAE3_RING_TYPE_TX);
3160 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3161 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S
3162
3163 cur_chain->next = NULL;
3164
3165 while (tx_ring->next) {
3166 tx_ring = tx_ring->next;
3167
3168 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3169 GFP_KERNEL);
3170 if (!chain)
73b907a0 3171 goto err_free_chain;
76ad4f0e
S
3172
3173 cur_chain->next = chain;
3174 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL
3175 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3176 HNAE3_RING_TYPE_TX);
3177 hnae3_set_field(chain->int_gl_idx,
3178 HNAE3_RING_GL_IDX_M,
3179 HNAE3_RING_GL_IDX_S,
3180 HNAE3_RING_GL_TX);
76ad4f0e
S
3181
3182 cur_chain = chain;
3183 }
3184 }
3185
3186 rx_ring = tqp_vector->rx_group.ring;
3187 if (!tx_ring && rx_ring) {
3188 cur_chain->next = NULL;
3189 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL
3190 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3191 HNAE3_RING_TYPE_RX);
3192 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3193 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S
3194
3195 rx_ring = rx_ring->next;
3196 }
3197
3198 while (rx_ring) {
3199 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3200 if (!chain)
73b907a0 3201 goto err_free_chain;
76ad4f0e
S
3202
3203 cur_chain->next = chain;
3204 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL
3205 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3206 HNAE3_RING_TYPE_RX);
3207 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3208 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 3209
76ad4f0e
S
3210 cur_chain = chain;
3211
3212 rx_ring = rx_ring->next;
3213 }
3214
3215 return 0;
73b907a0
HT
3216
3217err_free_chain:
3218 cur_chain = head->next;
3219 while (cur_chain) {
3220 chain = cur_chain->next;
cda69d24 3221 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT
3222 cur_chain = chain;
3223 }
cda69d24 3224 head->next = NULL;
73b907a0
HT
3225
3226 return -ENOMEM;
76ad4f0e
S
3227}
3228
3229static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3230 struct hnae3_ring_chain_node *head)
3231{
3232 struct pci_dev *pdev = tqp_vector->handle->pdev;
3233 struct hnae3_ring_chain_node *chain_tmp, *chain;
3234
3235 chain = head->next;
3236
3237 while (chain) {
3238 chain_tmp = chain->next;
3239 devm_kfree(&pdev->dev, chain);
3240 chain = chain_tmp;
3241 }
3242}
3243
3244static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3245 struct hns3_enet_ring *ring)
3246{
3247 ring->next = group->ring;
3248 group->ring = ring;
3249
3250 group->count++;
3251}
3252
874bff0b
PL
3253static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3254{
3255 struct pci_dev *pdev = priv->ae_handle->pdev;
3256 struct hns3_enet_tqp_vector *tqp_vector;
3257 int num_vectors = priv->vector_num;
3258 int numa_node;
3259 int vector_i;
3260
3261 numa_node = dev_to_node(&pdev->dev);
3262
3263 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3264 tqp_vector = &priv->tqp_vector[vector_i];
3265 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3266 &tqp_vector->affinity_mask);
3267 }
3268}
3269
76ad4f0e
S
3270static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3271{
3272 struct hnae3_ring_chain_node vector_ring_chain;
3273 struct hnae3_handle *h = priv->ae_handle;
3274 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3275 int ret = 0;
ece4bf46 3276 int i;
76ad4f0e 3277
874bff0b
PL
3278 hns3_nic_set_cpumask(priv);
3279
dd38c726
YL
3280 for (i = 0; i < priv->vector_num; i++) {
3281 tqp_vector = &priv->tqp_vector[i];
3282 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3283 tqp_vector->num_tqps = 0;
3284 }
76ad4f0e 3285
dd38c726
YL
3286 for (i = 0; i < h->kinfo.num_tqps; i++) {
3287 u16 vector_i = i % priv->vector_num;
3288 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S
3289
3290 tqp_vector = &priv->tqp_vector[vector_i];
3291
3292 hns3_add_ring_to_group(&tqp_vector->tx_group,
3293 priv->ring_data[i].ring);
3294
3295 hns3_add_ring_to_group(&tqp_vector->rx_group,
3296 priv->ring_data[i + tqp_num].ring);
3297
76ad4f0e
S
3298 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3299 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
dd38c726 3300 tqp_vector->num_tqps++;
76ad4f0e
S
3301 }
3302
dd38c726 3303 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S
3304 tqp_vector = &priv->tqp_vector[i];
3305
3306 tqp_vector->rx_group.total_bytes = 0;
3307 tqp_vector->rx_group.total_packets = 0;
3308 tqp_vector->tx_group.total_bytes = 0;
3309 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S
3310 tqp_vector->handle = h;
3311
3312 ret = hns3_get_vector_ring_chain(tqp_vector,
3313 &vector_ring_chain);
3314 if (ret)
cda69d24 3315 goto map_ring_fail;
76ad4f0e
S
3316
3317 ret = h->ae_algo->ops->map_ring_to_vector(h,
3318 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S
3319
3320 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3321
dd38c726 3322 if (ret)
ece4bf46 3323 goto map_ring_fail;
dd38c726 3324
76ad4f0e
S
3325 netif_napi_add(priv->netdev, &tqp_vector->napi,
3326 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3327 }
3328
dd38c726 3329 return 0;
ece4bf46
HT
3330
3331map_ring_fail:
3332 while (i--)
3333 netif_napi_del(&priv->tqp_vector[i].napi);
3334
3335 return ret;
dd38c726
YL
3336}
3337
3338static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3339{
75edb610
JS
3340#define HNS3_VECTOR_PF_MAX_NUM 64
3341
dd38c726
YL
3342 struct hnae3_handle *h = priv->ae_handle;
3343 struct hns3_enet_tqp_vector *tqp_vector;
3344 struct hnae3_vector_info *vector;
3345 struct pci_dev *pdev = h->pdev;
3346 u16 tqp_num = h->kinfo.num_tqps;
3347 u16 vector_num;
3348 int ret = 0;
3349 u16 i;
3350
3351 /* RSS size, cpu online and vector_num should be the same */
3352 /* Should consider 2p/4p later */
3353 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610
JS
3354 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3355
dd38c726
YL
3356 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3357 GFP_KERNEL);
3358 if (!vector)
3359 return -ENOMEM;
3360
9b2f3477 3361 /* save the actual available vector number */
dd38c726
YL
3362 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3363
3364 priv->vector_num = vector_num;
3365 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3366 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3367 GFP_KERNEL);
3368 if (!priv->tqp_vector) {
3369 ret = -ENOMEM;
3370 goto out;
3371 }
3372
3373 for (i = 0; i < priv->vector_num; i++) {
3374 tqp_vector = &priv->tqp_vector[i];
3375 tqp_vector->idx = i;
3376 tqp_vector->mask_addr = vector[i].io_addr;
3377 tqp_vector->vector_irq = vector[i].vector;
3378 hns3_vector_gl_rl_init(tqp_vector, priv);
3379 }
3380
76ad4f0e
S
3381out:
3382 devm_kfree(&pdev->dev, vector);
3383 return ret;
3384}
3385
dd38c726
YL
3386static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3387{
3388 group->ring = NULL;
3389 group->count = 0;
3390}
3391
e2152785 3392static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S
3393{
3394 struct hnae3_ring_chain_node vector_ring_chain;
3395 struct hnae3_handle *h = priv->ae_handle;
3396 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 3397 int i;
76ad4f0e
S
3398
3399 for (i = 0; i < priv->vector_num; i++) {
3400 tqp_vector = &priv->tqp_vector[i];
3401
2c9dd668
HT
3402 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3403 continue;
3404
e2152785 3405 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain);
76ad4f0e 3406
e2152785 3407 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 3408 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S
3409
3410 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3411
ae6017a7 3412 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
ae6017a7
HT
3413 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3414 free_irq(tqp_vector->vector_irq, tqp_vector);
3415 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
76ad4f0e
S
3416 }
3417
dd38c726
YL
3418 hns3_clear_ring_group(&tqp_vector->rx_group);
3419 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S
3420 netif_napi_del(&priv->tqp_vector[i].napi);
3421 }
dd38c726
YL
3422}
3423
3424static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3425{
3426 struct hnae3_handle *h = priv->ae_handle;
3427 struct pci_dev *pdev = h->pdev;
3428 int i, ret;
3429
3430 for (i = 0; i < priv->vector_num; i++) {
3431 struct hns3_enet_tqp_vector *tqp_vector;
3432
3433 tqp_vector = &priv->tqp_vector[i];
3434 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3435 if (ret)
3436 return ret;
3437 }
76ad4f0e 3438
dd38c726 3439 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S
3440 return 0;
3441}
3442
3443static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
ebaf1908 3444 unsigned int ring_type)
76ad4f0e
S
3445{
3446 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3447 int queue_num = priv->ae_handle->kinfo.num_tqps;
3448 struct pci_dev *pdev = priv->ae_handle->pdev;
3449 struct hns3_enet_ring *ring;
c0425944 3450 int desc_num;
76ad4f0e
S
3451
3452 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3453 if (!ring)
3454 return -ENOMEM;
3455
3456 if (ring_type == HNAE3_RING_TYPE_TX) {
c0425944 3457 desc_num = priv->ae_handle->kinfo.num_tx_desc;
76ad4f0e 3458 ring_data[q->tqp_index].ring = ring;
66b44730 3459 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S
3460 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3461 } else {
c0425944 3462 desc_num = priv->ae_handle->kinfo.num_rx_desc;
76ad4f0e 3463 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 3464 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S
3465 ring->io_base = q->io_base;
3466 }
3467
e4e87715 3468 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3469
76ad4f0e
S
3470 ring->tqp = q;
3471 ring->desc = NULL;
3472 ring->desc_cb = NULL;
3473 ring->dev = priv->dev;
3474 ring->desc_dma_addr = 0;
3475 ring->buf_size = q->buf_size;
2c9dd668 3476 ring->desc_num = desc_num;
76ad4f0e
S
3477 ring->next_to_use = 0;
3478 ring->next_to_clean = 0;
3479
3480 return 0;
3481}
3482
3483static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3484 struct hns3_nic_priv *priv)
3485{
3486 int ret;
3487
3488 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3489 if (ret)
3490 return ret;
3491
3492 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
73b907a0
HT
3493 if (ret) {
3494 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
76ad4f0e 3495 return ret;
73b907a0 3496 }
76ad4f0e
S
3497
3498 return 0;
3499}
3500
3501static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3502{
3503 struct hnae3_handle *h = priv->ae_handle;
3504 struct pci_dev *pdev = h->pdev;
3505 int i, ret;
3506
a86854d0
KC
3507 priv->ring_data = devm_kzalloc(&pdev->dev,
3508 array3_size(h->kinfo.num_tqps,
3509 sizeof(*priv->ring_data),
3510 2),
76ad4f0e
S
3511 GFP_KERNEL);
3512 if (!priv->ring_data)
3513 return -ENOMEM;
3514
3515 for (i = 0; i < h->kinfo.num_tqps; i++) {
3516 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3517 if (ret)
3518 goto err;
3519 }
3520
3521 return 0;
3522err:
73b907a0
HT
3523 while (i--) {
3524 devm_kfree(priv->dev, priv->ring_data[i].ring);
3525 devm_kfree(priv->dev,
3526 priv->ring_data[i + h->kinfo.num_tqps].ring);
3527 }
3528
76ad4f0e 3529 devm_kfree(&pdev->dev, priv->ring_data);
7b8f622e 3530 priv->ring_data = NULL;
76ad4f0e
S
3531 return ret;
3532}
3533
09f2af64
PL
3534static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3535{
3536 struct hnae3_handle *h = priv->ae_handle;
3537 int i;
3538
7b8f622e
HT
3539 if (!priv->ring_data)
3540 return;
3541
09f2af64
PL
3542 for (i = 0; i < h->kinfo.num_tqps; i++) {
3543 devm_kfree(priv->dev, priv->ring_data[i].ring);
3544 devm_kfree(priv->dev,
3545 priv->ring_data[i + h->kinfo.num_tqps].ring);
3546 }
3547 devm_kfree(priv->dev, priv->ring_data);
7b8f622e 3548 priv->ring_data = NULL;
09f2af64
PL
3549}
3550
76ad4f0e
S
3551static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3552{
3553 int ret;
3554
3555 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3556 return -EINVAL;
3557
77296bf6
YL
3558 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3559 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S
3560 if (!ring->desc_cb) {
3561 ret = -ENOMEM;
3562 goto out;
3563 }
3564
3565 ret = hns3_alloc_desc(ring);
3566 if (ret)
3567 goto out_with_desc_cb;
3568
3569 if (!HNAE3_IS_TX_RING(ring)) {
3570 ret = hns3_alloc_ring_buffers(ring);
3571 if (ret)
3572 goto out_with_desc;
3573 }
3574
3575 return 0;
3576
3577out_with_desc:
3578 hns3_free_desc(ring);
3579out_with_desc_cb:
77296bf6 3580 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S
3581 ring->desc_cb = NULL;
3582out:
3583 return ret;
3584}
3585
3586static void hns3_fini_ring(struct hns3_enet_ring *ring)
3587{
3588 hns3_free_desc(ring);
77296bf6 3589 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S
3590 ring->desc_cb = NULL;
3591 ring->next_to_clean = 0;
3592 ring->next_to_use = 0;
ac574b80
PL
3593 ring->pending_buf = 0;
3594 if (ring->skb) {
3595 dev_kfree_skb_any(ring->skb);
3596 ring->skb = NULL;
3597 }
76ad4f0e
S
3598}
3599
1db9b1bf 3600static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S
3601{
3602 int bd_size_type;
3603
3604 switch (buf_size) {
3605 case 512:
3606 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3607 break;
3608 case 1024:
3609 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3610 break;
3611 case 2048:
3612 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3613 break;
3614 case 4096:
3615 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3616 break;
3617 default:
3618 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3619 }
3620
3621 return bd_size_type;
3622}
3623
3624static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3625{
3626 dma_addr_t dma = ring->desc_dma_addr;
3627 struct hnae3_queue *q = ring->tqp;
3628
3629 if (!HNAE3_IS_TX_RING(ring)) {
9b2f3477 3630 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
76ad4f0e
S
3631 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3632 (u32)((dma >> 31) >> 1));
3633
3634 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3635 hns3_buf_size2type(ring->buf_size));
3636 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3637 ring->desc_num / 8 - 1);
3638
3639 } else {
3640 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3641 (u32)dma);
3642 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3643 (u32)((dma >> 31) >> 1));
3644
76ad4f0e
S
3645 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3646 ring->desc_num / 8 - 1);
3647 }
3648}
3649
1c772154
YL
3650static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3651{
3652 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3653 int i;
3654
3655 for (i = 0; i < HNAE3_MAX_TC; i++) {
3656 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3657 int j;
3658
3659 if (!tc_info->enable)
3660 continue;
3661
3662 for (j = 0; j < tc_info->tqp_count; j++) {
3663 struct hnae3_queue *q;
3664
3665 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3666 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3667 tc_info->tc);
3668 }
3669 }
3670}
3671
5668abda 3672int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S
3673{
3674 struct hnae3_handle *h = priv->ae_handle;
3675 int ring_num = h->kinfo.num_tqps * 2;
3676 int i, j;
3677 int ret;
3678
3679 for (i = 0; i < ring_num; i++) {
3680 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3681 if (ret) {
3682 dev_err(priv->dev,
3683 "Alloc ring memory fail! ret=%d\n", ret);
3684 goto out_when_alloc_ring_memory;
3685 }
3686
76ad4f0e
S
3687 u64_stats_init(&priv->ring_data[i].ring->syncp);
3688 }
3689
3690 return 0;
3691
3692out_when_alloc_ring_memory:
3693 for (j = i - 1; j >= 0; j--)
ee83f776 3694 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S
3695
3696 return -ENOMEM;
3697}
3698
5668abda 3699int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S
3700{
3701 struct hnae3_handle *h = priv->ae_handle;
3702 int i;
3703
3704 for (i = 0; i < h->kinfo.num_tqps; i++) {
76ad4f0e
S
3705 hns3_fini_ring(priv->ring_data[i].ring);
3706 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3707 }
76ad4f0e
S
3708 return 0;
3709}
3710
3711/* Set mac addr if it is configured. or leave it to the AE driver */
7fa6be4f 3712static int hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S
3713{
3714 struct hns3_nic_priv *priv = netdev_priv(netdev);
3715 struct hnae3_handle *h = priv->ae_handle;
3716 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 3717 int ret = 0;
76ad4f0e 3718
f09555ff 3719 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S
3720 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3721 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3722 }
3723
3724 /* Check if the MAC address is valid, if not get a random one */
3725 if (!is_valid_ether_addr(netdev->dev_addr)) {
3726 eth_hw_addr_random(netdev);
3727 dev_warn(priv->dev, "using random MAC address %pM\n",
3728 netdev->dev_addr);
76ad4f0e 3729 }
139e8792
L
3730
3731 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 3732 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3733
7fa6be4f 3734 return ret;
76ad4f0e
S
3735}
3736
c8a8045b
HT
3737static int hns3_init_phy(struct net_device *netdev)
3738{
3739 struct hnae3_handle *h = hns3_get_handle(netdev);
3740 int ret = 0;
3741
3742 if (h->ae_algo->ops->mac_connect_phy)
3743 ret = h->ae_algo->ops->mac_connect_phy(h);
3744
3745 return ret;
3746}
3747
3748static void hns3_uninit_phy(struct net_device *netdev)
3749{
3750 struct hnae3_handle *h = hns3_get_handle(netdev);
3751
3752 if (h->ae_algo->ops->mac_disconnect_phy)
3753 h->ae_algo->ops->mac_disconnect_phy(h);
3754}
3755
6871af29
JS
3756static int hns3_restore_fd_rules(struct net_device *netdev)
3757{
3758 struct hnae3_handle *h = hns3_get_handle(netdev);
3759 int ret = 0;
3760
3761 if (h->ae_algo->ops->restore_fd_rules)
3762 ret = h->ae_algo->ops->restore_fd_rules(h);
3763
3764 return ret;
3765}
3766
3767static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3768{
3769 struct hnae3_handle *h = hns3_get_handle(netdev);
3770
3771 if (h->ae_algo->ops->del_all_fd_entries)
3772 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3773}
3774
a6d818e3
YL
3775static int hns3_client_start(struct hnae3_handle *handle)
3776{
3777 if (!handle->ae_algo->ops->client_start)
3778 return 0;
3779
3780 return handle->ae_algo->ops->client_start(handle);
3781}
3782
3783static void hns3_client_stop(struct hnae3_handle *handle)
3784{
3785 if (!handle->ae_algo->ops->client_stop)
3786 return;
3787
3788 handle->ae_algo->ops->client_stop(handle);
3789}
3790
bb87be87
YL
3791static void hns3_info_show(struct hns3_nic_priv *priv)
3792{
3793 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3794
3795 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3796 dev_info(priv->dev, "Task queue pairs numbers: %d\n", kinfo->num_tqps);
3797 dev_info(priv->dev, "RSS size: %d\n", kinfo->rss_size);
3798 dev_info(priv->dev, "Allocated RSS size: %d\n", kinfo->req_rss_size);
3799 dev_info(priv->dev, "RX buffer length: %d\n", kinfo->rx_buf_len);
3800 dev_info(priv->dev, "Desc num per TX queue: %d\n", kinfo->num_tx_desc);
3801 dev_info(priv->dev, "Desc num per RX queue: %d\n", kinfo->num_rx_desc);
3802 dev_info(priv->dev, "Total number of enabled TCs: %d\n", kinfo->num_tc);
3803 dev_info(priv->dev, "Max mtu size: %d\n", priv->netdev->max_mtu);
3804}
3805
76ad4f0e
S
3806static int hns3_client_init(struct hnae3_handle *handle)
3807{
3808 struct pci_dev *pdev = handle->pdev;
0d43bf45 3809 u16 alloc_tqps, max_rss_size;
76ad4f0e
S
3810 struct hns3_nic_priv *priv;
3811 struct net_device *netdev;
3812 int ret;
3813
0d43bf45
HT
3814 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3815 &max_rss_size);
3816 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S
3817 if (!netdev)
3818 return -ENOMEM;
3819
3820 priv = netdev_priv(netdev);
3821 priv->dev = &pdev->dev;
3822 priv->netdev = netdev;
3823 priv->ae_handle = handle;
f8fa222c 3824 priv->tx_timeout_count = 0;
b7b585c2 3825 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 3826
bb87be87
YL
3827 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3828
76ad4f0e
S
3829 handle->kinfo.netdev = netdev;
3830 handle->priv = (void *)priv;
3831
f09555ff 3832 hns3_init_mac_addr(netdev, true);
76ad4f0e
S
3833
3834 hns3_set_default_feature(netdev);
3835
3836 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3837 netdev->priv_flags |= IFF_UNICAST_FLT;
3838 netdev->netdev_ops = &hns3_nic_netdev_ops;
3839 SET_NETDEV_DEV(netdev, &pdev->dev);
3840 hns3_ethtool_set_ops(netdev);
76ad4f0e
S
3841
3842 /* Carrier off reporting is important to ethtool even BEFORE open */
3843 netif_carrier_off(netdev);
3844
3845 ret = hns3_get_ring_config(priv);
3846 if (ret) {
3847 ret = -ENOMEM;
3848 goto out_get_ring_cfg;
3849 }
3850
dd38c726
YL
3851 ret = hns3_nic_alloc_vector_data(priv);
3852 if (ret) {
3853 ret = -ENOMEM;
3854 goto out_alloc_vector_data;
3855 }
3856
76ad4f0e
S
3857 ret = hns3_nic_init_vector_data(priv);
3858 if (ret) {
3859 ret = -ENOMEM;
3860 goto out_init_vector_data;
3861 }
3862
3863 ret = hns3_init_all_ring(priv);
3864 if (ret) {
3865 ret = -ENOMEM;
3866 goto out_init_ring_data;
3867 }
3868
c8a8045b
HT
3869 ret = hns3_init_phy(netdev);
3870 if (ret)
3871 goto out_init_phy;
3872
76ad4f0e
S
3873 ret = register_netdev(netdev);
3874 if (ret) {
3875 dev_err(priv->dev, "probe register netdev fail!\n");
3876 goto out_reg_netdev_fail;
3877 }
3878
a6d818e3
YL
3879 ret = hns3_client_start(handle);
3880 if (ret) {
3881 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
bf6de231 3882 goto out_client_start;
a6d818e3
YL
3883 }
3884
986743db
YL
3885 hns3_dcbnl_setup(handle);
3886
b2292360 3887 hns3_dbg_init(handle);
3888
a0b43717 3889 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 3890 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 3891
814da63c
HT
3892 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3893
bb87be87
YL
3894 if (netif_msg_drv(handle))
3895 hns3_info_show(priv);
3896
76ad4f0e
S
3897 return ret;
3898
18655128
HT
3899out_client_start:
3900 unregister_netdev(netdev);
76ad4f0e 3901out_reg_netdev_fail:
c8a8045b
HT
3902 hns3_uninit_phy(netdev);
3903out_init_phy:
3904 hns3_uninit_all_ring(priv);
76ad4f0e 3905out_init_ring_data:
e2152785 3906 hns3_nic_uninit_vector_data(priv);
76ad4f0e 3907out_init_vector_data:
dd38c726
YL
3908 hns3_nic_dealloc_vector_data(priv);
3909out_alloc_vector_data:
3910 priv->ring_data = NULL;
76ad4f0e
S
3911out_get_ring_cfg:
3912 priv->ae_handle = NULL;
3913 free_netdev(netdev);
3914 return ret;
3915}
3916
3917static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3918{
3919 struct net_device *netdev = handle->kinfo.netdev;
3920 struct hns3_nic_priv *priv = netdev_priv(netdev);
3921 int ret;
3922
f05e2109
JS
3923 hns3_remove_hw_addr(netdev);
3924
76ad4f0e
S
3925 if (netdev->reg_state != NETREG_UNINITIALIZED)
3926 unregister_netdev(netdev);
3927
eb32c896
HT
3928 hns3_client_stop(handle);
3929
0d2f68c7
HT
3930 hns3_uninit_phy(netdev);
3931
814da63c
HT
3932 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3933 netdev_warn(netdev, "already uninitialized\n");
3934 goto out_netdev_free;
3935 }
3936
dc5e6064
JS
3937 hns3_del_all_fd_rules(netdev, true);
3938
f96315f2 3939 hns3_clear_all_ring(handle, true);
7b763f3f 3940
e2152785 3941 hns3_nic_uninit_vector_data(priv);
76ad4f0e 3942
dd38c726
YL
3943 ret = hns3_nic_dealloc_vector_data(priv);
3944 if (ret)
3945 netdev_err(netdev, "dealloc vector error\n");
3946
76ad4f0e
S
3947 ret = hns3_uninit_all_ring(priv);
3948 if (ret)
3949 netdev_err(netdev, "uninit ring error\n");
3950
ec777890
YL
3951 hns3_put_ring_config(priv);
3952
b2292360 3953 hns3_dbg_uninit(handle);
3954
814da63c 3955out_netdev_free:
76ad4f0e
S
3956 free_netdev(netdev);
3957}
3958
3959static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3960{
3961 struct net_device *netdev = handle->kinfo.netdev;
3962
3963 if (!netdev)
3964 return;
3965
3966 if (linkup) {
3967 netif_carrier_on(netdev);
3968 netif_tx_wake_all_queues(netdev);
bb87be87
YL
3969 if (netif_msg_link(handle))
3970 netdev_info(netdev, "link up\n");
76ad4f0e
S
3971 } else {
3972 netif_carrier_off(netdev);
3973 netif_tx_stop_all_queues(netdev);
bb87be87
YL
3974 if (netif_msg_link(handle))
3975 netdev_info(netdev, "link down\n");
76ad4f0e
S
3976 }
3977}
3978
9df8f79a
YL
3979static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3980{
3981 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3982 struct net_device *ndev = kinfo->netdev;
9df8f79a
YL
3983
3984 if (tc > HNAE3_MAX_TC)
3985 return -EINVAL;
3986
3987 if (!ndev)
3988 return -ENODEV;
3989
a1ef124e 3990 return hns3_nic_set_real_num_queue(ndev);
9df8f79a
YL
3991}
3992
7fa6be4f 3993static int hns3_recover_hw_addr(struct net_device *ndev)
bb6b94a8
L
3994{
3995 struct netdev_hw_addr_list *list;
3996 struct netdev_hw_addr *ha, *tmp;
7fa6be4f 3997 int ret = 0;
bb6b94a8 3998
389775a6 3999 netif_addr_lock_bh(ndev);
bb6b94a8
L
4000 /* go through and sync uc_addr entries to the device */
4001 list = &ndev->uc;
7fa6be4f
HT
4002 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4003 ret = hns3_nic_uc_sync(ndev, ha->addr);
4004 if (ret)
389775a6 4005 goto out;
7fa6be4f 4006 }
bb6b94a8
L
4007
4008 /* go through and sync mc_addr entries to the device */
4009 list = &ndev->mc;
7fa6be4f
HT
4010 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4011 ret = hns3_nic_mc_sync(ndev, ha->addr);
4012 if (ret)
389775a6 4013 goto out;
7fa6be4f
HT
4014 }
4015
389775a6
JS
4016out:
4017 netif_addr_unlock_bh(ndev);
7fa6be4f 4018 return ret;
bb6b94a8
L
4019}
4020
f05e2109
JS
4021static void hns3_remove_hw_addr(struct net_device *netdev)
4022{
4023 struct netdev_hw_addr_list *list;
4024 struct netdev_hw_addr *ha, *tmp;
4025
4026 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
4027
389775a6 4028 netif_addr_lock_bh(netdev);
f05e2109
JS
4029 /* go through and unsync uc_addr entries to the device */
4030 list = &netdev->uc;
4031 list_for_each_entry_safe(ha, tmp, &list->list, list)
4032 hns3_nic_uc_unsync(netdev, ha->addr);
4033
4034 /* go through and unsync mc_addr entries to the device */
4035 list = &netdev->mc;
4036 list_for_each_entry_safe(ha, tmp, &list->list, list)
4037 if (ha->refcount > 1)
4038 hns3_nic_mc_unsync(netdev, ha->addr);
389775a6
JS
4039
4040 netif_addr_unlock_bh(netdev);
f05e2109
JS
4041}
4042
beebca3a 4043static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 4044{
beebca3a 4045 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 4046 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
beebca3a
YL
4047 hns3_free_buffer_detach(ring, ring->next_to_clean);
4048 ring_ptr_move_fw(ring, next_to_clean);
4049 }
4050}
4051
7b763f3f
FL
4052static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4053{
4054 struct hns3_desc_cb res_cbs;
4055 int ret;
4056
4057 while (ring->next_to_use != ring->next_to_clean) {
4058 /* When a buffer is not reused, it's memory has been
4059 * freed in hns3_handle_rx_bd or will be freed by
4060 * stack, so we need to replace the buffer here.
4061 */
4062 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4063 ret = hns3_reserve_buffer_map(ring, &res_cbs);
4064 if (ret) {
4065 u64_stats_update_begin(&ring->syncp);
4066 ring->stats.sw_err_cnt++;
4067 u64_stats_update_end(&ring->syncp);
4068 /* if alloc new buffer fail, exit directly
4069 * and reclear in up flow.
4070 */
4071 netdev_warn(ring->tqp->handle->kinfo.netdev,
4072 "reserve buffer map failed, ret = %d\n",
4073 ret);
4074 return ret;
4075 }
9b2f3477 4076 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
7b763f3f
FL
4077 }
4078 ring_ptr_move_fw(ring, next_to_use);
4079 }
4080
cc5ff6e9
PL
4081 /* Free the pending skb in rx ring */
4082 if (ring->skb) {
4083 dev_kfree_skb_any(ring->skb);
4084 ring->skb = NULL;
4085 ring->pending_buf = 0;
4086 }
4087
7b763f3f
FL
4088 return 0;
4089}
4090
4091static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 4092{
beebca3a
YL
4093 while (ring->next_to_use != ring->next_to_clean) {
4094 /* When a buffer is not reused, it's memory has been
4095 * freed in hns3_handle_rx_bd or will be freed by
4096 * stack, so only need to unmap the buffer here.
4097 */
4098 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4099 hns3_unmap_buffer(ring,
4100 &ring->desc_cb[ring->next_to_use]);
4101 ring->desc_cb[ring->next_to_use].dma = 0;
4102 }
4103
4104 ring_ptr_move_fw(ring, next_to_use);
4105 }
bb6b94a8
L
4106}
4107
f96315f2 4108static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
bb6b94a8
L
4109{
4110 struct net_device *ndev = h->kinfo.netdev;
4111 struct hns3_nic_priv *priv = netdev_priv(ndev);
4112 u32 i;
4113
4114 for (i = 0; i < h->kinfo.num_tqps; i++) {
bb6b94a8
L
4115 struct hns3_enet_ring *ring;
4116
4117 ring = priv->ring_data[i].ring;
beebca3a 4118 hns3_clear_tx_ring(ring);
bb6b94a8
L
4119
4120 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
7b763f3f
FL
4121 /* Continue to clear other rings even if clearing some
4122 * rings failed.
4123 */
f96315f2
HT
4124 if (force)
4125 hns3_force_clear_rx_ring(ring);
4126 else
4127 hns3_clear_rx_ring(ring);
bb6b94a8
L
4128 }
4129}
4130
7b763f3f
FL
4131int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4132{
4133 struct net_device *ndev = h->kinfo.netdev;
4134 struct hns3_nic_priv *priv = netdev_priv(ndev);
4135 struct hns3_enet_ring *rx_ring;
4136 int i, j;
4137 int ret;
4138
4139 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT
4140 ret = h->ae_algo->ops->reset_queue(h, i);
4141 if (ret)
4142 return ret;
4143
7b763f3f
FL
4144 hns3_init_ring_hw(priv->ring_data[i].ring);
4145
4146 /* We need to clear tx ring here because self test will
4147 * use the ring and will not run down before up
4148 */
4149 hns3_clear_tx_ring(priv->ring_data[i].ring);
4150 priv->ring_data[i].ring->next_to_clean = 0;
4151 priv->ring_data[i].ring->next_to_use = 0;
4152
4153 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
4154 hns3_init_ring_hw(rx_ring);
4155 ret = hns3_clear_rx_ring(rx_ring);
4156 if (ret)
4157 return ret;
4158
4159 /* We can not know the hardware head and tail when this
4160 * function is called in reset flow, so we reuse all desc.
4161 */
4162 for (j = 0; j < rx_ring->desc_num; j++)
4163 hns3_reuse_buffer(rx_ring, j);
4164
4165 rx_ring->next_to_clean = 0;
4166 rx_ring->next_to_use = 0;
4167 }
4168
1c772154
YL
4169 hns3_init_tx_ring_tc(priv);
4170
7b763f3f
FL
4171 return 0;
4172}
4173
e4fd7502
HT
4174static void hns3_store_coal(struct hns3_nic_priv *priv)
4175{
4176 /* ethtool only support setting and querying one coal
4177 * configuation for now, so save the vector 0' coal
4178 * configuation here in order to restore it.
4179 */
4180 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4181 sizeof(struct hns3_enet_coalesce));
4182 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4183 sizeof(struct hns3_enet_coalesce));
4184}
4185
4186static void hns3_restore_coal(struct hns3_nic_priv *priv)
4187{
4188 u16 vector_num = priv->vector_num;
4189 int i;
4190
4191 for (i = 0; i < vector_num; i++) {
4192 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4193 sizeof(struct hns3_enet_coalesce));
4194 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4195 sizeof(struct hns3_enet_coalesce));
4196 }
4197}
4198
bb6b94a8
L
4199static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4200{
7edff533 4201 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
bb6b94a8
L
4202 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4203 struct net_device *ndev = kinfo->netdev;
257e4f29
HT
4204 struct hns3_nic_priv *priv = netdev_priv(ndev);
4205
4206 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4207 return 0;
bb6b94a8 4208
7edff533
HT
4209 /* it is cumbersome for hardware to pick-and-choose entries for deletion
4210 * from table space. Hence, for function reset software intervention is
4211 * required to delete the entries
4212 */
4213 if (hns3_dev_ongoing_func_reset(ae_dev)) {
4214 hns3_remove_hw_addr(ndev);
4215 hns3_del_all_fd_rules(ndev, false);
4216 }
4217
bb6b94a8 4218 if (!netif_running(ndev))
6b1385cc 4219 return 0;
bb6b94a8
L
4220
4221 return hns3_nic_net_stop(ndev);
4222}
4223
4224static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4225{
4226 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 4227 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L
4228 int ret = 0;
4229
e8884027
HT
4230 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4231
bb6b94a8 4232 if (netif_running(kinfo->netdev)) {
e8884027 4233 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4234 if (ret) {
e8884027 4235 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8 4236 netdev_err(kinfo->netdev,
9b2f3477 4237 "net up fail, ret=%d!\n", ret);
bb6b94a8
L
4238 return ret;
4239 }
bb6b94a8
L
4240 }
4241
4242 return ret;
4243}
4244
4245static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4246{
4247 struct net_device *netdev = handle->kinfo.netdev;
4248 struct hns3_nic_priv *priv = netdev_priv(netdev);
4249 int ret;
4250
bb6b94a8
L
4251 /* Carrier off reporting is important to ethtool even BEFORE open */
4252 netif_carrier_off(netdev);
4253
2c9dd668 4254 ret = hns3_get_ring_config(priv);
862d969a
HT
4255 if (ret)
4256 return ret;
4257
2c9dd668
HT
4258 ret = hns3_nic_alloc_vector_data(priv);
4259 if (ret)
4260 goto err_put_ring;
4261
e4fd7502
HT
4262 hns3_restore_coal(priv);
4263
bb6b94a8
L
4264 ret = hns3_nic_init_vector_data(priv);
4265 if (ret)
862d969a 4266 goto err_dealloc_vector;
bb6b94a8
L
4267
4268 ret = hns3_init_all_ring(priv);
862d969a
HT
4269 if (ret)
4270 goto err_uninit_vector;
bb6b94a8 4271
cd513a69
HT
4272 ret = hns3_client_start(handle);
4273 if (ret) {
4274 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4275 goto err_uninit_ring;
4276 }
4277
814da63c
HT
4278 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4279
862d969a
HT
4280 return ret;
4281
cd513a69
HT
4282err_uninit_ring:
4283 hns3_uninit_all_ring(priv);
862d969a
HT
4284err_uninit_vector:
4285 hns3_nic_uninit_vector_data(priv);
862d969a
HT
4286err_dealloc_vector:
4287 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT
4288err_put_ring:
4289 hns3_put_ring_config(priv);
862d969a 4290
bb6b94a8
L
4291 return ret;
4292}
4293
1f609492
YL
4294static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4295{
4296 struct net_device *netdev = handle->kinfo.netdev;
4297 bool vlan_filter_enable;
4298 int ret;
4299
4300 ret = hns3_init_mac_addr(netdev, false);
4301 if (ret)
4302 return ret;
4303
4304 ret = hns3_recover_hw_addr(netdev);
4305 if (ret)
4306 return ret;
4307
4308 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4309 if (ret)
4310 return ret;
4311
4312 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4313 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4314
b524b38f
JS
4315 if (handle->ae_algo->ops->restore_vlan_table)
4316 handle->ae_algo->ops->restore_vlan_table(handle);
1f609492
YL
4317
4318 return hns3_restore_fd_rules(netdev);
4319}
4320
bb6b94a8
L
4321static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4322{
4323 struct net_device *netdev = handle->kinfo.netdev;
4324 struct hns3_nic_priv *priv = netdev_priv(netdev);
4325 int ret;
4326
1eeb3367 4327 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT
4328 netdev_warn(netdev, "already uninitialized\n");
4329 return 0;
4330 }
4331
f96315f2
HT
4332 hns3_clear_all_ring(handle, true);
4333 hns3_reset_tx_queue(priv->ae_handle);
bb6b94a8 4334
e2152785 4335 hns3_nic_uninit_vector_data(priv);
bb6b94a8 4336
e4fd7502
HT
4337 hns3_store_coal(priv);
4338
862d969a
HT
4339 ret = hns3_nic_dealloc_vector_data(priv);
4340 if (ret)
4341 netdev_err(netdev, "dealloc vector error\n");
4342
bb6b94a8
L
4343 ret = hns3_uninit_all_ring(priv);
4344 if (ret)
4345 netdev_err(netdev, "uninit ring error\n");
4346
2c9dd668 4347 hns3_put_ring_config(priv);
2c9dd668 4348
bb6b94a8
L
4349 return ret;
4350}
4351
4352static int hns3_reset_notify(struct hnae3_handle *handle,
4353 enum hnae3_reset_notify_type type)
4354{
4355 int ret = 0;
4356
4357 switch (type) {
4358 case HNAE3_UP_CLIENT:
e1586241
SM
4359 ret = hns3_reset_notify_up_enet(handle);
4360 break;
bb6b94a8
L
4361 case HNAE3_DOWN_CLIENT:
4362 ret = hns3_reset_notify_down_enet(handle);
4363 break;
4364 case HNAE3_INIT_CLIENT:
4365 ret = hns3_reset_notify_init_enet(handle);
4366 break;
4367 case HNAE3_UNINIT_CLIENT:
4368 ret = hns3_reset_notify_uninit_enet(handle);
4369 break;
1f609492
YL
4370 case HNAE3_RESTORE_CLIENT:
4371 ret = hns3_reset_notify_restore_enet(handle);
4372 break;
bb6b94a8
L
4373 default:
4374 break;
4375 }
4376
4377 return ret;
4378}
4379
c7757f7d
PL
4380static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4381 bool rxfh_configured)
4382{
4383 int ret;
4384
4385 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4386 rxfh_configured);
4387 if (ret) {
4388 dev_err(&handle->pdev->dev,
4389 "Change tqp num(%u) fail.\n", new_tqp_num);
4390 return ret;
4391 }
4392
4393 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4394 if (ret)
4395 return ret;
4396
4397 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4398 if (ret)
4399 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4400
4401 return ret;
4402}
4403
09f2af64
PL
4404int hns3_set_channels(struct net_device *netdev,
4405 struct ethtool_channels *ch)
4406{
09f2af64
PL
4407 struct hnae3_handle *h = hns3_get_handle(netdev);
4408 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 4409 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL
4410 u32 new_tqp_num = ch->combined_count;
4411 u16 org_tqp_num;
4412 int ret;
4413
4414 if (ch->rx_count || ch->tx_count)
4415 return -EINVAL;
4416
678335a1 4417 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 4418 new_tqp_num < 1) {
09f2af64 4419 dev_err(&netdev->dev,
c78b5b6c 4420 "Change tqps fail, the tqp range is from 1 to %d",
678335a1 4421 hns3_get_max_available_channels(h));
09f2af64
PL
4422 return -EINVAL;
4423 }
4424
c78b5b6c 4425 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL
4426 return 0;
4427
65749f73
HT
4428 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4429 if (ret)
4430 return ret;
dd38c726 4431
65749f73
HT
4432 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4433 if (ret)
4434 return ret;
09f2af64
PL
4435
4436 org_tqp_num = h->kinfo.num_tqps;
c7757f7d 4437 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
09f2af64 4438 if (ret) {
c7757f7d
PL
4439 int ret1;
4440
4441 netdev_warn(netdev,
4442 "Change channels fail, revert to old value\n");
4443 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4444 if (ret1) {
4445 netdev_err(netdev,
4446 "revert to old channel fail\n");
4447 return ret1;
09f2af64 4448 }
c7757f7d 4449
65749f73 4450 return ret;
c7757f7d 4451 }
09f2af64 4452
c7757f7d 4453 return 0;
09f2af64
PL
4454}
4455
1db9b1bf 4456static const struct hnae3_client_ops client_ops = {
76ad4f0e
S
4457 .init_instance = hns3_client_init,
4458 .uninit_instance = hns3_client_uninit,
4459 .link_status_change = hns3_link_status_change,
9df8f79a 4460 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4461 .reset_notify = hns3_reset_notify,
76ad4f0e
S
4462};
4463
4464/* hns3_init_module - Driver registration routine
4465 * hns3_init_module is the first routine called when the driver is
4466 * loaded. All it does is register with the PCI subsystem.
4467 */
4468static int __init hns3_init_module(void)
4469{
4470 int ret;
4471
4472 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4473 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4474
4475 client.type = HNAE3_CLIENT_KNIC;
4476 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4477 hns3_driver_name);
4478
4479 client.ops = &client_ops;
4480
13562d1f
XW
4481 INIT_LIST_HEAD(&client.node);
4482
b2292360 4483 hns3_dbg_register_debugfs(hns3_driver_name);
4484
76ad4f0e
S
4485 ret = hnae3_register_client(&client);
4486 if (ret)
b2292360 4487 goto err_reg_client;
76ad4f0e
S
4488
4489 ret = pci_register_driver(&hns3_driver);
4490 if (ret)
b2292360 4491 goto err_reg_driver;
76ad4f0e
S
4492
4493 return ret;
b2292360 4494
4495err_reg_driver:
4496 hnae3_unregister_client(&client);
4497err_reg_client:
4498 hns3_dbg_unregister_debugfs();
4499 return ret;
76ad4f0e
S
4500}
4501module_init(hns3_init_module);
4502
4503/* hns3_exit_module - Driver exit cleanup routine
4504 * hns3_exit_module is called just before the driver is removed
4505 * from memory.
4506 */
4507static void __exit hns3_exit_module(void)
4508{
4509 pci_unregister_driver(&hns3_driver);
4510 hnae3_unregister_client(&client);
b2292360 4511 hns3_dbg_unregister_debugfs();
76ad4f0e
S
4512}
4513module_exit(hns3_exit_module);
4514
4515MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4516MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4517MODULE_LICENSE("GPL");
4518MODULE_ALIAS("pci:hns-nic");
3c7624d8 4519MODULE_VERSION(HNS3_MOD_VERSION);