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net: hns3: Remove redundant hclge_get_port_type()
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
ef57c40f
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
7#include <linux/if_vlan.h>
8#include <linux/ip.h>
9#include <linux/ipv6.h>
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/skbuff.h>
13#include <linux/sctp.h>
14#include <linux/vermagic.h>
15#include <net/gre.h>
30d240df 16#include <net/pkt_cls.h>
76ad4f0e
S		 17#include <net/vxlan.h>
18
19#include "hnae3.h"
20#include "hns3_enet.h"
21
e32a805a
FL		 22static void hns3_clear_all_ring(struct hnae3_handle *h);
23static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
24
1db9b1bf 25static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 26const char hns3_driver_version[] = VERMAGIC_STRING;
27static const char hns3_driver_string[] =
28 "Hisilicon Ethernet Network Driver for Hip08 Family";
29static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
30static struct hnae3_client client;
31
32/* hns3_pci_tbl - PCI Device ID Table
33 *
34 * Last entry must be all 0s
35 *
36 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
37 * Class, Class Mask, private data (not used) }
38 */
39static const struct pci_device_id hns3_pci_tbl[] = {
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 43 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 45 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 47 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 49 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 51 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
a9c89a3f 52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
f4e4e86c
JS		 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 55 /* required last entry */
56 {0, }
57};
58MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
59
5a8b1a40 60static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 61{
5a8b1a40 62 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e
S		 63
64 napi_schedule(&tqp_vector->napi);
65
66 return IRQ_HANDLED;
67}
68
15040788
PL		 69/* This callback function is used to set affinity changes to the irq affinity
70 * masks when the irq_set_affinity_notifier function is used.
71 */
72static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify,
73 const cpumask_t *mask)
74{
75 struct hns3_enet_tqp_vector *tqp_vectors =
76 container_of(notify, struct hns3_enet_tqp_vector,
77 affinity_notify);
78
79 tqp_vectors->affinity_mask = *mask;
80}
81
82static void hns3_nic_irq_affinity_release(struct kref *ref)
83{
84}
85
76ad4f0e
S		 86static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
87{
88 struct hns3_enet_tqp_vector *tqp_vectors;
89 unsigned int i;
90
91 for (i = 0; i < priv->vector_num; i++) {
92 tqp_vectors = &priv->tqp_vector[i];
93
94 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
95 continue;
96
15040788
PL		 97 /* clear the affinity notifier and affinity mask */
98 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL);
99 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
100
76ad4f0e
S		 101 /* release the irq resource */
102 free_irq(tqp_vectors->vector_irq, tqp_vectors);
103 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
104 }
105}
106
107static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
108{
109 struct hns3_enet_tqp_vector *tqp_vectors;
110 int txrx_int_idx = 0;
111 int rx_int_idx = 0;
112 int tx_int_idx = 0;
113 unsigned int i;
114 int ret;
115
116 for (i = 0; i < priv->vector_num; i++) {
117 tqp_vectors = &priv->tqp_vector[i];
118
119 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
120 continue;
121
122 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
123 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
124 "%s-%s-%d", priv->netdev->name, "TxRx",
125 txrx_int_idx++);
126 txrx_int_idx++;
127 } else if (tqp_vectors->rx_group.ring) {
128 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
129 "%s-%s-%d", priv->netdev->name, "Rx",
130 rx_int_idx++);
131 } else if (tqp_vectors->tx_group.ring) {
132 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
133 "%s-%s-%d", priv->netdev->name, "Tx",
134 tx_int_idx++);
135 } else {
136 /* Skip this unused q_vector */
137 continue;
138 }
139
140 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
141
142 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
143 tqp_vectors->name,
144 tqp_vectors);
145 if (ret) {
146 netdev_err(priv->netdev, "request irq(%d) fail\n",
147 tqp_vectors->vector_irq);
148 return ret;
149 }
150
15040788
PL		 151 tqp_vectors->affinity_notify.notify =
152 hns3_nic_irq_affinity_notify;
153 tqp_vectors->affinity_notify.release =
154 hns3_nic_irq_affinity_release;
155 irq_set_affinity_notifier(tqp_vectors->vector_irq,
156 &tqp_vectors->affinity_notify);
157 irq_set_affinity_hint(tqp_vectors->vector_irq,
158 &tqp_vectors->affinity_mask);
159
76ad4f0e
S		 160 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
161 }
162
163 return 0;
164}
165
166static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
167 u32 mask_en)
168{
169 writel(mask_en, tqp_vector->mask_addr);
170}
171
172static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
173{
174 napi_enable(&tqp_vector->napi);
175
176 /* enable vector */
177 hns3_mask_vector_irq(tqp_vector, 1);
178}
179
180static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
181{
182 /* disable vector */
183 hns3_mask_vector_irq(tqp_vector, 0);
184
185 disable_irq(tqp_vector->vector_irq);
186 napi_disable(&tqp_vector->napi);
187}
188
5acd0356
FL		 189void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
190 u32 rl_value)
76ad4f0e 191{
5acd0356
FL		 192 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
193
76ad4f0e
S		 194 /* this defines the configuration for RL (Interrupt Rate Limiter).
195 * Rl defines rate of interrupts i.e. number of interrupts-per-second
196 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
197 */
5acd0356 198
d420d2de
YL		 199 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
200 !tqp_vector->rx_group.coal.gl_adapt_enable)
5acd0356
FL		 201 /* According to the hardware, the range of rl_reg is
202 * 0-59 and the unit is 4.
203 */
204 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
205
206 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
207}
208
209void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
210 u32 gl_value)
211{
212 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
213
214 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
215}
216
217void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
218 u32 gl_value)
219{
220 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
221
222 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 223}
224
2b27decc
FL		 225static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
226 struct hns3_nic_priv *priv)
76ad4f0e 227{
2b27decc
FL		 228 struct hnae3_handle *h = priv->ae_handle;
229
76ad4f0e
S		 230 /* initialize the configuration for interrupt coalescing.
231 * 1. GL (Interrupt Gap Limiter)
232 * 2. RL (Interrupt Rate Limiter)
233 */
234
2b27decc 235 /* Default: enable interrupt coalescing self-adaptive and GL */
d420d2de
YL		 236 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
237 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
2b27decc 238
d420d2de
YL		 239 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
240 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
2b27decc 241
2b27decc
FL		 242 /* Default: disable RL */
243 h->kinfo.int_rl_setting = 0;
2b27decc 244
3f97bd23 245 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
d420d2de
YL		 246 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
247 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 248}
249
6cbd6d33
YL		 250static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
251 struct hns3_nic_priv *priv)
252{
253 struct hnae3_handle *h = priv->ae_handle;
254
255 hns3_set_vector_coalesce_tx_gl(tqp_vector,
d420d2de 256 tqp_vector->tx_group.coal.int_gl);
6cbd6d33 257 hns3_set_vector_coalesce_rx_gl(tqp_vector,
d420d2de 258 tqp_vector->rx_group.coal.int_gl);
6cbd6d33
YL		 259 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
260}
261
9df8f79a
YL		 262static int hns3_nic_set_real_num_queue(struct net_device *netdev)
263{
9780cb97 264 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 265 struct hnae3_knic_private_info *kinfo = &h->kinfo;
266 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
7e114e7d
YL		 267 int i, ret;
268
269 if (kinfo->num_tc <= 1) {
270 netdev_reset_tc(netdev);
271 } else {
272 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
273 if (ret) {
274 netdev_err(netdev,
275 "netdev_set_num_tc fail, ret=%d!\n", ret);
276 return ret;
277 }
278
279 for (i = 0; i < HNAE3_MAX_TC; i++) {
280 if (!kinfo->tc_info[i].enable)
281 continue;
282
283 netdev_set_tc_queue(netdev,
284 kinfo->tc_info[i].tc,
285 kinfo->tc_info[i].tqp_count,
286 kinfo->tc_info[i].tqp_offset);
287 }
288 }
9df8f79a
YL		 289
290 ret = netif_set_real_num_tx_queues(netdev, queue_size);
291 if (ret) {
292 netdev_err(netdev,
293 "netif_set_real_num_tx_queues fail, ret=%d!\n",
294 ret);
295 return ret;
296 }
297
298 ret = netif_set_real_num_rx_queues(netdev, queue_size);
299 if (ret) {
300 netdev_err(netdev,
301 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
302 return ret;
303 }
304
305 return 0;
306}
307
2d7187ce
PL		 308static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
309{
310 u16 free_tqps, max_rss_size, max_tqps;
311
312 h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size);
313 max_tqps = h->kinfo.num_tc * max_rss_size;
314
315 return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps));
316}
317
76ad4f0e
S		 318static int hns3_nic_net_up(struct net_device *netdev)
319{
320 struct hns3_nic_priv *priv = netdev_priv(netdev);
321 struct hnae3_handle *h = priv->ae_handle;
322 int i, j;
323 int ret;
324
e32a805a
FL		 325 ret = hns3_nic_reset_all_ring(h);
326 if (ret)
327 return ret;
328
76ad4f0e
S		 329 /* get irq resource for all vectors */
330 ret = hns3_nic_init_irq(priv);
331 if (ret) {
332 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
333 return ret;
334 }
335
336 /* enable the vectors */
337 for (i = 0; i < priv->vector_num; i++)
338 hns3_vector_enable(&priv->tqp_vector[i]);
339
340 /* start the ae_dev */
341 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
342 if (ret)
343 goto out_start_err;
344
a3083abb
JS		 345 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
346
76ad4f0e
S		 347 return 0;
348
349out_start_err:
350 for (j = i - 1; j >= 0; j--)
351 hns3_vector_disable(&priv->tqp_vector[j]);
352
353 hns3_nic_uninit_irq(priv);
354
355 return ret;
356}
357
358static int hns3_nic_net_open(struct net_device *netdev)
359{
f8fa222c 360 struct hns3_nic_priv *priv = netdev_priv(netdev);
7e114e7d
YL		 361 struct hnae3_handle *h = hns3_get_handle(netdev);
362 struct hnae3_knic_private_info *kinfo;
363 int i, ret;
76ad4f0e
S		 364
365 netif_carrier_off(netdev);
366
9df8f79a
YL		 367 ret = hns3_nic_set_real_num_queue(netdev);
368 if (ret)
76ad4f0e 369 return ret;
76ad4f0e
S		 370
371 ret = hns3_nic_net_up(netdev);
372 if (ret) {
373 netdev_err(netdev,
374 "hns net up fail, ret=%d!\n", ret);
375 return ret;
376 }
377
7e114e7d
YL		 378 kinfo = &h->kinfo;
379 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
380 netdev_set_prio_tc_map(netdev, i,
381 kinfo->prio_tc[i]);
382 }
383
4aef908d 384 priv->ae_handle->last_reset_time = jiffies;
76ad4f0e
S		 385 return 0;
386}
387
388static void hns3_nic_net_down(struct net_device *netdev)
389{
390 struct hns3_nic_priv *priv = netdev_priv(netdev);
391 const struct hnae3_ae_ops *ops;
392 int i;
393
a3083abb
JS		 394 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
395 return;
396
e32a805a
FL		 397 /* disable vectors */
398 for (i = 0; i < priv->vector_num; i++)
399 hns3_vector_disable(&priv->tqp_vector[i]);
400
76ad4f0e
S		 401 /* stop ae_dev */
402 ops = priv->ae_handle->ae_algo->ops;
403 if (ops->stop)
404 ops->stop(priv->ae_handle);
405
76ad4f0e
S		 406 /* free irq resources */
407 hns3_nic_uninit_irq(priv);
e32a805a
FL		 408
409 hns3_clear_all_ring(priv->ae_handle);
76ad4f0e
S		 410}
411
412static int hns3_nic_net_stop(struct net_device *netdev)
413{
414 netif_tx_stop_all_queues(netdev);
415 netif_carrier_off(netdev);
416
417 hns3_nic_net_down(netdev);
418
419 return 0;
420}
421
76ad4f0e
S		 422static int hns3_nic_uc_sync(struct net_device *netdev,
423 const unsigned char *addr)
424{
9780cb97 425 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 426
427 if (h->ae_algo->ops->add_uc_addr)
428 return h->ae_algo->ops->add_uc_addr(h, addr);
429
430 return 0;
431}
432
433static int hns3_nic_uc_unsync(struct net_device *netdev,
434 const unsigned char *addr)
435{
9780cb97 436 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 437
438 if (h->ae_algo->ops->rm_uc_addr)
439 return h->ae_algo->ops->rm_uc_addr(h, addr);
440
441 return 0;
442}
443
444static int hns3_nic_mc_sync(struct net_device *netdev,
445 const unsigned char *addr)
446{
9780cb97 447 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 448
720a8478 449 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 450 return h->ae_algo->ops->add_mc_addr(h, addr);
451
452 return 0;
453}
454
455static int hns3_nic_mc_unsync(struct net_device *netdev,
456 const unsigned char *addr)
457{
9780cb97 458 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 459
720a8478 460 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 461 return h->ae_algo->ops->rm_mc_addr(h, addr);
462
463 return 0;
464}
465
1db9b1bf 466static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 467{
9780cb97 468 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 469
470 if (h->ae_algo->ops->set_promisc_mode) {
471 if (netdev->flags & IFF_PROMISC)
e8600a3d
PL		 472 h->ae_algo->ops->set_promisc_mode(h, true, true);
473 else if (netdev->flags & IFF_ALLMULTI)
474 h->ae_algo->ops->set_promisc_mode(h, false, true);
76ad4f0e 475 else
e8600a3d 476 h->ae_algo->ops->set_promisc_mode(h, false, false);
76ad4f0e
S		 477 }
478 if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync))
479 netdev_err(netdev, "sync uc address fail\n");
a832d8b5 480 if (netdev->flags & IFF_MULTICAST) {
76ad4f0e
S		 481 if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync))
482 netdev_err(netdev, "sync mc address fail\n");
a832d8b5
XW		 483
484 if (h->ae_algo->ops->update_mta_status)
485 h->ae_algo->ops->update_mta_status(h);
486 }
76ad4f0e
S		 487}
488
489static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
490 u16 *mss, u32 *type_cs_vlan_tso)
491{
492 u32 l4_offset, hdr_len;
493 union l3_hdr_info l3;
494 union l4_hdr_info l4;
495 u32 l4_paylen;
496 int ret;
497
498 if (!skb_is_gso(skb))
499 return 0;
500
501 ret = skb_cow_head(skb, 0);
502 if (ret)
503 return ret;
504
505 l3.hdr = skb_network_header(skb);
506 l4.hdr = skb_transport_header(skb);
507
508 /* Software should clear the IPv4's checksum field when tso is
509 * needed.
510 */
511 if (l3.v4->version == 4)
512 l3.v4->check = 0;
513
514 /* tunnel packet.*/
515 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
516 SKB_GSO_GRE_CSUM |
517 SKB_GSO_UDP_TUNNEL |
518 SKB_GSO_UDP_TUNNEL_CSUM)) {
519 if ((!(skb_shinfo(skb)->gso_type &
520 SKB_GSO_PARTIAL)) &&
521 (skb_shinfo(skb)->gso_type &
522 SKB_GSO_UDP_TUNNEL_CSUM)) {
523 /* Software should clear the udp's checksum
524 * field when tso is needed.
525 */
526 l4.udp->check = 0;
527 }
528 /* reset l3&l4 pointers from outer to inner headers */
529 l3.hdr = skb_inner_network_header(skb);
530 l4.hdr = skb_inner_transport_header(skb);
531
532 /* Software should clear the IPv4's checksum field when
533 * tso is needed.
534 */
535 if (l3.v4->version == 4)
536 l3.v4->check = 0;
537 }
538
539 /* normal or tunnel packet*/
540 l4_offset = l4.hdr - skb->data;
541 hdr_len = (l4.tcp->doff * 4) + l4_offset;
542
543 /* remove payload length from inner pseudo checksum when tso*/
544 l4_paylen = skb->len - l4_offset;
545 csum_replace_by_diff(&l4.tcp->check,
546 (__force __wsum)htonl(l4_paylen));
547
548 /* find the txbd field values */
549 *paylen = skb->len - hdr_len;
ccc23ef3
PL		 550 hnae3_set_bit(*type_cs_vlan_tso,
551 HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 552
553 /* get MSS for TSO */
554 *mss = skb_shinfo(skb)->gso_size;
555
556 return 0;
557}
558
1898d4e4
S		 559static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
560 u8 *il4_proto)
76ad4f0e
S		 561{
562 union {
563 struct iphdr *v4;
564 struct ipv6hdr *v6;
565 unsigned char *hdr;
566 } l3;
567 unsigned char *l4_hdr;
568 unsigned char *exthdr;
569 u8 l4_proto_tmp;
570 __be16 frag_off;
571
572 /* find outer header point */
573 l3.hdr = skb_network_header(skb);
c82a5497 574 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 575
576 if (skb->protocol == htons(ETH_P_IPV6)) {
577 exthdr = l3.hdr + sizeof(*l3.v6);
578 l4_proto_tmp = l3.v6->nexthdr;
579 if (l4_hdr != exthdr)
580 ipv6_skip_exthdr(skb, exthdr - skb->data,
581 &l4_proto_tmp, &frag_off);
582 } else if (skb->protocol == htons(ETH_P_IP)) {
583 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 584 } else {
585 return -EINVAL;
76ad4f0e
S		 586 }
587
588 *ol4_proto = l4_proto_tmp;
589
590 /* tunnel packet */
591 if (!skb->encapsulation) {
592 *il4_proto = 0;
1898d4e4 593 return 0;
76ad4f0e
S		 594 }
595
596 /* find inner header point */
597 l3.hdr = skb_inner_network_header(skb);
598 l4_hdr = skb_inner_transport_header(skb);
599
600 if (l3.v6->version == 6) {
601 exthdr = l3.hdr + sizeof(*l3.v6);
602 l4_proto_tmp = l3.v6->nexthdr;
603 if (l4_hdr != exthdr)
604 ipv6_skip_exthdr(skb, exthdr - skb->data,
605 &l4_proto_tmp, &frag_off);
606 } else if (l3.v4->version == 4) {
607 l4_proto_tmp = l3.v4->protocol;
608 }
609
610 *il4_proto = l4_proto_tmp;
1898d4e4
S		 611
612 return 0;
76ad4f0e
S		 613}
614
615static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
616 u8 il4_proto, u32 *type_cs_vlan_tso,
617 u32 *ol_type_vlan_len_msec)
618{
619 union {
620 struct iphdr *v4;
621 struct ipv6hdr *v6;
622 unsigned char *hdr;
623 } l3;
624 union {
625 struct tcphdr *tcp;
626 struct udphdr *udp;
627 struct gre_base_hdr *gre;
628 unsigned char *hdr;
629 } l4;
630 unsigned char *l2_hdr;
631 u8 l4_proto = ol4_proto;
632 u32 ol2_len;
633 u32 ol3_len;
634 u32 ol4_len;
635 u32 l2_len;
636 u32 l3_len;
637
638 l3.hdr = skb_network_header(skb);
639 l4.hdr = skb_transport_header(skb);
640
641 /* compute L2 header size for normal packet, defined in 2 Bytes */
642 l2_len = l3.hdr - skb->data;
ccc23ef3
PL		 643 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
644 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 645
646 /* tunnel packet*/
647 if (skb->encapsulation) {
648 /* compute OL2 header size, defined in 2 Bytes */
649 ol2_len = l2_len;
ccc23ef3
PL		 650 hnae3_set_field(*ol_type_vlan_len_msec,
651 HNS3_TXD_L2LEN_M,
652 HNS3_TXD_L2LEN_S, ol2_len >> 1);
76ad4f0e
S		 653
654 /* compute OL3 header size, defined in 4 Bytes */
655 ol3_len = l4.hdr - l3.hdr;
ccc23ef3
PL		 656 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
657 HNS3_TXD_L3LEN_S, ol3_len >> 2);
76ad4f0e
S		 658
659 /* MAC in UDP, MAC in GRE (0x6558)*/
660 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
661 /* switch MAC header ptr from outer to inner header.*/
662 l2_hdr = skb_inner_mac_header(skb);
663
664 /* compute OL4 header size, defined in 4 Bytes. */
665 ol4_len = l2_hdr - l4.hdr;
ccc23ef3
PL		 666 hnae3_set_field(*ol_type_vlan_len_msec,
667 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
668 ol4_len >> 2);
76ad4f0e
S		 669
670 /* switch IP header ptr from outer to inner header */
671 l3.hdr = skb_inner_network_header(skb);
672
673 /* compute inner l2 header size, defined in 2 Bytes. */
674 l2_len = l3.hdr - l2_hdr;
ccc23ef3
PL		 675 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
676 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 677 } else {
678 /* skb packet types not supported by hardware,
679 * txbd len fild doesn't be filled.
680 */
681 return;
682 }
683
684 /* switch L4 header pointer from outer to inner */
685 l4.hdr = skb_inner_transport_header(skb);
686
687 l4_proto = il4_proto;
688 }
689
690 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
691 l3_len = l4.hdr - l3.hdr;
ccc23ef3
PL		 692 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
693 HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e
S		 694
695 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
696 switch (l4_proto) {
697 case IPPROTO_TCP:
ccc23ef3
PL		 698 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
699 HNS3_TXD_L4LEN_S, l4.tcp->doff);
76ad4f0e
S		 700 break;
701 case IPPROTO_SCTP:
ccc23ef3
PL		 702 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
703 HNS3_TXD_L4LEN_S,
704 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 705 break;
706 case IPPROTO_UDP:
ccc23ef3
PL		 707 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
708 HNS3_TXD_L4LEN_S,
709 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 710 break;
711 default:
712 /* skb packet types not supported by hardware,
713 * txbd len fild doesn't be filled.
714 */
715 return;
716 }
717}
718
cfdd6e86
YL		 719/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
720 * and it is udp packet, which has a dest port as the IANA assigned.
721 * the hardware is expected to do the checksum offload, but the
722 * hardware will not do the checksum offload when udp dest port is
723 * 4789.
724 */
725static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
726{
727#define IANA_VXLAN_PORT 4789
728 union {
729 struct tcphdr *tcp;
730 struct udphdr *udp;
731 struct gre_base_hdr *gre;
732 unsigned char *hdr;
733 } l4;
734
735 l4.hdr = skb_transport_header(skb);
736
737 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
738 return false;
739
740 skb_checksum_help(skb);
741
742 return true;
743}
744
76ad4f0e
S		 745static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
746 u8 il4_proto, u32 *type_cs_vlan_tso,
747 u32 *ol_type_vlan_len_msec)
748{
749 union {
750 struct iphdr *v4;
751 struct ipv6hdr *v6;
752 unsigned char *hdr;
753 } l3;
754 u32 l4_proto = ol4_proto;
755
756 l3.hdr = skb_network_header(skb);
757
758 /* define OL3 type and tunnel type(OL4).*/
759 if (skb->encapsulation) {
760 /* define outer network header type.*/
761 if (skb->protocol == htons(ETH_P_IP)) {
762 if (skb_is_gso(skb))
ccc23ef3
PL		 763 hnae3_set_field(*ol_type_vlan_len_msec,
764 HNS3_TXD_OL3T_M,
765 HNS3_TXD_OL3T_S,
766 HNS3_OL3T_IPV4_CSUM);
76ad4f0e 767 else
ccc23ef3
PL		 768 hnae3_set_field(*ol_type_vlan_len_msec,
769 HNS3_TXD_OL3T_M,
770 HNS3_TXD_OL3T_S,
771 HNS3_OL3T_IPV4_NO_CSUM);
76ad4f0e
S		 772
773 } else if (skb->protocol == htons(ETH_P_IPV6)) {
ccc23ef3
PL		 774 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
775 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
76ad4f0e
S		 776 }
777
778 /* define tunnel type(OL4).*/
779 switch (l4_proto) {
780 case IPPROTO_UDP:
ccc23ef3
PL		 781 hnae3_set_field(*ol_type_vlan_len_msec,
782 HNS3_TXD_TUNTYPE_M,
783 HNS3_TXD_TUNTYPE_S,
784 HNS3_TUN_MAC_IN_UDP);
76ad4f0e
S		 785 break;
786 case IPPROTO_GRE:
ccc23ef3
PL		 787 hnae3_set_field(*ol_type_vlan_len_msec,
788 HNS3_TXD_TUNTYPE_M,
789 HNS3_TXD_TUNTYPE_S,
790 HNS3_TUN_NVGRE);
76ad4f0e
S		 791 break;
792 default:
793 /* drop the skb tunnel packet if hardware don't support,
794 * because hardware can't calculate csum when TSO.
795 */
796 if (skb_is_gso(skb))
797 return -EDOM;
798
799 /* the stack computes the IP header already,
800 * driver calculate l4 checksum when not TSO.
801 */
802 skb_checksum_help(skb);
803 return 0;
804 }
805
806 l3.hdr = skb_inner_network_header(skb);
807 l4_proto = il4_proto;
808 }
809
810 if (l3.v4->version == 4) {
ccc23ef3
PL		 811 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
812 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
76ad4f0e
S		 813
814 /* the stack computes the IP header already, the only time we
815 * need the hardware to recompute it is in the case of TSO.
816 */
817 if (skb_is_gso(skb))
ccc23ef3 818 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 819 } else if (l3.v6->version == 6) {
ccc23ef3
PL		 820 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
821 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
76ad4f0e
S		 822 }
823
824 switch (l4_proto) {
825 case IPPROTO_TCP:
79fa1b6a 826 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 827 hnae3_set_field(*type_cs_vlan_tso,
828 HNS3_TXD_L4T_M,
829 HNS3_TXD_L4T_S,
830 HNS3_L4T_TCP);
76ad4f0e
S		 831 break;
832 case IPPROTO_UDP:
cfdd6e86
YL		 833 if (hns3_tunnel_csum_bug(skb))
834 break;
835
79fa1b6a 836 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 837 hnae3_set_field(*type_cs_vlan_tso,
838 HNS3_TXD_L4T_M,
839 HNS3_TXD_L4T_S,
840 HNS3_L4T_UDP);
76ad4f0e
S		 841 break;
842 case IPPROTO_SCTP:
79fa1b6a 843 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 844 hnae3_set_field(*type_cs_vlan_tso,
845 HNS3_TXD_L4T_M,
846 HNS3_TXD_L4T_S,
847 HNS3_L4T_SCTP);
76ad4f0e
S		 848 break;
849 default:
850 /* drop the skb tunnel packet if hardware don't support,
851 * because hardware can't calculate csum when TSO.
852 */
853 if (skb_is_gso(skb))
854 return -EDOM;
855
856 /* the stack computes the IP header already,
857 * driver calculate l4 checksum when not TSO.
858 */
859 skb_checksum_help(skb);
860 return 0;
861 }
862
863 return 0;
864}
865
866static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
867{
868 /* Config bd buffer end */
ccc23ef3
PL		 869 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
870 HNS3_TXD_BDTYPE_S, 0);
871 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
872 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
873 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
76ad4f0e
S		 874}
875
1fdd8dc5
PL		 876static int hns3_fill_desc_vtags(struct sk_buff *skb,
877 struct hns3_enet_ring *tx_ring,
878 u32 *inner_vlan_flag,
879 u32 *out_vlan_flag,
880 u16 *inner_vtag,
881 u16 *out_vtag)
882{
883#define HNS3_TX_VLAN_PRIO_SHIFT 13
884
885 if (skb->protocol == htons(ETH_P_8021Q) &&
886 !(tx_ring->tqp->handle->kinfo.netdev->features &
887 NETIF_F_HW_VLAN_CTAG_TX)) {
888 /* When HW VLAN acceleration is turned off, and the stack
889 * sets the protocol to 802.1q, the driver just need to
890 * set the protocol to the encapsulated ethertype.
891 */
892 skb->protocol = vlan_get_protocol(skb);
893 return 0;
894 }
895
896 if (skb_vlan_tag_present(skb)) {
897 u16 vlan_tag;
898
899 vlan_tag = skb_vlan_tag_get(skb);
900 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
901
902 /* Based on hw strategy, use out_vtag in two layer tag case,
903 * and use inner_vtag in one tag case.
904 */
905 if (skb->protocol == htons(ETH_P_8021Q)) {
ccc23ef3 906 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
1fdd8dc5
PL		 907 *out_vtag = vlan_tag;
908 } else {
ccc23ef3 909 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
1fdd8dc5
PL		 910 *inner_vtag = vlan_tag;
911 }
912 } else if (skb->protocol == htons(ETH_P_8021Q)) {
913 struct vlan_ethhdr *vhdr;
914 int rc;
915
916 rc = skb_cow_head(skb, 0);
917 if (rc < 0)
918 return rc;
919 vhdr = (struct vlan_ethhdr *)skb->data;
920 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
921 << HNS3_TX_VLAN_PRIO_SHIFT);
922 }
923
924 skb->protocol = vlan_get_protocol(skb);
925 return 0;
926}
927
76ad4f0e
S		 928static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
929 int size, dma_addr_t dma, int frag_end,
930 enum hns_desc_type type)
931{
932 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
933 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
934 u32 ol_type_vlan_len_msec = 0;
935 u16 bdtp_fe_sc_vld_ra_ri = 0;
936 u32 type_cs_vlan_tso = 0;
937 struct sk_buff *skb;
1fdd8dc5
PL		 938 u16 inner_vtag = 0;
939 u16 out_vtag = 0;
76ad4f0e
S		 940 u32 paylen = 0;
941 u16 mss = 0;
76ad4f0e
S		 942 u8 ol4_proto;
943 u8 il4_proto;
944 int ret;
945
946 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
947 desc_cb->priv = priv;
948 desc_cb->length = size;
949 desc_cb->dma = dma;
950 desc_cb->type = type;
951
952 /* now, fill the descriptor */
953 desc->addr = cpu_to_le64(dma);
954 desc->tx.send_size = cpu_to_le16((u16)size);
955 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
956 desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
957
958 if (type == DESC_TYPE_SKB) {
959 skb = (struct sk_buff *)priv;
a90bb9a5 960 paylen = skb->len;
76ad4f0e 961
1fdd8dc5
PL		 962 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
963 &ol_type_vlan_len_msec,
964 &inner_vtag, &out_vtag);
965 if (unlikely(ret))
966 return ret;
967
76ad4f0e
S		 968 if (skb->ip_summed == CHECKSUM_PARTIAL) {
969 skb_reset_mac_len(skb);
76ad4f0e 970
1898d4e4
S		 971 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
972 if (ret)
973 return ret;
76ad4f0e
S		 974 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
975 &type_cs_vlan_tso,
976 &ol_type_vlan_len_msec);
977 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
978 &type_cs_vlan_tso,
979 &ol_type_vlan_len_msec);
980 if (ret)
981 return ret;
982
983 ret = hns3_set_tso(skb, &paylen, &mss,
984 &type_cs_vlan_tso);
985 if (ret)
986 return ret;
987 }
988
989 /* Set txbd */
990 desc->tx.ol_type_vlan_len_msec =
991 cpu_to_le32(ol_type_vlan_len_msec);
992 desc->tx.type_cs_vlan_tso_len =
993 cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 994 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 995 desc->tx.mss = cpu_to_le16(mss);
1fdd8dc5
PL		 996 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
997 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
76ad4f0e
S		 998 }
999
1000 /* move ring pointer to next.*/
1001 ring_ptr_move_fw(ring, next_to_use);
1002
1003 return 0;
1004}
1005
1006static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv,
1007 int size, dma_addr_t dma, int frag_end,
1008 enum hns_desc_type type)
1009{
1010 unsigned int frag_buf_num;
1011 unsigned int k;
1012 int sizeoflast;
1013 int ret;
1014
1015 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1016 sizeoflast = size % HNS3_MAX_BD_SIZE;
1017 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1018
1019 /* When the frag size is bigger than hardware, split this frag */
1020 for (k = 0; k < frag_buf_num; k++) {
1021 ret = hns3_fill_desc(ring, priv,
1022 (k == frag_buf_num - 1) ?
1023 sizeoflast : HNS3_MAX_BD_SIZE,
1024 dma + HNS3_MAX_BD_SIZE * k,
1025 frag_end && (k == frag_buf_num - 1) ? 1 : 0,
1026 (type == DESC_TYPE_SKB && !k) ?
1027 DESC_TYPE_SKB : DESC_TYPE_PAGE);
1028 if (ret)
1029 return ret;
1030 }
1031
1032 return 0;
1033}
1034
1035static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1036 struct hns3_enet_ring *ring)
1037{
1038 struct sk_buff *skb = *out_skb;
1039 struct skb_frag_struct *frag;
1040 int bdnum_for_frag;
1041 int frag_num;
1042 int buf_num;
1043 int size;
1044 int i;
1045
1046 size = skb_headlen(skb);
1047 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1048
1049 frag_num = skb_shinfo(skb)->nr_frags;
1050 for (i = 0; i < frag_num; i++) {
1051 frag = &skb_shinfo(skb)->frags[i];
1052 size = skb_frag_size(frag);
1053 bdnum_for_frag =
1054 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1055 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1056 return -ENOMEM;
1057
1058 buf_num += bdnum_for_frag;
1059 }
1060
1061 if (buf_num > ring_space(ring))
1062 return -EBUSY;
1063
1064 *bnum = buf_num;
1065 return 0;
1066}
1067
1068static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1069 struct hns3_enet_ring *ring)
1070{
1071 struct sk_buff *skb = *out_skb;
1072 int buf_num;
1073
1074 /* No. of segments (plus a header) */
1075 buf_num = skb_shinfo(skb)->nr_frags + 1;
1076
91a2f02f 1077 if (unlikely(ring_space(ring) < buf_num))
76ad4f0e
S		 1078 return -EBUSY;
1079
1080 *bnum = buf_num;
1081
1082 return 0;
1083}
1084
1085static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig)
1086{
1087 struct device *dev = ring_to_dev(ring);
1088 unsigned int i;
1089
1090 for (i = 0; i < ring->desc_num; i++) {
1091 /* check if this is where we started */
1092 if (ring->next_to_use == next_to_use_orig)
1093 break;
1094
1095 /* unmap the descriptor dma address */
1096 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1097 dma_unmap_single(dev,
1098 ring->desc_cb[ring->next_to_use].dma,
1099 ring->desc_cb[ring->next_to_use].length,
1100 DMA_TO_DEVICE);
1101 else
1102 dma_unmap_page(dev,
1103 ring->desc_cb[ring->next_to_use].dma,
1104 ring->desc_cb[ring->next_to_use].length,
1105 DMA_TO_DEVICE);
1106
1107 /* rollback one */
1108 ring_ptr_move_bw(ring, next_to_use);
1109 }
1110}
1111
d43e5aca 1112netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1113{
1114 struct hns3_nic_priv *priv = netdev_priv(netdev);
1115 struct hns3_nic_ring_data *ring_data =
1116 &tx_ring_data(priv, skb->queue_mapping);
1117 struct hns3_enet_ring *ring = ring_data->ring;
1118 struct device *dev = priv->dev;
1119 struct netdev_queue *dev_queue;
1120 struct skb_frag_struct *frag;
1121 int next_to_use_head;
1122 int next_to_use_frag;
1123 dma_addr_t dma;
1124 int buf_num;
1125 int seg_num;
1126 int size;
1127 int ret;
1128 int i;
1129
1130 /* Prefetch the data used later */
1131 prefetch(skb->data);
1132
1133 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1134 case -EBUSY:
1135 u64_stats_update_begin(&ring->syncp);
1136 ring->stats.tx_busy++;
1137 u64_stats_update_end(&ring->syncp);
1138
1139 goto out_net_tx_busy;
1140 case -ENOMEM:
1141 u64_stats_update_begin(&ring->syncp);
1142 ring->stats.sw_err_cnt++;
1143 u64_stats_update_end(&ring->syncp);
1144 netdev_err(netdev, "no memory to xmit!\n");
1145
1146 goto out_err_tx_ok;
1147 default:
1148 break;
1149 }
1150
1151 /* No. of segments (plus a header) */
1152 seg_num = skb_shinfo(skb)->nr_frags + 1;
1153 /* Fill the first part */
1154 size = skb_headlen(skb);
1155
1156 next_to_use_head = ring->next_to_use;
1157
1158 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1159 if (dma_mapping_error(dev, dma)) {
1160 netdev_err(netdev, "TX head DMA map failed\n");
1161 ring->stats.sw_err_cnt++;
1162 goto out_err_tx_ok;
1163 }
1164
1165 ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0,
1166 DESC_TYPE_SKB);
1167 if (ret)
1168 goto head_dma_map_err;
1169
1170 next_to_use_frag = ring->next_to_use;
1171 /* Fill the fragments */
1172 for (i = 1; i < seg_num; i++) {
1173 frag = &skb_shinfo(skb)->frags[i - 1];
1174 size = skb_frag_size(frag);
1175 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1176 if (dma_mapping_error(dev, dma)) {
1177 netdev_err(netdev, "TX frag(%d) DMA map failed\n", i);
1178 ring->stats.sw_err_cnt++;
1179 goto frag_dma_map_err;
1180 }
1181 ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma,
1182 seg_num - 1 == i ? 1 : 0,
1183 DESC_TYPE_PAGE);
1184
1185 if (ret)
1186 goto frag_dma_map_err;
1187 }
1188
1189 /* Complete translate all packets */
1190 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1191 netdev_tx_sent_queue(dev_queue, skb->len);
1192
1193 wmb(); /* Commit all data before submit */
1194
ccc23ef3 1195 hnae3_queue_xmit(ring->tqp, buf_num);
76ad4f0e
S		 1196
1197 return NETDEV_TX_OK;
1198
1199frag_dma_map_err:
1200 hns_nic_dma_unmap(ring, next_to_use_frag);
1201
1202head_dma_map_err:
1203 hns_nic_dma_unmap(ring, next_to_use_head);
1204
1205out_err_tx_ok:
1206 dev_kfree_skb_any(skb);
1207 return NETDEV_TX_OK;
1208
1209out_net_tx_busy:
1210 netif_stop_subqueue(netdev, ring_data->queue_index);
1211 smp_mb(); /* Commit all data before submit */
1212
1213 return NETDEV_TX_BUSY;
1214}
1215
1216static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1217{
9780cb97 1218 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1219 struct sockaddr *mac_addr = p;
1220 int ret;
1221
1222 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1223 return -EADDRNOTAVAIL;
1224
f37fc980
JS		 1225 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1226 netdev_info(netdev, "already using mac address %pM\n",
1227 mac_addr->sa_data);
1228 return 0;
1229 }
1230
3cbf5e2d 1231 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1232 if (ret) {
1233 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1234 return ret;
1235 }
1236
1237 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1238
1239 return 0;
1240}
1241
a185d723
XW		 1242static int hns3_nic_do_ioctl(struct net_device *netdev,
1243 struct ifreq *ifr, int cmd)
1244{
1245 struct hnae3_handle *h = hns3_get_handle(netdev);
1246
1247 if (!netif_running(netdev))
1248 return -EINVAL;
1249
1250 if (!h->ae_algo->ops->do_ioctl)
1251 return -EOPNOTSUPP;
1252
1253 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1254}
1255
76ad4f0e
S		 1256static int hns3_nic_set_features(struct net_device *netdev,
1257 netdev_features_t features)
1258{
21b6fd34 1259 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1260 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f9a7732 1261 struct hnae3_handle *h = priv->ae_handle;
5f9a7732 1262 int ret;
76ad4f0e 1263
21b6fd34
JS		 1264 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
1265 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) {
1266 priv->ops.fill_desc = hns3_fill_desc_tso;
1267 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
1268 } else {
1269 priv->ops.fill_desc = hns3_fill_desc;
1270 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
1271 }
76ad4f0e
S		 1272 }
1273
88576b4b
JS		 1274 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1275 h->ae_algo->ops->enable_vlan_filter) {
21b6fd34
JS		 1276 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1277 h->ae_algo->ops->enable_vlan_filter(h, true);
1278 else
1279 h->ae_algo->ops->enable_vlan_filter(h, false);
1280 }
d818396d 1281
88576b4b
JS		 1282 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1283 h->ae_algo->ops->enable_hw_strip_rxvtag) {
5f9a7732
PL		 1284 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1285 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1286 else
1287 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1288
1289 if (ret)
1290 return ret;
1291 }
1292
76ad4f0e
S		 1293 netdev->features = features;
1294 return 0;
1295}
1296
9596f6f0
PL		 1297static void hns3_nic_get_stats64(struct net_device *netdev,
1298 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1299{
1300 struct hns3_nic_priv *priv = netdev_priv(netdev);
1301 int queue_num = priv->ae_handle->kinfo.num_tqps;
7a5d2a39 1302 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e
S		 1303 struct hns3_enet_ring *ring;
1304 unsigned int start;
1305 unsigned int idx;
1306 u64 tx_bytes = 0;
1307 u64 rx_bytes = 0;
1308 u64 tx_pkts = 0;
1309 u64 rx_pkts = 0;
0a83231f
JS		 1310 u64 tx_drop = 0;
1311 u64 rx_drop = 0;
76ad4f0e 1312
a3083abb
JS		 1313 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1314 return;
1315
7a5d2a39
JS		 1316 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1317
76ad4f0e
S		 1318 for (idx = 0; idx < queue_num; idx++) {
1319 /* fetch the tx stats */
1320 ring = priv->ring_data[idx].ring;
1321 do {
d36d36ce 1322 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1323 tx_bytes += ring->stats.tx_bytes;
1324 tx_pkts += ring->stats.tx_pkts;
0a83231f
JS		 1325 tx_drop += ring->stats.tx_busy;
1326 tx_drop += ring->stats.sw_err_cnt;
76ad4f0e
S		 1327 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1328
1329 /* fetch the rx stats */
1330 ring = priv->ring_data[idx + queue_num].ring;
1331 do {
d36d36ce 1332 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1333 rx_bytes += ring->stats.rx_bytes;
1334 rx_pkts += ring->stats.rx_pkts;
0a83231f
JS		 1335 rx_drop += ring->stats.non_vld_descs;
1336 rx_drop += ring->stats.err_pkt_len;
1337 rx_drop += ring->stats.l2_err;
76ad4f0e
S		 1338 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1339 }
1340
1341 stats->tx_bytes = tx_bytes;
1342 stats->tx_packets = tx_pkts;
1343 stats->rx_bytes = rx_bytes;
1344 stats->rx_packets = rx_pkts;
1345
1346 stats->rx_errors = netdev->stats.rx_errors;
1347 stats->multicast = netdev->stats.multicast;
1348 stats->rx_length_errors = netdev->stats.rx_length_errors;
1349 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
1350 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1351
1352 stats->tx_errors = netdev->stats.tx_errors;
0a83231f
JS		 1353 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
1354 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
76ad4f0e
S		 1355 stats->collisions = netdev->stats.collisions;
1356 stats->rx_over_errors = netdev->stats.rx_over_errors;
1357 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1358 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1359 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1360 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1361 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1362 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1363 stats->tx_window_errors = netdev->stats.tx_window_errors;
1364 stats->rx_compressed = netdev->stats.rx_compressed;
1365 stats->tx_compressed = netdev->stats.tx_compressed;
1366}
1367
30d240df 1368static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1369{
30d240df 1370 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
9780cb97 1371 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 1372 struct hnae3_knic_private_info *kinfo = &h->kinfo;
30d240df
YL		 1373 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1374 u8 tc = mqprio_qopt->qopt.num_tc;
1375 u16 mode = mqprio_qopt->mode;
1376 u8 hw = mqprio_qopt->qopt.hw;
1377 bool if_running;
76ad4f0e
S		 1378 int ret;
1379
30d240df
YL		 1380 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1381 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1382 return -EOPNOTSUPP;
1383
76ad4f0e
S		 1384 if (tc > HNAE3_MAX_TC)
1385 return -EINVAL;
1386
76ad4f0e
S		 1387 if (!netdev)
1388 return -EINVAL;
1389
30d240df
YL		 1390 if_running = netif_running(netdev);
1391 if (if_running) {
1392 hns3_nic_net_stop(netdev);
1393 msleep(100);
76ad4f0e
S		 1394 }
1395
30d240df
YL		 1396 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1397 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e 1398 if (ret)
30d240df
YL		 1399 goto out;
1400
30d240df
YL		 1401 ret = hns3_nic_set_real_num_queue(netdev);
1402
1403out:
1404 if (if_running)
1405 hns3_nic_net_open(netdev);
1406
1407 return ret;
76ad4f0e
S		 1408}
1409
2572ac53 1410static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1411 void *type_data)
76ad4f0e 1412{
575ed7d3 1413 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1414 return -EOPNOTSUPP;
76ad4f0e 1415
30d240df 1416 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1417}
1418
1419static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1420 __be16 proto, u16 vid)
1421{
9780cb97 1422 struct hnae3_handle *h = hns3_get_handle(netdev);
103ce052 1423 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1424 int ret = -EIO;
1425
1426 if (h->ae_algo->ops->set_vlan_filter)
1427 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1428
103ce052
YL		 1429 if (!ret)
1430 set_bit(vid, priv->active_vlans);
1431
76ad4f0e
S		 1432 return ret;
1433}
1434
1435static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1436 __be16 proto, u16 vid)
1437{
9780cb97 1438 struct hnae3_handle *h = hns3_get_handle(netdev);
103ce052 1439 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1440 int ret = -EIO;
1441
1442 if (h->ae_algo->ops->set_vlan_filter)
1443 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1444
103ce052
YL		 1445 if (!ret)
1446 clear_bit(vid, priv->active_vlans);
1447
76ad4f0e
S		 1448 return ret;
1449}
1450
103ce052
YL		 1451static void hns3_restore_vlan(struct net_device *netdev)
1452{
1453 struct hns3_nic_priv *priv = netdev_priv(netdev);
1454 u16 vid;
1455 int ret;
1456
1457 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1458 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
1459 if (ret)
1460 netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n",
1461 vid, ret);
1462 }
1463}
1464
76ad4f0e
S		 1465static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1466 u8 qos, __be16 vlan_proto)
1467{
9780cb97 1468 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1469 int ret = -EIO;
1470
1471 if (h->ae_algo->ops->set_vf_vlan_filter)
1472 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1473 qos, vlan_proto);
1474
1475 return ret;
1476}
1477
a8e8b7ff
S		 1478static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1479{
9780cb97 1480 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1481 bool if_running = netif_running(netdev);
1482 int ret;
1483
1484 if (!h->ae_algo->ops->set_mtu)
1485 return -EOPNOTSUPP;
1486
1487 /* if this was called with netdev up then bring netdevice down */
1488 if (if_running) {
1489 (void)hns3_nic_net_stop(netdev);
1490 msleep(100);
1491 }
1492
1493 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1494 if (ret) {
1495 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1496 ret);
1497 return ret;
1498 }
1499
fe6362f9
FL		 1500 netdev->mtu = new_mtu;
1501
a8e8b7ff
S		 1502 /* if the netdev was running earlier, bring it up again */
1503 if (if_running && hns3_nic_net_open(netdev))
1504 ret = -EINVAL;
1505
1506 return ret;
1507}
1508
f8fa222c
L		 1509static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1510{
1511 struct hns3_nic_priv *priv = netdev_priv(ndev);
1512 struct hns3_enet_ring *tx_ring = NULL;
1513 int timeout_queue = 0;
1514 int hw_head, hw_tail;
1515 int i;
1516
1517 /* Find the stopped queue the same way the stack does */
1518 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1519 struct netdev_queue *q;
1520 unsigned long trans_start;
1521
1522 q = netdev_get_tx_queue(ndev, i);
1523 trans_start = q->trans_start;
1524 if (netif_xmit_stopped(q) &&
1525 time_after(jiffies,
1526 (trans_start + ndev->watchdog_timeo))) {
1527 timeout_queue = i;
1528 break;
1529 }
1530 }
1531
1532 if (i == ndev->num_tx_queues) {
1533 netdev_info(ndev,
1534 "no netdev TX timeout queue found, timeout count: %llu\n",
1535 priv->tx_timeout_count);
1536 return false;
1537 }
1538
1539 tx_ring = priv->ring_data[timeout_queue].ring;
1540
1541 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1542 HNS3_RING_TX_RING_HEAD_REG);
1543 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1544 HNS3_RING_TX_RING_TAIL_REG);
1545 netdev_info(ndev,
1546 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1547 priv->tx_timeout_count,
1548 timeout_queue,
1549 tx_ring->next_to_use,
1550 tx_ring->next_to_clean,
1551 hw_head,
1552 hw_tail,
1553 readl(tx_ring->tqp_vector->mask_addr));
1554
1555 return true;
1556}
1557
1558static void hns3_nic_net_timeout(struct net_device *ndev)
1559{
1560 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1561 struct hnae3_handle *h = priv->ae_handle;
1562
1563 if (!hns3_get_tx_timeo_queue_info(ndev))
1564 return;
1565
1566 priv->tx_timeout_count++;
1567
4aef908d 1568 if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo)))
f8fa222c
L		 1569 return;
1570
4aef908d 1571 /* request the reset */
f8fa222c 1572 if (h->ae_algo->ops->reset_event)
4aef908d 1573 h->ae_algo->ops->reset_event(h);
f8fa222c
L		 1574}
1575
76ad4f0e
S		 1576static const struct net_device_ops hns3_nic_netdev_ops = {
1577 .ndo_open = hns3_nic_net_open,
1578 .ndo_stop = hns3_nic_net_stop,
1579 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1580 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1581 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
a185d723 1582 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1583 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1584 .ndo_set_features = hns3_nic_set_features,
1585 .ndo_get_stats64 = hns3_nic_get_stats64,
1586 .ndo_setup_tc = hns3_nic_setup_tc,
1587 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1588 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1589 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1590 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1591};
1592
bc59f827
FL		 1593static bool hns3_is_phys_func(struct pci_dev *pdev)
1594{
1595 u32 dev_id = pdev->device;
1596
1597 switch (dev_id) {
1598 case HNAE3_DEV_ID_GE:
1599 case HNAE3_DEV_ID_25GE:
1600 case HNAE3_DEV_ID_25GE_RDMA:
1601 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1602 case HNAE3_DEV_ID_50GE_RDMA:
1603 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1604 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1605 return true;
1606 case HNAE3_DEV_ID_100G_VF:
1607 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1608 return false;
1609 default:
1610 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1611 dev_id);
1612 }
1613
1614 return false;
1615}
1616
bc59f827
FL		 1617static void hns3_disable_sriov(struct pci_dev *pdev)
1618{
1619 /* If our VFs are assigned we cannot shut down SR-IOV
1620 * without causing issues, so just leave the hardware
1621 * available but disabled
1622 */
1623 if (pci_vfs_assigned(pdev)) {
1624 dev_warn(&pdev->dev,
1625 "disabling driver while VFs are assigned\n");
1626 return;
1627 }
1628
1629 pci_disable_sriov(pdev);
1630}
1631
76ad4f0e
S		 1632/* hns3_probe - Device initialization routine
1633 * @pdev: PCI device information struct
1634 * @ent: entry in hns3_pci_tbl
1635 *
1636 * hns3_probe initializes a PF identified by a pci_dev structure.
1637 * The OS initialization, configuring of the PF private structure,
1638 * and a hardware reset occur.
1639 *
1640 * Returns 0 on success, negative on failure
1641 */
1642static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1643{
1644 struct hnae3_ae_dev *ae_dev;
1645 int ret;
1646
1647 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1648 GFP_KERNEL);
1649 if (!ae_dev) {
1650 ret = -ENOMEM;
1651 return ret;
1652 }
1653
1654 ae_dev->pdev = pdev;
e92a0843 1655 ae_dev->flag = ent->driver_data;
76ad4f0e
S		 1656 ae_dev->dev_type = HNAE3_DEV_KNIC;
1657 pci_set_drvdata(pdev, ae_dev);
1658
fb919349 1659 hnae3_register_ae_dev(ae_dev);
bc59f827 1660
bc59f827 1661 return 0;
76ad4f0e
S		 1662}
1663
1664/* hns3_remove - Device removal routine
1665 * @pdev: PCI device information struct
1666 */
1667static void hns3_remove(struct pci_dev *pdev)
1668{
1669 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1670
bc59f827
FL		 1671 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1672 hns3_disable_sriov(pdev);
1673
76ad4f0e 1674 hnae3_unregister_ae_dev(ae_dev);
76ad4f0e
S		 1675}
1676
cfeff578
PL		 1677/**
1678 * hns3_pci_sriov_configure
1679 * @pdev: pointer to a pci_dev structure
1680 * @num_vfs: number of VFs to allocate
1681 *
1682 * Enable or change the number of VFs. Called when the user updates the number
1683 * of VFs in sysfs.
1684 **/
baff3ed7 1685static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
cfeff578
PL		 1686{
1687 int ret;
1688
1689 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1690 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1691 return -EINVAL;
1692 }
1693
1694 if (num_vfs) {
1695 ret = pci_enable_sriov(pdev, num_vfs);
1696 if (ret)
1697 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
baff3ed7
SM		 1698 else
1699 return num_vfs;
cfeff578
PL		 1700 } else if (!pci_vfs_assigned(pdev)) {
1701 pci_disable_sriov(pdev);
1702 } else {
1703 dev_warn(&pdev->dev,
1704 "Unable to free VFs because some are assigned to VMs.\n");
1705 }
1706
1707 return 0;
1708}
1709
4f043c3e
YL		 1710static void hns3_shutdown(struct pci_dev *pdev)
1711{
1712 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1713
1714 hnae3_unregister_ae_dev(ae_dev);
1715 devm_kfree(&pdev->dev, ae_dev);
1716 pci_set_drvdata(pdev, NULL);
1717
1718 if (system_state == SYSTEM_POWER_OFF)
1719 pci_set_power_state(pdev, PCI_D3hot);
1720}
1721
76ad4f0e
S		 1722static struct pci_driver hns3_driver = {
1723 .name = hns3_driver_name,
1724 .id_table = hns3_pci_tbl,
1725 .probe = hns3_probe,
1726 .remove = hns3_remove,
4f043c3e 1727 .shutdown = hns3_shutdown,
cfeff578 1728 .sriov_configure = hns3_pci_sriov_configure,
76ad4f0e
S		 1729};
1730
1731/* set default feature to hns3 */
1732static void hns3_set_default_feature(struct net_device *netdev)
1733{
a4c378bb
PL		 1734 struct hnae3_handle *h = hns3_get_handle(netdev);
1735 struct pci_dev *pdev = h->pdev;
1736
76ad4f0e
S		 1737 netdev->priv_flags |= IFF_UNICAST_FLT;
1738
1739 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1740 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1741 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1742 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1743 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1744
1745 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1746
1747 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1748
1749 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1750 NETIF_F_HW_VLAN_CTAG_FILTER |
5f9a7732 1751 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1752 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1753 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1754 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1755 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1756
1757 netdev->vlan_features |=
1758 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1759 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1760 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1761 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1762 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1763
1764 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3849d494 1765 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1766 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1767 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1768 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1769 NETIF_F_GSO_UDP_TUNNEL_CSUM;
a4c378bb
PL		 1770
1771 if (pdev->revision != 0x20)
1772 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
76ad4f0e
S		 1773}
1774
1775static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1776 struct hns3_desc_cb *cb)
1777{
ccc23ef3 1778 unsigned int order = hnae3_page_order(ring);
76ad4f0e
S		 1779 struct page *p;
1780
1781 p = dev_alloc_pages(order);
1782 if (!p)
1783 return -ENOMEM;
1784
1785 cb->priv = p;
1786 cb->page_offset = 0;
1787 cb->reuse_flag = 0;
1788 cb->buf = page_address(p);
ccc23ef3 1789 cb->length = hnae3_page_size(ring);
76ad4f0e
S		 1790 cb->type = DESC_TYPE_PAGE;
1791
76ad4f0e
S		 1792 return 0;
1793}
1794
1795static void hns3_free_buffer(struct hns3_enet_ring *ring,
1796 struct hns3_desc_cb *cb)
1797{
1798 if (cb->type == DESC_TYPE_SKB)
1799 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1800 else if (!HNAE3_IS_TX_RING(ring))
1801 put_page((struct page *)cb->priv);
1802 memset(cb, 0, sizeof(*cb));
1803}
1804
1805static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1806{
1807 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1808 cb->length, ring_to_dma_dir(ring));
1809
39bbc873 1810 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 1811 return -EIO;
1812
1813 return 0;
1814}
1815
1816static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
1817 struct hns3_desc_cb *cb)
1818{
1819 if (cb->type == DESC_TYPE_SKB)
1820 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
1821 ring_to_dma_dir(ring));
1822 else
1823 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
1824 ring_to_dma_dir(ring));
1825}
1826
1827static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
1828{
1829 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
1830 ring->desc[i].addr = 0;
1831}
1832
1833static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
1834{
1835 struct hns3_desc_cb *cb = &ring->desc_cb[i];
1836
1837 if (!ring->desc_cb[i].dma)
1838 return;
1839
1840 hns3_buffer_detach(ring, i);
1841 hns3_free_buffer(ring, cb);
1842}
1843
1844static void hns3_free_buffers(struct hns3_enet_ring *ring)
1845{
1846 int i;
1847
1848 for (i = 0; i < ring->desc_num; i++)
1849 hns3_free_buffer_detach(ring, i);
1850}
1851
1852/* free desc along with its attached buffer */
1853static void hns3_free_desc(struct hns3_enet_ring *ring)
1854{
d61c1a80
HT		 1855 int size = ring->desc_num * sizeof(ring->desc[0]);
1856
76ad4f0e
S		 1857 hns3_free_buffers(ring);
1858
d61c1a80
HT		 1859 if (ring->desc) {
1860 dma_free_coherent(ring_to_dev(ring), size,
1861 ring->desc, ring->desc_dma_addr);
1862 ring->desc = NULL;
1863 }
76ad4f0e
S		 1864}
1865
1866static int hns3_alloc_desc(struct hns3_enet_ring *ring)
1867{
1868 int size = ring->desc_num * sizeof(ring->desc[0]);
1869
d61c1a80
HT		 1870 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size,
1871 &ring->desc_dma_addr,
1872 GFP_KERNEL);
76ad4f0e
S		 1873 if (!ring->desc)
1874 return -ENOMEM;
1875
76ad4f0e
S		 1876 return 0;
1877}
1878
1879static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
1880 struct hns3_desc_cb *cb)
1881{
1882 int ret;
1883
1884 ret = hns3_alloc_buffer(ring, cb);
1885 if (ret)
1886 goto out;
1887
1888 ret = hns3_map_buffer(ring, cb);
1889 if (ret)
1890 goto out_with_buf;
1891
1892 return 0;
1893
1894out_with_buf:
564883bb 1895 hns3_free_buffer(ring, cb);
76ad4f0e
S		 1896out:
1897 return ret;
1898}
1899
1900static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
1901{
1902 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
1903
1904 if (ret)
1905 return ret;
1906
1907 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
1908
1909 return 0;
1910}
1911
1912/* Allocate memory for raw pkg, and map with dma */
1913static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
1914{
1915 int i, j, ret;
1916
1917 for (i = 0; i < ring->desc_num; i++) {
1918 ret = hns3_alloc_buffer_attach(ring, i);
1919 if (ret)
1920 goto out_buffer_fail;
1921 }
1922
1923 return 0;
1924
1925out_buffer_fail:
1926 for (j = i - 1; j >= 0; j--)
1927 hns3_free_buffer_detach(ring, j);
1928 return ret;
1929}
1930
1931/* detach a in-used buffer and replace with a reserved one */
1932static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
1933 struct hns3_desc_cb *res_cb)
1934{
b9077428 1935 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 1936 ring->desc_cb[i] = *res_cb;
1937 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
4169a686 1938 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 1939}
1940
1941static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
1942{
1943 ring->desc_cb[i].reuse_flag = 0;
1944 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
1945 + ring->desc_cb[i].page_offset);
4169a686 1946 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 1947}
1948
1949static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
1950 int *pkts)
1951{
1952 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
1953
1954 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
1955 (*bytes) += desc_cb->length;
ccc23ef3 1956 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
76ad4f0e
S		 1957 hns3_free_buffer_detach(ring, ring->next_to_clean);
1958
1959 ring_ptr_move_fw(ring, next_to_clean);
1960}
1961
1962static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
1963{
1964 int u = ring->next_to_use;
1965 int c = ring->next_to_clean;
1966
1967 if (unlikely(h > ring->desc_num))
1968 return 0;
1969
1970 return u > c ? (h > c && h <= u) : (h > c || h <= u);
1971}
1972
6a38a95f 1973void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 1974{
1975 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
c3e4287e 1976 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1977 struct netdev_queue *dev_queue;
1978 int bytes, pkts;
1979 int head;
1980
1981 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
1982 rmb(); /* Make sure head is ready before touch any data */
1983
1984 if (is_ring_empty(ring) || head == ring->next_to_clean)
6a38a95f 1985 return; /* no data to poll */
76ad4f0e 1986
2ea8667b 1987 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S		 1988 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
1989 ring->next_to_use, ring->next_to_clean);
1990
1991 u64_stats_update_begin(&ring->syncp);
1992 ring->stats.io_err_cnt++;
1993 u64_stats_update_end(&ring->syncp);
6a38a95f 1994 return;
76ad4f0e
S		 1995 }
1996
1997 bytes = 0;
1998 pkts = 0;
6a38a95f 1999 while (head != ring->next_to_clean) {
76ad4f0e
S		 2000 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
2001 /* Issue prefetch for next Tx descriptor */
2002 prefetch(&ring->desc_cb[ring->next_to_clean]);
76ad4f0e
S		 2003 }
2004
2005 ring->tqp_vector->tx_group.total_bytes += bytes;
2006 ring->tqp_vector->tx_group.total_packets += pkts;
2007
2008 u64_stats_update_begin(&ring->syncp);
2009 ring->stats.tx_bytes += bytes;
2010 ring->stats.tx_pkts += pkts;
2011 u64_stats_update_end(&ring->syncp);
2012
2013 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2014 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2015
2016 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2017 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2018 /* Make sure that anybody stopping the queue after this
2019 * sees the new next_to_clean.
2020 */
2021 smp_mb();
c3e4287e
JS		 2022 if (netif_tx_queue_stopped(dev_queue) &&
2023 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2024 netif_tx_wake_queue(dev_queue);
2025 ring->stats.restart_queue++;
2026 }
2027 }
76ad4f0e
S		 2028}
2029
2030static int hns3_desc_unused(struct hns3_enet_ring *ring)
2031{
2032 int ntc = ring->next_to_clean;
2033 int ntu = ring->next_to_use;
2034
2035 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2036}
2037
2038static void
2039hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2040{
2041 struct hns3_desc_cb *desc_cb;
2042 struct hns3_desc_cb res_cbs;
2043 int i, ret;
2044
2045 for (i = 0; i < cleand_count; i++) {
2046 desc_cb = &ring->desc_cb[ring->next_to_use];
2047 if (desc_cb->reuse_flag) {
2048 u64_stats_update_begin(&ring->syncp);
2049 ring->stats.reuse_pg_cnt++;
2050 u64_stats_update_end(&ring->syncp);
2051
2052 hns3_reuse_buffer(ring, ring->next_to_use);
2053 } else {
2054 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2055 if (ret) {
2056 u64_stats_update_begin(&ring->syncp);
2057 ring->stats.sw_err_cnt++;
2058 u64_stats_update_end(&ring->syncp);
2059
2060 netdev_err(ring->tqp->handle->kinfo.netdev,
2061 "hnae reserve buffer map failed.\n");
2062 break;
2063 }
2064 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2065 }
2066
2067 ring_ptr_move_fw(ring, next_to_use);
2068 }
2069
2070 wmb(); /* Make all data has been write before submit */
2071 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2072}
2073
76ad4f0e
S		 2074static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2075 struct hns3_enet_ring *ring, int pull_len,
2076 struct hns3_desc_cb *desc_cb)
2077{
2078 struct hns3_desc *desc;
e56a15b7
HT		 2079 u32 truesize;
2080 int size;
76ad4f0e
S		 2081 int last_offset;
2082 bool twobufs;
2083
2084 twobufs = ((PAGE_SIZE < 8192) &&
ccc23ef3 2085 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
76ad4f0e
S		 2086
2087 desc = &ring->desc[ring->next_to_clean];
2088 size = le16_to_cpu(desc->rx.size);
2089
ccc23ef3 2090 truesize = hnae3_buf_size(ring);
885a882a
PL		 2091
2092 if (!twobufs)
ccc23ef3 2093 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
76ad4f0e
S		 2094
2095 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
885a882a 2096 size - pull_len, truesize);
76ad4f0e
S		 2097
2098 /* Avoid re-using remote pages,flag default unreuse */
2099 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2100 return;
2101
2102 if (twobufs) {
2103 /* If we are only owner of page we can reuse it */
2104 if (likely(page_count(desc_cb->priv) == 1)) {
2105 /* Flip page offset to other buffer */
2106 desc_cb->page_offset ^= truesize;
2107
2108 desc_cb->reuse_flag = 1;
2109 /* bump ref count on page before it is given*/
2110 get_page(desc_cb->priv);
2111 }
2112 return;
2113 }
2114
2115 /* Move offset up to the next cache line */
2116 desc_cb->page_offset += truesize;
2117
2118 if (desc_cb->page_offset <= last_offset) {
2119 desc_cb->reuse_flag = 1;
2120 /* Bump ref count on page before it is given*/
2121 get_page(desc_cb->priv);
2122 }
2123}
2124
2125static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2126 struct hns3_desc *desc)
2127{
2128 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2129 int l3_type, l4_type;
2130 u32 bd_base_info;
2131 int ol4_type;
2132 u32 l234info;
2133
2134 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2135 l234info = le32_to_cpu(desc->rx.l234_info);
2136
2137 skb->ip_summed = CHECKSUM_NONE;
2138
2139 skb_checksum_none_assert(skb);
2140
2141 if (!(netdev->features & NETIF_F_RXCSUM))
2142 return;
2143
2144 /* check if hardware has done checksum */
ccc23ef3 2145 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
76ad4f0e
S		 2146 return;
2147
ccc23ef3
PL		 2148 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2149 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2150 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2151 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
76ad4f0e
S		 2152 u64_stats_update_begin(&ring->syncp);
2153 ring->stats.l3l4_csum_err++;
2154 u64_stats_update_end(&ring->syncp);
2155
2156 return;
2157 }
2158
ccc23ef3
PL		 2159 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2160 HNS3_RXD_L3ID_S);
2161 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2162 HNS3_RXD_L4ID_S);
76ad4f0e 2163
ccc23ef3
PL		 2164 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2165 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2166 switch (ol4_type) {
2167 case HNS3_OL4_TYPE_MAC_IN_UDP:
2168 case HNS3_OL4_TYPE_NVGRE:
2169 skb->csum_level = 1;
64061deb 2170 /* fall through */
76ad4f0e
S		 2171 case HNS3_OL4_TYPE_NO_TUN:
2172 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
ffa051fa
PL		 2173 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2174 l3_type == HNS3_L3_TYPE_IPV6) &&
2175 (l4_type == HNS3_L4_TYPE_UDP ||
2176 l4_type == HNS3_L4_TYPE_TCP ||
2177 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2178 skb->ip_summed = CHECKSUM_UNNECESSARY;
2179 break;
085920ba
JS		 2180 default:
2181 break;
76ad4f0e
S		 2182 }
2183}
2184
d43e5aca
YL		 2185static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2186{
2187 napi_gro_receive(&ring->tqp_vector->napi, skb);
2188}
2189
1e8f8bd3
PL		 2190static u16 hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2191 struct hns3_desc *desc, u32 l234info)
2192{
2193 struct pci_dev *pdev = ring->tqp->handle->pdev;
2194 u16 vlan_tag;
2195
2196 if (pdev->revision == 0x20) {
2197 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2198 if (!(vlan_tag & VLAN_VID_MASK))
2199 vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2200
2201 return vlan_tag;
2202 }
2203
2204#define HNS3_STRP_OUTER_VLAN 0x1
2205#define HNS3_STRP_INNER_VLAN 0x2
2206
ccc23ef3
PL		 2207 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2208 HNS3_RXD_STRP_TAGP_S)) {
1e8f8bd3
PL		 2209 case HNS3_STRP_OUTER_VLAN:
2210 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2211 break;
2212 case HNS3_STRP_INNER_VLAN:
2213 vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2214 break;
2215 default:
2216 vlan_tag = 0;
2217 break;
2218 }
2219
2220 return vlan_tag;
2221}
2222
76ad4f0e
S		 2223static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2224 struct sk_buff **out_skb, int *out_bnum)
2225{
2226 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2227 struct hns3_desc_cb *desc_cb;
2228 struct hns3_desc *desc;
2229 struct sk_buff *skb;
2230 unsigned char *va;
2231 u32 bd_base_info;
2232 int pull_len;
2233 u32 l234info;
2234 int length;
2235 int bnum;
2236
2237 desc = &ring->desc[ring->next_to_clean];
2238 desc_cb = &ring->desc_cb[ring->next_to_clean];
2239
2240 prefetch(desc);
2241
ca61f05e 2242 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2243 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 2244
2245 /* Check valid BD */
ccc23ef3 2246 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
76ad4f0e
S		 2247 return -EFAULT;
2248
2249 va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
2250
2251 /* Prefetch first cache line of first page
2252 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2253 * line size is 64B so need to prefetch twice to make it 128B. But in
2254 * actual we can have greater size of caches with 128B Level 1 cache
2255 * lines. In such a case, single fetch would suffice to cache in the
2256 * relevant part of the header.
2257 */
2258 prefetch(va);
2259#if L1_CACHE_BYTES < 128
2260 prefetch(va + L1_CACHE_BYTES);
2261#endif
2262
2263 skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2264 HNS3_RX_HEAD_SIZE);
2265 if (unlikely(!skb)) {
2266 netdev_err(netdev, "alloc rx skb fail\n");
2267
2268 u64_stats_update_begin(&ring->syncp);
2269 ring->stats.sw_err_cnt++;
2270 u64_stats_update_end(&ring->syncp);
2271
2272 return -ENOMEM;
2273 }
2274
2275 prefetchw(skb->data);
2276
2277 bnum = 1;
2278 if (length <= HNS3_RX_HEAD_SIZE) {
2279 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2280
2281 /* We can reuse buffer as-is, just make sure it is local */
2282 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2283 desc_cb->reuse_flag = 1;
2284 else /* This page cannot be reused so discard it */
2285 put_page(desc_cb->priv);
2286
2287 ring_ptr_move_fw(ring, next_to_clean);
2288 } else {
2289 u64_stats_update_begin(&ring->syncp);
2290 ring->stats.seg_pkt_cnt++;
2291 u64_stats_update_end(&ring->syncp);
2292
42b927ba
PL		 2293 pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2294
76ad4f0e
S		 2295 memcpy(__skb_put(skb, pull_len), va,
2296 ALIGN(pull_len, sizeof(long)));
2297
2298 hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb);
2299 ring_ptr_move_fw(ring, next_to_clean);
2300
ccc23ef3 2301 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
76ad4f0e
S		 2302 desc = &ring->desc[ring->next_to_clean];
2303 desc_cb = &ring->desc_cb[ring->next_to_clean];
2304 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2305 hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb);
2306 ring_ptr_move_fw(ring, next_to_clean);
2307 bnum++;
2308 }
2309 }
2310
2311 *out_bnum = bnum;
1e8f8bd3 2312
928d369a 2313 l234info = le32_to_cpu(desc->rx.l234_info);
2314
ca61f05e
PL		 2315 /* Based on hw strategy, the tag offloaded will be stored at
2316 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2317 * in one layer tag case.
2318 */
2319 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2320 u16 vlan_tag;
2321
1e8f8bd3 2322 vlan_tag = hns3_parse_vlan_tag(ring, desc, l234info);
ca61f05e
PL		 2323 if (vlan_tag & VLAN_VID_MASK)
2324 __vlan_hwaccel_put_tag(skb,
2325 htons(ETH_P_8021Q),
2326 vlan_tag);
2327 }
2328
ccc23ef3 2329 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
76ad4f0e
S		 2330 u64_stats_update_begin(&ring->syncp);
2331 ring->stats.non_vld_descs++;
2332 u64_stats_update_end(&ring->syncp);
2333
2334 dev_kfree_skb_any(skb);
2335 return -EINVAL;
2336 }
2337
2338 if (unlikely((!desc->rx.pkt_len) ||
ccc23ef3 2339 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
76ad4f0e
S		 2340 u64_stats_update_begin(&ring->syncp);
2341 ring->stats.err_pkt_len++;
2342 u64_stats_update_end(&ring->syncp);
2343
2344 dev_kfree_skb_any(skb);
2345 return -EFAULT;
2346 }
2347
ccc23ef3 2348 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
76ad4f0e
S		 2349 u64_stats_update_begin(&ring->syncp);
2350 ring->stats.l2_err++;
2351 u64_stats_update_end(&ring->syncp);
2352
2353 dev_kfree_skb_any(skb);
2354 return -EFAULT;
2355 }
2356
2357 u64_stats_update_begin(&ring->syncp);
2358 ring->stats.rx_pkts++;
2359 ring->stats.rx_bytes += skb->len;
2360 u64_stats_update_end(&ring->syncp);
2361
2362 ring->tqp_vector->rx_group.total_bytes += skb->len;
2363
2364 hns3_rx_checksum(ring, skb, desc);
2365 return 0;
2366}
2367
d43e5aca
YL		 2368int hns3_clean_rx_ring(
2369 struct hns3_enet_ring *ring, int budget,
2370 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2371{
2372#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2373 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2374 int recv_pkts, recv_bds, clean_count, err;
2375 int unused_count = hns3_desc_unused(ring);
2376 struct sk_buff *skb = NULL;
2377 int num, bnum = 0;
2378
2379 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2380 rmb(); /* Make sure num taken effect before the other data is touched */
2381
2382 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2383 num -= unused_count;
2384
2385 while (recv_pkts < budget && recv_bds < num) {
2386 /* Reuse or realloc buffers */
2387 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2388 hns3_nic_alloc_rx_buffers(ring,
2389 clean_count + unused_count);
2390 clean_count = 0;
2391 unused_count = hns3_desc_unused(ring);
2392 }
2393
2394 /* Poll one pkt */
2395 err = hns3_handle_rx_bd(ring, &skb, &bnum);
2396 if (unlikely(!skb)) /* This fault cannot be repaired */
2397 goto out;
2398
2399 recv_bds += bnum;
2400 clean_count += bnum;
2401 if (unlikely(err)) { /* Do jump the err */
2402 recv_pkts++;
2403 continue;
2404 }
2405
2406 /* Do update ip stack process */
2407 skb->protocol = eth_type_trans(skb, netdev);
d43e5aca 2408 rx_fn(ring, skb);
76ad4f0e
S		 2409
2410 recv_pkts++;
2411 }
2412
2413out:
2414 /* Make all data has been write before submit */
2415 if (clean_count + unused_count > 0)
2416 hns3_nic_alloc_rx_buffers(ring,
2417 clean_count + unused_count);
2418
2419 return recv_pkts;
2420}
2421
2422static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2423{
50477f37
FL		 2424 struct hns3_enet_tqp_vector *tqp_vector =
2425 ring_group->ring->tqp_vector;
76ad4f0e 2426 enum hns3_flow_level_range new_flow_level;
50477f37
FL		 2427 int packets_per_msecs;
2428 int bytes_per_msecs;
2429 u32 time_passed_ms;
76ad4f0e 2430 u16 new_int_gl;
76ad4f0e 2431
50477f37 2432 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies)
76ad4f0e
S		 2433 return false;
2434
2435 if (ring_group->total_packets == 0) {
d420d2de
YL		 2436 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2437 ring_group->coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 2438 return true;
2439 }
2440
2441 /* Simple throttlerate management
2442 * 0-10MB/s lower (50000 ints/s)
2443 * 10-20MB/s middle (20000 ints/s)
2444 * 20-1249MB/s high (18000 ints/s)
2445 * > 40000pps ultra (8000 ints/s)
2446 */
d420d2de
YL		 2447 new_flow_level = ring_group->coal.flow_level;
2448 new_int_gl = ring_group->coal.int_gl;
50477f37
FL		 2449 time_passed_ms =
2450 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2451
2452 if (!time_passed_ms)
2453 return false;
2454
2455 do_div(ring_group->total_packets, time_passed_ms);
2456 packets_per_msecs = ring_group->total_packets;
2457
2458 do_div(ring_group->total_bytes, time_passed_ms);
2459 bytes_per_msecs = ring_group->total_bytes;
2460
2461#define HNS3_RX_LOW_BYTE_RATE 10000
2462#define HNS3_RX_MID_BYTE_RATE 20000
76ad4f0e
S		 2463
2464 switch (new_flow_level) {
2465 case HNS3_FLOW_LOW:
50477f37 2466 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2467 new_flow_level = HNS3_FLOW_MID;
2468 break;
2469 case HNS3_FLOW_MID:
50477f37 2470 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2471 new_flow_level = HNS3_FLOW_HIGH;
50477f37 2472 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2473 new_flow_level = HNS3_FLOW_LOW;
2474 break;
2475 case HNS3_FLOW_HIGH:
2476 case HNS3_FLOW_ULTRA:
2477 default:
50477f37 2478 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2479 new_flow_level = HNS3_FLOW_MID;
2480 break;
2481 }
2482
50477f37
FL		 2483#define HNS3_RX_ULTRA_PACKET_RATE 40
2484
2485 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2486 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 2487 new_flow_level = HNS3_FLOW_ULTRA;
2488
2489 switch (new_flow_level) {
2490 case HNS3_FLOW_LOW:
2491 new_int_gl = HNS3_INT_GL_50K;
2492 break;
2493 case HNS3_FLOW_MID:
2494 new_int_gl = HNS3_INT_GL_20K;
2495 break;
2496 case HNS3_FLOW_HIGH:
2497 new_int_gl = HNS3_INT_GL_18K;
2498 break;
2499 case HNS3_FLOW_ULTRA:
2500 new_int_gl = HNS3_INT_GL_8K;
2501 break;
2502 default:
2503 break;
2504 }
2505
2506 ring_group->total_bytes = 0;
2507 ring_group->total_packets = 0;
d420d2de
YL		 2508 ring_group->coal.flow_level = new_flow_level;
2509 if (new_int_gl != ring_group->coal.int_gl) {
2510 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 2511 return true;
2512 }
2513 return false;
2514}
2515
2516static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2517{
dc114fce
FL		 2518 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2519 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2520 bool rx_update, tx_update;
2521
3f97bd23
FL		 2522 if (tqp_vector->int_adapt_down > 0) {
2523 tqp_vector->int_adapt_down--;
2524 return;
2525 }
2526
d420d2de 2527 if (rx_group->coal.gl_adapt_enable) {
dc114fce
FL		 2528 rx_update = hns3_get_new_int_gl(rx_group);
2529 if (rx_update)
2530 hns3_set_vector_coalesce_rx_gl(tqp_vector,
d420d2de 2531 rx_group->coal.int_gl);
dc114fce
FL		 2532 }
2533
d420d2de 2534 if (tx_group->coal.gl_adapt_enable) {
dc114fce
FL		 2535 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2536 if (tx_update)
2537 hns3_set_vector_coalesce_tx_gl(tqp_vector,
d420d2de 2538 tx_group->coal.int_gl);
76ad4f0e 2539 }
3f97bd23 2540
50477f37 2541 tqp_vector->last_jiffies = jiffies;
3f97bd23 2542 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
76ad4f0e
S		 2543}
2544
2545static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2546{
2547 struct hns3_enet_ring *ring;
2548 int rx_pkt_total = 0;
2549
2550 struct hns3_enet_tqp_vector *tqp_vector =
2551 container_of(napi, struct hns3_enet_tqp_vector, napi);
2552 bool clean_complete = true;
2553 int rx_budget;
2554
2555 /* Since the actual Tx work is minimal, we can give the Tx a larger
2556 * budget and be more aggressive about cleaning up the Tx descriptors.
2557 */
6a38a95f
PL		 2558 hns3_for_each_ring(ring, tqp_vector->tx_group)
2559 hns3_clean_tx_ring(ring);
76ad4f0e
S		 2560
2561 /* make sure rx ring budget not smaller than 1 */
2562 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2563
2564 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 2565 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2566 hns3_rx_skb);
76ad4f0e
S		 2567
2568 if (rx_cleaned >= rx_budget)
2569 clean_complete = false;
2570
2571 rx_pkt_total += rx_cleaned;
2572 }
2573
2574 tqp_vector->rx_group.total_packets += rx_pkt_total;
2575
2576 if (!clean_complete)
2577 return budget;
2578
2579 napi_complete(napi);
2580 hns3_update_new_int_gl(tqp_vector);
2581 hns3_mask_vector_irq(tqp_vector, 1);
2582
2583 return rx_pkt_total;
2584}
2585
2586static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2587 struct hnae3_ring_chain_node *head)
2588{
2589 struct pci_dev *pdev = tqp_vector->handle->pdev;
2590 struct hnae3_ring_chain_node *cur_chain = head;
2591 struct hnae3_ring_chain_node *chain;
2592 struct hns3_enet_ring *tx_ring;
2593 struct hns3_enet_ring *rx_ring;
2594
2595 tx_ring = tqp_vector->tx_group.ring;
2596 if (tx_ring) {
2597 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
ccc23ef3
PL		 2598 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2599 HNAE3_RING_TYPE_TX);
2600 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2601 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 2602
2603 cur_chain->next = NULL;
2604
2605 while (tx_ring->next) {
2606 tx_ring = tx_ring->next;
2607
2608 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2609 GFP_KERNEL);
2610 if (!chain)
2611 return -ENOMEM;
2612
2613 cur_chain->next = chain;
2614 chain->tqp_index = tx_ring->tqp->tqp_index;
ccc23ef3
PL		 2615 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2616 HNAE3_RING_TYPE_TX);
2617 hnae3_set_field(chain->int_gl_idx,
2618 HNAE3_RING_GL_IDX_M,
2619 HNAE3_RING_GL_IDX_S,
2620 HNAE3_RING_GL_TX);
76ad4f0e
S		 2621
2622 cur_chain = chain;
2623 }
2624 }
2625
2626 rx_ring = tqp_vector->rx_group.ring;
2627 if (!tx_ring && rx_ring) {
2628 cur_chain->next = NULL;
2629 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
ccc23ef3
PL		 2630 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2631 HNAE3_RING_TYPE_RX);
2632 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2633 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 2634
2635 rx_ring = rx_ring->next;
2636 }
2637
2638 while (rx_ring) {
2639 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
2640 if (!chain)
2641 return -ENOMEM;
2642
2643 cur_chain->next = chain;
2644 chain->tqp_index = rx_ring->tqp->tqp_index;
ccc23ef3
PL		 2645 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2646 HNAE3_RING_TYPE_RX);
2647 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2648 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
f230c6c5 2649
76ad4f0e
S		 2650 cur_chain = chain;
2651
2652 rx_ring = rx_ring->next;
2653 }
2654
2655 return 0;
2656}
2657
2658static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2659 struct hnae3_ring_chain_node *head)
2660{
2661 struct pci_dev *pdev = tqp_vector->handle->pdev;
2662 struct hnae3_ring_chain_node *chain_tmp, *chain;
2663
2664 chain = head->next;
2665
2666 while (chain) {
2667 chain_tmp = chain->next;
2668 devm_kfree(&pdev->dev, chain);
2669 chain = chain_tmp;
2670 }
2671}
2672
2673static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
2674 struct hns3_enet_ring *ring)
2675{
2676 ring->next = group->ring;
2677 group->ring = ring;
2678
2679 group->count++;
2680}
2681
15040788
PL		 2682static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
2683{
2684 struct pci_dev *pdev = priv->ae_handle->pdev;
2685 struct hns3_enet_tqp_vector *tqp_vector;
2686 int num_vectors = priv->vector_num;
2687 int numa_node;
2688 int vector_i;
2689
2690 numa_node = dev_to_node(&pdev->dev);
2691
2692 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
2693 tqp_vector = &priv->tqp_vector[vector_i];
2694 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
2695 &tqp_vector->affinity_mask);
2696 }
2697}
2698
76ad4f0e
S		 2699static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
2700{
2701 struct hnae3_ring_chain_node vector_ring_chain;
2702 struct hnae3_handle *h = priv->ae_handle;
2703 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 2704 int ret = 0;
2705 u16 i;
2706
15040788
PL		 2707 hns3_nic_set_cpumask(priv);
2708
6cbd6d33
YL		 2709 for (i = 0; i < priv->vector_num; i++) {
2710 tqp_vector = &priv->tqp_vector[i];
2711 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
2712 tqp_vector->num_tqps = 0;
2713 }
76ad4f0e 2714
6cbd6d33
YL		 2715 for (i = 0; i < h->kinfo.num_tqps; i++) {
2716 u16 vector_i = i % priv->vector_num;
2717 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 2718
2719 tqp_vector = &priv->tqp_vector[vector_i];
2720
2721 hns3_add_ring_to_group(&tqp_vector->tx_group,
2722 priv->ring_data[i].ring);
2723
2724 hns3_add_ring_to_group(&tqp_vector->rx_group,
2725 priv->ring_data[i + tqp_num].ring);
2726
76ad4f0e
S		 2727 priv->ring_data[i].ring->tqp_vector = tqp_vector;
2728 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
6cbd6d33 2729 tqp_vector->num_tqps++;
76ad4f0e
S		 2730 }
2731
6cbd6d33 2732 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 2733 tqp_vector = &priv->tqp_vector[i];
2734
2735 tqp_vector->rx_group.total_bytes = 0;
2736 tqp_vector->rx_group.total_packets = 0;
2737 tqp_vector->tx_group.total_bytes = 0;
2738 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 2739 tqp_vector->handle = h;
2740
2741 ret = hns3_get_vector_ring_chain(tqp_vector,
2742 &vector_ring_chain);
2743 if (ret)
6cbd6d33 2744 return ret;
76ad4f0e
S		 2745
2746 ret = h->ae_algo->ops->map_ring_to_vector(h,
2747 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 2748
2749 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2750
6cbd6d33
YL		 2751 if (ret)
2752 return ret;
2753
76ad4f0e
S		 2754 netif_napi_add(priv->netdev, &tqp_vector->napi,
2755 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
2756 }
2757
6cbd6d33
YL		 2758 return 0;
2759}
2760
2761static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
2762{
2763 struct hnae3_handle *h = priv->ae_handle;
2764 struct hns3_enet_tqp_vector *tqp_vector;
2765 struct hnae3_vector_info *vector;
2766 struct pci_dev *pdev = h->pdev;
2767 u16 tqp_num = h->kinfo.num_tqps;
2768 u16 vector_num;
2769 int ret = 0;
2770 u16 i;
2771
2772 /* RSS size, cpu online and vector_num should be the same */
2773 /* Should consider 2p/4p later */
2774 vector_num = min_t(u16, num_online_cpus(), tqp_num);
2775 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
2776 GFP_KERNEL);
2777 if (!vector)
2778 return -ENOMEM;
2779
2780 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
2781
2782 priv->vector_num = vector_num;
2783 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
2784 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
2785 GFP_KERNEL);
2786 if (!priv->tqp_vector) {
2787 ret = -ENOMEM;
2788 goto out;
2789 }
2790
2791 for (i = 0; i < priv->vector_num; i++) {
2792 tqp_vector = &priv->tqp_vector[i];
2793 tqp_vector->idx = i;
2794 tqp_vector->mask_addr = vector[i].io_addr;
2795 tqp_vector->vector_irq = vector[i].vector;
2796 hns3_vector_gl_rl_init(tqp_vector, priv);
2797 }
2798
76ad4f0e
S		 2799out:
2800 devm_kfree(&pdev->dev, vector);
2801 return ret;
2802}
2803
6cbd6d33
YL		 2804static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
2805{
2806 group->ring = NULL;
2807 group->count = 0;
2808}
2809
76ad4f0e
S		 2810static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
2811{
2812 struct hnae3_ring_chain_node vector_ring_chain;
2813 struct hnae3_handle *h = priv->ae_handle;
2814 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 2815 int i, ret;
2816
2817 for (i = 0; i < priv->vector_num; i++) {
2818 tqp_vector = &priv->tqp_vector[i];
2819
2820 ret = hns3_get_vector_ring_chain(tqp_vector,
2821 &vector_ring_chain);
2822 if (ret)
2823 return ret;
2824
2825 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
2826 tqp_vector->vector_irq, &vector_ring_chain);
2827 if (ret)
2828 return ret;
2829
2830 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2831
2832 if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) {
2833 (void)irq_set_affinity_hint(
2834 priv->tqp_vector[i].vector_irq,
2835 NULL);
ae064e61 2836 free_irq(priv->tqp_vector[i].vector_irq,
2837 &priv->tqp_vector[i]);
76ad4f0e
S		 2838 }
2839
2840 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
6cbd6d33
YL		 2841 hns3_clear_ring_group(&tqp_vector->rx_group);
2842 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 2843 netif_napi_del(&priv->tqp_vector[i].napi);
2844 }
2845
6cbd6d33
YL		 2846 return 0;
2847}
2848
2849static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
2850{
2851 struct hnae3_handle *h = priv->ae_handle;
2852 struct pci_dev *pdev = h->pdev;
2853 int i, ret;
2854
2855 for (i = 0; i < priv->vector_num; i++) {
2856 struct hns3_enet_tqp_vector *tqp_vector;
2857
2858 tqp_vector = &priv->tqp_vector[i];
2859 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
2860 if (ret)
2861 return ret;
2862 }
76ad4f0e 2863
6cbd6d33 2864 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 2865 return 0;
2866}
2867
2868static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
2869 int ring_type)
2870{
2871 struct hns3_nic_ring_data *ring_data = priv->ring_data;
2872 int queue_num = priv->ae_handle->kinfo.num_tqps;
2873 struct pci_dev *pdev = priv->ae_handle->pdev;
2874 struct hns3_enet_ring *ring;
2875
2876 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
2877 if (!ring)
2878 return -ENOMEM;
2879
2880 if (ring_type == HNAE3_RING_TYPE_TX) {
2881 ring_data[q->tqp_index].ring = ring;
66b44730 2882 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 2883 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
2884 } else {
2885 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 2886 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 2887 ring->io_base = q->io_base;
2888 }
2889
ccc23ef3 2890 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 2891
76ad4f0e
S		 2892 ring->tqp = q;
2893 ring->desc = NULL;
2894 ring->desc_cb = NULL;
2895 ring->dev = priv->dev;
2896 ring->desc_dma_addr = 0;
2897 ring->buf_size = q->buf_size;
2898 ring->desc_num = q->desc_num;
2899 ring->next_to_use = 0;
2900 ring->next_to_clean = 0;
2901
2902 return 0;
2903}
2904
2905static int hns3_queue_to_ring(struct hnae3_queue *tqp,
2906 struct hns3_nic_priv *priv)
2907{
2908 int ret;
2909
2910 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
2911 if (ret)
2912 return ret;
2913
2914 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
2915 if (ret)
2916 return ret;
2917
2918 return 0;
2919}
2920
2921static int hns3_get_ring_config(struct hns3_nic_priv *priv)
2922{
2923 struct hnae3_handle *h = priv->ae_handle;
2924 struct pci_dev *pdev = h->pdev;
2925 int i, ret;
2926
2927 priv->ring_data = devm_kzalloc(&pdev->dev, h->kinfo.num_tqps *
2928 sizeof(*priv->ring_data) * 2,
2929 GFP_KERNEL);
2930 if (!priv->ring_data)
2931 return -ENOMEM;
2932
2933 for (i = 0; i < h->kinfo.num_tqps; i++) {
2934 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
2935 if (ret)
2936 goto err;
2937 }
2938
2939 return 0;
2940err:
2941 devm_kfree(&pdev->dev, priv->ring_data);
2942 return ret;
2943}
2944
f1f779ce
PL		 2945static void hns3_put_ring_config(struct hns3_nic_priv *priv)
2946{
2947 struct hnae3_handle *h = priv->ae_handle;
2948 int i;
2949
2950 for (i = 0; i < h->kinfo.num_tqps; i++) {
2951 devm_kfree(priv->dev, priv->ring_data[i].ring);
2952 devm_kfree(priv->dev,
2953 priv->ring_data[i + h->kinfo.num_tqps].ring);
2954 }
2955 devm_kfree(priv->dev, priv->ring_data);
2956}
2957
76ad4f0e
S		 2958static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
2959{
2960 int ret;
2961
2962 if (ring->desc_num <= 0 || ring->buf_size <= 0)
2963 return -EINVAL;
2964
2965 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
2966 GFP_KERNEL);
2967 if (!ring->desc_cb) {
2968 ret = -ENOMEM;
2969 goto out;
2970 }
2971
2972 ret = hns3_alloc_desc(ring);
2973 if (ret)
2974 goto out_with_desc_cb;
2975
2976 if (!HNAE3_IS_TX_RING(ring)) {
2977 ret = hns3_alloc_ring_buffers(ring);
2978 if (ret)
2979 goto out_with_desc;
2980 }
2981
2982 return 0;
2983
2984out_with_desc:
2985 hns3_free_desc(ring);
2986out_with_desc_cb:
2987 kfree(ring->desc_cb);
2988 ring->desc_cb = NULL;
2989out:
2990 return ret;
2991}
2992
2993static void hns3_fini_ring(struct hns3_enet_ring *ring)
2994{
2995 hns3_free_desc(ring);
2996 kfree(ring->desc_cb);
2997 ring->desc_cb = NULL;
2998 ring->next_to_clean = 0;
2999 ring->next_to_use = 0;
3000}
3001
1db9b1bf 3002static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3003{
3004 int bd_size_type;
3005
3006 switch (buf_size) {
3007 case 512:
3008 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3009 break;
3010 case 1024:
3011 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3012 break;
3013 case 2048:
3014 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3015 break;
3016 case 4096:
3017 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3018 break;
3019 default:
3020 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3021 }
3022
3023 return bd_size_type;
3024}
3025
3026static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3027{
3028 dma_addr_t dma = ring->desc_dma_addr;
3029 struct hnae3_queue *q = ring->tqp;
3030
3031 if (!HNAE3_IS_TX_RING(ring)) {
3032 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3033 (u32)dma);
3034 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3035 (u32)((dma >> 31) >> 1));
3036
3037 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3038 hns3_buf_size2type(ring->buf_size));
3039 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3040 ring->desc_num / 8 - 1);
3041
3042 } else {
3043 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3044 (u32)dma);
3045 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3046 (u32)((dma >> 31) >> 1));
3047
76ad4f0e
S		 3048 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3049 ring->desc_num / 8 - 1);
3050 }
3051}
3052
fe46c859
YL		 3053static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3054{
3055 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3056 int i;
3057
3058 for (i = 0; i < HNAE3_MAX_TC; i++) {
3059 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3060 int j;
3061
3062 if (!tc_info->enable)
3063 continue;
3064
3065 for (j = 0; j < tc_info->tqp_count; j++) {
3066 struct hnae3_queue *q;
3067
3068 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3069 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3070 tc_info->tc);
3071 }
3072 }
3073}
3074
5668abda 3075int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3076{
3077 struct hnae3_handle *h = priv->ae_handle;
3078 int ring_num = h->kinfo.num_tqps * 2;
3079 int i, j;
3080 int ret;
3081
3082 for (i = 0; i < ring_num; i++) {
3083 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3084 if (ret) {
3085 dev_err(priv->dev,
3086 "Alloc ring memory fail! ret=%d\n", ret);
3087 goto out_when_alloc_ring_memory;
3088 }
3089
76ad4f0e
S		 3090 u64_stats_init(&priv->ring_data[i].ring->syncp);
3091 }
3092
3093 return 0;
3094
3095out_when_alloc_ring_memory:
3096 for (j = i - 1; j >= 0; j--)
ee83f776 3097 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 3098
3099 return -ENOMEM;
3100}
3101
5668abda 3102int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3103{
3104 struct hnae3_handle *h = priv->ae_handle;
3105 int i;
3106
3107 for (i = 0; i < h->kinfo.num_tqps; i++) {
3108 if (h->ae_algo->ops->reset_queue)
3109 h->ae_algo->ops->reset_queue(h, i);
3110
3111 hns3_fini_ring(priv->ring_data[i].ring);
3112 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3113 }
76ad4f0e
S		 3114 return 0;
3115}
3116
3117/* Set mac addr if it is configured. or leave it to the AE driver */
edf76c8e 3118static void hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 3119{
3120 struct hns3_nic_priv *priv = netdev_priv(netdev);
3121 struct hnae3_handle *h = priv->ae_handle;
3122 u8 mac_addr_temp[ETH_ALEN];
3123
edf76c8e 3124 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 3125 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3126 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3127 }
3128
3129 /* Check if the MAC address is valid, if not get a random one */
3130 if (!is_valid_ether_addr(netdev->dev_addr)) {
3131 eth_hw_addr_random(netdev);
3132 dev_warn(priv->dev, "using random MAC address %pM\n",
3133 netdev->dev_addr);
76ad4f0e 3134 }
139e8792
L		 3135
3136 if (h->ae_algo->ops->set_mac_addr)
3cbf5e2d 3137 h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3138
76ad4f0e
S		 3139}
3140
cbe8be06
JS		 3141static void hns3_uninit_mac_addr(struct net_device *netdev)
3142{
3143 struct hns3_nic_priv *priv = netdev_priv(netdev);
3144 struct hnae3_handle *h = priv->ae_handle;
3145
3146 if (h->ae_algo->ops->rm_uc_addr)
3147 h->ae_algo->ops->rm_uc_addr(h, netdev->dev_addr);
3148}
3149
76ad4f0e
S		 3150static void hns3_nic_set_priv_ops(struct net_device *netdev)
3151{
3152 struct hns3_nic_priv *priv = netdev_priv(netdev);
3153
3154 if ((netdev->features & NETIF_F_TSO) ||
3155 (netdev->features & NETIF_F_TSO6)) {
3156 priv->ops.fill_desc = hns3_fill_desc_tso;
3157 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
3158 } else {
3159 priv->ops.fill_desc = hns3_fill_desc;
3160 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
3161 }
3162}
3163
3164static int hns3_client_init(struct hnae3_handle *handle)
3165{
3166 struct pci_dev *pdev = handle->pdev;
3167 struct hns3_nic_priv *priv;
3168 struct net_device *netdev;
3169 int ret;
3170
3171 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv),
2d7187ce 3172 hns3_get_max_available_channels(handle));
76ad4f0e
S		 3173 if (!netdev)
3174 return -ENOMEM;
3175
3176 priv = netdev_priv(netdev);
3177 priv->dev = &pdev->dev;
3178 priv->netdev = netdev;
3179 priv->ae_handle = handle;
4aef908d 3180 priv->ae_handle->last_reset_time = jiffies;
f8fa222c 3181 priv->tx_timeout_count = 0;
76ad4f0e
S		 3182
3183 handle->kinfo.netdev = netdev;
3184 handle->priv = (void *)priv;
3185
edf76c8e 3186 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3187
3188 hns3_set_default_feature(netdev);
3189
3190 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3191 netdev->priv_flags |= IFF_UNICAST_FLT;
3192 netdev->netdev_ops = &hns3_nic_netdev_ops;
3193 SET_NETDEV_DEV(netdev, &pdev->dev);
3194 hns3_ethtool_set_ops(netdev);
3195 hns3_nic_set_priv_ops(netdev);
3196
3197 /* Carrier off reporting is important to ethtool even BEFORE open */
3198 netif_carrier_off(netdev);
3199
ca16933f
YL		 3200 if (handle->flags & HNAE3_SUPPORT_VF)
3201 handle->reset_level = HNAE3_VF_RESET;
3202 else
3203 handle->reset_level = HNAE3_FUNC_RESET;
3204
76ad4f0e
S		 3205 ret = hns3_get_ring_config(priv);
3206 if (ret) {
3207 ret = -ENOMEM;
3208 goto out_get_ring_cfg;
3209 }
3210
6cbd6d33
YL		 3211 ret = hns3_nic_alloc_vector_data(priv);
3212 if (ret) {
3213 ret = -ENOMEM;
3214 goto out_alloc_vector_data;
3215 }
3216
76ad4f0e
S		 3217 ret = hns3_nic_init_vector_data(priv);
3218 if (ret) {
3219 ret = -ENOMEM;
3220 goto out_init_vector_data;
3221 }
3222
3223 ret = hns3_init_all_ring(priv);
3224 if (ret) {
3225 ret = -ENOMEM;
3226 goto out_init_ring_data;
3227 }
3228
3229 ret = register_netdev(netdev);
3230 if (ret) {
3231 dev_err(priv->dev, "probe register netdev fail!\n");
3232 goto out_reg_netdev_fail;
3233 }
3234
986743db
YL		 3235 hns3_dcbnl_setup(handle);
3236
a8e8b7ff
S		 3237 /* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */
3238 netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
3239
76ad4f0e
S		 3240 return ret;
3241
3242out_reg_netdev_fail:
3243out_init_ring_data:
3244 (void)hns3_nic_uninit_vector_data(priv);
76ad4f0e 3245out_init_vector_data:
6cbd6d33
YL		 3246 hns3_nic_dealloc_vector_data(priv);
3247out_alloc_vector_data:
3248 priv->ring_data = NULL;
76ad4f0e
S		 3249out_get_ring_cfg:
3250 priv->ae_handle = NULL;
3251 free_netdev(netdev);
3252 return ret;
3253}
3254
3255static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3256{
3257 struct net_device *netdev = handle->kinfo.netdev;
3258 struct hns3_nic_priv *priv = netdev_priv(netdev);
3259 int ret;
3260
3261 if (netdev->reg_state != NETREG_UNINITIALIZED)
3262 unregister_netdev(netdev);
3263
e32a805a
FL		 3264 hns3_force_clear_all_rx_ring(handle);
3265
76ad4f0e
S		 3266 ret = hns3_nic_uninit_vector_data(priv);
3267 if (ret)
3268 netdev_err(netdev, "uninit vector error\n");
3269
6cbd6d33
YL		 3270 ret = hns3_nic_dealloc_vector_data(priv);
3271 if (ret)
3272 netdev_err(netdev, "dealloc vector error\n");
3273
76ad4f0e
S		 3274 ret = hns3_uninit_all_ring(priv);
3275 if (ret)
3276 netdev_err(netdev, "uninit ring error\n");
3277
a2ddee8c
YL		 3278 hns3_put_ring_config(priv);
3279
76ad4f0e
S		 3280 priv->ring_data = NULL;
3281
cbe8be06
JS		 3282 hns3_uninit_mac_addr(netdev);
3283
76ad4f0e
S		 3284 free_netdev(netdev);
3285}
3286
3287static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3288{
3289 struct net_device *netdev = handle->kinfo.netdev;
3290
3291 if (!netdev)
3292 return;
3293
3294 if (linkup) {
3295 netif_carrier_on(netdev);
3296 netif_tx_wake_all_queues(netdev);
3297 netdev_info(netdev, "link up\n");
3298 } else {
3299 netif_carrier_off(netdev);
3300 netif_tx_stop_all_queues(netdev);
3301 netdev_info(netdev, "link down\n");
3302 }
3303}
3304
9df8f79a
YL		 3305static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3306{
3307 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3308 struct net_device *ndev = kinfo->netdev;
075cfdd6 3309 bool if_running;
9df8f79a 3310 int ret;
9df8f79a
YL		 3311
3312 if (tc > HNAE3_MAX_TC)
3313 return -EINVAL;
3314
3315 if (!ndev)
3316 return -ENODEV;
3317
075cfdd6
CIK		 3318 if_running = netif_running(ndev);
3319
9df8f79a
YL		 3320 if (if_running) {
3321 (void)hns3_nic_net_stop(ndev);
3322 msleep(100);
3323 }
3324
3325 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3326 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3327 if (ret)
3328 goto err_out;
3329
9df8f79a
YL		 3330 ret = hns3_nic_set_real_num_queue(ndev);
3331
3332err_out:
3333 if (if_running)
3334 (void)hns3_nic_net_open(ndev);
3335
3336 return ret;
3337}
3338
bb6b94a8
L		 3339static void hns3_recover_hw_addr(struct net_device *ndev)
3340{
3341 struct netdev_hw_addr_list *list;
3342 struct netdev_hw_addr *ha, *tmp;
3343
3344 /* go through and sync uc_addr entries to the device */
3345 list = &ndev->uc;
3346 list_for_each_entry_safe(ha, tmp, &list->list, list)
3347 hns3_nic_uc_sync(ndev, ha->addr);
3348
3349 /* go through and sync mc_addr entries to the device */
3350 list = &ndev->mc;
3351 list_for_each_entry_safe(ha, tmp, &list->list, list)
3352 hns3_nic_mc_sync(ndev, ha->addr);
3353}
3354
82172ec9 3355static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 3356{
82172ec9 3357 while (ring->next_to_clean != ring->next_to_use) {
e32a805a 3358 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
82172ec9
YL		 3359 hns3_free_buffer_detach(ring, ring->next_to_clean);
3360 ring_ptr_move_fw(ring, next_to_clean);
3361 }
3362}
3363
e32a805a
FL		 3364static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3365{
3366 struct hns3_desc_cb res_cbs;
3367 int ret;
3368
3369 while (ring->next_to_use != ring->next_to_clean) {
3370 /* When a buffer is not reused, it's memory has been
3371 * freed in hns3_handle_rx_bd or will be freed by
3372 * stack, so we need to replace the buffer here.
3373 */
3374 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3375 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3376 if (ret) {
3377 u64_stats_update_begin(&ring->syncp);
3378 ring->stats.sw_err_cnt++;
3379 u64_stats_update_end(&ring->syncp);
3380 /* if alloc new buffer fail, exit directly
3381 * and reclear in up flow.
3382 */
3383 netdev_warn(ring->tqp->handle->kinfo.netdev,
3384 "reserve buffer map failed, ret = %d\n",
3385 ret);
3386 return ret;
3387 }
3388 hns3_replace_buffer(ring, ring->next_to_use,
3389 &res_cbs);
3390 }
3391 ring_ptr_move_fw(ring, next_to_use);
3392 }
3393
3394 return 0;
3395}
3396
3397static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
82172ec9 3398{
82172ec9
YL		 3399 while (ring->next_to_use != ring->next_to_clean) {
3400 /* When a buffer is not reused, it's memory has been
3401 * freed in hns3_handle_rx_bd or will be freed by
3402 * stack, so only need to unmap the buffer here.
3403 */
3404 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3405 hns3_unmap_buffer(ring,
3406 &ring->desc_cb[ring->next_to_use]);
3407 ring->desc_cb[ring->next_to_use].dma = 0;
3408 }
3409
3410 ring_ptr_move_fw(ring, next_to_use);
3411 }
bb6b94a8
L		 3412}
3413
e32a805a
FL		 3414static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3415{
3416 struct net_device *ndev = h->kinfo.netdev;
3417 struct hns3_nic_priv *priv = netdev_priv(ndev);
3418 struct hns3_enet_ring *ring;
3419 u32 i;
3420
3421 for (i = 0; i < h->kinfo.num_tqps; i++) {
3422 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3423 hns3_force_clear_rx_ring(ring);
3424 }
3425}
3426
bb6b94a8
L		 3427static void hns3_clear_all_ring(struct hnae3_handle *h)
3428{
3429 struct net_device *ndev = h->kinfo.netdev;
3430 struct hns3_nic_priv *priv = netdev_priv(ndev);
3431 u32 i;
3432
3433 for (i = 0; i < h->kinfo.num_tqps; i++) {
3434 struct netdev_queue *dev_queue;
3435 struct hns3_enet_ring *ring;
3436
3437 ring = priv->ring_data[i].ring;
82172ec9 3438 hns3_clear_tx_ring(ring);
bb6b94a8
L		 3439 dev_queue = netdev_get_tx_queue(ndev,
3440 priv->ring_data[i].queue_index);
3441 netdev_tx_reset_queue(dev_queue);
3442
3443 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
e32a805a
FL		 3444 /* Continue to clear other rings even if clearing some
3445 * rings failed.
3446 */
82172ec9 3447 hns3_clear_rx_ring(ring);
bb6b94a8
L		 3448 }
3449}
3450
e32a805a
FL		 3451int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3452{
3453 struct net_device *ndev = h->kinfo.netdev;
3454 struct hns3_nic_priv *priv = netdev_priv(ndev);
3455 struct hns3_enet_ring *rx_ring;
3456 int i, j;
3457 int ret;
3458
3459 for (i = 0; i < h->kinfo.num_tqps; i++) {
3460 h->ae_algo->ops->reset_queue(h, i);
3461 hns3_init_ring_hw(priv->ring_data[i].ring);
3462
3463 /* We need to clear tx ring here because self test will
3464 * use the ring and will not run down before up
3465 */
3466 hns3_clear_tx_ring(priv->ring_data[i].ring);
3467 priv->ring_data[i].ring->next_to_clean = 0;
3468 priv->ring_data[i].ring->next_to_use = 0;
3469
3470 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3471 hns3_init_ring_hw(rx_ring);
3472 ret = hns3_clear_rx_ring(rx_ring);
3473 if (ret)
3474 return ret;
3475
3476 /* We can not know the hardware head and tail when this
3477 * function is called in reset flow, so we reuse all desc.
3478 */
3479 for (j = 0; j < rx_ring->desc_num; j++)
3480 hns3_reuse_buffer(rx_ring, j);
3481
3482 rx_ring->next_to_clean = 0;
3483 rx_ring->next_to_use = 0;
3484 }
3485
fe46c859
YL		 3486 hns3_init_tx_ring_tc(priv);
3487
e32a805a
FL		 3488 return 0;
3489}
3490
bb6b94a8
L		 3491static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3492{
3493 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3494 struct net_device *ndev = kinfo->netdev;
3495
3496 if (!netif_running(ndev))
196b8760 3497 return 0;
bb6b94a8
L		 3498
3499 return hns3_nic_net_stop(ndev);
3500}
3501
3502static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
3503{
3504 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
bb6b94a8
L		 3505 int ret = 0;
3506
3507 if (netif_running(kinfo->netdev)) {
3508 ret = hns3_nic_net_up(kinfo->netdev);
3509 if (ret) {
3510 netdev_err(kinfo->netdev,
3511 "hns net up fail, ret=%d!\n", ret);
3512 return ret;
3513 }
4aef908d 3514 handle->last_reset_time = jiffies;
bb6b94a8
L		 3515 }
3516
3517 return ret;
3518}
3519
3520static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
3521{
3522 struct net_device *netdev = handle->kinfo.netdev;
3523 struct hns3_nic_priv *priv = netdev_priv(netdev);
3524 int ret;
3525
edf76c8e 3526 hns3_init_mac_addr(netdev, false);
bb6b94a8
L		 3527 hns3_nic_set_rx_mode(netdev);
3528 hns3_recover_hw_addr(netdev);
3529
103ce052
YL		 3530 /* Hardware table is only clear when pf resets */
3531 if (!(handle->flags & HNAE3_SUPPORT_VF))
3532 hns3_restore_vlan(netdev);
3533
bb6b94a8
L		 3534 /* Carrier off reporting is important to ethtool even BEFORE open */
3535 netif_carrier_off(netdev);
3536
bb6b94a8
L		 3537 ret = hns3_nic_init_vector_data(priv);
3538 if (ret)
3539 return ret;
3540
3541 ret = hns3_init_all_ring(priv);
3542 if (ret) {
3543 hns3_nic_uninit_vector_data(priv);
3544 priv->ring_data = NULL;
3545 }
3546
3547 return ret;
3548}
3549
3550static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
3551{
3552 struct net_device *netdev = handle->kinfo.netdev;
3553 struct hns3_nic_priv *priv = netdev_priv(netdev);
3554 int ret;
3555
e32a805a 3556 hns3_force_clear_all_rx_ring(handle);
bb6b94a8
L		 3557
3558 ret = hns3_nic_uninit_vector_data(priv);
3559 if (ret) {
3560 netdev_err(netdev, "uninit vector error\n");
3561 return ret;
3562 }
3563
3564 ret = hns3_uninit_all_ring(priv);
3565 if (ret)
3566 netdev_err(netdev, "uninit ring error\n");
3567
cbe8be06
JS		 3568 hns3_uninit_mac_addr(netdev);
3569
bb6b94a8
L		 3570 return ret;
3571}
3572
3573static int hns3_reset_notify(struct hnae3_handle *handle,
3574 enum hnae3_reset_notify_type type)
3575{
3576 int ret = 0;
3577
3578 switch (type) {
3579 case HNAE3_UP_CLIENT:
741e1778
SM		 3580 ret = hns3_reset_notify_up_enet(handle);
3581 break;
bb6b94a8
L		 3582 case HNAE3_DOWN_CLIENT:
3583 ret = hns3_reset_notify_down_enet(handle);
3584 break;
3585 case HNAE3_INIT_CLIENT:
3586 ret = hns3_reset_notify_init_enet(handle);
3587 break;
3588 case HNAE3_UNINIT_CLIENT:
3589 ret = hns3_reset_notify_uninit_enet(handle);
3590 break;
3591 default:
3592 break;
3593 }
3594
3595 return ret;
3596}
3597
351dad5e
YL		 3598static void hns3_restore_coal(struct hns3_nic_priv *priv,
3599 struct hns3_enet_coalesce *tx,
3600 struct hns3_enet_coalesce *rx)
3601{
3602 u16 vector_num = priv->vector_num;
3603 int i;
3604
3605 for (i = 0; i < vector_num; i++) {
3606 memcpy(&priv->tqp_vector[i].tx_group.coal, tx,
3607 sizeof(struct hns3_enet_coalesce));
3608 memcpy(&priv->tqp_vector[i].rx_group.coal, rx,
3609 sizeof(struct hns3_enet_coalesce));
3610 }
3611}
3612
3613static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num,
3614 struct hns3_enet_coalesce *tx,
3615 struct hns3_enet_coalesce *rx)
f1f779ce
PL		 3616{
3617 struct hns3_nic_priv *priv = netdev_priv(netdev);
3618 struct hnae3_handle *h = hns3_get_handle(netdev);
3619 int ret;
3620
3621 ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
3622 if (ret)
3623 return ret;
3624
3625 ret = hns3_get_ring_config(priv);
3626 if (ret)
3627 return ret;
3628
6cbd6d33
YL		 3629 ret = hns3_nic_alloc_vector_data(priv);
3630 if (ret)
3631 goto err_alloc_vector;
3632
351dad5e
YL		 3633 hns3_restore_coal(priv, tx, rx);
3634
f1f779ce
PL		 3635 ret = hns3_nic_init_vector_data(priv);
3636 if (ret)
3637 goto err_uninit_vector;
3638
3639 ret = hns3_init_all_ring(priv);
3640 if (ret)
3641 goto err_put_ring;
3642
3643 return 0;
3644
3645err_put_ring:
3646 hns3_put_ring_config(priv);
3647err_uninit_vector:
3648 hns3_nic_uninit_vector_data(priv);
6cbd6d33
YL		 3649err_alloc_vector:
3650 hns3_nic_dealloc_vector_data(priv);
f1f779ce
PL		 3651 return ret;
3652}
3653
3654static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num)
3655{
3656 return (new_tqp_num / num_tc) * num_tc;
3657}
3658
3659int hns3_set_channels(struct net_device *netdev,
3660 struct ethtool_channels *ch)
3661{
3662 struct hns3_nic_priv *priv = netdev_priv(netdev);
3663 struct hnae3_handle *h = hns3_get_handle(netdev);
3664 struct hnae3_knic_private_info *kinfo = &h->kinfo;
351dad5e 3665 struct hns3_enet_coalesce tx_coal, rx_coal;
f1f779ce
PL		 3666 bool if_running = netif_running(netdev);
3667 u32 new_tqp_num = ch->combined_count;
3668 u16 org_tqp_num;
3669 int ret;
3670
3671 if (ch->rx_count || ch->tx_count)
3672 return -EINVAL;
3673
2d7187ce 3674 if (new_tqp_num > hns3_get_max_available_channels(h) ||
f1f779ce
PL		 3675 new_tqp_num < kinfo->num_tc) {
3676 dev_err(&netdev->dev,
3677 "Change tqps fail, the tqp range is from %d to %d",
3678 kinfo->num_tc,
2d7187ce 3679 hns3_get_max_available_channels(h));
f1f779ce
PL		 3680 return -EINVAL;
3681 }
3682
3683 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num);
3684 if (kinfo->num_tqps == new_tqp_num)
3685 return 0;
3686
3687 if (if_running)
41efd6b1 3688 hns3_nic_net_stop(netdev);
f1f779ce 3689
f1f779ce
PL		 3690 ret = hns3_nic_uninit_vector_data(priv);
3691 if (ret) {
3692 dev_err(&netdev->dev,
3693 "Unbind vector with tqp fail, nothing is changed");
3694 goto open_netdev;
3695 }
3696
351dad5e
YL		 3697 /* Changing the tqp num may also change the vector num,
3698 * ethtool only support setting and querying one coal
3699 * configuation for now, so save the vector 0' coal
3700 * configuation here in order to restore it.
3701 */
3702 memcpy(&tx_coal, &priv->tqp_vector[0].tx_group.coal,
3703 sizeof(struct hns3_enet_coalesce));
3704 memcpy(&rx_coal, &priv->tqp_vector[0].rx_group.coal,
3705 sizeof(struct hns3_enet_coalesce));
3706
6cbd6d33
YL		 3707 hns3_nic_dealloc_vector_data(priv);
3708
f1f779ce 3709 hns3_uninit_all_ring(priv);
a2ddee8c 3710 hns3_put_ring_config(priv);
f1f779ce
PL		 3711
3712 org_tqp_num = h->kinfo.num_tqps;
351dad5e 3713 ret = hns3_modify_tqp_num(netdev, new_tqp_num, &tx_coal, &rx_coal);
f1f779ce 3714 if (ret) {
351dad5e
YL		 3715 ret = hns3_modify_tqp_num(netdev, org_tqp_num,
3716 &tx_coal, &rx_coal);
f1f779ce
PL		 3717 if (ret) {
3718 /* If revert to old tqp failed, fatal error occurred */
3719 dev_err(&netdev->dev,
3720 "Revert to old tqp num fail, ret=%d", ret);
3721 return ret;
3722 }
3723 dev_info(&netdev->dev,
3724 "Change tqp num fail, Revert to old tqp num");
3725 }
3726
3727open_netdev:
3728 if (if_running)
41efd6b1 3729 hns3_nic_net_open(netdev);
f1f779ce
PL		 3730
3731 return ret;
3732}
3733
1db9b1bf 3734static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 3735 .init_instance = hns3_client_init,
3736 .uninit_instance = hns3_client_uninit,
3737 .link_status_change = hns3_link_status_change,
9df8f79a 3738 .setup_tc = hns3_client_setup_tc,
bb6b94a8 3739 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 3740};
3741
3742/* hns3_init_module - Driver registration routine
3743 * hns3_init_module is the first routine called when the driver is
3744 * loaded. All it does is register with the PCI subsystem.
3745 */
3746static int __init hns3_init_module(void)
3747{
3748 int ret;
3749
3750 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
3751 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
3752
3753 client.type = HNAE3_CLIENT_KNIC;
3754 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
3755 hns3_driver_name);
3756
3757 client.ops = &client_ops;
3758
dadc9935
XW		 3759 INIT_LIST_HEAD(&client.node);
3760
76ad4f0e
S		 3761 ret = hnae3_register_client(&client);
3762 if (ret)
3763 return ret;
3764
3765 ret = pci_register_driver(&hns3_driver);
3766 if (ret)
3767 hnae3_unregister_client(&client);
3768
3769 return ret;
3770}
3771module_init(hns3_init_module);
3772
3773/* hns3_exit_module - Driver exit cleanup routine
3774 * hns3_exit_module is called just before the driver is removed
3775 * from memory.
3776 */
3777static void __exit hns3_exit_module(void)
3778{
3779 pci_unregister_driver(&hns3_driver);
3780 hnae3_unregister_client(&client);
3781}
3782module_exit(hns3_exit_module);
3783
3784MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
3785MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3786MODULE_LICENSE("GPL");
3787MODULE_ALIAS("pci:hns-nic");
4786ad87 3788MODULE_VERSION(HNS3_MOD_VERSION);
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