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net: hns3: fix loop condition of hns3_get_tx_timeo_queue_info()
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
ef57c40f
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
7#include <linux/if_vlan.h>
8#include <linux/ip.h>
9#include <linux/ipv6.h>
10#include <linux/module.h>
11#include <linux/pci.h>
538d8ba0 12#include <linux/aer.h>
76ad4f0e
S		 13#include <linux/skbuff.h>
14#include <linux/sctp.h>
15#include <linux/vermagic.h>
16#include <net/gre.h>
30d240df 17#include <net/pkt_cls.h>
5337b725 18#include <net/tcp.h>
76ad4f0e
S		 19#include <net/vxlan.h>
20
21#include "hnae3.h"
22#include "hns3_enet.h"
23
e32a805a
FL		 24static void hns3_clear_all_ring(struct hnae3_handle *h);
25static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
2c794374 26static void hns3_remove_hw_addr(struct net_device *netdev);
e32a805a 27
1db9b1bf 28static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 29const char hns3_driver_version[] = VERMAGIC_STRING;
30static const char hns3_driver_string[] =
31 "Hisilicon Ethernet Network Driver for Hip08 Family";
32static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
33static struct hnae3_client client;
34
35/* hns3_pci_tbl - PCI Device ID Table
36 *
37 * Last entry must be all 0s
38 *
39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
40 * Class, Class Mask, private data (not used) }
41 */
42static const struct pci_device_id hns3_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
a9c89a3f 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
f4e4e86c
JS		 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 58 /* required last entry */
59 {0, }
60};
61MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
62
5a8b1a40 63static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 64{
5a8b1a40 65 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e
S		 66
67 napi_schedule(&tqp_vector->napi);
68
69 return IRQ_HANDLED;
70}
71
15040788
PL		 72/* This callback function is used to set affinity changes to the irq affinity
73 * masks when the irq_set_affinity_notifier function is used.
74 */
75static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify,
76 const cpumask_t *mask)
77{
78 struct hns3_enet_tqp_vector *tqp_vectors =
79 container_of(notify, struct hns3_enet_tqp_vector,
80 affinity_notify);
81
82 tqp_vectors->affinity_mask = *mask;
83}
84
85static void hns3_nic_irq_affinity_release(struct kref *ref)
86{
87}
88
76ad4f0e
S		 89static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
90{
91 struct hns3_enet_tqp_vector *tqp_vectors;
92 unsigned int i;
93
94 for (i = 0; i < priv->vector_num; i++) {
95 tqp_vectors = &priv->tqp_vector[i];
96
97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
98 continue;
99
15040788
PL		 100 /* clear the affinity notifier and affinity mask */
101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL);
102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
103
76ad4f0e
S		 104 /* release the irq resource */
105 free_irq(tqp_vectors->vector_irq, tqp_vectors);
106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
107 }
108}
109
110static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
111{
112 struct hns3_enet_tqp_vector *tqp_vectors;
113 int txrx_int_idx = 0;
114 int rx_int_idx = 0;
115 int tx_int_idx = 0;
116 unsigned int i;
117 int ret;
118
119 for (i = 0; i < priv->vector_num; i++) {
120 tqp_vectors = &priv->tqp_vector[i];
121
122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
123 continue;
124
125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
127 "%s-%s-%d", priv->netdev->name, "TxRx",
128 txrx_int_idx++);
129 txrx_int_idx++;
130 } else if (tqp_vectors->rx_group.ring) {
131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
132 "%s-%s-%d", priv->netdev->name, "Rx",
133 rx_int_idx++);
134 } else if (tqp_vectors->tx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
136 "%s-%s-%d", priv->netdev->name, "Tx",
137 tx_int_idx++);
138 } else {
139 /* Skip this unused q_vector */
140 continue;
141 }
142
143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
144
145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
146 tqp_vectors->name,
147 tqp_vectors);
148 if (ret) {
149 netdev_err(priv->netdev, "request irq(%d) fail\n",
150 tqp_vectors->vector_irq);
151 return ret;
152 }
153
15040788
PL		 154 tqp_vectors->affinity_notify.notify =
155 hns3_nic_irq_affinity_notify;
156 tqp_vectors->affinity_notify.release =
157 hns3_nic_irq_affinity_release;
158 irq_set_affinity_notifier(tqp_vectors->vector_irq,
159 &tqp_vectors->affinity_notify);
160 irq_set_affinity_hint(tqp_vectors->vector_irq,
161 &tqp_vectors->affinity_mask);
162
76ad4f0e
S		 163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
164 }
165
166 return 0;
167}
168
169static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
170 u32 mask_en)
171{
172 writel(mask_en, tqp_vector->mask_addr);
173}
174
175static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
176{
177 napi_enable(&tqp_vector->napi);
178
179 /* enable vector */
180 hns3_mask_vector_irq(tqp_vector, 1);
181}
182
183static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
184{
185 /* disable vector */
186 hns3_mask_vector_irq(tqp_vector, 0);
187
188 disable_irq(tqp_vector->vector_irq);
189 napi_disable(&tqp_vector->napi);
190}
191
5acd0356
FL		 192void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
193 u32 rl_value)
76ad4f0e 194{
5acd0356
FL		 195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
196
76ad4f0e
S		 197 /* this defines the configuration for RL (Interrupt Rate Limiter).
198 * Rl defines rate of interrupts i.e. number of interrupts-per-second
199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
200 */
5acd0356 201
d420d2de
YL		 202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
203 !tqp_vector->rx_group.coal.gl_adapt_enable)
5acd0356
FL		 204 /* According to the hardware, the range of rl_reg is
205 * 0-59 and the unit is 4.
206 */
207 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
208
209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
210}
211
212void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
213 u32 gl_value)
214{
215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
216
217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
218}
219
220void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
221 u32 gl_value)
222{
223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
224
225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 226}
227
2b27decc
FL		 228static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
229 struct hns3_nic_priv *priv)
76ad4f0e
S		 230{
231 /* initialize the configuration for interrupt coalescing.
232 * 1. GL (Interrupt Gap Limiter)
233 * 2. RL (Interrupt Rate Limiter)
234 */
235
2b27decc 236 /* Default: enable interrupt coalescing self-adaptive and GL */
d420d2de
YL		 237 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
238 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
2b27decc 239
d420d2de
YL		 240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
2b27decc 242
d420d2de
YL		 243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 245}
246
6cbd6d33
YL		 247static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
248 struct hns3_nic_priv *priv)
249{
250 struct hnae3_handle *h = priv->ae_handle;
251
252 hns3_set_vector_coalesce_tx_gl(tqp_vector,
d420d2de 253 tqp_vector->tx_group.coal.int_gl);
6cbd6d33 254 hns3_set_vector_coalesce_rx_gl(tqp_vector,
d420d2de 255 tqp_vector->rx_group.coal.int_gl);
6cbd6d33
YL		 256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
257}
258
9df8f79a
YL		 259static int hns3_nic_set_real_num_queue(struct net_device *netdev)
260{
9780cb97 261 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 262 struct hnae3_knic_private_info *kinfo = &h->kinfo;
263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
7e114e7d
YL		 264 int i, ret;
265
266 if (kinfo->num_tc <= 1) {
267 netdev_reset_tc(netdev);
268 } else {
269 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
270 if (ret) {
271 netdev_err(netdev,
272 "netdev_set_num_tc fail, ret=%d!\n", ret);
273 return ret;
274 }
275
276 for (i = 0; i < HNAE3_MAX_TC; i++) {
277 if (!kinfo->tc_info[i].enable)
278 continue;
279
280 netdev_set_tc_queue(netdev,
281 kinfo->tc_info[i].tc,
282 kinfo->tc_info[i].tqp_count,
283 kinfo->tc_info[i].tqp_offset);
284 }
285 }
9df8f79a
YL		 286
287 ret = netif_set_real_num_tx_queues(netdev, queue_size);
288 if (ret) {
289 netdev_err(netdev,
290 "netif_set_real_num_tx_queues fail, ret=%d!\n",
291 ret);
292 return ret;
293 }
294
295 ret = netif_set_real_num_rx_queues(netdev, queue_size);
296 if (ret) {
297 netdev_err(netdev,
298 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
299 return ret;
300 }
301
302 return 0;
303}
304
2d7187ce
PL		 305static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
306{
08ca3d58 307 u16 alloc_tqps, max_rss_size, rss_size;
2d7187ce 308
08ca3d58
HT		 309 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
310 rss_size = alloc_tqps / h->kinfo.num_tc;
2d7187ce 311
08ca3d58 312 return min_t(u16, rss_size, max_rss_size);
2d7187ce
PL		 313}
314
2b5251b7
HT		 315static void hns3_tqp_enable(struct hnae3_queue *tqp)
316{
317 u32 rcb_reg;
318
319 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
320 rcb_reg |= BIT(HNS3_RING_EN_B);
321 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
322}
323
324static void hns3_tqp_disable(struct hnae3_queue *tqp)
325{
326 u32 rcb_reg;
327
328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
329 rcb_reg &= ~BIT(HNS3_RING_EN_B);
330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
331}
332
76ad4f0e
S		 333static int hns3_nic_net_up(struct net_device *netdev)
334{
335 struct hns3_nic_priv *priv = netdev_priv(netdev);
336 struct hnae3_handle *h = priv->ae_handle;
337 int i, j;
338 int ret;
339
e32a805a
FL		 340 ret = hns3_nic_reset_all_ring(h);
341 if (ret)
342 return ret;
343
76ad4f0e
S		 344 /* get irq resource for all vectors */
345 ret = hns3_nic_init_irq(priv);
346 if (ret) {
347 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
348 return ret;
349 }
350
351 /* enable the vectors */
352 for (i = 0; i < priv->vector_num; i++)
353 hns3_vector_enable(&priv->tqp_vector[i]);
354
2b5251b7
HT		 355 /* enable rcb */
356 for (j = 0; j < h->kinfo.num_tqps; j++)
357 hns3_tqp_enable(h->kinfo.tqp[j]);
358
76ad4f0e
S		 359 /* start the ae_dev */
360 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
361 if (ret)
362 goto out_start_err;
363
a3083abb
JS		 364 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
365
76ad4f0e
S		 366 return 0;
367
368out_start_err:
2b5251b7
HT		 369 while (j--)
370 hns3_tqp_disable(h->kinfo.tqp[j]);
371
76ad4f0e
S		 372 for (j = i - 1; j >= 0; j--)
373 hns3_vector_disable(&priv->tqp_vector[j]);
374
375 hns3_nic_uninit_irq(priv);
376
377 return ret;
378}
379
380static int hns3_nic_net_open(struct net_device *netdev)
381{
fad0e9d8 382 struct hns3_nic_priv *priv = netdev_priv(netdev);
7e114e7d
YL		 383 struct hnae3_handle *h = hns3_get_handle(netdev);
384 struct hnae3_knic_private_info *kinfo;
385 int i, ret;
76ad4f0e 386
3a11f446
HT		 387 if (hns3_nic_resetting(netdev))
388 return -EBUSY;
389
76ad4f0e
S		 390 netif_carrier_off(netdev);
391
9df8f79a
YL		 392 ret = hns3_nic_set_real_num_queue(netdev);
393 if (ret)
76ad4f0e 394 return ret;
76ad4f0e
S		 395
396 ret = hns3_nic_net_up(netdev);
397 if (ret) {
398 netdev_err(netdev,
399 "hns net up fail, ret=%d!\n", ret);
400 return ret;
401 }
402
7e114e7d
YL		 403 kinfo = &h->kinfo;
404 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
405 netdev_set_prio_tc_map(netdev, i,
406 kinfo->prio_tc[i]);
407 }
408
fad0e9d8
JS		 409 if (h->ae_algo->ops->set_timer_task)
410 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
411
76ad4f0e
S		 412 return 0;
413}
414
415static void hns3_nic_net_down(struct net_device *netdev)
416{
417 struct hns3_nic_priv *priv = netdev_priv(netdev);
2b5251b7 418 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 419 const struct hnae3_ae_ops *ops;
420 int i;
421
e32a805a
FL		 422 /* disable vectors */
423 for (i = 0; i < priv->vector_num; i++)
424 hns3_vector_disable(&priv->tqp_vector[i]);
425
2b5251b7
HT		 426 /* disable rcb */
427 for (i = 0; i < h->kinfo.num_tqps; i++)
428 hns3_tqp_disable(h->kinfo.tqp[i]);
429
76ad4f0e
S		 430 /* stop ae_dev */
431 ops = priv->ae_handle->ae_algo->ops;
432 if (ops->stop)
433 ops->stop(priv->ae_handle);
434
76ad4f0e
S		 435 /* free irq resources */
436 hns3_nic_uninit_irq(priv);
e32a805a
FL		 437
438 hns3_clear_all_ring(priv->ae_handle);
76ad4f0e
S		 439}
440
441static int hns3_nic_net_stop(struct net_device *netdev)
442{
f22463fd 443 struct hns3_nic_priv *priv = netdev_priv(netdev);
fad0e9d8 444 struct hnae3_handle *h = hns3_get_handle(netdev);
f22463fd
HT		 445
446 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
447 return 0;
448
fad0e9d8
JS		 449 if (h->ae_algo->ops->set_timer_task)
450 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
451
76ad4f0e
S		 452 netif_tx_stop_all_queues(netdev);
453 netif_carrier_off(netdev);
454
455 hns3_nic_net_down(netdev);
456
457 return 0;
458}
459
76ad4f0e
S		 460static int hns3_nic_uc_sync(struct net_device *netdev,
461 const unsigned char *addr)
462{
9780cb97 463 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 464
465 if (h->ae_algo->ops->add_uc_addr)
466 return h->ae_algo->ops->add_uc_addr(h, addr);
467
468 return 0;
469}
470
471static int hns3_nic_uc_unsync(struct net_device *netdev,
472 const unsigned char *addr)
473{
9780cb97 474 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 475
476 if (h->ae_algo->ops->rm_uc_addr)
477 return h->ae_algo->ops->rm_uc_addr(h, addr);
478
479 return 0;
480}
481
482static int hns3_nic_mc_sync(struct net_device *netdev,
483 const unsigned char *addr)
484{
9780cb97 485 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 486
720a8478 487 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 488 return h->ae_algo->ops->add_mc_addr(h, addr);
489
490 return 0;
491}
492
493static int hns3_nic_mc_unsync(struct net_device *netdev,
494 const unsigned char *addr)
495{
9780cb97 496 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 497
720a8478 498 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 499 return h->ae_algo->ops->rm_mc_addr(h, addr);
500
501 return 0;
502}
503
1e3653db
JS		 504static u8 hns3_get_netdev_flags(struct net_device *netdev)
505{
506 u8 flags = 0;
507
508 if (netdev->flags & IFF_PROMISC) {
509 flags = HNAE3_USER_UPE | HNAE3_USER_MPE;
510 } else {
511 flags |= HNAE3_VLAN_FLTR;
512 if (netdev->flags & IFF_ALLMULTI)
513 flags |= HNAE3_USER_MPE;
514 }
515
516 return flags;
517}
518
1db9b1bf 519static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 520{
9780cb97 521 struct hnae3_handle *h = hns3_get_handle(netdev);
1e3653db
JS		 522 u8 new_flags;
523 int ret;
76ad4f0e 524
1e3653db
JS		 525 new_flags = hns3_get_netdev_flags(netdev);
526
527 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
528 if (ret) {
76ad4f0e 529 netdev_err(netdev, "sync uc address fail\n");
1e3653db
JS		 530 if (ret == -ENOSPC)
531 new_flags |= HNAE3_OVERFLOW_UPE;
532 }
533
a832d8b5 534 if (netdev->flags & IFF_MULTICAST) {
1e3653db
JS		 535 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
536 hns3_nic_mc_unsync);
537 if (ret) {
76ad4f0e 538 netdev_err(netdev, "sync mc address fail\n");
1e3653db
JS		 539 if (ret == -ENOSPC)
540 new_flags |= HNAE3_OVERFLOW_MPE;
541 }
542 }
543
544 hns3_update_promisc_mode(netdev, new_flags);
545 /* User mode Promisc mode enable and vlan filtering is disabled to
546 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
547 * vlan fitering is enabled
548 */
549 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
550 h->netdev_flags = new_flags;
551}
552
abe62a63 553int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
1e3653db
JS		 554{
555 struct hns3_nic_priv *priv = netdev_priv(netdev);
556 struct hnae3_handle *h = priv->ae_handle;
557
558 if (h->ae_algo->ops->set_promisc_mode) {
abe62a63
HT		 559 return h->ae_algo->ops->set_promisc_mode(h,
560 promisc_flags & HNAE3_UPE,
561 promisc_flags & HNAE3_MPE);
1e3653db 562 }
abe62a63
HT		 563
564 return 0;
1e3653db
JS		 565}
566
567void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
568{
569 struct hns3_nic_priv *priv = netdev_priv(netdev);
570 struct hnae3_handle *h = priv->ae_handle;
571 bool last_state;
572
573 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
574 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
575 if (enable != last_state) {
576 netdev_info(netdev,
577 "%s vlan filter\n",
578 enable ? "enable" : "disable");
579 h->ae_algo->ops->enable_vlan_filter(h, enable);
580 }
a832d8b5 581 }
76ad4f0e
S		 582}
583
584static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
585 u16 *mss, u32 *type_cs_vlan_tso)
586{
587 u32 l4_offset, hdr_len;
588 union l3_hdr_info l3;
589 union l4_hdr_info l4;
590 u32 l4_paylen;
591 int ret;
592
593 if (!skb_is_gso(skb))
594 return 0;
595
596 ret = skb_cow_head(skb, 0);
597 if (ret)
598 return ret;
599
600 l3.hdr = skb_network_header(skb);
601 l4.hdr = skb_transport_header(skb);
602
603 /* Software should clear the IPv4's checksum field when tso is
604 * needed.
605 */
606 if (l3.v4->version == 4)
607 l3.v4->check = 0;
608
609 /* tunnel packet.*/
610 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
611 SKB_GSO_GRE_CSUM |
612 SKB_GSO_UDP_TUNNEL |
613 SKB_GSO_UDP_TUNNEL_CSUM)) {
614 if ((!(skb_shinfo(skb)->gso_type &
615 SKB_GSO_PARTIAL)) &&
616 (skb_shinfo(skb)->gso_type &
617 SKB_GSO_UDP_TUNNEL_CSUM)) {
618 /* Software should clear the udp's checksum
619 * field when tso is needed.
620 */
621 l4.udp->check = 0;
622 }
623 /* reset l3&l4 pointers from outer to inner headers */
624 l3.hdr = skb_inner_network_header(skb);
625 l4.hdr = skb_inner_transport_header(skb);
626
627 /* Software should clear the IPv4's checksum field when
628 * tso is needed.
629 */
630 if (l3.v4->version == 4)
631 l3.v4->check = 0;
632 }
633
634 /* normal or tunnel packet*/
635 l4_offset = l4.hdr - skb->data;
636 hdr_len = (l4.tcp->doff * 4) + l4_offset;
637
638 /* remove payload length from inner pseudo checksum when tso*/
639 l4_paylen = skb->len - l4_offset;
640 csum_replace_by_diff(&l4.tcp->check,
641 (__force __wsum)htonl(l4_paylen));
642
643 /* find the txbd field values */
644 *paylen = skb->len - hdr_len;
ccc23ef3
PL		 645 hnae3_set_bit(*type_cs_vlan_tso,
646 HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 647
648 /* get MSS for TSO */
649 *mss = skb_shinfo(skb)->gso_size;
650
651 return 0;
652}
653
1898d4e4
S		 654static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
655 u8 *il4_proto)
76ad4f0e
S		 656{
657 union {
658 struct iphdr *v4;
659 struct ipv6hdr *v6;
660 unsigned char *hdr;
661 } l3;
662 unsigned char *l4_hdr;
663 unsigned char *exthdr;
664 u8 l4_proto_tmp;
665 __be16 frag_off;
666
667 /* find outer header point */
668 l3.hdr = skb_network_header(skb);
c82a5497 669 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 670
671 if (skb->protocol == htons(ETH_P_IPV6)) {
672 exthdr = l3.hdr + sizeof(*l3.v6);
673 l4_proto_tmp = l3.v6->nexthdr;
674 if (l4_hdr != exthdr)
675 ipv6_skip_exthdr(skb, exthdr - skb->data,
676 &l4_proto_tmp, &frag_off);
677 } else if (skb->protocol == htons(ETH_P_IP)) {
678 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 679 } else {
680 return -EINVAL;
76ad4f0e
S		 681 }
682
683 *ol4_proto = l4_proto_tmp;
684
685 /* tunnel packet */
686 if (!skb->encapsulation) {
687 *il4_proto = 0;
1898d4e4 688 return 0;
76ad4f0e
S		 689 }
690
691 /* find inner header point */
692 l3.hdr = skb_inner_network_header(skb);
693 l4_hdr = skb_inner_transport_header(skb);
694
695 if (l3.v6->version == 6) {
696 exthdr = l3.hdr + sizeof(*l3.v6);
697 l4_proto_tmp = l3.v6->nexthdr;
698 if (l4_hdr != exthdr)
699 ipv6_skip_exthdr(skb, exthdr - skb->data,
700 &l4_proto_tmp, &frag_off);
701 } else if (l3.v4->version == 4) {
702 l4_proto_tmp = l3.v4->protocol;
703 }
704
705 *il4_proto = l4_proto_tmp;
1898d4e4
S		 706
707 return 0;
76ad4f0e
S		 708}
709
710static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
711 u8 il4_proto, u32 *type_cs_vlan_tso,
712 u32 *ol_type_vlan_len_msec)
713{
714 union {
715 struct iphdr *v4;
716 struct ipv6hdr *v6;
717 unsigned char *hdr;
718 } l3;
719 union {
720 struct tcphdr *tcp;
721 struct udphdr *udp;
722 struct gre_base_hdr *gre;
723 unsigned char *hdr;
724 } l4;
725 unsigned char *l2_hdr;
726 u8 l4_proto = ol4_proto;
727 u32 ol2_len;
728 u32 ol3_len;
729 u32 ol4_len;
730 u32 l2_len;
731 u32 l3_len;
732
733 l3.hdr = skb_network_header(skb);
734 l4.hdr = skb_transport_header(skb);
735
736 /* compute L2 header size for normal packet, defined in 2 Bytes */
737 l2_len = l3.hdr - skb->data;
ccc23ef3
PL		 738 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
739 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 740
741 /* tunnel packet*/
742 if (skb->encapsulation) {
743 /* compute OL2 header size, defined in 2 Bytes */
744 ol2_len = l2_len;
ccc23ef3
PL		 745 hnae3_set_field(*ol_type_vlan_len_msec,
746 HNS3_TXD_L2LEN_M,
747 HNS3_TXD_L2LEN_S, ol2_len >> 1);
76ad4f0e
S		 748
749 /* compute OL3 header size, defined in 4 Bytes */
750 ol3_len = l4.hdr - l3.hdr;
ccc23ef3
PL		 751 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
752 HNS3_TXD_L3LEN_S, ol3_len >> 2);
76ad4f0e
S		 753
754 /* MAC in UDP, MAC in GRE (0x6558)*/
755 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
756 /* switch MAC header ptr from outer to inner header.*/
757 l2_hdr = skb_inner_mac_header(skb);
758
759 /* compute OL4 header size, defined in 4 Bytes. */
760 ol4_len = l2_hdr - l4.hdr;
ccc23ef3
PL		 761 hnae3_set_field(*ol_type_vlan_len_msec,
762 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
763 ol4_len >> 2);
76ad4f0e
S		 764
765 /* switch IP header ptr from outer to inner header */
766 l3.hdr = skb_inner_network_header(skb);
767
768 /* compute inner l2 header size, defined in 2 Bytes. */
769 l2_len = l3.hdr - l2_hdr;
ccc23ef3
PL		 770 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
771 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 772 } else {
773 /* skb packet types not supported by hardware,
774 * txbd len fild doesn't be filled.
775 */
776 return;
777 }
778
779 /* switch L4 header pointer from outer to inner */
780 l4.hdr = skb_inner_transport_header(skb);
781
782 l4_proto = il4_proto;
783 }
784
785 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
786 l3_len = l4.hdr - l3.hdr;
ccc23ef3
PL		 787 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
788 HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e
S		 789
790 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
791 switch (l4_proto) {
792 case IPPROTO_TCP:
ccc23ef3
PL		 793 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
794 HNS3_TXD_L4LEN_S, l4.tcp->doff);
76ad4f0e
S		 795 break;
796 case IPPROTO_SCTP:
ccc23ef3
PL		 797 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
798 HNS3_TXD_L4LEN_S,
799 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 800 break;
801 case IPPROTO_UDP:
ccc23ef3
PL		 802 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
803 HNS3_TXD_L4LEN_S,
804 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 805 break;
806 default:
807 /* skb packet types not supported by hardware,
808 * txbd len fild doesn't be filled.
809 */
810 return;
811 }
812}
813
cfdd6e86
YL		 814/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
815 * and it is udp packet, which has a dest port as the IANA assigned.
816 * the hardware is expected to do the checksum offload, but the
817 * hardware will not do the checksum offload when udp dest port is
818 * 4789.
819 */
820static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
821{
822#define IANA_VXLAN_PORT 4789
823 union {
824 struct tcphdr *tcp;
825 struct udphdr *udp;
826 struct gre_base_hdr *gre;
827 unsigned char *hdr;
828 } l4;
829
830 l4.hdr = skb_transport_header(skb);
831
832 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
833 return false;
834
835 skb_checksum_help(skb);
836
837 return true;
838}
839
76ad4f0e
S		 840static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
841 u8 il4_proto, u32 *type_cs_vlan_tso,
842 u32 *ol_type_vlan_len_msec)
843{
844 union {
845 struct iphdr *v4;
846 struct ipv6hdr *v6;
847 unsigned char *hdr;
848 } l3;
849 u32 l4_proto = ol4_proto;
850
851 l3.hdr = skb_network_header(skb);
852
853 /* define OL3 type and tunnel type(OL4).*/
854 if (skb->encapsulation) {
855 /* define outer network header type.*/
856 if (skb->protocol == htons(ETH_P_IP)) {
857 if (skb_is_gso(skb))
ccc23ef3
PL		 858 hnae3_set_field(*ol_type_vlan_len_msec,
859 HNS3_TXD_OL3T_M,
860 HNS3_TXD_OL3T_S,
861 HNS3_OL3T_IPV4_CSUM);
76ad4f0e 862 else
ccc23ef3
PL		 863 hnae3_set_field(*ol_type_vlan_len_msec,
864 HNS3_TXD_OL3T_M,
865 HNS3_TXD_OL3T_S,
866 HNS3_OL3T_IPV4_NO_CSUM);
76ad4f0e
S		 867
868 } else if (skb->protocol == htons(ETH_P_IPV6)) {
ccc23ef3
PL		 869 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
870 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
76ad4f0e
S		 871 }
872
873 /* define tunnel type(OL4).*/
874 switch (l4_proto) {
875 case IPPROTO_UDP:
ccc23ef3
PL		 876 hnae3_set_field(*ol_type_vlan_len_msec,
877 HNS3_TXD_TUNTYPE_M,
878 HNS3_TXD_TUNTYPE_S,
879 HNS3_TUN_MAC_IN_UDP);
76ad4f0e
S		 880 break;
881 case IPPROTO_GRE:
ccc23ef3
PL		 882 hnae3_set_field(*ol_type_vlan_len_msec,
883 HNS3_TXD_TUNTYPE_M,
884 HNS3_TXD_TUNTYPE_S,
885 HNS3_TUN_NVGRE);
76ad4f0e
S		 886 break;
887 default:
888 /* drop the skb tunnel packet if hardware don't support,
889 * because hardware can't calculate csum when TSO.
890 */
891 if (skb_is_gso(skb))
892 return -EDOM;
893
894 /* the stack computes the IP header already,
895 * driver calculate l4 checksum when not TSO.
896 */
897 skb_checksum_help(skb);
898 return 0;
899 }
900
901 l3.hdr = skb_inner_network_header(skb);
902 l4_proto = il4_proto;
903 }
904
905 if (l3.v4->version == 4) {
ccc23ef3
PL		 906 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
907 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
76ad4f0e
S		 908
909 /* the stack computes the IP header already, the only time we
910 * need the hardware to recompute it is in the case of TSO.
911 */
912 if (skb_is_gso(skb))
ccc23ef3 913 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 914 } else if (l3.v6->version == 6) {
ccc23ef3
PL		 915 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
916 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
76ad4f0e
S		 917 }
918
919 switch (l4_proto) {
920 case IPPROTO_TCP:
79fa1b6a 921 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 922 hnae3_set_field(*type_cs_vlan_tso,
923 HNS3_TXD_L4T_M,
924 HNS3_TXD_L4T_S,
925 HNS3_L4T_TCP);
76ad4f0e
S		 926 break;
927 case IPPROTO_UDP:
cfdd6e86
YL		 928 if (hns3_tunnel_csum_bug(skb))
929 break;
930
79fa1b6a 931 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 932 hnae3_set_field(*type_cs_vlan_tso,
933 HNS3_TXD_L4T_M,
934 HNS3_TXD_L4T_S,
935 HNS3_L4T_UDP);
76ad4f0e
S		 936 break;
937 case IPPROTO_SCTP:
79fa1b6a 938 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 939 hnae3_set_field(*type_cs_vlan_tso,
940 HNS3_TXD_L4T_M,
941 HNS3_TXD_L4T_S,
942 HNS3_L4T_SCTP);
76ad4f0e
S		 943 break;
944 default:
945 /* drop the skb tunnel packet if hardware don't support,
946 * because hardware can't calculate csum when TSO.
947 */
948 if (skb_is_gso(skb))
949 return -EDOM;
950
951 /* the stack computes the IP header already,
952 * driver calculate l4 checksum when not TSO.
953 */
954 skb_checksum_help(skb);
955 return 0;
956 }
957
958 return 0;
959}
960
961static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
962{
963 /* Config bd buffer end */
ccc23ef3
PL		 964 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
965 HNS3_TXD_BDTYPE_S, 0);
966 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
967 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
968 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
76ad4f0e
S		 969}
970
1fdd8dc5
PL		 971static int hns3_fill_desc_vtags(struct sk_buff *skb,
972 struct hns3_enet_ring *tx_ring,
973 u32 *inner_vlan_flag,
974 u32 *out_vlan_flag,
975 u16 *inner_vtag,
976 u16 *out_vtag)
977{
978#define HNS3_TX_VLAN_PRIO_SHIFT 13
979
980 if (skb->protocol == htons(ETH_P_8021Q) &&
981 !(tx_ring->tqp->handle->kinfo.netdev->features &
982 NETIF_F_HW_VLAN_CTAG_TX)) {
983 /* When HW VLAN acceleration is turned off, and the stack
984 * sets the protocol to 802.1q, the driver just need to
985 * set the protocol to the encapsulated ethertype.
986 */
987 skb->protocol = vlan_get_protocol(skb);
988 return 0;
989 }
990
991 if (skb_vlan_tag_present(skb)) {
992 u16 vlan_tag;
993
994 vlan_tag = skb_vlan_tag_get(skb);
995 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
996
997 /* Based on hw strategy, use out_vtag in two layer tag case,
998 * and use inner_vtag in one tag case.
999 */
1000 if (skb->protocol == htons(ETH_P_8021Q)) {
ccc23ef3 1001 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
1fdd8dc5
PL		 1002 *out_vtag = vlan_tag;
1003 } else {
ccc23ef3 1004 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
1fdd8dc5
PL		 1005 *inner_vtag = vlan_tag;
1006 }
1007 } else if (skb->protocol == htons(ETH_P_8021Q)) {
1008 struct vlan_ethhdr *vhdr;
1009 int rc;
1010
1011 rc = skb_cow_head(skb, 0);
1012 if (rc < 0)
1013 return rc;
1014 vhdr = (struct vlan_ethhdr *)skb->data;
1015 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1016 << HNS3_TX_VLAN_PRIO_SHIFT);
1017 }
1018
1019 skb->protocol = vlan_get_protocol(skb);
1020 return 0;
1021}
1022
76ad4f0e 1023static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
91040825 1024 int size, int frag_end, enum hns_desc_type type)
76ad4f0e
S		 1025{
1026 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1027 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
91040825 1028 struct device *dev = ring_to_dev(ring);
76ad4f0e
S		 1029 u32 ol_type_vlan_len_msec = 0;
1030 u16 bdtp_fe_sc_vld_ra_ri = 0;
91040825 1031 struct skb_frag_struct *frag;
13491411 1032 unsigned int frag_buf_num;
76ad4f0e
S		 1033 u32 type_cs_vlan_tso = 0;
1034 struct sk_buff *skb;
1fdd8dc5
PL		 1035 u16 inner_vtag = 0;
1036 u16 out_vtag = 0;
13491411
FL		 1037 unsigned int k;
1038 int sizeoflast;
76ad4f0e 1039 u32 paylen = 0;
91040825 1040 dma_addr_t dma;
76ad4f0e 1041 u16 mss = 0;
76ad4f0e
S		 1042 u8 ol4_proto;
1043 u8 il4_proto;
1044 int ret;
1045
76ad4f0e
S		 1046 if (type == DESC_TYPE_SKB) {
1047 skb = (struct sk_buff *)priv;
a90bb9a5 1048 paylen = skb->len;
76ad4f0e 1049
1fdd8dc5
PL		 1050 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1051 &ol_type_vlan_len_msec,
1052 &inner_vtag, &out_vtag);
1053 if (unlikely(ret))
1054 return ret;
1055
76ad4f0e
S		 1056 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1057 skb_reset_mac_len(skb);
76ad4f0e 1058
1898d4e4
S		 1059 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1060 if (ret)
1061 return ret;
76ad4f0e
S		 1062 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
1063 &type_cs_vlan_tso,
1064 &ol_type_vlan_len_msec);
1065 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
1066 &type_cs_vlan_tso,
1067 &ol_type_vlan_len_msec);
1068 if (ret)
1069 return ret;
1070
1071 ret = hns3_set_tso(skb, &paylen, &mss,
1072 &type_cs_vlan_tso);
1073 if (ret)
1074 return ret;
1075 }
1076
1077 /* Set txbd */
1078 desc->tx.ol_type_vlan_len_msec =
1079 cpu_to_le32(ol_type_vlan_len_msec);
1080 desc->tx.type_cs_vlan_tso_len =
1081 cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 1082 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 1083 desc->tx.mss = cpu_to_le16(mss);
1fdd8dc5
PL		 1084 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1085 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
91040825
PL		 1086
1087 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1088 } else {
1089 frag = (struct skb_frag_struct *)priv;
1090 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1091 }
1092
1093 if (dma_mapping_error(ring->dev, dma)) {
1094 ring->stats.sw_err_cnt++;
1095 return -ENOMEM;
76ad4f0e
S		 1096 }
1097
6a3bff0d
FL		 1098 desc_cb->length = size;
1099
13491411
FL		 1100 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1101 sizeoflast = size % HNS3_MAX_BD_SIZE;
1102 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1103
1104 /* When frag size is bigger than hardware limit, split this frag */
1105 for (k = 0; k < frag_buf_num; k++) {
1106 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1107 desc_cb->priv = priv;
13491411
FL		 1108 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1109 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1110 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1111
1112 /* now, fill the descriptor */
1113 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
6a3bff0d
FL		 1114 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1115 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
13491411
FL		 1116 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1117 frag_end && (k == frag_buf_num - 1) ?
1118 1 : 0);
1119 desc->tx.bdtp_fe_sc_vld_ra_ri =
1120 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1121
1122 /* move ring pointer to next.*/
1123 ring_ptr_move_fw(ring, next_to_use);
1124
1125 desc_cb = &ring->desc_cb[ring->next_to_use];
1126 desc = &ring->desc[ring->next_to_use];
1127 }
76ad4f0e
S		 1128
1129 return 0;
1130}
1131
76ad4f0e
S		 1132static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1133 struct hns3_enet_ring *ring)
1134{
1135 struct sk_buff *skb = *out_skb;
1136 struct skb_frag_struct *frag;
1137 int bdnum_for_frag;
1138 int frag_num;
1139 int buf_num;
1140 int size;
1141 int i;
1142
1143 size = skb_headlen(skb);
1144 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1145
1146 frag_num = skb_shinfo(skb)->nr_frags;
1147 for (i = 0; i < frag_num; i++) {
1148 frag = &skb_shinfo(skb)->frags[i];
1149 size = skb_frag_size(frag);
1150 bdnum_for_frag =
1151 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1152 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1153 return -ENOMEM;
1154
1155 buf_num += bdnum_for_frag;
1156 }
1157
1158 if (buf_num > ring_space(ring))
1159 return -EBUSY;
1160
1161 *bnum = buf_num;
1162 return 0;
1163}
1164
1165static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1166 struct hns3_enet_ring *ring)
1167{
1168 struct sk_buff *skb = *out_skb;
1169 int buf_num;
1170
1171 /* No. of segments (plus a header) */
1172 buf_num = skb_shinfo(skb)->nr_frags + 1;
1173
91a2f02f 1174 if (unlikely(ring_space(ring) < buf_num))
76ad4f0e
S		 1175 return -EBUSY;
1176
1177 *bnum = buf_num;
1178
1179 return 0;
1180}
1181
fc09d03d 1182static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1183{
1184 struct device *dev = ring_to_dev(ring);
1185 unsigned int i;
1186
1187 for (i = 0; i < ring->desc_num; i++) {
1188 /* check if this is where we started */
1189 if (ring->next_to_use == next_to_use_orig)
1190 break;
1191
1192 /* unmap the descriptor dma address */
1193 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1194 dma_unmap_single(dev,
1195 ring->desc_cb[ring->next_to_use].dma,
1196 ring->desc_cb[ring->next_to_use].length,
1197 DMA_TO_DEVICE);
6a3bff0d 1198 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1199 dma_unmap_page(dev,
1200 ring->desc_cb[ring->next_to_use].dma,
1201 ring->desc_cb[ring->next_to_use].length,
1202 DMA_TO_DEVICE);
1203
6a3bff0d
FL		 1204 ring->desc_cb[ring->next_to_use].length = 0;
1205
76ad4f0e
S		 1206 /* rollback one */
1207 ring_ptr_move_bw(ring, next_to_use);
1208 }
1209}
1210
d43e5aca 1211netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1212{
1213 struct hns3_nic_priv *priv = netdev_priv(netdev);
1214 struct hns3_nic_ring_data *ring_data =
1215 &tx_ring_data(priv, skb->queue_mapping);
1216 struct hns3_enet_ring *ring = ring_data->ring;
76ad4f0e
S		 1217 struct netdev_queue *dev_queue;
1218 struct skb_frag_struct *frag;
1219 int next_to_use_head;
1220 int next_to_use_frag;
76ad4f0e
S		 1221 int buf_num;
1222 int seg_num;
1223 int size;
1224 int ret;
1225 int i;
1226
1227 /* Prefetch the data used later */
1228 prefetch(skb->data);
1229
1230 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1231 case -EBUSY:
1232 u64_stats_update_begin(&ring->syncp);
1233 ring->stats.tx_busy++;
1234 u64_stats_update_end(&ring->syncp);
1235
1236 goto out_net_tx_busy;
1237 case -ENOMEM:
1238 u64_stats_update_begin(&ring->syncp);
1239 ring->stats.sw_err_cnt++;
1240 u64_stats_update_end(&ring->syncp);
1241 netdev_err(netdev, "no memory to xmit!\n");
1242
1243 goto out_err_tx_ok;
1244 default:
1245 break;
1246 }
1247
1248 /* No. of segments (plus a header) */
1249 seg_num = skb_shinfo(skb)->nr_frags + 1;
1250 /* Fill the first part */
1251 size = skb_headlen(skb);
1252
1253 next_to_use_head = ring->next_to_use;
1254
91040825
PL		 1255 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1256 DESC_TYPE_SKB);
76ad4f0e 1257 if (ret)
fc09d03d 1258 goto head_fill_err;
76ad4f0e
S		 1259
1260 next_to_use_frag = ring->next_to_use;
1261 /* Fill the fragments */
1262 for (i = 1; i < seg_num; i++) {
1263 frag = &skb_shinfo(skb)->frags[i - 1];
1264 size = skb_frag_size(frag);
91040825
PL		 1265
1266 ret = priv->ops.fill_desc(ring, frag, size,
1267 seg_num - 1 == i ? 1 : 0,
1268 DESC_TYPE_PAGE);
76ad4f0e
S		 1269
1270 if (ret)
fc09d03d 1271 goto frag_fill_err;
76ad4f0e
S		 1272 }
1273
1274 /* Complete translate all packets */
1275 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1276 netdev_tx_sent_queue(dev_queue, skb->len);
1277
1278 wmb(); /* Commit all data before submit */
1279
ccc23ef3 1280 hnae3_queue_xmit(ring->tqp, buf_num);
76ad4f0e
S		 1281
1282 return NETDEV_TX_OK;
1283
fc09d03d
FL		 1284frag_fill_err:
1285 hns3_clear_desc(ring, next_to_use_frag);
76ad4f0e 1286
fc09d03d
FL		 1287head_fill_err:
1288 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1289
1290out_err_tx_ok:
1291 dev_kfree_skb_any(skb);
1292 return NETDEV_TX_OK;
1293
1294out_net_tx_busy:
1295 netif_stop_subqueue(netdev, ring_data->queue_index);
1296 smp_mb(); /* Commit all data before submit */
1297
1298 return NETDEV_TX_BUSY;
1299}
1300
1301static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1302{
9780cb97 1303 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1304 struct sockaddr *mac_addr = p;
1305 int ret;
1306
1307 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1308 return -EADDRNOTAVAIL;
1309
f37fc980
JS		 1310 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1311 netdev_info(netdev, "already using mac address %pM\n",
1312 mac_addr->sa_data);
1313 return 0;
1314 }
1315
3cbf5e2d 1316 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1317 if (ret) {
1318 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1319 return ret;
1320 }
1321
1322 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1323
1324 return 0;
1325}
1326
a185d723
XW		 1327static int hns3_nic_do_ioctl(struct net_device *netdev,
1328 struct ifreq *ifr, int cmd)
1329{
1330 struct hnae3_handle *h = hns3_get_handle(netdev);
1331
1332 if (!netif_running(netdev))
1333 return -EINVAL;
1334
1335 if (!h->ae_algo->ops->do_ioctl)
1336 return -EOPNOTSUPP;
1337
1338 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1339}
1340
76ad4f0e
S		 1341static int hns3_nic_set_features(struct net_device *netdev,
1342 netdev_features_t features)
1343{
21b6fd34 1344 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1345 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f9a7732 1346 struct hnae3_handle *h = priv->ae_handle;
5f9a7732 1347 int ret;
76ad4f0e 1348
21b6fd34 1349 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
e4c38d6e 1350 if (features & (NETIF_F_TSO | NETIF_F_TSO6))
21b6fd34 1351 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
e4c38d6e 1352 else
21b6fd34 1353 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
76ad4f0e
S		 1354 }
1355
88576b4b
JS		 1356 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1357 h->ae_algo->ops->enable_vlan_filter) {
21b6fd34
JS		 1358 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1359 h->ae_algo->ops->enable_vlan_filter(h, true);
1360 else
1361 h->ae_algo->ops->enable_vlan_filter(h, false);
1362 }
d818396d 1363
88576b4b
JS		 1364 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1365 h->ae_algo->ops->enable_hw_strip_rxvtag) {
5f9a7732
PL		 1366 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1367 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1368 else
1369 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1370
1371 if (ret)
1372 return ret;
1373 }
1374
d1f04a80
JS		 1375 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1376 if (features & NETIF_F_NTUPLE)
1377 h->ae_algo->ops->enable_fd(h, true);
1378 else
1379 h->ae_algo->ops->enable_fd(h, false);
1380 }
1381
76ad4f0e
S		 1382 netdev->features = features;
1383 return 0;
1384}
1385
9596f6f0
PL		 1386static void hns3_nic_get_stats64(struct net_device *netdev,
1387 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1388{
1389 struct hns3_nic_priv *priv = netdev_priv(netdev);
1390 int queue_num = priv->ae_handle->kinfo.num_tqps;
7a5d2a39 1391 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e
S		 1392 struct hns3_enet_ring *ring;
1393 unsigned int start;
1394 unsigned int idx;
1395 u64 tx_bytes = 0;
1396 u64 rx_bytes = 0;
1397 u64 tx_pkts = 0;
1398 u64 rx_pkts = 0;
0a83231f
JS		 1399 u64 tx_drop = 0;
1400 u64 rx_drop = 0;
76ad4f0e 1401
a3083abb
JS		 1402 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1403 return;
1404
7a5d2a39
JS		 1405 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1406
76ad4f0e
S		 1407 for (idx = 0; idx < queue_num; idx++) {
1408 /* fetch the tx stats */
1409 ring = priv->ring_data[idx].ring;
1410 do {
d36d36ce 1411 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1412 tx_bytes += ring->stats.tx_bytes;
1413 tx_pkts += ring->stats.tx_pkts;
0a83231f
JS		 1414 tx_drop += ring->stats.tx_busy;
1415 tx_drop += ring->stats.sw_err_cnt;
76ad4f0e
S		 1416 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1417
1418 /* fetch the rx stats */
1419 ring = priv->ring_data[idx + queue_num].ring;
1420 do {
d36d36ce 1421 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1422 rx_bytes += ring->stats.rx_bytes;
1423 rx_pkts += ring->stats.rx_pkts;
0a83231f
JS		 1424 rx_drop += ring->stats.non_vld_descs;
1425 rx_drop += ring->stats.err_pkt_len;
1426 rx_drop += ring->stats.l2_err;
76ad4f0e
S		 1427 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1428 }
1429
1430 stats->tx_bytes = tx_bytes;
1431 stats->tx_packets = tx_pkts;
1432 stats->rx_bytes = rx_bytes;
1433 stats->rx_packets = rx_pkts;
1434
1435 stats->rx_errors = netdev->stats.rx_errors;
1436 stats->multicast = netdev->stats.multicast;
1437 stats->rx_length_errors = netdev->stats.rx_length_errors;
1438 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
1439 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1440
1441 stats->tx_errors = netdev->stats.tx_errors;
0a83231f
JS		 1442 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
1443 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
76ad4f0e
S		 1444 stats->collisions = netdev->stats.collisions;
1445 stats->rx_over_errors = netdev->stats.rx_over_errors;
1446 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1447 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1448 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1449 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1450 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1451 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1452 stats->tx_window_errors = netdev->stats.tx_window_errors;
1453 stats->rx_compressed = netdev->stats.rx_compressed;
1454 stats->tx_compressed = netdev->stats.tx_compressed;
1455}
1456
30d240df 1457static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1458{
30d240df 1459 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
9780cb97 1460 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 1461 struct hnae3_knic_private_info *kinfo = &h->kinfo;
30d240df
YL		 1462 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1463 u8 tc = mqprio_qopt->qopt.num_tc;
1464 u16 mode = mqprio_qopt->mode;
1465 u8 hw = mqprio_qopt->qopt.hw;
1466 bool if_running;
76ad4f0e
S		 1467 int ret;
1468
30d240df
YL		 1469 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1470 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1471 return -EOPNOTSUPP;
1472
76ad4f0e
S		 1473 if (tc > HNAE3_MAX_TC)
1474 return -EINVAL;
1475
76ad4f0e
S		 1476 if (!netdev)
1477 return -EINVAL;
1478
30d240df
YL		 1479 if_running = netif_running(netdev);
1480 if (if_running) {
1481 hns3_nic_net_stop(netdev);
1482 msleep(100);
76ad4f0e
S		 1483 }
1484
30d240df
YL		 1485 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1486 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e 1487 if (ret)
30d240df
YL		 1488 goto out;
1489
30d240df
YL		 1490 ret = hns3_nic_set_real_num_queue(netdev);
1491
1492out:
1493 if (if_running)
1494 hns3_nic_net_open(netdev);
1495
1496 return ret;
76ad4f0e
S		 1497}
1498
2572ac53 1499static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1500 void *type_data)
76ad4f0e 1501{
575ed7d3 1502 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1503 return -EOPNOTSUPP;
76ad4f0e 1504
30d240df 1505 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1506}
1507
1508static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1509 __be16 proto, u16 vid)
1510{
9780cb97 1511 struct hnae3_handle *h = hns3_get_handle(netdev);
103ce052 1512 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1513 int ret = -EIO;
1514
1515 if (h->ae_algo->ops->set_vlan_filter)
1516 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1517
103ce052
YL		 1518 if (!ret)
1519 set_bit(vid, priv->active_vlans);
1520
76ad4f0e
S		 1521 return ret;
1522}
1523
1524static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1525 __be16 proto, u16 vid)
1526{
9780cb97 1527 struct hnae3_handle *h = hns3_get_handle(netdev);
103ce052 1528 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1529 int ret = -EIO;
1530
1531 if (h->ae_algo->ops->set_vlan_filter)
1532 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1533
103ce052
YL		 1534 if (!ret)
1535 clear_bit(vid, priv->active_vlans);
1536
76ad4f0e
S		 1537 return ret;
1538}
1539
abe62a63 1540static int hns3_restore_vlan(struct net_device *netdev)
103ce052
YL		 1541{
1542 struct hns3_nic_priv *priv = netdev_priv(netdev);
abe62a63 1543 int ret = 0;
103ce052 1544 u16 vid;
103ce052
YL		 1545
1546 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1547 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
abe62a63
HT		 1548 if (ret) {
1549 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n",
1550 vid, ret);
1551 return ret;
1552 }
103ce052 1553 }
abe62a63
HT		 1554
1555 return ret;
103ce052
YL		 1556}
1557
76ad4f0e
S		 1558static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1559 u8 qos, __be16 vlan_proto)
1560{
9780cb97 1561 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1562 int ret = -EIO;
1563
1564 if (h->ae_algo->ops->set_vf_vlan_filter)
1565 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1566 qos, vlan_proto);
1567
1568 return ret;
1569}
1570
a8e8b7ff
S		 1571static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1572{
9780cb97 1573 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1574 int ret;
1575
1576 if (!h->ae_algo->ops->set_mtu)
1577 return -EOPNOTSUPP;
1578
a8e8b7ff 1579 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
6a2953dd 1580 if (ret)
a8e8b7ff
S		 1581 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1582 ret);
6a2953dd
YL		 1583 else
1584 netdev->mtu = new_mtu;
fe6362f9 1585
a8e8b7ff
S		 1586 return ret;
1587}
1588
f8fa222c
L		 1589static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1590{
1591 struct hns3_nic_priv *priv = netdev_priv(ndev);
1592 struct hns3_enet_ring *tx_ring = NULL;
1593 int timeout_queue = 0;
1594 int hw_head, hw_tail;
1595 int i;
1596
1597 /* Find the stopped queue the same way the stack does */
923e5809 1598 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 1599 struct netdev_queue *q;
1600 unsigned long trans_start;
1601
1602 q = netdev_get_tx_queue(ndev, i);
1603 trans_start = q->trans_start;
1604 if (netif_xmit_stopped(q) &&
1605 time_after(jiffies,
1606 (trans_start + ndev->watchdog_timeo))) {
1607 timeout_queue = i;
724d05cc
YL		 1608 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1609 q->state,
1610 jiffies_to_msecs(jiffies - trans_start));
f8fa222c
L		 1611 break;
1612 }
1613 }
1614
1615 if (i == ndev->num_tx_queues) {
1616 netdev_info(ndev,
1617 "no netdev TX timeout queue found, timeout count: %llu\n",
1618 priv->tx_timeout_count);
1619 return false;
1620 }
1621
1622 tx_ring = priv->ring_data[timeout_queue].ring;
1623
1624 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1625 HNS3_RING_TX_RING_HEAD_REG);
1626 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1627 HNS3_RING_TX_RING_TAIL_REG);
1628 netdev_info(ndev,
1629 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1630 priv->tx_timeout_count,
1631 timeout_queue,
1632 tx_ring->next_to_use,
1633 tx_ring->next_to_clean,
1634 hw_head,
1635 hw_tail,
1636 readl(tx_ring->tqp_vector->mask_addr));
1637
1638 return true;
1639}
1640
1641static void hns3_nic_net_timeout(struct net_device *ndev)
1642{
1643 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1644 struct hnae3_handle *h = priv->ae_handle;
1645
1646 if (!hns3_get_tx_timeo_queue_info(ndev))
1647 return;
1648
1649 priv->tx_timeout_count++;
1650
1a2f7bf2
HT		 1651 /* request the reset, and let the hclge to determine
1652 * which reset level should be done
1653 */
f8fa222c 1654 if (h->ae_algo->ops->reset_event)
538d8ba0 1655 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 1656}
1657
76ad4f0e
S		 1658static const struct net_device_ops hns3_nic_netdev_ops = {
1659 .ndo_open = hns3_nic_net_open,
1660 .ndo_stop = hns3_nic_net_stop,
1661 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1662 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1663 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
a185d723 1664 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1665 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1666 .ndo_set_features = hns3_nic_set_features,
1667 .ndo_get_stats64 = hns3_nic_get_stats64,
1668 .ndo_setup_tc = hns3_nic_setup_tc,
1669 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1670 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1671 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1672 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1673};
1674
bc59f827
FL		 1675static bool hns3_is_phys_func(struct pci_dev *pdev)
1676{
1677 u32 dev_id = pdev->device;
1678
1679 switch (dev_id) {
1680 case HNAE3_DEV_ID_GE:
1681 case HNAE3_DEV_ID_25GE:
1682 case HNAE3_DEV_ID_25GE_RDMA:
1683 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1684 case HNAE3_DEV_ID_50GE_RDMA:
1685 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1686 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1687 return true;
1688 case HNAE3_DEV_ID_100G_VF:
1689 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1690 return false;
1691 default:
1692 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1693 dev_id);
1694 }
1695
1696 return false;
1697}
1698
bc59f827
FL		 1699static void hns3_disable_sriov(struct pci_dev *pdev)
1700{
1701 /* If our VFs are assigned we cannot shut down SR-IOV
1702 * without causing issues, so just leave the hardware
1703 * available but disabled
1704 */
1705 if (pci_vfs_assigned(pdev)) {
1706 dev_warn(&pdev->dev,
1707 "disabling driver while VFs are assigned\n");
1708 return;
1709 }
1710
1711 pci_disable_sriov(pdev);
1712}
1713
10a954bc
JS		 1714static void hns3_get_dev_capability(struct pci_dev *pdev,
1715 struct hnae3_ae_dev *ae_dev)
1716{
73f88b00 1717 if (pdev->revision >= 0x21) {
10a954bc 1718 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
73f88b00
PL		 1719 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1720 }
10a954bc
JS		 1721}
1722
76ad4f0e
S		 1723/* hns3_probe - Device initialization routine
1724 * @pdev: PCI device information struct
1725 * @ent: entry in hns3_pci_tbl
1726 *
1727 * hns3_probe initializes a PF identified by a pci_dev structure.
1728 * The OS initialization, configuring of the PF private structure,
1729 * and a hardware reset occur.
1730 *
1731 * Returns 0 on success, negative on failure
1732 */
1733static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1734{
1735 struct hnae3_ae_dev *ae_dev;
1736 int ret;
1737
1738 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1739 GFP_KERNEL);
1740 if (!ae_dev) {
1741 ret = -ENOMEM;
1742 return ret;
1743 }
1744
1745 ae_dev->pdev = pdev;
e92a0843 1746 ae_dev->flag = ent->driver_data;
76ad4f0e 1747 ae_dev->dev_type = HNAE3_DEV_KNIC;
7ce98982 1748 ae_dev->reset_type = HNAE3_NONE_RESET;
10a954bc 1749 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S		 1750 pci_set_drvdata(pdev, ae_dev);
1751
17901db4
HT		 1752 ret = hnae3_register_ae_dev(ae_dev);
1753 if (ret) {
1754 devm_kfree(&pdev->dev, ae_dev);
1755 pci_set_drvdata(pdev, NULL);
1756 }
bc59f827 1757
17901db4 1758 return ret;
76ad4f0e
S		 1759}
1760
1761/* hns3_remove - Device removal routine
1762 * @pdev: PCI device information struct
1763 */
1764static void hns3_remove(struct pci_dev *pdev)
1765{
1766 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1767
bc59f827
FL		 1768 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1769 hns3_disable_sriov(pdev);
1770
76ad4f0e 1771 hnae3_unregister_ae_dev(ae_dev);
142e1137 1772 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 1773}
1774
cfeff578
PL		 1775/**
1776 * hns3_pci_sriov_configure
1777 * @pdev: pointer to a pci_dev structure
1778 * @num_vfs: number of VFs to allocate
1779 *
1780 * Enable or change the number of VFs. Called when the user updates the number
1781 * of VFs in sysfs.
1782 **/
baff3ed7 1783static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
cfeff578
PL		 1784{
1785 int ret;
1786
1787 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1788 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1789 return -EINVAL;
1790 }
1791
1792 if (num_vfs) {
1793 ret = pci_enable_sriov(pdev, num_vfs);
1794 if (ret)
1795 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
baff3ed7
SM		 1796 else
1797 return num_vfs;
cfeff578
PL		 1798 } else if (!pci_vfs_assigned(pdev)) {
1799 pci_disable_sriov(pdev);
1800 } else {
1801 dev_warn(&pdev->dev,
1802 "Unable to free VFs because some are assigned to VMs.\n");
1803 }
1804
1805 return 0;
1806}
1807
4f043c3e
YL		 1808static void hns3_shutdown(struct pci_dev *pdev)
1809{
1810 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1811
1812 hnae3_unregister_ae_dev(ae_dev);
1813 devm_kfree(&pdev->dev, ae_dev);
1814 pci_set_drvdata(pdev, NULL);
1815
1816 if (system_state == SYSTEM_POWER_OFF)
1817 pci_set_power_state(pdev, PCI_D3hot);
1818}
1819
00bb612a
SJ		 1820static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1821 pci_channel_state_t state)
1822{
1823 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1824 pci_ers_result_t ret;
1825
1826 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1827
1828 if (state == pci_channel_io_perm_failure)
1829 return PCI_ERS_RESULT_DISCONNECT;
1830
1831 if (!ae_dev) {
1832 dev_err(&pdev->dev,
1833 "Can't recover - error happened during device init\n");
1834 return PCI_ERS_RESULT_NONE;
1835 }
1836
af72a21f
SJ		 1837 if (ae_dev->ops->handle_hw_ras_error)
1838 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
00bb612a
SJ		 1839 else
1840 return PCI_ERS_RESULT_NONE;
1841
1842 return ret;
1843}
1844
538d8ba0
SJ		 1845static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1846{
1847 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1848 struct device *dev = &pdev->dev;
1849
1850 dev_info(dev, "requesting reset due to PCI error\n");
1851
1852 /* request the reset */
1853 if (ae_dev->ops->reset_event) {
1854 ae_dev->ops->reset_event(pdev, NULL);
1855 return PCI_ERS_RESULT_RECOVERED;
1856 }
1857
1858 return PCI_ERS_RESULT_DISCONNECT;
1859}
1860
26977990
HT		 1861static void hns3_reset_prepare(struct pci_dev *pdev)
1862{
1863 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1864
1865 dev_info(&pdev->dev, "hns3 flr prepare\n");
1866 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1867 ae_dev->ops->flr_prepare(ae_dev);
1868}
1869
1870static void hns3_reset_done(struct pci_dev *pdev)
1871{
1872 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1873
1874 dev_info(&pdev->dev, "hns3 flr done\n");
1875 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
1876 ae_dev->ops->flr_done(ae_dev);
1877}
1878
00bb612a
SJ		 1879static const struct pci_error_handlers hns3_err_handler = {
1880 .error_detected = hns3_error_detected,
538d8ba0 1881 .slot_reset = hns3_slot_reset,
26977990
HT		 1882 .reset_prepare = hns3_reset_prepare,
1883 .reset_done = hns3_reset_done,
00bb612a
SJ		 1884};
1885
76ad4f0e
S		 1886static struct pci_driver hns3_driver = {
1887 .name = hns3_driver_name,
1888 .id_table = hns3_pci_tbl,
1889 .probe = hns3_probe,
1890 .remove = hns3_remove,
4f043c3e 1891 .shutdown = hns3_shutdown,
cfeff578 1892 .sriov_configure = hns3_pci_sriov_configure,
00bb612a 1893 .err_handler = &hns3_err_handler,
76ad4f0e
S		 1894};
1895
1896/* set default feature to hns3 */
1897static void hns3_set_default_feature(struct net_device *netdev)
1898{
a4c378bb
PL		 1899 struct hnae3_handle *h = hns3_get_handle(netdev);
1900 struct pci_dev *pdev = h->pdev;
1901
76ad4f0e
S		 1902 netdev->priv_flags |= IFF_UNICAST_FLT;
1903
1904 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1905 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1906 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1907 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
0361a8bc 1908 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1909
1910 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1911
1912 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1913
1914 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1915 NETIF_F_HW_VLAN_CTAG_FILTER |
5f9a7732 1916 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1917 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1918 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1919 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
0361a8bc 1920 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1921
1922 netdev->vlan_features |=
1923 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1924 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1925 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1926 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
0361a8bc 1927 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 1928
1929 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3849d494 1930 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1931 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1932 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1933 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
0361a8bc 1934 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
a4c378bb 1935
d1f04a80 1936 if (pdev->revision >= 0x21) {
a4c378bb 1937 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d1f04a80
JS		 1938
1939 if (!(h->flags & HNAE3_SUPPORT_VF)) {
1940 netdev->hw_features |= NETIF_F_NTUPLE;
1941 netdev->features |= NETIF_F_NTUPLE;
1942 }
1943 }
76ad4f0e
S		 1944}
1945
1946static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1947 struct hns3_desc_cb *cb)
1948{
ccc23ef3 1949 unsigned int order = hnae3_page_order(ring);
76ad4f0e
S		 1950 struct page *p;
1951
1952 p = dev_alloc_pages(order);
1953 if (!p)
1954 return -ENOMEM;
1955
1956 cb->priv = p;
1957 cb->page_offset = 0;
1958 cb->reuse_flag = 0;
1959 cb->buf = page_address(p);
ccc23ef3 1960 cb->length = hnae3_page_size(ring);
76ad4f0e
S		 1961 cb->type = DESC_TYPE_PAGE;
1962
76ad4f0e
S		 1963 return 0;
1964}
1965
1966static void hns3_free_buffer(struct hns3_enet_ring *ring,
1967 struct hns3_desc_cb *cb)
1968{
1969 if (cb->type == DESC_TYPE_SKB)
1970 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1971 else if (!HNAE3_IS_TX_RING(ring))
1972 put_page((struct page *)cb->priv);
1973 memset(cb, 0, sizeof(*cb));
1974}
1975
1976static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1977{
1978 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1979 cb->length, ring_to_dma_dir(ring));
1980
39bbc873 1981 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 1982 return -EIO;
1983
1984 return 0;
1985}
1986
1987static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
1988 struct hns3_desc_cb *cb)
1989{
1990 if (cb->type == DESC_TYPE_SKB)
1991 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
1992 ring_to_dma_dir(ring));
6a3bff0d 1993 else if (cb->length)
76ad4f0e
S		 1994 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
1995 ring_to_dma_dir(ring));
1996}
1997
1998static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
1999{
2000 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2001 ring->desc[i].addr = 0;
2002}
2003
2004static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2005{
2006 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2007
2008 if (!ring->desc_cb[i].dma)
2009 return;
2010
2011 hns3_buffer_detach(ring, i);
2012 hns3_free_buffer(ring, cb);
2013}
2014
2015static void hns3_free_buffers(struct hns3_enet_ring *ring)
2016{
2017 int i;
2018
2019 for (i = 0; i < ring->desc_num; i++)
2020 hns3_free_buffer_detach(ring, i);
2021}
2022
2023/* free desc along with its attached buffer */
2024static void hns3_free_desc(struct hns3_enet_ring *ring)
2025{
d61c1a80
HT		 2026 int size = ring->desc_num * sizeof(ring->desc[0]);
2027
76ad4f0e
S		 2028 hns3_free_buffers(ring);
2029
d61c1a80
HT		 2030 if (ring->desc) {
2031 dma_free_coherent(ring_to_dev(ring), size,
2032 ring->desc, ring->desc_dma_addr);
2033 ring->desc = NULL;
2034 }
76ad4f0e
S		 2035}
2036
2037static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2038{
2039 int size = ring->desc_num * sizeof(ring->desc[0]);
2040
d61c1a80
HT		 2041 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size,
2042 &ring->desc_dma_addr,
2043 GFP_KERNEL);
76ad4f0e
S		 2044 if (!ring->desc)
2045 return -ENOMEM;
2046
76ad4f0e
S		 2047 return 0;
2048}
2049
2050static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2051 struct hns3_desc_cb *cb)
2052{
2053 int ret;
2054
2055 ret = hns3_alloc_buffer(ring, cb);
2056 if (ret)
2057 goto out;
2058
2059 ret = hns3_map_buffer(ring, cb);
2060 if (ret)
2061 goto out_with_buf;
2062
2063 return 0;
2064
2065out_with_buf:
564883bb 2066 hns3_free_buffer(ring, cb);
76ad4f0e
S		 2067out:
2068 return ret;
2069}
2070
2071static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2072{
2073 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2074
2075 if (ret)
2076 return ret;
2077
2078 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2079
2080 return 0;
2081}
2082
2083/* Allocate memory for raw pkg, and map with dma */
2084static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2085{
2086 int i, j, ret;
2087
2088 for (i = 0; i < ring->desc_num; i++) {
2089 ret = hns3_alloc_buffer_attach(ring, i);
2090 if (ret)
2091 goto out_buffer_fail;
2092 }
2093
2094 return 0;
2095
2096out_buffer_fail:
2097 for (j = i - 1; j >= 0; j--)
2098 hns3_free_buffer_detach(ring, j);
2099 return ret;
2100}
2101
2102/* detach a in-used buffer and replace with a reserved one */
2103static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2104 struct hns3_desc_cb *res_cb)
2105{
b9077428 2106 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2107 ring->desc_cb[i] = *res_cb;
2108 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
4169a686 2109 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2110}
2111
2112static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2113{
2114 ring->desc_cb[i].reuse_flag = 0;
2115 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
2116 + ring->desc_cb[i].page_offset);
4169a686 2117 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2118}
2119
1f9c1dcb
YL		 2120static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2121 int *bytes, int *pkts)
76ad4f0e 2122{
a41def26
YL		 2123 int ntc = ring->next_to_clean;
2124 struct hns3_desc_cb *desc_cb;
76ad4f0e 2125
1f9c1dcb
YL		 2126 while (head != ntc) {
2127 desc_cb = &ring->desc_cb[ntc];
2128 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2129 (*bytes) += desc_cb->length;
2130 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2131 hns3_free_buffer_detach(ring, ntc);
76ad4f0e 2132
1f9c1dcb
YL		 2133 if (++ntc == ring->desc_num)
2134 ntc = 0;
2135
2136 /* Issue prefetch for next Tx descriptor */
2137 prefetch(&ring->desc_cb[ntc]);
2138 }
a41def26
YL		 2139
2140 /* This smp_store_release() pairs with smp_load_acquire() in
2141 * ring_space called by hns3_nic_net_xmit.
2142 */
2143 smp_store_release(&ring->next_to_clean, ntc);
76ad4f0e
S		 2144}
2145
2146static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2147{
2148 int u = ring->next_to_use;
2149 int c = ring->next_to_clean;
2150
2151 if (unlikely(h > ring->desc_num))
2152 return 0;
2153
2154 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2155}
2156
6a38a95f 2157void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 2158{
2159 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
c3e4287e 2160 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2161 struct netdev_queue *dev_queue;
2162 int bytes, pkts;
2163 int head;
2164
2165 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2166 rmb(); /* Make sure head is ready before touch any data */
2167
2168 if (is_ring_empty(ring) || head == ring->next_to_clean)
6a38a95f 2169 return; /* no data to poll */
76ad4f0e 2170
2ea8667b 2171 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S		 2172 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2173 ring->next_to_use, ring->next_to_clean);
2174
2175 u64_stats_update_begin(&ring->syncp);
2176 ring->stats.io_err_cnt++;
2177 u64_stats_update_end(&ring->syncp);
6a38a95f 2178 return;
76ad4f0e
S		 2179 }
2180
2181 bytes = 0;
2182 pkts = 0;
1f9c1dcb 2183 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
76ad4f0e
S		 2184
2185 ring->tqp_vector->tx_group.total_bytes += bytes;
2186 ring->tqp_vector->tx_group.total_packets += pkts;
2187
2188 u64_stats_update_begin(&ring->syncp);
2189 ring->stats.tx_bytes += bytes;
2190 ring->stats.tx_pkts += pkts;
2191 u64_stats_update_end(&ring->syncp);
2192
2193 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2194 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2195
2196 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2197 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2198 /* Make sure that anybody stopping the queue after this
2199 * sees the new next_to_clean.
2200 */
2201 smp_mb();
c3e4287e
JS		 2202 if (netif_tx_queue_stopped(dev_queue) &&
2203 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2204 netif_tx_wake_queue(dev_queue);
2205 ring->stats.restart_queue++;
2206 }
2207 }
76ad4f0e
S		 2208}
2209
2210static int hns3_desc_unused(struct hns3_enet_ring *ring)
2211{
2212 int ntc = ring->next_to_clean;
2213 int ntu = ring->next_to_use;
2214
2215 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2216}
2217
2218static void
2219hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2220{
2221 struct hns3_desc_cb *desc_cb;
2222 struct hns3_desc_cb res_cbs;
2223 int i, ret;
2224
2225 for (i = 0; i < cleand_count; i++) {
2226 desc_cb = &ring->desc_cb[ring->next_to_use];
2227 if (desc_cb->reuse_flag) {
2228 u64_stats_update_begin(&ring->syncp);
2229 ring->stats.reuse_pg_cnt++;
2230 u64_stats_update_end(&ring->syncp);
2231
2232 hns3_reuse_buffer(ring, ring->next_to_use);
2233 } else {
2234 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2235 if (ret) {
2236 u64_stats_update_begin(&ring->syncp);
2237 ring->stats.sw_err_cnt++;
2238 u64_stats_update_end(&ring->syncp);
2239
2240 netdev_err(ring->tqp->handle->kinfo.netdev,
2241 "hnae reserve buffer map failed.\n");
2242 break;
2243 }
2244 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2245 }
2246
2247 ring_ptr_move_fw(ring, next_to_use);
2248 }
2249
2250 wmb(); /* Make all data has been write before submit */
2251 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2252}
2253
76ad4f0e
S		 2254static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2255 struct hns3_enet_ring *ring, int pull_len,
2256 struct hns3_desc_cb *desc_cb)
2257{
2258 struct hns3_desc *desc;
e56a15b7
HT		 2259 u32 truesize;
2260 int size;
76ad4f0e
S		 2261 int last_offset;
2262 bool twobufs;
2263
2264 twobufs = ((PAGE_SIZE < 8192) &&
ccc23ef3 2265 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
76ad4f0e
S		 2266
2267 desc = &ring->desc[ring->next_to_clean];
2268 size = le16_to_cpu(desc->rx.size);
2269
ccc23ef3 2270 truesize = hnae3_buf_size(ring);
885a882a
PL		 2271
2272 if (!twobufs)
ccc23ef3 2273 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
76ad4f0e
S		 2274
2275 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
885a882a 2276 size - pull_len, truesize);
76ad4f0e
S		 2277
2278 /* Avoid re-using remote pages,flag default unreuse */
2279 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2280 return;
2281
2282 if (twobufs) {
2283 /* If we are only owner of page we can reuse it */
2284 if (likely(page_count(desc_cb->priv) == 1)) {
2285 /* Flip page offset to other buffer */
2286 desc_cb->page_offset ^= truesize;
2287
2288 desc_cb->reuse_flag = 1;
2289 /* bump ref count on page before it is given*/
2290 get_page(desc_cb->priv);
2291 }
2292 return;
2293 }
2294
2295 /* Move offset up to the next cache line */
2296 desc_cb->page_offset += truesize;
2297
2298 if (desc_cb->page_offset <= last_offset) {
2299 desc_cb->reuse_flag = 1;
2300 /* Bump ref count on page before it is given*/
2301 get_page(desc_cb->priv);
2302 }
2303}
2304
2305static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2306 struct hns3_desc *desc)
2307{
2308 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2309 int l3_type, l4_type;
2310 u32 bd_base_info;
2311 int ol4_type;
2312 u32 l234info;
2313
2314 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2315 l234info = le32_to_cpu(desc->rx.l234_info);
2316
2317 skb->ip_summed = CHECKSUM_NONE;
2318
2319 skb_checksum_none_assert(skb);
2320
2321 if (!(netdev->features & NETIF_F_RXCSUM))
2322 return;
2323
5337b725
PL		 2324 /* We MUST enable hardware checksum before enabling hardware GRO */
2325 if (skb_shinfo(skb)->gso_size) {
2326 skb->ip_summed = CHECKSUM_UNNECESSARY;
2327 return;
2328 }
2329
76ad4f0e 2330 /* check if hardware has done checksum */
ccc23ef3 2331 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
76ad4f0e
S		 2332 return;
2333
ccc23ef3
PL		 2334 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2335 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2336 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2337 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
76ad4f0e
S		 2338 u64_stats_update_begin(&ring->syncp);
2339 ring->stats.l3l4_csum_err++;
2340 u64_stats_update_end(&ring->syncp);
2341
2342 return;
2343 }
2344
ccc23ef3
PL		 2345 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2346 HNS3_RXD_L3ID_S);
2347 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2348 HNS3_RXD_L4ID_S);
76ad4f0e 2349
ccc23ef3
PL		 2350 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2351 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2352 switch (ol4_type) {
2353 case HNS3_OL4_TYPE_MAC_IN_UDP:
2354 case HNS3_OL4_TYPE_NVGRE:
2355 skb->csum_level = 1;
64061deb 2356 /* fall through */
76ad4f0e
S		 2357 case HNS3_OL4_TYPE_NO_TUN:
2358 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
ffa051fa
PL		 2359 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2360 l3_type == HNS3_L3_TYPE_IPV6) &&
2361 (l4_type == HNS3_L4_TYPE_UDP ||
2362 l4_type == HNS3_L4_TYPE_TCP ||
2363 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2364 skb->ip_summed = CHECKSUM_UNNECESSARY;
2365 break;
085920ba
JS		 2366 default:
2367 break;
76ad4f0e
S		 2368 }
2369}
2370
d43e5aca
YL		 2371static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2372{
4110bcf6
PL		 2373 if (skb_has_frag_list(skb))
2374 napi_gro_flush(&ring->tqp_vector->napi, false);
2375
d43e5aca
YL		 2376 napi_gro_receive(&ring->tqp_vector->napi, skb);
2377}
2378
34456a7c
JS		 2379static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2380 struct hns3_desc *desc, u32 l234info,
2381 u16 *vlan_tag)
1e8f8bd3
PL		 2382{
2383 struct pci_dev *pdev = ring->tqp->handle->pdev;
1e8f8bd3
PL		 2384
2385 if (pdev->revision == 0x20) {
34456a7c
JS		 2386 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2387 if (!(*vlan_tag & VLAN_VID_MASK))
2388 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
1e8f8bd3 2389
34456a7c 2390 return (*vlan_tag != 0);
1e8f8bd3
PL		 2391 }
2392
2393#define HNS3_STRP_OUTER_VLAN 0x1
2394#define HNS3_STRP_INNER_VLAN 0x2
2395
ccc23ef3
PL		 2396 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2397 HNS3_RXD_STRP_TAGP_S)) {
1e8f8bd3 2398 case HNS3_STRP_OUTER_VLAN:
34456a7c
JS		 2399 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2400 return true;
1e8f8bd3 2401 case HNS3_STRP_INNER_VLAN:
34456a7c
JS		 2402 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2403 return true;
1e8f8bd3 2404 default:
34456a7c 2405 return false;
1e8f8bd3 2406 }
1e8f8bd3
PL		 2407}
2408
72b50a78
PL		 2409static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length,
2410 unsigned char *va)
2411{
2412#define HNS3_NEED_ADD_FRAG 1
2413 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2414 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2415 struct sk_buff *skb;
2416
2417 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2418 skb = ring->skb;
2419 if (unlikely(!skb)) {
2420 netdev_err(netdev, "alloc rx skb fail\n");
2421
2422 u64_stats_update_begin(&ring->syncp);
2423 ring->stats.sw_err_cnt++;
2424 u64_stats_update_end(&ring->syncp);
2425
2426 return -ENOMEM;
2427 }
2428
2429 prefetchw(skb->data);
2430
2431 ring->pending_buf = 1;
4110bcf6
PL		 2432 ring->frag_num = 0;
2433 ring->tail_skb = NULL;
72b50a78
PL		 2434 if (length <= HNS3_RX_HEAD_SIZE) {
2435 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2436
2437 /* We can reuse buffer as-is, just make sure it is local */
2438 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2439 desc_cb->reuse_flag = 1;
2440 else /* This page cannot be reused so discard it */
2441 put_page(desc_cb->priv);
2442
2443 ring_ptr_move_fw(ring, next_to_clean);
2444 return 0;
2445 }
2446 u64_stats_update_begin(&ring->syncp);
2447 ring->stats.seg_pkt_cnt++;
2448 u64_stats_update_end(&ring->syncp);
2449
2450 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2451 __skb_put(skb, ring->pull_len);
4110bcf6 2452 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
72b50a78
PL		 2453 desc_cb);
2454 ring_ptr_move_fw(ring, next_to_clean);
2455
2456 return HNS3_NEED_ADD_FRAG;
2457}
2458
2459static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2460 struct sk_buff **out_skb, bool pending)
2461{
2462 struct sk_buff *skb = *out_skb;
4110bcf6
PL		 2463 struct sk_buff *head_skb = *out_skb;
2464 struct sk_buff *new_skb;
72b50a78
PL		 2465 struct hns3_desc_cb *desc_cb;
2466 struct hns3_desc *pre_desc;
2467 u32 bd_base_info;
2468 int pre_bd;
2469
2470 /* if there is pending bd, the SW param next_to_clean has moved
2471 * to next and the next is NULL
2472 */
2473 if (pending) {
2474 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2475 ring->desc_num;
2476 pre_desc = &ring->desc[pre_bd];
2477 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2478 } else {
2479 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2480 }
2481
2482 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2483 desc = &ring->desc[ring->next_to_clean];
2484 desc_cb = &ring->desc_cb[ring->next_to_clean];
2485 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2ed550c5
JS		 2486 /* make sure HW write desc complete */
2487 dma_rmb();
72b50a78
PL		 2488 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))
2489 return -ENXIO;
2490
4110bcf6
PL		 2491 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2492 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2493 HNS3_RX_HEAD_SIZE);
2494 if (unlikely(!new_skb)) {
2495 netdev_err(ring->tqp->handle->kinfo.netdev,
2496 "alloc rx skb frag fail\n");
2497 return -ENXIO;
2498 }
2499 ring->frag_num = 0;
2500
2501 if (ring->tail_skb) {
2502 ring->tail_skb->next = new_skb;
2503 ring->tail_skb = new_skb;
2504 } else {
2505 skb_shinfo(skb)->frag_list = new_skb;
2506 ring->tail_skb = new_skb;
2507 }
2508 }
2509
2510 if (ring->tail_skb) {
2511 head_skb->truesize += hnae3_buf_size(ring);
2512 head_skb->data_len += le16_to_cpu(desc->rx.size);
2513 head_skb->len += le16_to_cpu(desc->rx.size);
2514 skb = ring->tail_skb;
2515 }
2516
2517 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
72b50a78
PL		 2518 ring_ptr_move_fw(ring, next_to_clean);
2519 ring->pending_buf++;
2520 }
2521
2522 return 0;
2523}
2524
5337b725
PL		 2525static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info,
2526 u32 bd_base_info)
2527{
2528 u16 gro_count;
2529 u32 l3_type;
2530
2531 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M,
2532 HNS3_RXD_GRO_COUNT_S);
2533 /* if there is no HW GRO, do not set gro params */
2534 if (!gro_count)
2535 return;
2536
2537 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
2538 * to skb_shinfo(skb)->gso_segs
2539 */
2540 NAPI_GRO_CB(skb)->count = gro_count;
2541
2542 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2543 HNS3_RXD_L3ID_S);
2544 if (l3_type == HNS3_L3_TYPE_IPV4)
2545 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2546 else if (l3_type == HNS3_L3_TYPE_IPV6)
2547 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2548 else
2549 return;
2550
2551 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2552 HNS3_RXD_GRO_SIZE_M,
2553 HNS3_RXD_GRO_SIZE_S);
2554 if (skb_shinfo(skb)->gso_size)
2555 tcp_gro_complete(skb);
2556}
2557
8e4c877d
PL		 2558static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2559 struct sk_buff *skb)
2560{
8e4c877d
PL		 2561 struct hnae3_handle *handle = ring->tqp->handle;
2562 enum pkt_hash_types rss_type;
023a793f
PL		 2563 struct hns3_desc *desc;
2564 int last_bd;
2565
2566 /* When driver handle the rss type, ring->next_to_clean indicates the
2567 * first descriptor of next packet, need -1 here.
2568 */
2569 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num;
2570 desc = &ring->desc[last_bd];
8e4c877d
PL		 2571
2572 if (le32_to_cpu(desc->rx.rss_hash))
2573 rss_type = handle->kinfo.rss_type;
2574 else
2575 rss_type = PKT_HASH_TYPE_NONE;
2576
2577 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type);
2578}
2579
76ad4f0e 2580static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
72b50a78 2581 struct sk_buff **out_skb)
76ad4f0e
S		 2582{
2583 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
72b50a78 2584 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 2585 struct hns3_desc_cb *desc_cb;
2586 struct hns3_desc *desc;
76ad4f0e 2587 u32 bd_base_info;
76ad4f0e
S		 2588 u32 l234info;
2589 int length;
72b50a78 2590 int ret;
76ad4f0e
S		 2591
2592 desc = &ring->desc[ring->next_to_clean];
2593 desc_cb = &ring->desc_cb[ring->next_to_clean];
2594
2595 prefetch(desc);
2596
ca61f05e 2597 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2598 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 2599
2600 /* Check valid BD */
ccc23ef3 2601 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
72b50a78 2602 return -ENXIO;
76ad4f0e 2603
72b50a78
PL		 2604 if (!skb)
2605 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
76ad4f0e
S		 2606
2607 /* Prefetch first cache line of first page
2608 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2609 * line size is 64B so need to prefetch twice to make it 128B. But in
2610 * actual we can have greater size of caches with 128B Level 1 cache
2611 * lines. In such a case, single fetch would suffice to cache in the
2612 * relevant part of the header.
2613 */
72b50a78 2614 prefetch(ring->va);
76ad4f0e 2615#if L1_CACHE_BYTES < 128
72b50a78 2616 prefetch(ring->va + L1_CACHE_BYTES);
76ad4f0e
S		 2617#endif
2618
72b50a78
PL		 2619 if (!skb) {
2620 ret = hns3_alloc_skb(ring, length, ring->va);
2621 *out_skb = skb = ring->skb;
76ad4f0e 2622
72b50a78
PL		 2623 if (ret < 0) /* alloc buffer fail */
2624 return ret;
2625 if (ret > 0) { /* need add frag */
2626 ret = hns3_add_frag(ring, desc, &skb, false);
2627 if (ret)
2628 return ret;
76ad4f0e 2629
72b50a78
PL		 2630 /* As the head data may be changed when GRO enable, copy
2631 * the head data in after other data rx completed
2632 */
2633 memcpy(skb->data, ring->va,
2634 ALIGN(ring->pull_len, sizeof(long)));
2635 }
76ad4f0e 2636 } else {
72b50a78
PL		 2637 ret = hns3_add_frag(ring, desc, &skb, true);
2638 if (ret)
2639 return ret;
76ad4f0e 2640
72b50a78
PL		 2641 /* As the head data may be changed when GRO enable, copy
2642 * the head data in after other data rx completed
2643 */
2644 memcpy(skb->data, ring->va,
2645 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e
S		 2646 }
2647
928d369a 2648 l234info = le32_to_cpu(desc->rx.l234_info);
72b50a78 2649 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
928d369a 2650
ca61f05e
PL		 2651 /* Based on hw strategy, the tag offloaded will be stored at
2652 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2653 * in one layer tag case.
2654 */
2655 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2656 u16 vlan_tag;
2657
34456a7c 2658 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
ca61f05e
PL		 2659 __vlan_hwaccel_put_tag(skb,
2660 htons(ETH_P_8021Q),
2661 vlan_tag);
2662 }
2663
ccc23ef3 2664 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
76ad4f0e
S		 2665 u64_stats_update_begin(&ring->syncp);
2666 ring->stats.non_vld_descs++;
2667 u64_stats_update_end(&ring->syncp);
2668
2669 dev_kfree_skb_any(skb);
2670 return -EINVAL;
2671 }
2672
2673 if (unlikely((!desc->rx.pkt_len) ||
ccc23ef3 2674 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
76ad4f0e
S		 2675 u64_stats_update_begin(&ring->syncp);
2676 ring->stats.err_pkt_len++;
2677 u64_stats_update_end(&ring->syncp);
2678
2679 dev_kfree_skb_any(skb);
2680 return -EFAULT;
2681 }
2682
ccc23ef3 2683 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
76ad4f0e
S		 2684 u64_stats_update_begin(&ring->syncp);
2685 ring->stats.l2_err++;
2686 u64_stats_update_end(&ring->syncp);
2687
2688 dev_kfree_skb_any(skb);
2689 return -EFAULT;
2690 }
2691
2692 u64_stats_update_begin(&ring->syncp);
2693 ring->stats.rx_pkts++;
2694 ring->stats.rx_bytes += skb->len;
2695 u64_stats_update_end(&ring->syncp);
2696
2697 ring->tqp_vector->rx_group.total_bytes += skb->len;
2698
5337b725
PL		 2699 /* This is needed in order to enable forwarding support */
2700 hns3_set_gro_param(skb, l234info, bd_base_info);
2701
76ad4f0e 2702 hns3_rx_checksum(ring, skb, desc);
72b50a78 2703 *out_skb = skb;
8e4c877d
PL		 2704 hns3_set_rx_skb_rss_type(ring, skb);
2705
76ad4f0e
S		 2706 return 0;
2707}
2708
d43e5aca
YL		 2709int hns3_clean_rx_ring(
2710 struct hns3_enet_ring *ring, int budget,
2711 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2712{
2713#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2714 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2715 int recv_pkts, recv_bds, clean_count, err;
72b50a78
PL		 2716 int unused_count = hns3_desc_unused(ring) - ring->pending_buf;
2717 struct sk_buff *skb = ring->skb;
2718 int num;
76ad4f0e
S		 2719
2720 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2721 rmb(); /* Make sure num taken effect before the other data is touched */
2722
2723 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2724 num -= unused_count;
2725
2726 while (recv_pkts < budget && recv_bds < num) {
2727 /* Reuse or realloc buffers */
2728 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2729 hns3_nic_alloc_rx_buffers(ring,
2730 clean_count + unused_count);
2731 clean_count = 0;
72b50a78
PL		 2732 unused_count = hns3_desc_unused(ring) -
2733 ring->pending_buf;
76ad4f0e
S		 2734 }
2735
2736 /* Poll one pkt */
72b50a78 2737 err = hns3_handle_rx_bd(ring, &skb);
76ad4f0e
S		 2738 if (unlikely(!skb)) /* This fault cannot be repaired */
2739 goto out;
2740
72b50a78
PL		 2741 if (err == -ENXIO) { /* Do not get FE for the packet */
2742 goto out;
2743 } else if (unlikely(err)) { /* Do jump the err */
2744 recv_bds += ring->pending_buf;
2745 clean_count += ring->pending_buf;
2746 ring->skb = NULL;
2747 ring->pending_buf = 0;
76ad4f0e
S		 2748 continue;
2749 }
2750
2751 /* Do update ip stack process */
2752 skb->protocol = eth_type_trans(skb, netdev);
d43e5aca 2753 rx_fn(ring, skb);
72b50a78
PL		 2754 recv_bds += ring->pending_buf;
2755 clean_count += ring->pending_buf;
2756 ring->skb = NULL;
2757 ring->pending_buf = 0;
76ad4f0e
S		 2758
2759 recv_pkts++;
2760 }
2761
2762out:
2763 /* Make all data has been write before submit */
2764 if (clean_count + unused_count > 0)
2765 hns3_nic_alloc_rx_buffers(ring,
2766 clean_count + unused_count);
2767
2768 return recv_pkts;
2769}
2770
2771static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2772{
50477f37
FL		 2773 struct hns3_enet_tqp_vector *tqp_vector =
2774 ring_group->ring->tqp_vector;
76ad4f0e 2775 enum hns3_flow_level_range new_flow_level;
50477f37
FL		 2776 int packets_per_msecs;
2777 int bytes_per_msecs;
2778 u32 time_passed_ms;
76ad4f0e 2779 u16 new_int_gl;
76ad4f0e 2780
3f58e29e 2781 if (!tqp_vector->last_jiffies)
76ad4f0e
S		 2782 return false;
2783
2784 if (ring_group->total_packets == 0) {
d420d2de
YL		 2785 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2786 ring_group->coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 2787 return true;
2788 }
2789
2790 /* Simple throttlerate management
2791 * 0-10MB/s lower (50000 ints/s)
2792 * 10-20MB/s middle (20000 ints/s)
2793 * 20-1249MB/s high (18000 ints/s)
2794 * > 40000pps ultra (8000 ints/s)
2795 */
d420d2de
YL		 2796 new_flow_level = ring_group->coal.flow_level;
2797 new_int_gl = ring_group->coal.int_gl;
50477f37
FL		 2798 time_passed_ms =
2799 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2800
2801 if (!time_passed_ms)
2802 return false;
2803
2804 do_div(ring_group->total_packets, time_passed_ms);
2805 packets_per_msecs = ring_group->total_packets;
2806
2807 do_div(ring_group->total_bytes, time_passed_ms);
2808 bytes_per_msecs = ring_group->total_bytes;
2809
2810#define HNS3_RX_LOW_BYTE_RATE 10000
2811#define HNS3_RX_MID_BYTE_RATE 20000
76ad4f0e
S		 2812
2813 switch (new_flow_level) {
2814 case HNS3_FLOW_LOW:
50477f37 2815 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2816 new_flow_level = HNS3_FLOW_MID;
2817 break;
2818 case HNS3_FLOW_MID:
50477f37 2819 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2820 new_flow_level = HNS3_FLOW_HIGH;
50477f37 2821 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2822 new_flow_level = HNS3_FLOW_LOW;
2823 break;
2824 case HNS3_FLOW_HIGH:
2825 case HNS3_FLOW_ULTRA:
2826 default:
50477f37 2827 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2828 new_flow_level = HNS3_FLOW_MID;
2829 break;
2830 }
2831
50477f37
FL		 2832#define HNS3_RX_ULTRA_PACKET_RATE 40
2833
2834 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2835 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 2836 new_flow_level = HNS3_FLOW_ULTRA;
2837
2838 switch (new_flow_level) {
2839 case HNS3_FLOW_LOW:
2840 new_int_gl = HNS3_INT_GL_50K;
2841 break;
2842 case HNS3_FLOW_MID:
2843 new_int_gl = HNS3_INT_GL_20K;
2844 break;
2845 case HNS3_FLOW_HIGH:
2846 new_int_gl = HNS3_INT_GL_18K;
2847 break;
2848 case HNS3_FLOW_ULTRA:
2849 new_int_gl = HNS3_INT_GL_8K;
2850 break;
2851 default:
2852 break;
2853 }
2854
2855 ring_group->total_bytes = 0;
2856 ring_group->total_packets = 0;
d420d2de
YL		 2857 ring_group->coal.flow_level = new_flow_level;
2858 if (new_int_gl != ring_group->coal.int_gl) {
2859 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 2860 return true;
2861 }
2862 return false;
2863}
2864
2865static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2866{
dc114fce
FL		 2867 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2868 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2869 bool rx_update, tx_update;
2870
9c46bc10
PL		 2871 /* update param every 1000ms */
2872 if (time_before(jiffies,
2873 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
3f97bd23 2874 return;
3f97bd23 2875
d420d2de 2876 if (rx_group->coal.gl_adapt_enable) {
dc114fce
FL		 2877 rx_update = hns3_get_new_int_gl(rx_group);
2878 if (rx_update)
2879 hns3_set_vector_coalesce_rx_gl(tqp_vector,
d420d2de 2880 rx_group->coal.int_gl);
dc114fce
FL		 2881 }
2882
d420d2de 2883 if (tx_group->coal.gl_adapt_enable) {
dc114fce
FL		 2884 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2885 if (tx_update)
2886 hns3_set_vector_coalesce_tx_gl(tqp_vector,
d420d2de 2887 tx_group->coal.int_gl);
76ad4f0e 2888 }
3f97bd23 2889
50477f37 2890 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 2891}
2892
2893static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2894{
f22463fd 2895 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 2896 struct hns3_enet_ring *ring;
2897 int rx_pkt_total = 0;
2898
2899 struct hns3_enet_tqp_vector *tqp_vector =
2900 container_of(napi, struct hns3_enet_tqp_vector, napi);
2901 bool clean_complete = true;
2902 int rx_budget;
2903
f22463fd
HT		 2904 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
2905 napi_complete(napi);
2906 return 0;
2907 }
2908
76ad4f0e
S		 2909 /* Since the actual Tx work is minimal, we can give the Tx a larger
2910 * budget and be more aggressive about cleaning up the Tx descriptors.
2911 */
6a38a95f
PL		 2912 hns3_for_each_ring(ring, tqp_vector->tx_group)
2913 hns3_clean_tx_ring(ring);
76ad4f0e
S		 2914
2915 /* make sure rx ring budget not smaller than 1 */
2916 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2917
2918 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 2919 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2920 hns3_rx_skb);
76ad4f0e
S		 2921
2922 if (rx_cleaned >= rx_budget)
2923 clean_complete = false;
2924
2925 rx_pkt_total += rx_cleaned;
2926 }
2927
2928 tqp_vector->rx_group.total_packets += rx_pkt_total;
2929
2930 if (!clean_complete)
2931 return budget;
2932
be1c4048
HT		 2933 if (napi_complete(napi) &&
2934 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
f22463fd
HT		 2935 hns3_update_new_int_gl(tqp_vector);
2936 hns3_mask_vector_irq(tqp_vector, 1);
2937 }
76ad4f0e
S		 2938
2939 return rx_pkt_total;
2940}
2941
2942static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2943 struct hnae3_ring_chain_node *head)
2944{
2945 struct pci_dev *pdev = tqp_vector->handle->pdev;
2946 struct hnae3_ring_chain_node *cur_chain = head;
2947 struct hnae3_ring_chain_node *chain;
2948 struct hns3_enet_ring *tx_ring;
2949 struct hns3_enet_ring *rx_ring;
2950
2951 tx_ring = tqp_vector->tx_group.ring;
2952 if (tx_ring) {
2953 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
ccc23ef3
PL		 2954 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2955 HNAE3_RING_TYPE_TX);
2956 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2957 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 2958
2959 cur_chain->next = NULL;
2960
2961 while (tx_ring->next) {
2962 tx_ring = tx_ring->next;
2963
2964 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2965 GFP_KERNEL);
2966 if (!chain)
1129d424 2967 goto err_free_chain;
76ad4f0e
S		 2968
2969 cur_chain->next = chain;
2970 chain->tqp_index = tx_ring->tqp->tqp_index;
ccc23ef3
PL		 2971 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2972 HNAE3_RING_TYPE_TX);
2973 hnae3_set_field(chain->int_gl_idx,
2974 HNAE3_RING_GL_IDX_M,
2975 HNAE3_RING_GL_IDX_S,
2976 HNAE3_RING_GL_TX);
76ad4f0e
S		 2977
2978 cur_chain = chain;
2979 }
2980 }
2981
2982 rx_ring = tqp_vector->rx_group.ring;
2983 if (!tx_ring && rx_ring) {
2984 cur_chain->next = NULL;
2985 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
ccc23ef3
PL		 2986 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2987 HNAE3_RING_TYPE_RX);
2988 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2989 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 2990
2991 rx_ring = rx_ring->next;
2992 }
2993
2994 while (rx_ring) {
2995 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
2996 if (!chain)
1129d424 2997 goto err_free_chain;
76ad4f0e
S		 2998
2999 cur_chain->next = chain;
3000 chain->tqp_index = rx_ring->tqp->tqp_index;
ccc23ef3
PL		 3001 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3002 HNAE3_RING_TYPE_RX);
3003 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3004 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
f230c6c5 3005
76ad4f0e
S		 3006 cur_chain = chain;
3007
3008 rx_ring = rx_ring->next;
3009 }
3010
3011 return 0;
1129d424
HT		 3012
3013err_free_chain:
3014 cur_chain = head->next;
3015 while (cur_chain) {
3016 chain = cur_chain->next;
cc8e7db2 3017 devm_kfree(&pdev->dev, cur_chain);
1129d424
HT		 3018 cur_chain = chain;
3019 }
cc8e7db2 3020 head->next = NULL;
1129d424
HT		 3021
3022 return -ENOMEM;
76ad4f0e
S		 3023}
3024
3025static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3026 struct hnae3_ring_chain_node *head)
3027{
3028 struct pci_dev *pdev = tqp_vector->handle->pdev;
3029 struct hnae3_ring_chain_node *chain_tmp, *chain;
3030
3031 chain = head->next;
3032
3033 while (chain) {
3034 chain_tmp = chain->next;
3035 devm_kfree(&pdev->dev, chain);
3036 chain = chain_tmp;
3037 }
3038}
3039
3040static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3041 struct hns3_enet_ring *ring)
3042{
3043 ring->next = group->ring;
3044 group->ring = ring;
3045
3046 group->count++;
3047}
3048
15040788
PL		 3049static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3050{
3051 struct pci_dev *pdev = priv->ae_handle->pdev;
3052 struct hns3_enet_tqp_vector *tqp_vector;
3053 int num_vectors = priv->vector_num;
3054 int numa_node;
3055 int vector_i;
3056
3057 numa_node = dev_to_node(&pdev->dev);
3058
3059 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3060 tqp_vector = &priv->tqp_vector[vector_i];
3061 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3062 &tqp_vector->affinity_mask);
3063 }
3064}
3065
76ad4f0e
S		 3066static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3067{
3068 struct hnae3_ring_chain_node vector_ring_chain;
3069 struct hnae3_handle *h = priv->ae_handle;
3070 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3071 int ret = 0;
3c424930 3072 int i;
76ad4f0e 3073
15040788
PL		 3074 hns3_nic_set_cpumask(priv);
3075
6cbd6d33
YL		 3076 for (i = 0; i < priv->vector_num; i++) {
3077 tqp_vector = &priv->tqp_vector[i];
3078 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3079 tqp_vector->num_tqps = 0;
3080 }
76ad4f0e 3081
6cbd6d33
YL		 3082 for (i = 0; i < h->kinfo.num_tqps; i++) {
3083 u16 vector_i = i % priv->vector_num;
3084 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3085
3086 tqp_vector = &priv->tqp_vector[vector_i];
3087
3088 hns3_add_ring_to_group(&tqp_vector->tx_group,
3089 priv->ring_data[i].ring);
3090
3091 hns3_add_ring_to_group(&tqp_vector->rx_group,
3092 priv->ring_data[i + tqp_num].ring);
3093
76ad4f0e
S		 3094 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3095 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
6cbd6d33 3096 tqp_vector->num_tqps++;
76ad4f0e
S		 3097 }
3098
6cbd6d33 3099 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3100 tqp_vector = &priv->tqp_vector[i];
3101
3102 tqp_vector->rx_group.total_bytes = 0;
3103 tqp_vector->rx_group.total_packets = 0;
3104 tqp_vector->tx_group.total_bytes = 0;
3105 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3106 tqp_vector->handle = h;
3107
3108 ret = hns3_get_vector_ring_chain(tqp_vector,
3109 &vector_ring_chain);
3110 if (ret)
cc8e7db2 3111 goto map_ring_fail;
76ad4f0e
S		 3112
3113 ret = h->ae_algo->ops->map_ring_to_vector(h,
3114 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3115
3116 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3117
6cbd6d33 3118 if (ret)
3c424930 3119 goto map_ring_fail;
6cbd6d33 3120
76ad4f0e
S		 3121 netif_napi_add(priv->netdev, &tqp_vector->napi,
3122 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3123 }
3124
6cbd6d33 3125 return 0;
3c424930
HT		 3126
3127map_ring_fail:
3128 while (i--)
3129 netif_napi_del(&priv->tqp_vector[i].napi);
3130
3131 return ret;
6cbd6d33
YL		 3132}
3133
3134static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3135{
f56424b6
JS		 3136#define HNS3_VECTOR_PF_MAX_NUM 64
3137
6cbd6d33
YL		 3138 struct hnae3_handle *h = priv->ae_handle;
3139 struct hns3_enet_tqp_vector *tqp_vector;
3140 struct hnae3_vector_info *vector;
3141 struct pci_dev *pdev = h->pdev;
3142 u16 tqp_num = h->kinfo.num_tqps;
3143 u16 vector_num;
3144 int ret = 0;
3145 u16 i;
3146
3147 /* RSS size, cpu online and vector_num should be the same */
3148 /* Should consider 2p/4p later */
3149 vector_num = min_t(u16, num_online_cpus(), tqp_num);
f56424b6
JS		 3150 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3151
6cbd6d33
YL		 3152 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3153 GFP_KERNEL);
3154 if (!vector)
3155 return -ENOMEM;
3156
3157 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3158
3159 priv->vector_num = vector_num;
3160 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3161 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3162 GFP_KERNEL);
3163 if (!priv->tqp_vector) {
3164 ret = -ENOMEM;
3165 goto out;
3166 }
3167
3168 for (i = 0; i < priv->vector_num; i++) {
3169 tqp_vector = &priv->tqp_vector[i];
3170 tqp_vector->idx = i;
3171 tqp_vector->mask_addr = vector[i].io_addr;
3172 tqp_vector->vector_irq = vector[i].vector;
3173 hns3_vector_gl_rl_init(tqp_vector, priv);
3174 }
3175
76ad4f0e
S		 3176out:
3177 devm_kfree(&pdev->dev, vector);
3178 return ret;
3179}
3180
6cbd6d33
YL		 3181static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3182{
3183 group->ring = NULL;
3184 group->count = 0;
3185}
3186
76ad4f0e
S		 3187static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3188{
3189 struct hnae3_ring_chain_node vector_ring_chain;
3190 struct hnae3_handle *h = priv->ae_handle;
3191 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 3192 int i, ret;
3193
3194 for (i = 0; i < priv->vector_num; i++) {
3195 tqp_vector = &priv->tqp_vector[i];
3196
3197 ret = hns3_get_vector_ring_chain(tqp_vector,
3198 &vector_ring_chain);
3199 if (ret)
3200 return ret;
3201
3202 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
3203 tqp_vector->vector_irq, &vector_ring_chain);
3204 if (ret)
3205 return ret;
3206
3207 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3208
32a9b305
HT		 3209 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
3210 irq_set_affinity_notifier(tqp_vector->vector_irq,
3211 NULL);
3212 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3213 free_irq(tqp_vector->vector_irq, tqp_vector);
3214 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
76ad4f0e
S		 3215 }
3216
3217 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
6cbd6d33
YL		 3218 hns3_clear_ring_group(&tqp_vector->rx_group);
3219 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3220 netif_napi_del(&priv->tqp_vector[i].napi);
3221 }
3222
6cbd6d33
YL		 3223 return 0;
3224}
3225
3226static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3227{
3228 struct hnae3_handle *h = priv->ae_handle;
3229 struct pci_dev *pdev = h->pdev;
3230 int i, ret;
3231
3232 for (i = 0; i < priv->vector_num; i++) {
3233 struct hns3_enet_tqp_vector *tqp_vector;
3234
3235 tqp_vector = &priv->tqp_vector[i];
3236 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3237 if (ret)
3238 return ret;
3239 }
76ad4f0e 3240
6cbd6d33 3241 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3242 return 0;
3243}
3244
3245static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3246 int ring_type)
3247{
3248 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3249 int queue_num = priv->ae_handle->kinfo.num_tqps;
3250 struct pci_dev *pdev = priv->ae_handle->pdev;
3251 struct hns3_enet_ring *ring;
3252
3253 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3254 if (!ring)
3255 return -ENOMEM;
3256
3257 if (ring_type == HNAE3_RING_TYPE_TX) {
3258 ring_data[q->tqp_index].ring = ring;
66b44730 3259 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 3260 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3261 } else {
3262 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 3263 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 3264 ring->io_base = q->io_base;
3265 }
3266
ccc23ef3 3267 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3268
76ad4f0e
S		 3269 ring->tqp = q;
3270 ring->desc = NULL;
3271 ring->desc_cb = NULL;
3272 ring->dev = priv->dev;
3273 ring->desc_dma_addr = 0;
3274 ring->buf_size = q->buf_size;
3275 ring->desc_num = q->desc_num;
3276 ring->next_to_use = 0;
3277 ring->next_to_clean = 0;
3278
3279 return 0;
3280}
3281
3282static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3283 struct hns3_nic_priv *priv)
3284{
3285 int ret;
3286
3287 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3288 if (ret)
3289 return ret;
3290
3291 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
1129d424
HT		 3292 if (ret) {
3293 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
76ad4f0e 3294 return ret;
1129d424 3295 }
76ad4f0e
S		 3296
3297 return 0;
3298}
3299
3300static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3301{
3302 struct hnae3_handle *h = priv->ae_handle;
3303 struct pci_dev *pdev = h->pdev;
3304 int i, ret;
3305
3306 priv->ring_data = devm_kzalloc(&pdev->dev, h->kinfo.num_tqps *
3307 sizeof(*priv->ring_data) * 2,
3308 GFP_KERNEL);
3309 if (!priv->ring_data)
3310 return -ENOMEM;
3311
3312 for (i = 0; i < h->kinfo.num_tqps; i++) {
3313 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3314 if (ret)
3315 goto err;
3316 }
3317
3318 return 0;
3319err:
1129d424
HT		 3320 while (i--) {
3321 devm_kfree(priv->dev, priv->ring_data[i].ring);
3322 devm_kfree(priv->dev,
3323 priv->ring_data[i + h->kinfo.num_tqps].ring);
3324 }
3325
76ad4f0e
S		 3326 devm_kfree(&pdev->dev, priv->ring_data);
3327 return ret;
3328}
3329
f1f779ce
PL		 3330static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3331{
3332 struct hnae3_handle *h = priv->ae_handle;
3333 int i;
3334
3335 for (i = 0; i < h->kinfo.num_tqps; i++) {
3336 devm_kfree(priv->dev, priv->ring_data[i].ring);
3337 devm_kfree(priv->dev,
3338 priv->ring_data[i + h->kinfo.num_tqps].ring);
3339 }
3340 devm_kfree(priv->dev, priv->ring_data);
3341}
3342
76ad4f0e
S		 3343static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3344{
3345 int ret;
3346
3347 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3348 return -EINVAL;
3349
3350 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
3351 GFP_KERNEL);
3352 if (!ring->desc_cb) {
3353 ret = -ENOMEM;
3354 goto out;
3355 }
3356
3357 ret = hns3_alloc_desc(ring);
3358 if (ret)
3359 goto out_with_desc_cb;
3360
3361 if (!HNAE3_IS_TX_RING(ring)) {
3362 ret = hns3_alloc_ring_buffers(ring);
3363 if (ret)
3364 goto out_with_desc;
3365 }
3366
3367 return 0;
3368
3369out_with_desc:
3370 hns3_free_desc(ring);
3371out_with_desc_cb:
3372 kfree(ring->desc_cb);
3373 ring->desc_cb = NULL;
3374out:
3375 return ret;
3376}
3377
3378static void hns3_fini_ring(struct hns3_enet_ring *ring)
3379{
3380 hns3_free_desc(ring);
3381 kfree(ring->desc_cb);
3382 ring->desc_cb = NULL;
3383 ring->next_to_clean = 0;
3384 ring->next_to_use = 0;
3385}
3386
1db9b1bf 3387static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3388{
3389 int bd_size_type;
3390
3391 switch (buf_size) {
3392 case 512:
3393 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3394 break;
3395 case 1024:
3396 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3397 break;
3398 case 2048:
3399 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3400 break;
3401 case 4096:
3402 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3403 break;
3404 default:
3405 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3406 }
3407
3408 return bd_size_type;
3409}
3410
3411static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3412{
3413 dma_addr_t dma = ring->desc_dma_addr;
3414 struct hnae3_queue *q = ring->tqp;
3415
3416 if (!HNAE3_IS_TX_RING(ring)) {
3417 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3418 (u32)dma);
3419 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3420 (u32)((dma >> 31) >> 1));
3421
3422 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3423 hns3_buf_size2type(ring->buf_size));
3424 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3425 ring->desc_num / 8 - 1);
3426
3427 } else {
3428 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3429 (u32)dma);
3430 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3431 (u32)((dma >> 31) >> 1));
3432
76ad4f0e
S		 3433 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3434 ring->desc_num / 8 - 1);
3435 }
3436}
3437
fe46c859
YL		 3438static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3439{
3440 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3441 int i;
3442
3443 for (i = 0; i < HNAE3_MAX_TC; i++) {
3444 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3445 int j;
3446
3447 if (!tc_info->enable)
3448 continue;
3449
3450 for (j = 0; j < tc_info->tqp_count; j++) {
3451 struct hnae3_queue *q;
3452
3453 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3454 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3455 tc_info->tc);
3456 }
3457 }
3458}
3459
5668abda 3460int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3461{
3462 struct hnae3_handle *h = priv->ae_handle;
3463 int ring_num = h->kinfo.num_tqps * 2;
3464 int i, j;
3465 int ret;
3466
3467 for (i = 0; i < ring_num; i++) {
3468 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3469 if (ret) {
3470 dev_err(priv->dev,
3471 "Alloc ring memory fail! ret=%d\n", ret);
3472 goto out_when_alloc_ring_memory;
3473 }
3474
76ad4f0e
S		 3475 u64_stats_init(&priv->ring_data[i].ring->syncp);
3476 }
3477
3478 return 0;
3479
3480out_when_alloc_ring_memory:
3481 for (j = i - 1; j >= 0; j--)
ee83f776 3482 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 3483
3484 return -ENOMEM;
3485}
3486
5668abda 3487int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3488{
3489 struct hnae3_handle *h = priv->ae_handle;
3490 int i;
3491
3492 for (i = 0; i < h->kinfo.num_tqps; i++) {
76ad4f0e
S		 3493 hns3_fini_ring(priv->ring_data[i].ring);
3494 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3495 }
76ad4f0e
S		 3496 return 0;
3497}
3498
3499/* Set mac addr if it is configured. or leave it to the AE driver */
abe62a63 3500static int hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 3501{
3502 struct hns3_nic_priv *priv = netdev_priv(netdev);
3503 struct hnae3_handle *h = priv->ae_handle;
3504 u8 mac_addr_temp[ETH_ALEN];
abe62a63 3505 int ret = 0;
76ad4f0e 3506
edf76c8e 3507 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 3508 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3509 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3510 }
3511
3512 /* Check if the MAC address is valid, if not get a random one */
3513 if (!is_valid_ether_addr(netdev->dev_addr)) {
3514 eth_hw_addr_random(netdev);
3515 dev_warn(priv->dev, "using random MAC address %pM\n",
3516 netdev->dev_addr);
76ad4f0e 3517 }
139e8792
L		 3518
3519 if (h->ae_algo->ops->set_mac_addr)
abe62a63 3520 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3521
abe62a63 3522 return ret;
76ad4f0e
S		 3523}
3524
7ce98982
JS		 3525static int hns3_restore_fd_rules(struct net_device *netdev)
3526{
3527 struct hnae3_handle *h = hns3_get_handle(netdev);
3528 int ret = 0;
3529
3530 if (h->ae_algo->ops->restore_fd_rules)
3531 ret = h->ae_algo->ops->restore_fd_rules(h);
3532
3533 return ret;
3534}
3535
3536static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3537{
3538 struct hnae3_handle *h = hns3_get_handle(netdev);
3539
3540 if (h->ae_algo->ops->del_all_fd_entries)
3541 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3542}
3543
76ad4f0e
S		 3544static void hns3_nic_set_priv_ops(struct net_device *netdev)
3545{
3546 struct hns3_nic_priv *priv = netdev_priv(netdev);
3547
e4c38d6e 3548 priv->ops.fill_desc = hns3_fill_desc;
76ad4f0e 3549 if ((netdev->features & NETIF_F_TSO) ||
e4c38d6e 3550 (netdev->features & NETIF_F_TSO6))
76ad4f0e 3551 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
e4c38d6e 3552 else
76ad4f0e 3553 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
76ad4f0e
S		 3554}
3555
337460de
YL		 3556static int hns3_client_start(struct hnae3_handle *handle)
3557{
3558 if (!handle->ae_algo->ops->client_start)
3559 return 0;
3560
3561 return handle->ae_algo->ops->client_start(handle);
3562}
3563
3564static void hns3_client_stop(struct hnae3_handle *handle)
3565{
3566 if (!handle->ae_algo->ops->client_stop)
3567 return;
3568
3569 handle->ae_algo->ops->client_stop(handle);
3570}
3571
76ad4f0e
S		 3572static int hns3_client_init(struct hnae3_handle *handle)
3573{
3574 struct pci_dev *pdev = handle->pdev;
08ca3d58 3575 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 3576 struct hns3_nic_priv *priv;
3577 struct net_device *netdev;
3578 int ret;
3579
08ca3d58
HT		 3580 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3581 &max_rss_size);
3582 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 3583 if (!netdev)
3584 return -ENOMEM;
3585
3586 priv = netdev_priv(netdev);
3587 priv->dev = &pdev->dev;
3588 priv->netdev = netdev;
3589 priv->ae_handle = handle;
f8fa222c 3590 priv->tx_timeout_count = 0;
76ad4f0e
S		 3591
3592 handle->kinfo.netdev = netdev;
3593 handle->priv = (void *)priv;
3594
edf76c8e 3595 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3596
3597 hns3_set_default_feature(netdev);
3598
3599 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3600 netdev->priv_flags |= IFF_UNICAST_FLT;
3601 netdev->netdev_ops = &hns3_nic_netdev_ops;
3602 SET_NETDEV_DEV(netdev, &pdev->dev);
3603 hns3_ethtool_set_ops(netdev);
3604 hns3_nic_set_priv_ops(netdev);
3605
3606 /* Carrier off reporting is important to ethtool even BEFORE open */
3607 netif_carrier_off(netdev);
3608
3609 ret = hns3_get_ring_config(priv);
3610 if (ret) {
3611 ret = -ENOMEM;
3612 goto out_get_ring_cfg;
3613 }
3614
6cbd6d33
YL		 3615 ret = hns3_nic_alloc_vector_data(priv);
3616 if (ret) {
3617 ret = -ENOMEM;
3618 goto out_alloc_vector_data;
3619 }
3620
76ad4f0e
S		 3621 ret = hns3_nic_init_vector_data(priv);
3622 if (ret) {
3623 ret = -ENOMEM;
3624 goto out_init_vector_data;
3625 }
3626
3627 ret = hns3_init_all_ring(priv);
3628 if (ret) {
3629 ret = -ENOMEM;
3630 goto out_init_ring_data;
3631 }
3632
3633 ret = register_netdev(netdev);
3634 if (ret) {
3635 dev_err(priv->dev, "probe register netdev fail!\n");
3636 goto out_reg_netdev_fail;
3637 }
3638
337460de
YL		 3639 ret = hns3_client_start(handle);
3640 if (ret) {
3641 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
3642 goto out_reg_netdev_fail;
3643 }
3644
986743db
YL		 3645 hns3_dcbnl_setup(handle);
3646
a9556d8c 3647 hns3_dbg_init(handle);
3648
bd975002 3649 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
4ee09281 3650 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 3651
352285f1
HT		 3652 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3653
76ad4f0e
S		 3654 return ret;
3655
3656out_reg_netdev_fail:
3657out_init_ring_data:
3658 (void)hns3_nic_uninit_vector_data(priv);
76ad4f0e 3659out_init_vector_data:
6cbd6d33
YL		 3660 hns3_nic_dealloc_vector_data(priv);
3661out_alloc_vector_data:
3662 priv->ring_data = NULL;
76ad4f0e
S		 3663out_get_ring_cfg:
3664 priv->ae_handle = NULL;
3665 free_netdev(netdev);
3666 return ret;
3667}
3668
3669static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3670{
3671 struct net_device *netdev = handle->kinfo.netdev;
3672 struct hns3_nic_priv *priv = netdev_priv(netdev);
3673 int ret;
3674
337460de
YL		 3675 hns3_client_stop(handle);
3676
2c794374
JS		 3677 hns3_remove_hw_addr(netdev);
3678
76ad4f0e
S		 3679 if (netdev->reg_state != NETREG_UNINITIALIZED)
3680 unregister_netdev(netdev);
3681
352285f1
HT		 3682 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3683 netdev_warn(netdev, "already uninitialized\n");
3684 goto out_netdev_free;
3685 }
3686
c27ad61b
JS		 3687 hns3_del_all_fd_rules(netdev, true);
3688
e32a805a
FL		 3689 hns3_force_clear_all_rx_ring(handle);
3690
76ad4f0e
S		 3691 ret = hns3_nic_uninit_vector_data(priv);
3692 if (ret)
3693 netdev_err(netdev, "uninit vector error\n");
3694
6cbd6d33
YL		 3695 ret = hns3_nic_dealloc_vector_data(priv);
3696 if (ret)
3697 netdev_err(netdev, "dealloc vector error\n");
3698
76ad4f0e
S		 3699 ret = hns3_uninit_all_ring(priv);
3700 if (ret)
3701 netdev_err(netdev, "uninit ring error\n");
3702
a2ddee8c
YL		 3703 hns3_put_ring_config(priv);
3704
a9556d8c 3705 hns3_dbg_uninit(handle);
3706
76ad4f0e
S		 3707 priv->ring_data = NULL;
3708
352285f1 3709out_netdev_free:
76ad4f0e
S		 3710 free_netdev(netdev);
3711}
3712
3713static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3714{
3715 struct net_device *netdev = handle->kinfo.netdev;
3716
3717 if (!netdev)
3718 return;
3719
3720 if (linkup) {
3721 netif_carrier_on(netdev);
3722 netif_tx_wake_all_queues(netdev);
3723 netdev_info(netdev, "link up\n");
3724 } else {
3725 netif_carrier_off(netdev);
3726 netif_tx_stop_all_queues(netdev);
3727 netdev_info(netdev, "link down\n");
3728 }
3729}
3730
9df8f79a
YL		 3731static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3732{
3733 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3734 struct net_device *ndev = kinfo->netdev;
075cfdd6 3735 bool if_running;
9df8f79a 3736 int ret;
9df8f79a
YL		 3737
3738 if (tc > HNAE3_MAX_TC)
3739 return -EINVAL;
3740
3741 if (!ndev)
3742 return -ENODEV;
3743
075cfdd6
CIK		 3744 if_running = netif_running(ndev);
3745
9df8f79a
YL		 3746 if (if_running) {
3747 (void)hns3_nic_net_stop(ndev);
3748 msleep(100);
3749 }
3750
3751 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3752 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3753 if (ret)
3754 goto err_out;
3755
9df8f79a
YL		 3756 ret = hns3_nic_set_real_num_queue(ndev);
3757
3758err_out:
3759 if (if_running)
3760 (void)hns3_nic_net_open(ndev);
3761
3762 return ret;
3763}
3764
abe62a63 3765static int hns3_recover_hw_addr(struct net_device *ndev)
bb6b94a8
L		 3766{
3767 struct netdev_hw_addr_list *list;
3768 struct netdev_hw_addr *ha, *tmp;
abe62a63 3769 int ret = 0;
bb6b94a8
L		 3770
3771 /* go through and sync uc_addr entries to the device */
3772 list = &ndev->uc;
abe62a63
HT		 3773 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3774 ret = hns3_nic_uc_sync(ndev, ha->addr);
3775 if (ret)
3776 return ret;
3777 }
bb6b94a8
L		 3778
3779 /* go through and sync mc_addr entries to the device */
3780 list = &ndev->mc;
abe62a63
HT		 3781 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3782 ret = hns3_nic_mc_sync(ndev, ha->addr);
3783 if (ret)
3784 return ret;
3785 }
3786
3787 return ret;
bb6b94a8
L		 3788}
3789
2c794374
JS		 3790static void hns3_remove_hw_addr(struct net_device *netdev)
3791{
3792 struct netdev_hw_addr_list *list;
3793 struct netdev_hw_addr *ha, *tmp;
3794
3795 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
3796
3797 /* go through and unsync uc_addr entries to the device */
3798 list = &netdev->uc;
3799 list_for_each_entry_safe(ha, tmp, &list->list, list)
3800 hns3_nic_uc_unsync(netdev, ha->addr);
3801
3802 /* go through and unsync mc_addr entries to the device */
3803 list = &netdev->mc;
3804 list_for_each_entry_safe(ha, tmp, &list->list, list)
3805 if (ha->refcount > 1)
3806 hns3_nic_mc_unsync(netdev, ha->addr);
3807}
3808
82172ec9 3809static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 3810{
82172ec9 3811 while (ring->next_to_clean != ring->next_to_use) {
e32a805a 3812 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
82172ec9
YL		 3813 hns3_free_buffer_detach(ring, ring->next_to_clean);
3814 ring_ptr_move_fw(ring, next_to_clean);
3815 }
3816}
3817
e32a805a
FL		 3818static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3819{
3820 struct hns3_desc_cb res_cbs;
3821 int ret;
3822
3823 while (ring->next_to_use != ring->next_to_clean) {
3824 /* When a buffer is not reused, it's memory has been
3825 * freed in hns3_handle_rx_bd or will be freed by
3826 * stack, so we need to replace the buffer here.
3827 */
3828 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3829 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3830 if (ret) {
3831 u64_stats_update_begin(&ring->syncp);
3832 ring->stats.sw_err_cnt++;
3833 u64_stats_update_end(&ring->syncp);
3834 /* if alloc new buffer fail, exit directly
3835 * and reclear in up flow.
3836 */
3837 netdev_warn(ring->tqp->handle->kinfo.netdev,
3838 "reserve buffer map failed, ret = %d\n",
3839 ret);
3840 return ret;
3841 }
3842 hns3_replace_buffer(ring, ring->next_to_use,
3843 &res_cbs);
3844 }
3845 ring_ptr_move_fw(ring, next_to_use);
3846 }
3847
3848 return 0;
3849}
3850
3851static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
82172ec9 3852{
82172ec9
YL		 3853 while (ring->next_to_use != ring->next_to_clean) {
3854 /* When a buffer is not reused, it's memory has been
3855 * freed in hns3_handle_rx_bd or will be freed by
3856 * stack, so only need to unmap the buffer here.
3857 */
3858 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3859 hns3_unmap_buffer(ring,
3860 &ring->desc_cb[ring->next_to_use]);
3861 ring->desc_cb[ring->next_to_use].dma = 0;
3862 }
3863
3864 ring_ptr_move_fw(ring, next_to_use);
3865 }
bb6b94a8
L		 3866}
3867
e32a805a
FL		 3868static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3869{
3870 struct net_device *ndev = h->kinfo.netdev;
3871 struct hns3_nic_priv *priv = netdev_priv(ndev);
3872 struct hns3_enet_ring *ring;
3873 u32 i;
3874
3875 for (i = 0; i < h->kinfo.num_tqps; i++) {
3876 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3877 hns3_force_clear_rx_ring(ring);
3878 }
3879}
3880
bb6b94a8
L		 3881static void hns3_clear_all_ring(struct hnae3_handle *h)
3882{
3883 struct net_device *ndev = h->kinfo.netdev;
3884 struct hns3_nic_priv *priv = netdev_priv(ndev);
3885 u32 i;
3886
3887 for (i = 0; i < h->kinfo.num_tqps; i++) {
3888 struct netdev_queue *dev_queue;
3889 struct hns3_enet_ring *ring;
3890
3891 ring = priv->ring_data[i].ring;
82172ec9 3892 hns3_clear_tx_ring(ring);
bb6b94a8
L		 3893 dev_queue = netdev_get_tx_queue(ndev,
3894 priv->ring_data[i].queue_index);
3895 netdev_tx_reset_queue(dev_queue);
3896
3897 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
e32a805a
FL		 3898 /* Continue to clear other rings even if clearing some
3899 * rings failed.
3900 */
82172ec9 3901 hns3_clear_rx_ring(ring);
bb6b94a8
L		 3902 }
3903}
3904
e32a805a
FL		 3905int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3906{
3907 struct net_device *ndev = h->kinfo.netdev;
3908 struct hns3_nic_priv *priv = netdev_priv(ndev);
3909 struct hns3_enet_ring *rx_ring;
3910 int i, j;
3911 int ret;
3912
3913 for (i = 0; i < h->kinfo.num_tqps; i++) {
abe62a63
HT		 3914 ret = h->ae_algo->ops->reset_queue(h, i);
3915 if (ret)
3916 return ret;
3917
e32a805a
FL		 3918 hns3_init_ring_hw(priv->ring_data[i].ring);
3919
3920 /* We need to clear tx ring here because self test will
3921 * use the ring and will not run down before up
3922 */
3923 hns3_clear_tx_ring(priv->ring_data[i].ring);
3924 priv->ring_data[i].ring->next_to_clean = 0;
3925 priv->ring_data[i].ring->next_to_use = 0;
3926
3927 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3928 hns3_init_ring_hw(rx_ring);
3929 ret = hns3_clear_rx_ring(rx_ring);
3930 if (ret)
3931 return ret;
3932
3933 /* We can not know the hardware head and tail when this
3934 * function is called in reset flow, so we reuse all desc.
3935 */
3936 for (j = 0; j < rx_ring->desc_num; j++)
3937 hns3_reuse_buffer(rx_ring, j);
3938
3939 rx_ring->next_to_clean = 0;
3940 rx_ring->next_to_use = 0;
3941 }
3942
fe46c859
YL		 3943 hns3_init_tx_ring_tc(priv);
3944
e32a805a
FL		 3945 return 0;
3946}
3947
0378eccc
HT		 3948static void hns3_store_coal(struct hns3_nic_priv *priv)
3949{
3950 /* ethtool only support setting and querying one coal
3951 * configuation for now, so save the vector 0' coal
3952 * configuation here in order to restore it.
3953 */
3954 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
3955 sizeof(struct hns3_enet_coalesce));
3956 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
3957 sizeof(struct hns3_enet_coalesce));
3958}
3959
3960static void hns3_restore_coal(struct hns3_nic_priv *priv)
3961{
3962 u16 vector_num = priv->vector_num;
3963 int i;
3964
3965 for (i = 0; i < vector_num; i++) {
3966 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
3967 sizeof(struct hns3_enet_coalesce));
3968 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
3969 sizeof(struct hns3_enet_coalesce));
3970 }
3971}
3972
bb6b94a8
L		 3973static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3974{
7e68177b 3975 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
bb6b94a8
L		 3976 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3977 struct net_device *ndev = kinfo->netdev;
3a11f446
HT		 3978 struct hns3_nic_priv *priv = netdev_priv(ndev);
3979
3980 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
3981 return 0;
bb6b94a8 3982
7e68177b
HT		 3983 /* it is cumbersome for hardware to pick-and-choose entries for deletion
3984 * from table space. Hence, for function reset software intervention is
3985 * required to delete the entries
3986 */
3987 if (hns3_dev_ongoing_func_reset(ae_dev)) {
3988 hns3_remove_hw_addr(ndev);
3989 hns3_del_all_fd_rules(ndev, false);
3990 }
3991
bb6b94a8 3992 if (!netif_running(ndev))
196b8760 3993 return 0;
bb6b94a8
L		 3994
3995 return hns3_nic_net_stop(ndev);
3996}
3997
3998static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
3999{
4000 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3a11f446 4001 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 4002 int ret = 0;
4003
ac2dca6b
HT		 4004 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4005
bb6b94a8 4006 if (netif_running(kinfo->netdev)) {
ac2dca6b 4007 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4008 if (ret) {
ac2dca6b 4009 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8
L		 4010 netdev_err(kinfo->netdev,
4011 "hns net up fail, ret=%d!\n", ret);
4012 return ret;
4013 }
bb6b94a8
L		 4014 }
4015
4016 return ret;
4017}
4018
4019static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4020{
4021 struct net_device *netdev = handle->kinfo.netdev;
4022 struct hns3_nic_priv *priv = netdev_priv(netdev);
ad94a397 4023 bool vlan_filter_enable;
bb6b94a8
L		 4024 int ret;
4025
abe62a63
HT		 4026 ret = hns3_init_mac_addr(netdev, false);
4027 if (ret)
4028 return ret;
4029
4030 ret = hns3_recover_hw_addr(netdev);
4031 if (ret)
4032 return ret;
4033
4034 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4035 if (ret)
4036 return ret;
4037
ad94a397
JS		 4038 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4039 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4040
103ce052 4041 /* Hardware table is only clear when pf resets */
abe62a63
HT		 4042 if (!(handle->flags & HNAE3_SUPPORT_VF)) {
4043 ret = hns3_restore_vlan(netdev);
8eb0e623
HT		 4044 if (ret)
4045 return ret;
abe62a63 4046 }
103ce052 4047
abe62a63
HT		 4048 ret = hns3_restore_fd_rules(netdev);
4049 if (ret)
4050 return ret;
7ce98982 4051
bb6b94a8
L		 4052 /* Carrier off reporting is important to ethtool even BEFORE open */
4053 netif_carrier_off(netdev);
4054
1c92981c
HT		 4055 ret = hns3_nic_alloc_vector_data(priv);
4056 if (ret)
4057 return ret;
4058
0378eccc
HT		 4059 hns3_restore_coal(priv);
4060
bb6b94a8
L		 4061 ret = hns3_nic_init_vector_data(priv);
4062 if (ret)
1c92981c 4063 goto err_dealloc_vector;
bb6b94a8
L		 4064
4065 ret = hns3_init_all_ring(priv);
1c92981c
HT		 4066 if (ret)
4067 goto err_uninit_vector;
bb6b94a8 4068
352285f1
HT		 4069 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4070
1c92981c
HT		 4071 return ret;
4072
4073err_uninit_vector:
4074 hns3_nic_uninit_vector_data(priv);
4075 priv->ring_data = NULL;
4076err_dealloc_vector:
4077 hns3_nic_dealloc_vector_data(priv);
4078
bb6b94a8
L		 4079 return ret;
4080}
4081
4082static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4083{
4084 struct net_device *netdev = handle->kinfo.netdev;
4085 struct hns3_nic_priv *priv = netdev_priv(netdev);
4086 int ret;
4087
352285f1
HT		 4088 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4089 netdev_warn(netdev, "already uninitialized\n");
4090 return 0;
4091 }
4092
e32a805a 4093 hns3_force_clear_all_rx_ring(handle);
bb6b94a8
L		 4094
4095 ret = hns3_nic_uninit_vector_data(priv);
4096 if (ret) {
4097 netdev_err(netdev, "uninit vector error\n");
4098 return ret;
4099 }
4100
0378eccc
HT		 4101 hns3_store_coal(priv);
4102
1c92981c
HT		 4103 ret = hns3_nic_dealloc_vector_data(priv);
4104 if (ret)
4105 netdev_err(netdev, "dealloc vector error\n");
4106
bb6b94a8
L		 4107 ret = hns3_uninit_all_ring(priv);
4108 if (ret)
4109 netdev_err(netdev, "uninit ring error\n");
4110
352285f1
HT		 4111 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
4112
bb6b94a8
L		 4113 return ret;
4114}
4115
4116static int hns3_reset_notify(struct hnae3_handle *handle,
4117 enum hnae3_reset_notify_type type)
4118{
4119 int ret = 0;
4120
4121 switch (type) {
4122 case HNAE3_UP_CLIENT:
741e1778
SM		 4123 ret = hns3_reset_notify_up_enet(handle);
4124 break;
bb6b94a8
L		 4125 case HNAE3_DOWN_CLIENT:
4126 ret = hns3_reset_notify_down_enet(handle);
4127 break;
4128 case HNAE3_INIT_CLIENT:
4129 ret = hns3_reset_notify_init_enet(handle);
4130 break;
4131 case HNAE3_UNINIT_CLIENT:
4132 ret = hns3_reset_notify_uninit_enet(handle);
4133 break;
4134 default:
4135 break;
4136 }
4137
4138 return ret;
4139}
4140
0378eccc 4141static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num)
f1f779ce
PL		 4142{
4143 struct hns3_nic_priv *priv = netdev_priv(netdev);
4144 struct hnae3_handle *h = hns3_get_handle(netdev);
4145 int ret;
4146
4147 ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
4148 if (ret)
4149 return ret;
4150
4151 ret = hns3_get_ring_config(priv);
4152 if (ret)
4153 return ret;
4154
6cbd6d33
YL		 4155 ret = hns3_nic_alloc_vector_data(priv);
4156 if (ret)
4157 goto err_alloc_vector;
4158
0378eccc 4159 hns3_restore_coal(priv);
351dad5e 4160
f1f779ce
PL		 4161 ret = hns3_nic_init_vector_data(priv);
4162 if (ret)
4163 goto err_uninit_vector;
4164
4165 ret = hns3_init_all_ring(priv);
4166 if (ret)
4167 goto err_put_ring;
4168
4169 return 0;
4170
4171err_put_ring:
4172 hns3_put_ring_config(priv);
4173err_uninit_vector:
4174 hns3_nic_uninit_vector_data(priv);
6cbd6d33
YL		 4175err_alloc_vector:
4176 hns3_nic_dealloc_vector_data(priv);
f1f779ce
PL		 4177 return ret;
4178}
4179
4180static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num)
4181{
4182 return (new_tqp_num / num_tc) * num_tc;
4183}
4184
4185int hns3_set_channels(struct net_device *netdev,
4186 struct ethtool_channels *ch)
4187{
4188 struct hns3_nic_priv *priv = netdev_priv(netdev);
4189 struct hnae3_handle *h = hns3_get_handle(netdev);
4190 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4191 bool if_running = netif_running(netdev);
4192 u32 new_tqp_num = ch->combined_count;
4193 u16 org_tqp_num;
4194 int ret;
4195
4196 if (ch->rx_count || ch->tx_count)
4197 return -EINVAL;
4198
2d7187ce 4199 if (new_tqp_num > hns3_get_max_available_channels(h) ||
f1f779ce
PL		 4200 new_tqp_num < kinfo->num_tc) {
4201 dev_err(&netdev->dev,
4202 "Change tqps fail, the tqp range is from %d to %d",
4203 kinfo->num_tc,
2d7187ce 4204 hns3_get_max_available_channels(h));
f1f779ce
PL		 4205 return -EINVAL;
4206 }
4207
4208 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num);
4209 if (kinfo->num_tqps == new_tqp_num)
4210 return 0;
4211
4212 if (if_running)
41efd6b1 4213 hns3_nic_net_stop(netdev);
f1f779ce 4214
f1f779ce
PL		 4215 ret = hns3_nic_uninit_vector_data(priv);
4216 if (ret) {
4217 dev_err(&netdev->dev,
4218 "Unbind vector with tqp fail, nothing is changed");
4219 goto open_netdev;
4220 }
4221
0378eccc 4222 hns3_store_coal(priv);
351dad5e 4223
6cbd6d33
YL		 4224 hns3_nic_dealloc_vector_data(priv);
4225
f1f779ce 4226 hns3_uninit_all_ring(priv);
a2ddee8c 4227 hns3_put_ring_config(priv);
f1f779ce
PL		 4228
4229 org_tqp_num = h->kinfo.num_tqps;
0378eccc 4230 ret = hns3_modify_tqp_num(netdev, new_tqp_num);
f1f779ce 4231 if (ret) {
0378eccc 4232 ret = hns3_modify_tqp_num(netdev, org_tqp_num);
f1f779ce
PL		 4233 if (ret) {
4234 /* If revert to old tqp failed, fatal error occurred */
4235 dev_err(&netdev->dev,
4236 "Revert to old tqp num fail, ret=%d", ret);
4237 return ret;
4238 }
4239 dev_info(&netdev->dev,
4240 "Change tqp num fail, Revert to old tqp num");
4241 }
4242
4243open_netdev:
4244 if (if_running)
41efd6b1 4245 hns3_nic_net_open(netdev);
f1f779ce
PL		 4246
4247 return ret;
4248}
4249
1db9b1bf 4250static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4251 .init_instance = hns3_client_init,
4252 .uninit_instance = hns3_client_uninit,
4253 .link_status_change = hns3_link_status_change,
9df8f79a 4254 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4255 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 4256};
4257
4258/* hns3_init_module - Driver registration routine
4259 * hns3_init_module is the first routine called when the driver is
4260 * loaded. All it does is register with the PCI subsystem.
4261 */
4262static int __init hns3_init_module(void)
4263{
4264 int ret;
4265
4266 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4267 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4268
4269 client.type = HNAE3_CLIENT_KNIC;
4270 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4271 hns3_driver_name);
4272
4273 client.ops = &client_ops;
4274
dadc9935
XW		 4275 INIT_LIST_HEAD(&client.node);
4276
a9556d8c 4277 hns3_dbg_register_debugfs(hns3_driver_name);
4278
76ad4f0e
S		 4279 ret = hnae3_register_client(&client);
4280 if (ret)
a9556d8c 4281 goto err_reg_client;
76ad4f0e
S		 4282
4283 ret = pci_register_driver(&hns3_driver);
4284 if (ret)
a9556d8c 4285 goto err_reg_driver;
76ad4f0e
S		 4286
4287 return ret;
a9556d8c 4288
4289err_reg_driver:
4290 hnae3_unregister_client(&client);
4291err_reg_client:
4292 hns3_dbg_unregister_debugfs();
4293 return ret;
76ad4f0e
S		 4294}
4295module_init(hns3_init_module);
4296
4297/* hns3_exit_module - Driver exit cleanup routine
4298 * hns3_exit_module is called just before the driver is removed
4299 * from memory.
4300 */
4301static void __exit hns3_exit_module(void)
4302{
4303 pci_unregister_driver(&hns3_driver);
4304 hnae3_unregister_client(&client);
a9556d8c 4305 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4306}
4307module_exit(hns3_exit_module);
4308
4309MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4310MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4311MODULE_LICENSE("GPL");
4312MODULE_ALIAS("pci:hns-nic");
4786ad87 4313MODULE_VERSION(HNS3_MOD_VERSION);
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