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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
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1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
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S
3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
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7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
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10#include <linux/if_vlan.h>
11#include <linux/ip.h>
12#include <linux/ipv6.h>
13#include <linux/module.h>
14#include <linux/pci.h>
6ae4e733 15#include <linux/aer.h>
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16#include <linux/skbuff.h>
17#include <linux/sctp.h>
18#include <linux/vermagic.h>
19#include <net/gre.h>
e2ee1c5a 20#include <net/ip6_checksum.h>
30d240df 21#include <net/pkt_cls.h>
a6d53b97 22#include <net/tcp.h>
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23#include <net/vxlan.h>
24
25#include "hnae3.h"
26#include "hns3_enet.h"
27
cde4ffad 28#define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
5f543a54 29#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 30
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31#define hns3_rl_err(fmt, ...) \
32 do { \
33 if (net_ratelimit()) \
34 netdev_err(fmt, ##__VA_ARGS__); \
35 } while (0)
36
f96315f2 37static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
f05e2109 38static void hns3_remove_hw_addr(struct net_device *netdev);
7b763f3f 39
1db9b1bf 40static const char hns3_driver_name[] = "hns3";
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41const char hns3_driver_version[] = VERMAGIC_STRING;
42static const char hns3_driver_string[] =
43 "Hisilicon Ethernet Network Driver for Hip08 Family";
44static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
45static struct hnae3_client client;
46
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YL
47static int debug = -1;
48module_param(debug, int, 0);
49MODULE_PARM_DESC(debug, " Network interface message level setting");
50
51#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
52 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
53
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54#define HNS3_INNER_VLAN_TAG 1
55#define HNS3_OUTER_VLAN_TAG 2
56
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57/* hns3_pci_tbl - PCI Device ID Table
58 *
59 * Last entry must be all 0s
60 *
61 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
62 * Class, Class Mask, private data (not used) }
63 */
64static const struct pci_device_id hns3_pci_tbl[] = {
65 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
66 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 67 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 68 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 69 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 70 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 72 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 74 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 76 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
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78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
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80 /* required last entry */
81 {0, }
82};
83MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
84
ef0c5009 85static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 86{
ef0c5009 87 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 88
fb00331b 89 napi_schedule_irqoff(&tqp_vector->napi);
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S
90
91 return IRQ_HANDLED;
92}
93
94static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
95{
96 struct hns3_enet_tqp_vector *tqp_vectors;
97 unsigned int i;
98
99 for (i = 0; i < priv->vector_num; i++) {
100 tqp_vectors = &priv->tqp_vector[i];
101
102 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
103 continue;
104
ffab9691 105 /* clear the affinity mask */
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PL
106 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
107
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108 /* release the irq resource */
109 free_irq(tqp_vectors->vector_irq, tqp_vectors);
110 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
111 }
112}
113
114static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
115{
116 struct hns3_enet_tqp_vector *tqp_vectors;
117 int txrx_int_idx = 0;
118 int rx_int_idx = 0;
119 int tx_int_idx = 0;
120 unsigned int i;
121 int ret;
122
123 for (i = 0; i < priv->vector_num; i++) {
124 tqp_vectors = &priv->tqp_vector[i];
125
126 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
127 continue;
128
129 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
130 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
131 "%s-%s-%d", priv->netdev->name, "TxRx",
132 txrx_int_idx++);
133 txrx_int_idx++;
134 } else if (tqp_vectors->rx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
136 "%s-%s-%d", priv->netdev->name, "Rx",
137 rx_int_idx++);
138 } else if (tqp_vectors->tx_group.ring) {
139 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
140 "%s-%s-%d", priv->netdev->name, "Tx",
141 tx_int_idx++);
142 } else {
143 /* Skip this unused q_vector */
144 continue;
145 }
146
147 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
148
149 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
9b2f3477 150 tqp_vectors->name, tqp_vectors);
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151 if (ret) {
152 netdev_err(priv->netdev, "request irq(%d) fail\n",
153 tqp_vectors->vector_irq);
d547ecdc 154 hns3_nic_uninit_irq(priv);
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155 return ret;
156 }
157
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158 irq_set_affinity_hint(tqp_vectors->vector_irq,
159 &tqp_vectors->affinity_mask);
160
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161 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
162 }
163
164 return 0;
165}
166
167static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
168 u32 mask_en)
169{
170 writel(mask_en, tqp_vector->mask_addr);
171}
172
173static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
174{
175 napi_enable(&tqp_vector->napi);
176
177 /* enable vector */
178 hns3_mask_vector_irq(tqp_vector, 1);
179}
180
181static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
182{
183 /* disable vector */
184 hns3_mask_vector_irq(tqp_vector, 0);
185
186 disable_irq(tqp_vector->vector_irq);
187 napi_disable(&tqp_vector->napi);
188}
189
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190void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
191 u32 rl_value)
76ad4f0e 192{
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FL
193 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
194
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195 /* this defines the configuration for RL (Interrupt Rate Limiter).
196 * Rl defines rate of interrupts i.e. number of interrupts-per-second
197 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
198 */
434776a5 199
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200 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
201 !tqp_vector->rx_group.coal.gl_adapt_enable)
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FL
202 /* According to the hardware, the range of rl_reg is
203 * 0-59 and the unit is 4.
204 */
205 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
206
207 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
208}
209
210void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
211 u32 gl_value)
212{
213 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
214
215 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
216}
217
218void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
219 u32 gl_value)
220{
221 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
222
223 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S
224}
225
5fd4789a
FL
226static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
227 struct hns3_nic_priv *priv)
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228{
229 /* initialize the configuration for interrupt coalescing.
230 * 1. GL (Interrupt Gap Limiter)
231 * 2. RL (Interrupt Rate Limiter)
46ee7350
GL
232 *
233 * Default: enable interrupt coalescing self-adaptive and GL
76ad4f0e 234 */
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235 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
236 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 237
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238 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
239 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 240
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YL
241 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
242 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
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243}
244
dd38c726
YL
245static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
246 struct hns3_nic_priv *priv)
247{
248 struct hnae3_handle *h = priv->ae_handle;
249
250 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 251 tqp_vector->tx_group.coal.int_gl);
dd38c726 252 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 253 tqp_vector->rx_group.coal.int_gl);
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254 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
255}
256
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257static int hns3_nic_set_real_num_queue(struct net_device *netdev)
258{
9780cb97 259 struct hnae3_handle *h = hns3_get_handle(netdev);
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YL
260 struct hnae3_knic_private_info *kinfo = &h->kinfo;
261 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
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YL
262 int i, ret;
263
264 if (kinfo->num_tc <= 1) {
265 netdev_reset_tc(netdev);
266 } else {
267 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
268 if (ret) {
269 netdev_err(netdev,
270 "netdev_set_num_tc fail, ret=%d!\n", ret);
271 return ret;
272 }
273
274 for (i = 0; i < HNAE3_MAX_TC; i++) {
275 if (!kinfo->tc_info[i].enable)
276 continue;
277
278 netdev_set_tc_queue(netdev,
279 kinfo->tc_info[i].tc,
280 kinfo->tc_info[i].tqp_count,
281 kinfo->tc_info[i].tqp_offset);
282 }
283 }
9df8f79a
YL
284
285 ret = netif_set_real_num_tx_queues(netdev, queue_size);
286 if (ret) {
287 netdev_err(netdev,
9b2f3477 288 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
9df8f79a
YL
289 return ret;
290 }
291
292 ret = netif_set_real_num_rx_queues(netdev, queue_size);
293 if (ret) {
294 netdev_err(netdev,
295 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
296 return ret;
297 }
298
299 return 0;
300}
301
678335a1
PL
302static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
303{
0d43bf45 304 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 305
0d43bf45
HT
306 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
307 rss_size = alloc_tqps / h->kinfo.num_tc;
678335a1 308
0d43bf45 309 return min_t(u16, rss_size, max_rss_size);
678335a1
PL
310}
311
8df0fa91
HT
312static void hns3_tqp_enable(struct hnae3_queue *tqp)
313{
314 u32 rcb_reg;
315
316 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
317 rcb_reg |= BIT(HNS3_RING_EN_B);
318 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
319}
320
321static void hns3_tqp_disable(struct hnae3_queue *tqp)
322{
323 u32 rcb_reg;
324
325 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
326 rcb_reg &= ~BIT(HNS3_RING_EN_B);
327 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
328}
329
ffab9691
JS
330static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
331{
332#ifdef CONFIG_RFS_ACCEL
333 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
334 netdev->rx_cpu_rmap = NULL;
335#endif
336}
337
338static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
339{
340#ifdef CONFIG_RFS_ACCEL
341 struct hns3_nic_priv *priv = netdev_priv(netdev);
342 struct hns3_enet_tqp_vector *tqp_vector;
343 int i, ret;
344
345 if (!netdev->rx_cpu_rmap) {
346 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
347 if (!netdev->rx_cpu_rmap)
348 return -ENOMEM;
349 }
350
351 for (i = 0; i < priv->vector_num; i++) {
352 tqp_vector = &priv->tqp_vector[i];
353 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
354 tqp_vector->vector_irq);
355 if (ret) {
356 hns3_free_rx_cpu_rmap(netdev);
357 return ret;
358 }
359 }
360#endif
361 return 0;
362}
363
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S
364static int hns3_nic_net_up(struct net_device *netdev)
365{
366 struct hns3_nic_priv *priv = netdev_priv(netdev);
367 struct hnae3_handle *h = priv->ae_handle;
368 int i, j;
369 int ret;
370
7b763f3f
FL
371 ret = hns3_nic_reset_all_ring(h);
372 if (ret)
373 return ret;
374
ffab9691
JS
375 /* the device can work without cpu rmap, only aRFS needs it */
376 ret = hns3_set_rx_cpu_rmap(netdev);
377 if (ret)
378 netdev_warn(netdev, "set rx cpu rmap fail, ret=%d!\n", ret);
379
76ad4f0e
S
380 /* get irq resource for all vectors */
381 ret = hns3_nic_init_irq(priv);
382 if (ret) {
9b2f3477 383 netdev_err(netdev, "init irq failed! ret=%d\n", ret);
ffab9691 384 goto free_rmap;
76ad4f0e
S
385 }
386
b7b585c2
JS
387 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
388
76ad4f0e
S
389 /* enable the vectors */
390 for (i = 0; i < priv->vector_num; i++)
391 hns3_vector_enable(&priv->tqp_vector[i]);
392
8df0fa91
HT
393 /* enable rcb */
394 for (j = 0; j < h->kinfo.num_tqps; j++)
395 hns3_tqp_enable(h->kinfo.tqp[j]);
396
76ad4f0e
S
397 /* start the ae_dev */
398 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
399 if (ret)
400 goto out_start_err;
401
402 return 0;
403
404out_start_err:
b7b585c2 405 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
8df0fa91
HT
406 while (j--)
407 hns3_tqp_disable(h->kinfo.tqp[j]);
408
76ad4f0e
S
409 for (j = i - 1; j >= 0; j--)
410 hns3_vector_disable(&priv->tqp_vector[j]);
411
412 hns3_nic_uninit_irq(priv);
ffab9691
JS
413free_rmap:
414 hns3_free_rx_cpu_rmap(netdev);
76ad4f0e
S
415 return ret;
416}
417
2a73ac3e
YL
418static void hns3_config_xps(struct hns3_nic_priv *priv)
419{
420 int i;
421
422 for (i = 0; i < priv->vector_num; i++) {
423 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
424 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
425
426 while (ring) {
427 int ret;
428
429 ret = netif_set_xps_queue(priv->netdev,
430 &tqp_vector->affinity_mask,
431 ring->tqp->tqp_index);
432 if (ret)
433 netdev_warn(priv->netdev,
434 "set xps queue failed: %d", ret);
435
436 ring = ring->next;
437 }
438 }
439}
440
76ad4f0e
S
441static int hns3_nic_net_open(struct net_device *netdev)
442{
8cdb992f 443 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL
444 struct hnae3_handle *h = hns3_get_handle(netdev);
445 struct hnae3_knic_private_info *kinfo;
446 int i, ret;
76ad4f0e 447
257e4f29
HT
448 if (hns3_nic_resetting(netdev))
449 return -EBUSY;
450
76ad4f0e
S
451 netif_carrier_off(netdev);
452
9df8f79a
YL
453 ret = hns3_nic_set_real_num_queue(netdev);
454 if (ret)
76ad4f0e 455 return ret;
76ad4f0e
S
456
457 ret = hns3_nic_net_up(netdev);
458 if (ret) {
9b2f3477 459 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
76ad4f0e
S
460 return ret;
461 }
462
a75a8efa 463 kinfo = &h->kinfo;
9b2f3477
WL
464 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
465 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
a75a8efa 466
8cdb992f
JS
467 if (h->ae_algo->ops->set_timer_task)
468 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
469
2a73ac3e 470 hns3_config_xps(priv);
1c822948
YL
471
472 netif_dbg(h, drv, netdev, "net open\n");
473
76ad4f0e
S
474 return 0;
475}
476
f96315f2
HT
477static void hns3_reset_tx_queue(struct hnae3_handle *h)
478{
479 struct net_device *ndev = h->kinfo.netdev;
480 struct hns3_nic_priv *priv = netdev_priv(ndev);
481 struct netdev_queue *dev_queue;
482 u32 i;
483
484 for (i = 0; i < h->kinfo.num_tqps; i++) {
485 dev_queue = netdev_get_tx_queue(ndev,
5f06b903 486 priv->ring[i].queue_index);
f96315f2
HT
487 netdev_tx_reset_queue(dev_queue);
488 }
489}
490
76ad4f0e
S
491static void hns3_nic_net_down(struct net_device *netdev)
492{
493 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 494 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
495 const struct hnae3_ae_ops *ops;
496 int i;
497
7b763f3f
FL
498 /* disable vectors */
499 for (i = 0; i < priv->vector_num; i++)
500 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT
501
502 /* disable rcb */
503 for (i = 0; i < h->kinfo.num_tqps; i++)
504 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 505
76ad4f0e
S
506 /* stop ae_dev */
507 ops = priv->ae_handle->ae_algo->ops;
508 if (ops->stop)
509 ops->stop(priv->ae_handle);
510
ffab9691
JS
511 hns3_free_rx_cpu_rmap(netdev);
512
76ad4f0e
S
513 /* free irq resources */
514 hns3_nic_uninit_irq(priv);
7b763f3f 515
3a30964a
YL
516 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
517 * during reset process, because driver may not be able
518 * to disable the ring through firmware when downing the netdev.
519 */
520 if (!hns3_nic_resetting(netdev))
f96315f2
HT
521 hns3_clear_all_ring(priv->ae_handle, false);
522
523 hns3_reset_tx_queue(priv->ae_handle);
76ad4f0e
S
524}
525
526static int hns3_nic_net_stop(struct net_device *netdev)
527{
ff0699e0 528 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 529 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT
530
531 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
532 return 0;
533
1c822948
YL
534 netif_dbg(h, drv, netdev, "net stop\n");
535
8cdb992f
JS
536 if (h->ae_algo->ops->set_timer_task)
537 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
538
76ad4f0e
S
539 netif_tx_stop_all_queues(netdev);
540 netif_carrier_off(netdev);
541
542 hns3_nic_net_down(netdev);
543
544 return 0;
545}
546
76ad4f0e
S
547static int hns3_nic_uc_sync(struct net_device *netdev,
548 const unsigned char *addr)
549{
9780cb97 550 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
551
552 if (h->ae_algo->ops->add_uc_addr)
553 return h->ae_algo->ops->add_uc_addr(h, addr);
554
555 return 0;
556}
557
558static int hns3_nic_uc_unsync(struct net_device *netdev,
559 const unsigned char *addr)
560{
9780cb97 561 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
562
563 if (h->ae_algo->ops->rm_uc_addr)
564 return h->ae_algo->ops->rm_uc_addr(h, addr);
565
566 return 0;
567}
568
569static int hns3_nic_mc_sync(struct net_device *netdev,
570 const unsigned char *addr)
571{
9780cb97 572 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 573
720a8478 574 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S
575 return h->ae_algo->ops->add_mc_addr(h, addr);
576
577 return 0;
578}
579
580static int hns3_nic_mc_unsync(struct net_device *netdev,
581 const unsigned char *addr)
582{
9780cb97 583 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 584
720a8478 585 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S
586 return h->ae_algo->ops->rm_mc_addr(h, addr);
587
588 return 0;
589}
590
c60edc17
JS
591static u8 hns3_get_netdev_flags(struct net_device *netdev)
592{
593 u8 flags = 0;
594
595 if (netdev->flags & IFF_PROMISC) {
28673b33 596 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
c60edc17
JS
597 } else {
598 flags |= HNAE3_VLAN_FLTR;
599 if (netdev->flags & IFF_ALLMULTI)
600 flags |= HNAE3_USER_MPE;
601 }
602
603 return flags;
604}
605
1db9b1bf 606static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 607{
9780cb97 608 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17
JS
609 u8 new_flags;
610 int ret;
76ad4f0e 611
c60edc17
JS
612 new_flags = hns3_get_netdev_flags(netdev);
613
614 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
615 if (ret) {
76ad4f0e 616 netdev_err(netdev, "sync uc address fail\n");
c60edc17
JS
617 if (ret == -ENOSPC)
618 new_flags |= HNAE3_OVERFLOW_UPE;
619 }
620
40cca1c5 621 if (netdev->flags & IFF_MULTICAST) {
c60edc17
JS
622 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
623 hns3_nic_mc_unsync);
624 if (ret) {
76ad4f0e 625 netdev_err(netdev, "sync mc address fail\n");
c60edc17
JS
626 if (ret == -ENOSPC)
627 new_flags |= HNAE3_OVERFLOW_MPE;
628 }
629 }
630
c60edc17
JS
631 /* User mode Promisc mode enable and vlan filtering is disabled to
632 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
633 * vlan fitering is enabled
634 */
635 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
636 h->netdev_flags = new_flags;
28673b33 637 hns3_update_promisc_mode(netdev, new_flags);
c60edc17
JS
638}
639
7fa6be4f 640int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
c60edc17
JS
641{
642 struct hns3_nic_priv *priv = netdev_priv(netdev);
643 struct hnae3_handle *h = priv->ae_handle;
644
645 if (h->ae_algo->ops->set_promisc_mode) {
7fa6be4f
HT
646 return h->ae_algo->ops->set_promisc_mode(h,
647 promisc_flags & HNAE3_UPE,
648 promisc_flags & HNAE3_MPE);
c60edc17 649 }
7fa6be4f
HT
650
651 return 0;
c60edc17
JS
652}
653
654void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
655{
656 struct hns3_nic_priv *priv = netdev_priv(netdev);
657 struct hnae3_handle *h = priv->ae_handle;
658 bool last_state;
659
660 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
661 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
662 if (enable != last_state) {
663 netdev_info(netdev,
664 "%s vlan filter\n",
665 enable ? "enable" : "disable");
666 h->ae_algo->ops->enable_vlan_filter(h, enable);
667 }
40cca1c5 668 }
76ad4f0e
S
669}
670
671static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
672 u16 *mss, u32 *type_cs_vlan_tso)
673{
674 u32 l4_offset, hdr_len;
675 union l3_hdr_info l3;
676 union l4_hdr_info l4;
677 u32 l4_paylen;
678 int ret;
679
680 if (!skb_is_gso(skb))
681 return 0;
682
683 ret = skb_cow_head(skb, 0);
8ae10cfb 684 if (unlikely(ret < 0))
76ad4f0e
S
685 return ret;
686
687 l3.hdr = skb_network_header(skb);
688 l4.hdr = skb_transport_header(skb);
689
690 /* Software should clear the IPv4's checksum field when tso is
691 * needed.
692 */
693 if (l3.v4->version == 4)
694 l3.v4->check = 0;
695
9b2f3477 696 /* tunnel packet */
76ad4f0e
S
697 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
698 SKB_GSO_GRE_CSUM |
699 SKB_GSO_UDP_TUNNEL |
700 SKB_GSO_UDP_TUNNEL_CSUM)) {
701 if ((!(skb_shinfo(skb)->gso_type &
702 SKB_GSO_PARTIAL)) &&
703 (skb_shinfo(skb)->gso_type &
704 SKB_GSO_UDP_TUNNEL_CSUM)) {
705 /* Software should clear the udp's checksum
706 * field when tso is needed.
707 */
708 l4.udp->check = 0;
709 }
710 /* reset l3&l4 pointers from outer to inner headers */
711 l3.hdr = skb_inner_network_header(skb);
712 l4.hdr = skb_inner_transport_header(skb);
713
714 /* Software should clear the IPv4's checksum field when
715 * tso is needed.
716 */
717 if (l3.v4->version == 4)
718 l3.v4->check = 0;
719 }
720
9b2f3477 721 /* normal or tunnel packet */
76ad4f0e 722 l4_offset = l4.hdr - skb->data;
3fe13ed9 723 hdr_len = (l4.tcp->doff << 2) + l4_offset;
76ad4f0e 724
9b2f3477 725 /* remove payload length from inner pseudo checksum when tso */
76ad4f0e
S
726 l4_paylen = skb->len - l4_offset;
727 csum_replace_by_diff(&l4.tcp->check,
728 (__force __wsum)htonl(l4_paylen));
729
730 /* find the txbd field values */
731 *paylen = skb->len - hdr_len;
cde4ffad 732 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e
S
733
734 /* get MSS for TSO */
735 *mss = skb_shinfo(skb)->gso_size;
736
737 return 0;
738}
739
1898d4e4
S
740static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
741 u8 *il4_proto)
76ad4f0e 742{
1a6e552d 743 union l3_hdr_info l3;
76ad4f0e
S
744 unsigned char *l4_hdr;
745 unsigned char *exthdr;
746 u8 l4_proto_tmp;
747 __be16 frag_off;
748
749 /* find outer header point */
750 l3.hdr = skb_network_header(skb);
35f58fd7 751 l4_hdr = skb_transport_header(skb);
76ad4f0e
S
752
753 if (skb->protocol == htons(ETH_P_IPV6)) {
754 exthdr = l3.hdr + sizeof(*l3.v6);
755 l4_proto_tmp = l3.v6->nexthdr;
756 if (l4_hdr != exthdr)
757 ipv6_skip_exthdr(skb, exthdr - skb->data,
758 &l4_proto_tmp, &frag_off);
759 } else if (skb->protocol == htons(ETH_P_IP)) {
760 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S
761 } else {
762 return -EINVAL;
76ad4f0e
S
763 }
764
765 *ol4_proto = l4_proto_tmp;
766
767 /* tunnel packet */
768 if (!skb->encapsulation) {
769 *il4_proto = 0;
1898d4e4 770 return 0;
76ad4f0e
S
771 }
772
773 /* find inner header point */
774 l3.hdr = skb_inner_network_header(skb);
775 l4_hdr = skb_inner_transport_header(skb);
776
777 if (l3.v6->version == 6) {
778 exthdr = l3.hdr + sizeof(*l3.v6);
779 l4_proto_tmp = l3.v6->nexthdr;
780 if (l4_hdr != exthdr)
781 ipv6_skip_exthdr(skb, exthdr - skb->data,
782 &l4_proto_tmp, &frag_off);
783 } else if (l3.v4->version == 4) {
784 l4_proto_tmp = l3.v4->protocol;
785 }
786
787 *il4_proto = l4_proto_tmp;
1898d4e4
S
788
789 return 0;
76ad4f0e
S
790}
791
3db084d2
YL
792/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
793 * and it is udp packet, which has a dest port as the IANA assigned.
794 * the hardware is expected to do the checksum offload, but the
795 * hardware will not do the checksum offload when udp dest port is
796 * 4789.
797 */
798static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
799{
1a6e552d 800 union l4_hdr_info l4;
3db084d2
YL
801
802 l4.hdr = skb_transport_header(skb);
803
bea96410
MS
804 if (!(!skb->encapsulation &&
805 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
3db084d2
YL
806 return false;
807
808 skb_checksum_help(skb);
809
810 return true;
811}
812
757cd1e4
YL
813static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
814 u32 *ol_type_vlan_len_msec)
76ad4f0e 815{
757cd1e4
YL
816 u32 l2_len, l3_len, l4_len;
817 unsigned char *il2_hdr;
1a6e552d 818 union l3_hdr_info l3;
757cd1e4 819 union l4_hdr_info l4;
76ad4f0e
S
820
821 l3.hdr = skb_network_header(skb);
757cd1e4 822 l4.hdr = skb_transport_header(skb);
76ad4f0e 823
757cd1e4
YL
824 /* compute OL2 header size, defined in 2 Bytes */
825 l2_len = l3.hdr - skb->data;
826 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
827
828 /* compute OL3 header size, defined in 4 Bytes */
829 l3_len = l4.hdr - l3.hdr;
830 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 831
757cd1e4 832 il2_hdr = skb_inner_mac_header(skb);
9b2f3477 833 /* compute OL4 header size, defined in 4 Bytes */
757cd1e4
YL
834 l4_len = il2_hdr - l4.hdr;
835 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
836
837 /* define outer network header type */
838 if (skb->protocol == htons(ETH_P_IP)) {
839 if (skb_is_gso(skb))
cde4ffad 840 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL
841 HNS3_TXD_OL3T_S,
842 HNS3_OL3T_IPV4_CSUM);
843 else
cde4ffad 844 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL
845 HNS3_TXD_OL3T_S,
846 HNS3_OL3T_IPV4_NO_CSUM);
847
848 } else if (skb->protocol == htons(ETH_P_IPV6)) {
849 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
850 HNS3_OL3T_IPV6);
851 }
852
853 if (ol4_proto == IPPROTO_UDP)
854 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
855 HNS3_TUN_MAC_IN_UDP);
856 else if (ol4_proto == IPPROTO_GRE)
857 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
858 HNS3_TUN_NVGRE);
859}
860
861static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
862 u8 il4_proto, u32 *type_cs_vlan_tso,
863 u32 *ol_type_vlan_len_msec)
864{
c264ed44 865 unsigned char *l2_hdr = skb->data;
757cd1e4
YL
866 u32 l4_proto = ol4_proto;
867 union l4_hdr_info l4;
868 union l3_hdr_info l3;
869 u32 l2_len, l3_len;
870
871 l4.hdr = skb_transport_header(skb);
872 l3.hdr = skb_network_header(skb);
873
874 /* handle encapsulation skb */
875 if (skb->encapsulation) {
876 /* If this is a not UDP/GRE encapsulation skb */
877 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S
878 /* drop the skb tunnel packet if hardware don't support,
879 * because hardware can't calculate csum when TSO.
880 */
881 if (skb_is_gso(skb))
882 return -EDOM;
883
884 /* the stack computes the IP header already,
885 * driver calculate l4 checksum when not TSO.
886 */
887 skb_checksum_help(skb);
888 return 0;
889 }
890
757cd1e4
YL
891 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
892
893 /* switch to inner header */
894 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 895 l3.hdr = skb_inner_network_header(skb);
757cd1e4 896 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S
897 l4_proto = il4_proto;
898 }
899
900 if (l3.v4->version == 4) {
cde4ffad
YL
901 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
902 HNS3_L3T_IPV4);
76ad4f0e
S
903
904 /* the stack computes the IP header already, the only time we
905 * need the hardware to recompute it is in the case of TSO.
906 */
907 if (skb_is_gso(skb))
cde4ffad 908 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 909 } else if (l3.v6->version == 6) {
cde4ffad
YL
910 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
911 HNS3_L3T_IPV6);
76ad4f0e
S
912 }
913
757cd1e4
YL
914 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
915 l2_len = l3.hdr - l2_hdr;
916 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
917
918 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
919 l3_len = l4.hdr - l3.hdr;
920 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
921
922 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S
923 switch (l4_proto) {
924 case IPPROTO_TCP:
cde4ffad
YL
925 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
926 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
927 HNS3_L4T_TCP);
757cd1e4
YL
928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
929 l4.tcp->doff);
76ad4f0e
S
930 break;
931 case IPPROTO_UDP:
3db084d2
YL
932 if (hns3_tunnel_csum_bug(skb))
933 break;
934
cde4ffad
YL
935 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
936 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
937 HNS3_L4T_UDP);
757cd1e4
YL
938 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
939 (sizeof(struct udphdr) >> 2));
76ad4f0e
S
940 break;
941 case IPPROTO_SCTP:
cde4ffad
YL
942 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
943 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
944 HNS3_L4T_SCTP);
757cd1e4
YL
945 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
946 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S
947 break;
948 default:
949 /* drop the skb tunnel packet if hardware don't support,
950 * because hardware can't calculate csum when TSO.
951 */
952 if (skb_is_gso(skb))
953 return -EDOM;
954
955 /* the stack computes the IP header already,
956 * driver calculate l4 checksum when not TSO.
957 */
958 skb_checksum_help(skb);
959 return 0;
960 }
961
962 return 0;
963}
964
eb977d99
YL
965static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
966 struct sk_buff *skb)
9699cffe 967{
44e626f7 968 struct hnae3_handle *handle = tx_ring->tqp->handle;
eb977d99
YL
969 struct vlan_ethhdr *vhdr;
970 int rc;
971
972 if (!(skb->protocol == htons(ETH_P_8021Q) ||
973 skb_vlan_tag_present(skb)))
974 return 0;
44e626f7
JS
975
976 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
977 * header is allowed in skb, otherwise it will cause RAS error.
978 */
979 if (unlikely(skb_vlan_tagged_multi(skb) &&
980 handle->port_base_vlan_state ==
981 HNAE3_PORT_BASE_VLAN_ENABLE))
982 return -EINVAL;
983
9699cffe 984 if (skb->protocol == htons(ETH_P_8021Q) &&
eb977d99 985 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
9699cffe
PL
986 /* When HW VLAN acceleration is turned off, and the stack
987 * sets the protocol to 802.1q, the driver just need to
988 * set the protocol to the encapsulated ethertype.
989 */
990 skb->protocol = vlan_get_protocol(skb);
991 return 0;
992 }
993
994 if (skb_vlan_tag_present(skb)) {
9699cffe
PL
995 /* Based on hw strategy, use out_vtag in two layer tag case,
996 * and use inner_vtag in one tag case.
997 */
eb977d99
YL
998 if (skb->protocol == htons(ETH_P_8021Q) &&
999 handle->port_base_vlan_state ==
1000 HNAE3_PORT_BASE_VLAN_DISABLE)
1001 rc = HNS3_OUTER_VLAN_TAG;
1002 else
1003 rc = HNS3_INNER_VLAN_TAG;
1004
1005 skb->protocol = vlan_get_protocol(skb);
1006 return rc;
9699cffe
PL
1007 }
1008
eb977d99
YL
1009 rc = skb_cow_head(skb, 0);
1010 if (unlikely(rc < 0))
1011 return rc;
1012
1013 vhdr = (struct vlan_ethhdr *)skb->data;
1014 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1015 & VLAN_PRIO_MASK);
1016
9699cffe
PL
1017 skb->protocol = vlan_get_protocol(skb);
1018 return 0;
1019}
1020
eb977d99
YL
1021static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1022 struct sk_buff *skb, struct hns3_desc *desc)
1023{
1024 u32 ol_type_vlan_len_msec = 0;
1025 u32 type_cs_vlan_tso = 0;
1026 u32 paylen = skb->len;
1027 u16 inner_vtag = 0;
1028 u16 out_vtag = 0;
1029 u16 mss = 0;
1030 int ret;
1031
1032 ret = hns3_handle_vtags(ring, skb);
1033 if (unlikely(ret < 0)) {
b20d7fe5
YL
1034 u64_stats_update_begin(&ring->syncp);
1035 ring->stats.tx_vlan_err++;
1036 u64_stats_update_end(&ring->syncp);
eb977d99
YL
1037 return ret;
1038 } else if (ret == HNS3_INNER_VLAN_TAG) {
1039 inner_vtag = skb_vlan_tag_get(skb);
1040 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1041 VLAN_PRIO_MASK;
1042 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1043 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1044 out_vtag = skb_vlan_tag_get(skb);
1045 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1046 VLAN_PRIO_MASK;
1047 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1048 1);
1049 }
1050
1051 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1052 u8 ol4_proto, il4_proto;
1053
1054 skb_reset_mac_len(skb);
1055
1056 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
8ae10cfb 1057 if (unlikely(ret < 0)) {
b20d7fe5
YL
1058 u64_stats_update_begin(&ring->syncp);
1059 ring->stats.tx_l4_proto_err++;
1060 u64_stats_update_end(&ring->syncp);
eb977d99 1061 return ret;
b20d7fe5 1062 }
eb977d99
YL
1063
1064 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1065 &type_cs_vlan_tso,
1066 &ol_type_vlan_len_msec);
8ae10cfb 1067 if (unlikely(ret < 0)) {
b20d7fe5
YL
1068 u64_stats_update_begin(&ring->syncp);
1069 ring->stats.tx_l2l3l4_err++;
1070 u64_stats_update_end(&ring->syncp);
eb977d99 1071 return ret;
b20d7fe5 1072 }
eb977d99
YL
1073
1074 ret = hns3_set_tso(skb, &paylen, &mss,
1075 &type_cs_vlan_tso);
8ae10cfb 1076 if (unlikely(ret < 0)) {
b20d7fe5
YL
1077 u64_stats_update_begin(&ring->syncp);
1078 ring->stats.tx_tso_err++;
1079 u64_stats_update_end(&ring->syncp);
eb977d99 1080 return ret;
b20d7fe5 1081 }
eb977d99
YL
1082 }
1083
1084 /* Set txbd */
1085 desc->tx.ol_type_vlan_len_msec =
1086 cpu_to_le32(ol_type_vlan_len_msec);
1087 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1088 desc->tx.paylen = cpu_to_le32(paylen);
1089 desc->tx.mss = cpu_to_le16(mss);
1090 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1091 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1092
1093 return 0;
1094}
1095
76ad4f0e 1096static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
8ae10cfb 1097 unsigned int size, enum hns_desc_type type)
76ad4f0e 1098{
8ae10cfb
YL
1099#define HNS3_LIKELY_BD_NUM 1
1100
76ad4f0e
S
1101 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1102 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1103 struct device *dev = ring_to_dev(ring);
d7840976 1104 skb_frag_t *frag;
1e8a7977 1105 unsigned int frag_buf_num;
47e7b13b 1106 int k, sizeoflast;
5188f218 1107 dma_addr_t dma;
76ad4f0e 1108
76ad4f0e 1109 if (type == DESC_TYPE_SKB) {
47e7b13b 1110 struct sk_buff *skb = (struct sk_buff *)priv;
47e7b13b 1111 int ret;
76ad4f0e 1112
eb977d99 1113 ret = hns3_fill_skb_desc(ring, skb, desc);
8ae10cfb 1114 if (unlikely(ret < 0))
9699cffe
PL
1115 return ret;
1116
5188f218
PL
1117 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1118 } else {
d7840976 1119 frag = (skb_frag_t *)priv;
5188f218
PL
1120 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1121 }
1122
845e0d1d 1123 if (unlikely(dma_mapping_error(dev, dma))) {
b20d7fe5 1124 u64_stats_update_begin(&ring->syncp);
5188f218 1125 ring->stats.sw_err_cnt++;
b20d7fe5 1126 u64_stats_update_end(&ring->syncp);
5188f218 1127 return -ENOMEM;
76ad4f0e
S
1128 }
1129
bcdb12b7
FL
1130 desc_cb->length = size;
1131
ceca4a5e 1132 if (likely(size <= HNS3_MAX_BD_SIZE)) {
ceca4a5e
YL
1133 desc_cb->priv = priv;
1134 desc_cb->dma = dma;
1135 desc_cb->type = type;
1136 desc->addr = cpu_to_le64(dma);
1137 desc->tx.send_size = cpu_to_le16(size);
ceca4a5e 1138 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1139 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
ceca4a5e
YL
1140
1141 ring_ptr_move_fw(ring, next_to_use);
8ae10cfb 1142 return HNS3_LIKELY_BD_NUM;
ceca4a5e
YL
1143 }
1144
5f543a54 1145 frag_buf_num = hns3_tx_bd_count(size);
3fe13ed9 1146 sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1e8a7977
FL
1147 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1148
1149 /* When frag size is bigger than hardware limit, split this frag */
1150 for (k = 0; k < frag_buf_num; k++) {
1151 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1152 desc_cb->priv = priv;
1e8a7977
FL
1153 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1154 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
9b2f3477 1155 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1e8a7977
FL
1156
1157 /* now, fill the descriptor */
1158 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7 1159 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
9b2f3477 1160 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977 1161 desc->tx.bdtp_fe_sc_vld_ra_ri =
8ae10cfb 1162 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1e8a7977 1163
9b2f3477 1164 /* move ring pointer to next */
1e8a7977
FL
1165 ring_ptr_move_fw(ring, next_to_use);
1166
1167 desc_cb = &ring->desc_cb[ring->next_to_use];
1168 desc = &ring->desc[ring->next_to_use];
1169 }
76ad4f0e 1170
8ae10cfb 1171 return frag_buf_num;
76ad4f0e
S
1172}
1173
8ae10cfb
YL
1174static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1175 unsigned int bd_num)
76ad4f0e 1176{
8ae10cfb 1177 unsigned int size;
42611b70 1178 int i;
76ad4f0e 1179
8ae10cfb
YL
1180 size = skb_headlen(skb);
1181 while (size > HNS3_MAX_BD_SIZE) {
1182 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1183 size -= HNS3_MAX_BD_SIZE;
1184
1185 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1186 return bd_num;
1187 }
76ad4f0e 1188
8ae10cfb
YL
1189 if (size) {
1190 bd_size[bd_num++] = size;
1191 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1192 return bd_num;
1193 }
76ad4f0e 1194
3d5f3741 1195 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
d7840976 1196 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8ae10cfb
YL
1197 size = skb_frag_size(frag);
1198 if (!size)
1199 continue;
1200
1201 while (size > HNS3_MAX_BD_SIZE) {
1202 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1203 size -= HNS3_MAX_BD_SIZE;
1204
1205 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1206 return bd_num;
1207 }
1208
1209 bd_size[bd_num++] = size;
1210 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1211 return bd_num;
1212 }
1213
1214 return bd_num;
1215}
1216
1217static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1218{
1219 struct sk_buff *frag_skb;
1220 unsigned int bd_num = 0;
1221
1222 /* If the total len is within the max bd limit */
1223 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1224 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1225 return skb_shinfo(skb)->nr_frags + 1U;
1226
1227 /* The below case will always be linearized, return
1228 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1229 */
1230 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1231 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1232 return HNS3_MAX_TSO_BD_NUM + 1U;
1233
1234 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1235
1236 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1237 return bd_num;
1238
1239 skb_walk_frags(skb, frag_skb) {
1240 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1241 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1242 return bd_num;
3d5f3741 1243 }
76ad4f0e 1244
3d5f3741 1245 return bd_num;
76ad4f0e
S
1246}
1247
db4970aa
YL
1248static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1249{
1250 if (!skb->encapsulation)
1251 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1252
1253 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1254}
1255
1256/* HW need every continuous 8 buffer data to be larger than MSS,
1257 * we simplify it by ensuring skb_headlen + the first continuous
1258 * 7 frags to to be larger than gso header len + mss, and the remaining
1259 * continuous 7 frags to be larger than MSS except the last 7 frags.
1260 */
8ae10cfb
YL
1261static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1262 unsigned int bd_num)
db4970aa 1263{
db4970aa
YL
1264 unsigned int tot_len = 0;
1265 int i;
1266
8ae10cfb
YL
1267 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1268 tot_len += bd_size[i];
db4970aa 1269
8ae10cfb
YL
1270 /* ensure the first 8 frags is greater than mss + header */
1271 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1272 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
db4970aa
YL
1273 return true;
1274
8ae10cfb
YL
1275 /* ensure every continuous 7 buffer is greater than mss
1276 * except the last one.
1277 */
1278 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1279 tot_len -= bd_size[i];
1280 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
db4970aa
YL
1281
1282 if (tot_len < skb_shinfo(skb)->gso_size)
1283 return true;
1284 }
1285
1286 return false;
1287}
1288
3d5f3741
YL
1289static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1290 struct sk_buff **out_skb)
76ad4f0e 1291{
8ae10cfb 1292 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
76ad4f0e 1293 struct sk_buff *skb = *out_skb;
42611b70 1294 unsigned int bd_num;
76ad4f0e 1295
8ae10cfb
YL
1296 bd_num = hns3_tx_bd_num(skb, bd_size);
1297 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
3d5f3741 1298 struct sk_buff *new_skb;
76ad4f0e 1299
8ae10cfb
YL
1300 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1301 !hns3_skb_need_linearized(skb, bd_size, bd_num))
db4970aa
YL
1302 goto out;
1303
51e8439f
PL
1304 /* manual split the send packet */
1305 new_skb = skb_copy(skb, GFP_ATOMIC);
1306 if (!new_skb)
1307 return -ENOMEM;
1308 dev_kfree_skb_any(skb);
1309 *out_skb = new_skb;
3d5f3741 1310
8ae10cfb
YL
1311 bd_num = hns3_tx_bd_count(new_skb->len);
1312 if ((skb_is_gso(new_skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1313 (!skb_is_gso(new_skb) &&
1314 bd_num > HNS3_MAX_NON_TSO_BD_NUM))
42611b70
YL
1315 return -ENOMEM;
1316
3d5f3741
YL
1317 u64_stats_update_begin(&ring->syncp);
1318 ring->stats.tx_copy++;
1319 u64_stats_update_end(&ring->syncp);
51e8439f
PL
1320 }
1321
db4970aa 1322out:
3d5f3741 1323 if (unlikely(ring_space(ring) < bd_num))
76ad4f0e
S
1324 return -EBUSY;
1325
3d5f3741 1326 return bd_num;
76ad4f0e
S
1327}
1328
ba3f808f 1329static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S
1330{
1331 struct device *dev = ring_to_dev(ring);
1332 unsigned int i;
1333
1334 for (i = 0; i < ring->desc_num; i++) {
1335 /* check if this is where we started */
1336 if (ring->next_to_use == next_to_use_orig)
1337 break;
1338
aa9d22dd
YL
1339 /* rollback one */
1340 ring_ptr_move_bw(ring, next_to_use);
1341
76ad4f0e
S
1342 /* unmap the descriptor dma address */
1343 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1344 dma_unmap_single(dev,
1345 ring->desc_cb[ring->next_to_use].dma,
1346 ring->desc_cb[ring->next_to_use].length,
1347 DMA_TO_DEVICE);
bcdb12b7 1348 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S
1349 dma_unmap_page(dev,
1350 ring->desc_cb[ring->next_to_use].dma,
1351 ring->desc_cb[ring->next_to_use].length,
1352 DMA_TO_DEVICE);
1353
bcdb12b7 1354 ring->desc_cb[ring->next_to_use].length = 0;
aa9d22dd 1355 ring->desc_cb[ring->next_to_use].dma = 0;
76ad4f0e
S
1356 }
1357}
1358
8ae10cfb
YL
1359static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1360 struct sk_buff *skb, enum hns_desc_type type)
1361{
1362 unsigned int size = skb_headlen(skb);
1363 int i, ret, bd_num = 0;
1364
1365 if (size) {
1366 ret = hns3_fill_desc(ring, skb, size, type);
1367 if (unlikely(ret < 0))
1368 return ret;
1369
1370 bd_num += ret;
1371 }
1372
1373 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1374 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1375
1376 size = skb_frag_size(frag);
1377 if (!size)
1378 continue;
1379
1380 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1381 if (unlikely(ret < 0))
1382 return ret;
1383
1384 bd_num += ret;
1385 }
1386
1387 return bd_num;
1388}
1389
d43e5aca 1390netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S
1391{
1392 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f06b903 1393 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
76ad4f0e 1394 struct netdev_queue *dev_queue;
8ae10cfb
YL
1395 int pre_ntu, next_to_use_head;
1396 struct sk_buff *frag_skb;
1397 int bd_num = 0;
76ad4f0e 1398 int ret;
76ad4f0e
S
1399
1400 /* Prefetch the data used later */
1401 prefetch(skb->data);
1402
8ae10cfb
YL
1403 ret = hns3_nic_maybe_stop_tx(ring, &skb);
1404 if (unlikely(ret <= 0)) {
1405 if (ret == -EBUSY) {
3d5f3741
YL
1406 u64_stats_update_begin(&ring->syncp);
1407 ring->stats.tx_busy++;
1408 u64_stats_update_end(&ring->syncp);
1409 goto out_net_tx_busy;
8ae10cfb 1410 } else if (ret == -ENOMEM) {
3d5f3741
YL
1411 u64_stats_update_begin(&ring->syncp);
1412 ring->stats.sw_err_cnt++;
1413 u64_stats_update_end(&ring->syncp);
1414 }
76ad4f0e 1415
8ae10cfb 1416 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
76ad4f0e 1417 goto out_err_tx_ok;
76ad4f0e
S
1418 }
1419
76ad4f0e
S
1420 next_to_use_head = ring->next_to_use;
1421
8ae10cfb
YL
1422 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1423 if (unlikely(ret < 0))
aa9d22dd 1424 goto fill_err;
76ad4f0e 1425
8ae10cfb 1426 bd_num += ret;
5188f218 1427
8ae10cfb
YL
1428 if (!skb_has_frag_list(skb))
1429 goto out;
76ad4f0e 1430
8ae10cfb
YL
1431 skb_walk_frags(skb, frag_skb) {
1432 ret = hns3_fill_skb_to_desc(ring, frag_skb, DESC_TYPE_PAGE);
1433 if (unlikely(ret < 0))
aa9d22dd 1434 goto fill_err;
8ae10cfb
YL
1435
1436 bd_num += ret;
76ad4f0e 1437 }
8ae10cfb
YL
1438out:
1439 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1440 (ring->desc_num - 1);
1441 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1442 cpu_to_le16(BIT(HNS3_TXD_FE_B));
76ad4f0e
S
1443
1444 /* Complete translate all packets */
5f06b903 1445 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
76ad4f0e
S
1446 netdev_tx_sent_queue(dev_queue, skb->len);
1447
1448 wmb(); /* Commit all data before submit */
1449
8ae10cfb 1450 hnae3_queue_xmit(ring->tqp, bd_num);
76ad4f0e
S
1451
1452 return NETDEV_TX_OK;
1453
aa9d22dd 1454fill_err:
ba3f808f 1455 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S
1456
1457out_err_tx_ok:
1458 dev_kfree_skb_any(skb);
1459 return NETDEV_TX_OK;
1460
1461out_net_tx_busy:
5f06b903 1462 netif_stop_subqueue(netdev, ring->queue_index);
76ad4f0e
S
1463 smp_mb(); /* Commit all data before submit */
1464
1465 return NETDEV_TX_BUSY;
1466}
1467
1468static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1469{
9780cb97 1470 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
1471 struct sockaddr *mac_addr = p;
1472 int ret;
1473
1474 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1475 return -EADDRNOTAVAIL;
1476
5ec2a51e
JS
1477 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1478 netdev_info(netdev, "already using mac address %pM\n",
1479 mac_addr->sa_data);
1480 return 0;
1481 }
1482
8e6de441
HT
1483 /* For VF device, if there is a perm_addr, then the user will not
1484 * be allowed to change the address.
1485 */
1486 if (!hns3_is_phys_func(h->pdev) &&
1487 !is_zero_ether_addr(netdev->perm_addr)) {
1488 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1489 netdev->perm_addr, mac_addr->sa_data);
1490 return -EPERM;
1491 }
1492
59098055 1493 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S
1494 if (ret) {
1495 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1496 return ret;
1497 }
1498
1499 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1500
1501 return 0;
1502}
1503
26483246
XW
1504static int hns3_nic_do_ioctl(struct net_device *netdev,
1505 struct ifreq *ifr, int cmd)
1506{
1507 struct hnae3_handle *h = hns3_get_handle(netdev);
1508
1509 if (!netif_running(netdev))
1510 return -EINVAL;
1511
1512 if (!h->ae_algo->ops->do_ioctl)
1513 return -EOPNOTSUPP;
1514
1515 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1516}
1517
76ad4f0e
S
1518static int hns3_nic_set_features(struct net_device *netdev,
1519 netdev_features_t features)
1520{
181d454b 1521 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1522 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1523 struct hnae3_handle *h = priv->ae_handle;
1731be4c 1524 bool enable;
052ece6d 1525 int ret;
76ad4f0e 1526
5c9f6b39 1527 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL
1528 enable = !!(features & NETIF_F_GRO_HW);
1529 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL
1530 if (ret)
1531 return ret;
1532 }
1533
bd368416
JS
1534 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1535 h->ae_algo->ops->enable_vlan_filter) {
1731be4c
YL
1536 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
1537 h->ae_algo->ops->enable_vlan_filter(h, enable);
181d454b 1538 }
391b5e93 1539
bd368416
JS
1540 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1541 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL
1542 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1543 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL
1544 if (ret)
1545 return ret;
1546 }
1547
c17852a8 1548 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL
1549 enable = !!(features & NETIF_F_NTUPLE);
1550 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS
1551 }
1552
76ad4f0e
S
1553 netdev->features = features;
1554 return 0;
1555}
1556
6c88d9d7
PL
1557static void hns3_nic_get_stats64(struct net_device *netdev,
1558 struct rtnl_link_stats64 *stats)
76ad4f0e
S
1559{
1560 struct hns3_nic_priv *priv = netdev_priv(netdev);
1561 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1562 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 1563 struct hns3_enet_ring *ring;
d3ec4ef6
JS
1564 u64 rx_length_errors = 0;
1565 u64 rx_crc_errors = 0;
1566 u64 rx_multicast = 0;
76ad4f0e 1567 unsigned int start;
d3ec4ef6
JS
1568 u64 tx_errors = 0;
1569 u64 rx_errors = 0;
76ad4f0e
S
1570 unsigned int idx;
1571 u64 tx_bytes = 0;
1572 u64 rx_bytes = 0;
1573 u64 tx_pkts = 0;
1574 u64 rx_pkts = 0;
d2a5dca8
JS
1575 u64 tx_drop = 0;
1576 u64 rx_drop = 0;
76ad4f0e 1577
b875cc37
JS
1578 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1579 return;
1580
c5f65480
JS
1581 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1582
76ad4f0e
S
1583 for (idx = 0; idx < queue_num; idx++) {
1584 /* fetch the tx stats */
5f06b903 1585 ring = &priv->ring[idx];
76ad4f0e 1586 do {
d36d36ce 1587 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S
1588 tx_bytes += ring->stats.tx_bytes;
1589 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 1590 tx_drop += ring->stats.sw_err_cnt;
b20d7fe5
YL
1591 tx_drop += ring->stats.tx_vlan_err;
1592 tx_drop += ring->stats.tx_l4_proto_err;
1593 tx_drop += ring->stats.tx_l2l3l4_err;
1594 tx_drop += ring->stats.tx_tso_err;
d3ec4ef6 1595 tx_errors += ring->stats.sw_err_cnt;
b20d7fe5
YL
1596 tx_errors += ring->stats.tx_vlan_err;
1597 tx_errors += ring->stats.tx_l4_proto_err;
1598 tx_errors += ring->stats.tx_l2l3l4_err;
1599 tx_errors += ring->stats.tx_tso_err;
76ad4f0e
S
1600 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1601
1602 /* fetch the rx stats */
5f06b903 1603 ring = &priv->ring[idx + queue_num];
76ad4f0e 1604 do {
d36d36ce 1605 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S
1606 rx_bytes += ring->stats.rx_bytes;
1607 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 1608 rx_drop += ring->stats.l2_err;
d3ec4ef6 1609 rx_errors += ring->stats.l2_err;
8b552079 1610 rx_errors += ring->stats.l3l4_csum_err;
d3ec4ef6 1611 rx_crc_errors += ring->stats.l2_err;
d3ec4ef6
JS
1612 rx_multicast += ring->stats.rx_multicast;
1613 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S
1614 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1615 }
1616
1617 stats->tx_bytes = tx_bytes;
1618 stats->tx_packets = tx_pkts;
1619 stats->rx_bytes = rx_bytes;
1620 stats->rx_packets = rx_pkts;
1621
d3ec4ef6
JS
1622 stats->rx_errors = rx_errors;
1623 stats->multicast = rx_multicast;
1624 stats->rx_length_errors = rx_length_errors;
1625 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S
1626 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1627
d3ec4ef6
JS
1628 stats->tx_errors = tx_errors;
1629 stats->rx_dropped = rx_drop;
1630 stats->tx_dropped = tx_drop;
76ad4f0e
S
1631 stats->collisions = netdev->stats.collisions;
1632 stats->rx_over_errors = netdev->stats.rx_over_errors;
1633 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1634 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1635 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1636 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1637 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1638 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1639 stats->tx_window_errors = netdev->stats.tx_window_errors;
1640 stats->rx_compressed = netdev->stats.rx_compressed;
1641 stats->tx_compressed = netdev->stats.tx_compressed;
1642}
1643
30d240df 1644static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1645{
30d240df 1646 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
30d240df 1647 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
75718800 1648 struct hnae3_knic_private_info *kinfo;
30d240df
YL
1649 u8 tc = mqprio_qopt->qopt.num_tc;
1650 u16 mode = mqprio_qopt->mode;
1651 u8 hw = mqprio_qopt->qopt.hw;
75718800 1652 struct hnae3_handle *h;
76ad4f0e 1653
30d240df
YL
1654 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1655 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1656 return -EOPNOTSUPP;
1657
76ad4f0e
S
1658 if (tc > HNAE3_MAX_TC)
1659 return -EINVAL;
1660
76ad4f0e
S
1661 if (!netdev)
1662 return -EINVAL;
1663
75718800
YL
1664 h = hns3_get_handle(netdev);
1665 kinfo = &h->kinfo;
1666
1c822948
YL
1667 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1668
1cce5eb6 1669 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
30d240df 1670 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e
S
1671}
1672
2572ac53 1673static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1674 void *type_data)
76ad4f0e 1675{
575ed7d3 1676 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1677 return -EOPNOTSUPP;
76ad4f0e 1678
30d240df 1679 return hns3_setup_tc(dev, type_data);
76ad4f0e
S
1680}
1681
1682static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1683 __be16 proto, u16 vid)
1684{
9780cb97 1685 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
1686 int ret = -EIO;
1687
1688 if (h->ae_algo->ops->set_vlan_filter)
1689 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1690
1691 return ret;
1692}
1693
1694static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1695 __be16 proto, u16 vid)
1696{
9780cb97 1697 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
1698 int ret = -EIO;
1699
1700 if (h->ae_algo->ops->set_vlan_filter)
1701 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1702
7fa6be4f 1703 return ret;
681ec399
YL
1704}
1705
76ad4f0e
S
1706static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1707 u8 qos, __be16 vlan_proto)
1708{
9780cb97 1709 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S
1710 int ret = -EIO;
1711
1c822948 1712 netif_dbg(h, drv, netdev,
39edaf24
GL
1713 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
1714 vf, vlan, qos, ntohs(vlan_proto));
1c822948 1715
76ad4f0e
S
1716 if (h->ae_algo->ops->set_vf_vlan_filter)
1717 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
9b2f3477 1718 qos, vlan_proto);
76ad4f0e
S
1719
1720 return ret;
1721}
1722
22044f95
JS
1723static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1724{
1725 struct hnae3_handle *handle = hns3_get_handle(netdev);
1726
1727 if (hns3_nic_resetting(netdev))
1728 return -EBUSY;
1729
1730 if (!handle->ae_algo->ops->set_vf_spoofchk)
1731 return -EOPNOTSUPP;
1732
1733 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1734}
1735
e196ec75
JS
1736static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1737{
1738 struct hnae3_handle *handle = hns3_get_handle(netdev);
1739
1740 if (!handle->ae_algo->ops->set_vf_trust)
1741 return -EOPNOTSUPP;
1742
1743 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1744}
1745
a8e8b7ff
S
1746static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1747{
9780cb97 1748 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S
1749 int ret;
1750
6ff7ed80
HT
1751 if (hns3_nic_resetting(netdev))
1752 return -EBUSY;
1753
a8e8b7ff
S
1754 if (!h->ae_algo->ops->set_mtu)
1755 return -EOPNOTSUPP;
1756
1c822948
YL
1757 netif_dbg(h, drv, netdev,
1758 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1759
a8e8b7ff 1760 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1761 if (ret)
a8e8b7ff
S
1762 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1763 ret);
93d8daf4
YL
1764 else
1765 netdev->mtu = new_mtu;
5bad95a1 1766
a8e8b7ff
S
1767 return ret;
1768}
1769
f8fa222c
L
1770static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1771{
1772 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 1773 struct hnae3_handle *h = hns3_get_handle(ndev);
0bfdf286 1774 struct hns3_enet_ring *tx_ring;
e511c97d 1775 struct napi_struct *napi;
f8fa222c
L
1776 int timeout_queue = 0;
1777 int hw_head, hw_tail;
e511c97d
JS
1778 int fbd_num, fbd_oft;
1779 int ebd_num, ebd_oft;
1780 int bd_num, bd_err;
1781 int ring_en, tc;
f8fa222c
L
1782 int i;
1783
1784 /* Find the stopped queue the same way the stack does */
fa6c4084 1785 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L
1786 struct netdev_queue *q;
1787 unsigned long trans_start;
1788
1789 q = netdev_get_tx_queue(ndev, i);
1790 trans_start = q->trans_start;
1791 if (netif_xmit_stopped(q) &&
1792 time_after(jiffies,
1793 (trans_start + ndev->watchdog_timeo))) {
1794 timeout_queue = i;
647522a5
YL
1795 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1796 q->state,
1797 jiffies_to_msecs(jiffies - trans_start));
f8fa222c
L
1798 break;
1799 }
1800 }
1801
1802 if (i == ndev->num_tx_queues) {
1803 netdev_info(ndev,
1804 "no netdev TX timeout queue found, timeout count: %llu\n",
1805 priv->tx_timeout_count);
1806 return false;
1807 }
1808
beab694a
JS
1809 priv->tx_timeout_count++;
1810
5f06b903 1811 tx_ring = &priv->ring[timeout_queue];
e511c97d
JS
1812 napi = &tx_ring->tqp_vector->napi;
1813
1814 netdev_info(ndev,
1815 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1816 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1817 tx_ring->next_to_clean, napi->state);
1818
1819 netdev_info(ndev,
1820 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1821 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1822 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1823
1824 netdev_info(ndev,
1825 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1826 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1827 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1828
1829 /* When mac received many pause frames continuous, it's unable to send
1830 * packets, which may cause tx timeout
1831 */
615466ce
YM
1832 if (h->ae_algo->ops->get_mac_stats) {
1833 struct hns3_mac_stats mac_stats;
e511c97d 1834
615466ce 1835 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
e511c97d 1836 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
615466ce 1837 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
e511c97d 1838 }
f8fa222c
L
1839
1840 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1841 HNS3_RING_TX_RING_HEAD_REG);
1842 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1843 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS
1844 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1845 HNS3_RING_TX_RING_FBDNUM_REG);
1846 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1847 HNS3_RING_TX_RING_OFFSET_REG);
1848 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1849 HNS3_RING_TX_RING_EBDNUM_REG);
1850 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1851 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1852 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1853 HNS3_RING_TX_RING_BD_NUM_REG);
1854 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1855 HNS3_RING_TX_RING_BD_ERR_REG);
1856 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1857 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1858
f8fa222c 1859 netdev_info(ndev,
e511c97d
JS
1860 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1861 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 1862 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS
1863 netdev_info(ndev,
1864 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1865 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L
1866
1867 return true;
1868}
1869
1870static void hns3_nic_net_timeout(struct net_device *ndev)
1871{
1872 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L
1873 struct hnae3_handle *h = priv->ae_handle;
1874
1875 if (!hns3_get_tx_timeo_queue_info(ndev))
1876 return;
1877
0742ed7c
HT
1878 /* request the reset, and let the hclge to determine
1879 * which reset level should be done
1880 */
f8fa222c 1881 if (h->ae_algo->ops->reset_event)
6ae4e733 1882 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L
1883}
1884
d93ed94f
JS
1885#ifdef CONFIG_RFS_ACCEL
1886static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1887 u16 rxq_index, u32 flow_id)
1888{
1889 struct hnae3_handle *h = hns3_get_handle(dev);
1890 struct flow_keys fkeys;
1891
1892 if (!h->ae_algo->ops->add_arfs_entry)
1893 return -EOPNOTSUPP;
1894
1895 if (skb->encapsulation)
1896 return -EPROTONOSUPPORT;
1897
1898 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1899 return -EPROTONOSUPPORT;
1900
1901 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1902 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1903 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1904 fkeys.basic.ip_proto != IPPROTO_UDP))
1905 return -EPROTONOSUPPORT;
1906
1907 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1908}
1909#endif
1910
6430f744
YM
1911static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1912 struct ifla_vf_info *ivf)
1913{
1914 struct hnae3_handle *h = hns3_get_handle(ndev);
1915
1916 if (!h->ae_algo->ops->get_vf_config)
1917 return -EOPNOTSUPP;
1918
1919 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1920}
1921
1922static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1923 int link_state)
1924{
1925 struct hnae3_handle *h = hns3_get_handle(ndev);
1926
1927 if (!h->ae_algo->ops->set_vf_link_state)
1928 return -EOPNOTSUPP;
1929
1930 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1931}
1932
ee9e4424
YL
1933static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1934 int min_tx_rate, int max_tx_rate)
1935{
1936 struct hnae3_handle *h = hns3_get_handle(ndev);
1937
1938 if (!h->ae_algo->ops->set_vf_rate)
1939 return -EOPNOTSUPP;
1940
1941 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1942 false);
1943}
1944
8e6de441
HT
1945static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1946{
1947 struct hnae3_handle *h = hns3_get_handle(netdev);
1948
1949 if (!h->ae_algo->ops->set_vf_mac)
1950 return -EOPNOTSUPP;
1951
1952 if (is_multicast_ether_addr(mac)) {
1953 netdev_err(netdev,
1954 "Invalid MAC:%pM specified. Could not set MAC\n",
1955 mac);
1956 return -EINVAL;
1957 }
1958
1959 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
1960}
1961
76ad4f0e
S
1962static const struct net_device_ops hns3_nic_netdev_ops = {
1963 .ndo_open = hns3_nic_net_open,
1964 .ndo_stop = hns3_nic_net_stop,
1965 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1966 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1967 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 1968 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1969 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S
1970 .ndo_set_features = hns3_nic_set_features,
1971 .ndo_get_stats64 = hns3_nic_get_stats64,
1972 .ndo_setup_tc = hns3_nic_setup_tc,
1973 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S
1974 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1975 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1976 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
22044f95 1977 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
e196ec75 1978 .ndo_set_vf_trust = hns3_set_vf_trust,
d93ed94f
JS
1979#ifdef CONFIG_RFS_ACCEL
1980 .ndo_rx_flow_steer = hns3_rx_flow_steer,
1981#endif
6430f744
YM
1982 .ndo_get_vf_config = hns3_nic_get_vf_config,
1983 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
ee9e4424 1984 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
8e6de441 1985 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
76ad4f0e
S
1986};
1987
97afd47b 1988bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL
1989{
1990 u32 dev_id = pdev->device;
1991
1992 switch (dev_id) {
1993 case HNAE3_DEV_ID_GE:
1994 case HNAE3_DEV_ID_25GE:
1995 case HNAE3_DEV_ID_25GE_RDMA:
1996 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1997 case HNAE3_DEV_ID_50GE_RDMA:
1998 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1999 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2000 return true;
2001 case HNAE3_DEV_ID_100G_VF:
2002 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2003 return false;
2004 default:
adcf738b 2005 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2312e050
FL
2006 dev_id);
2007 }
2008
2009 return false;
2010}
2011
2312e050
FL
2012static void hns3_disable_sriov(struct pci_dev *pdev)
2013{
2014 /* If our VFs are assigned we cannot shut down SR-IOV
2015 * without causing issues, so just leave the hardware
2016 * available but disabled
2017 */
2018 if (pci_vfs_assigned(pdev)) {
2019 dev_warn(&pdev->dev,
2020 "disabling driver while VFs are assigned\n");
2021 return;
2022 }
2023
2024 pci_disable_sriov(pdev);
2025}
2026
d695964d
JS
2027static void hns3_get_dev_capability(struct pci_dev *pdev,
2028 struct hnae3_ae_dev *ae_dev)
2029{
b26a6fea 2030 if (pdev->revision >= 0x21) {
d695964d 2031 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
b26a6fea
PL
2032 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2033 }
d695964d
JS
2034}
2035
76ad4f0e
S
2036/* hns3_probe - Device initialization routine
2037 * @pdev: PCI device information struct
2038 * @ent: entry in hns3_pci_tbl
2039 *
2040 * hns3_probe initializes a PF identified by a pci_dev structure.
2041 * The OS initialization, configuring of the PF private structure,
2042 * and a hardware reset occur.
2043 *
2044 * Returns 0 on success, negative on failure
2045 */
2046static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2047{
2048 struct hnae3_ae_dev *ae_dev;
2049 int ret;
2050
9b2f3477 2051 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
76ad4f0e
S
2052 if (!ae_dev) {
2053 ret = -ENOMEM;
2054 return ret;
2055 }
2056
2057 ae_dev->pdev = pdev;
e92a0843 2058 ae_dev->flag = ent->driver_data;
6871af29 2059 ae_dev->reset_type = HNAE3_NONE_RESET;
d695964d 2060 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S
2061 pci_set_drvdata(pdev, ae_dev);
2062
74354140
HT
2063 ret = hnae3_register_ae_dev(ae_dev);
2064 if (ret) {
2065 devm_kfree(&pdev->dev, ae_dev);
2066 pci_set_drvdata(pdev, NULL);
2067 }
2312e050 2068
74354140 2069 return ret;
76ad4f0e
S
2070}
2071
2072/* hns3_remove - Device removal routine
2073 * @pdev: PCI device information struct
2074 */
2075static void hns3_remove(struct pci_dev *pdev)
2076{
2077 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2078
2312e050
FL
2079 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2080 hns3_disable_sriov(pdev);
2081
76ad4f0e 2082 hnae3_unregister_ae_dev(ae_dev);
ac864c23 2083 pci_set_drvdata(pdev, NULL);
76ad4f0e
S
2084}
2085
fa8d82e8
PL
2086/**
2087 * hns3_pci_sriov_configure
2088 * @pdev: pointer to a pci_dev structure
2089 * @num_vfs: number of VFs to allocate
2090 *
2091 * Enable or change the number of VFs. Called when the user updates the number
2092 * of VFs in sysfs.
2093 **/
743e1a84 2094static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL
2095{
2096 int ret;
2097
2098 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2099 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2100 return -EINVAL;
2101 }
2102
2103 if (num_vfs) {
2104 ret = pci_enable_sriov(pdev, num_vfs);
2105 if (ret)
2106 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM
2107 else
2108 return num_vfs;
fa8d82e8
PL
2109 } else if (!pci_vfs_assigned(pdev)) {
2110 pci_disable_sriov(pdev);
2111 } else {
2112 dev_warn(&pdev->dev,
2113 "Unable to free VFs because some are assigned to VMs.\n");
2114 }
2115
2116 return 0;
2117}
2118
ce2c1d2e
YL
2119static void hns3_shutdown(struct pci_dev *pdev)
2120{
2121 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2122
2123 hnae3_unregister_ae_dev(ae_dev);
2124 devm_kfree(&pdev->dev, ae_dev);
2125 pci_set_drvdata(pdev, NULL);
2126
2127 if (system_state == SYSTEM_POWER_OFF)
2128 pci_set_power_state(pdev, PCI_D3hot);
2129}
2130
5a9f0eac
SJ
2131static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2132 pci_channel_state_t state)
2133{
2134 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2135 pci_ers_result_t ret;
2136
2137 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2138
2139 if (state == pci_channel_io_perm_failure)
2140 return PCI_ERS_RESULT_DISCONNECT;
2141
661262bc 2142 if (!ae_dev || !ae_dev->ops) {
5a9f0eac 2143 dev_err(&pdev->dev,
661262bc 2144 "Can't recover - error happened before device initialized\n");
5a9f0eac
SJ
2145 return PCI_ERS_RESULT_NONE;
2146 }
2147
381c356e
SJ
2148 if (ae_dev->ops->handle_hw_ras_error)
2149 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ
2150 else
2151 return PCI_ERS_RESULT_NONE;
2152
2153 return ret;
2154}
2155
6ae4e733
SJ
2156static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2157{
2158 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
ad9bf545 2159 const struct hnae3_ae_ops *ops;
123297b7 2160 enum hnae3_reset_type reset_type;
6ae4e733
SJ
2161 struct device *dev = &pdev->dev;
2162
661262bc
WL
2163 if (!ae_dev || !ae_dev->ops)
2164 return PCI_ERS_RESULT_NONE;
2165
ad9bf545 2166 ops = ae_dev->ops;
6ae4e733 2167 /* request the reset */
fa17c708
GH
2168 if (ops->reset_event && ops->get_reset_level &&
2169 ops->set_default_reset_request) {
9d5e67d1 2170 if (ae_dev->hw_err_reset_req) {
123297b7
SJ
2171 reset_type = ops->get_reset_level(ae_dev,
2172 &ae_dev->hw_err_reset_req);
2173 ops->set_default_reset_request(ae_dev, reset_type);
2174 dev_info(dev, "requesting reset due to PCI error\n");
2175 ops->reset_event(pdev, NULL);
2176 }
69b51bbb 2177
6ae4e733
SJ
2178 return PCI_ERS_RESULT_RECOVERED;
2179 }
2180
2181 return PCI_ERS_RESULT_DISCONNECT;
2182}
2183
6b9a97ee
HT
2184static void hns3_reset_prepare(struct pci_dev *pdev)
2185{
2186 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2187
2188 dev_info(&pdev->dev, "hns3 flr prepare\n");
2189 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2190 ae_dev->ops->flr_prepare(ae_dev);
2191}
2192
2193static void hns3_reset_done(struct pci_dev *pdev)
2194{
2195 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2196
2197 dev_info(&pdev->dev, "hns3 flr done\n");
2198 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2199 ae_dev->ops->flr_done(ae_dev);
2200}
2201
5a9f0eac
SJ
2202static const struct pci_error_handlers hns3_err_handler = {
2203 .error_detected = hns3_error_detected,
6ae4e733 2204 .slot_reset = hns3_slot_reset,
6b9a97ee
HT
2205 .reset_prepare = hns3_reset_prepare,
2206 .reset_done = hns3_reset_done,
5a9f0eac
SJ
2207};
2208
76ad4f0e
S
2209static struct pci_driver hns3_driver = {
2210 .name = hns3_driver_name,
2211 .id_table = hns3_pci_tbl,
2212 .probe = hns3_probe,
2213 .remove = hns3_remove,
ce2c1d2e 2214 .shutdown = hns3_shutdown,
fa8d82e8 2215 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 2216 .err_handler = &hns3_err_handler,
76ad4f0e
S
2217};
2218
2219/* set default feature to hns3 */
2220static void hns3_set_default_feature(struct net_device *netdev)
2221{
3e85af6a
PL
2222 struct hnae3_handle *h = hns3_get_handle(netdev);
2223 struct pci_dev *pdev = h->pdev;
2224
76ad4f0e
S
2225 netdev->priv_flags |= IFF_UNICAST_FLT;
2226
2227 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2228 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2229 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2230 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL
2231 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2232 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
76ad4f0e
S
2233
2234 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2235
2236 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2237 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 2238 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S
2239 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2240 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2241 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL
2242 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2243 NETIF_F_FRAGLIST;
76ad4f0e
S
2244
2245 netdev->vlan_features |=
2246 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2247 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2248 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2249 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL
2250 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2251 NETIF_F_FRAGLIST;
76ad4f0e
S
2252
2253 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 2254 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S
2255 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2256 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2257 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
8ae10cfb
YL
2258 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2259 NETIF_F_FRAGLIST;
3e85af6a 2260
c17852a8 2261 if (pdev->revision >= 0x21) {
77af09c6 2262 netdev->hw_features |= NETIF_F_GRO_HW;
5c9f6b39 2263 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS
2264
2265 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2266 netdev->hw_features |= NETIF_F_NTUPLE;
2267 netdev->features |= NETIF_F_NTUPLE;
2268 }
2269 }
76ad4f0e
S
2270}
2271
2272static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2273 struct hns3_desc_cb *cb)
2274{
dbba6da0 2275 unsigned int order = hns3_page_order(ring);
76ad4f0e
S
2276 struct page *p;
2277
2278 p = dev_alloc_pages(order);
2279 if (!p)
2280 return -ENOMEM;
2281
2282 cb->priv = p;
2283 cb->page_offset = 0;
2284 cb->reuse_flag = 0;
2285 cb->buf = page_address(p);
dbba6da0 2286 cb->length = hns3_page_size(ring);
76ad4f0e
S
2287 cb->type = DESC_TYPE_PAGE;
2288
76ad4f0e
S
2289 return 0;
2290}
2291
2292static void hns3_free_buffer(struct hns3_enet_ring *ring,
2293 struct hns3_desc_cb *cb)
2294{
2295 if (cb->type == DESC_TYPE_SKB)
2296 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2297 else if (!HNAE3_IS_TX_RING(ring))
2298 put_page((struct page *)cb->priv);
2299 memset(cb, 0, sizeof(*cb));
2300}
2301
2302static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2303{
2304 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2305 cb->length, ring_to_dma_dir(ring));
2306
2211f4e1 2307 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S
2308 return -EIO;
2309
2310 return 0;
2311}
2312
2313static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2314 struct hns3_desc_cb *cb)
2315{
2316 if (cb->type == DESC_TYPE_SKB)
2317 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2318 ring_to_dma_dir(ring));
bcdb12b7 2319 else if (cb->length)
76ad4f0e
S
2320 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2321 ring_to_dma_dir(ring));
2322}
2323
2324static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2325{
2326 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2327 ring->desc[i].addr = 0;
2328}
2329
2330static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2331{
2332 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2333
2334 if (!ring->desc_cb[i].dma)
2335 return;
2336
2337 hns3_buffer_detach(ring, i);
2338 hns3_free_buffer(ring, cb);
2339}
2340
2341static void hns3_free_buffers(struct hns3_enet_ring *ring)
2342{
2343 int i;
2344
2345 for (i = 0; i < ring->desc_num; i++)
2346 hns3_free_buffer_detach(ring, i);
2347}
2348
2349/* free desc along with its attached buffer */
2350static void hns3_free_desc(struct hns3_enet_ring *ring)
2351{
024cc792
HT
2352 int size = ring->desc_num * sizeof(ring->desc[0]);
2353
76ad4f0e
S
2354 hns3_free_buffers(ring);
2355
024cc792
HT
2356 if (ring->desc) {
2357 dma_free_coherent(ring_to_dev(ring), size,
2358 ring->desc, ring->desc_dma_addr);
2359 ring->desc = NULL;
2360 }
76ad4f0e
S
2361}
2362
2363static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2364{
2365 int size = ring->desc_num * sizeof(ring->desc[0]);
2366
750afb08
LC
2367 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2368 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S
2369 if (!ring->desc)
2370 return -ENOMEM;
2371
76ad4f0e
S
2372 return 0;
2373}
2374
2375static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2376 struct hns3_desc_cb *cb)
2377{
2378 int ret;
2379
2380 ret = hns3_alloc_buffer(ring, cb);
2381 if (ret)
2382 goto out;
2383
2384 ret = hns3_map_buffer(ring, cb);
2385 if (ret)
2386 goto out_with_buf;
2387
2388 return 0;
2389
2390out_with_buf:
564883bb 2391 hns3_free_buffer(ring, cb);
76ad4f0e
S
2392out:
2393 return ret;
2394}
2395
2396static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2397{
2398 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2399
2400 if (ret)
2401 return ret;
2402
2403 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2404
2405 return 0;
2406}
2407
2408/* Allocate memory for raw pkg, and map with dma */
2409static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2410{
2411 int i, j, ret;
2412
2413 for (i = 0; i < ring->desc_num; i++) {
2414 ret = hns3_alloc_buffer_attach(ring, i);
2415 if (ret)
2416 goto out_buffer_fail;
2417 }
2418
2419 return 0;
2420
2421out_buffer_fail:
2422 for (j = i - 1; j >= 0; j--)
2423 hns3_free_buffer_detach(ring, j);
2424 return ret;
2425}
2426
9b2f3477 2427/* detach a in-used buffer and replace with a reserved one */
76ad4f0e
S
2428static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2429 struct hns3_desc_cb *res_cb)
2430{
b9077428 2431 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S
2432 ring->desc_cb[i] = *res_cb;
2433 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2434 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S
2435}
2436
2437static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2438{
2439 ring->desc_cb[i].reuse_flag = 0;
9b2f3477
WL
2440 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2441 ring->desc_cb[i].page_offset);
7d0b130c 2442 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S
2443}
2444
ce74370c
YL
2445static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2446 int *bytes, int *pkts)
76ad4f0e 2447{
26cda2f1
YL
2448 int ntc = ring->next_to_clean;
2449 struct hns3_desc_cb *desc_cb;
76ad4f0e 2450
ce74370c
YL
2451 while (head != ntc) {
2452 desc_cb = &ring->desc_cb[ntc];
2453 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2454 (*bytes) += desc_cb->length;
2455 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2456 hns3_free_buffer_detach(ring, ntc);
76ad4f0e 2457
ce74370c
YL
2458 if (++ntc == ring->desc_num)
2459 ntc = 0;
2460
2461 /* Issue prefetch for next Tx descriptor */
2462 prefetch(&ring->desc_cb[ntc]);
2463 }
26cda2f1
YL
2464
2465 /* This smp_store_release() pairs with smp_load_acquire() in
2466 * ring_space called by hns3_nic_net_xmit.
2467 */
2468 smp_store_release(&ring->next_to_clean, ntc);
76ad4f0e
S
2469}
2470
2471static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2472{
2473 int u = ring->next_to_use;
2474 int c = ring->next_to_clean;
2475
2476 if (unlikely(h > ring->desc_num))
2477 return 0;
2478
2479 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2480}
2481
799997a3 2482void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e 2483{
c8711956 2484 struct net_device *netdev = ring_to_netdev(ring);
7a810110 2485 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S
2486 struct netdev_queue *dev_queue;
2487 int bytes, pkts;
2488 int head;
2489
2490 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
76ad4f0e
S
2491
2492 if (is_ring_empty(ring) || head == ring->next_to_clean)
799997a3 2493 return; /* no data to poll */
76ad4f0e 2494
88b7c58c
YL
2495 rmb(); /* Make sure head is ready before touch any data */
2496
0e6084aa 2497 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S
2498 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2499 ring->next_to_use, ring->next_to_clean);
2500
2501 u64_stats_update_begin(&ring->syncp);
2502 ring->stats.io_err_cnt++;
2503 u64_stats_update_end(&ring->syncp);
799997a3 2504 return;
76ad4f0e
S
2505 }
2506
2507 bytes = 0;
2508 pkts = 0;
ce74370c 2509 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
76ad4f0e
S
2510
2511 ring->tqp_vector->tx_group.total_bytes += bytes;
2512 ring->tqp_vector->tx_group.total_packets += pkts;
2513
2514 u64_stats_update_begin(&ring->syncp);
2515 ring->stats.tx_bytes += bytes;
2516 ring->stats.tx_pkts += pkts;
2517 u64_stats_update_end(&ring->syncp);
2518
2519 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2520 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2521
2522 if (unlikely(pkts && netif_carrier_ok(netdev) &&
8ae10cfb 2523 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
76ad4f0e
S
2524 /* Make sure that anybody stopping the queue after this
2525 * sees the new next_to_clean.
2526 */
2527 smp_mb();
7a810110
JS
2528 if (netif_tx_queue_stopped(dev_queue) &&
2529 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S
2530 netif_tx_wake_queue(dev_queue);
2531 ring->stats.restart_queue++;
2532 }
2533 }
76ad4f0e
S
2534}
2535
2536static int hns3_desc_unused(struct hns3_enet_ring *ring)
2537{
2538 int ntc = ring->next_to_clean;
2539 int ntu = ring->next_to_use;
2540
2541 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2542}
2543
9b2f3477
WL
2544static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2545 int cleand_count)
76ad4f0e
S
2546{
2547 struct hns3_desc_cb *desc_cb;
2548 struct hns3_desc_cb res_cbs;
2549 int i, ret;
2550
2551 for (i = 0; i < cleand_count; i++) {
2552 desc_cb = &ring->desc_cb[ring->next_to_use];
2553 if (desc_cb->reuse_flag) {
2554 u64_stats_update_begin(&ring->syncp);
2555 ring->stats.reuse_pg_cnt++;
2556 u64_stats_update_end(&ring->syncp);
2557
2558 hns3_reuse_buffer(ring, ring->next_to_use);
2559 } else {
2560 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2561 if (ret) {
2562 u64_stats_update_begin(&ring->syncp);
2563 ring->stats.sw_err_cnt++;
2564 u64_stats_update_end(&ring->syncp);
2565
c8711956 2566 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5
YL
2567 "alloc rx buffer failed: %d\n",
2568 ret);
76ad4f0e
S
2569 break;
2570 }
2571 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL
2572
2573 u64_stats_update_begin(&ring->syncp);
2574 ring->stats.non_reuse_pg++;
2575 u64_stats_update_end(&ring->syncp);
76ad4f0e
S
2576 }
2577
2578 ring_ptr_move_fw(ring, next_to_use);
2579 }
2580
2581 wmb(); /* Make all data has been write before submit */
2582 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2583}
2584
76ad4f0e
S
2585static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2586 struct hns3_enet_ring *ring, int pull_len,
2587 struct hns3_desc_cb *desc_cb)
2588{
389ca146
YL
2589 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2590 int size = le16_to_cpu(desc->rx.size);
dbba6da0 2591 u32 truesize = hns3_buf_size(ring);
76ad4f0e
S
2592
2593 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2594 size - pull_len, truesize);
76ad4f0e 2595
389ca146
YL
2596 /* Avoid re-using remote pages, or the stack is still using the page
2597 * when page_offset rollback to zero, flag default unreuse
2598 */
d5970dc7 2599 if (unlikely(page_to_nid(desc_cb->priv) != numa_mem_id()) ||
389ca146 2600 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
76ad4f0e 2601 return;
76ad4f0e
S
2602
2603 /* Move offset up to the next cache line */
2604 desc_cb->page_offset += truesize;
2605
dbba6da0 2606 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
76ad4f0e 2607 desc_cb->reuse_flag = 1;
9b2f3477 2608 /* Bump ref count on page before it is given */
76ad4f0e 2609 get_page(desc_cb->priv);
389ca146
YL
2610 } else if (page_count(desc_cb->priv) == 1) {
2611 desc_cb->reuse_flag = 1;
2612 desc_cb->page_offset = 0;
2613 get_page(desc_cb->priv);
76ad4f0e
S
2614 }
2615}
2616
e2ee1c5a 2617static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
d474d88f
YL
2618{
2619 __be16 type = skb->protocol;
2620 struct tcphdr *th;
2621 int depth = 0;
2622
e2ee1c5a 2623 while (eth_type_vlan(type)) {
d474d88f
YL
2624 struct vlan_hdr *vh;
2625
2626 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2627 return -EFAULT;
2628
2629 vh = (struct vlan_hdr *)(skb->data + depth);
2630 type = vh->h_vlan_encapsulated_proto;
2631 depth += VLAN_HLEN;
2632 }
2633
e2ee1c5a
YL
2634 skb_set_network_header(skb, depth);
2635
d474d88f 2636 if (type == htons(ETH_P_IP)) {
e2ee1c5a
YL
2637 const struct iphdr *iph = ip_hdr(skb);
2638
d474d88f 2639 depth += sizeof(struct iphdr);
e2ee1c5a
YL
2640 skb_set_transport_header(skb, depth);
2641 th = tcp_hdr(skb);
2642 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2643 iph->daddr, 0);
d474d88f 2644 } else if (type == htons(ETH_P_IPV6)) {
e2ee1c5a
YL
2645 const struct ipv6hdr *iph = ipv6_hdr(skb);
2646
d474d88f 2647 depth += sizeof(struct ipv6hdr);
e2ee1c5a
YL
2648 skb_set_transport_header(skb, depth);
2649 th = tcp_hdr(skb);
2650 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2651 &iph->daddr, 0);
d474d88f 2652 } else {
b20d7fe5
YL
2653 hns3_rl_err(skb->dev,
2654 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2655 be16_to_cpu(type), depth);
d474d88f
YL
2656 return -EFAULT;
2657 }
2658
d474d88f
YL
2659 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2660 if (th->cwr)
2661 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2662
e2ee1c5a
YL
2663 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2664 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
d474d88f 2665
e2ee1c5a
YL
2666 skb->csum_start = (unsigned char *)th - skb->head;
2667 skb->csum_offset = offsetof(struct tcphdr, check);
2668 skb->ip_summed = CHECKSUM_PARTIAL;
d474d88f
YL
2669 return 0;
2670}
2671
76ad4f0e 2672static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
39c38824 2673 u32 l234info, u32 bd_base_info, u32 ol_info)
76ad4f0e 2674{
c8711956 2675 struct net_device *netdev = ring_to_netdev(ring);
76ad4f0e 2676 int l3_type, l4_type;
76ad4f0e 2677 int ol4_type;
76ad4f0e
S
2678
2679 skb->ip_summed = CHECKSUM_NONE;
2680
2681 skb_checksum_none_assert(skb);
2682
2683 if (!(netdev->features & NETIF_F_RXCSUM))
2684 return;
2685
2686 /* check if hardware has done checksum */
e8149933 2687 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
76ad4f0e
S
2688 return;
2689
f4772dee
DC
2690 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2691 BIT(HNS3_RXD_OL3E_B) |
e8149933 2692 BIT(HNS3_RXD_OL4E_B)))) {
76ad4f0e
S
2693 u64_stats_update_begin(&ring->syncp);
2694 ring->stats.l3l4_csum_err++;
2695 u64_stats_update_end(&ring->syncp);
2696
2697 return;
2698 }
2699
39c38824 2700 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 2701 HNS3_RXD_OL4ID_S);
76ad4f0e
S
2702 switch (ol4_type) {
2703 case HNS3_OL4_TYPE_MAC_IN_UDP:
2704 case HNS3_OL4_TYPE_NVGRE:
2705 skb->csum_level = 1;
be44b3af 2706 /* fall through */
76ad4f0e 2707 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL
2708 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2709 HNS3_RXD_L3ID_S);
2710 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2711 HNS3_RXD_L4ID_S);
2712
76ad4f0e 2713 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL
2714 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2715 l3_type == HNS3_L3_TYPE_IPV6) &&
2716 (l4_type == HNS3_L4_TYPE_UDP ||
2717 l4_type == HNS3_L4_TYPE_TCP ||
2718 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S
2719 skb->ip_summed = CHECKSUM_UNNECESSARY;
2720 break;
fa7a4bd5
JS
2721 default:
2722 break;
76ad4f0e
S
2723 }
2724}
2725
d43e5aca
YL
2726static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2727{
81ae0e04
PL
2728 if (skb_has_frag_list(skb))
2729 napi_gro_flush(&ring->tqp_vector->napi, false);
2730
d43e5aca
YL
2731 napi_gro_receive(&ring->tqp_vector->napi, skb);
2732}
2733
701a6d6a
JS
2734static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2735 struct hns3_desc *desc, u32 l234info,
2736 u16 *vlan_tag)
5b5455a9 2737{
44e626f7 2738 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 2739 struct pci_dev *pdev = ring->tqp->handle->pdev;
5b5455a9
PL
2740
2741 if (pdev->revision == 0x20) {
701a6d6a
JS
2742 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2743 if (!(*vlan_tag & VLAN_VID_MASK))
2744 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 2745
701a6d6a 2746 return (*vlan_tag != 0);
5b5455a9
PL
2747 }
2748
2749#define HNS3_STRP_OUTER_VLAN 0x1
2750#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 2751#define HNS3_STRP_BOTH 0x3
5b5455a9 2752
44e626f7
JS
2753 /* Hardware always insert VLAN tag into RX descriptor when
2754 * remove the tag from packet, driver needs to determine
2755 * reporting which tag to stack.
2756 */
e4e87715
PL
2757 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2758 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 2759 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS
2760 if (handle->port_base_vlan_state !=
2761 HNAE3_PORT_BASE_VLAN_DISABLE)
2762 return false;
2763
701a6d6a
JS
2764 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2765 return true;
5b5455a9 2766 case HNS3_STRP_INNER_VLAN:
44e626f7
JS
2767 if (handle->port_base_vlan_state !=
2768 HNAE3_PORT_BASE_VLAN_DISABLE)
2769 return false;
2770
701a6d6a 2771 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS
2772 return true;
2773 case HNS3_STRP_BOTH:
2774 if (handle->port_base_vlan_state ==
2775 HNAE3_PORT_BASE_VLAN_DISABLE)
2776 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2777 else
2778 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2779
701a6d6a 2780 return true;
5b5455a9 2781 default:
701a6d6a 2782 return false;
5b5455a9 2783 }
5b5455a9
PL
2784}
2785
b9a8f883 2786static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
e5597095
PL
2787 unsigned char *va)
2788{
2789#define HNS3_NEED_ADD_FRAG 1
2790 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
c8711956 2791 struct net_device *netdev = ring_to_netdev(ring);
e5597095
PL
2792 struct sk_buff *skb;
2793
2794 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2795 skb = ring->skb;
2796 if (unlikely(!skb)) {
b20d7fe5 2797 hns3_rl_err(netdev, "alloc rx skb fail\n");
e5597095
PL
2798
2799 u64_stats_update_begin(&ring->syncp);
2800 ring->stats.sw_err_cnt++;
2801 u64_stats_update_end(&ring->syncp);
2802
2803 return -ENOMEM;
2804 }
2805
2806 prefetchw(skb->data);
2807
2808 ring->pending_buf = 1;
81ae0e04
PL
2809 ring->frag_num = 0;
2810 ring->tail_skb = NULL;
e5597095
PL
2811 if (length <= HNS3_RX_HEAD_SIZE) {
2812 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2813
2814 /* We can reuse buffer as-is, just make sure it is local */
d5970dc7 2815 if (likely(page_to_nid(desc_cb->priv) == numa_mem_id()))
e5597095
PL
2816 desc_cb->reuse_flag = 1;
2817 else /* This page cannot be reused so discard it */
2818 put_page(desc_cb->priv);
2819
2820 ring_ptr_move_fw(ring, next_to_clean);
2821 return 0;
2822 }
2823 u64_stats_update_begin(&ring->syncp);
2824 ring->stats.seg_pkt_cnt++;
2825 u64_stats_update_end(&ring->syncp);
2826
c43f1255 2827 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 2828 __skb_put(skb, ring->pull_len);
81ae0e04 2829 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095
PL
2830 desc_cb);
2831 ring_ptr_move_fw(ring, next_to_clean);
2832
2833 return HNS3_NEED_ADD_FRAG;
2834}
2835
2836static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
d35bced8 2837 bool pending)
e5597095 2838{
d35bced8
YL
2839 struct sk_buff *skb = ring->skb;
2840 struct sk_buff *head_skb = skb;
81ae0e04 2841 struct sk_buff *new_skb;
e5597095
PL
2842 struct hns3_desc_cb *desc_cb;
2843 struct hns3_desc *pre_desc;
2844 u32 bd_base_info;
2845 int pre_bd;
2846
2847 /* if there is pending bd, the SW param next_to_clean has moved
2848 * to next and the next is NULL
2849 */
2850 if (pending) {
2851 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
9b2f3477 2852 ring->desc_num;
e5597095
PL
2853 pre_desc = &ring->desc[pre_bd];
2854 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2855 } else {
2856 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2857 }
2858
e8149933 2859 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
e5597095
PL
2860 desc = &ring->desc[ring->next_to_clean];
2861 desc_cb = &ring->desc_cb[ring->next_to_clean];
2862 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS
2863 /* make sure HW write desc complete */
2864 dma_rmb();
e8149933 2865 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL
2866 return -ENXIO;
2867
81ae0e04 2868 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
7fda3a93 2869 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
81ae0e04 2870 if (unlikely(!new_skb)) {
c8711956 2871 hns3_rl_err(ring_to_netdev(ring),
b20d7fe5 2872 "alloc rx fraglist skb fail\n");
81ae0e04
PL
2873 return -ENXIO;
2874 }
2875 ring->frag_num = 0;
2876
2877 if (ring->tail_skb) {
2878 ring->tail_skb->next = new_skb;
2879 ring->tail_skb = new_skb;
2880 } else {
2881 skb_shinfo(skb)->frag_list = new_skb;
2882 ring->tail_skb = new_skb;
2883 }
2884 }
2885
2886 if (ring->tail_skb) {
dbba6da0 2887 head_skb->truesize += hns3_buf_size(ring);
81ae0e04
PL
2888 head_skb->data_len += le16_to_cpu(desc->rx.size);
2889 head_skb->len += le16_to_cpu(desc->rx.size);
2890 skb = ring->tail_skb;
2891 }
2892
2893 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
e5597095
PL
2894 ring_ptr_move_fw(ring, next_to_clean);
2895 ring->pending_buf++;
2896 }
2897
2898 return 0;
2899}
2900
d474d88f
YL
2901static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2902 struct sk_buff *skb, u32 l234info,
39c38824 2903 u32 bd_base_info, u32 ol_info)
a6d53b97 2904{
a6d53b97
PL
2905 u32 l3_type;
2906
e2ee1c5a
YL
2907 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2908 HNS3_RXD_GRO_SIZE_M,
2909 HNS3_RXD_GRO_SIZE_S);
a6d53b97 2910 /* if there is no HW GRO, do not set gro params */
e2ee1c5a 2911 if (!skb_shinfo(skb)->gso_size) {
39c38824 2912 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
d474d88f
YL
2913 return 0;
2914 }
a6d53b97 2915
e2ee1c5a
YL
2916 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2917 HNS3_RXD_GRO_COUNT_M,
2918 HNS3_RXD_GRO_COUNT_S);
a6d53b97 2919
9b2f3477 2920 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
a6d53b97
PL
2921 if (l3_type == HNS3_L3_TYPE_IPV4)
2922 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2923 else if (l3_type == HNS3_L3_TYPE_IPV6)
2924 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2925 else
d474d88f 2926 return -EFAULT;
a6d53b97 2927
e2ee1c5a 2928 return hns3_gro_complete(skb, l234info);
a6d53b97
PL
2929}
2930
232fc64b 2931static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 2932 struct sk_buff *skb, u32 rss_hash)
232fc64b 2933{
232fc64b
PL
2934 struct hnae3_handle *handle = ring->tqp->handle;
2935 enum pkt_hash_types rss_type;
2936
ea485867 2937 if (rss_hash)
232fc64b
PL
2938 rss_type = handle->kinfo.rss_type;
2939 else
2940 rss_type = PKT_HASH_TYPE_NONE;
2941
ea485867 2942 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL
2943}
2944
ea485867 2945static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e 2946{
c8711956 2947 struct net_device *netdev = ring_to_netdev(ring);
c376fa1a 2948 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 2949 u32 bd_base_info, l234info, ol_info;
ea485867 2950 struct hns3_desc *desc;
d474d88f 2951 unsigned int len;
ea485867
YL
2952 int pre_ntc, ret;
2953
2954 /* bdinfo handled below is only valid on the last BD of the
2955 * current packet, and ring->next_to_clean indicates the first
2956 * descriptor of next packet, so need - 1 below.
2957 */
2958 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2959 (ring->desc_num - 1);
2960 desc = &ring->desc[pre_ntc];
2961 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2962 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 2963 ol_info = le32_to_cpu(desc->rx.ol_info);
d474d88f
YL
2964
2965 /* Based on hw strategy, the tag offloaded will be stored at
2966 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2967 * in one layer tag case.
2968 */
2969 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2970 u16 vlan_tag;
2971
2972 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2973 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2974 vlan_tag);
2975 }
2976
d474d88f
YL
2977 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
2978 BIT(HNS3_RXD_L2E_B))))) {
2979 u64_stats_update_begin(&ring->syncp);
2980 if (l234info & BIT(HNS3_RXD_L2E_B))
2981 ring->stats.l2_err++;
2982 else
2983 ring->stats.err_pkt_len++;
2984 u64_stats_update_end(&ring->syncp);
2985
2986 return -EFAULT;
2987 }
2988
2989 len = skb->len;
2990
2991 /* Do update ip stack process */
2992 skb->protocol = eth_type_trans(skb, netdev);
2993
2994 /* This is needed in order to enable forwarding support */
39c38824
YL
2995 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
2996 bd_base_info, ol_info);
d474d88f
YL
2997 if (unlikely(ret)) {
2998 u64_stats_update_begin(&ring->syncp);
2999 ring->stats.rx_err_cnt++;
3000 u64_stats_update_end(&ring->syncp);
3001 return ret;
3002 }
3003
3004 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3005 HNS3_RXD_DMAC_S);
3006
3007 u64_stats_update_begin(&ring->syncp);
3008 ring->stats.rx_pkts++;
3009 ring->stats.rx_bytes += len;
3010
3011 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3012 ring->stats.rx_multicast++;
3013
3014 u64_stats_update_end(&ring->syncp);
3015
3016 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL
3017
3018 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL
3019 return 0;
3020}
3021
d35bced8 3022static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
d474d88f 3023{
e5597095 3024 struct sk_buff *skb = ring->skb;
76ad4f0e
S
3025 struct hns3_desc_cb *desc_cb;
3026 struct hns3_desc *desc;
b9a8f883 3027 unsigned int length;
76ad4f0e 3028 u32 bd_base_info;
e5597095 3029 int ret;
76ad4f0e
S
3030
3031 desc = &ring->desc[ring->next_to_clean];
3032 desc_cb = &ring->desc_cb[ring->next_to_clean];
3033
3034 prefetch(desc);
3035
846fcc83 3036 length = le16_to_cpu(desc->rx.size);
76ad4f0e 3037 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S
3038
3039 /* Check valid BD */
e8149933 3040 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
e5597095 3041 return -ENXIO;
76ad4f0e 3042
e5597095
PL
3043 if (!skb)
3044 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
76ad4f0e
S
3045
3046 /* Prefetch first cache line of first page
3047 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
3048 * line size is 64B so need to prefetch twice to make it 128B. But in
3049 * actual we can have greater size of caches with 128B Level 1 cache
3050 * lines. In such a case, single fetch would suffice to cache in the
3051 * relevant part of the header.
3052 */
e5597095 3053 prefetch(ring->va);
76ad4f0e 3054#if L1_CACHE_BYTES < 128
e5597095 3055 prefetch(ring->va + L1_CACHE_BYTES);
76ad4f0e
S
3056#endif
3057
e5597095
PL
3058 if (!skb) {
3059 ret = hns3_alloc_skb(ring, length, ring->va);
d35bced8 3060 skb = ring->skb;
76ad4f0e 3061
e5597095
PL
3062 if (ret < 0) /* alloc buffer fail */
3063 return ret;
3064 if (ret > 0) { /* need add frag */
d35bced8 3065 ret = hns3_add_frag(ring, desc, false);
e5597095
PL
3066 if (ret)
3067 return ret;
76ad4f0e 3068
e5597095
PL
3069 /* As the head data may be changed when GRO enable, copy
3070 * the head data in after other data rx completed
3071 */
3072 memcpy(skb->data, ring->va,
3073 ALIGN(ring->pull_len, sizeof(long)));
3074 }
76ad4f0e 3075 } else {
d35bced8 3076 ret = hns3_add_frag(ring, desc, true);
e5597095
PL
3077 if (ret)
3078 return ret;
76ad4f0e 3079
e5597095
PL
3080 /* As the head data may be changed when GRO enable, copy
3081 * the head data in after other data rx completed
3082 */
3083 memcpy(skb->data, ring->va,
3084 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e
S
3085 }
3086
ea485867 3087 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 3088 if (unlikely(ret)) {
76ad4f0e 3089 dev_kfree_skb_any(skb);
d474d88f 3090 return ret;
76ad4f0e
S
3091 }
3092
d93ed94f 3093 skb_record_rx_queue(skb, ring->tqp->tqp_index);
76ad4f0e
S
3094 return 0;
3095}
3096
9b2f3477
WL
3097int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3098 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S
3099{
3100#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
63380a1a 3101 int unused_count = hns3_desc_unused(ring);
a4ee7624
YL
3102 int recv_pkts = 0;
3103 int recv_bds = 0;
3104 int err, num;
76ad4f0e
S
3105
3106 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
76ad4f0e 3107 num -= unused_count;
63380a1a 3108 unused_count -= ring->pending_buf;
76ad4f0e 3109
88b7c58c
YL
3110 if (num <= 0)
3111 goto out;
3112
3113 rmb(); /* Make sure num taken effect before the other data is touched */
3114
76ad4f0e
S
3115 while (recv_pkts < budget && recv_bds < num) {
3116 /* Reuse or realloc buffers */
a4ee7624
YL
3117 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3118 hns3_nic_alloc_rx_buffers(ring, unused_count);
e5597095
PL
3119 unused_count = hns3_desc_unused(ring) -
3120 ring->pending_buf;
76ad4f0e
S
3121 }
3122
3123 /* Poll one pkt */
d35bced8
YL
3124 err = hns3_handle_rx_bd(ring);
3125 /* Do not get FE for the packet or failed to alloc skb */
3126 if (unlikely(!ring->skb || err == -ENXIO)) {
76ad4f0e 3127 goto out;
d35bced8
YL
3128 } else if (likely(!err)) {
3129 rx_fn(ring, ring->skb);
3130 recv_pkts++;
76ad4f0e
S
3131 }
3132
e5597095 3133 recv_bds += ring->pending_buf;
a4ee7624 3134 unused_count += ring->pending_buf;
e5597095
PL
3135 ring->skb = NULL;
3136 ring->pending_buf = 0;
76ad4f0e
S
3137 }
3138
3139out:
3140 /* Make all data has been write before submit */
a4ee7624
YL
3141 if (unused_count > 0)
3142 hns3_nic_alloc_rx_buffers(ring, unused_count);
76ad4f0e
S
3143
3144 return recv_pkts;
3145}
3146
4a43caf5 3147static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
76ad4f0e 3148{
4a43caf5
YL
3149#define HNS3_RX_LOW_BYTE_RATE 10000
3150#define HNS3_RX_MID_BYTE_RATE 20000
3151#define HNS3_RX_ULTRA_PACKET_RATE 40
3152
76ad4f0e 3153 enum hns3_flow_level_range new_flow_level;
4a43caf5
YL
3154 struct hns3_enet_tqp_vector *tqp_vector;
3155 int packets_per_msecs, bytes_per_msecs;
a95e1f86 3156 u32 time_passed_ms;
76ad4f0e 3157
4a43caf5 3158 tqp_vector = ring_group->ring->tqp_vector;
a95e1f86
FL
3159 time_passed_ms =
3160 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
a95e1f86
FL
3161 if (!time_passed_ms)
3162 return false;
3163
3164 do_div(ring_group->total_packets, time_passed_ms);
3165 packets_per_msecs = ring_group->total_packets;
3166
3167 do_div(ring_group->total_bytes, time_passed_ms);
3168 bytes_per_msecs = ring_group->total_bytes;
3169
4a43caf5 3170 new_flow_level = ring_group->coal.flow_level;
76ad4f0e 3171
4a43caf5
YL
3172 /* Simple throttlerate management
3173 * 0-10MB/s lower (50000 ints/s)
3174 * 10-20MB/s middle (20000 ints/s)
3175 * 20-1249MB/s high (18000 ints/s)
3176 * > 40000pps ultra (8000 ints/s)
3177 */
76ad4f0e
S
3178 switch (new_flow_level) {
3179 case HNS3_FLOW_LOW:
a95e1f86 3180 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S
3181 new_flow_level = HNS3_FLOW_MID;
3182 break;
3183 case HNS3_FLOW_MID:
a95e1f86 3184 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 3185 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 3186 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S
3187 new_flow_level = HNS3_FLOW_LOW;
3188 break;
3189 case HNS3_FLOW_HIGH:
3190 case HNS3_FLOW_ULTRA:
3191 default:
a95e1f86 3192 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S
3193 new_flow_level = HNS3_FLOW_MID;
3194 break;
3195 }
3196
a95e1f86
FL
3197 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3198 &tqp_vector->rx_group == ring_group)
76ad4f0e
S
3199 new_flow_level = HNS3_FLOW_ULTRA;
3200
4a43caf5
YL
3201 ring_group->total_bytes = 0;
3202 ring_group->total_packets = 0;
3203 ring_group->coal.flow_level = new_flow_level;
3204
3205 return true;
3206}
3207
3208static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3209{
3210 struct hns3_enet_tqp_vector *tqp_vector;
3211 u16 new_int_gl;
3212
3213 if (!ring_group->ring)
3214 return false;
3215
3216 tqp_vector = ring_group->ring->tqp_vector;
3217 if (!tqp_vector->last_jiffies)
3218 return false;
3219
3220 if (ring_group->total_packets == 0) {
3221 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3222 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3223 return true;
3224 }
3225
3226 if (!hns3_get_new_flow_lvl(ring_group))
3227 return false;
3228
3229 new_int_gl = ring_group->coal.int_gl;
3230 switch (ring_group->coal.flow_level) {
76ad4f0e
S
3231 case HNS3_FLOW_LOW:
3232 new_int_gl = HNS3_INT_GL_50K;
3233 break;
3234 case HNS3_FLOW_MID:
3235 new_int_gl = HNS3_INT_GL_20K;
3236 break;
3237 case HNS3_FLOW_HIGH:
3238 new_int_gl = HNS3_INT_GL_18K;
3239 break;
3240 case HNS3_FLOW_ULTRA:
3241 new_int_gl = HNS3_INT_GL_8K;
3242 break;
3243 default:
3244 break;
3245 }
3246
9bc727a9
YL
3247 if (new_int_gl != ring_group->coal.int_gl) {
3248 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S
3249 return true;
3250 }
3251 return false;
3252}
3253
3254static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3255{
8b1ff1ea
FL
3256 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3257 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3258 bool rx_update, tx_update;
3259
7445565c
PL
3260 /* update param every 1000ms */
3261 if (time_before(jiffies,
3262 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 3263 return;
cd9d187b 3264
9bc727a9 3265 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL
3266 rx_update = hns3_get_new_int_gl(rx_group);
3267 if (rx_update)
3268 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 3269 rx_group->coal.int_gl);
8b1ff1ea
FL
3270 }
3271
9bc727a9 3272 if (tx_group->coal.gl_adapt_enable) {
9e50dc11 3273 tx_update = hns3_get_new_int_gl(tx_group);
8b1ff1ea
FL
3274 if (tx_update)
3275 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 3276 tx_group->coal.int_gl);
76ad4f0e 3277 }
cd9d187b 3278
a95e1f86 3279 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S
3280}
3281
3282static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3283{
ff0699e0 3284 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S
3285 struct hns3_enet_ring *ring;
3286 int rx_pkt_total = 0;
3287
3288 struct hns3_enet_tqp_vector *tqp_vector =
3289 container_of(napi, struct hns3_enet_tqp_vector, napi);
3290 bool clean_complete = true;
ceca4a5e 3291 int rx_budget = budget;
76ad4f0e 3292
ff0699e0
HT
3293 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3294 napi_complete(napi);
3295 return 0;
3296 }
3297
76ad4f0e
S
3298 /* Since the actual Tx work is minimal, we can give the Tx a larger
3299 * budget and be more aggressive about cleaning up the Tx descriptors.
3300 */
799997a3
PL
3301 hns3_for_each_ring(ring, tqp_vector->tx_group)
3302 hns3_clean_tx_ring(ring);
76ad4f0e
S
3303
3304 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL
3305 if (tqp_vector->num_tqps > 1)
3306 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S
3307
3308 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL
3309 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3310 hns3_rx_skb);
76ad4f0e
S
3311
3312 if (rx_cleaned >= rx_budget)
3313 clean_complete = false;
3314
3315 rx_pkt_total += rx_cleaned;
3316 }
3317
3318 tqp_vector->rx_group.total_packets += rx_pkt_total;
3319
3320 if (!clean_complete)
3321 return budget;
3322
531eba0f
HT
3323 if (napi_complete(napi) &&
3324 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT
3325 hns3_update_new_int_gl(tqp_vector);
3326 hns3_mask_vector_irq(tqp_vector, 1);
3327 }
76ad4f0e
S
3328
3329 return rx_pkt_total;
3330}
3331
3332static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3333 struct hnae3_ring_chain_node *head)
3334{
3335 struct pci_dev *pdev = tqp_vector->handle->pdev;
3336 struct hnae3_ring_chain_node *cur_chain = head;
3337 struct hnae3_ring_chain_node *chain;
3338 struct hns3_enet_ring *tx_ring;
3339 struct hns3_enet_ring *rx_ring;
3340
3341 tx_ring = tqp_vector->tx_group.ring;
3342 if (tx_ring) {
3343 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL
3344 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3345 HNAE3_RING_TYPE_TX);
3346 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3347 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S
3348
3349 cur_chain->next = NULL;
3350
3351 while (tx_ring->next) {
3352 tx_ring = tx_ring->next;
3353
3354 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3355 GFP_KERNEL);
3356 if (!chain)
73b907a0 3357 goto err_free_chain;
76ad4f0e
S
3358
3359 cur_chain->next = chain;
3360 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL
3361 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3362 HNAE3_RING_TYPE_TX);
3363 hnae3_set_field(chain->int_gl_idx,
3364 HNAE3_RING_GL_IDX_M,
3365 HNAE3_RING_GL_IDX_S,
3366 HNAE3_RING_GL_TX);
76ad4f0e
S
3367
3368 cur_chain = chain;
3369 }
3370 }
3371
3372 rx_ring = tqp_vector->rx_group.ring;
3373 if (!tx_ring && rx_ring) {
3374 cur_chain->next = NULL;
3375 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL
3376 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3377 HNAE3_RING_TYPE_RX);
3378 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3379 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S
3380
3381 rx_ring = rx_ring->next;
3382 }
3383
3384 while (rx_ring) {
3385 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3386 if (!chain)
73b907a0 3387 goto err_free_chain;
76ad4f0e
S
3388
3389 cur_chain->next = chain;
3390 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL
3391 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3392 HNAE3_RING_TYPE_RX);
3393 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3394 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 3395
76ad4f0e
S
3396 cur_chain = chain;
3397
3398 rx_ring = rx_ring->next;
3399 }
3400
3401 return 0;
73b907a0
HT
3402
3403err_free_chain:
3404 cur_chain = head->next;
3405 while (cur_chain) {
3406 chain = cur_chain->next;
cda69d24 3407 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT
3408 cur_chain = chain;
3409 }
cda69d24 3410 head->next = NULL;
73b907a0
HT
3411
3412 return -ENOMEM;
76ad4f0e
S
3413}
3414
3415static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3416 struct hnae3_ring_chain_node *head)
3417{
3418 struct pci_dev *pdev = tqp_vector->handle->pdev;
3419 struct hnae3_ring_chain_node *chain_tmp, *chain;
3420
3421 chain = head->next;
3422
3423 while (chain) {
3424 chain_tmp = chain->next;
3425 devm_kfree(&pdev->dev, chain);
3426 chain = chain_tmp;
3427 }
3428}
3429
3430static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3431 struct hns3_enet_ring *ring)
3432{
3433 ring->next = group->ring;
3434 group->ring = ring;
3435
3436 group->count++;
3437}
3438
874bff0b
PL
3439static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3440{
3441 struct pci_dev *pdev = priv->ae_handle->pdev;
3442 struct hns3_enet_tqp_vector *tqp_vector;
3443 int num_vectors = priv->vector_num;
3444 int numa_node;
3445 int vector_i;
3446
3447 numa_node = dev_to_node(&pdev->dev);
3448
3449 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3450 tqp_vector = &priv->tqp_vector[vector_i];
3451 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3452 &tqp_vector->affinity_mask);
3453 }
3454}
3455
76ad4f0e
S
3456static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3457{
3458 struct hnae3_ring_chain_node vector_ring_chain;
3459 struct hnae3_handle *h = priv->ae_handle;
3460 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3461 int ret = 0;
ece4bf46 3462 int i;
76ad4f0e 3463
874bff0b
PL
3464 hns3_nic_set_cpumask(priv);
3465
dd38c726
YL
3466 for (i = 0; i < priv->vector_num; i++) {
3467 tqp_vector = &priv->tqp_vector[i];
3468 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3469 tqp_vector->num_tqps = 0;
3470 }
76ad4f0e 3471
dd38c726
YL
3472 for (i = 0; i < h->kinfo.num_tqps; i++) {
3473 u16 vector_i = i % priv->vector_num;
3474 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S
3475
3476 tqp_vector = &priv->tqp_vector[vector_i];
3477
3478 hns3_add_ring_to_group(&tqp_vector->tx_group,
5f06b903 3479 &priv->ring[i]);
76ad4f0e
S
3480
3481 hns3_add_ring_to_group(&tqp_vector->rx_group,
5f06b903 3482 &priv->ring[i + tqp_num]);
76ad4f0e 3483
5f06b903
YL
3484 priv->ring[i].tqp_vector = tqp_vector;
3485 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
dd38c726 3486 tqp_vector->num_tqps++;
76ad4f0e
S
3487 }
3488
dd38c726 3489 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S
3490 tqp_vector = &priv->tqp_vector[i];
3491
3492 tqp_vector->rx_group.total_bytes = 0;
3493 tqp_vector->rx_group.total_packets = 0;
3494 tqp_vector->tx_group.total_bytes = 0;
3495 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S
3496 tqp_vector->handle = h;
3497
3498 ret = hns3_get_vector_ring_chain(tqp_vector,
3499 &vector_ring_chain);
3500 if (ret)
cda69d24 3501 goto map_ring_fail;
76ad4f0e
S
3502
3503 ret = h->ae_algo->ops->map_ring_to_vector(h,
3504 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S
3505
3506 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3507
dd38c726 3508 if (ret)
ece4bf46 3509 goto map_ring_fail;
dd38c726 3510
76ad4f0e
S
3511 netif_napi_add(priv->netdev, &tqp_vector->napi,
3512 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3513 }
3514
dd38c726 3515 return 0;
ece4bf46
HT
3516
3517map_ring_fail:
3518 while (i--)
3519 netif_napi_del(&priv->tqp_vector[i].napi);
3520
3521 return ret;
dd38c726
YL
3522}
3523
3524static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3525{
75edb610
JS
3526#define HNS3_VECTOR_PF_MAX_NUM 64
3527
dd38c726
YL
3528 struct hnae3_handle *h = priv->ae_handle;
3529 struct hns3_enet_tqp_vector *tqp_vector;
3530 struct hnae3_vector_info *vector;
3531 struct pci_dev *pdev = h->pdev;
3532 u16 tqp_num = h->kinfo.num_tqps;
3533 u16 vector_num;
3534 int ret = 0;
3535 u16 i;
3536
3537 /* RSS size, cpu online and vector_num should be the same */
3538 /* Should consider 2p/4p later */
3539 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610
JS
3540 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3541
dd38c726
YL
3542 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3543 GFP_KERNEL);
3544 if (!vector)
3545 return -ENOMEM;
3546
9b2f3477 3547 /* save the actual available vector number */
dd38c726
YL
3548 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3549
3550 priv->vector_num = vector_num;
3551 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3552 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3553 GFP_KERNEL);
3554 if (!priv->tqp_vector) {
3555 ret = -ENOMEM;
3556 goto out;
3557 }
3558
3559 for (i = 0; i < priv->vector_num; i++) {
3560 tqp_vector = &priv->tqp_vector[i];
3561 tqp_vector->idx = i;
3562 tqp_vector->mask_addr = vector[i].io_addr;
3563 tqp_vector->vector_irq = vector[i].vector;
3564 hns3_vector_gl_rl_init(tqp_vector, priv);
3565 }
3566
76ad4f0e
S
3567out:
3568 devm_kfree(&pdev->dev, vector);
3569 return ret;
3570}
3571
dd38c726
YL
3572static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3573{
3574 group->ring = NULL;
3575 group->count = 0;
3576}
3577
e2152785 3578static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S
3579{
3580 struct hnae3_ring_chain_node vector_ring_chain;
3581 struct hnae3_handle *h = priv->ae_handle;
3582 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 3583 int i;
76ad4f0e
S
3584
3585 for (i = 0; i < priv->vector_num; i++) {
3586 tqp_vector = &priv->tqp_vector[i];
3587
2c9dd668
HT
3588 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3589 continue;
3590
e2152785 3591 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain);
76ad4f0e 3592
e2152785 3593 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 3594 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S
3595
3596 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3597
ae6017a7 3598 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
ae6017a7
HT
3599 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3600 free_irq(tqp_vector->vector_irq, tqp_vector);
3601 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
76ad4f0e
S
3602 }
3603
dd38c726
YL
3604 hns3_clear_ring_group(&tqp_vector->rx_group);
3605 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S
3606 netif_napi_del(&priv->tqp_vector[i].napi);
3607 }
dd38c726
YL
3608}
3609
3610static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3611{
3612 struct hnae3_handle *h = priv->ae_handle;
3613 struct pci_dev *pdev = h->pdev;
3614 int i, ret;
3615
3616 for (i = 0; i < priv->vector_num; i++) {
3617 struct hns3_enet_tqp_vector *tqp_vector;
3618
3619 tqp_vector = &priv->tqp_vector[i];
3620 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3621 if (ret)
3622 return ret;
3623 }
76ad4f0e 3624
dd38c726 3625 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S
3626 return 0;
3627}
3628
5f06b903
YL
3629static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3630 unsigned int ring_type)
76ad4f0e 3631{
76ad4f0e 3632 int queue_num = priv->ae_handle->kinfo.num_tqps;
76ad4f0e 3633 struct hns3_enet_ring *ring;
c0425944 3634 int desc_num;
76ad4f0e 3635
76ad4f0e 3636 if (ring_type == HNAE3_RING_TYPE_TX) {
5f06b903 3637 ring = &priv->ring[q->tqp_index];
c0425944 3638 desc_num = priv->ae_handle->kinfo.num_tx_desc;
5f06b903 3639 ring->queue_index = q->tqp_index;
76ad4f0e
S
3640 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3641 } else {
5f06b903 3642 ring = &priv->ring[q->tqp_index + queue_num];
c0425944 3643 desc_num = priv->ae_handle->kinfo.num_rx_desc;
5f06b903 3644 ring->queue_index = q->tqp_index;
76ad4f0e
S
3645 ring->io_base = q->io_base;
3646 }
3647
e4e87715 3648 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3649
76ad4f0e
S
3650 ring->tqp = q;
3651 ring->desc = NULL;
3652 ring->desc_cb = NULL;
3653 ring->dev = priv->dev;
3654 ring->desc_dma_addr = 0;
3655 ring->buf_size = q->buf_size;
2c9dd668 3656 ring->desc_num = desc_num;
76ad4f0e
S
3657 ring->next_to_use = 0;
3658 ring->next_to_clean = 0;
76ad4f0e
S
3659}
3660
5f06b903
YL
3661static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3662 struct hns3_nic_priv *priv)
76ad4f0e 3663{
5f06b903
YL
3664 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3665 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
76ad4f0e
S
3666}
3667
3668static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3669{
3670 struct hnae3_handle *h = priv->ae_handle;
3671 struct pci_dev *pdev = h->pdev;
5f06b903 3672 int i;
76ad4f0e 3673
5f06b903
YL
3674 priv->ring = devm_kzalloc(&pdev->dev,
3675 array3_size(h->kinfo.num_tqps,
3676 sizeof(*priv->ring), 2),
3677 GFP_KERNEL);
3678 if (!priv->ring)
76ad4f0e
S
3679 return -ENOMEM;
3680
5f06b903
YL
3681 for (i = 0; i < h->kinfo.num_tqps; i++)
3682 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
76ad4f0e
S
3683
3684 return 0;
76ad4f0e
S
3685}
3686
09f2af64
PL
3687static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3688{
5f06b903 3689 if (!priv->ring)
7b8f622e
HT
3690 return;
3691
5f06b903
YL
3692 devm_kfree(priv->dev, priv->ring);
3693 priv->ring = NULL;
09f2af64
PL
3694}
3695
76ad4f0e
S
3696static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3697{
3698 int ret;
3699
3700 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3701 return -EINVAL;
3702
77296bf6
YL
3703 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3704 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S
3705 if (!ring->desc_cb) {
3706 ret = -ENOMEM;
3707 goto out;
3708 }
3709
3710 ret = hns3_alloc_desc(ring);
3711 if (ret)
3712 goto out_with_desc_cb;
3713
3714 if (!HNAE3_IS_TX_RING(ring)) {
3715 ret = hns3_alloc_ring_buffers(ring);
3716 if (ret)
3717 goto out_with_desc;
3718 }
3719
3720 return 0;
3721
3722out_with_desc:
3723 hns3_free_desc(ring);
3724out_with_desc_cb:
77296bf6 3725 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S
3726 ring->desc_cb = NULL;
3727out:
3728 return ret;
3729}
3730
a723fb8e 3731void hns3_fini_ring(struct hns3_enet_ring *ring)
76ad4f0e
S
3732{
3733 hns3_free_desc(ring);
77296bf6 3734 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S
3735 ring->desc_cb = NULL;
3736 ring->next_to_clean = 0;
3737 ring->next_to_use = 0;
ac574b80
PL
3738 ring->pending_buf = 0;
3739 if (ring->skb) {
3740 dev_kfree_skb_any(ring->skb);
3741 ring->skb = NULL;
3742 }
76ad4f0e
S
3743}
3744
1db9b1bf 3745static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S
3746{
3747 int bd_size_type;
3748
3749 switch (buf_size) {
3750 case 512:
3751 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3752 break;
3753 case 1024:
3754 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3755 break;
3756 case 2048:
3757 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3758 break;
3759 case 4096:
3760 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3761 break;
3762 default:
3763 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3764 }
3765
3766 return bd_size_type;
3767}
3768
3769static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3770{
3771 dma_addr_t dma = ring->desc_dma_addr;
3772 struct hnae3_queue *q = ring->tqp;
3773
3774 if (!HNAE3_IS_TX_RING(ring)) {
9b2f3477 3775 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
76ad4f0e
S
3776 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3777 (u32)((dma >> 31) >> 1));
3778
3779 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3780 hns3_buf_size2type(ring->buf_size));
3781 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3782 ring->desc_num / 8 - 1);
3783
3784 } else {
3785 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3786 (u32)dma);
3787 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3788 (u32)((dma >> 31) >> 1));
3789
76ad4f0e
S
3790 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3791 ring->desc_num / 8 - 1);
3792 }
3793}
3794
1c772154
YL
3795static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3796{
3797 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3798 int i;
3799
3800 for (i = 0; i < HNAE3_MAX_TC; i++) {
3801 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3802 int j;
3803
3804 if (!tc_info->enable)
3805 continue;
3806
3807 for (j = 0; j < tc_info->tqp_count; j++) {
3808 struct hnae3_queue *q;
3809
5f06b903 3810 q = priv->ring[tc_info->tqp_offset + j].tqp;
1c772154
YL
3811 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3812 tc_info->tc);
3813 }
3814 }
3815}
3816
5668abda 3817int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S
3818{
3819 struct hnae3_handle *h = priv->ae_handle;
3820 int ring_num = h->kinfo.num_tqps * 2;
3821 int i, j;
3822 int ret;
3823
3824 for (i = 0; i < ring_num; i++) {
5f06b903 3825 ret = hns3_alloc_ring_memory(&priv->ring[i]);
76ad4f0e
S
3826 if (ret) {
3827 dev_err(priv->dev,
3828 "Alloc ring memory fail! ret=%d\n", ret);
3829 goto out_when_alloc_ring_memory;
3830 }
3831
5f06b903 3832 u64_stats_init(&priv->ring[i].syncp);
76ad4f0e
S
3833 }
3834
3835 return 0;
3836
3837out_when_alloc_ring_memory:
3838 for (j = i - 1; j >= 0; j--)
5f06b903 3839 hns3_fini_ring(&priv->ring[j]);
76ad4f0e
S
3840
3841 return -ENOMEM;
3842}
3843
5668abda 3844int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S
3845{
3846 struct hnae3_handle *h = priv->ae_handle;
3847 int i;
3848
3849 for (i = 0; i < h->kinfo.num_tqps; i++) {
5f06b903
YL
3850 hns3_fini_ring(&priv->ring[i]);
3851 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
76ad4f0e 3852 }
76ad4f0e
S
3853 return 0;
3854}
3855
3856/* Set mac addr if it is configured. or leave it to the AE driver */
8e6de441 3857static int hns3_init_mac_addr(struct net_device *netdev)
76ad4f0e
S
3858{
3859 struct hns3_nic_priv *priv = netdev_priv(netdev);
3860 struct hnae3_handle *h = priv->ae_handle;
3861 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 3862 int ret = 0;
76ad4f0e 3863
8e6de441 3864 if (h->ae_algo->ops->get_mac_addr)
76ad4f0e 3865 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
76ad4f0e
S
3866
3867 /* Check if the MAC address is valid, if not get a random one */
8e6de441 3868 if (!is_valid_ether_addr(mac_addr_temp)) {
76ad4f0e
S
3869 eth_hw_addr_random(netdev);
3870 dev_warn(priv->dev, "using random MAC address %pM\n",
3871 netdev->dev_addr);
8e6de441
HT
3872 } else {
3873 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3874 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
76ad4f0e 3875 }
139e8792
L
3876
3877 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 3878 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3879
7fa6be4f 3880 return ret;
76ad4f0e
S
3881}
3882
c8a8045b
HT
3883static int hns3_init_phy(struct net_device *netdev)
3884{
3885 struct hnae3_handle *h = hns3_get_handle(netdev);
3886 int ret = 0;
3887
3888 if (h->ae_algo->ops->mac_connect_phy)
3889 ret = h->ae_algo->ops->mac_connect_phy(h);
3890
3891 return ret;
3892}
3893
3894static void hns3_uninit_phy(struct net_device *netdev)
3895{
3896 struct hnae3_handle *h = hns3_get_handle(netdev);
3897
3898 if (h->ae_algo->ops->mac_disconnect_phy)
3899 h->ae_algo->ops->mac_disconnect_phy(h);
3900}
3901
6871af29
JS
3902static int hns3_restore_fd_rules(struct net_device *netdev)
3903{
3904 struct hnae3_handle *h = hns3_get_handle(netdev);
3905 int ret = 0;
3906
3907 if (h->ae_algo->ops->restore_fd_rules)
3908 ret = h->ae_algo->ops->restore_fd_rules(h);
3909
3910 return ret;
3911}
3912
3913static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3914{
3915 struct hnae3_handle *h = hns3_get_handle(netdev);
3916
3917 if (h->ae_algo->ops->del_all_fd_entries)
3918 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3919}
3920
a6d818e3
YL
3921static int hns3_client_start(struct hnae3_handle *handle)
3922{
3923 if (!handle->ae_algo->ops->client_start)
3924 return 0;
3925
3926 return handle->ae_algo->ops->client_start(handle);
3927}
3928
3929static void hns3_client_stop(struct hnae3_handle *handle)
3930{
3931 if (!handle->ae_algo->ops->client_stop)
3932 return;
3933
3934 handle->ae_algo->ops->client_stop(handle);
3935}
3936
bb87be87
YL
3937static void hns3_info_show(struct hns3_nic_priv *priv)
3938{
3939 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3940
3941 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
adcf738b
GL
3942 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
3943 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
3944 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
3945 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
3946 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
3947 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
3948 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
3949 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
bb87be87
YL
3950}
3951
76ad4f0e
S
3952static int hns3_client_init(struct hnae3_handle *handle)
3953{
3954 struct pci_dev *pdev = handle->pdev;
0d43bf45 3955 u16 alloc_tqps, max_rss_size;
76ad4f0e
S
3956 struct hns3_nic_priv *priv;
3957 struct net_device *netdev;
3958 int ret;
3959
0d43bf45
HT
3960 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3961 &max_rss_size);
3962 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S
3963 if (!netdev)
3964 return -ENOMEM;
3965
3966 priv = netdev_priv(netdev);
3967 priv->dev = &pdev->dev;
3968 priv->netdev = netdev;
3969 priv->ae_handle = handle;
f8fa222c 3970 priv->tx_timeout_count = 0;
b7b585c2 3971 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 3972
bb87be87
YL
3973 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3974
76ad4f0e
S
3975 handle->kinfo.netdev = netdev;
3976 handle->priv = (void *)priv;
3977
8e6de441 3978 hns3_init_mac_addr(netdev);
76ad4f0e
S
3979
3980 hns3_set_default_feature(netdev);
3981
3982 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3983 netdev->priv_flags |= IFF_UNICAST_FLT;
3984 netdev->netdev_ops = &hns3_nic_netdev_ops;
3985 SET_NETDEV_DEV(netdev, &pdev->dev);
3986 hns3_ethtool_set_ops(netdev);
76ad4f0e
S
3987
3988 /* Carrier off reporting is important to ethtool even BEFORE open */
3989 netif_carrier_off(netdev);
3990
3991 ret = hns3_get_ring_config(priv);
3992 if (ret) {
3993 ret = -ENOMEM;
3994 goto out_get_ring_cfg;
3995 }
3996
dd38c726
YL
3997 ret = hns3_nic_alloc_vector_data(priv);
3998 if (ret) {
3999 ret = -ENOMEM;
4000 goto out_alloc_vector_data;
4001 }
4002
76ad4f0e
S
4003 ret = hns3_nic_init_vector_data(priv);
4004 if (ret) {
4005 ret = -ENOMEM;
4006 goto out_init_vector_data;
4007 }
4008
4009 ret = hns3_init_all_ring(priv);
4010 if (ret) {
4011 ret = -ENOMEM;
5f06b903 4012 goto out_init_ring;
76ad4f0e
S
4013 }
4014
c8a8045b
HT
4015 ret = hns3_init_phy(netdev);
4016 if (ret)
4017 goto out_init_phy;
4018
76ad4f0e
S
4019 ret = register_netdev(netdev);
4020 if (ret) {
4021 dev_err(priv->dev, "probe register netdev fail!\n");
4022 goto out_reg_netdev_fail;
4023 }
4024
a6d818e3
YL
4025 ret = hns3_client_start(handle);
4026 if (ret) {
4027 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
bf6de231 4028 goto out_client_start;
a6d818e3
YL
4029 }
4030
986743db
YL
4031 hns3_dcbnl_setup(handle);
4032
b2292360 4033 hns3_dbg_init(handle);
4034
a0b43717 4035 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 4036 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 4037
814da63c
HT
4038 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4039
bb87be87
YL
4040 if (netif_msg_drv(handle))
4041 hns3_info_show(priv);
4042
76ad4f0e
S
4043 return ret;
4044
18655128
HT
4045out_client_start:
4046 unregister_netdev(netdev);
76ad4f0e 4047out_reg_netdev_fail:
c8a8045b
HT
4048 hns3_uninit_phy(netdev);
4049out_init_phy:
4050 hns3_uninit_all_ring(priv);
5f06b903 4051out_init_ring:
e2152785 4052 hns3_nic_uninit_vector_data(priv);
76ad4f0e 4053out_init_vector_data:
dd38c726
YL
4054 hns3_nic_dealloc_vector_data(priv);
4055out_alloc_vector_data:
5f06b903 4056 priv->ring = NULL;
76ad4f0e
S
4057out_get_ring_cfg:
4058 priv->ae_handle = NULL;
4059 free_netdev(netdev);
4060 return ret;
4061}
4062
4063static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4064{
4065 struct net_device *netdev = handle->kinfo.netdev;
4066 struct hns3_nic_priv *priv = netdev_priv(netdev);
4067 int ret;
4068
f05e2109
JS
4069 hns3_remove_hw_addr(netdev);
4070
76ad4f0e
S
4071 if (netdev->reg_state != NETREG_UNINITIALIZED)
4072 unregister_netdev(netdev);
4073
eb32c896
HT
4074 hns3_client_stop(handle);
4075
0d2f68c7
HT
4076 hns3_uninit_phy(netdev);
4077
814da63c
HT
4078 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4079 netdev_warn(netdev, "already uninitialized\n");
4080 goto out_netdev_free;
4081 }
4082
dc5e6064
JS
4083 hns3_del_all_fd_rules(netdev, true);
4084
f96315f2 4085 hns3_clear_all_ring(handle, true);
7b763f3f 4086
e2152785 4087 hns3_nic_uninit_vector_data(priv);
76ad4f0e 4088
dd38c726
YL
4089 ret = hns3_nic_dealloc_vector_data(priv);
4090 if (ret)
4091 netdev_err(netdev, "dealloc vector error\n");
4092
76ad4f0e
S
4093 ret = hns3_uninit_all_ring(priv);
4094 if (ret)
4095 netdev_err(netdev, "uninit ring error\n");
4096
ec777890
YL
4097 hns3_put_ring_config(priv);
4098
b2292360 4099 hns3_dbg_uninit(handle);
4100
814da63c 4101out_netdev_free:
76ad4f0e
S
4102 free_netdev(netdev);
4103}
4104
4105static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4106{
4107 struct net_device *netdev = handle->kinfo.netdev;
4108
4109 if (!netdev)
4110 return;
4111
4112 if (linkup) {
4113 netif_carrier_on(netdev);
4114 netif_tx_wake_all_queues(netdev);
bb87be87
YL
4115 if (netif_msg_link(handle))
4116 netdev_info(netdev, "link up\n");
76ad4f0e
S
4117 } else {
4118 netif_carrier_off(netdev);
4119 netif_tx_stop_all_queues(netdev);
bb87be87
YL
4120 if (netif_msg_link(handle))
4121 netdev_info(netdev, "link down\n");
76ad4f0e
S
4122 }
4123}
4124
9df8f79a
YL
4125static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4126{
4127 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4128 struct net_device *ndev = kinfo->netdev;
9df8f79a
YL
4129
4130 if (tc > HNAE3_MAX_TC)
4131 return -EINVAL;
4132
4133 if (!ndev)
4134 return -ENODEV;
4135
a1ef124e 4136 return hns3_nic_set_real_num_queue(ndev);
9df8f79a
YL
4137}
4138
7fa6be4f 4139static int hns3_recover_hw_addr(struct net_device *ndev)
bb6b94a8
L
4140{
4141 struct netdev_hw_addr_list *list;
4142 struct netdev_hw_addr *ha, *tmp;
7fa6be4f 4143 int ret = 0;
bb6b94a8 4144
389775a6 4145 netif_addr_lock_bh(ndev);
bb6b94a8
L
4146 /* go through and sync uc_addr entries to the device */
4147 list = &ndev->uc;
7fa6be4f
HT
4148 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4149 ret = hns3_nic_uc_sync(ndev, ha->addr);
4150 if (ret)
389775a6 4151 goto out;
7fa6be4f 4152 }
bb6b94a8
L
4153
4154 /* go through and sync mc_addr entries to the device */
4155 list = &ndev->mc;
7fa6be4f
HT
4156 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4157 ret = hns3_nic_mc_sync(ndev, ha->addr);
4158 if (ret)
389775a6 4159 goto out;
7fa6be4f
HT
4160 }
4161
389775a6
JS
4162out:
4163 netif_addr_unlock_bh(ndev);
7fa6be4f 4164 return ret;
bb6b94a8
L
4165}
4166
f05e2109
JS
4167static void hns3_remove_hw_addr(struct net_device *netdev)
4168{
4169 struct netdev_hw_addr_list *list;
4170 struct netdev_hw_addr *ha, *tmp;
4171
4172 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
4173
389775a6 4174 netif_addr_lock_bh(netdev);
f05e2109
JS
4175 /* go through and unsync uc_addr entries to the device */
4176 list = &netdev->uc;
4177 list_for_each_entry_safe(ha, tmp, &list->list, list)
4178 hns3_nic_uc_unsync(netdev, ha->addr);
4179
4180 /* go through and unsync mc_addr entries to the device */
4181 list = &netdev->mc;
4182 list_for_each_entry_safe(ha, tmp, &list->list, list)
4183 if (ha->refcount > 1)
4184 hns3_nic_mc_unsync(netdev, ha->addr);
389775a6
JS
4185
4186 netif_addr_unlock_bh(netdev);
f05e2109
JS
4187}
4188
beebca3a 4189static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 4190{
beebca3a 4191 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 4192 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
beebca3a
YL
4193 hns3_free_buffer_detach(ring, ring->next_to_clean);
4194 ring_ptr_move_fw(ring, next_to_clean);
4195 }
4196}
4197
7b763f3f
FL
4198static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4199{
4200 struct hns3_desc_cb res_cbs;
4201 int ret;
4202
4203 while (ring->next_to_use != ring->next_to_clean) {
4204 /* When a buffer is not reused, it's memory has been
4205 * freed in hns3_handle_rx_bd or will be freed by
4206 * stack, so we need to replace the buffer here.
4207 */
4208 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4209 ret = hns3_reserve_buffer_map(ring, &res_cbs);
4210 if (ret) {
4211 u64_stats_update_begin(&ring->syncp);
4212 ring->stats.sw_err_cnt++;
4213 u64_stats_update_end(&ring->syncp);
4214 /* if alloc new buffer fail, exit directly
4215 * and reclear in up flow.
4216 */
c8711956 4217 netdev_warn(ring_to_netdev(ring),
7b763f3f
FL
4218 "reserve buffer map failed, ret = %d\n",
4219 ret);
4220 return ret;
4221 }
9b2f3477 4222 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
7b763f3f
FL
4223 }
4224 ring_ptr_move_fw(ring, next_to_use);
4225 }
4226
cc5ff6e9
PL
4227 /* Free the pending skb in rx ring */
4228 if (ring->skb) {
4229 dev_kfree_skb_any(ring->skb);
4230 ring->skb = NULL;
4231 ring->pending_buf = 0;
4232 }
4233
7b763f3f
FL
4234 return 0;
4235}
4236
4237static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 4238{
beebca3a
YL
4239 while (ring->next_to_use != ring->next_to_clean) {
4240 /* When a buffer is not reused, it's memory has been
4241 * freed in hns3_handle_rx_bd or will be freed by
4242 * stack, so only need to unmap the buffer here.
4243 */
4244 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4245 hns3_unmap_buffer(ring,
4246 &ring->desc_cb[ring->next_to_use]);
4247 ring->desc_cb[ring->next_to_use].dma = 0;
4248 }
4249
4250 ring_ptr_move_fw(ring, next_to_use);
4251 }
bb6b94a8
L
4252}
4253
f96315f2 4254static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
bb6b94a8
L
4255{
4256 struct net_device *ndev = h->kinfo.netdev;
4257 struct hns3_nic_priv *priv = netdev_priv(ndev);
4258 u32 i;
4259
4260 for (i = 0; i < h->kinfo.num_tqps; i++) {
bb6b94a8
L
4261 struct hns3_enet_ring *ring;
4262
5f06b903 4263 ring = &priv->ring[i];
beebca3a 4264 hns3_clear_tx_ring(ring);
bb6b94a8 4265
5f06b903 4266 ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL
4267 /* Continue to clear other rings even if clearing some
4268 * rings failed.
4269 */
f96315f2
HT
4270 if (force)
4271 hns3_force_clear_rx_ring(ring);
4272 else
4273 hns3_clear_rx_ring(ring);
bb6b94a8
L
4274 }
4275}
4276
7b763f3f
FL
4277int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4278{
4279 struct net_device *ndev = h->kinfo.netdev;
4280 struct hns3_nic_priv *priv = netdev_priv(ndev);
4281 struct hns3_enet_ring *rx_ring;
4282 int i, j;
4283 int ret;
4284
4285 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT
4286 ret = h->ae_algo->ops->reset_queue(h, i);
4287 if (ret)
4288 return ret;
4289
5f06b903 4290 hns3_init_ring_hw(&priv->ring[i]);
7b763f3f
FL
4291
4292 /* We need to clear tx ring here because self test will
4293 * use the ring and will not run down before up
4294 */
5f06b903
YL
4295 hns3_clear_tx_ring(&priv->ring[i]);
4296 priv->ring[i].next_to_clean = 0;
4297 priv->ring[i].next_to_use = 0;
7b763f3f 4298
5f06b903 4299 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
7b763f3f
FL
4300 hns3_init_ring_hw(rx_ring);
4301 ret = hns3_clear_rx_ring(rx_ring);
4302 if (ret)
4303 return ret;
4304
4305 /* We can not know the hardware head and tail when this
4306 * function is called in reset flow, so we reuse all desc.
4307 */
4308 for (j = 0; j < rx_ring->desc_num; j++)
4309 hns3_reuse_buffer(rx_ring, j);
4310
4311 rx_ring->next_to_clean = 0;
4312 rx_ring->next_to_use = 0;
4313 }
4314
1c772154
YL
4315 hns3_init_tx_ring_tc(priv);
4316
7b763f3f
FL
4317 return 0;
4318}
4319
e4fd7502
HT
4320static void hns3_store_coal(struct hns3_nic_priv *priv)
4321{
4322 /* ethtool only support setting and querying one coal
46ee7350
GL
4323 * configuration for now, so save the vector 0' coal
4324 * configuration here in order to restore it.
e4fd7502
HT
4325 */
4326 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4327 sizeof(struct hns3_enet_coalesce));
4328 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4329 sizeof(struct hns3_enet_coalesce));
4330}
4331
4332static void hns3_restore_coal(struct hns3_nic_priv *priv)
4333{
4334 u16 vector_num = priv->vector_num;
4335 int i;
4336
4337 for (i = 0; i < vector_num; i++) {
4338 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4339 sizeof(struct hns3_enet_coalesce));
4340 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4341 sizeof(struct hns3_enet_coalesce));
4342 }
4343}
4344
bb6b94a8
L
4345static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4346{
7edff533 4347 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
bb6b94a8
L
4348 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4349 struct net_device *ndev = kinfo->netdev;
257e4f29
HT
4350 struct hns3_nic_priv *priv = netdev_priv(ndev);
4351
4352 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4353 return 0;
bb6b94a8 4354
7edff533
HT
4355 /* it is cumbersome for hardware to pick-and-choose entries for deletion
4356 * from table space. Hence, for function reset software intervention is
4357 * required to delete the entries
4358 */
4359 if (hns3_dev_ongoing_func_reset(ae_dev)) {
4360 hns3_remove_hw_addr(ndev);
4361 hns3_del_all_fd_rules(ndev, false);
4362 }
4363
bb6b94a8 4364 if (!netif_running(ndev))
6b1385cc 4365 return 0;
bb6b94a8
L
4366
4367 return hns3_nic_net_stop(ndev);
4368}
4369
4370static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4371{
4372 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 4373 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L
4374 int ret = 0;
4375
e8884027
HT
4376 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4377
bb6b94a8 4378 if (netif_running(kinfo->netdev)) {
e8884027 4379 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4380 if (ret) {
e8884027 4381 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8 4382 netdev_err(kinfo->netdev,
9b2f3477 4383 "net up fail, ret=%d!\n", ret);
bb6b94a8
L
4384 return ret;
4385 }
bb6b94a8
L
4386 }
4387
4388 return ret;
4389}
4390
4391static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4392{
4393 struct net_device *netdev = handle->kinfo.netdev;
4394 struct hns3_nic_priv *priv = netdev_priv(netdev);
4395 int ret;
4396
bb6b94a8
L
4397 /* Carrier off reporting is important to ethtool even BEFORE open */
4398 netif_carrier_off(netdev);
4399
2c9dd668 4400 ret = hns3_get_ring_config(priv);
862d969a
HT
4401 if (ret)
4402 return ret;
4403
2c9dd668
HT
4404 ret = hns3_nic_alloc_vector_data(priv);
4405 if (ret)
4406 goto err_put_ring;
4407
e4fd7502
HT
4408 hns3_restore_coal(priv);
4409
bb6b94a8
L
4410 ret = hns3_nic_init_vector_data(priv);
4411 if (ret)
862d969a 4412 goto err_dealloc_vector;
bb6b94a8
L
4413
4414 ret = hns3_init_all_ring(priv);
862d969a
HT
4415 if (ret)
4416 goto err_uninit_vector;
bb6b94a8 4417
cd513a69
HT
4418 ret = hns3_client_start(handle);
4419 if (ret) {
4420 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4421 goto err_uninit_ring;
4422 }
4423
814da63c
HT
4424 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4425
862d969a
HT
4426 return ret;
4427
cd513a69
HT
4428err_uninit_ring:
4429 hns3_uninit_all_ring(priv);
862d969a
HT
4430err_uninit_vector:
4431 hns3_nic_uninit_vector_data(priv);
862d969a
HT
4432err_dealloc_vector:
4433 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT
4434err_put_ring:
4435 hns3_put_ring_config(priv);
862d969a 4436
bb6b94a8
L
4437 return ret;
4438}
4439
1f609492
YL
4440static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4441{
4442 struct net_device *netdev = handle->kinfo.netdev;
4443 bool vlan_filter_enable;
4444 int ret;
4445
8e6de441 4446 ret = hns3_init_mac_addr(netdev);
1f609492
YL
4447 if (ret)
4448 return ret;
4449
4450 ret = hns3_recover_hw_addr(netdev);
4451 if (ret)
4452 return ret;
4453
4454 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4455 if (ret)
4456 return ret;
4457
4458 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4459 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4460
b524b38f
JS
4461 if (handle->ae_algo->ops->restore_vlan_table)
4462 handle->ae_algo->ops->restore_vlan_table(handle);
1f609492
YL
4463
4464 return hns3_restore_fd_rules(netdev);
4465}
4466
bb6b94a8
L
4467static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4468{
4469 struct net_device *netdev = handle->kinfo.netdev;
4470 struct hns3_nic_priv *priv = netdev_priv(netdev);
4471 int ret;
4472
1eeb3367 4473 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT
4474 netdev_warn(netdev, "already uninitialized\n");
4475 return 0;
4476 }
4477
f96315f2
HT
4478 hns3_clear_all_ring(handle, true);
4479 hns3_reset_tx_queue(priv->ae_handle);
bb6b94a8 4480
e2152785 4481 hns3_nic_uninit_vector_data(priv);
bb6b94a8 4482
e4fd7502
HT
4483 hns3_store_coal(priv);
4484
862d969a
HT
4485 ret = hns3_nic_dealloc_vector_data(priv);
4486 if (ret)
4487 netdev_err(netdev, "dealloc vector error\n");
4488
bb6b94a8
L
4489 ret = hns3_uninit_all_ring(priv);
4490 if (ret)
4491 netdev_err(netdev, "uninit ring error\n");
4492
2c9dd668 4493 hns3_put_ring_config(priv);
2c9dd668 4494
bb6b94a8
L
4495 return ret;
4496}
4497
4498static int hns3_reset_notify(struct hnae3_handle *handle,
4499 enum hnae3_reset_notify_type type)
4500{
4501 int ret = 0;
4502
4503 switch (type) {
4504 case HNAE3_UP_CLIENT:
e1586241
SM
4505 ret = hns3_reset_notify_up_enet(handle);
4506 break;
bb6b94a8
L
4507 case HNAE3_DOWN_CLIENT:
4508 ret = hns3_reset_notify_down_enet(handle);
4509 break;
4510 case HNAE3_INIT_CLIENT:
4511 ret = hns3_reset_notify_init_enet(handle);
4512 break;
4513 case HNAE3_UNINIT_CLIENT:
4514 ret = hns3_reset_notify_uninit_enet(handle);
4515 break;
1f609492
YL
4516 case HNAE3_RESTORE_CLIENT:
4517 ret = hns3_reset_notify_restore_enet(handle);
4518 break;
bb6b94a8
L
4519 default:
4520 break;
4521 }
4522
4523 return ret;
4524}
4525
3a5a5f06
PL
4526static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4527 bool rxfh_configured)
4528{
4529 int ret;
4530
4531 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4532 rxfh_configured);
4533 if (ret) {
4534 dev_err(&handle->pdev->dev,
4535 "Change tqp num(%u) fail.\n", new_tqp_num);
4536 return ret;
4537 }
4538
4539 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4540 if (ret)
4541 return ret;
4542
4543 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4544 if (ret)
4545 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4546
4547 return ret;
4548}
4549
09f2af64
PL
4550int hns3_set_channels(struct net_device *netdev,
4551 struct ethtool_channels *ch)
4552{
09f2af64
PL
4553 struct hnae3_handle *h = hns3_get_handle(netdev);
4554 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 4555 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL
4556 u32 new_tqp_num = ch->combined_count;
4557 u16 org_tqp_num;
4558 int ret;
4559
44950d28
JS
4560 if (hns3_nic_resetting(netdev))
4561 return -EBUSY;
4562
09f2af64
PL
4563 if (ch->rx_count || ch->tx_count)
4564 return -EINVAL;
4565
678335a1 4566 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 4567 new_tqp_num < 1) {
09f2af64 4568 dev_err(&netdev->dev,
adcf738b 4569 "Change tqps fail, the tqp range is from 1 to %u",
678335a1 4570 hns3_get_max_available_channels(h));
09f2af64
PL
4571 return -EINVAL;
4572 }
4573
c78b5b6c 4574 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL
4575 return 0;
4576
1c822948
YL
4577 netif_dbg(h, drv, netdev,
4578 "set channels: tqp_num=%u, rxfh=%d\n",
4579 new_tqp_num, rxfh_configured);
4580
65749f73
HT
4581 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4582 if (ret)
4583 return ret;
dd38c726 4584
65749f73
HT
4585 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4586 if (ret)
4587 return ret;
09f2af64
PL
4588
4589 org_tqp_num = h->kinfo.num_tqps;
3a5a5f06 4590 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
09f2af64 4591 if (ret) {
3a5a5f06
PL
4592 int ret1;
4593
4594 netdev_warn(netdev,
4595 "Change channels fail, revert to old value\n");
4596 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4597 if (ret1) {
4598 netdev_err(netdev,
4599 "revert to old channel fail\n");
4600 return ret1;
09f2af64 4601 }
3a5a5f06 4602
65749f73 4603 return ret;
3a5a5f06 4604 }
09f2af64 4605
3a5a5f06 4606 return 0;
09f2af64
PL
4607}
4608
a83d2961
WL
4609static const struct hns3_hw_error_info hns3_hw_err[] = {
4610 { .type = HNAE3_PPU_POISON_ERROR,
4611 .msg = "PPU poison" },
4612 { .type = HNAE3_CMDQ_ECC_ERROR,
4613 .msg = "IMP CMDQ error" },
4614 { .type = HNAE3_IMP_RD_POISON_ERROR,
4615 .msg = "IMP RD poison" },
4616};
4617
4618static void hns3_process_hw_error(struct hnae3_handle *handle,
4619 enum hnae3_hw_error_type type)
4620{
4621 int i;
4622
4623 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4624 if (hns3_hw_err[i].type == type) {
4625 dev_err(&handle->pdev->dev, "Detected %s!\n",
4626 hns3_hw_err[i].msg);
4627 break;
4628 }
4629 }
4630}
4631
1db9b1bf 4632static const struct hnae3_client_ops client_ops = {
76ad4f0e
S
4633 .init_instance = hns3_client_init,
4634 .uninit_instance = hns3_client_uninit,
4635 .link_status_change = hns3_link_status_change,
9df8f79a 4636 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4637 .reset_notify = hns3_reset_notify,
a83d2961 4638 .process_hw_error = hns3_process_hw_error,
76ad4f0e
S
4639};
4640
4641/* hns3_init_module - Driver registration routine
4642 * hns3_init_module is the first routine called when the driver is
4643 * loaded. All it does is register with the PCI subsystem.
4644 */
4645static int __init hns3_init_module(void)
4646{
4647 int ret;
4648
4649 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4650 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4651
4652 client.type = HNAE3_CLIENT_KNIC;
4653 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4654 hns3_driver_name);
4655
4656 client.ops = &client_ops;
4657
13562d1f
XW
4658 INIT_LIST_HEAD(&client.node);
4659
b2292360 4660 hns3_dbg_register_debugfs(hns3_driver_name);
4661
76ad4f0e
S
4662 ret = hnae3_register_client(&client);
4663 if (ret)
b2292360 4664 goto err_reg_client;
76ad4f0e
S
4665
4666 ret = pci_register_driver(&hns3_driver);
4667 if (ret)
b2292360 4668 goto err_reg_driver;
76ad4f0e
S
4669
4670 return ret;
b2292360 4671
4672err_reg_driver:
4673 hnae3_unregister_client(&client);
4674err_reg_client:
4675 hns3_dbg_unregister_debugfs();
4676 return ret;
76ad4f0e
S
4677}
4678module_init(hns3_init_module);
4679
4680/* hns3_exit_module - Driver exit cleanup routine
4681 * hns3_exit_module is called just before the driver is removed
4682 * from memory.
4683 */
4684static void __exit hns3_exit_module(void)
4685{
4686 pci_unregister_driver(&hns3_driver);
4687 hnae3_unregister_client(&client);
b2292360 4688 hns3_dbg_unregister_debugfs();
76ad4f0e
S
4689}
4690module_exit(hns3_exit_module);
4691
4692MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4693MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4694MODULE_LICENSE("GPL");
4695MODULE_ALIAS("pci:hns-nic");
3c7624d8 4696MODULE_VERSION(HNS3_MOD_VERSION);