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net: hns3: Unify the prefix of vf functions
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
ef57c40f
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
7#include <linux/if_vlan.h>
8#include <linux/ip.h>
9#include <linux/ipv6.h>
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/skbuff.h>
13#include <linux/sctp.h>
14#include <linux/vermagic.h>
15#include <net/gre.h>
30d240df 16#include <net/pkt_cls.h>
76ad4f0e
S		 17#include <net/vxlan.h>
18
19#include "hnae3.h"
20#include "hns3_enet.h"
21
e32a805a
FL		 22static void hns3_clear_all_ring(struct hnae3_handle *h);
23static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
24
1db9b1bf 25static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 26const char hns3_driver_version[] = VERMAGIC_STRING;
27static const char hns3_driver_string[] =
28 "Hisilicon Ethernet Network Driver for Hip08 Family";
29static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
30static struct hnae3_client client;
31
32/* hns3_pci_tbl - PCI Device ID Table
33 *
34 * Last entry must be all 0s
35 *
36 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
37 * Class, Class Mask, private data (not used) }
38 */
39static const struct pci_device_id hns3_pci_tbl[] = {
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 43 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 45 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 47 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 49 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 51 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
a9c89a3f 52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
f4e4e86c
JS		 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 55 /* required last entry */
56 {0, }
57};
58MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
59
5a8b1a40 60static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 61{
5a8b1a40 62 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e
S		 63
64 napi_schedule(&tqp_vector->napi);
65
66 return IRQ_HANDLED;
67}
68
15040788
PL		 69/* This callback function is used to set affinity changes to the irq affinity
70 * masks when the irq_set_affinity_notifier function is used.
71 */
72static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify,
73 const cpumask_t *mask)
74{
75 struct hns3_enet_tqp_vector *tqp_vectors =
76 container_of(notify, struct hns3_enet_tqp_vector,
77 affinity_notify);
78
79 tqp_vectors->affinity_mask = *mask;
80}
81
82static void hns3_nic_irq_affinity_release(struct kref *ref)
83{
84}
85
76ad4f0e
S		 86static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
87{
88 struct hns3_enet_tqp_vector *tqp_vectors;
89 unsigned int i;
90
91 for (i = 0; i < priv->vector_num; i++) {
92 tqp_vectors = &priv->tqp_vector[i];
93
94 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
95 continue;
96
15040788
PL		 97 /* clear the affinity notifier and affinity mask */
98 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL);
99 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
100
76ad4f0e
S		 101 /* release the irq resource */
102 free_irq(tqp_vectors->vector_irq, tqp_vectors);
103 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
104 }
105}
106
107static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
108{
109 struct hns3_enet_tqp_vector *tqp_vectors;
110 int txrx_int_idx = 0;
111 int rx_int_idx = 0;
112 int tx_int_idx = 0;
113 unsigned int i;
114 int ret;
115
116 for (i = 0; i < priv->vector_num; i++) {
117 tqp_vectors = &priv->tqp_vector[i];
118
119 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
120 continue;
121
122 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
123 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
124 "%s-%s-%d", priv->netdev->name, "TxRx",
125 txrx_int_idx++);
126 txrx_int_idx++;
127 } else if (tqp_vectors->rx_group.ring) {
128 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
129 "%s-%s-%d", priv->netdev->name, "Rx",
130 rx_int_idx++);
131 } else if (tqp_vectors->tx_group.ring) {
132 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
133 "%s-%s-%d", priv->netdev->name, "Tx",
134 tx_int_idx++);
135 } else {
136 /* Skip this unused q_vector */
137 continue;
138 }
139
140 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
141
142 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
143 tqp_vectors->name,
144 tqp_vectors);
145 if (ret) {
146 netdev_err(priv->netdev, "request irq(%d) fail\n",
147 tqp_vectors->vector_irq);
148 return ret;
149 }
150
15040788
PL		 151 tqp_vectors->affinity_notify.notify =
152 hns3_nic_irq_affinity_notify;
153 tqp_vectors->affinity_notify.release =
154 hns3_nic_irq_affinity_release;
155 irq_set_affinity_notifier(tqp_vectors->vector_irq,
156 &tqp_vectors->affinity_notify);
157 irq_set_affinity_hint(tqp_vectors->vector_irq,
158 &tqp_vectors->affinity_mask);
159
76ad4f0e
S		 160 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
161 }
162
163 return 0;
164}
165
166static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
167 u32 mask_en)
168{
169 writel(mask_en, tqp_vector->mask_addr);
170}
171
172static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
173{
174 napi_enable(&tqp_vector->napi);
175
176 /* enable vector */
177 hns3_mask_vector_irq(tqp_vector, 1);
178}
179
180static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
181{
182 /* disable vector */
183 hns3_mask_vector_irq(tqp_vector, 0);
184
185 disable_irq(tqp_vector->vector_irq);
186 napi_disable(&tqp_vector->napi);
187}
188
5acd0356
FL		 189void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
190 u32 rl_value)
76ad4f0e 191{
5acd0356
FL		 192 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
193
76ad4f0e
S		 194 /* this defines the configuration for RL (Interrupt Rate Limiter).
195 * Rl defines rate of interrupts i.e. number of interrupts-per-second
196 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
197 */
5acd0356 198
d420d2de
YL		 199 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
200 !tqp_vector->rx_group.coal.gl_adapt_enable)
5acd0356
FL		 201 /* According to the hardware, the range of rl_reg is
202 * 0-59 and the unit is 4.
203 */
204 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
205
206 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
207}
208
209void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
210 u32 gl_value)
211{
212 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
213
214 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
215}
216
217void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
218 u32 gl_value)
219{
220 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
221
222 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 223}
224
2b27decc
FL		 225static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
226 struct hns3_nic_priv *priv)
76ad4f0e 227{
2b27decc
FL		 228 struct hnae3_handle *h = priv->ae_handle;
229
76ad4f0e
S		 230 /* initialize the configuration for interrupt coalescing.
231 * 1. GL (Interrupt Gap Limiter)
232 * 2. RL (Interrupt Rate Limiter)
233 */
234
2b27decc 235 /* Default: enable interrupt coalescing self-adaptive and GL */
d420d2de
YL		 236 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
237 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
2b27decc 238
d420d2de
YL		 239 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
240 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
2b27decc 241
2b27decc
FL		 242 /* Default: disable RL */
243 h->kinfo.int_rl_setting = 0;
2b27decc 244
3f97bd23 245 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
d420d2de
YL		 246 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
247 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 248}
249
6cbd6d33
YL		 250static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
251 struct hns3_nic_priv *priv)
252{
253 struct hnae3_handle *h = priv->ae_handle;
254
255 hns3_set_vector_coalesce_tx_gl(tqp_vector,
d420d2de 256 tqp_vector->tx_group.coal.int_gl);
6cbd6d33 257 hns3_set_vector_coalesce_rx_gl(tqp_vector,
d420d2de 258 tqp_vector->rx_group.coal.int_gl);
6cbd6d33
YL		 259 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
260}
261
9df8f79a
YL		 262static int hns3_nic_set_real_num_queue(struct net_device *netdev)
263{
9780cb97 264 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 265 struct hnae3_knic_private_info *kinfo = &h->kinfo;
266 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
7e114e7d
YL		 267 int i, ret;
268
269 if (kinfo->num_tc <= 1) {
270 netdev_reset_tc(netdev);
271 } else {
272 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
273 if (ret) {
274 netdev_err(netdev,
275 "netdev_set_num_tc fail, ret=%d!\n", ret);
276 return ret;
277 }
278
279 for (i = 0; i < HNAE3_MAX_TC; i++) {
280 if (!kinfo->tc_info[i].enable)
281 continue;
282
283 netdev_set_tc_queue(netdev,
284 kinfo->tc_info[i].tc,
285 kinfo->tc_info[i].tqp_count,
286 kinfo->tc_info[i].tqp_offset);
287 }
288 }
9df8f79a
YL		 289
290 ret = netif_set_real_num_tx_queues(netdev, queue_size);
291 if (ret) {
292 netdev_err(netdev,
293 "netif_set_real_num_tx_queues fail, ret=%d!\n",
294 ret);
295 return ret;
296 }
297
298 ret = netif_set_real_num_rx_queues(netdev, queue_size);
299 if (ret) {
300 netdev_err(netdev,
301 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
302 return ret;
303 }
304
305 return 0;
306}
307
2d7187ce
PL		 308static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
309{
310 u16 free_tqps, max_rss_size, max_tqps;
311
312 h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size);
313 max_tqps = h->kinfo.num_tc * max_rss_size;
314
315 return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps));
316}
317
76ad4f0e
S		 318static int hns3_nic_net_up(struct net_device *netdev)
319{
320 struct hns3_nic_priv *priv = netdev_priv(netdev);
321 struct hnae3_handle *h = priv->ae_handle;
322 int i, j;
323 int ret;
324
e32a805a
FL		 325 ret = hns3_nic_reset_all_ring(h);
326 if (ret)
327 return ret;
328
76ad4f0e
S		 329 /* get irq resource for all vectors */
330 ret = hns3_nic_init_irq(priv);
331 if (ret) {
332 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
333 return ret;
334 }
335
336 /* enable the vectors */
337 for (i = 0; i < priv->vector_num; i++)
338 hns3_vector_enable(&priv->tqp_vector[i]);
339
340 /* start the ae_dev */
341 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
342 if (ret)
343 goto out_start_err;
344
a3083abb
JS		 345 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
346
76ad4f0e
S		 347 return 0;
348
349out_start_err:
350 for (j = i - 1; j >= 0; j--)
351 hns3_vector_disable(&priv->tqp_vector[j]);
352
353 hns3_nic_uninit_irq(priv);
354
355 return ret;
356}
357
358static int hns3_nic_net_open(struct net_device *netdev)
359{
f8fa222c 360 struct hns3_nic_priv *priv = netdev_priv(netdev);
7e114e7d
YL		 361 struct hnae3_handle *h = hns3_get_handle(netdev);
362 struct hnae3_knic_private_info *kinfo;
363 int i, ret;
76ad4f0e
S		 364
365 netif_carrier_off(netdev);
366
9df8f79a
YL		 367 ret = hns3_nic_set_real_num_queue(netdev);
368 if (ret)
76ad4f0e 369 return ret;
76ad4f0e
S		 370
371 ret = hns3_nic_net_up(netdev);
372 if (ret) {
373 netdev_err(netdev,
374 "hns net up fail, ret=%d!\n", ret);
375 return ret;
376 }
377
7e114e7d
YL		 378 kinfo = &h->kinfo;
379 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
380 netdev_set_prio_tc_map(netdev, i,
381 kinfo->prio_tc[i]);
382 }
383
4aef908d 384 priv->ae_handle->last_reset_time = jiffies;
76ad4f0e
S		 385 return 0;
386}
387
388static void hns3_nic_net_down(struct net_device *netdev)
389{
390 struct hns3_nic_priv *priv = netdev_priv(netdev);
391 const struct hnae3_ae_ops *ops;
392 int i;
393
a3083abb
JS		 394 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
395 return;
396
e32a805a
FL		 397 /* disable vectors */
398 for (i = 0; i < priv->vector_num; i++)
399 hns3_vector_disable(&priv->tqp_vector[i]);
400
76ad4f0e
S		 401 /* stop ae_dev */
402 ops = priv->ae_handle->ae_algo->ops;
403 if (ops->stop)
404 ops->stop(priv->ae_handle);
405
76ad4f0e
S		 406 /* free irq resources */
407 hns3_nic_uninit_irq(priv);
e32a805a
FL		 408
409 hns3_clear_all_ring(priv->ae_handle);
76ad4f0e
S		 410}
411
412static int hns3_nic_net_stop(struct net_device *netdev)
413{
414 netif_tx_stop_all_queues(netdev);
415 netif_carrier_off(netdev);
416
417 hns3_nic_net_down(netdev);
418
419 return 0;
420}
421
76ad4f0e
S		 422static int hns3_nic_uc_sync(struct net_device *netdev,
423 const unsigned char *addr)
424{
9780cb97 425 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 426
427 if (h->ae_algo->ops->add_uc_addr)
428 return h->ae_algo->ops->add_uc_addr(h, addr);
429
430 return 0;
431}
432
433static int hns3_nic_uc_unsync(struct net_device *netdev,
434 const unsigned char *addr)
435{
9780cb97 436 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 437
438 if (h->ae_algo->ops->rm_uc_addr)
439 return h->ae_algo->ops->rm_uc_addr(h, addr);
440
441 return 0;
442}
443
444static int hns3_nic_mc_sync(struct net_device *netdev,
445 const unsigned char *addr)
446{
9780cb97 447 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 448
720a8478 449 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 450 return h->ae_algo->ops->add_mc_addr(h, addr);
451
452 return 0;
453}
454
455static int hns3_nic_mc_unsync(struct net_device *netdev,
456 const unsigned char *addr)
457{
9780cb97 458 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 459
720a8478 460 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 461 return h->ae_algo->ops->rm_mc_addr(h, addr);
462
463 return 0;
464}
465
1db9b1bf 466static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 467{
9780cb97 468 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 469
470 if (h->ae_algo->ops->set_promisc_mode) {
471 if (netdev->flags & IFF_PROMISC)
e8600a3d
PL		 472 h->ae_algo->ops->set_promisc_mode(h, true, true);
473 else if (netdev->flags & IFF_ALLMULTI)
474 h->ae_algo->ops->set_promisc_mode(h, false, true);
76ad4f0e 475 else
e8600a3d 476 h->ae_algo->ops->set_promisc_mode(h, false, false);
76ad4f0e
S		 477 }
478 if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync))
479 netdev_err(netdev, "sync uc address fail\n");
a832d8b5 480 if (netdev->flags & IFF_MULTICAST) {
76ad4f0e
S		 481 if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync))
482 netdev_err(netdev, "sync mc address fail\n");
a832d8b5
XW		 483
484 if (h->ae_algo->ops->update_mta_status)
485 h->ae_algo->ops->update_mta_status(h);
486 }
76ad4f0e
S		 487}
488
489static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
490 u16 *mss, u32 *type_cs_vlan_tso)
491{
492 u32 l4_offset, hdr_len;
493 union l3_hdr_info l3;
494 union l4_hdr_info l4;
495 u32 l4_paylen;
496 int ret;
497
498 if (!skb_is_gso(skb))
499 return 0;
500
501 ret = skb_cow_head(skb, 0);
502 if (ret)
503 return ret;
504
505 l3.hdr = skb_network_header(skb);
506 l4.hdr = skb_transport_header(skb);
507
508 /* Software should clear the IPv4's checksum field when tso is
509 * needed.
510 */
511 if (l3.v4->version == 4)
512 l3.v4->check = 0;
513
514 /* tunnel packet.*/
515 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
516 SKB_GSO_GRE_CSUM |
517 SKB_GSO_UDP_TUNNEL |
518 SKB_GSO_UDP_TUNNEL_CSUM)) {
519 if ((!(skb_shinfo(skb)->gso_type &
520 SKB_GSO_PARTIAL)) &&
521 (skb_shinfo(skb)->gso_type &
522 SKB_GSO_UDP_TUNNEL_CSUM)) {
523 /* Software should clear the udp's checksum
524 * field when tso is needed.
525 */
526 l4.udp->check = 0;
527 }
528 /* reset l3&l4 pointers from outer to inner headers */
529 l3.hdr = skb_inner_network_header(skb);
530 l4.hdr = skb_inner_transport_header(skb);
531
532 /* Software should clear the IPv4's checksum field when
533 * tso is needed.
534 */
535 if (l3.v4->version == 4)
536 l3.v4->check = 0;
537 }
538
539 /* normal or tunnel packet*/
540 l4_offset = l4.hdr - skb->data;
541 hdr_len = (l4.tcp->doff * 4) + l4_offset;
542
543 /* remove payload length from inner pseudo checksum when tso*/
544 l4_paylen = skb->len - l4_offset;
545 csum_replace_by_diff(&l4.tcp->check,
546 (__force __wsum)htonl(l4_paylen));
547
548 /* find the txbd field values */
549 *paylen = skb->len - hdr_len;
ccc23ef3
PL		 550 hnae3_set_bit(*type_cs_vlan_tso,
551 HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 552
553 /* get MSS for TSO */
554 *mss = skb_shinfo(skb)->gso_size;
555
556 return 0;
557}
558
1898d4e4
S		 559static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
560 u8 *il4_proto)
76ad4f0e
S		 561{
562 union {
563 struct iphdr *v4;
564 struct ipv6hdr *v6;
565 unsigned char *hdr;
566 } l3;
567 unsigned char *l4_hdr;
568 unsigned char *exthdr;
569 u8 l4_proto_tmp;
570 __be16 frag_off;
571
572 /* find outer header point */
573 l3.hdr = skb_network_header(skb);
c82a5497 574 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 575
576 if (skb->protocol == htons(ETH_P_IPV6)) {
577 exthdr = l3.hdr + sizeof(*l3.v6);
578 l4_proto_tmp = l3.v6->nexthdr;
579 if (l4_hdr != exthdr)
580 ipv6_skip_exthdr(skb, exthdr - skb->data,
581 &l4_proto_tmp, &frag_off);
582 } else if (skb->protocol == htons(ETH_P_IP)) {
583 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 584 } else {
585 return -EINVAL;
76ad4f0e
S		 586 }
587
588 *ol4_proto = l4_proto_tmp;
589
590 /* tunnel packet */
591 if (!skb->encapsulation) {
592 *il4_proto = 0;
1898d4e4 593 return 0;
76ad4f0e
S		 594 }
595
596 /* find inner header point */
597 l3.hdr = skb_inner_network_header(skb);
598 l4_hdr = skb_inner_transport_header(skb);
599
600 if (l3.v6->version == 6) {
601 exthdr = l3.hdr + sizeof(*l3.v6);
602 l4_proto_tmp = l3.v6->nexthdr;
603 if (l4_hdr != exthdr)
604 ipv6_skip_exthdr(skb, exthdr - skb->data,
605 &l4_proto_tmp, &frag_off);
606 } else if (l3.v4->version == 4) {
607 l4_proto_tmp = l3.v4->protocol;
608 }
609
610 *il4_proto = l4_proto_tmp;
1898d4e4
S		 611
612 return 0;
76ad4f0e
S		 613}
614
615static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
616 u8 il4_proto, u32 *type_cs_vlan_tso,
617 u32 *ol_type_vlan_len_msec)
618{
619 union {
620 struct iphdr *v4;
621 struct ipv6hdr *v6;
622 unsigned char *hdr;
623 } l3;
624 union {
625 struct tcphdr *tcp;
626 struct udphdr *udp;
627 struct gre_base_hdr *gre;
628 unsigned char *hdr;
629 } l4;
630 unsigned char *l2_hdr;
631 u8 l4_proto = ol4_proto;
632 u32 ol2_len;
633 u32 ol3_len;
634 u32 ol4_len;
635 u32 l2_len;
636 u32 l3_len;
637
638 l3.hdr = skb_network_header(skb);
639 l4.hdr = skb_transport_header(skb);
640
641 /* compute L2 header size for normal packet, defined in 2 Bytes */
642 l2_len = l3.hdr - skb->data;
ccc23ef3
PL		 643 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
644 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 645
646 /* tunnel packet*/
647 if (skb->encapsulation) {
648 /* compute OL2 header size, defined in 2 Bytes */
649 ol2_len = l2_len;
ccc23ef3
PL		 650 hnae3_set_field(*ol_type_vlan_len_msec,
651 HNS3_TXD_L2LEN_M,
652 HNS3_TXD_L2LEN_S, ol2_len >> 1);
76ad4f0e
S		 653
654 /* compute OL3 header size, defined in 4 Bytes */
655 ol3_len = l4.hdr - l3.hdr;
ccc23ef3
PL		 656 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
657 HNS3_TXD_L3LEN_S, ol3_len >> 2);
76ad4f0e
S		 658
659 /* MAC in UDP, MAC in GRE (0x6558)*/
660 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
661 /* switch MAC header ptr from outer to inner header.*/
662 l2_hdr = skb_inner_mac_header(skb);
663
664 /* compute OL4 header size, defined in 4 Bytes. */
665 ol4_len = l2_hdr - l4.hdr;
ccc23ef3
PL		 666 hnae3_set_field(*ol_type_vlan_len_msec,
667 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
668 ol4_len >> 2);
76ad4f0e
S		 669
670 /* switch IP header ptr from outer to inner header */
671 l3.hdr = skb_inner_network_header(skb);
672
673 /* compute inner l2 header size, defined in 2 Bytes. */
674 l2_len = l3.hdr - l2_hdr;
ccc23ef3
PL		 675 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
676 HNS3_TXD_L2LEN_S, l2_len >> 1);
76ad4f0e
S		 677 } else {
678 /* skb packet types not supported by hardware,
679 * txbd len fild doesn't be filled.
680 */
681 return;
682 }
683
684 /* switch L4 header pointer from outer to inner */
685 l4.hdr = skb_inner_transport_header(skb);
686
687 l4_proto = il4_proto;
688 }
689
690 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
691 l3_len = l4.hdr - l3.hdr;
ccc23ef3
PL		 692 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
693 HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e
S		 694
695 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
696 switch (l4_proto) {
697 case IPPROTO_TCP:
ccc23ef3
PL		 698 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
699 HNS3_TXD_L4LEN_S, l4.tcp->doff);
76ad4f0e
S		 700 break;
701 case IPPROTO_SCTP:
ccc23ef3
PL		 702 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
703 HNS3_TXD_L4LEN_S,
704 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 705 break;
706 case IPPROTO_UDP:
ccc23ef3
PL		 707 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
708 HNS3_TXD_L4LEN_S,
709 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 710 break;
711 default:
712 /* skb packet types not supported by hardware,
713 * txbd len fild doesn't be filled.
714 */
715 return;
716 }
717}
718
cfdd6e86
YL		 719/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
720 * and it is udp packet, which has a dest port as the IANA assigned.
721 * the hardware is expected to do the checksum offload, but the
722 * hardware will not do the checksum offload when udp dest port is
723 * 4789.
724 */
725static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
726{
727#define IANA_VXLAN_PORT 4789
728 union {
729 struct tcphdr *tcp;
730 struct udphdr *udp;
731 struct gre_base_hdr *gre;
732 unsigned char *hdr;
733 } l4;
734
735 l4.hdr = skb_transport_header(skb);
736
737 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
738 return false;
739
740 skb_checksum_help(skb);
741
742 return true;
743}
744
76ad4f0e
S		 745static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
746 u8 il4_proto, u32 *type_cs_vlan_tso,
747 u32 *ol_type_vlan_len_msec)
748{
749 union {
750 struct iphdr *v4;
751 struct ipv6hdr *v6;
752 unsigned char *hdr;
753 } l3;
754 u32 l4_proto = ol4_proto;
755
756 l3.hdr = skb_network_header(skb);
757
758 /* define OL3 type and tunnel type(OL4).*/
759 if (skb->encapsulation) {
760 /* define outer network header type.*/
761 if (skb->protocol == htons(ETH_P_IP)) {
762 if (skb_is_gso(skb))
ccc23ef3
PL		 763 hnae3_set_field(*ol_type_vlan_len_msec,
764 HNS3_TXD_OL3T_M,
765 HNS3_TXD_OL3T_S,
766 HNS3_OL3T_IPV4_CSUM);
76ad4f0e 767 else
ccc23ef3
PL		 768 hnae3_set_field(*ol_type_vlan_len_msec,
769 HNS3_TXD_OL3T_M,
770 HNS3_TXD_OL3T_S,
771 HNS3_OL3T_IPV4_NO_CSUM);
76ad4f0e
S		 772
773 } else if (skb->protocol == htons(ETH_P_IPV6)) {
ccc23ef3
PL		 774 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
775 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
76ad4f0e
S		 776 }
777
778 /* define tunnel type(OL4).*/
779 switch (l4_proto) {
780 case IPPROTO_UDP:
ccc23ef3
PL		 781 hnae3_set_field(*ol_type_vlan_len_msec,
782 HNS3_TXD_TUNTYPE_M,
783 HNS3_TXD_TUNTYPE_S,
784 HNS3_TUN_MAC_IN_UDP);
76ad4f0e
S		 785 break;
786 case IPPROTO_GRE:
ccc23ef3
PL		 787 hnae3_set_field(*ol_type_vlan_len_msec,
788 HNS3_TXD_TUNTYPE_M,
789 HNS3_TXD_TUNTYPE_S,
790 HNS3_TUN_NVGRE);
76ad4f0e
S		 791 break;
792 default:
793 /* drop the skb tunnel packet if hardware don't support,
794 * because hardware can't calculate csum when TSO.
795 */
796 if (skb_is_gso(skb))
797 return -EDOM;
798
799 /* the stack computes the IP header already,
800 * driver calculate l4 checksum when not TSO.
801 */
802 skb_checksum_help(skb);
803 return 0;
804 }
805
806 l3.hdr = skb_inner_network_header(skb);
807 l4_proto = il4_proto;
808 }
809
810 if (l3.v4->version == 4) {
ccc23ef3
PL		 811 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
812 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
76ad4f0e
S		 813
814 /* the stack computes the IP header already, the only time we
815 * need the hardware to recompute it is in the case of TSO.
816 */
817 if (skb_is_gso(skb))
ccc23ef3 818 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 819 } else if (l3.v6->version == 6) {
ccc23ef3
PL		 820 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
821 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
76ad4f0e
S		 822 }
823
824 switch (l4_proto) {
825 case IPPROTO_TCP:
79fa1b6a 826 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 827 hnae3_set_field(*type_cs_vlan_tso,
828 HNS3_TXD_L4T_M,
829 HNS3_TXD_L4T_S,
830 HNS3_L4T_TCP);
76ad4f0e
S		 831 break;
832 case IPPROTO_UDP:
cfdd6e86
YL		 833 if (hns3_tunnel_csum_bug(skb))
834 break;
835
79fa1b6a 836 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 837 hnae3_set_field(*type_cs_vlan_tso,
838 HNS3_TXD_L4T_M,
839 HNS3_TXD_L4T_S,
840 HNS3_L4T_UDP);
76ad4f0e
S		 841 break;
842 case IPPROTO_SCTP:
79fa1b6a 843 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
ccc23ef3
PL		 844 hnae3_set_field(*type_cs_vlan_tso,
845 HNS3_TXD_L4T_M,
846 HNS3_TXD_L4T_S,
847 HNS3_L4T_SCTP);
76ad4f0e
S		 848 break;
849 default:
850 /* drop the skb tunnel packet if hardware don't support,
851 * because hardware can't calculate csum when TSO.
852 */
853 if (skb_is_gso(skb))
854 return -EDOM;
855
856 /* the stack computes the IP header already,
857 * driver calculate l4 checksum when not TSO.
858 */
859 skb_checksum_help(skb);
860 return 0;
861 }
862
863 return 0;
864}
865
866static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
867{
868 /* Config bd buffer end */
ccc23ef3
PL		 869 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
870 HNS3_TXD_BDTYPE_S, 0);
871 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
872 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
873 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
76ad4f0e
S		 874}
875
1fdd8dc5
PL		 876static int hns3_fill_desc_vtags(struct sk_buff *skb,
877 struct hns3_enet_ring *tx_ring,
878 u32 *inner_vlan_flag,
879 u32 *out_vlan_flag,
880 u16 *inner_vtag,
881 u16 *out_vtag)
882{
883#define HNS3_TX_VLAN_PRIO_SHIFT 13
884
885 if (skb->protocol == htons(ETH_P_8021Q) &&
886 !(tx_ring->tqp->handle->kinfo.netdev->features &
887 NETIF_F_HW_VLAN_CTAG_TX)) {
888 /* When HW VLAN acceleration is turned off, and the stack
889 * sets the protocol to 802.1q, the driver just need to
890 * set the protocol to the encapsulated ethertype.
891 */
892 skb->protocol = vlan_get_protocol(skb);
893 return 0;
894 }
895
896 if (skb_vlan_tag_present(skb)) {
897 u16 vlan_tag;
898
899 vlan_tag = skb_vlan_tag_get(skb);
900 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
901
902 /* Based on hw strategy, use out_vtag in two layer tag case,
903 * and use inner_vtag in one tag case.
904 */
905 if (skb->protocol == htons(ETH_P_8021Q)) {
ccc23ef3 906 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
1fdd8dc5
PL		 907 *out_vtag = vlan_tag;
908 } else {
ccc23ef3 909 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
1fdd8dc5
PL		 910 *inner_vtag = vlan_tag;
911 }
912 } else if (skb->protocol == htons(ETH_P_8021Q)) {
913 struct vlan_ethhdr *vhdr;
914 int rc;
915
916 rc = skb_cow_head(skb, 0);
917 if (rc < 0)
918 return rc;
919 vhdr = (struct vlan_ethhdr *)skb->data;
920 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
921 << HNS3_TX_VLAN_PRIO_SHIFT);
922 }
923
924 skb->protocol = vlan_get_protocol(skb);
925 return 0;
926}
927
76ad4f0e
S		 928static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
929 int size, dma_addr_t dma, int frag_end,
930 enum hns_desc_type type)
931{
932 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
933 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
934 u32 ol_type_vlan_len_msec = 0;
935 u16 bdtp_fe_sc_vld_ra_ri = 0;
936 u32 type_cs_vlan_tso = 0;
937 struct sk_buff *skb;
1fdd8dc5
PL		 938 u16 inner_vtag = 0;
939 u16 out_vtag = 0;
76ad4f0e
S		 940 u32 paylen = 0;
941 u16 mss = 0;
76ad4f0e
S		 942 u8 ol4_proto;
943 u8 il4_proto;
944 int ret;
945
946 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
947 desc_cb->priv = priv;
948 desc_cb->length = size;
949 desc_cb->dma = dma;
950 desc_cb->type = type;
951
952 /* now, fill the descriptor */
953 desc->addr = cpu_to_le64(dma);
954 desc->tx.send_size = cpu_to_le16((u16)size);
955 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
956 desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
957
958 if (type == DESC_TYPE_SKB) {
959 skb = (struct sk_buff *)priv;
a90bb9a5 960 paylen = skb->len;
76ad4f0e 961
1fdd8dc5
PL		 962 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
963 &ol_type_vlan_len_msec,
964 &inner_vtag, &out_vtag);
965 if (unlikely(ret))
966 return ret;
967
76ad4f0e
S		 968 if (skb->ip_summed == CHECKSUM_PARTIAL) {
969 skb_reset_mac_len(skb);
76ad4f0e 970
1898d4e4
S		 971 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
972 if (ret)
973 return ret;
76ad4f0e
S		 974 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
975 &type_cs_vlan_tso,
976 &ol_type_vlan_len_msec);
977 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
978 &type_cs_vlan_tso,
979 &ol_type_vlan_len_msec);
980 if (ret)
981 return ret;
982
983 ret = hns3_set_tso(skb, &paylen, &mss,
984 &type_cs_vlan_tso);
985 if (ret)
986 return ret;
987 }
988
989 /* Set txbd */
990 desc->tx.ol_type_vlan_len_msec =
991 cpu_to_le32(ol_type_vlan_len_msec);
992 desc->tx.type_cs_vlan_tso_len =
993 cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 994 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 995 desc->tx.mss = cpu_to_le16(mss);
1fdd8dc5
PL		 996 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
997 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
76ad4f0e
S		 998 }
999
1000 /* move ring pointer to next.*/
1001 ring_ptr_move_fw(ring, next_to_use);
1002
1003 return 0;
1004}
1005
1006static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv,
1007 int size, dma_addr_t dma, int frag_end,
1008 enum hns_desc_type type)
1009{
1010 unsigned int frag_buf_num;
1011 unsigned int k;
1012 int sizeoflast;
1013 int ret;
1014
1015 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1016 sizeoflast = size % HNS3_MAX_BD_SIZE;
1017 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1018
1019 /* When the frag size is bigger than hardware, split this frag */
1020 for (k = 0; k < frag_buf_num; k++) {
1021 ret = hns3_fill_desc(ring, priv,
1022 (k == frag_buf_num - 1) ?
1023 sizeoflast : HNS3_MAX_BD_SIZE,
1024 dma + HNS3_MAX_BD_SIZE * k,
1025 frag_end && (k == frag_buf_num - 1) ? 1 : 0,
1026 (type == DESC_TYPE_SKB && !k) ?
1027 DESC_TYPE_SKB : DESC_TYPE_PAGE);
1028 if (ret)
1029 return ret;
1030 }
1031
1032 return 0;
1033}
1034
1035static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1036 struct hns3_enet_ring *ring)
1037{
1038 struct sk_buff *skb = *out_skb;
1039 struct skb_frag_struct *frag;
1040 int bdnum_for_frag;
1041 int frag_num;
1042 int buf_num;
1043 int size;
1044 int i;
1045
1046 size = skb_headlen(skb);
1047 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1048
1049 frag_num = skb_shinfo(skb)->nr_frags;
1050 for (i = 0; i < frag_num; i++) {
1051 frag = &skb_shinfo(skb)->frags[i];
1052 size = skb_frag_size(frag);
1053 bdnum_for_frag =
1054 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1055 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1056 return -ENOMEM;
1057
1058 buf_num += bdnum_for_frag;
1059 }
1060
1061 if (buf_num > ring_space(ring))
1062 return -EBUSY;
1063
1064 *bnum = buf_num;
1065 return 0;
1066}
1067
1068static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1069 struct hns3_enet_ring *ring)
1070{
1071 struct sk_buff *skb = *out_skb;
1072 int buf_num;
1073
1074 /* No. of segments (plus a header) */
1075 buf_num = skb_shinfo(skb)->nr_frags + 1;
1076
91a2f02f 1077 if (unlikely(ring_space(ring) < buf_num))
76ad4f0e
S		 1078 return -EBUSY;
1079
1080 *bnum = buf_num;
1081
1082 return 0;
1083}
1084
1085static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig)
1086{
1087 struct device *dev = ring_to_dev(ring);
1088 unsigned int i;
1089
1090 for (i = 0; i < ring->desc_num; i++) {
1091 /* check if this is where we started */
1092 if (ring->next_to_use == next_to_use_orig)
1093 break;
1094
1095 /* unmap the descriptor dma address */
1096 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1097 dma_unmap_single(dev,
1098 ring->desc_cb[ring->next_to_use].dma,
1099 ring->desc_cb[ring->next_to_use].length,
1100 DMA_TO_DEVICE);
1101 else
1102 dma_unmap_page(dev,
1103 ring->desc_cb[ring->next_to_use].dma,
1104 ring->desc_cb[ring->next_to_use].length,
1105 DMA_TO_DEVICE);
1106
1107 /* rollback one */
1108 ring_ptr_move_bw(ring, next_to_use);
1109 }
1110}
1111
d43e5aca 1112netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1113{
1114 struct hns3_nic_priv *priv = netdev_priv(netdev);
1115 struct hns3_nic_ring_data *ring_data =
1116 &tx_ring_data(priv, skb->queue_mapping);
1117 struct hns3_enet_ring *ring = ring_data->ring;
1118 struct device *dev = priv->dev;
1119 struct netdev_queue *dev_queue;
1120 struct skb_frag_struct *frag;
1121 int next_to_use_head;
1122 int next_to_use_frag;
1123 dma_addr_t dma;
1124 int buf_num;
1125 int seg_num;
1126 int size;
1127 int ret;
1128 int i;
1129
1130 /* Prefetch the data used later */
1131 prefetch(skb->data);
1132
1133 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1134 case -EBUSY:
1135 u64_stats_update_begin(&ring->syncp);
1136 ring->stats.tx_busy++;
1137 u64_stats_update_end(&ring->syncp);
1138
1139 goto out_net_tx_busy;
1140 case -ENOMEM:
1141 u64_stats_update_begin(&ring->syncp);
1142 ring->stats.sw_err_cnt++;
1143 u64_stats_update_end(&ring->syncp);
1144 netdev_err(netdev, "no memory to xmit!\n");
1145
1146 goto out_err_tx_ok;
1147 default:
1148 break;
1149 }
1150
1151 /* No. of segments (plus a header) */
1152 seg_num = skb_shinfo(skb)->nr_frags + 1;
1153 /* Fill the first part */
1154 size = skb_headlen(skb);
1155
1156 next_to_use_head = ring->next_to_use;
1157
1158 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1159 if (dma_mapping_error(dev, dma)) {
1160 netdev_err(netdev, "TX head DMA map failed\n");
1161 ring->stats.sw_err_cnt++;
1162 goto out_err_tx_ok;
1163 }
1164
1165 ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0,
1166 DESC_TYPE_SKB);
1167 if (ret)
1168 goto head_dma_map_err;
1169
1170 next_to_use_frag = ring->next_to_use;
1171 /* Fill the fragments */
1172 for (i = 1; i < seg_num; i++) {
1173 frag = &skb_shinfo(skb)->frags[i - 1];
1174 size = skb_frag_size(frag);
1175 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1176 if (dma_mapping_error(dev, dma)) {
1177 netdev_err(netdev, "TX frag(%d) DMA map failed\n", i);
1178 ring->stats.sw_err_cnt++;
1179 goto frag_dma_map_err;
1180 }
1181 ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma,
1182 seg_num - 1 == i ? 1 : 0,
1183 DESC_TYPE_PAGE);
1184
1185 if (ret)
1186 goto frag_dma_map_err;
1187 }
1188
1189 /* Complete translate all packets */
1190 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1191 netdev_tx_sent_queue(dev_queue, skb->len);
1192
1193 wmb(); /* Commit all data before submit */
1194
ccc23ef3 1195 hnae3_queue_xmit(ring->tqp, buf_num);
76ad4f0e
S		 1196
1197 return NETDEV_TX_OK;
1198
1199frag_dma_map_err:
1200 hns_nic_dma_unmap(ring, next_to_use_frag);
1201
1202head_dma_map_err:
1203 hns_nic_dma_unmap(ring, next_to_use_head);
1204
1205out_err_tx_ok:
1206 dev_kfree_skb_any(skb);
1207 return NETDEV_TX_OK;
1208
1209out_net_tx_busy:
1210 netif_stop_subqueue(netdev, ring_data->queue_index);
1211 smp_mb(); /* Commit all data before submit */
1212
1213 return NETDEV_TX_BUSY;
1214}
1215
1216static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1217{
9780cb97 1218 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1219 struct sockaddr *mac_addr = p;
1220 int ret;
1221
1222 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1223 return -EADDRNOTAVAIL;
1224
f37fc980
JS		 1225 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1226 netdev_info(netdev, "already using mac address %pM\n",
1227 mac_addr->sa_data);
1228 return 0;
1229 }
1230
3cbf5e2d 1231 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1232 if (ret) {
1233 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1234 return ret;
1235 }
1236
1237 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1238
1239 return 0;
1240}
1241
a185d723
XW		 1242static int hns3_nic_do_ioctl(struct net_device *netdev,
1243 struct ifreq *ifr, int cmd)
1244{
1245 struct hnae3_handle *h = hns3_get_handle(netdev);
1246
1247 if (!netif_running(netdev))
1248 return -EINVAL;
1249
1250 if (!h->ae_algo->ops->do_ioctl)
1251 return -EOPNOTSUPP;
1252
1253 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1254}
1255
76ad4f0e
S		 1256static int hns3_nic_set_features(struct net_device *netdev,
1257 netdev_features_t features)
1258{
21b6fd34 1259 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1260 struct hns3_nic_priv *priv = netdev_priv(netdev);
5f9a7732 1261 struct hnae3_handle *h = priv->ae_handle;
5f9a7732 1262 int ret;
76ad4f0e 1263
21b6fd34
JS		 1264 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
1265 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) {
1266 priv->ops.fill_desc = hns3_fill_desc_tso;
1267 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
1268 } else {
1269 priv->ops.fill_desc = hns3_fill_desc;
1270 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
1271 }
76ad4f0e
S		 1272 }
1273
88576b4b
JS		 1274 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1275 h->ae_algo->ops->enable_vlan_filter) {
21b6fd34
JS		 1276 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1277 h->ae_algo->ops->enable_vlan_filter(h, true);
1278 else
1279 h->ae_algo->ops->enable_vlan_filter(h, false);
1280 }
d818396d 1281
88576b4b
JS		 1282 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1283 h->ae_algo->ops->enable_hw_strip_rxvtag) {
5f9a7732
PL		 1284 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1285 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true);
1286 else
1287 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false);
1288
1289 if (ret)
1290 return ret;
1291 }
1292
76ad4f0e
S		 1293 netdev->features = features;
1294 return 0;
1295}
1296
9596f6f0
PL		 1297static void hns3_nic_get_stats64(struct net_device *netdev,
1298 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1299{
1300 struct hns3_nic_priv *priv = netdev_priv(netdev);
1301 int queue_num = priv->ae_handle->kinfo.num_tqps;
7a5d2a39 1302 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e
S		 1303 struct hns3_enet_ring *ring;
1304 unsigned int start;
1305 unsigned int idx;
1306 u64 tx_bytes = 0;
1307 u64 rx_bytes = 0;
1308 u64 tx_pkts = 0;
1309 u64 rx_pkts = 0;
0a83231f
JS		 1310 u64 tx_drop = 0;
1311 u64 rx_drop = 0;
76ad4f0e 1312
a3083abb
JS		 1313 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1314 return;
1315
7a5d2a39
JS		 1316 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1317
76ad4f0e
S		 1318 for (idx = 0; idx < queue_num; idx++) {
1319 /* fetch the tx stats */
1320 ring = priv->ring_data[idx].ring;
1321 do {
d36d36ce 1322 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1323 tx_bytes += ring->stats.tx_bytes;
1324 tx_pkts += ring->stats.tx_pkts;
0a83231f
JS		 1325 tx_drop += ring->stats.tx_busy;
1326 tx_drop += ring->stats.sw_err_cnt;
76ad4f0e
S		 1327 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1328
1329 /* fetch the rx stats */
1330 ring = priv->ring_data[idx + queue_num].ring;
1331 do {
d36d36ce 1332 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1333 rx_bytes += ring->stats.rx_bytes;
1334 rx_pkts += ring->stats.rx_pkts;
0a83231f
JS		 1335 rx_drop += ring->stats.non_vld_descs;
1336 rx_drop += ring->stats.err_pkt_len;
1337 rx_drop += ring->stats.l2_err;
76ad4f0e
S		 1338 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1339 }
1340
1341 stats->tx_bytes = tx_bytes;
1342 stats->tx_packets = tx_pkts;
1343 stats->rx_bytes = rx_bytes;
1344 stats->rx_packets = rx_pkts;
1345
1346 stats->rx_errors = netdev->stats.rx_errors;
1347 stats->multicast = netdev->stats.multicast;
1348 stats->rx_length_errors = netdev->stats.rx_length_errors;
1349 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
1350 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1351
1352 stats->tx_errors = netdev->stats.tx_errors;
0a83231f
JS		 1353 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped;
1354 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped;
76ad4f0e
S		 1355 stats->collisions = netdev->stats.collisions;
1356 stats->rx_over_errors = netdev->stats.rx_over_errors;
1357 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1358 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1359 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1360 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1361 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1362 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1363 stats->tx_window_errors = netdev->stats.tx_window_errors;
1364 stats->rx_compressed = netdev->stats.rx_compressed;
1365 stats->tx_compressed = netdev->stats.tx_compressed;
1366}
1367
30d240df 1368static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1369{
30d240df 1370 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
9780cb97 1371 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 1372 struct hnae3_knic_private_info *kinfo = &h->kinfo;
30d240df
YL		 1373 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1374 u8 tc = mqprio_qopt->qopt.num_tc;
1375 u16 mode = mqprio_qopt->mode;
1376 u8 hw = mqprio_qopt->qopt.hw;
1377 bool if_running;
76ad4f0e
S		 1378 int ret;
1379
30d240df
YL		 1380 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1381 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1382 return -EOPNOTSUPP;
1383
76ad4f0e
S		 1384 if (tc > HNAE3_MAX_TC)
1385 return -EINVAL;
1386
76ad4f0e
S		 1387 if (!netdev)
1388 return -EINVAL;
1389
30d240df
YL		 1390 if_running = netif_running(netdev);
1391 if (if_running) {
1392 hns3_nic_net_stop(netdev);
1393 msleep(100);
76ad4f0e
S		 1394 }
1395
30d240df
YL		 1396 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1397 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e 1398 if (ret)
30d240df
YL		 1399 goto out;
1400
30d240df
YL		 1401 ret = hns3_nic_set_real_num_queue(netdev);
1402
1403out:
1404 if (if_running)
1405 hns3_nic_net_open(netdev);
1406
1407 return ret;
76ad4f0e
S		 1408}
1409
2572ac53 1410static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1411 void *type_data)
76ad4f0e 1412{
575ed7d3 1413 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1414 return -EOPNOTSUPP;
76ad4f0e 1415
30d240df 1416 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1417}
1418
1419static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1420 __be16 proto, u16 vid)
1421{
9780cb97 1422 struct hnae3_handle *h = hns3_get_handle(netdev);
103ce052 1423 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1424 int ret = -EIO;
1425
1426 if (h->ae_algo->ops->set_vlan_filter)
1427 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1428
103ce052
YL		 1429 if (!ret)
1430 set_bit(vid, priv->active_vlans);
1431
76ad4f0e
S		 1432 return ret;
1433}
1434
1435static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1436 __be16 proto, u16 vid)
1437{
9780cb97 1438 struct hnae3_handle *h = hns3_get_handle(netdev);
103ce052 1439 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 1440 int ret = -EIO;
1441
1442 if (h->ae_algo->ops->set_vlan_filter)
1443 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1444
103ce052
YL		 1445 if (!ret)
1446 clear_bit(vid, priv->active_vlans);
1447
76ad4f0e
S		 1448 return ret;
1449}
1450
103ce052
YL		 1451static void hns3_restore_vlan(struct net_device *netdev)
1452{
1453 struct hns3_nic_priv *priv = netdev_priv(netdev);
1454 u16 vid;
1455 int ret;
1456
1457 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1458 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
1459 if (ret)
1460 netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n",
1461 vid, ret);
1462 }
1463}
1464
76ad4f0e
S		 1465static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1466 u8 qos, __be16 vlan_proto)
1467{
9780cb97 1468 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1469 int ret = -EIO;
1470
1471 if (h->ae_algo->ops->set_vf_vlan_filter)
1472 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1473 qos, vlan_proto);
1474
1475 return ret;
1476}
1477
a8e8b7ff
S		 1478static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1479{
9780cb97 1480 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1481 bool if_running = netif_running(netdev);
1482 int ret;
1483
1484 if (!h->ae_algo->ops->set_mtu)
1485 return -EOPNOTSUPP;
1486
1487 /* if this was called with netdev up then bring netdevice down */
1488 if (if_running) {
1489 (void)hns3_nic_net_stop(netdev);
1490 msleep(100);
1491 }
1492
1493 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1494 if (ret) {
1495 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1496 ret);
1497 return ret;
1498 }
1499
fe6362f9
FL		 1500 netdev->mtu = new_mtu;
1501
a8e8b7ff
S		 1502 /* if the netdev was running earlier, bring it up again */
1503 if (if_running && hns3_nic_net_open(netdev))
1504 ret = -EINVAL;
1505
1506 return ret;
1507}
1508
f8fa222c
L		 1509static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1510{
1511 struct hns3_nic_priv *priv = netdev_priv(ndev);
1512 struct hns3_enet_ring *tx_ring = NULL;
1513 int timeout_queue = 0;
1514 int hw_head, hw_tail;
1515 int i;
1516
1517 /* Find the stopped queue the same way the stack does */
1518 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1519 struct netdev_queue *q;
1520 unsigned long trans_start;
1521
1522 q = netdev_get_tx_queue(ndev, i);
1523 trans_start = q->trans_start;
1524 if (netif_xmit_stopped(q) &&
1525 time_after(jiffies,
1526 (trans_start + ndev->watchdog_timeo))) {
1527 timeout_queue = i;
1528 break;
1529 }
1530 }
1531
1532 if (i == ndev->num_tx_queues) {
1533 netdev_info(ndev,
1534 "no netdev TX timeout queue found, timeout count: %llu\n",
1535 priv->tx_timeout_count);
1536 return false;
1537 }
1538
1539 tx_ring = priv->ring_data[timeout_queue].ring;
1540
1541 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1542 HNS3_RING_TX_RING_HEAD_REG);
1543 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1544 HNS3_RING_TX_RING_TAIL_REG);
1545 netdev_info(ndev,
1546 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1547 priv->tx_timeout_count,
1548 timeout_queue,
1549 tx_ring->next_to_use,
1550 tx_ring->next_to_clean,
1551 hw_head,
1552 hw_tail,
1553 readl(tx_ring->tqp_vector->mask_addr));
1554
1555 return true;
1556}
1557
1558static void hns3_nic_net_timeout(struct net_device *ndev)
1559{
1560 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1561 struct hnae3_handle *h = priv->ae_handle;
1562
1563 if (!hns3_get_tx_timeo_queue_info(ndev))
1564 return;
1565
1566 priv->tx_timeout_count++;
1567
4aef908d 1568 if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo)))
f8fa222c
L		 1569 return;
1570
4aef908d 1571 /* request the reset */
f8fa222c 1572 if (h->ae_algo->ops->reset_event)
4aef908d 1573 h->ae_algo->ops->reset_event(h);
f8fa222c
L		 1574}
1575
76ad4f0e
S		 1576static const struct net_device_ops hns3_nic_netdev_ops = {
1577 .ndo_open = hns3_nic_net_open,
1578 .ndo_stop = hns3_nic_net_stop,
1579 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1580 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1581 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
a185d723 1582 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1583 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1584 .ndo_set_features = hns3_nic_set_features,
1585 .ndo_get_stats64 = hns3_nic_get_stats64,
1586 .ndo_setup_tc = hns3_nic_setup_tc,
1587 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1588 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1589 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1590 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1591};
1592
bc59f827
FL		 1593static bool hns3_is_phys_func(struct pci_dev *pdev)
1594{
1595 u32 dev_id = pdev->device;
1596
1597 switch (dev_id) {
1598 case HNAE3_DEV_ID_GE:
1599 case HNAE3_DEV_ID_25GE:
1600 case HNAE3_DEV_ID_25GE_RDMA:
1601 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1602 case HNAE3_DEV_ID_50GE_RDMA:
1603 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1604 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1605 return true;
1606 case HNAE3_DEV_ID_100G_VF:
1607 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1608 return false;
1609 default:
1610 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1611 dev_id);
1612 }
1613
1614 return false;
1615}
1616
bc59f827
FL		 1617static void hns3_disable_sriov(struct pci_dev *pdev)
1618{
1619 /* If our VFs are assigned we cannot shut down SR-IOV
1620 * without causing issues, so just leave the hardware
1621 * available but disabled
1622 */
1623 if (pci_vfs_assigned(pdev)) {
1624 dev_warn(&pdev->dev,
1625 "disabling driver while VFs are assigned\n");
1626 return;
1627 }
1628
1629 pci_disable_sriov(pdev);
1630}
1631
76ad4f0e
S		 1632/* hns3_probe - Device initialization routine
1633 * @pdev: PCI device information struct
1634 * @ent: entry in hns3_pci_tbl
1635 *
1636 * hns3_probe initializes a PF identified by a pci_dev structure.
1637 * The OS initialization, configuring of the PF private structure,
1638 * and a hardware reset occur.
1639 *
1640 * Returns 0 on success, negative on failure
1641 */
1642static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1643{
1644 struct hnae3_ae_dev *ae_dev;
1645 int ret;
1646
1647 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1648 GFP_KERNEL);
1649 if (!ae_dev) {
1650 ret = -ENOMEM;
1651 return ret;
1652 }
1653
1654 ae_dev->pdev = pdev;
e92a0843 1655 ae_dev->flag = ent->driver_data;
76ad4f0e
S		 1656 ae_dev->dev_type = HNAE3_DEV_KNIC;
1657 pci_set_drvdata(pdev, ae_dev);
1658
fb919349 1659 hnae3_register_ae_dev(ae_dev);
bc59f827 1660
bc59f827 1661 return 0;
76ad4f0e
S		 1662}
1663
1664/* hns3_remove - Device removal routine
1665 * @pdev: PCI device information struct
1666 */
1667static void hns3_remove(struct pci_dev *pdev)
1668{
1669 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1670
bc59f827
FL		 1671 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1672 hns3_disable_sriov(pdev);
1673
76ad4f0e 1674 hnae3_unregister_ae_dev(ae_dev);
76ad4f0e
S		 1675}
1676
cfeff578
PL		 1677/**
1678 * hns3_pci_sriov_configure
1679 * @pdev: pointer to a pci_dev structure
1680 * @num_vfs: number of VFs to allocate
1681 *
1682 * Enable or change the number of VFs. Called when the user updates the number
1683 * of VFs in sysfs.
1684 **/
baff3ed7 1685static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
cfeff578
PL		 1686{
1687 int ret;
1688
1689 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1690 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1691 return -EINVAL;
1692 }
1693
1694 if (num_vfs) {
1695 ret = pci_enable_sriov(pdev, num_vfs);
1696 if (ret)
1697 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
baff3ed7
SM		 1698 else
1699 return num_vfs;
cfeff578
PL		 1700 } else if (!pci_vfs_assigned(pdev)) {
1701 pci_disable_sriov(pdev);
1702 } else {
1703 dev_warn(&pdev->dev,
1704 "Unable to free VFs because some are assigned to VMs.\n");
1705 }
1706
1707 return 0;
1708}
1709
4f043c3e
YL		 1710static void hns3_shutdown(struct pci_dev *pdev)
1711{
1712 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1713
1714 hnae3_unregister_ae_dev(ae_dev);
1715 devm_kfree(&pdev->dev, ae_dev);
1716 pci_set_drvdata(pdev, NULL);
1717
1718 if (system_state == SYSTEM_POWER_OFF)
1719 pci_set_power_state(pdev, PCI_D3hot);
1720}
1721
76ad4f0e
S		 1722static struct pci_driver hns3_driver = {
1723 .name = hns3_driver_name,
1724 .id_table = hns3_pci_tbl,
1725 .probe = hns3_probe,
1726 .remove = hns3_remove,
4f043c3e 1727 .shutdown = hns3_shutdown,
cfeff578 1728 .sriov_configure = hns3_pci_sriov_configure,
76ad4f0e
S		 1729};
1730
1731/* set default feature to hns3 */
1732static void hns3_set_default_feature(struct net_device *netdev)
1733{
a4c378bb
PL		 1734 struct hnae3_handle *h = hns3_get_handle(netdev);
1735 struct pci_dev *pdev = h->pdev;
1736
76ad4f0e
S		 1737 netdev->priv_flags |= IFF_UNICAST_FLT;
1738
1739 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1740 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1741 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1742 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1743 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1744
1745 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1746
1747 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1748
1749 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1750 NETIF_F_HW_VLAN_CTAG_FILTER |
5f9a7732 1751 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1752 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1753 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1754 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1755 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1756
1757 netdev->vlan_features |=
1758 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1759 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1760 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1761 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1762 NETIF_F_GSO_UDP_TUNNEL_CSUM;
1763
1764 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3849d494 1765 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 1766 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1767 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1768 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1769 NETIF_F_GSO_UDP_TUNNEL_CSUM;
a4c378bb
PL		 1770
1771 if (pdev->revision != 0x20)
1772 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
76ad4f0e
S		 1773}
1774
1775static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1776 struct hns3_desc_cb *cb)
1777{
ccc23ef3 1778 unsigned int order = hnae3_page_order(ring);
76ad4f0e
S		 1779 struct page *p;
1780
1781 p = dev_alloc_pages(order);
1782 if (!p)
1783 return -ENOMEM;
1784
1785 cb->priv = p;
1786 cb->page_offset = 0;
1787 cb->reuse_flag = 0;
1788 cb->buf = page_address(p);
ccc23ef3 1789 cb->length = hnae3_page_size(ring);
76ad4f0e
S		 1790 cb->type = DESC_TYPE_PAGE;
1791
76ad4f0e
S		 1792 return 0;
1793}
1794
1795static void hns3_free_buffer(struct hns3_enet_ring *ring,
1796 struct hns3_desc_cb *cb)
1797{
1798 if (cb->type == DESC_TYPE_SKB)
1799 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1800 else if (!HNAE3_IS_TX_RING(ring))
1801 put_page((struct page *)cb->priv);
1802 memset(cb, 0, sizeof(*cb));
1803}
1804
1805static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1806{
1807 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
1808 cb->length, ring_to_dma_dir(ring));
1809
1810 if (dma_mapping_error(ring_to_dev(ring), cb->dma))
1811 return -EIO;
1812
1813 return 0;
1814}
1815
1816static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
1817 struct hns3_desc_cb *cb)
1818{
1819 if (cb->type == DESC_TYPE_SKB)
1820 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
1821 ring_to_dma_dir(ring));
1822 else
1823 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
1824 ring_to_dma_dir(ring));
1825}
1826
1827static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
1828{
1829 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
1830 ring->desc[i].addr = 0;
1831}
1832
1833static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
1834{
1835 struct hns3_desc_cb *cb = &ring->desc_cb[i];
1836
1837 if (!ring->desc_cb[i].dma)
1838 return;
1839
1840 hns3_buffer_detach(ring, i);
1841 hns3_free_buffer(ring, cb);
1842}
1843
1844static void hns3_free_buffers(struct hns3_enet_ring *ring)
1845{
1846 int i;
1847
1848 for (i = 0; i < ring->desc_num; i++)
1849 hns3_free_buffer_detach(ring, i);
1850}
1851
1852/* free desc along with its attached buffer */
1853static void hns3_free_desc(struct hns3_enet_ring *ring)
1854{
d61c1a80
HT		 1855 int size = ring->desc_num * sizeof(ring->desc[0]);
1856
76ad4f0e
S		 1857 hns3_free_buffers(ring);
1858
d61c1a80
HT		 1859 if (ring->desc) {
1860 dma_free_coherent(ring_to_dev(ring), size,
1861 ring->desc, ring->desc_dma_addr);
1862 ring->desc = NULL;
1863 }
76ad4f0e
S		 1864}
1865
1866static int hns3_alloc_desc(struct hns3_enet_ring *ring)
1867{
1868 int size = ring->desc_num * sizeof(ring->desc[0]);
1869
d61c1a80
HT		 1870 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size,
1871 &ring->desc_dma_addr,
1872 GFP_KERNEL);
76ad4f0e
S		 1873 if (!ring->desc)
1874 return -ENOMEM;
1875
76ad4f0e
S		 1876 return 0;
1877}
1878
1879static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
1880 struct hns3_desc_cb *cb)
1881{
1882 int ret;
1883
1884 ret = hns3_alloc_buffer(ring, cb);
1885 if (ret)
1886 goto out;
1887
1888 ret = hns3_map_buffer(ring, cb);
1889 if (ret)
1890 goto out_with_buf;
1891
1892 return 0;
1893
1894out_with_buf:
564883bb 1895 hns3_free_buffer(ring, cb);
76ad4f0e
S		 1896out:
1897 return ret;
1898}
1899
1900static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
1901{
1902 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
1903
1904 if (ret)
1905 return ret;
1906
1907 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
1908
1909 return 0;
1910}
1911
1912/* Allocate memory for raw pkg, and map with dma */
1913static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
1914{
1915 int i, j, ret;
1916
1917 for (i = 0; i < ring->desc_num; i++) {
1918 ret = hns3_alloc_buffer_attach(ring, i);
1919 if (ret)
1920 goto out_buffer_fail;
1921 }
1922
1923 return 0;
1924
1925out_buffer_fail:
1926 for (j = i - 1; j >= 0; j--)
1927 hns3_free_buffer_detach(ring, j);
1928 return ret;
1929}
1930
1931/* detach a in-used buffer and replace with a reserved one */
1932static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
1933 struct hns3_desc_cb *res_cb)
1934{
b9077428 1935 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 1936 ring->desc_cb[i] = *res_cb;
1937 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
4169a686 1938 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 1939}
1940
1941static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
1942{
1943 ring->desc_cb[i].reuse_flag = 0;
1944 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
1945 + ring->desc_cb[i].page_offset);
4169a686 1946 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 1947}
1948
1949static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
1950 int *pkts)
1951{
1952 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
1953
1954 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
1955 (*bytes) += desc_cb->length;
ccc23ef3 1956 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
76ad4f0e
S		 1957 hns3_free_buffer_detach(ring, ring->next_to_clean);
1958
1959 ring_ptr_move_fw(ring, next_to_clean);
1960}
1961
1962static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
1963{
1964 int u = ring->next_to_use;
1965 int c = ring->next_to_clean;
1966
1967 if (unlikely(h > ring->desc_num))
1968 return 0;
1969
1970 return u > c ? (h > c && h <= u) : (h > c || h <= u);
1971}
1972
6a38a95f 1973void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 1974{
1975 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
1976 struct netdev_queue *dev_queue;
1977 int bytes, pkts;
1978 int head;
1979
1980 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
1981 rmb(); /* Make sure head is ready before touch any data */
1982
1983 if (is_ring_empty(ring) || head == ring->next_to_clean)
6a38a95f 1984 return; /* no data to poll */
76ad4f0e 1985
2ea8667b 1986 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S		 1987 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
1988 ring->next_to_use, ring->next_to_clean);
1989
1990 u64_stats_update_begin(&ring->syncp);
1991 ring->stats.io_err_cnt++;
1992 u64_stats_update_end(&ring->syncp);
6a38a95f 1993 return;
76ad4f0e
S		 1994 }
1995
1996 bytes = 0;
1997 pkts = 0;
6a38a95f 1998 while (head != ring->next_to_clean) {
76ad4f0e
S		 1999 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
2000 /* Issue prefetch for next Tx descriptor */
2001 prefetch(&ring->desc_cb[ring->next_to_clean]);
76ad4f0e
S		 2002 }
2003
2004 ring->tqp_vector->tx_group.total_bytes += bytes;
2005 ring->tqp_vector->tx_group.total_packets += pkts;
2006
2007 u64_stats_update_begin(&ring->syncp);
2008 ring->stats.tx_bytes += bytes;
2009 ring->stats.tx_pkts += pkts;
2010 u64_stats_update_end(&ring->syncp);
2011
2012 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2013 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2014
2015 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2016 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2017 /* Make sure that anybody stopping the queue after this
2018 * sees the new next_to_clean.
2019 */
2020 smp_mb();
2021 if (netif_tx_queue_stopped(dev_queue)) {
2022 netif_tx_wake_queue(dev_queue);
2023 ring->stats.restart_queue++;
2024 }
2025 }
76ad4f0e
S		 2026}
2027
2028static int hns3_desc_unused(struct hns3_enet_ring *ring)
2029{
2030 int ntc = ring->next_to_clean;
2031 int ntu = ring->next_to_use;
2032
2033 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2034}
2035
2036static void
2037hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2038{
2039 struct hns3_desc_cb *desc_cb;
2040 struct hns3_desc_cb res_cbs;
2041 int i, ret;
2042
2043 for (i = 0; i < cleand_count; i++) {
2044 desc_cb = &ring->desc_cb[ring->next_to_use];
2045 if (desc_cb->reuse_flag) {
2046 u64_stats_update_begin(&ring->syncp);
2047 ring->stats.reuse_pg_cnt++;
2048 u64_stats_update_end(&ring->syncp);
2049
2050 hns3_reuse_buffer(ring, ring->next_to_use);
2051 } else {
2052 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2053 if (ret) {
2054 u64_stats_update_begin(&ring->syncp);
2055 ring->stats.sw_err_cnt++;
2056 u64_stats_update_end(&ring->syncp);
2057
2058 netdev_err(ring->tqp->handle->kinfo.netdev,
2059 "hnae reserve buffer map failed.\n");
2060 break;
2061 }
2062 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2063 }
2064
2065 ring_ptr_move_fw(ring, next_to_use);
2066 }
2067
2068 wmb(); /* Make all data has been write before submit */
2069 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2070}
2071
76ad4f0e
S		 2072static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2073 struct hns3_enet_ring *ring, int pull_len,
2074 struct hns3_desc_cb *desc_cb)
2075{
2076 struct hns3_desc *desc;
e56a15b7
HT		 2077 u32 truesize;
2078 int size;
76ad4f0e
S		 2079 int last_offset;
2080 bool twobufs;
2081
2082 twobufs = ((PAGE_SIZE < 8192) &&
ccc23ef3 2083 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
76ad4f0e
S		 2084
2085 desc = &ring->desc[ring->next_to_clean];
2086 size = le16_to_cpu(desc->rx.size);
2087
ccc23ef3 2088 truesize = hnae3_buf_size(ring);
885a882a
PL		 2089
2090 if (!twobufs)
ccc23ef3 2091 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
76ad4f0e
S		 2092
2093 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
885a882a 2094 size - pull_len, truesize);
76ad4f0e
S		 2095
2096 /* Avoid re-using remote pages,flag default unreuse */
2097 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2098 return;
2099
2100 if (twobufs) {
2101 /* If we are only owner of page we can reuse it */
2102 if (likely(page_count(desc_cb->priv) == 1)) {
2103 /* Flip page offset to other buffer */
2104 desc_cb->page_offset ^= truesize;
2105
2106 desc_cb->reuse_flag = 1;
2107 /* bump ref count on page before it is given*/
2108 get_page(desc_cb->priv);
2109 }
2110 return;
2111 }
2112
2113 /* Move offset up to the next cache line */
2114 desc_cb->page_offset += truesize;
2115
2116 if (desc_cb->page_offset <= last_offset) {
2117 desc_cb->reuse_flag = 1;
2118 /* Bump ref count on page before it is given*/
2119 get_page(desc_cb->priv);
2120 }
2121}
2122
2123static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2124 struct hns3_desc *desc)
2125{
2126 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2127 int l3_type, l4_type;
2128 u32 bd_base_info;
2129 int ol4_type;
2130 u32 l234info;
2131
2132 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2133 l234info = le32_to_cpu(desc->rx.l234_info);
2134
2135 skb->ip_summed = CHECKSUM_NONE;
2136
2137 skb_checksum_none_assert(skb);
2138
2139 if (!(netdev->features & NETIF_F_RXCSUM))
2140 return;
2141
2142 /* check if hardware has done checksum */
ccc23ef3 2143 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
76ad4f0e
S		 2144 return;
2145
ccc23ef3
PL		 2146 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2147 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2148 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2149 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
76ad4f0e
S		 2150 netdev_err(netdev, "L3/L4 error pkt\n");
2151 u64_stats_update_begin(&ring->syncp);
2152 ring->stats.l3l4_csum_err++;
2153 u64_stats_update_end(&ring->syncp);
2154
2155 return;
2156 }
2157
ccc23ef3
PL		 2158 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2159 HNS3_RXD_L3ID_S);
2160 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2161 HNS3_RXD_L4ID_S);
76ad4f0e 2162
ccc23ef3
PL		 2163 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2164 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2165 switch (ol4_type) {
2166 case HNS3_OL4_TYPE_MAC_IN_UDP:
2167 case HNS3_OL4_TYPE_NVGRE:
2168 skb->csum_level = 1;
64061deb 2169 /* fall through */
76ad4f0e
S		 2170 case HNS3_OL4_TYPE_NO_TUN:
2171 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
ffa051fa
PL		 2172 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2173 l3_type == HNS3_L3_TYPE_IPV6) &&
2174 (l4_type == HNS3_L4_TYPE_UDP ||
2175 l4_type == HNS3_L4_TYPE_TCP ||
2176 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2177 skb->ip_summed = CHECKSUM_UNNECESSARY;
2178 break;
2179 }
2180}
2181
d43e5aca
YL		 2182static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2183{
2184 napi_gro_receive(&ring->tqp_vector->napi, skb);
2185}
2186
1e8f8bd3
PL		 2187static u16 hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2188 struct hns3_desc *desc, u32 l234info)
2189{
2190 struct pci_dev *pdev = ring->tqp->handle->pdev;
2191 u16 vlan_tag;
2192
2193 if (pdev->revision == 0x20) {
2194 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2195 if (!(vlan_tag & VLAN_VID_MASK))
2196 vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2197
2198 return vlan_tag;
2199 }
2200
2201#define HNS3_STRP_OUTER_VLAN 0x1
2202#define HNS3_STRP_INNER_VLAN 0x2
2203
ccc23ef3
PL		 2204 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2205 HNS3_RXD_STRP_TAGP_S)) {
1e8f8bd3
PL		 2206 case HNS3_STRP_OUTER_VLAN:
2207 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2208 break;
2209 case HNS3_STRP_INNER_VLAN:
2210 vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2211 break;
2212 default:
2213 vlan_tag = 0;
2214 break;
2215 }
2216
2217 return vlan_tag;
2218}
2219
76ad4f0e
S		 2220static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2221 struct sk_buff **out_skb, int *out_bnum)
2222{
2223 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2224 struct hns3_desc_cb *desc_cb;
2225 struct hns3_desc *desc;
2226 struct sk_buff *skb;
2227 unsigned char *va;
2228 u32 bd_base_info;
2229 int pull_len;
2230 u32 l234info;
2231 int length;
2232 int bnum;
2233
2234 desc = &ring->desc[ring->next_to_clean];
2235 desc_cb = &ring->desc_cb[ring->next_to_clean];
2236
2237 prefetch(desc);
2238
ca61f05e 2239 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2240 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 2241
2242 /* Check valid BD */
ccc23ef3 2243 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
76ad4f0e
S		 2244 return -EFAULT;
2245
2246 va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
2247
2248 /* Prefetch first cache line of first page
2249 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2250 * line size is 64B so need to prefetch twice to make it 128B. But in
2251 * actual we can have greater size of caches with 128B Level 1 cache
2252 * lines. In such a case, single fetch would suffice to cache in the
2253 * relevant part of the header.
2254 */
2255 prefetch(va);
2256#if L1_CACHE_BYTES < 128
2257 prefetch(va + L1_CACHE_BYTES);
2258#endif
2259
2260 skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2261 HNS3_RX_HEAD_SIZE);
2262 if (unlikely(!skb)) {
2263 netdev_err(netdev, "alloc rx skb fail\n");
2264
2265 u64_stats_update_begin(&ring->syncp);
2266 ring->stats.sw_err_cnt++;
2267 u64_stats_update_end(&ring->syncp);
2268
2269 return -ENOMEM;
2270 }
2271
2272 prefetchw(skb->data);
2273
2274 bnum = 1;
2275 if (length <= HNS3_RX_HEAD_SIZE) {
2276 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2277
2278 /* We can reuse buffer as-is, just make sure it is local */
2279 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2280 desc_cb->reuse_flag = 1;
2281 else /* This page cannot be reused so discard it */
2282 put_page(desc_cb->priv);
2283
2284 ring_ptr_move_fw(ring, next_to_clean);
2285 } else {
2286 u64_stats_update_begin(&ring->syncp);
2287 ring->stats.seg_pkt_cnt++;
2288 u64_stats_update_end(&ring->syncp);
2289
42b927ba
PL		 2290 pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2291
76ad4f0e
S		 2292 memcpy(__skb_put(skb, pull_len), va,
2293 ALIGN(pull_len, sizeof(long)));
2294
2295 hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb);
2296 ring_ptr_move_fw(ring, next_to_clean);
2297
ccc23ef3 2298 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
76ad4f0e
S		 2299 desc = &ring->desc[ring->next_to_clean];
2300 desc_cb = &ring->desc_cb[ring->next_to_clean];
2301 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2302 hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb);
2303 ring_ptr_move_fw(ring, next_to_clean);
2304 bnum++;
2305 }
2306 }
2307
2308 *out_bnum = bnum;
1e8f8bd3 2309
928d369a 2310 l234info = le32_to_cpu(desc->rx.l234_info);
2311
ca61f05e
PL		 2312 /* Based on hw strategy, the tag offloaded will be stored at
2313 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2314 * in one layer tag case.
2315 */
2316 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2317 u16 vlan_tag;
2318
1e8f8bd3 2319 vlan_tag = hns3_parse_vlan_tag(ring, desc, l234info);
ca61f05e
PL		 2320 if (vlan_tag & VLAN_VID_MASK)
2321 __vlan_hwaccel_put_tag(skb,
2322 htons(ETH_P_8021Q),
2323 vlan_tag);
2324 }
2325
ccc23ef3 2326 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
76ad4f0e
S		 2327 netdev_err(netdev, "no valid bd,%016llx,%016llx\n",
2328 ((u64 *)desc)[0], ((u64 *)desc)[1]);
2329 u64_stats_update_begin(&ring->syncp);
2330 ring->stats.non_vld_descs++;
2331 u64_stats_update_end(&ring->syncp);
2332
2333 dev_kfree_skb_any(skb);
2334 return -EINVAL;
2335 }
2336
2337 if (unlikely((!desc->rx.pkt_len) ||
ccc23ef3 2338 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
76ad4f0e
S		 2339 netdev_err(netdev, "truncated pkt\n");
2340 u64_stats_update_begin(&ring->syncp);
2341 ring->stats.err_pkt_len++;
2342 u64_stats_update_end(&ring->syncp);
2343
2344 dev_kfree_skb_any(skb);
2345 return -EFAULT;
2346 }
2347
ccc23ef3 2348 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
76ad4f0e
S		 2349 netdev_err(netdev, "L2 error pkt\n");
2350 u64_stats_update_begin(&ring->syncp);
2351 ring->stats.l2_err++;
2352 u64_stats_update_end(&ring->syncp);
2353
2354 dev_kfree_skb_any(skb);
2355 return -EFAULT;
2356 }
2357
2358 u64_stats_update_begin(&ring->syncp);
2359 ring->stats.rx_pkts++;
2360 ring->stats.rx_bytes += skb->len;
2361 u64_stats_update_end(&ring->syncp);
2362
2363 ring->tqp_vector->rx_group.total_bytes += skb->len;
2364
2365 hns3_rx_checksum(ring, skb, desc);
2366 return 0;
2367}
2368
d43e5aca
YL		 2369int hns3_clean_rx_ring(
2370 struct hns3_enet_ring *ring, int budget,
2371 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2372{
2373#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2374 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2375 int recv_pkts, recv_bds, clean_count, err;
2376 int unused_count = hns3_desc_unused(ring);
2377 struct sk_buff *skb = NULL;
2378 int num, bnum = 0;
2379
2380 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2381 rmb(); /* Make sure num taken effect before the other data is touched */
2382
2383 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2384 num -= unused_count;
2385
2386 while (recv_pkts < budget && recv_bds < num) {
2387 /* Reuse or realloc buffers */
2388 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2389 hns3_nic_alloc_rx_buffers(ring,
2390 clean_count + unused_count);
2391 clean_count = 0;
2392 unused_count = hns3_desc_unused(ring);
2393 }
2394
2395 /* Poll one pkt */
2396 err = hns3_handle_rx_bd(ring, &skb, &bnum);
2397 if (unlikely(!skb)) /* This fault cannot be repaired */
2398 goto out;
2399
2400 recv_bds += bnum;
2401 clean_count += bnum;
2402 if (unlikely(err)) { /* Do jump the err */
2403 recv_pkts++;
2404 continue;
2405 }
2406
2407 /* Do update ip stack process */
2408 skb->protocol = eth_type_trans(skb, netdev);
d43e5aca 2409 rx_fn(ring, skb);
76ad4f0e
S		 2410
2411 recv_pkts++;
2412 }
2413
2414out:
2415 /* Make all data has been write before submit */
2416 if (clean_count + unused_count > 0)
2417 hns3_nic_alloc_rx_buffers(ring,
2418 clean_count + unused_count);
2419
2420 return recv_pkts;
2421}
2422
2423static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2424{
50477f37
FL		 2425 struct hns3_enet_tqp_vector *tqp_vector =
2426 ring_group->ring->tqp_vector;
76ad4f0e 2427 enum hns3_flow_level_range new_flow_level;
50477f37
FL		 2428 int packets_per_msecs;
2429 int bytes_per_msecs;
2430 u32 time_passed_ms;
76ad4f0e 2431 u16 new_int_gl;
76ad4f0e 2432
50477f37 2433 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies)
76ad4f0e
S		 2434 return false;
2435
2436 if (ring_group->total_packets == 0) {
d420d2de
YL		 2437 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2438 ring_group->coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 2439 return true;
2440 }
2441
2442 /* Simple throttlerate management
2443 * 0-10MB/s lower (50000 ints/s)
2444 * 10-20MB/s middle (20000 ints/s)
2445 * 20-1249MB/s high (18000 ints/s)
2446 * > 40000pps ultra (8000 ints/s)
2447 */
d420d2de
YL		 2448 new_flow_level = ring_group->coal.flow_level;
2449 new_int_gl = ring_group->coal.int_gl;
50477f37
FL		 2450 time_passed_ms =
2451 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2452
2453 if (!time_passed_ms)
2454 return false;
2455
2456 do_div(ring_group->total_packets, time_passed_ms);
2457 packets_per_msecs = ring_group->total_packets;
2458
2459 do_div(ring_group->total_bytes, time_passed_ms);
2460 bytes_per_msecs = ring_group->total_bytes;
2461
2462#define HNS3_RX_LOW_BYTE_RATE 10000
2463#define HNS3_RX_MID_BYTE_RATE 20000
76ad4f0e
S		 2464
2465 switch (new_flow_level) {
2466 case HNS3_FLOW_LOW:
50477f37 2467 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2468 new_flow_level = HNS3_FLOW_MID;
2469 break;
2470 case HNS3_FLOW_MID:
50477f37 2471 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2472 new_flow_level = HNS3_FLOW_HIGH;
50477f37 2473 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2474 new_flow_level = HNS3_FLOW_LOW;
2475 break;
2476 case HNS3_FLOW_HIGH:
2477 case HNS3_FLOW_ULTRA:
2478 default:
50477f37 2479 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2480 new_flow_level = HNS3_FLOW_MID;
2481 break;
2482 }
2483
50477f37
FL		 2484#define HNS3_RX_ULTRA_PACKET_RATE 40
2485
2486 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2487 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 2488 new_flow_level = HNS3_FLOW_ULTRA;
2489
2490 switch (new_flow_level) {
2491 case HNS3_FLOW_LOW:
2492 new_int_gl = HNS3_INT_GL_50K;
2493 break;
2494 case HNS3_FLOW_MID:
2495 new_int_gl = HNS3_INT_GL_20K;
2496 break;
2497 case HNS3_FLOW_HIGH:
2498 new_int_gl = HNS3_INT_GL_18K;
2499 break;
2500 case HNS3_FLOW_ULTRA:
2501 new_int_gl = HNS3_INT_GL_8K;
2502 break;
2503 default:
2504 break;
2505 }
2506
2507 ring_group->total_bytes = 0;
2508 ring_group->total_packets = 0;
d420d2de
YL		 2509 ring_group->coal.flow_level = new_flow_level;
2510 if (new_int_gl != ring_group->coal.int_gl) {
2511 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 2512 return true;
2513 }
2514 return false;
2515}
2516
2517static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2518{
dc114fce
FL		 2519 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2520 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2521 bool rx_update, tx_update;
2522
3f97bd23
FL		 2523 if (tqp_vector->int_adapt_down > 0) {
2524 tqp_vector->int_adapt_down--;
2525 return;
2526 }
2527
d420d2de 2528 if (rx_group->coal.gl_adapt_enable) {
dc114fce
FL		 2529 rx_update = hns3_get_new_int_gl(rx_group);
2530 if (rx_update)
2531 hns3_set_vector_coalesce_rx_gl(tqp_vector,
d420d2de 2532 rx_group->coal.int_gl);
dc114fce
FL		 2533 }
2534
d420d2de 2535 if (tx_group->coal.gl_adapt_enable) {
dc114fce
FL		 2536 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group);
2537 if (tx_update)
2538 hns3_set_vector_coalesce_tx_gl(tqp_vector,
d420d2de 2539 tx_group->coal.int_gl);
76ad4f0e 2540 }
3f97bd23 2541
50477f37 2542 tqp_vector->last_jiffies = jiffies;
3f97bd23 2543 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START;
76ad4f0e
S		 2544}
2545
2546static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2547{
2548 struct hns3_enet_ring *ring;
2549 int rx_pkt_total = 0;
2550
2551 struct hns3_enet_tqp_vector *tqp_vector =
2552 container_of(napi, struct hns3_enet_tqp_vector, napi);
2553 bool clean_complete = true;
2554 int rx_budget;
2555
2556 /* Since the actual Tx work is minimal, we can give the Tx a larger
2557 * budget and be more aggressive about cleaning up the Tx descriptors.
2558 */
6a38a95f
PL		 2559 hns3_for_each_ring(ring, tqp_vector->tx_group)
2560 hns3_clean_tx_ring(ring);
76ad4f0e
S		 2561
2562 /* make sure rx ring budget not smaller than 1 */
2563 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2564
2565 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 2566 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2567 hns3_rx_skb);
76ad4f0e
S		 2568
2569 if (rx_cleaned >= rx_budget)
2570 clean_complete = false;
2571
2572 rx_pkt_total += rx_cleaned;
2573 }
2574
2575 tqp_vector->rx_group.total_packets += rx_pkt_total;
2576
2577 if (!clean_complete)
2578 return budget;
2579
2580 napi_complete(napi);
2581 hns3_update_new_int_gl(tqp_vector);
2582 hns3_mask_vector_irq(tqp_vector, 1);
2583
2584 return rx_pkt_total;
2585}
2586
2587static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2588 struct hnae3_ring_chain_node *head)
2589{
2590 struct pci_dev *pdev = tqp_vector->handle->pdev;
2591 struct hnae3_ring_chain_node *cur_chain = head;
2592 struct hnae3_ring_chain_node *chain;
2593 struct hns3_enet_ring *tx_ring;
2594 struct hns3_enet_ring *rx_ring;
2595
2596 tx_ring = tqp_vector->tx_group.ring;
2597 if (tx_ring) {
2598 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
ccc23ef3
PL		 2599 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2600 HNAE3_RING_TYPE_TX);
2601 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2602 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 2603
2604 cur_chain->next = NULL;
2605
2606 while (tx_ring->next) {
2607 tx_ring = tx_ring->next;
2608
2609 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2610 GFP_KERNEL);
2611 if (!chain)
2612 return -ENOMEM;
2613
2614 cur_chain->next = chain;
2615 chain->tqp_index = tx_ring->tqp->tqp_index;
ccc23ef3
PL		 2616 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2617 HNAE3_RING_TYPE_TX);
2618 hnae3_set_field(chain->int_gl_idx,
2619 HNAE3_RING_GL_IDX_M,
2620 HNAE3_RING_GL_IDX_S,
2621 HNAE3_RING_GL_TX);
76ad4f0e
S		 2622
2623 cur_chain = chain;
2624 }
2625 }
2626
2627 rx_ring = tqp_vector->rx_group.ring;
2628 if (!tx_ring && rx_ring) {
2629 cur_chain->next = NULL;
2630 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
ccc23ef3
PL		 2631 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2632 HNAE3_RING_TYPE_RX);
2633 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2634 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 2635
2636 rx_ring = rx_ring->next;
2637 }
2638
2639 while (rx_ring) {
2640 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
2641 if (!chain)
2642 return -ENOMEM;
2643
2644 cur_chain->next = chain;
2645 chain->tqp_index = rx_ring->tqp->tqp_index;
ccc23ef3
PL		 2646 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2647 HNAE3_RING_TYPE_RX);
2648 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2649 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
f230c6c5 2650
76ad4f0e
S		 2651 cur_chain = chain;
2652
2653 rx_ring = rx_ring->next;
2654 }
2655
2656 return 0;
2657}
2658
2659static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2660 struct hnae3_ring_chain_node *head)
2661{
2662 struct pci_dev *pdev = tqp_vector->handle->pdev;
2663 struct hnae3_ring_chain_node *chain_tmp, *chain;
2664
2665 chain = head->next;
2666
2667 while (chain) {
2668 chain_tmp = chain->next;
2669 devm_kfree(&pdev->dev, chain);
2670 chain = chain_tmp;
2671 }
2672}
2673
2674static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
2675 struct hns3_enet_ring *ring)
2676{
2677 ring->next = group->ring;
2678 group->ring = ring;
2679
2680 group->count++;
2681}
2682
15040788
PL		 2683static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
2684{
2685 struct pci_dev *pdev = priv->ae_handle->pdev;
2686 struct hns3_enet_tqp_vector *tqp_vector;
2687 int num_vectors = priv->vector_num;
2688 int numa_node;
2689 int vector_i;
2690
2691 numa_node = dev_to_node(&pdev->dev);
2692
2693 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
2694 tqp_vector = &priv->tqp_vector[vector_i];
2695 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
2696 &tqp_vector->affinity_mask);
2697 }
2698}
2699
76ad4f0e
S		 2700static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
2701{
2702 struct hnae3_ring_chain_node vector_ring_chain;
2703 struct hnae3_handle *h = priv->ae_handle;
2704 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 2705 int ret = 0;
2706 u16 i;
2707
15040788
PL		 2708 hns3_nic_set_cpumask(priv);
2709
6cbd6d33
YL		 2710 for (i = 0; i < priv->vector_num; i++) {
2711 tqp_vector = &priv->tqp_vector[i];
2712 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
2713 tqp_vector->num_tqps = 0;
2714 }
76ad4f0e 2715
6cbd6d33
YL		 2716 for (i = 0; i < h->kinfo.num_tqps; i++) {
2717 u16 vector_i = i % priv->vector_num;
2718 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 2719
2720 tqp_vector = &priv->tqp_vector[vector_i];
2721
2722 hns3_add_ring_to_group(&tqp_vector->tx_group,
2723 priv->ring_data[i].ring);
2724
2725 hns3_add_ring_to_group(&tqp_vector->rx_group,
2726 priv->ring_data[i + tqp_num].ring);
2727
76ad4f0e
S		 2728 priv->ring_data[i].ring->tqp_vector = tqp_vector;
2729 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
6cbd6d33 2730 tqp_vector->num_tqps++;
76ad4f0e
S		 2731 }
2732
6cbd6d33 2733 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 2734 tqp_vector = &priv->tqp_vector[i];
2735
2736 tqp_vector->rx_group.total_bytes = 0;
2737 tqp_vector->rx_group.total_packets = 0;
2738 tqp_vector->tx_group.total_bytes = 0;
2739 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 2740 tqp_vector->handle = h;
2741
2742 ret = hns3_get_vector_ring_chain(tqp_vector,
2743 &vector_ring_chain);
2744 if (ret)
6cbd6d33 2745 return ret;
76ad4f0e
S		 2746
2747 ret = h->ae_algo->ops->map_ring_to_vector(h,
2748 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 2749
2750 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2751
6cbd6d33
YL		 2752 if (ret)
2753 return ret;
2754
76ad4f0e
S		 2755 netif_napi_add(priv->netdev, &tqp_vector->napi,
2756 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
2757 }
2758
6cbd6d33
YL		 2759 return 0;
2760}
2761
2762static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
2763{
2764 struct hnae3_handle *h = priv->ae_handle;
2765 struct hns3_enet_tqp_vector *tqp_vector;
2766 struct hnae3_vector_info *vector;
2767 struct pci_dev *pdev = h->pdev;
2768 u16 tqp_num = h->kinfo.num_tqps;
2769 u16 vector_num;
2770 int ret = 0;
2771 u16 i;
2772
2773 /* RSS size, cpu online and vector_num should be the same */
2774 /* Should consider 2p/4p later */
2775 vector_num = min_t(u16, num_online_cpus(), tqp_num);
2776 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
2777 GFP_KERNEL);
2778 if (!vector)
2779 return -ENOMEM;
2780
2781 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
2782
2783 priv->vector_num = vector_num;
2784 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
2785 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
2786 GFP_KERNEL);
2787 if (!priv->tqp_vector) {
2788 ret = -ENOMEM;
2789 goto out;
2790 }
2791
2792 for (i = 0; i < priv->vector_num; i++) {
2793 tqp_vector = &priv->tqp_vector[i];
2794 tqp_vector->idx = i;
2795 tqp_vector->mask_addr = vector[i].io_addr;
2796 tqp_vector->vector_irq = vector[i].vector;
2797 hns3_vector_gl_rl_init(tqp_vector, priv);
2798 }
2799
76ad4f0e
S		 2800out:
2801 devm_kfree(&pdev->dev, vector);
2802 return ret;
2803}
2804
6cbd6d33
YL		 2805static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
2806{
2807 group->ring = NULL;
2808 group->count = 0;
2809}
2810
76ad4f0e
S		 2811static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
2812{
2813 struct hnae3_ring_chain_node vector_ring_chain;
2814 struct hnae3_handle *h = priv->ae_handle;
2815 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e
S		 2816 int i, ret;
2817
2818 for (i = 0; i < priv->vector_num; i++) {
2819 tqp_vector = &priv->tqp_vector[i];
2820
2821 ret = hns3_get_vector_ring_chain(tqp_vector,
2822 &vector_ring_chain);
2823 if (ret)
2824 return ret;
2825
2826 ret = h->ae_algo->ops->unmap_ring_from_vector(h,
2827 tqp_vector->vector_irq, &vector_ring_chain);
2828 if (ret)
2829 return ret;
2830
2831 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
2832
2833 if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) {
2834 (void)irq_set_affinity_hint(
2835 priv->tqp_vector[i].vector_irq,
2836 NULL);
ae064e61 2837 free_irq(priv->tqp_vector[i].vector_irq,
2838 &priv->tqp_vector[i]);
76ad4f0e
S		 2839 }
2840
2841 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED;
6cbd6d33
YL		 2842 hns3_clear_ring_group(&tqp_vector->rx_group);
2843 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 2844 netif_napi_del(&priv->tqp_vector[i].napi);
2845 }
2846
6cbd6d33
YL		 2847 return 0;
2848}
2849
2850static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
2851{
2852 struct hnae3_handle *h = priv->ae_handle;
2853 struct pci_dev *pdev = h->pdev;
2854 int i, ret;
2855
2856 for (i = 0; i < priv->vector_num; i++) {
2857 struct hns3_enet_tqp_vector *tqp_vector;
2858
2859 tqp_vector = &priv->tqp_vector[i];
2860 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
2861 if (ret)
2862 return ret;
2863 }
76ad4f0e 2864
6cbd6d33 2865 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 2866 return 0;
2867}
2868
2869static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
2870 int ring_type)
2871{
2872 struct hns3_nic_ring_data *ring_data = priv->ring_data;
2873 int queue_num = priv->ae_handle->kinfo.num_tqps;
2874 struct pci_dev *pdev = priv->ae_handle->pdev;
2875 struct hns3_enet_ring *ring;
2876
2877 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
2878 if (!ring)
2879 return -ENOMEM;
2880
2881 if (ring_type == HNAE3_RING_TYPE_TX) {
2882 ring_data[q->tqp_index].ring = ring;
66b44730 2883 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 2884 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
2885 } else {
2886 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 2887 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 2888 ring->io_base = q->io_base;
2889 }
2890
ccc23ef3 2891 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 2892
76ad4f0e
S		 2893 ring->tqp = q;
2894 ring->desc = NULL;
2895 ring->desc_cb = NULL;
2896 ring->dev = priv->dev;
2897 ring->desc_dma_addr = 0;
2898 ring->buf_size = q->buf_size;
2899 ring->desc_num = q->desc_num;
2900 ring->next_to_use = 0;
2901 ring->next_to_clean = 0;
2902
2903 return 0;
2904}
2905
2906static int hns3_queue_to_ring(struct hnae3_queue *tqp,
2907 struct hns3_nic_priv *priv)
2908{
2909 int ret;
2910
2911 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
2912 if (ret)
2913 return ret;
2914
2915 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
2916 if (ret)
2917 return ret;
2918
2919 return 0;
2920}
2921
2922static int hns3_get_ring_config(struct hns3_nic_priv *priv)
2923{
2924 struct hnae3_handle *h = priv->ae_handle;
2925 struct pci_dev *pdev = h->pdev;
2926 int i, ret;
2927
2928 priv->ring_data = devm_kzalloc(&pdev->dev, h->kinfo.num_tqps *
2929 sizeof(*priv->ring_data) * 2,
2930 GFP_KERNEL);
2931 if (!priv->ring_data)
2932 return -ENOMEM;
2933
2934 for (i = 0; i < h->kinfo.num_tqps; i++) {
2935 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
2936 if (ret)
2937 goto err;
2938 }
2939
2940 return 0;
2941err:
2942 devm_kfree(&pdev->dev, priv->ring_data);
2943 return ret;
2944}
2945
f1f779ce
PL		 2946static void hns3_put_ring_config(struct hns3_nic_priv *priv)
2947{
2948 struct hnae3_handle *h = priv->ae_handle;
2949 int i;
2950
2951 for (i = 0; i < h->kinfo.num_tqps; i++) {
2952 devm_kfree(priv->dev, priv->ring_data[i].ring);
2953 devm_kfree(priv->dev,
2954 priv->ring_data[i + h->kinfo.num_tqps].ring);
2955 }
2956 devm_kfree(priv->dev, priv->ring_data);
2957}
2958
76ad4f0e
S		 2959static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
2960{
2961 int ret;
2962
2963 if (ring->desc_num <= 0 || ring->buf_size <= 0)
2964 return -EINVAL;
2965
2966 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
2967 GFP_KERNEL);
2968 if (!ring->desc_cb) {
2969 ret = -ENOMEM;
2970 goto out;
2971 }
2972
2973 ret = hns3_alloc_desc(ring);
2974 if (ret)
2975 goto out_with_desc_cb;
2976
2977 if (!HNAE3_IS_TX_RING(ring)) {
2978 ret = hns3_alloc_ring_buffers(ring);
2979 if (ret)
2980 goto out_with_desc;
2981 }
2982
2983 return 0;
2984
2985out_with_desc:
2986 hns3_free_desc(ring);
2987out_with_desc_cb:
2988 kfree(ring->desc_cb);
2989 ring->desc_cb = NULL;
2990out:
2991 return ret;
2992}
2993
2994static void hns3_fini_ring(struct hns3_enet_ring *ring)
2995{
2996 hns3_free_desc(ring);
2997 kfree(ring->desc_cb);
2998 ring->desc_cb = NULL;
2999 ring->next_to_clean = 0;
3000 ring->next_to_use = 0;
3001}
3002
1db9b1bf 3003static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3004{
3005 int bd_size_type;
3006
3007 switch (buf_size) {
3008 case 512:
3009 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3010 break;
3011 case 1024:
3012 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3013 break;
3014 case 2048:
3015 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3016 break;
3017 case 4096:
3018 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3019 break;
3020 default:
3021 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3022 }
3023
3024 return bd_size_type;
3025}
3026
3027static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3028{
3029 dma_addr_t dma = ring->desc_dma_addr;
3030 struct hnae3_queue *q = ring->tqp;
3031
3032 if (!HNAE3_IS_TX_RING(ring)) {
3033 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3034 (u32)dma);
3035 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3036 (u32)((dma >> 31) >> 1));
3037
3038 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3039 hns3_buf_size2type(ring->buf_size));
3040 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3041 ring->desc_num / 8 - 1);
3042
3043 } else {
3044 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3045 (u32)dma);
3046 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3047 (u32)((dma >> 31) >> 1));
3048
76ad4f0e
S		 3049 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3050 ring->desc_num / 8 - 1);
3051 }
3052}
3053
fe46c859
YL		 3054static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3055{
3056 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3057 int i;
3058
3059 for (i = 0; i < HNAE3_MAX_TC; i++) {
3060 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3061 int j;
3062
3063 if (!tc_info->enable)
3064 continue;
3065
3066 for (j = 0; j < tc_info->tqp_count; j++) {
3067 struct hnae3_queue *q;
3068
3069 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3070 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3071 tc_info->tc);
3072 }
3073 }
3074}
3075
5668abda 3076int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3077{
3078 struct hnae3_handle *h = priv->ae_handle;
3079 int ring_num = h->kinfo.num_tqps * 2;
3080 int i, j;
3081 int ret;
3082
3083 for (i = 0; i < ring_num; i++) {
3084 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3085 if (ret) {
3086 dev_err(priv->dev,
3087 "Alloc ring memory fail! ret=%d\n", ret);
3088 goto out_when_alloc_ring_memory;
3089 }
3090
76ad4f0e
S		 3091 u64_stats_init(&priv->ring_data[i].ring->syncp);
3092 }
3093
3094 return 0;
3095
3096out_when_alloc_ring_memory:
3097 for (j = i - 1; j >= 0; j--)
ee83f776 3098 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 3099
3100 return -ENOMEM;
3101}
3102
5668abda 3103int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3104{
3105 struct hnae3_handle *h = priv->ae_handle;
3106 int i;
3107
3108 for (i = 0; i < h->kinfo.num_tqps; i++) {
3109 if (h->ae_algo->ops->reset_queue)
3110 h->ae_algo->ops->reset_queue(h, i);
3111
3112 hns3_fini_ring(priv->ring_data[i].ring);
3113 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3114 }
76ad4f0e
S		 3115 return 0;
3116}
3117
3118/* Set mac addr if it is configured. or leave it to the AE driver */
edf76c8e 3119static void hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 3120{
3121 struct hns3_nic_priv *priv = netdev_priv(netdev);
3122 struct hnae3_handle *h = priv->ae_handle;
3123 u8 mac_addr_temp[ETH_ALEN];
3124
edf76c8e 3125 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 3126 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3127 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3128 }
3129
3130 /* Check if the MAC address is valid, if not get a random one */
3131 if (!is_valid_ether_addr(netdev->dev_addr)) {
3132 eth_hw_addr_random(netdev);
3133 dev_warn(priv->dev, "using random MAC address %pM\n",
3134 netdev->dev_addr);
76ad4f0e 3135 }
139e8792
L		 3136
3137 if (h->ae_algo->ops->set_mac_addr)
3cbf5e2d 3138 h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3139
76ad4f0e
S		 3140}
3141
cbe8be06
JS		 3142static void hns3_uninit_mac_addr(struct net_device *netdev)
3143{
3144 struct hns3_nic_priv *priv = netdev_priv(netdev);
3145 struct hnae3_handle *h = priv->ae_handle;
3146
3147 if (h->ae_algo->ops->rm_uc_addr)
3148 h->ae_algo->ops->rm_uc_addr(h, netdev->dev_addr);
3149}
3150
76ad4f0e
S		 3151static void hns3_nic_set_priv_ops(struct net_device *netdev)
3152{
3153 struct hns3_nic_priv *priv = netdev_priv(netdev);
3154
3155 if ((netdev->features & NETIF_F_TSO) ||
3156 (netdev->features & NETIF_F_TSO6)) {
3157 priv->ops.fill_desc = hns3_fill_desc_tso;
3158 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
3159 } else {
3160 priv->ops.fill_desc = hns3_fill_desc;
3161 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
3162 }
3163}
3164
3165static int hns3_client_init(struct hnae3_handle *handle)
3166{
3167 struct pci_dev *pdev = handle->pdev;
3168 struct hns3_nic_priv *priv;
3169 struct net_device *netdev;
3170 int ret;
3171
3172 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv),
2d7187ce 3173 hns3_get_max_available_channels(handle));
76ad4f0e
S		 3174 if (!netdev)
3175 return -ENOMEM;
3176
3177 priv = netdev_priv(netdev);
3178 priv->dev = &pdev->dev;
3179 priv->netdev = netdev;
3180 priv->ae_handle = handle;
4aef908d 3181 priv->ae_handle->last_reset_time = jiffies;
f8fa222c 3182 priv->tx_timeout_count = 0;
76ad4f0e
S		 3183
3184 handle->kinfo.netdev = netdev;
3185 handle->priv = (void *)priv;
3186
edf76c8e 3187 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3188
3189 hns3_set_default_feature(netdev);
3190
3191 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3192 netdev->priv_flags |= IFF_UNICAST_FLT;
3193 netdev->netdev_ops = &hns3_nic_netdev_ops;
3194 SET_NETDEV_DEV(netdev, &pdev->dev);
3195 hns3_ethtool_set_ops(netdev);
3196 hns3_nic_set_priv_ops(netdev);
3197
3198 /* Carrier off reporting is important to ethtool even BEFORE open */
3199 netif_carrier_off(netdev);
3200
ca16933f
YL		 3201 if (handle->flags & HNAE3_SUPPORT_VF)
3202 handle->reset_level = HNAE3_VF_RESET;
3203 else
3204 handle->reset_level = HNAE3_FUNC_RESET;
3205
76ad4f0e
S		 3206 ret = hns3_get_ring_config(priv);
3207 if (ret) {
3208 ret = -ENOMEM;
3209 goto out_get_ring_cfg;
3210 }
3211
6cbd6d33
YL		 3212 ret = hns3_nic_alloc_vector_data(priv);
3213 if (ret) {
3214 ret = -ENOMEM;
3215 goto out_alloc_vector_data;
3216 }
3217
76ad4f0e
S		 3218 ret = hns3_nic_init_vector_data(priv);
3219 if (ret) {
3220 ret = -ENOMEM;
3221 goto out_init_vector_data;
3222 }
3223
3224 ret = hns3_init_all_ring(priv);
3225 if (ret) {
3226 ret = -ENOMEM;
3227 goto out_init_ring_data;
3228 }
3229
3230 ret = register_netdev(netdev);
3231 if (ret) {
3232 dev_err(priv->dev, "probe register netdev fail!\n");
3233 goto out_reg_netdev_fail;
3234 }
3235
986743db
YL		 3236 hns3_dcbnl_setup(handle);
3237
a8e8b7ff
S		 3238 /* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */
3239 netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
3240
76ad4f0e
S		 3241 return ret;
3242
3243out_reg_netdev_fail:
3244out_init_ring_data:
3245 (void)hns3_nic_uninit_vector_data(priv);
76ad4f0e 3246out_init_vector_data:
6cbd6d33
YL		 3247 hns3_nic_dealloc_vector_data(priv);
3248out_alloc_vector_data:
3249 priv->ring_data = NULL;
76ad4f0e
S		 3250out_get_ring_cfg:
3251 priv->ae_handle = NULL;
3252 free_netdev(netdev);
3253 return ret;
3254}
3255
3256static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3257{
3258 struct net_device *netdev = handle->kinfo.netdev;
3259 struct hns3_nic_priv *priv = netdev_priv(netdev);
3260 int ret;
3261
3262 if (netdev->reg_state != NETREG_UNINITIALIZED)
3263 unregister_netdev(netdev);
3264
e32a805a
FL		 3265 hns3_force_clear_all_rx_ring(handle);
3266
76ad4f0e
S		 3267 ret = hns3_nic_uninit_vector_data(priv);
3268 if (ret)
3269 netdev_err(netdev, "uninit vector error\n");
3270
6cbd6d33
YL		 3271 ret = hns3_nic_dealloc_vector_data(priv);
3272 if (ret)
3273 netdev_err(netdev, "dealloc vector error\n");
3274
76ad4f0e
S		 3275 ret = hns3_uninit_all_ring(priv);
3276 if (ret)
3277 netdev_err(netdev, "uninit ring error\n");
3278
a2ddee8c
YL		 3279 hns3_put_ring_config(priv);
3280
76ad4f0e
S		 3281 priv->ring_data = NULL;
3282
cbe8be06
JS		 3283 hns3_uninit_mac_addr(netdev);
3284
76ad4f0e
S		 3285 free_netdev(netdev);
3286}
3287
3288static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3289{
3290 struct net_device *netdev = handle->kinfo.netdev;
3291
3292 if (!netdev)
3293 return;
3294
3295 if (linkup) {
3296 netif_carrier_on(netdev);
3297 netif_tx_wake_all_queues(netdev);
3298 netdev_info(netdev, "link up\n");
3299 } else {
3300 netif_carrier_off(netdev);
3301 netif_tx_stop_all_queues(netdev);
3302 netdev_info(netdev, "link down\n");
3303 }
3304}
3305
9df8f79a
YL		 3306static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3307{
3308 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3309 struct net_device *ndev = kinfo->netdev;
075cfdd6 3310 bool if_running;
9df8f79a 3311 int ret;
9df8f79a
YL		 3312
3313 if (tc > HNAE3_MAX_TC)
3314 return -EINVAL;
3315
3316 if (!ndev)
3317 return -ENODEV;
3318
075cfdd6
CIK		 3319 if_running = netif_running(ndev);
3320
9df8f79a
YL		 3321 if (if_running) {
3322 (void)hns3_nic_net_stop(ndev);
3323 msleep(100);
3324 }
3325
3326 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ?
3327 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP;
3328 if (ret)
3329 goto err_out;
3330
9df8f79a
YL		 3331 ret = hns3_nic_set_real_num_queue(ndev);
3332
3333err_out:
3334 if (if_running)
3335 (void)hns3_nic_net_open(ndev);
3336
3337 return ret;
3338}
3339
bb6b94a8
L		 3340static void hns3_recover_hw_addr(struct net_device *ndev)
3341{
3342 struct netdev_hw_addr_list *list;
3343 struct netdev_hw_addr *ha, *tmp;
3344
3345 /* go through and sync uc_addr entries to the device */
3346 list = &ndev->uc;
3347 list_for_each_entry_safe(ha, tmp, &list->list, list)
3348 hns3_nic_uc_sync(ndev, ha->addr);
3349
3350 /* go through and sync mc_addr entries to the device */
3351 list = &ndev->mc;
3352 list_for_each_entry_safe(ha, tmp, &list->list, list)
3353 hns3_nic_mc_sync(ndev, ha->addr);
3354}
3355
82172ec9 3356static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 3357{
82172ec9 3358 while (ring->next_to_clean != ring->next_to_use) {
e32a805a 3359 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
82172ec9
YL		 3360 hns3_free_buffer_detach(ring, ring->next_to_clean);
3361 ring_ptr_move_fw(ring, next_to_clean);
3362 }
3363}
3364
e32a805a
FL		 3365static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3366{
3367 struct hns3_desc_cb res_cbs;
3368 int ret;
3369
3370 while (ring->next_to_use != ring->next_to_clean) {
3371 /* When a buffer is not reused, it's memory has been
3372 * freed in hns3_handle_rx_bd or will be freed by
3373 * stack, so we need to replace the buffer here.
3374 */
3375 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3376 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3377 if (ret) {
3378 u64_stats_update_begin(&ring->syncp);
3379 ring->stats.sw_err_cnt++;
3380 u64_stats_update_end(&ring->syncp);
3381 /* if alloc new buffer fail, exit directly
3382 * and reclear in up flow.
3383 */
3384 netdev_warn(ring->tqp->handle->kinfo.netdev,
3385 "reserve buffer map failed, ret = %d\n",
3386 ret);
3387 return ret;
3388 }
3389 hns3_replace_buffer(ring, ring->next_to_use,
3390 &res_cbs);
3391 }
3392 ring_ptr_move_fw(ring, next_to_use);
3393 }
3394
3395 return 0;
3396}
3397
3398static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
82172ec9 3399{
82172ec9
YL		 3400 while (ring->next_to_use != ring->next_to_clean) {
3401 /* When a buffer is not reused, it's memory has been
3402 * freed in hns3_handle_rx_bd or will be freed by
3403 * stack, so only need to unmap the buffer here.
3404 */
3405 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3406 hns3_unmap_buffer(ring,
3407 &ring->desc_cb[ring->next_to_use]);
3408 ring->desc_cb[ring->next_to_use].dma = 0;
3409 }
3410
3411 ring_ptr_move_fw(ring, next_to_use);
3412 }
bb6b94a8
L		 3413}
3414
e32a805a
FL		 3415static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3416{
3417 struct net_device *ndev = h->kinfo.netdev;
3418 struct hns3_nic_priv *priv = netdev_priv(ndev);
3419 struct hns3_enet_ring *ring;
3420 u32 i;
3421
3422 for (i = 0; i < h->kinfo.num_tqps; i++) {
3423 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3424 hns3_force_clear_rx_ring(ring);
3425 }
3426}
3427
bb6b94a8
L		 3428static void hns3_clear_all_ring(struct hnae3_handle *h)
3429{
3430 struct net_device *ndev = h->kinfo.netdev;
3431 struct hns3_nic_priv *priv = netdev_priv(ndev);
3432 u32 i;
3433
3434 for (i = 0; i < h->kinfo.num_tqps; i++) {
3435 struct netdev_queue *dev_queue;
3436 struct hns3_enet_ring *ring;
3437
3438 ring = priv->ring_data[i].ring;
82172ec9 3439 hns3_clear_tx_ring(ring);
bb6b94a8
L		 3440 dev_queue = netdev_get_tx_queue(ndev,
3441 priv->ring_data[i].queue_index);
3442 netdev_tx_reset_queue(dev_queue);
3443
3444 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
e32a805a
FL		 3445 /* Continue to clear other rings even if clearing some
3446 * rings failed.
3447 */
82172ec9 3448 hns3_clear_rx_ring(ring);
bb6b94a8
L		 3449 }
3450}
3451
e32a805a
FL		 3452int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3453{
3454 struct net_device *ndev = h->kinfo.netdev;
3455 struct hns3_nic_priv *priv = netdev_priv(ndev);
3456 struct hns3_enet_ring *rx_ring;
3457 int i, j;
3458 int ret;
3459
3460 for (i = 0; i < h->kinfo.num_tqps; i++) {
3461 h->ae_algo->ops->reset_queue(h, i);
3462 hns3_init_ring_hw(priv->ring_data[i].ring);
3463
3464 /* We need to clear tx ring here because self test will
3465 * use the ring and will not run down before up
3466 */
3467 hns3_clear_tx_ring(priv->ring_data[i].ring);
3468 priv->ring_data[i].ring->next_to_clean = 0;
3469 priv->ring_data[i].ring->next_to_use = 0;
3470
3471 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3472 hns3_init_ring_hw(rx_ring);
3473 ret = hns3_clear_rx_ring(rx_ring);
3474 if (ret)
3475 return ret;
3476
3477 /* We can not know the hardware head and tail when this
3478 * function is called in reset flow, so we reuse all desc.
3479 */
3480 for (j = 0; j < rx_ring->desc_num; j++)
3481 hns3_reuse_buffer(rx_ring, j);
3482
3483 rx_ring->next_to_clean = 0;
3484 rx_ring->next_to_use = 0;
3485 }
3486
fe46c859
YL		 3487 hns3_init_tx_ring_tc(priv);
3488
e32a805a
FL		 3489 return 0;
3490}
3491
bb6b94a8
L		 3492static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
3493{
3494 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3495 struct net_device *ndev = kinfo->netdev;
3496
3497 if (!netif_running(ndev))
196b8760 3498 return 0;
bb6b94a8
L		 3499
3500 return hns3_nic_net_stop(ndev);
3501}
3502
3503static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
3504{
3505 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
bb6b94a8
L		 3506 int ret = 0;
3507
3508 if (netif_running(kinfo->netdev)) {
3509 ret = hns3_nic_net_up(kinfo->netdev);
3510 if (ret) {
3511 netdev_err(kinfo->netdev,
3512 "hns net up fail, ret=%d!\n", ret);
3513 return ret;
3514 }
4aef908d 3515 handle->last_reset_time = jiffies;
bb6b94a8
L		 3516 }
3517
3518 return ret;
3519}
3520
3521static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
3522{
3523 struct net_device *netdev = handle->kinfo.netdev;
3524 struct hns3_nic_priv *priv = netdev_priv(netdev);
3525 int ret;
3526
edf76c8e 3527 hns3_init_mac_addr(netdev, false);
bb6b94a8
L		 3528 hns3_nic_set_rx_mode(netdev);
3529 hns3_recover_hw_addr(netdev);
3530
103ce052
YL		 3531 /* Hardware table is only clear when pf resets */
3532 if (!(handle->flags & HNAE3_SUPPORT_VF))
3533 hns3_restore_vlan(netdev);
3534
bb6b94a8
L		 3535 /* Carrier off reporting is important to ethtool even BEFORE open */
3536 netif_carrier_off(netdev);
3537
bb6b94a8
L		 3538 ret = hns3_nic_init_vector_data(priv);
3539 if (ret)
3540 return ret;
3541
3542 ret = hns3_init_all_ring(priv);
3543 if (ret) {
3544 hns3_nic_uninit_vector_data(priv);
3545 priv->ring_data = NULL;
3546 }
3547
3548 return ret;
3549}
3550
3551static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
3552{
3553 struct net_device *netdev = handle->kinfo.netdev;
3554 struct hns3_nic_priv *priv = netdev_priv(netdev);
3555 int ret;
3556
e32a805a 3557 hns3_force_clear_all_rx_ring(handle);
bb6b94a8
L		 3558
3559 ret = hns3_nic_uninit_vector_data(priv);
3560 if (ret) {
3561 netdev_err(netdev, "uninit vector error\n");
3562 return ret;
3563 }
3564
3565 ret = hns3_uninit_all_ring(priv);
3566 if (ret)
3567 netdev_err(netdev, "uninit ring error\n");
3568
cbe8be06
JS		 3569 hns3_uninit_mac_addr(netdev);
3570
bb6b94a8
L		 3571 return ret;
3572}
3573
3574static int hns3_reset_notify(struct hnae3_handle *handle,
3575 enum hnae3_reset_notify_type type)
3576{
3577 int ret = 0;
3578
3579 switch (type) {
3580 case HNAE3_UP_CLIENT:
741e1778
SM		 3581 ret = hns3_reset_notify_up_enet(handle);
3582 break;
bb6b94a8
L		 3583 case HNAE3_DOWN_CLIENT:
3584 ret = hns3_reset_notify_down_enet(handle);
3585 break;
3586 case HNAE3_INIT_CLIENT:
3587 ret = hns3_reset_notify_init_enet(handle);
3588 break;
3589 case HNAE3_UNINIT_CLIENT:
3590 ret = hns3_reset_notify_uninit_enet(handle);
3591 break;
3592 default:
3593 break;
3594 }
3595
3596 return ret;
3597}
3598
351dad5e
YL		 3599static void hns3_restore_coal(struct hns3_nic_priv *priv,
3600 struct hns3_enet_coalesce *tx,
3601 struct hns3_enet_coalesce *rx)
3602{
3603 u16 vector_num = priv->vector_num;
3604 int i;
3605
3606 for (i = 0; i < vector_num; i++) {
3607 memcpy(&priv->tqp_vector[i].tx_group.coal, tx,
3608 sizeof(struct hns3_enet_coalesce));
3609 memcpy(&priv->tqp_vector[i].rx_group.coal, rx,
3610 sizeof(struct hns3_enet_coalesce));
3611 }
3612}
3613
3614static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num,
3615 struct hns3_enet_coalesce *tx,
3616 struct hns3_enet_coalesce *rx)
f1f779ce
PL		 3617{
3618 struct hns3_nic_priv *priv = netdev_priv(netdev);
3619 struct hnae3_handle *h = hns3_get_handle(netdev);
3620 int ret;
3621
3622 ret = h->ae_algo->ops->set_channels(h, new_tqp_num);
3623 if (ret)
3624 return ret;
3625
3626 ret = hns3_get_ring_config(priv);
3627 if (ret)
3628 return ret;
3629
6cbd6d33
YL		 3630 ret = hns3_nic_alloc_vector_data(priv);
3631 if (ret)
3632 goto err_alloc_vector;
3633
351dad5e
YL		 3634 hns3_restore_coal(priv, tx, rx);
3635
f1f779ce
PL		 3636 ret = hns3_nic_init_vector_data(priv);
3637 if (ret)
3638 goto err_uninit_vector;
3639
3640 ret = hns3_init_all_ring(priv);
3641 if (ret)
3642 goto err_put_ring;
3643
3644 return 0;
3645
3646err_put_ring:
3647 hns3_put_ring_config(priv);
3648err_uninit_vector:
3649 hns3_nic_uninit_vector_data(priv);
6cbd6d33
YL		 3650err_alloc_vector:
3651 hns3_nic_dealloc_vector_data(priv);
f1f779ce
PL		 3652 return ret;
3653}
3654
3655static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num)
3656{
3657 return (new_tqp_num / num_tc) * num_tc;
3658}
3659
3660int hns3_set_channels(struct net_device *netdev,
3661 struct ethtool_channels *ch)
3662{
3663 struct hns3_nic_priv *priv = netdev_priv(netdev);
3664 struct hnae3_handle *h = hns3_get_handle(netdev);
3665 struct hnae3_knic_private_info *kinfo = &h->kinfo;
351dad5e 3666 struct hns3_enet_coalesce tx_coal, rx_coal;
f1f779ce
PL		 3667 bool if_running = netif_running(netdev);
3668 u32 new_tqp_num = ch->combined_count;
3669 u16 org_tqp_num;
3670 int ret;
3671
3672 if (ch->rx_count || ch->tx_count)
3673 return -EINVAL;
3674
2d7187ce 3675 if (new_tqp_num > hns3_get_max_available_channels(h) ||
f1f779ce
PL		 3676 new_tqp_num < kinfo->num_tc) {
3677 dev_err(&netdev->dev,
3678 "Change tqps fail, the tqp range is from %d to %d",
3679 kinfo->num_tc,
2d7187ce 3680 hns3_get_max_available_channels(h));
f1f779ce
PL		 3681 return -EINVAL;
3682 }
3683
3684 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num);
3685 if (kinfo->num_tqps == new_tqp_num)
3686 return 0;
3687
3688 if (if_running)
41efd6b1 3689 hns3_nic_net_stop(netdev);
f1f779ce 3690
f1f779ce
PL		 3691 ret = hns3_nic_uninit_vector_data(priv);
3692 if (ret) {
3693 dev_err(&netdev->dev,
3694 "Unbind vector with tqp fail, nothing is changed");
3695 goto open_netdev;
3696 }
3697
351dad5e
YL		 3698 /* Changing the tqp num may also change the vector num,
3699 * ethtool only support setting and querying one coal
3700 * configuation for now, so save the vector 0' coal
3701 * configuation here in order to restore it.
3702 */
3703 memcpy(&tx_coal, &priv->tqp_vector[0].tx_group.coal,
3704 sizeof(struct hns3_enet_coalesce));
3705 memcpy(&rx_coal, &priv->tqp_vector[0].rx_group.coal,
3706 sizeof(struct hns3_enet_coalesce));
3707
6cbd6d33
YL		 3708 hns3_nic_dealloc_vector_data(priv);
3709
f1f779ce 3710 hns3_uninit_all_ring(priv);
a2ddee8c 3711 hns3_put_ring_config(priv);
f1f779ce
PL		 3712
3713 org_tqp_num = h->kinfo.num_tqps;
351dad5e 3714 ret = hns3_modify_tqp_num(netdev, new_tqp_num, &tx_coal, &rx_coal);
f1f779ce 3715 if (ret) {
351dad5e
YL		 3716 ret = hns3_modify_tqp_num(netdev, org_tqp_num,
3717 &tx_coal, &rx_coal);
f1f779ce
PL		 3718 if (ret) {
3719 /* If revert to old tqp failed, fatal error occurred */
3720 dev_err(&netdev->dev,
3721 "Revert to old tqp num fail, ret=%d", ret);
3722 return ret;
3723 }
3724 dev_info(&netdev->dev,
3725 "Change tqp num fail, Revert to old tqp num");
3726 }
3727
3728open_netdev:
3729 if (if_running)
41efd6b1 3730 hns3_nic_net_open(netdev);
f1f779ce
PL		 3731
3732 return ret;
3733}
3734
1db9b1bf 3735static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 3736 .init_instance = hns3_client_init,
3737 .uninit_instance = hns3_client_uninit,
3738 .link_status_change = hns3_link_status_change,
9df8f79a 3739 .setup_tc = hns3_client_setup_tc,
bb6b94a8 3740 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 3741};
3742
3743/* hns3_init_module - Driver registration routine
3744 * hns3_init_module is the first routine called when the driver is
3745 * loaded. All it does is register with the PCI subsystem.
3746 */
3747static int __init hns3_init_module(void)
3748{
3749 int ret;
3750
3751 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
3752 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
3753
3754 client.type = HNAE3_CLIENT_KNIC;
3755 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
3756 hns3_driver_name);
3757
3758 client.ops = &client_ops;
3759
dadc9935
XW		 3760 INIT_LIST_HEAD(&client.node);
3761
76ad4f0e
S		 3762 ret = hnae3_register_client(&client);
3763 if (ret)
3764 return ret;
3765
3766 ret = pci_register_driver(&hns3_driver);
3767 if (ret)
3768 hnae3_unregister_client(&client);
3769
3770 return ret;
3771}
3772module_init(hns3_init_module);
3773
3774/* hns3_exit_module - Driver exit cleanup routine
3775 * hns3_exit_module is called just before the driver is removed
3776 * from memory.
3777 */
3778static void __exit hns3_exit_module(void)
3779{
3780 pci_unregister_driver(&hns3_driver);
3781 hnae3_unregister_client(&client);
3782}
3783module_exit(hns3_exit_module);
3784
3785MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
3786MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3787MODULE_LICENSE("GPL");
3788MODULE_ALIAS("pci:hns-nic");
4786ad87 3789MODULE_VERSION(HNS3_MOD_VERSION);
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