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UBUNTU: Ubuntu-5.3.0-29.31
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e
S		 3
4#include <linux/dma-mapping.h>
5#include <linux/etherdevice.h>
6#include <linux/interrupt.h>
ffab9691
JS		 7#ifdef CONFIG_RFS_ACCEL
8#include <linux/cpu_rmap.h>
9#endif
76ad4f0e
S		 10#include <linux/if_vlan.h>
11#include <linux/ip.h>
12#include <linux/ipv6.h>
13#include <linux/module.h>
14#include <linux/pci.h>
6ae4e733 15#include <linux/aer.h>
76ad4f0e
S		 16#include <linux/skbuff.h>
17#include <linux/sctp.h>
18#include <linux/vermagic.h>
19#include <net/gre.h>
e2ee1c5a 20#include <net/ip6_checksum.h>
30d240df 21#include <net/pkt_cls.h>
a6d53b97 22#include <net/tcp.h>
76ad4f0e
S		 23#include <net/vxlan.h>
24
25#include "hnae3.h"
26#include "hns3_enet.h"
27
cde4ffad 28#define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
5f543a54 29#define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
cde4ffad 30
f96315f2 31static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
f05e2109 32static void hns3_remove_hw_addr(struct net_device *netdev);
7b763f3f 33
1db9b1bf 34static const char hns3_driver_name[] = "hns3";
76ad4f0e
S		 35const char hns3_driver_version[] = VERMAGIC_STRING;
36static const char hns3_driver_string[] =
37 "Hisilicon Ethernet Network Driver for Hip08 Family";
38static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
39static struct hnae3_client client;
40
bb87be87
YL		 41static int debug = -1;
42module_param(debug, int, 0);
43MODULE_PARM_DESC(debug, " Network interface message level setting");
44
45#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
46 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
47
76ad4f0e
S		 48/* hns3_pci_tbl - PCI Device ID Table
49 *
50 * Last entry must be all 0s
51 *
52 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
53 * Class, Class Mask, private data (not used) }
54 */
55static const struct pci_device_id hns3_pci_tbl[] = {
56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
57 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
e92a0843 58 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
2daf4a65 59 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 60 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
2daf4a65 61 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 62 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
2daf4a65 63 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 64 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
2daf4a65 65 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
e92a0843 66 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
2daf4a65 67 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
424eb834 68 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
07acf909
JS		 69 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
70 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76ad4f0e
S		 71 /* required last entry */
72 {0, }
73};
74MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
75
ef0c5009 76static irqreturn_t hns3_irq_handle(int irq, void *vector)
76ad4f0e 77{
ef0c5009 78 struct hns3_enet_tqp_vector *tqp_vector = vector;
76ad4f0e 79
fb00331b 80 napi_schedule_irqoff(&tqp_vector->napi);
76ad4f0e
S		 81
82 return IRQ_HANDLED;
83}
84
85static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
86{
87 struct hns3_enet_tqp_vector *tqp_vectors;
88 unsigned int i;
89
90 for (i = 0; i < priv->vector_num; i++) {
91 tqp_vectors = &priv->tqp_vector[i];
92
93 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
94 continue;
95
ffab9691 96 /* clear the affinity mask */
874bff0b
PL		 97 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
98
76ad4f0e
S		 99 /* release the irq resource */
100 free_irq(tqp_vectors->vector_irq, tqp_vectors);
101 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
102 }
103}
104
105static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
106{
107 struct hns3_enet_tqp_vector *tqp_vectors;
108 int txrx_int_idx = 0;
109 int rx_int_idx = 0;
110 int tx_int_idx = 0;
111 unsigned int i;
112 int ret;
113
114 for (i = 0; i < priv->vector_num; i++) {
115 tqp_vectors = &priv->tqp_vector[i];
116
117 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
118 continue;
119
120 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
121 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
122 "%s-%s-%d", priv->netdev->name, "TxRx",
123 txrx_int_idx++);
124 txrx_int_idx++;
125 } else if (tqp_vectors->rx_group.ring) {
126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
127 "%s-%s-%d", priv->netdev->name, "Rx",
128 rx_int_idx++);
129 } else if (tqp_vectors->tx_group.ring) {
130 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
131 "%s-%s-%d", priv->netdev->name, "Tx",
132 tx_int_idx++);
133 } else {
134 /* Skip this unused q_vector */
135 continue;
136 }
137
138 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
139
140 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
9b2f3477 141 tqp_vectors->name, tqp_vectors);
76ad4f0e
S		 142 if (ret) {
143 netdev_err(priv->netdev, "request irq(%d) fail\n",
144 tqp_vectors->vector_irq);
d547ecdc 145 hns3_nic_uninit_irq(priv);
76ad4f0e
S		 146 return ret;
147 }
148
874bff0b
PL		 149 irq_set_affinity_hint(tqp_vectors->vector_irq,
150 &tqp_vectors->affinity_mask);
151
76ad4f0e
S		 152 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
153 }
154
155 return 0;
156}
157
158static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
159 u32 mask_en)
160{
161 writel(mask_en, tqp_vector->mask_addr);
162}
163
164static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
165{
166 napi_enable(&tqp_vector->napi);
167
168 /* enable vector */
169 hns3_mask_vector_irq(tqp_vector, 1);
170}
171
172static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
173{
174 /* disable vector */
175 hns3_mask_vector_irq(tqp_vector, 0);
176
177 disable_irq(tqp_vector->vector_irq);
178 napi_disable(&tqp_vector->napi);
179}
180
434776a5
FL		 181void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
182 u32 rl_value)
76ad4f0e 183{
434776a5
FL		 184 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
185
76ad4f0e
S		 186 /* this defines the configuration for RL (Interrupt Rate Limiter).
187 * Rl defines rate of interrupts i.e. number of interrupts-per-second
188 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
189 */
434776a5 190
9bc727a9
YL		 191 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
192 !tqp_vector->rx_group.coal.gl_adapt_enable)
434776a5
FL		 193 /* According to the hardware, the range of rl_reg is
194 * 0-59 and the unit is 4.
195 */
196 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
197
198 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
199}
200
201void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
202 u32 gl_value)
203{
204 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
205
206 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
207}
208
209void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
210 u32 gl_value)
211{
212 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
213
214 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
76ad4f0e
S		 215}
216
5fd4789a
FL		 217static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
218 struct hns3_nic_priv *priv)
76ad4f0e
S		 219{
220 /* initialize the configuration for interrupt coalescing.
221 * 1. GL (Interrupt Gap Limiter)
222 * 2. RL (Interrupt Rate Limiter)
223 */
224
5fd4789a 225 /* Default: enable interrupt coalescing self-adaptive and GL */
9bc727a9
YL		 226 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
227 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
5fd4789a 228
9bc727a9
YL		 229 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
230 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
5fd4789a 231
9bc727a9
YL		 232 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
233 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
76ad4f0e
S		 234}
235
dd38c726
YL		 236static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
237 struct hns3_nic_priv *priv)
238{
239 struct hnae3_handle *h = priv->ae_handle;
240
241 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 242 tqp_vector->tx_group.coal.int_gl);
dd38c726 243 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 244 tqp_vector->rx_group.coal.int_gl);
dd38c726
YL		 245 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
246}
247
9df8f79a
YL		 248static int hns3_nic_set_real_num_queue(struct net_device *netdev)
249{
9780cb97 250 struct hnae3_handle *h = hns3_get_handle(netdev);
9df8f79a
YL		 251 struct hnae3_knic_private_info *kinfo = &h->kinfo;
252 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
a75a8efa
YL		 253 int i, ret;
254
255 if (kinfo->num_tc <= 1) {
256 netdev_reset_tc(netdev);
257 } else {
258 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
259 if (ret) {
260 netdev_err(netdev,
261 "netdev_set_num_tc fail, ret=%d!\n", ret);
262 return ret;
263 }
264
265 for (i = 0; i < HNAE3_MAX_TC; i++) {
266 if (!kinfo->tc_info[i].enable)
267 continue;
268
269 netdev_set_tc_queue(netdev,
270 kinfo->tc_info[i].tc,
271 kinfo->tc_info[i].tqp_count,
272 kinfo->tc_info[i].tqp_offset);
273 }
274 }
9df8f79a
YL		 275
276 ret = netif_set_real_num_tx_queues(netdev, queue_size);
277 if (ret) {
278 netdev_err(netdev,
9b2f3477 279 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
9df8f79a
YL		 280 return ret;
281 }
282
283 ret = netif_set_real_num_rx_queues(netdev, queue_size);
284 if (ret) {
285 netdev_err(netdev,
286 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
287 return ret;
288 }
289
290 return 0;
291}
292
678335a1
PL		 293static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
294{
0d43bf45 295 u16 alloc_tqps, max_rss_size, rss_size;
678335a1 296
0d43bf45
HT		 297 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
298 rss_size = alloc_tqps / h->kinfo.num_tc;
678335a1 299
0d43bf45 300 return min_t(u16, rss_size, max_rss_size);
678335a1
PL		 301}
302
8df0fa91
HT		 303static void hns3_tqp_enable(struct hnae3_queue *tqp)
304{
305 u32 rcb_reg;
306
307 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
308 rcb_reg |= BIT(HNS3_RING_EN_B);
309 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
310}
311
312static void hns3_tqp_disable(struct hnae3_queue *tqp)
313{
314 u32 rcb_reg;
315
316 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
317 rcb_reg &= ~BIT(HNS3_RING_EN_B);
318 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
319}
320
ffab9691
JS		 321static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
322{
323#ifdef CONFIG_RFS_ACCEL
324 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
325 netdev->rx_cpu_rmap = NULL;
326#endif
327}
328
329static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
330{
331#ifdef CONFIG_RFS_ACCEL
332 struct hns3_nic_priv *priv = netdev_priv(netdev);
333 struct hns3_enet_tqp_vector *tqp_vector;
334 int i, ret;
335
336 if (!netdev->rx_cpu_rmap) {
337 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
338 if (!netdev->rx_cpu_rmap)
339 return -ENOMEM;
340 }
341
342 for (i = 0; i < priv->vector_num; i++) {
343 tqp_vector = &priv->tqp_vector[i];
344 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
345 tqp_vector->vector_irq);
346 if (ret) {
347 hns3_free_rx_cpu_rmap(netdev);
348 return ret;
349 }
350 }
351#endif
352 return 0;
353}
354
76ad4f0e
S		 355static int hns3_nic_net_up(struct net_device *netdev)
356{
357 struct hns3_nic_priv *priv = netdev_priv(netdev);
358 struct hnae3_handle *h = priv->ae_handle;
359 int i, j;
360 int ret;
361
7b763f3f
FL		 362 ret = hns3_nic_reset_all_ring(h);
363 if (ret)
364 return ret;
365
ffab9691
JS		 366 /* the device can work without cpu rmap, only aRFS needs it */
367 ret = hns3_set_rx_cpu_rmap(netdev);
368 if (ret)
369 netdev_warn(netdev, "set rx cpu rmap fail, ret=%d!\n", ret);
370
76ad4f0e
S		 371 /* get irq resource for all vectors */
372 ret = hns3_nic_init_irq(priv);
373 if (ret) {
9b2f3477 374 netdev_err(netdev, "init irq failed! ret=%d\n", ret);
ffab9691 375 goto free_rmap;
76ad4f0e
S		 376 }
377
b7b585c2
JS		 378 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
379
76ad4f0e
S		 380 /* enable the vectors */
381 for (i = 0; i < priv->vector_num; i++)
382 hns3_vector_enable(&priv->tqp_vector[i]);
383
8df0fa91
HT		 384 /* enable rcb */
385 for (j = 0; j < h->kinfo.num_tqps; j++)
386 hns3_tqp_enable(h->kinfo.tqp[j]);
387
76ad4f0e
S		 388 /* start the ae_dev */
389 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
390 if (ret)
391 goto out_start_err;
392
393 return 0;
394
395out_start_err:
b7b585c2 396 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
8df0fa91
HT		 397 while (j--)
398 hns3_tqp_disable(h->kinfo.tqp[j]);
399
76ad4f0e
S		 400 for (j = i - 1; j >= 0; j--)
401 hns3_vector_disable(&priv->tqp_vector[j]);
402
403 hns3_nic_uninit_irq(priv);
ffab9691
JS		 404free_rmap:
405 hns3_free_rx_cpu_rmap(netdev);
76ad4f0e
S		 406 return ret;
407}
408
2a73ac3e
YL		 409static void hns3_config_xps(struct hns3_nic_priv *priv)
410{
411 int i;
412
413 for (i = 0; i < priv->vector_num; i++) {
414 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
415 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
416
417 while (ring) {
418 int ret;
419
420 ret = netif_set_xps_queue(priv->netdev,
421 &tqp_vector->affinity_mask,
422 ring->tqp->tqp_index);
423 if (ret)
424 netdev_warn(priv->netdev,
425 "set xps queue failed: %d", ret);
426
427 ring = ring->next;
428 }
429 }
430}
431
76ad4f0e
S		 432static int hns3_nic_net_open(struct net_device *netdev)
433{
8cdb992f 434 struct hns3_nic_priv *priv = netdev_priv(netdev);
a75a8efa
YL		 435 struct hnae3_handle *h = hns3_get_handle(netdev);
436 struct hnae3_knic_private_info *kinfo;
437 int i, ret;
76ad4f0e 438
257e4f29
HT		 439 if (hns3_nic_resetting(netdev))
440 return -EBUSY;
441
76ad4f0e
S		 442 netif_carrier_off(netdev);
443
9df8f79a
YL		 444 ret = hns3_nic_set_real_num_queue(netdev);
445 if (ret)
76ad4f0e 446 return ret;
76ad4f0e
S		 447
448 ret = hns3_nic_net_up(netdev);
449 if (ret) {
9b2f3477 450 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
76ad4f0e
S		 451 return ret;
452 }
453
a75a8efa 454 kinfo = &h->kinfo;
9b2f3477
WL		 455 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
456 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
a75a8efa 457
8cdb992f
JS		 458 if (h->ae_algo->ops->set_timer_task)
459 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
460
2a73ac3e 461 hns3_config_xps(priv);
76ad4f0e
S		 462 return 0;
463}
464
f96315f2
HT		 465static void hns3_reset_tx_queue(struct hnae3_handle *h)
466{
467 struct net_device *ndev = h->kinfo.netdev;
468 struct hns3_nic_priv *priv = netdev_priv(ndev);
469 struct netdev_queue *dev_queue;
470 u32 i;
471
472 for (i = 0; i < h->kinfo.num_tqps; i++) {
473 dev_queue = netdev_get_tx_queue(ndev,
474 priv->ring_data[i].queue_index);
475 netdev_tx_reset_queue(dev_queue);
476 }
477}
478
76ad4f0e
S		 479static void hns3_nic_net_down(struct net_device *netdev)
480{
481 struct hns3_nic_priv *priv = netdev_priv(netdev);
8df0fa91 482 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 483 const struct hnae3_ae_ops *ops;
484 int i;
485
7b763f3f
FL		 486 /* disable vectors */
487 for (i = 0; i < priv->vector_num; i++)
488 hns3_vector_disable(&priv->tqp_vector[i]);
8df0fa91
HT		 489
490 /* disable rcb */
491 for (i = 0; i < h->kinfo.num_tqps; i++)
492 hns3_tqp_disable(h->kinfo.tqp[i]);
7b763f3f 493
76ad4f0e
S		 494 /* stop ae_dev */
495 ops = priv->ae_handle->ae_algo->ops;
496 if (ops->stop)
497 ops->stop(priv->ae_handle);
498
ffab9691
JS		 499 hns3_free_rx_cpu_rmap(netdev);
500
76ad4f0e
S		 501 /* free irq resources */
502 hns3_nic_uninit_irq(priv);
7b763f3f 503
3a30964a
YL		 504 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
505 * during reset process, because driver may not be able
506 * to disable the ring through firmware when downing the netdev.
507 */
508 if (!hns3_nic_resetting(netdev))
f96315f2
HT		 509 hns3_clear_all_ring(priv->ae_handle, false);
510
511 hns3_reset_tx_queue(priv->ae_handle);
76ad4f0e
S		 512}
513
514static int hns3_nic_net_stop(struct net_device *netdev)
515{
ff0699e0 516 struct hns3_nic_priv *priv = netdev_priv(netdev);
8cdb992f 517 struct hnae3_handle *h = hns3_get_handle(netdev);
ff0699e0
HT		 518
519 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
520 return 0;
521
8cdb992f
JS		 522 if (h->ae_algo->ops->set_timer_task)
523 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
524
76ad4f0e
S		 525 netif_tx_stop_all_queues(netdev);
526 netif_carrier_off(netdev);
527
528 hns3_nic_net_down(netdev);
529
530 return 0;
531}
532
76ad4f0e
S		 533static int hns3_nic_uc_sync(struct net_device *netdev,
534 const unsigned char *addr)
535{
9780cb97 536 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 537
538 if (h->ae_algo->ops->add_uc_addr)
539 return h->ae_algo->ops->add_uc_addr(h, addr);
540
541 return 0;
542}
543
544static int hns3_nic_uc_unsync(struct net_device *netdev,
545 const unsigned char *addr)
546{
9780cb97 547 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 548
549 if (h->ae_algo->ops->rm_uc_addr)
550 return h->ae_algo->ops->rm_uc_addr(h, addr);
551
552 return 0;
553}
554
555static int hns3_nic_mc_sync(struct net_device *netdev,
556 const unsigned char *addr)
557{
9780cb97 558 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 559
720a8478 560 if (h->ae_algo->ops->add_mc_addr)
76ad4f0e
S		 561 return h->ae_algo->ops->add_mc_addr(h, addr);
562
563 return 0;
564}
565
566static int hns3_nic_mc_unsync(struct net_device *netdev,
567 const unsigned char *addr)
568{
9780cb97 569 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e 570
720a8478 571 if (h->ae_algo->ops->rm_mc_addr)
76ad4f0e
S		 572 return h->ae_algo->ops->rm_mc_addr(h, addr);
573
574 return 0;
575}
576
c60edc17
JS		 577static u8 hns3_get_netdev_flags(struct net_device *netdev)
578{
579 u8 flags = 0;
580
581 if (netdev->flags & IFF_PROMISC) {
28673b33 582 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
c60edc17
JS		 583 } else {
584 flags |= HNAE3_VLAN_FLTR;
585 if (netdev->flags & IFF_ALLMULTI)
586 flags |= HNAE3_USER_MPE;
587 }
588
589 return flags;
590}
591
1db9b1bf 592static void hns3_nic_set_rx_mode(struct net_device *netdev)
76ad4f0e 593{
9780cb97 594 struct hnae3_handle *h = hns3_get_handle(netdev);
c60edc17
JS		 595 u8 new_flags;
596 int ret;
76ad4f0e 597
c60edc17
JS		 598 new_flags = hns3_get_netdev_flags(netdev);
599
600 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
601 if (ret) {
76ad4f0e 602 netdev_err(netdev, "sync uc address fail\n");
c60edc17
JS		 603 if (ret == -ENOSPC)
604 new_flags |= HNAE3_OVERFLOW_UPE;
605 }
606
40cca1c5 607 if (netdev->flags & IFF_MULTICAST) {
c60edc17
JS		 608 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
609 hns3_nic_mc_unsync);
610 if (ret) {
76ad4f0e 611 netdev_err(netdev, "sync mc address fail\n");
c60edc17
JS		 612 if (ret == -ENOSPC)
613 new_flags |= HNAE3_OVERFLOW_MPE;
614 }
615 }
616
c60edc17
JS		 617 /* User mode Promisc mode enable and vlan filtering is disabled to
618 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
619 * vlan fitering is enabled
620 */
621 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
622 h->netdev_flags = new_flags;
28673b33 623 hns3_update_promisc_mode(netdev, new_flags);
c60edc17
JS		 624}
625
7fa6be4f 626int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
c60edc17
JS		 627{
628 struct hns3_nic_priv *priv = netdev_priv(netdev);
629 struct hnae3_handle *h = priv->ae_handle;
630
631 if (h->ae_algo->ops->set_promisc_mode) {
7fa6be4f
HT		 632 return h->ae_algo->ops->set_promisc_mode(h,
633 promisc_flags & HNAE3_UPE,
634 promisc_flags & HNAE3_MPE);
c60edc17 635 }
7fa6be4f
HT		 636
637 return 0;
c60edc17
JS		 638}
639
640void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
641{
642 struct hns3_nic_priv *priv = netdev_priv(netdev);
643 struct hnae3_handle *h = priv->ae_handle;
644 bool last_state;
645
646 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
647 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
648 if (enable != last_state) {
649 netdev_info(netdev,
650 "%s vlan filter\n",
651 enable ? "enable" : "disable");
652 h->ae_algo->ops->enable_vlan_filter(h, enable);
653 }
40cca1c5 654 }
76ad4f0e
S		 655}
656
657static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
658 u16 *mss, u32 *type_cs_vlan_tso)
659{
660 u32 l4_offset, hdr_len;
661 union l3_hdr_info l3;
662 union l4_hdr_info l4;
663 u32 l4_paylen;
664 int ret;
665
666 if (!skb_is_gso(skb))
667 return 0;
668
669 ret = skb_cow_head(skb, 0);
0cccebac 670 if (unlikely(ret))
76ad4f0e
S		 671 return ret;
672
673 l3.hdr = skb_network_header(skb);
674 l4.hdr = skb_transport_header(skb);
675
676 /* Software should clear the IPv4's checksum field when tso is
677 * needed.
678 */
679 if (l3.v4->version == 4)
680 l3.v4->check = 0;
681
9b2f3477 682 /* tunnel packet */
76ad4f0e
S		 683 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
684 SKB_GSO_GRE_CSUM |
685 SKB_GSO_UDP_TUNNEL |
686 SKB_GSO_UDP_TUNNEL_CSUM)) {
687 if ((!(skb_shinfo(skb)->gso_type &
688 SKB_GSO_PARTIAL)) &&
689 (skb_shinfo(skb)->gso_type &
690 SKB_GSO_UDP_TUNNEL_CSUM)) {
691 /* Software should clear the udp's checksum
692 * field when tso is needed.
693 */
694 l4.udp->check = 0;
695 }
696 /* reset l3&l4 pointers from outer to inner headers */
697 l3.hdr = skb_inner_network_header(skb);
698 l4.hdr = skb_inner_transport_header(skb);
699
700 /* Software should clear the IPv4's checksum field when
701 * tso is needed.
702 */
703 if (l3.v4->version == 4)
704 l3.v4->check = 0;
705 }
706
9b2f3477 707 /* normal or tunnel packet */
76ad4f0e 708 l4_offset = l4.hdr - skb->data;
3fe13ed9 709 hdr_len = (l4.tcp->doff << 2) + l4_offset;
76ad4f0e 710
9b2f3477 711 /* remove payload length from inner pseudo checksum when tso */
76ad4f0e
S		 712 l4_paylen = skb->len - l4_offset;
713 csum_replace_by_diff(&l4.tcp->check,
714 (__force __wsum)htonl(l4_paylen));
715
716 /* find the txbd field values */
717 *paylen = skb->len - hdr_len;
cde4ffad 718 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
76ad4f0e
S		 719
720 /* get MSS for TSO */
721 *mss = skb_shinfo(skb)->gso_size;
722
723 return 0;
724}
725
1898d4e4
S		 726static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
727 u8 *il4_proto)
76ad4f0e 728{
1a6e552d 729 union l3_hdr_info l3;
76ad4f0e
S		 730 unsigned char *l4_hdr;
731 unsigned char *exthdr;
732 u8 l4_proto_tmp;
733 __be16 frag_off;
734
735 /* find outer header point */
736 l3.hdr = skb_network_header(skb);
35f58fd7 737 l4_hdr = skb_transport_header(skb);
76ad4f0e
S		 738
739 if (skb->protocol == htons(ETH_P_IPV6)) {
740 exthdr = l3.hdr + sizeof(*l3.v6);
741 l4_proto_tmp = l3.v6->nexthdr;
742 if (l4_hdr != exthdr)
743 ipv6_skip_exthdr(skb, exthdr - skb->data,
744 &l4_proto_tmp, &frag_off);
745 } else if (skb->protocol == htons(ETH_P_IP)) {
746 l4_proto_tmp = l3.v4->protocol;
1898d4e4
S		 747 } else {
748 return -EINVAL;
76ad4f0e
S		 749 }
750
751 *ol4_proto = l4_proto_tmp;
752
753 /* tunnel packet */
754 if (!skb->encapsulation) {
755 *il4_proto = 0;
1898d4e4 756 return 0;
76ad4f0e
S		 757 }
758
759 /* find inner header point */
760 l3.hdr = skb_inner_network_header(skb);
761 l4_hdr = skb_inner_transport_header(skb);
762
763 if (l3.v6->version == 6) {
764 exthdr = l3.hdr + sizeof(*l3.v6);
765 l4_proto_tmp = l3.v6->nexthdr;
766 if (l4_hdr != exthdr)
767 ipv6_skip_exthdr(skb, exthdr - skb->data,
768 &l4_proto_tmp, &frag_off);
769 } else if (l3.v4->version == 4) {
770 l4_proto_tmp = l3.v4->protocol;
771 }
772
773 *il4_proto = l4_proto_tmp;
1898d4e4
S		 774
775 return 0;
76ad4f0e
S		 776}
777
3db084d2
YL		 778/* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
779 * and it is udp packet, which has a dest port as the IANA assigned.
780 * the hardware is expected to do the checksum offload, but the
781 * hardware will not do the checksum offload when udp dest port is
782 * 4789.
783 */
784static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
785{
1a6e552d 786 union l4_hdr_info l4;
3db084d2
YL		 787
788 l4.hdr = skb_transport_header(skb);
789
bea96410
MS		 790 if (!(!skb->encapsulation &&
791 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
3db084d2
YL		 792 return false;
793
794 skb_checksum_help(skb);
795
796 return true;
797}
798
757cd1e4
YL		 799static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
800 u32 *ol_type_vlan_len_msec)
76ad4f0e 801{
757cd1e4
YL		 802 u32 l2_len, l3_len, l4_len;
803 unsigned char *il2_hdr;
1a6e552d 804 union l3_hdr_info l3;
757cd1e4 805 union l4_hdr_info l4;
76ad4f0e
S		 806
807 l3.hdr = skb_network_header(skb);
757cd1e4 808 l4.hdr = skb_transport_header(skb);
76ad4f0e 809
757cd1e4
YL		 810 /* compute OL2 header size, defined in 2 Bytes */
811 l2_len = l3.hdr - skb->data;
812 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
813
814 /* compute OL3 header size, defined in 4 Bytes */
815 l3_len = l4.hdr - l3.hdr;
816 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
76ad4f0e 817
757cd1e4 818 il2_hdr = skb_inner_mac_header(skb);
9b2f3477 819 /* compute OL4 header size, defined in 4 Bytes */
757cd1e4
YL		 820 l4_len = il2_hdr - l4.hdr;
821 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
822
823 /* define outer network header type */
824 if (skb->protocol == htons(ETH_P_IP)) {
825 if (skb_is_gso(skb))
cde4ffad 826 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 827 HNS3_TXD_OL3T_S,
828 HNS3_OL3T_IPV4_CSUM);
829 else
cde4ffad 830 hns3_set_field(*ol_type_vlan_len_msec,
757cd1e4
YL		 831 HNS3_TXD_OL3T_S,
832 HNS3_OL3T_IPV4_NO_CSUM);
833
834 } else if (skb->protocol == htons(ETH_P_IPV6)) {
835 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
836 HNS3_OL3T_IPV6);
837 }
838
839 if (ol4_proto == IPPROTO_UDP)
840 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
841 HNS3_TUN_MAC_IN_UDP);
842 else if (ol4_proto == IPPROTO_GRE)
843 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
844 HNS3_TUN_NVGRE);
845}
846
847static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
848 u8 il4_proto, u32 *type_cs_vlan_tso,
849 u32 *ol_type_vlan_len_msec)
850{
c264ed44 851 unsigned char *l2_hdr = skb->data;
757cd1e4
YL		 852 u32 l4_proto = ol4_proto;
853 union l4_hdr_info l4;
854 union l3_hdr_info l3;
855 u32 l2_len, l3_len;
856
857 l4.hdr = skb_transport_header(skb);
858 l3.hdr = skb_network_header(skb);
859
860 /* handle encapsulation skb */
861 if (skb->encapsulation) {
862 /* If this is a not UDP/GRE encapsulation skb */
863 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
76ad4f0e
S		 864 /* drop the skb tunnel packet if hardware don't support,
865 * because hardware can't calculate csum when TSO.
866 */
867 if (skb_is_gso(skb))
868 return -EDOM;
869
870 /* the stack computes the IP header already,
871 * driver calculate l4 checksum when not TSO.
872 */
873 skb_checksum_help(skb);
874 return 0;
875 }
876
757cd1e4
YL		 877 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
878
879 /* switch to inner header */
880 l2_hdr = skb_inner_mac_header(skb);
76ad4f0e 881 l3.hdr = skb_inner_network_header(skb);
757cd1e4 882 l4.hdr = skb_inner_transport_header(skb);
76ad4f0e
S		 883 l4_proto = il4_proto;
884 }
885
886 if (l3.v4->version == 4) {
cde4ffad
YL		 887 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
888 HNS3_L3T_IPV4);
76ad4f0e
S		 889
890 /* the stack computes the IP header already, the only time we
891 * need the hardware to recompute it is in the case of TSO.
892 */
893 if (skb_is_gso(skb))
cde4ffad 894 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
76ad4f0e 895 } else if (l3.v6->version == 6) {
cde4ffad
YL		 896 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
897 HNS3_L3T_IPV6);
76ad4f0e
S		 898 }
899
757cd1e4
YL		 900 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
901 l2_len = l3.hdr - l2_hdr;
902 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
903
904 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
905 l3_len = l4.hdr - l3.hdr;
906 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
907
908 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
76ad4f0e
S		 909 switch (l4_proto) {
910 case IPPROTO_TCP:
cde4ffad
YL		 911 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
912 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
913 HNS3_L4T_TCP);
757cd1e4
YL		 914 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
915 l4.tcp->doff);
76ad4f0e
S		 916 break;
917 case IPPROTO_UDP:
3db084d2
YL		 918 if (hns3_tunnel_csum_bug(skb))
919 break;
920
cde4ffad
YL		 921 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
922 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
923 HNS3_L4T_UDP);
757cd1e4
YL		 924 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
925 (sizeof(struct udphdr) >> 2));
76ad4f0e
S		 926 break;
927 case IPPROTO_SCTP:
cde4ffad
YL		 928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
929 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
930 HNS3_L4T_SCTP);
757cd1e4
YL		 931 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
932 (sizeof(struct sctphdr) >> 2));
76ad4f0e
S		 933 break;
934 default:
935 /* drop the skb tunnel packet if hardware don't support,
936 * because hardware can't calculate csum when TSO.
937 */
938 if (skb_is_gso(skb))
939 return -EDOM;
940
941 /* the stack computes the IP header already,
942 * driver calculate l4 checksum when not TSO.
943 */
944 skb_checksum_help(skb);
945 return 0;
946 }
947
948 return 0;
949}
950
951static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
952{
953 /* Config bd buffer end */
b9a8f883
YL		 954 if (!!frag_end)
955 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, 1U);
956 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1U);
76ad4f0e
S		 957}
958
9699cffe
PL		 959static int hns3_fill_desc_vtags(struct sk_buff *skb,
960 struct hns3_enet_ring *tx_ring,
961 u32 *inner_vlan_flag,
962 u32 *out_vlan_flag,
963 u16 *inner_vtag,
964 u16 *out_vtag)
965{
966#define HNS3_TX_VLAN_PRIO_SHIFT 13
967
44e626f7
JS		 968 struct hnae3_handle *handle = tx_ring->tqp->handle;
969
970 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
971 * header is allowed in skb, otherwise it will cause RAS error.
972 */
973 if (unlikely(skb_vlan_tagged_multi(skb) &&
974 handle->port_base_vlan_state ==
975 HNAE3_PORT_BASE_VLAN_ENABLE))
976 return -EINVAL;
977
9699cffe
PL		 978 if (skb->protocol == htons(ETH_P_8021Q) &&
979 !(tx_ring->tqp->handle->kinfo.netdev->features &
980 NETIF_F_HW_VLAN_CTAG_TX)) {
981 /* When HW VLAN acceleration is turned off, and the stack
982 * sets the protocol to 802.1q, the driver just need to
983 * set the protocol to the encapsulated ethertype.
984 */
985 skb->protocol = vlan_get_protocol(skb);
986 return 0;
987 }
988
989 if (skb_vlan_tag_present(skb)) {
990 u16 vlan_tag;
991
992 vlan_tag = skb_vlan_tag_get(skb);
993 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
994
995 /* Based on hw strategy, use out_vtag in two layer tag case,
996 * and use inner_vtag in one tag case.
997 */
998 if (skb->protocol == htons(ETH_P_8021Q)) {
44e626f7
JS		 999 if (handle->port_base_vlan_state ==
1000 HNAE3_PORT_BASE_VLAN_DISABLE){
1001 hns3_set_field(*out_vlan_flag,
1002 HNS3_TXD_OVLAN_B, 1);
1003 *out_vtag = vlan_tag;
1004 } else {
1005 hns3_set_field(*inner_vlan_flag,
1006 HNS3_TXD_VLAN_B, 1);
1007 *inner_vtag = vlan_tag;
1008 }
9699cffe 1009 } else {
cde4ffad 1010 hns3_set_field(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
9699cffe
PL		 1011 *inner_vtag = vlan_tag;
1012 }
1013 } else if (skb->protocol == htons(ETH_P_8021Q)) {
1014 struct vlan_ethhdr *vhdr;
1015 int rc;
1016
1017 rc = skb_cow_head(skb, 0);
0cccebac 1018 if (unlikely(rc < 0))
9699cffe
PL		 1019 return rc;
1020 vhdr = (struct vlan_ethhdr *)skb->data;
1021 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1022 << HNS3_TX_VLAN_PRIO_SHIFT);
1023 }
1024
1025 skb->protocol = vlan_get_protocol(skb);
1026 return 0;
1027}
1028
76ad4f0e 1029static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
ebaf1908
WL		 1030 unsigned int size, int frag_end,
1031 enum hns_desc_type type)
76ad4f0e
S		 1032{
1033 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1034 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
5188f218 1035 struct device *dev = ring_to_dev(ring);
5188f218 1036 struct skb_frag_struct *frag;
1e8a7977 1037 unsigned int frag_buf_num;
47e7b13b 1038 int k, sizeoflast;
5188f218 1039 dma_addr_t dma;
76ad4f0e 1040
76ad4f0e 1041 if (type == DESC_TYPE_SKB) {
47e7b13b
YL		 1042 struct sk_buff *skb = (struct sk_buff *)priv;
1043 u32 ol_type_vlan_len_msec = 0;
1044 u32 type_cs_vlan_tso = 0;
1045 u32 paylen = skb->len;
1046 u16 inner_vtag = 0;
1047 u16 out_vtag = 0;
1048 u16 mss = 0;
1049 int ret;
76ad4f0e 1050
9699cffe
PL		 1051 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1052 &ol_type_vlan_len_msec,
1053 &inner_vtag, &out_vtag);
1054 if (unlikely(ret))
1055 return ret;
1056
76ad4f0e 1057 if (skb->ip_summed == CHECKSUM_PARTIAL) {
47e7b13b
YL		 1058 u8 ol4_proto, il4_proto;
1059
76ad4f0e 1060 skb_reset_mac_len(skb);
76ad4f0e 1061
1898d4e4 1062 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
0cccebac 1063 if (unlikely(ret))
1898d4e4 1064 return ret;
757cd1e4
YL		 1065
1066 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1067 &type_cs_vlan_tso,
1068 &ol_type_vlan_len_msec);
0cccebac 1069 if (unlikely(ret))
76ad4f0e
S		 1070 return ret;
1071
1072 ret = hns3_set_tso(skb, &paylen, &mss,
1073 &type_cs_vlan_tso);
0cccebac 1074 if (unlikely(ret))
76ad4f0e
S		 1075 return ret;
1076 }
1077
1078 /* Set txbd */
1079 desc->tx.ol_type_vlan_len_msec =
1080 cpu_to_le32(ol_type_vlan_len_msec);
9b2f3477 1081 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
a90bb9a5 1082 desc->tx.paylen = cpu_to_le32(paylen);
76ad4f0e 1083 desc->tx.mss = cpu_to_le16(mss);
9699cffe
PL		 1084 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1085 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
5188f218
PL		 1086
1087 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1088 } else {
1089 frag = (struct skb_frag_struct *)priv;
1090 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1091 }
1092
845e0d1d 1093 if (unlikely(dma_mapping_error(dev, dma))) {
5188f218
PL		 1094 ring->stats.sw_err_cnt++;
1095 return -ENOMEM;
76ad4f0e
S		 1096 }
1097
bcdb12b7
FL		 1098 desc_cb->length = size;
1099
ceca4a5e
YL		 1100 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1101 u16 bdtp_fe_sc_vld_ra_ri = 0;
1102
1103 desc_cb->priv = priv;
1104 desc_cb->dma = dma;
1105 desc_cb->type = type;
1106 desc->addr = cpu_to_le64(dma);
1107 desc->tx.send_size = cpu_to_le16(size);
1108 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end);
1109 desc->tx.bdtp_fe_sc_vld_ra_ri =
1110 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1111
1112 ring_ptr_move_fw(ring, next_to_use);
1113 return 0;
1114 }
1115
5f543a54 1116 frag_buf_num = hns3_tx_bd_count(size);
3fe13ed9 1117 sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1e8a7977
FL		 1118 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1119
1120 /* When frag size is bigger than hardware limit, split this frag */
1121 for (k = 0; k < frag_buf_num; k++) {
ceca4a5e
YL		 1122 u16 bdtp_fe_sc_vld_ra_ri = 0;
1123
1e8a7977
FL		 1124 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1125 desc_cb->priv = priv;
1e8a7977
FL		 1126 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1127 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
9b2f3477 1128 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1e8a7977
FL		 1129
1130 /* now, fill the descriptor */
1131 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
bcdb12b7 1132 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
9b2f3477 1133 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1e8a7977
FL		 1134 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1135 frag_end && (k == frag_buf_num - 1) ?
1136 1 : 0);
1137 desc->tx.bdtp_fe_sc_vld_ra_ri =
1138 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1139
9b2f3477 1140 /* move ring pointer to next */
1e8a7977
FL		 1141 ring_ptr_move_fw(ring, next_to_use);
1142
1143 desc_cb = &ring->desc_cb[ring->next_to_use];
1144 desc = &ring->desc[ring->next_to_use];
1145 }
76ad4f0e
S		 1146
1147 return 0;
1148}
1149
3d5f3741 1150static int hns3_nic_bd_num(struct sk_buff *skb)
76ad4f0e 1151{
3d5f3741
YL		 1152 int size = skb_headlen(skb);
1153 int i, bd_num;
76ad4f0e 1154
3d5f3741
YL		 1155 /* if the total len is within the max bd limit */
1156 if (likely(skb->len <= HNS3_MAX_BD_SIZE))
1157 return skb_shinfo(skb)->nr_frags + 1;
76ad4f0e 1158
3d5f3741 1159 bd_num = hns3_tx_bd_count(size);
76ad4f0e 1160
3d5f3741
YL		 1161 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1162 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1163 int frag_bd_num;
76ad4f0e 1164
3d5f3741
YL		 1165 size = skb_frag_size(frag);
1166 frag_bd_num = hns3_tx_bd_count(size);
1167
1168 if (unlikely(frag_bd_num > HNS3_MAX_BD_PER_FRAG))
51e8439f 1169 return -ENOMEM;
51e8439f 1170
3d5f3741
YL		 1171 bd_num += frag_bd_num;
1172 }
76ad4f0e 1173
3d5f3741 1174 return bd_num;
76ad4f0e
S		 1175}
1176
db4970aa
YL		 1177static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1178{
1179 if (!skb->encapsulation)
1180 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1181
1182 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1183}
1184
1185/* HW need every continuous 8 buffer data to be larger than MSS,
1186 * we simplify it by ensuring skb_headlen + the first continuous
1187 * 7 frags to to be larger than gso header len + mss, and the remaining
1188 * continuous 7 frags to be larger than MSS except the last 7 frags.
1189 */
1190static bool hns3_skb_need_linearized(struct sk_buff *skb)
1191{
1192 int bd_limit = HNS3_MAX_BD_PER_FRAG - 1;
1193 unsigned int tot_len = 0;
1194 int i;
1195
1196 for (i = 0; i < bd_limit; i++)
1197 tot_len += skb_frag_size(&skb_shinfo(skb)->frags[i]);
1198
1199 /* ensure headlen + the first 7 frags is greater than mss + header
1200 * and the first 7 frags is greater than mss.
1201 */
1202 if (((tot_len + skb_headlen(skb)) < (skb_shinfo(skb)->gso_size +
1203 hns3_gso_hdr_len(skb))) || (tot_len < skb_shinfo(skb)->gso_size))
1204 return true;
1205
1206 /* ensure the remaining continuous 7 buffer is greater than mss */
1207 for (i = 0; i < (skb_shinfo(skb)->nr_frags - bd_limit - 1); i++) {
1208 tot_len -= skb_frag_size(&skb_shinfo(skb)->frags[i]);
1209 tot_len += skb_frag_size(&skb_shinfo(skb)->frags[i + bd_limit]);
1210
1211 if (tot_len < skb_shinfo(skb)->gso_size)
1212 return true;
1213 }
1214
1215 return false;
1216}
1217
3d5f3741
YL		 1218static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1219 struct sk_buff **out_skb)
76ad4f0e
S		 1220{
1221 struct sk_buff *skb = *out_skb;
3d5f3741 1222 int bd_num;
76ad4f0e 1223
3d5f3741
YL		 1224 bd_num = hns3_nic_bd_num(skb);
1225 if (bd_num < 0)
1226 return bd_num;
1227
1228 if (unlikely(bd_num > HNS3_MAX_BD_PER_FRAG)) {
1229 struct sk_buff *new_skb;
76ad4f0e 1230
db4970aa
YL		 1231 if (skb_is_gso(skb) && !hns3_skb_need_linearized(skb))
1232 goto out;
1233
3d5f3741
YL		 1234 bd_num = hns3_tx_bd_count(skb->len);
1235 if (unlikely(ring_space(ring) < bd_num))
51e8439f
PL		 1236 return -EBUSY;
1237 /* manual split the send packet */
1238 new_skb = skb_copy(skb, GFP_ATOMIC);
1239 if (!new_skb)
1240 return -ENOMEM;
1241 dev_kfree_skb_any(skb);
1242 *out_skb = new_skb;
3d5f3741
YL		 1243
1244 u64_stats_update_begin(&ring->syncp);
1245 ring->stats.tx_copy++;
1246 u64_stats_update_end(&ring->syncp);
51e8439f
PL		 1247 }
1248
db4970aa 1249out:
3d5f3741 1250 if (unlikely(ring_space(ring) < bd_num))
76ad4f0e
S		 1251 return -EBUSY;
1252
3d5f3741 1253 return bd_num;
76ad4f0e
S		 1254}
1255
ba3f808f 1256static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
76ad4f0e
S		 1257{
1258 struct device *dev = ring_to_dev(ring);
1259 unsigned int i;
1260
1261 for (i = 0; i < ring->desc_num; i++) {
1262 /* check if this is where we started */
1263 if (ring->next_to_use == next_to_use_orig)
1264 break;
1265
aa9d22dd
YL		 1266 /* rollback one */
1267 ring_ptr_move_bw(ring, next_to_use);
1268
76ad4f0e
S		 1269 /* unmap the descriptor dma address */
1270 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1271 dma_unmap_single(dev,
1272 ring->desc_cb[ring->next_to_use].dma,
1273 ring->desc_cb[ring->next_to_use].length,
1274 DMA_TO_DEVICE);
bcdb12b7 1275 else if (ring->desc_cb[ring->next_to_use].length)
76ad4f0e
S		 1276 dma_unmap_page(dev,
1277 ring->desc_cb[ring->next_to_use].dma,
1278 ring->desc_cb[ring->next_to_use].length,
1279 DMA_TO_DEVICE);
1280
bcdb12b7 1281 ring->desc_cb[ring->next_to_use].length = 0;
aa9d22dd 1282 ring->desc_cb[ring->next_to_use].dma = 0;
76ad4f0e
S		 1283 }
1284}
1285
d43e5aca 1286netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
76ad4f0e
S		 1287{
1288 struct hns3_nic_priv *priv = netdev_priv(netdev);
1289 struct hns3_nic_ring_data *ring_data =
1290 &tx_ring_data(priv, skb->queue_mapping);
1291 struct hns3_enet_ring *ring = ring_data->ring;
76ad4f0e
S		 1292 struct netdev_queue *dev_queue;
1293 struct skb_frag_struct *frag;
1294 int next_to_use_head;
76ad4f0e
S		 1295 int buf_num;
1296 int seg_num;
1297 int size;
1298 int ret;
1299 int i;
1300
1301 /* Prefetch the data used later */
1302 prefetch(skb->data);
1303
3d5f3741
YL		 1304 buf_num = hns3_nic_maybe_stop_tx(ring, &skb);
1305 if (unlikely(buf_num <= 0)) {
1306 if (buf_num == -EBUSY) {
1307 u64_stats_update_begin(&ring->syncp);
1308 ring->stats.tx_busy++;
1309 u64_stats_update_end(&ring->syncp);
1310 goto out_net_tx_busy;
1311 } else if (buf_num == -ENOMEM) {
1312 u64_stats_update_begin(&ring->syncp);
1313 ring->stats.sw_err_cnt++;
1314 u64_stats_update_end(&ring->syncp);
1315 }
76ad4f0e 1316
3d5f3741
YL		 1317 if (net_ratelimit())
1318 netdev_err(netdev, "xmit error: %d!\n", buf_num);
76ad4f0e
S		 1319
1320 goto out_err_tx_ok;
76ad4f0e
S		 1321 }
1322
1323 /* No. of segments (plus a header) */
1324 seg_num = skb_shinfo(skb)->nr_frags + 1;
1325 /* Fill the first part */
1326 size = skb_headlen(skb);
1327
1328 next_to_use_head = ring->next_to_use;
1329
d40fa7ee
YL		 1330 ret = hns3_fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1331 DESC_TYPE_SKB);
0cccebac 1332 if (unlikely(ret))
aa9d22dd 1333 goto fill_err;
76ad4f0e 1334
76ad4f0e
S		 1335 /* Fill the fragments */
1336 for (i = 1; i < seg_num; i++) {
1337 frag = &skb_shinfo(skb)->frags[i - 1];
1338 size = skb_frag_size(frag);
5188f218 1339
d40fa7ee
YL		 1340 ret = hns3_fill_desc(ring, frag, size,
1341 seg_num - 1 == i ? 1 : 0,
1342 DESC_TYPE_PAGE);
76ad4f0e 1343
0cccebac 1344 if (unlikely(ret))
aa9d22dd 1345 goto fill_err;
76ad4f0e
S		 1346 }
1347
1348 /* Complete translate all packets */
1349 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1350 netdev_tx_sent_queue(dev_queue, skb->len);
1351
1352 wmb(); /* Commit all data before submit */
1353
e4e87715 1354 hnae3_queue_xmit(ring->tqp, buf_num);
76ad4f0e
S		 1355
1356 return NETDEV_TX_OK;
1357
aa9d22dd 1358fill_err:
ba3f808f 1359 hns3_clear_desc(ring, next_to_use_head);
76ad4f0e
S		 1360
1361out_err_tx_ok:
1362 dev_kfree_skb_any(skb);
1363 return NETDEV_TX_OK;
1364
1365out_net_tx_busy:
1366 netif_stop_subqueue(netdev, ring_data->queue_index);
1367 smp_mb(); /* Commit all data before submit */
1368
1369 return NETDEV_TX_BUSY;
1370}
1371
1372static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1373{
9780cb97 1374 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1375 struct sockaddr *mac_addr = p;
1376 int ret;
1377
1378 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1379 return -EADDRNOTAVAIL;
1380
5ec2a51e
JS		 1381 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1382 netdev_info(netdev, "already using mac address %pM\n",
1383 mac_addr->sa_data);
1384 return 0;
1385 }
1386
59098055 1387 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
76ad4f0e
S		 1388 if (ret) {
1389 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1390 return ret;
1391 }
1392
1393 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1394
1395 return 0;
1396}
1397
26483246
XW		 1398static int hns3_nic_do_ioctl(struct net_device *netdev,
1399 struct ifreq *ifr, int cmd)
1400{
1401 struct hnae3_handle *h = hns3_get_handle(netdev);
1402
1403 if (!netif_running(netdev))
1404 return -EINVAL;
1405
1406 if (!h->ae_algo->ops->do_ioctl)
1407 return -EOPNOTSUPP;
1408
1409 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1410}
1411
76ad4f0e
S		 1412static int hns3_nic_set_features(struct net_device *netdev,
1413 netdev_features_t features)
1414{
181d454b 1415 netdev_features_t changed = netdev->features ^ features;
76ad4f0e 1416 struct hns3_nic_priv *priv = netdev_priv(netdev);
052ece6d 1417 struct hnae3_handle *h = priv->ae_handle;
1731be4c 1418 bool enable;
052ece6d 1419 int ret;
76ad4f0e 1420
5c9f6b39 1421 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1731be4c
YL		 1422 enable = !!(features & NETIF_F_GRO_HW);
1423 ret = h->ae_algo->ops->set_gro_en(h, enable);
5c9f6b39
PL		 1424 if (ret)
1425 return ret;
1426 }
1427
bd368416
JS		 1428 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1429 h->ae_algo->ops->enable_vlan_filter) {
1731be4c
YL		 1430 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
1431 h->ae_algo->ops->enable_vlan_filter(h, enable);
181d454b 1432 }
391b5e93 1433
bd368416
JS		 1434 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1435 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1731be4c
YL		 1436 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1437 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
052ece6d
PL		 1438 if (ret)
1439 return ret;
1440 }
1441
c17852a8 1442 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1731be4c
YL		 1443 enable = !!(features & NETIF_F_NTUPLE);
1444 h->ae_algo->ops->enable_fd(h, enable);
c17852a8
JS		 1445 }
1446
76ad4f0e
S		 1447 netdev->features = features;
1448 return 0;
1449}
1450
6c88d9d7
PL		 1451static void hns3_nic_get_stats64(struct net_device *netdev,
1452 struct rtnl_link_stats64 *stats)
76ad4f0e
S		 1453{
1454 struct hns3_nic_priv *priv = netdev_priv(netdev);
1455 int queue_num = priv->ae_handle->kinfo.num_tqps;
c5f65480 1456 struct hnae3_handle *handle = priv->ae_handle;
76ad4f0e 1457 struct hns3_enet_ring *ring;
d3ec4ef6
JS		 1458 u64 rx_length_errors = 0;
1459 u64 rx_crc_errors = 0;
1460 u64 rx_multicast = 0;
76ad4f0e 1461 unsigned int start;
d3ec4ef6
JS		 1462 u64 tx_errors = 0;
1463 u64 rx_errors = 0;
76ad4f0e
S		 1464 unsigned int idx;
1465 u64 tx_bytes = 0;
1466 u64 rx_bytes = 0;
1467 u64 tx_pkts = 0;
1468 u64 rx_pkts = 0;
d2a5dca8
JS		 1469 u64 tx_drop = 0;
1470 u64 rx_drop = 0;
76ad4f0e 1471
b875cc37
JS		 1472 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1473 return;
1474
c5f65480
JS		 1475 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1476
76ad4f0e
S		 1477 for (idx = 0; idx < queue_num; idx++) {
1478 /* fetch the tx stats */
1479 ring = priv->ring_data[idx].ring;
1480 do {
d36d36ce 1481 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1482 tx_bytes += ring->stats.tx_bytes;
1483 tx_pkts += ring->stats.tx_pkts;
d2a5dca8 1484 tx_drop += ring->stats.sw_err_cnt;
d3ec4ef6 1485 tx_errors += ring->stats.sw_err_cnt;
76ad4f0e
S		 1486 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1487
1488 /* fetch the rx stats */
1489 ring = priv->ring_data[idx + queue_num].ring;
1490 do {
d36d36ce 1491 start = u64_stats_fetch_begin_irq(&ring->syncp);
76ad4f0e
S		 1492 rx_bytes += ring->stats.rx_bytes;
1493 rx_pkts += ring->stats.rx_pkts;
d2a5dca8 1494 rx_drop += ring->stats.l2_err;
d3ec4ef6 1495 rx_errors += ring->stats.l2_err;
8b552079 1496 rx_errors += ring->stats.l3l4_csum_err;
d3ec4ef6 1497 rx_crc_errors += ring->stats.l2_err;
d3ec4ef6
JS		 1498 rx_multicast += ring->stats.rx_multicast;
1499 rx_length_errors += ring->stats.err_pkt_len;
76ad4f0e
S		 1500 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1501 }
1502
1503 stats->tx_bytes = tx_bytes;
1504 stats->tx_packets = tx_pkts;
1505 stats->rx_bytes = rx_bytes;
1506 stats->rx_packets = rx_pkts;
1507
d3ec4ef6
JS		 1508 stats->rx_errors = rx_errors;
1509 stats->multicast = rx_multicast;
1510 stats->rx_length_errors = rx_length_errors;
1511 stats->rx_crc_errors = rx_crc_errors;
76ad4f0e
S		 1512 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1513
d3ec4ef6
JS		 1514 stats->tx_errors = tx_errors;
1515 stats->rx_dropped = rx_drop;
1516 stats->tx_dropped = tx_drop;
76ad4f0e
S		 1517 stats->collisions = netdev->stats.collisions;
1518 stats->rx_over_errors = netdev->stats.rx_over_errors;
1519 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1520 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1521 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1522 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1523 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1524 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1525 stats->tx_window_errors = netdev->stats.tx_window_errors;
1526 stats->rx_compressed = netdev->stats.rx_compressed;
1527 stats->tx_compressed = netdev->stats.tx_compressed;
1528}
1529
30d240df 1530static int hns3_setup_tc(struct net_device *netdev, void *type_data)
76ad4f0e 1531{
30d240df 1532 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
30d240df 1533 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
75718800 1534 struct hnae3_knic_private_info *kinfo;
30d240df
YL		 1535 u8 tc = mqprio_qopt->qopt.num_tc;
1536 u16 mode = mqprio_qopt->mode;
1537 u8 hw = mqprio_qopt->qopt.hw;
75718800 1538 struct hnae3_handle *h;
76ad4f0e 1539
30d240df
YL		 1540 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1541 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1542 return -EOPNOTSUPP;
1543
76ad4f0e
S		 1544 if (tc > HNAE3_MAX_TC)
1545 return -EINVAL;
1546
76ad4f0e
S		 1547 if (!netdev)
1548 return -EINVAL;
1549
75718800
YL		 1550 h = hns3_get_handle(netdev);
1551 kinfo = &h->kinfo;
1552
1cce5eb6 1553 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
30d240df 1554 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
76ad4f0e
S		 1555}
1556
2572ac53 1557static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 1558 void *type_data)
76ad4f0e 1559{
575ed7d3 1560 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 1561 return -EOPNOTSUPP;
76ad4f0e 1562
30d240df 1563 return hns3_setup_tc(dev, type_data);
76ad4f0e
S		 1564}
1565
1566static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1567 __be16 proto, u16 vid)
1568{
9780cb97 1569 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1570 int ret = -EIO;
1571
1572 if (h->ae_algo->ops->set_vlan_filter)
1573 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1574
1575 return ret;
1576}
1577
1578static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1579 __be16 proto, u16 vid)
1580{
9780cb97 1581 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1582 int ret = -EIO;
1583
1584 if (h->ae_algo->ops->set_vlan_filter)
1585 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1586
7fa6be4f 1587 return ret;
681ec399
YL		 1588}
1589
76ad4f0e
S		 1590static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1591 u8 qos, __be16 vlan_proto)
1592{
9780cb97 1593 struct hnae3_handle *h = hns3_get_handle(netdev);
76ad4f0e
S		 1594 int ret = -EIO;
1595
1596 if (h->ae_algo->ops->set_vf_vlan_filter)
1597 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
9b2f3477 1598 qos, vlan_proto);
76ad4f0e
S		 1599
1600 return ret;
1601}
1602
a8e8b7ff
S		 1603static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1604{
9780cb97 1605 struct hnae3_handle *h = hns3_get_handle(netdev);
a8e8b7ff
S		 1606 int ret;
1607
6ff7ed80
HT		 1608 if (hns3_nic_resetting(netdev))
1609 return -EBUSY;
1610
a8e8b7ff
S		 1611 if (!h->ae_algo->ops->set_mtu)
1612 return -EOPNOTSUPP;
1613
a8e8b7ff 1614 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
93d8daf4 1615 if (ret)
a8e8b7ff
S		 1616 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1617 ret);
93d8daf4
YL		 1618 else
1619 netdev->mtu = new_mtu;
5bad95a1 1620
a8e8b7ff
S		 1621 return ret;
1622}
1623
f8fa222c
L		 1624static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1625{
1626 struct hns3_nic_priv *priv = netdev_priv(ndev);
e511c97d 1627 struct hnae3_handle *h = hns3_get_handle(ndev);
f8fa222c 1628 struct hns3_enet_ring *tx_ring = NULL;
e511c97d 1629 struct napi_struct *napi;
f8fa222c
L		 1630 int timeout_queue = 0;
1631 int hw_head, hw_tail;
e511c97d
JS		 1632 int fbd_num, fbd_oft;
1633 int ebd_num, ebd_oft;
1634 int bd_num, bd_err;
1635 int ring_en, tc;
f8fa222c
L		 1636 int i;
1637
1638 /* Find the stopped queue the same way the stack does */
fa6c4084 1639 for (i = 0; i < ndev->num_tx_queues; i++) {
f8fa222c
L		 1640 struct netdev_queue *q;
1641 unsigned long trans_start;
1642
1643 q = netdev_get_tx_queue(ndev, i);
1644 trans_start = q->trans_start;
1645 if (netif_xmit_stopped(q) &&
1646 time_after(jiffies,
1647 (trans_start + ndev->watchdog_timeo))) {
1648 timeout_queue = i;
1649 break;
1650 }
1651 }
1652
1653 if (i == ndev->num_tx_queues) {
1654 netdev_info(ndev,
1655 "no netdev TX timeout queue found, timeout count: %llu\n",
1656 priv->tx_timeout_count);
1657 return false;
1658 }
1659
beab694a
JS		 1660 priv->tx_timeout_count++;
1661
f8fa222c 1662 tx_ring = priv->ring_data[timeout_queue].ring;
e511c97d
JS		 1663 napi = &tx_ring->tqp_vector->napi;
1664
1665 netdev_info(ndev,
1666 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1667 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1668 tx_ring->next_to_clean, napi->state);
1669
1670 netdev_info(ndev,
1671 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1672 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1673 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1674
1675 netdev_info(ndev,
1676 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1677 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1678 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1679
1680 /* When mac received many pause frames continuous, it's unable to send
1681 * packets, which may cause tx timeout
1682 */
1683 if (h->ae_algo->ops->update_stats &&
1684 h->ae_algo->ops->get_mac_pause_stats) {
1685 u64 tx_pause_cnt, rx_pause_cnt;
1686
1687 h->ae_algo->ops->update_stats(h, &ndev->stats);
1688 h->ae_algo->ops->get_mac_pause_stats(h, &tx_pause_cnt,
1689 &rx_pause_cnt);
1690 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1691 tx_pause_cnt, rx_pause_cnt);
1692 }
f8fa222c
L		 1693
1694 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1695 HNS3_RING_TX_RING_HEAD_REG);
1696 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1697 HNS3_RING_TX_RING_TAIL_REG);
e511c97d
JS		 1698 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1699 HNS3_RING_TX_RING_FBDNUM_REG);
1700 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1701 HNS3_RING_TX_RING_OFFSET_REG);
1702 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1703 HNS3_RING_TX_RING_EBDNUM_REG);
1704 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1705 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1706 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1707 HNS3_RING_TX_RING_BD_NUM_REG);
1708 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1709 HNS3_RING_TX_RING_BD_ERR_REG);
1710 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1711 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1712
f8fa222c 1713 netdev_info(ndev,
e511c97d
JS		 1714 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1715 bd_num, hw_head, hw_tail, bd_err,
f8fa222c 1716 readl(tx_ring->tqp_vector->mask_addr));
e511c97d
JS		 1717 netdev_info(ndev,
1718 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1719 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
f8fa222c
L		 1720
1721 return true;
1722}
1723
1724static void hns3_nic_net_timeout(struct net_device *ndev)
1725{
1726 struct hns3_nic_priv *priv = netdev_priv(ndev);
f8fa222c
L		 1727 struct hnae3_handle *h = priv->ae_handle;
1728
1729 if (!hns3_get_tx_timeo_queue_info(ndev))
1730 return;
1731
0742ed7c
HT		 1732 /* request the reset, and let the hclge to determine
1733 * which reset level should be done
1734 */
f8fa222c 1735 if (h->ae_algo->ops->reset_event)
6ae4e733 1736 h->ae_algo->ops->reset_event(h->pdev, h);
f8fa222c
L		 1737}
1738
d93ed94f
JS		 1739#ifdef CONFIG_RFS_ACCEL
1740static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1741 u16 rxq_index, u32 flow_id)
1742{
1743 struct hnae3_handle *h = hns3_get_handle(dev);
1744 struct flow_keys fkeys;
1745
1746 if (!h->ae_algo->ops->add_arfs_entry)
1747 return -EOPNOTSUPP;
1748
1749 if (skb->encapsulation)
1750 return -EPROTONOSUPPORT;
1751
1752 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1753 return -EPROTONOSUPPORT;
1754
1755 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1756 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1757 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1758 fkeys.basic.ip_proto != IPPROTO_UDP))
1759 return -EPROTONOSUPPORT;
1760
1761 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1762}
1763#endif
1764
76ad4f0e
S		 1765static const struct net_device_ops hns3_nic_netdev_ops = {
1766 .ndo_open = hns3_nic_net_open,
1767 .ndo_stop = hns3_nic_net_stop,
1768 .ndo_start_xmit = hns3_nic_net_xmit,
f8fa222c 1769 .ndo_tx_timeout = hns3_nic_net_timeout,
76ad4f0e 1770 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
26483246 1771 .ndo_do_ioctl = hns3_nic_do_ioctl,
a8e8b7ff 1772 .ndo_change_mtu = hns3_nic_change_mtu,
76ad4f0e
S		 1773 .ndo_set_features = hns3_nic_set_features,
1774 .ndo_get_stats64 = hns3_nic_get_stats64,
1775 .ndo_setup_tc = hns3_nic_setup_tc,
1776 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
76ad4f0e
S		 1777 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1778 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1779 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
d93ed94f
JS		 1780#ifdef CONFIG_RFS_ACCEL
1781 .ndo_rx_flow_steer = hns3_rx_flow_steer,
1782#endif
1783
76ad4f0e
S		 1784};
1785
97afd47b 1786bool hns3_is_phys_func(struct pci_dev *pdev)
2312e050
FL		 1787{
1788 u32 dev_id = pdev->device;
1789
1790 switch (dev_id) {
1791 case HNAE3_DEV_ID_GE:
1792 case HNAE3_DEV_ID_25GE:
1793 case HNAE3_DEV_ID_25GE_RDMA:
1794 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1795 case HNAE3_DEV_ID_50GE_RDMA:
1796 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1797 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1798 return true;
1799 case HNAE3_DEV_ID_100G_VF:
1800 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1801 return false;
1802 default:
1803 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1804 dev_id);
1805 }
1806
1807 return false;
1808}
1809
2312e050
FL		 1810static void hns3_disable_sriov(struct pci_dev *pdev)
1811{
1812 /* If our VFs are assigned we cannot shut down SR-IOV
1813 * without causing issues, so just leave the hardware
1814 * available but disabled
1815 */
1816 if (pci_vfs_assigned(pdev)) {
1817 dev_warn(&pdev->dev,
1818 "disabling driver while VFs are assigned\n");
1819 return;
1820 }
1821
1822 pci_disable_sriov(pdev);
1823}
1824
d695964d
JS		 1825static void hns3_get_dev_capability(struct pci_dev *pdev,
1826 struct hnae3_ae_dev *ae_dev)
1827{
b26a6fea 1828 if (pdev->revision >= 0x21) {
d695964d 1829 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
b26a6fea
PL		 1830 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1831 }
d695964d
JS		 1832}
1833
76ad4f0e
S		 1834/* hns3_probe - Device initialization routine
1835 * @pdev: PCI device information struct
1836 * @ent: entry in hns3_pci_tbl
1837 *
1838 * hns3_probe initializes a PF identified by a pci_dev structure.
1839 * The OS initialization, configuring of the PF private structure,
1840 * and a hardware reset occur.
1841 *
1842 * Returns 0 on success, negative on failure
1843 */
1844static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1845{
1846 struct hnae3_ae_dev *ae_dev;
1847 int ret;
1848
9b2f3477 1849 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
76ad4f0e
S		 1850 if (!ae_dev) {
1851 ret = -ENOMEM;
1852 return ret;
1853 }
1854
1855 ae_dev->pdev = pdev;
e92a0843 1856 ae_dev->flag = ent->driver_data;
6871af29 1857 ae_dev->reset_type = HNAE3_NONE_RESET;
d695964d 1858 hns3_get_dev_capability(pdev, ae_dev);
76ad4f0e
S		 1859 pci_set_drvdata(pdev, ae_dev);
1860
74354140
HT		 1861 ret = hnae3_register_ae_dev(ae_dev);
1862 if (ret) {
1863 devm_kfree(&pdev->dev, ae_dev);
1864 pci_set_drvdata(pdev, NULL);
1865 }
2312e050 1866
74354140 1867 return ret;
76ad4f0e
S		 1868}
1869
1870/* hns3_remove - Device removal routine
1871 * @pdev: PCI device information struct
1872 */
1873static void hns3_remove(struct pci_dev *pdev)
1874{
1875 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1876
2312e050
FL		 1877 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1878 hns3_disable_sriov(pdev);
1879
76ad4f0e 1880 hnae3_unregister_ae_dev(ae_dev);
ac864c23 1881 pci_set_drvdata(pdev, NULL);
76ad4f0e
S		 1882}
1883
fa8d82e8
PL		 1884/**
1885 * hns3_pci_sriov_configure
1886 * @pdev: pointer to a pci_dev structure
1887 * @num_vfs: number of VFs to allocate
1888 *
1889 * Enable or change the number of VFs. Called when the user updates the number
1890 * of VFs in sysfs.
1891 **/
743e1a84 1892static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
fa8d82e8
PL		 1893{
1894 int ret;
1895
1896 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1897 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1898 return -EINVAL;
1899 }
1900
1901 if (num_vfs) {
1902 ret = pci_enable_sriov(pdev, num_vfs);
1903 if (ret)
1904 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
743e1a84
SM		 1905 else
1906 return num_vfs;
fa8d82e8
PL		 1907 } else if (!pci_vfs_assigned(pdev)) {
1908 pci_disable_sriov(pdev);
1909 } else {
1910 dev_warn(&pdev->dev,
1911 "Unable to free VFs because some are assigned to VMs.\n");
1912 }
1913
1914 return 0;
1915}
1916
ce2c1d2e
YL		 1917static void hns3_shutdown(struct pci_dev *pdev)
1918{
1919 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1920
1921 hnae3_unregister_ae_dev(ae_dev);
1922 devm_kfree(&pdev->dev, ae_dev);
1923 pci_set_drvdata(pdev, NULL);
1924
1925 if (system_state == SYSTEM_POWER_OFF)
1926 pci_set_power_state(pdev, PCI_D3hot);
1927}
1928
5a9f0eac
SJ		 1929static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1930 pci_channel_state_t state)
1931{
1932 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1933 pci_ers_result_t ret;
1934
1935 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1936
1937 if (state == pci_channel_io_perm_failure)
1938 return PCI_ERS_RESULT_DISCONNECT;
1939
661262bc 1940 if (!ae_dev || !ae_dev->ops) {
5a9f0eac 1941 dev_err(&pdev->dev,
661262bc 1942 "Can't recover - error happened before device initialized\n");
5a9f0eac
SJ		 1943 return PCI_ERS_RESULT_NONE;
1944 }
1945
381c356e
SJ		 1946 if (ae_dev->ops->handle_hw_ras_error)
1947 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
5a9f0eac
SJ		 1948 else
1949 return PCI_ERS_RESULT_NONE;
1950
1951 return ret;
1952}
1953
6ae4e733
SJ		 1954static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1955{
1956 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
ad9bf545 1957 const struct hnae3_ae_ops *ops;
123297b7 1958 enum hnae3_reset_type reset_type;
6ae4e733
SJ		 1959 struct device *dev = &pdev->dev;
1960
661262bc
WL		 1961 if (!ae_dev || !ae_dev->ops)
1962 return PCI_ERS_RESULT_NONE;
1963
ad9bf545 1964 ops = ae_dev->ops;
6ae4e733 1965 /* request the reset */
123297b7 1966 if (ops->reset_event) {
9d5e67d1 1967 if (ae_dev->hw_err_reset_req) {
123297b7
SJ		 1968 reset_type = ops->get_reset_level(ae_dev,
1969 &ae_dev->hw_err_reset_req);
1970 ops->set_default_reset_request(ae_dev, reset_type);
1971 dev_info(dev, "requesting reset due to PCI error\n");
1972 ops->reset_event(pdev, NULL);
1973 }
69b51bbb 1974
6ae4e733
SJ		 1975 return PCI_ERS_RESULT_RECOVERED;
1976 }
1977
1978 return PCI_ERS_RESULT_DISCONNECT;
1979}
1980
6b9a97ee
HT		 1981static void hns3_reset_prepare(struct pci_dev *pdev)
1982{
1983 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1984
1985 dev_info(&pdev->dev, "hns3 flr prepare\n");
1986 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1987 ae_dev->ops->flr_prepare(ae_dev);
1988}
1989
1990static void hns3_reset_done(struct pci_dev *pdev)
1991{
1992 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1993
1994 dev_info(&pdev->dev, "hns3 flr done\n");
1995 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
1996 ae_dev->ops->flr_done(ae_dev);
1997}
1998
5a9f0eac
SJ		 1999static const struct pci_error_handlers hns3_err_handler = {
2000 .error_detected = hns3_error_detected,
6ae4e733 2001 .slot_reset = hns3_slot_reset,
6b9a97ee
HT		 2002 .reset_prepare = hns3_reset_prepare,
2003 .reset_done = hns3_reset_done,
5a9f0eac
SJ		 2004};
2005
76ad4f0e
S		 2006static struct pci_driver hns3_driver = {
2007 .name = hns3_driver_name,
2008 .id_table = hns3_pci_tbl,
2009 .probe = hns3_probe,
2010 .remove = hns3_remove,
ce2c1d2e 2011 .shutdown = hns3_shutdown,
fa8d82e8 2012 .sriov_configure = hns3_pci_sriov_configure,
5a9f0eac 2013 .err_handler = &hns3_err_handler,
76ad4f0e
S		 2014};
2015
2016/* set default feature to hns3 */
2017static void hns3_set_default_feature(struct net_device *netdev)
2018{
3e85af6a
PL		 2019 struct hnae3_handle *h = hns3_get_handle(netdev);
2020 struct pci_dev *pdev = h->pdev;
2021
76ad4f0e
S		 2022 netdev->priv_flags |= IFF_UNICAST_FLT;
2023
2024 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2025 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2026 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2027 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2028 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 2029
2030 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
2031
2032 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2033
2034 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2035 NETIF_F_HW_VLAN_CTAG_FILTER |
052ece6d 2036 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2037 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2038 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2039 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2040 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 2041
2042 netdev->vlan_features |=
2043 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2044 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2045 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2046 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2047 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
76ad4f0e
S		 2048
2049 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
b2641e2a 2050 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
76ad4f0e
S		 2051 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2052 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2053 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
5b71ac3c 2054 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
3e85af6a 2055
c17852a8 2056 if (pdev->revision >= 0x21) {
77af09c6 2057 netdev->hw_features |= NETIF_F_GRO_HW;
5c9f6b39 2058 netdev->features |= NETIF_F_GRO_HW;
c17852a8
JS		 2059
2060 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2061 netdev->hw_features |= NETIF_F_NTUPLE;
2062 netdev->features |= NETIF_F_NTUPLE;
2063 }
2064 }
76ad4f0e
S		 2065}
2066
2067static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2068 struct hns3_desc_cb *cb)
2069{
e4e87715 2070 unsigned int order = hnae3_page_order(ring);
76ad4f0e
S		 2071 struct page *p;
2072
2073 p = dev_alloc_pages(order);
2074 if (!p)
2075 return -ENOMEM;
2076
2077 cb->priv = p;
2078 cb->page_offset = 0;
2079 cb->reuse_flag = 0;
2080 cb->buf = page_address(p);
e4e87715 2081 cb->length = hnae3_page_size(ring);
76ad4f0e
S		 2082 cb->type = DESC_TYPE_PAGE;
2083
76ad4f0e
S		 2084 return 0;
2085}
2086
2087static void hns3_free_buffer(struct hns3_enet_ring *ring,
2088 struct hns3_desc_cb *cb)
2089{
2090 if (cb->type == DESC_TYPE_SKB)
2091 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2092 else if (!HNAE3_IS_TX_RING(ring))
2093 put_page((struct page *)cb->priv);
2094 memset(cb, 0, sizeof(*cb));
2095}
2096
2097static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2098{
2099 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2100 cb->length, ring_to_dma_dir(ring));
2101
2211f4e1 2102 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
76ad4f0e
S		 2103 return -EIO;
2104
2105 return 0;
2106}
2107
2108static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2109 struct hns3_desc_cb *cb)
2110{
2111 if (cb->type == DESC_TYPE_SKB)
2112 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2113 ring_to_dma_dir(ring));
bcdb12b7 2114 else if (cb->length)
76ad4f0e
S		 2115 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2116 ring_to_dma_dir(ring));
2117}
2118
2119static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2120{
2121 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2122 ring->desc[i].addr = 0;
2123}
2124
2125static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2126{
2127 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2128
2129 if (!ring->desc_cb[i].dma)
2130 return;
2131
2132 hns3_buffer_detach(ring, i);
2133 hns3_free_buffer(ring, cb);
2134}
2135
2136static void hns3_free_buffers(struct hns3_enet_ring *ring)
2137{
2138 int i;
2139
2140 for (i = 0; i < ring->desc_num; i++)
2141 hns3_free_buffer_detach(ring, i);
2142}
2143
2144/* free desc along with its attached buffer */
2145static void hns3_free_desc(struct hns3_enet_ring *ring)
2146{
024cc792
HT		 2147 int size = ring->desc_num * sizeof(ring->desc[0]);
2148
76ad4f0e
S		 2149 hns3_free_buffers(ring);
2150
024cc792
HT		 2151 if (ring->desc) {
2152 dma_free_coherent(ring_to_dev(ring), size,
2153 ring->desc, ring->desc_dma_addr);
2154 ring->desc = NULL;
2155 }
76ad4f0e
S		 2156}
2157
2158static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2159{
2160 int size = ring->desc_num * sizeof(ring->desc[0]);
2161
750afb08
LC		 2162 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2163 &ring->desc_dma_addr, GFP_KERNEL);
76ad4f0e
S		 2164 if (!ring->desc)
2165 return -ENOMEM;
2166
76ad4f0e
S		 2167 return 0;
2168}
2169
2170static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2171 struct hns3_desc_cb *cb)
2172{
2173 int ret;
2174
2175 ret = hns3_alloc_buffer(ring, cb);
2176 if (ret)
2177 goto out;
2178
2179 ret = hns3_map_buffer(ring, cb);
2180 if (ret)
2181 goto out_with_buf;
2182
2183 return 0;
2184
2185out_with_buf:
564883bb 2186 hns3_free_buffer(ring, cb);
76ad4f0e
S		 2187out:
2188 return ret;
2189}
2190
2191static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2192{
2193 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2194
2195 if (ret)
2196 return ret;
2197
2198 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2199
2200 return 0;
2201}
2202
2203/* Allocate memory for raw pkg, and map with dma */
2204static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2205{
2206 int i, j, ret;
2207
2208 for (i = 0; i < ring->desc_num; i++) {
2209 ret = hns3_alloc_buffer_attach(ring, i);
2210 if (ret)
2211 goto out_buffer_fail;
2212 }
2213
2214 return 0;
2215
2216out_buffer_fail:
2217 for (j = i - 1; j >= 0; j--)
2218 hns3_free_buffer_detach(ring, j);
2219 return ret;
2220}
2221
9b2f3477 2222/* detach a in-used buffer and replace with a reserved one */
76ad4f0e
S		 2223static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2224 struct hns3_desc_cb *res_cb)
2225{
b9077428 2226 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
76ad4f0e
S		 2227 ring->desc_cb[i] = *res_cb;
2228 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
7d0b130c 2229 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2230}
2231
2232static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2233{
2234 ring->desc_cb[i].reuse_flag = 0;
9b2f3477
WL		 2235 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2236 ring->desc_cb[i].page_offset);
7d0b130c 2237 ring->desc[i].rx.bd_base_info = 0;
76ad4f0e
S		 2238}
2239
ce74370c
YL		 2240static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2241 int *bytes, int *pkts)
76ad4f0e 2242{
26cda2f1
YL		 2243 int ntc = ring->next_to_clean;
2244 struct hns3_desc_cb *desc_cb;
76ad4f0e 2245
ce74370c
YL		 2246 while (head != ntc) {
2247 desc_cb = &ring->desc_cb[ntc];
2248 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2249 (*bytes) += desc_cb->length;
2250 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2251 hns3_free_buffer_detach(ring, ntc);
76ad4f0e 2252
ce74370c
YL		 2253 if (++ntc == ring->desc_num)
2254 ntc = 0;
2255
2256 /* Issue prefetch for next Tx descriptor */
2257 prefetch(&ring->desc_cb[ntc]);
2258 }
26cda2f1
YL		 2259
2260 /* This smp_store_release() pairs with smp_load_acquire() in
2261 * ring_space called by hns3_nic_net_xmit.
2262 */
2263 smp_store_release(&ring->next_to_clean, ntc);
76ad4f0e
S		 2264}
2265
2266static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2267{
2268 int u = ring->next_to_use;
2269 int c = ring->next_to_clean;
2270
2271 if (unlikely(h > ring->desc_num))
2272 return 0;
2273
2274 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2275}
2276
799997a3 2277void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
76ad4f0e
S		 2278{
2279 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
7a810110 2280 struct hns3_nic_priv *priv = netdev_priv(netdev);
76ad4f0e
S		 2281 struct netdev_queue *dev_queue;
2282 int bytes, pkts;
2283 int head;
2284
2285 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2286 rmb(); /* Make sure head is ready before touch any data */
2287
2288 if (is_ring_empty(ring) || head == ring->next_to_clean)
799997a3 2289 return; /* no data to poll */
76ad4f0e 2290
0e6084aa 2291 if (unlikely(!is_valid_clean_head(ring, head))) {
76ad4f0e
S		 2292 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2293 ring->next_to_use, ring->next_to_clean);
2294
2295 u64_stats_update_begin(&ring->syncp);
2296 ring->stats.io_err_cnt++;
2297 u64_stats_update_end(&ring->syncp);
799997a3 2298 return;
76ad4f0e
S		 2299 }
2300
2301 bytes = 0;
2302 pkts = 0;
ce74370c 2303 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
76ad4f0e
S		 2304
2305 ring->tqp_vector->tx_group.total_bytes += bytes;
2306 ring->tqp_vector->tx_group.total_packets += pkts;
2307
2308 u64_stats_update_begin(&ring->syncp);
2309 ring->stats.tx_bytes += bytes;
2310 ring->stats.tx_pkts += pkts;
2311 u64_stats_update_end(&ring->syncp);
2312
2313 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2314 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2315
2316 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2317 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2318 /* Make sure that anybody stopping the queue after this
2319 * sees the new next_to_clean.
2320 */
2321 smp_mb();
7a810110
JS		 2322 if (netif_tx_queue_stopped(dev_queue) &&
2323 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
76ad4f0e
S		 2324 netif_tx_wake_queue(dev_queue);
2325 ring->stats.restart_queue++;
2326 }
2327 }
76ad4f0e
S		 2328}
2329
2330static int hns3_desc_unused(struct hns3_enet_ring *ring)
2331{
2332 int ntc = ring->next_to_clean;
2333 int ntu = ring->next_to_use;
2334
2335 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2336}
2337
9b2f3477
WL		 2338static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2339 int cleand_count)
76ad4f0e
S		 2340{
2341 struct hns3_desc_cb *desc_cb;
2342 struct hns3_desc_cb res_cbs;
2343 int i, ret;
2344
2345 for (i = 0; i < cleand_count; i++) {
2346 desc_cb = &ring->desc_cb[ring->next_to_use];
2347 if (desc_cb->reuse_flag) {
2348 u64_stats_update_begin(&ring->syncp);
2349 ring->stats.reuse_pg_cnt++;
2350 u64_stats_update_end(&ring->syncp);
2351
2352 hns3_reuse_buffer(ring, ring->next_to_use);
2353 } else {
2354 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2355 if (ret) {
2356 u64_stats_update_begin(&ring->syncp);
2357 ring->stats.sw_err_cnt++;
2358 u64_stats_update_end(&ring->syncp);
2359
2360 netdev_err(ring->tqp->handle->kinfo.netdev,
2361 "hnae reserve buffer map failed.\n");
2362 break;
2363 }
2364 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
d21ff4f9
YL		 2365
2366 u64_stats_update_begin(&ring->syncp);
2367 ring->stats.non_reuse_pg++;
2368 u64_stats_update_end(&ring->syncp);
76ad4f0e
S		 2369 }
2370
2371 ring_ptr_move_fw(ring, next_to_use);
2372 }
2373
2374 wmb(); /* Make all data has been write before submit */
2375 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2376}
2377
76ad4f0e
S		 2378static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2379 struct hns3_enet_ring *ring, int pull_len,
2380 struct hns3_desc_cb *desc_cb)
2381{
389ca146
YL		 2382 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2383 int size = le16_to_cpu(desc->rx.size);
2384 u32 truesize = hnae3_buf_size(ring);
76ad4f0e
S		 2385
2386 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
f8d291f0 2387 size - pull_len, truesize);
76ad4f0e 2388
389ca146
YL		 2389 /* Avoid re-using remote pages, or the stack is still using the page
2390 * when page_offset rollback to zero, flag default unreuse
2391 */
d5970dc7 2392 if (unlikely(page_to_nid(desc_cb->priv) != numa_mem_id()) ||
389ca146 2393 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
76ad4f0e 2394 return;
76ad4f0e
S		 2395
2396 /* Move offset up to the next cache line */
2397 desc_cb->page_offset += truesize;
2398
389ca146 2399 if (desc_cb->page_offset + truesize <= hnae3_page_size(ring)) {
76ad4f0e 2400 desc_cb->reuse_flag = 1;
9b2f3477 2401 /* Bump ref count on page before it is given */
76ad4f0e 2402 get_page(desc_cb->priv);
389ca146
YL		 2403 } else if (page_count(desc_cb->priv) == 1) {
2404 desc_cb->reuse_flag = 1;
2405 desc_cb->page_offset = 0;
2406 get_page(desc_cb->priv);
76ad4f0e
S		 2407 }
2408}
2409
e2ee1c5a 2410static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
d474d88f
YL		 2411{
2412 __be16 type = skb->protocol;
2413 struct tcphdr *th;
2414 int depth = 0;
2415
e2ee1c5a 2416 while (eth_type_vlan(type)) {
d474d88f
YL		 2417 struct vlan_hdr *vh;
2418
2419 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2420 return -EFAULT;
2421
2422 vh = (struct vlan_hdr *)(skb->data + depth);
2423 type = vh->h_vlan_encapsulated_proto;
2424 depth += VLAN_HLEN;
2425 }
2426
e2ee1c5a
YL		 2427 skb_set_network_header(skb, depth);
2428
d474d88f 2429 if (type == htons(ETH_P_IP)) {
e2ee1c5a
YL		 2430 const struct iphdr *iph = ip_hdr(skb);
2431
d474d88f 2432 depth += sizeof(struct iphdr);
e2ee1c5a
YL		 2433 skb_set_transport_header(skb, depth);
2434 th = tcp_hdr(skb);
2435 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2436 iph->daddr, 0);
d474d88f 2437 } else if (type == htons(ETH_P_IPV6)) {
e2ee1c5a
YL		 2438 const struct ipv6hdr *iph = ipv6_hdr(skb);
2439
d474d88f 2440 depth += sizeof(struct ipv6hdr);
e2ee1c5a
YL		 2441 skb_set_transport_header(skb, depth);
2442 th = tcp_hdr(skb);
2443 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2444 &iph->daddr, 0);
d474d88f
YL		 2445 } else {
2446 netdev_err(skb->dev,
2447 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2448 be16_to_cpu(type), depth);
2449 return -EFAULT;
2450 }
2451
d474d88f
YL		 2452 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2453 if (th->cwr)
2454 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2455
e2ee1c5a
YL		 2456 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2457 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
d474d88f 2458
e2ee1c5a
YL		 2459 skb->csum_start = (unsigned char *)th - skb->head;
2460 skb->csum_offset = offsetof(struct tcphdr, check);
2461 skb->ip_summed = CHECKSUM_PARTIAL;
d474d88f
YL		 2462 return 0;
2463}
2464
76ad4f0e 2465static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
39c38824 2466 u32 l234info, u32 bd_base_info, u32 ol_info)
76ad4f0e
S		 2467{
2468 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2469 int l3_type, l4_type;
76ad4f0e 2470 int ol4_type;
76ad4f0e
S		 2471
2472 skb->ip_summed = CHECKSUM_NONE;
2473
2474 skb_checksum_none_assert(skb);
2475
2476 if (!(netdev->features & NETIF_F_RXCSUM))
2477 return;
2478
2479 /* check if hardware has done checksum */
e8149933 2480 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
76ad4f0e
S		 2481 return;
2482
f4772dee
DC		 2483 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2484 BIT(HNS3_RXD_OL3E_B) |
e8149933 2485 BIT(HNS3_RXD_OL4E_B)))) {
76ad4f0e
S		 2486 u64_stats_update_begin(&ring->syncp);
2487 ring->stats.l3l4_csum_err++;
2488 u64_stats_update_end(&ring->syncp);
2489
2490 return;
2491 }
2492
39c38824 2493 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
e4e87715 2494 HNS3_RXD_OL4ID_S);
76ad4f0e
S		 2495 switch (ol4_type) {
2496 case HNS3_OL4_TYPE_MAC_IN_UDP:
2497 case HNS3_OL4_TYPE_NVGRE:
2498 skb->csum_level = 1;
be44b3af 2499 /* fall through */
76ad4f0e 2500 case HNS3_OL4_TYPE_NO_TUN:
47e7b13b
YL		 2501 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2502 HNS3_RXD_L3ID_S);
2503 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2504 HNS3_RXD_L4ID_S);
2505
76ad4f0e 2506 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
94c5e532
PL		 2507 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2508 l3_type == HNS3_L3_TYPE_IPV6) &&
2509 (l4_type == HNS3_L4_TYPE_UDP ||
2510 l4_type == HNS3_L4_TYPE_TCP ||
2511 l4_type == HNS3_L4_TYPE_SCTP))
76ad4f0e
S		 2512 skb->ip_summed = CHECKSUM_UNNECESSARY;
2513 break;
fa7a4bd5
JS		 2514 default:
2515 break;
76ad4f0e
S		 2516 }
2517}
2518
d43e5aca
YL		 2519static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2520{
81ae0e04
PL		 2521 if (skb_has_frag_list(skb))
2522 napi_gro_flush(&ring->tqp_vector->napi, false);
2523
d43e5aca
YL		 2524 napi_gro_receive(&ring->tqp_vector->napi, skb);
2525}
2526
701a6d6a
JS		 2527static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2528 struct hns3_desc *desc, u32 l234info,
2529 u16 *vlan_tag)
5b5455a9 2530{
44e626f7 2531 struct hnae3_handle *handle = ring->tqp->handle;
5b5455a9 2532 struct pci_dev *pdev = ring->tqp->handle->pdev;
5b5455a9
PL		 2533
2534 if (pdev->revision == 0x20) {
701a6d6a
JS		 2535 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2536 if (!(*vlan_tag & VLAN_VID_MASK))
2537 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
5b5455a9 2538
701a6d6a 2539 return (*vlan_tag != 0);
5b5455a9
PL		 2540 }
2541
2542#define HNS3_STRP_OUTER_VLAN 0x1
2543#define HNS3_STRP_INNER_VLAN 0x2
44e626f7 2544#define HNS3_STRP_BOTH 0x3
5b5455a9 2545
44e626f7
JS		 2546 /* Hardware always insert VLAN tag into RX descriptor when
2547 * remove the tag from packet, driver needs to determine
2548 * reporting which tag to stack.
2549 */
e4e87715
PL		 2550 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2551 HNS3_RXD_STRP_TAGP_S)) {
5b5455a9 2552 case HNS3_STRP_OUTER_VLAN:
44e626f7
JS		 2553 if (handle->port_base_vlan_state !=
2554 HNAE3_PORT_BASE_VLAN_DISABLE)
2555 return false;
2556
701a6d6a
JS		 2557 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2558 return true;
5b5455a9 2559 case HNS3_STRP_INNER_VLAN:
44e626f7
JS		 2560 if (handle->port_base_vlan_state !=
2561 HNAE3_PORT_BASE_VLAN_DISABLE)
2562 return false;
2563
701a6d6a 2564 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
44e626f7
JS		 2565 return true;
2566 case HNS3_STRP_BOTH:
2567 if (handle->port_base_vlan_state ==
2568 HNAE3_PORT_BASE_VLAN_DISABLE)
2569 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2570 else
2571 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2572
701a6d6a 2573 return true;
5b5455a9 2574 default:
701a6d6a 2575 return false;
5b5455a9 2576 }
5b5455a9
PL		 2577}
2578
b9a8f883 2579static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
e5597095
PL		 2580 unsigned char *va)
2581{
2582#define HNS3_NEED_ADD_FRAG 1
2583 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2584 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2585 struct sk_buff *skb;
2586
2587 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2588 skb = ring->skb;
2589 if (unlikely(!skb)) {
2590 netdev_err(netdev, "alloc rx skb fail\n");
2591
2592 u64_stats_update_begin(&ring->syncp);
2593 ring->stats.sw_err_cnt++;
2594 u64_stats_update_end(&ring->syncp);
2595
2596 return -ENOMEM;
2597 }
2598
2599 prefetchw(skb->data);
2600
2601 ring->pending_buf = 1;
81ae0e04
PL		 2602 ring->frag_num = 0;
2603 ring->tail_skb = NULL;
e5597095
PL		 2604 if (length <= HNS3_RX_HEAD_SIZE) {
2605 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2606
2607 /* We can reuse buffer as-is, just make sure it is local */
d5970dc7 2608 if (likely(page_to_nid(desc_cb->priv) == numa_mem_id()))
e5597095
PL		 2609 desc_cb->reuse_flag = 1;
2610 else /* This page cannot be reused so discard it */
2611 put_page(desc_cb->priv);
2612
2613 ring_ptr_move_fw(ring, next_to_clean);
2614 return 0;
2615 }
2616 u64_stats_update_begin(&ring->syncp);
2617 ring->stats.seg_pkt_cnt++;
2618 u64_stats_update_end(&ring->syncp);
2619
c43f1255 2620 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
e5597095 2621 __skb_put(skb, ring->pull_len);
81ae0e04 2622 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
e5597095
PL		 2623 desc_cb);
2624 ring_ptr_move_fw(ring, next_to_clean);
2625
2626 return HNS3_NEED_ADD_FRAG;
2627}
2628
2629static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2630 struct sk_buff **out_skb, bool pending)
2631{
2632 struct sk_buff *skb = *out_skb;
81ae0e04
PL		 2633 struct sk_buff *head_skb = *out_skb;
2634 struct sk_buff *new_skb;
e5597095
PL		 2635 struct hns3_desc_cb *desc_cb;
2636 struct hns3_desc *pre_desc;
2637 u32 bd_base_info;
2638 int pre_bd;
2639
2640 /* if there is pending bd, the SW param next_to_clean has moved
2641 * to next and the next is NULL
2642 */
2643 if (pending) {
2644 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
9b2f3477 2645 ring->desc_num;
e5597095
PL		 2646 pre_desc = &ring->desc[pre_bd];
2647 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2648 } else {
2649 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2650 }
2651
e8149933 2652 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
e5597095
PL		 2653 desc = &ring->desc[ring->next_to_clean];
2654 desc_cb = &ring->desc_cb[ring->next_to_clean];
2655 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
d394d33b
JS		 2656 /* make sure HW write desc complete */
2657 dma_rmb();
e8149933 2658 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
e5597095
PL		 2659 return -ENXIO;
2660
81ae0e04
PL		 2661 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2662 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2663 HNS3_RX_HEAD_SIZE);
2664 if (unlikely(!new_skb)) {
2665 netdev_err(ring->tqp->handle->kinfo.netdev,
2666 "alloc rx skb frag fail\n");
2667 return -ENXIO;
2668 }
2669 ring->frag_num = 0;
2670
2671 if (ring->tail_skb) {
2672 ring->tail_skb->next = new_skb;
2673 ring->tail_skb = new_skb;
2674 } else {
2675 skb_shinfo(skb)->frag_list = new_skb;
2676 ring->tail_skb = new_skb;
2677 }
2678 }
2679
2680 if (ring->tail_skb) {
2681 head_skb->truesize += hnae3_buf_size(ring);
2682 head_skb->data_len += le16_to_cpu(desc->rx.size);
2683 head_skb->len += le16_to_cpu(desc->rx.size);
2684 skb = ring->tail_skb;
2685 }
2686
2687 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
e5597095
PL		 2688 ring_ptr_move_fw(ring, next_to_clean);
2689 ring->pending_buf++;
2690 }
2691
2692 return 0;
2693}
2694
d474d88f
YL		 2695static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2696 struct sk_buff *skb, u32 l234info,
39c38824 2697 u32 bd_base_info, u32 ol_info)
a6d53b97 2698{
a6d53b97
PL		 2699 u32 l3_type;
2700
e2ee1c5a
YL		 2701 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2702 HNS3_RXD_GRO_SIZE_M,
2703 HNS3_RXD_GRO_SIZE_S);
a6d53b97 2704 /* if there is no HW GRO, do not set gro params */
e2ee1c5a 2705 if (!skb_shinfo(skb)->gso_size) {
39c38824 2706 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
d474d88f
YL		 2707 return 0;
2708 }
a6d53b97 2709
e2ee1c5a
YL		 2710 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2711 HNS3_RXD_GRO_COUNT_M,
2712 HNS3_RXD_GRO_COUNT_S);
a6d53b97 2713
9b2f3477 2714 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
a6d53b97
PL		 2715 if (l3_type == HNS3_L3_TYPE_IPV4)
2716 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2717 else if (l3_type == HNS3_L3_TYPE_IPV6)
2718 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2719 else
d474d88f 2720 return -EFAULT;
a6d53b97 2721
e2ee1c5a 2722 return hns3_gro_complete(skb, l234info);
a6d53b97
PL		 2723}
2724
232fc64b 2725static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
ea485867 2726 struct sk_buff *skb, u32 rss_hash)
232fc64b 2727{
232fc64b
PL		 2728 struct hnae3_handle *handle = ring->tqp->handle;
2729 enum pkt_hash_types rss_type;
2730
ea485867 2731 if (rss_hash)
232fc64b
PL		 2732 rss_type = handle->kinfo.rss_type;
2733 else
2734 rss_type = PKT_HASH_TYPE_NONE;
2735
ea485867 2736 skb_set_hash(skb, rss_hash, rss_type);
232fc64b
PL		 2737}
2738
ea485867 2739static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
76ad4f0e
S		 2740{
2741 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
c376fa1a 2742 enum hns3_pkt_l2t_type l2_frame_type;
39c38824 2743 u32 bd_base_info, l234info, ol_info;
ea485867 2744 struct hns3_desc *desc;
d474d88f 2745 unsigned int len;
ea485867
YL		 2746 int pre_ntc, ret;
2747
2748 /* bdinfo handled below is only valid on the last BD of the
2749 * current packet, and ring->next_to_clean indicates the first
2750 * descriptor of next packet, so need - 1 below.
2751 */
2752 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2753 (ring->desc_num - 1);
2754 desc = &ring->desc[pre_ntc];
2755 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2756 l234info = le32_to_cpu(desc->rx.l234_info);
39c38824 2757 ol_info = le32_to_cpu(desc->rx.ol_info);
d474d88f
YL		 2758
2759 /* Based on hw strategy, the tag offloaded will be stored at
2760 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2761 * in one layer tag case.
2762 */
2763 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2764 u16 vlan_tag;
2765
2766 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2767 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2768 vlan_tag);
2769 }
2770
d474d88f
YL		 2771 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
2772 BIT(HNS3_RXD_L2E_B))))) {
2773 u64_stats_update_begin(&ring->syncp);
2774 if (l234info & BIT(HNS3_RXD_L2E_B))
2775 ring->stats.l2_err++;
2776 else
2777 ring->stats.err_pkt_len++;
2778 u64_stats_update_end(&ring->syncp);
2779
2780 return -EFAULT;
2781 }
2782
2783 len = skb->len;
2784
2785 /* Do update ip stack process */
2786 skb->protocol = eth_type_trans(skb, netdev);
2787
2788 /* This is needed in order to enable forwarding support */
39c38824
YL		 2789 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
2790 bd_base_info, ol_info);
d474d88f
YL		 2791 if (unlikely(ret)) {
2792 u64_stats_update_begin(&ring->syncp);
2793 ring->stats.rx_err_cnt++;
2794 u64_stats_update_end(&ring->syncp);
2795 return ret;
2796 }
2797
2798 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
2799 HNS3_RXD_DMAC_S);
2800
2801 u64_stats_update_begin(&ring->syncp);
2802 ring->stats.rx_pkts++;
2803 ring->stats.rx_bytes += len;
2804
2805 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
2806 ring->stats.rx_multicast++;
2807
2808 u64_stats_update_end(&ring->syncp);
2809
2810 ring->tqp_vector->rx_group.total_bytes += len;
ea485867
YL		 2811
2812 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
d474d88f
YL		 2813 return 0;
2814}
2815
2816static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2817 struct sk_buff **out_skb)
2818{
e5597095 2819 struct sk_buff *skb = ring->skb;
76ad4f0e
S		 2820 struct hns3_desc_cb *desc_cb;
2821 struct hns3_desc *desc;
b9a8f883 2822 unsigned int length;
76ad4f0e 2823 u32 bd_base_info;
e5597095 2824 int ret;
76ad4f0e
S		 2825
2826 desc = &ring->desc[ring->next_to_clean];
2827 desc_cb = &ring->desc_cb[ring->next_to_clean];
2828
2829 prefetch(desc);
2830
846fcc83 2831 length = le16_to_cpu(desc->rx.size);
76ad4f0e 2832 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
76ad4f0e
S		 2833
2834 /* Check valid BD */
e8149933 2835 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
e5597095 2836 return -ENXIO;
76ad4f0e 2837
e5597095
PL		 2838 if (!skb)
2839 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
76ad4f0e
S		 2840
2841 /* Prefetch first cache line of first page
2842 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2843 * line size is 64B so need to prefetch twice to make it 128B. But in
2844 * actual we can have greater size of caches with 128B Level 1 cache
2845 * lines. In such a case, single fetch would suffice to cache in the
2846 * relevant part of the header.
2847 */
e5597095 2848 prefetch(ring->va);
76ad4f0e 2849#if L1_CACHE_BYTES < 128
e5597095 2850 prefetch(ring->va + L1_CACHE_BYTES);
76ad4f0e
S		 2851#endif
2852
e5597095
PL		 2853 if (!skb) {
2854 ret = hns3_alloc_skb(ring, length, ring->va);
2855 *out_skb = skb = ring->skb;
76ad4f0e 2856
e5597095
PL		 2857 if (ret < 0) /* alloc buffer fail */
2858 return ret;
2859 if (ret > 0) { /* need add frag */
2860 ret = hns3_add_frag(ring, desc, &skb, false);
2861 if (ret)
2862 return ret;
76ad4f0e 2863
e5597095
PL		 2864 /* As the head data may be changed when GRO enable, copy
2865 * the head data in after other data rx completed
2866 */
2867 memcpy(skb->data, ring->va,
2868 ALIGN(ring->pull_len, sizeof(long)));
2869 }
76ad4f0e 2870 } else {
e5597095
PL		 2871 ret = hns3_add_frag(ring, desc, &skb, true);
2872 if (ret)
2873 return ret;
76ad4f0e 2874
e5597095
PL		 2875 /* As the head data may be changed when GRO enable, copy
2876 * the head data in after other data rx completed
2877 */
2878 memcpy(skb->data, ring->va,
2879 ALIGN(ring->pull_len, sizeof(long)));
76ad4f0e
S		 2880 }
2881
ea485867 2882 ret = hns3_handle_bdinfo(ring, skb);
d474d88f 2883 if (unlikely(ret)) {
76ad4f0e 2884 dev_kfree_skb_any(skb);
d474d88f 2885 return ret;
76ad4f0e
S		 2886 }
2887
d93ed94f 2888 skb_record_rx_queue(skb, ring->tqp->tqp_index);
e5597095 2889 *out_skb = skb;
232fc64b 2890
76ad4f0e
S		 2891 return 0;
2892}
2893
9b2f3477
WL		 2894int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
2895 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
76ad4f0e
S		 2896{
2897#define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
76ad4f0e 2898 int recv_pkts, recv_bds, clean_count, err;
63380a1a 2899 int unused_count = hns3_desc_unused(ring);
e5597095
PL		 2900 struct sk_buff *skb = ring->skb;
2901 int num;
76ad4f0e
S		 2902
2903 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2904 rmb(); /* Make sure num taken effect before the other data is touched */
2905
2906 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2907 num -= unused_count;
63380a1a 2908 unused_count -= ring->pending_buf;
76ad4f0e
S		 2909
2910 while (recv_pkts < budget && recv_bds < num) {
2911 /* Reuse or realloc buffers */
2912 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2913 hns3_nic_alloc_rx_buffers(ring,
2914 clean_count + unused_count);
2915 clean_count = 0;
e5597095
PL		 2916 unused_count = hns3_desc_unused(ring) -
2917 ring->pending_buf;
76ad4f0e
S		 2918 }
2919
2920 /* Poll one pkt */
e5597095 2921 err = hns3_handle_rx_bd(ring, &skb);
76ad4f0e
S		 2922 if (unlikely(!skb)) /* This fault cannot be repaired */
2923 goto out;
2924
e5597095
PL		 2925 if (err == -ENXIO) { /* Do not get FE for the packet */
2926 goto out;
2927 } else if (unlikely(err)) { /* Do jump the err */
2928 recv_bds += ring->pending_buf;
2929 clean_count += ring->pending_buf;
2930 ring->skb = NULL;
2931 ring->pending_buf = 0;
76ad4f0e
S		 2932 continue;
2933 }
2934
d43e5aca 2935 rx_fn(ring, skb);
e5597095
PL		 2936 recv_bds += ring->pending_buf;
2937 clean_count += ring->pending_buf;
2938 ring->skb = NULL;
2939 ring->pending_buf = 0;
76ad4f0e
S		 2940
2941 recv_pkts++;
2942 }
2943
2944out:
2945 /* Make all data has been write before submit */
2946 if (clean_count + unused_count > 0)
9b2f3477 2947 hns3_nic_alloc_rx_buffers(ring, clean_count + unused_count);
76ad4f0e
S		 2948
2949 return recv_pkts;
2950}
2951
4a43caf5 2952static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
76ad4f0e 2953{
4a43caf5
YL		 2954#define HNS3_RX_LOW_BYTE_RATE 10000
2955#define HNS3_RX_MID_BYTE_RATE 20000
2956#define HNS3_RX_ULTRA_PACKET_RATE 40
2957
76ad4f0e 2958 enum hns3_flow_level_range new_flow_level;
4a43caf5
YL		 2959 struct hns3_enet_tqp_vector *tqp_vector;
2960 int packets_per_msecs, bytes_per_msecs;
a95e1f86 2961 u32 time_passed_ms;
76ad4f0e 2962
4a43caf5 2963 tqp_vector = ring_group->ring->tqp_vector;
a95e1f86
FL		 2964 time_passed_ms =
2965 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
a95e1f86
FL		 2966 if (!time_passed_ms)
2967 return false;
2968
2969 do_div(ring_group->total_packets, time_passed_ms);
2970 packets_per_msecs = ring_group->total_packets;
2971
2972 do_div(ring_group->total_bytes, time_passed_ms);
2973 bytes_per_msecs = ring_group->total_bytes;
2974
4a43caf5 2975 new_flow_level = ring_group->coal.flow_level;
76ad4f0e 2976
4a43caf5
YL		 2977 /* Simple throttlerate management
2978 * 0-10MB/s lower (50000 ints/s)
2979 * 10-20MB/s middle (20000 ints/s)
2980 * 20-1249MB/s high (18000 ints/s)
2981 * > 40000pps ultra (8000 ints/s)
2982 */
76ad4f0e
S		 2983 switch (new_flow_level) {
2984 case HNS3_FLOW_LOW:
a95e1f86 2985 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2986 new_flow_level = HNS3_FLOW_MID;
2987 break;
2988 case HNS3_FLOW_MID:
a95e1f86 2989 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
76ad4f0e 2990 new_flow_level = HNS3_FLOW_HIGH;
a95e1f86 2991 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
76ad4f0e
S		 2992 new_flow_level = HNS3_FLOW_LOW;
2993 break;
2994 case HNS3_FLOW_HIGH:
2995 case HNS3_FLOW_ULTRA:
2996 default:
a95e1f86 2997 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
76ad4f0e
S		 2998 new_flow_level = HNS3_FLOW_MID;
2999 break;
3000 }
3001
a95e1f86
FL		 3002 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3003 &tqp_vector->rx_group == ring_group)
76ad4f0e
S		 3004 new_flow_level = HNS3_FLOW_ULTRA;
3005
4a43caf5
YL		 3006 ring_group->total_bytes = 0;
3007 ring_group->total_packets = 0;
3008 ring_group->coal.flow_level = new_flow_level;
3009
3010 return true;
3011}
3012
3013static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3014{
3015 struct hns3_enet_tqp_vector *tqp_vector;
3016 u16 new_int_gl;
3017
3018 if (!ring_group->ring)
3019 return false;
3020
3021 tqp_vector = ring_group->ring->tqp_vector;
3022 if (!tqp_vector->last_jiffies)
3023 return false;
3024
3025 if (ring_group->total_packets == 0) {
3026 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3027 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3028 return true;
3029 }
3030
3031 if (!hns3_get_new_flow_lvl(ring_group))
3032 return false;
3033
3034 new_int_gl = ring_group->coal.int_gl;
3035 switch (ring_group->coal.flow_level) {
76ad4f0e
S		 3036 case HNS3_FLOW_LOW:
3037 new_int_gl = HNS3_INT_GL_50K;
3038 break;
3039 case HNS3_FLOW_MID:
3040 new_int_gl = HNS3_INT_GL_20K;
3041 break;
3042 case HNS3_FLOW_HIGH:
3043 new_int_gl = HNS3_INT_GL_18K;
3044 break;
3045 case HNS3_FLOW_ULTRA:
3046 new_int_gl = HNS3_INT_GL_8K;
3047 break;
3048 default:
3049 break;
3050 }
3051
9bc727a9
YL		 3052 if (new_int_gl != ring_group->coal.int_gl) {
3053 ring_group->coal.int_gl = new_int_gl;
76ad4f0e
S		 3054 return true;
3055 }
3056 return false;
3057}
3058
3059static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3060{
8b1ff1ea
FL		 3061 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3062 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3063 bool rx_update, tx_update;
3064
7445565c
PL		 3065 /* update param every 1000ms */
3066 if (time_before(jiffies,
3067 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
cd9d187b 3068 return;
cd9d187b 3069
9bc727a9 3070 if (rx_group->coal.gl_adapt_enable) {
8b1ff1ea
FL		 3071 rx_update = hns3_get_new_int_gl(rx_group);
3072 if (rx_update)
3073 hns3_set_vector_coalesce_rx_gl(tqp_vector,
9bc727a9 3074 rx_group->coal.int_gl);
8b1ff1ea
FL		 3075 }
3076
9bc727a9 3077 if (tx_group->coal.gl_adapt_enable) {
9e50dc11 3078 tx_update = hns3_get_new_int_gl(tx_group);
8b1ff1ea
FL		 3079 if (tx_update)
3080 hns3_set_vector_coalesce_tx_gl(tqp_vector,
9bc727a9 3081 tx_group->coal.int_gl);
76ad4f0e 3082 }
cd9d187b 3083
a95e1f86 3084 tqp_vector->last_jiffies = jiffies;
76ad4f0e
S		 3085}
3086
3087static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3088{
ff0699e0 3089 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
76ad4f0e
S		 3090 struct hns3_enet_ring *ring;
3091 int rx_pkt_total = 0;
3092
3093 struct hns3_enet_tqp_vector *tqp_vector =
3094 container_of(napi, struct hns3_enet_tqp_vector, napi);
3095 bool clean_complete = true;
ceca4a5e 3096 int rx_budget = budget;
76ad4f0e 3097
ff0699e0
HT		 3098 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3099 napi_complete(napi);
3100 return 0;
3101 }
3102
76ad4f0e
S		 3103 /* Since the actual Tx work is minimal, we can give the Tx a larger
3104 * budget and be more aggressive about cleaning up the Tx descriptors.
3105 */
799997a3
PL		 3106 hns3_for_each_ring(ring, tqp_vector->tx_group)
3107 hns3_clean_tx_ring(ring);
76ad4f0e
S		 3108
3109 /* make sure rx ring budget not smaller than 1 */
ceca4a5e
YL		 3110 if (tqp_vector->num_tqps > 1)
3111 rx_budget = max(budget / tqp_vector->num_tqps, 1);
76ad4f0e
S		 3112
3113 hns3_for_each_ring(ring, tqp_vector->rx_group) {
d43e5aca
YL		 3114 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3115 hns3_rx_skb);
76ad4f0e
S		 3116
3117 if (rx_cleaned >= rx_budget)
3118 clean_complete = false;
3119
3120 rx_pkt_total += rx_cleaned;
3121 }
3122
3123 tqp_vector->rx_group.total_packets += rx_pkt_total;
3124
3125 if (!clean_complete)
3126 return budget;
3127
531eba0f
HT		 3128 if (napi_complete(napi) &&
3129 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
ff0699e0
HT		 3130 hns3_update_new_int_gl(tqp_vector);
3131 hns3_mask_vector_irq(tqp_vector, 1);
3132 }
76ad4f0e
S		 3133
3134 return rx_pkt_total;
3135}
3136
3137static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3138 struct hnae3_ring_chain_node *head)
3139{
3140 struct pci_dev *pdev = tqp_vector->handle->pdev;
3141 struct hnae3_ring_chain_node *cur_chain = head;
3142 struct hnae3_ring_chain_node *chain;
3143 struct hns3_enet_ring *tx_ring;
3144 struct hns3_enet_ring *rx_ring;
3145
3146 tx_ring = tqp_vector->tx_group.ring;
3147 if (tx_ring) {
3148 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3149 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3150 HNAE3_RING_TYPE_TX);
3151 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3152 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
76ad4f0e
S		 3153
3154 cur_chain->next = NULL;
3155
3156 while (tx_ring->next) {
3157 tx_ring = tx_ring->next;
3158
3159 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3160 GFP_KERNEL);
3161 if (!chain)
73b907a0 3162 goto err_free_chain;
76ad4f0e
S		 3163
3164 cur_chain->next = chain;
3165 chain->tqp_index = tx_ring->tqp->tqp_index;
e4e87715
PL		 3166 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3167 HNAE3_RING_TYPE_TX);
3168 hnae3_set_field(chain->int_gl_idx,
3169 HNAE3_RING_GL_IDX_M,
3170 HNAE3_RING_GL_IDX_S,
3171 HNAE3_RING_GL_TX);
76ad4f0e
S		 3172
3173 cur_chain = chain;
3174 }
3175 }
3176
3177 rx_ring = tqp_vector->rx_group.ring;
3178 if (!tx_ring && rx_ring) {
3179 cur_chain->next = NULL;
3180 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3181 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3182 HNAE3_RING_TYPE_RX);
3183 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3184 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
76ad4f0e
S		 3185
3186 rx_ring = rx_ring->next;
3187 }
3188
3189 while (rx_ring) {
3190 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3191 if (!chain)
73b907a0 3192 goto err_free_chain;
76ad4f0e
S		 3193
3194 cur_chain->next = chain;
3195 chain->tqp_index = rx_ring->tqp->tqp_index;
e4e87715
PL		 3196 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3197 HNAE3_RING_TYPE_RX);
3198 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3199 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
11af96a4 3200
76ad4f0e
S		 3201 cur_chain = chain;
3202
3203 rx_ring = rx_ring->next;
3204 }
3205
3206 return 0;
73b907a0
HT		 3207
3208err_free_chain:
3209 cur_chain = head->next;
3210 while (cur_chain) {
3211 chain = cur_chain->next;
cda69d24 3212 devm_kfree(&pdev->dev, cur_chain);
73b907a0
HT		 3213 cur_chain = chain;
3214 }
cda69d24 3215 head->next = NULL;
73b907a0
HT		 3216
3217 return -ENOMEM;
76ad4f0e
S		 3218}
3219
3220static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3221 struct hnae3_ring_chain_node *head)
3222{
3223 struct pci_dev *pdev = tqp_vector->handle->pdev;
3224 struct hnae3_ring_chain_node *chain_tmp, *chain;
3225
3226 chain = head->next;
3227
3228 while (chain) {
3229 chain_tmp = chain->next;
3230 devm_kfree(&pdev->dev, chain);
3231 chain = chain_tmp;
3232 }
3233}
3234
3235static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3236 struct hns3_enet_ring *ring)
3237{
3238 ring->next = group->ring;
3239 group->ring = ring;
3240
3241 group->count++;
3242}
3243
874bff0b
PL		 3244static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3245{
3246 struct pci_dev *pdev = priv->ae_handle->pdev;
3247 struct hns3_enet_tqp_vector *tqp_vector;
3248 int num_vectors = priv->vector_num;
3249 int numa_node;
3250 int vector_i;
3251
3252 numa_node = dev_to_node(&pdev->dev);
3253
3254 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3255 tqp_vector = &priv->tqp_vector[vector_i];
3256 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3257 &tqp_vector->affinity_mask);
3258 }
3259}
3260
76ad4f0e
S		 3261static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3262{
3263 struct hnae3_ring_chain_node vector_ring_chain;
3264 struct hnae3_handle *h = priv->ae_handle;
3265 struct hns3_enet_tqp_vector *tqp_vector;
76ad4f0e 3266 int ret = 0;
ece4bf46 3267 int i;
76ad4f0e 3268
874bff0b
PL		 3269 hns3_nic_set_cpumask(priv);
3270
dd38c726
YL		 3271 for (i = 0; i < priv->vector_num; i++) {
3272 tqp_vector = &priv->tqp_vector[i];
3273 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3274 tqp_vector->num_tqps = 0;
3275 }
76ad4f0e 3276
dd38c726
YL		 3277 for (i = 0; i < h->kinfo.num_tqps; i++) {
3278 u16 vector_i = i % priv->vector_num;
3279 u16 tqp_num = h->kinfo.num_tqps;
76ad4f0e
S		 3280
3281 tqp_vector = &priv->tqp_vector[vector_i];
3282
3283 hns3_add_ring_to_group(&tqp_vector->tx_group,
3284 priv->ring_data[i].ring);
3285
3286 hns3_add_ring_to_group(&tqp_vector->rx_group,
3287 priv->ring_data[i + tqp_num].ring);
3288
76ad4f0e
S		 3289 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3290 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
dd38c726 3291 tqp_vector->num_tqps++;
76ad4f0e
S		 3292 }
3293
dd38c726 3294 for (i = 0; i < priv->vector_num; i++) {
76ad4f0e
S		 3295 tqp_vector = &priv->tqp_vector[i];
3296
3297 tqp_vector->rx_group.total_bytes = 0;
3298 tqp_vector->rx_group.total_packets = 0;
3299 tqp_vector->tx_group.total_bytes = 0;
3300 tqp_vector->tx_group.total_packets = 0;
76ad4f0e
S		 3301 tqp_vector->handle = h;
3302
3303 ret = hns3_get_vector_ring_chain(tqp_vector,
3304 &vector_ring_chain);
3305 if (ret)
cda69d24 3306 goto map_ring_fail;
76ad4f0e
S		 3307
3308 ret = h->ae_algo->ops->map_ring_to_vector(h,
3309 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3310
3311 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3312
dd38c726 3313 if (ret)
ece4bf46 3314 goto map_ring_fail;
dd38c726 3315
76ad4f0e
S		 3316 netif_napi_add(priv->netdev, &tqp_vector->napi,
3317 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3318 }
3319
dd38c726 3320 return 0;
ece4bf46
HT		 3321
3322map_ring_fail:
3323 while (i--)
3324 netif_napi_del(&priv->tqp_vector[i].napi);
3325
3326 return ret;
dd38c726
YL		 3327}
3328
3329static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3330{
75edb610
JS		 3331#define HNS3_VECTOR_PF_MAX_NUM 64
3332
dd38c726
YL		 3333 struct hnae3_handle *h = priv->ae_handle;
3334 struct hns3_enet_tqp_vector *tqp_vector;
3335 struct hnae3_vector_info *vector;
3336 struct pci_dev *pdev = h->pdev;
3337 u16 tqp_num = h->kinfo.num_tqps;
3338 u16 vector_num;
3339 int ret = 0;
3340 u16 i;
3341
3342 /* RSS size, cpu online and vector_num should be the same */
3343 /* Should consider 2p/4p later */
3344 vector_num = min_t(u16, num_online_cpus(), tqp_num);
75edb610
JS		 3345 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3346
dd38c726
YL		 3347 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3348 GFP_KERNEL);
3349 if (!vector)
3350 return -ENOMEM;
3351
9b2f3477 3352 /* save the actual available vector number */
dd38c726
YL		 3353 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3354
3355 priv->vector_num = vector_num;
3356 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3357 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3358 GFP_KERNEL);
3359 if (!priv->tqp_vector) {
3360 ret = -ENOMEM;
3361 goto out;
3362 }
3363
3364 for (i = 0; i < priv->vector_num; i++) {
3365 tqp_vector = &priv->tqp_vector[i];
3366 tqp_vector->idx = i;
3367 tqp_vector->mask_addr = vector[i].io_addr;
3368 tqp_vector->vector_irq = vector[i].vector;
3369 hns3_vector_gl_rl_init(tqp_vector, priv);
3370 }
3371
76ad4f0e
S		 3372out:
3373 devm_kfree(&pdev->dev, vector);
3374 return ret;
3375}
3376
dd38c726
YL		 3377static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3378{
3379 group->ring = NULL;
3380 group->count = 0;
3381}
3382
e2152785 3383static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
76ad4f0e
S		 3384{
3385 struct hnae3_ring_chain_node vector_ring_chain;
3386 struct hnae3_handle *h = priv->ae_handle;
3387 struct hns3_enet_tqp_vector *tqp_vector;
e2152785 3388 int i;
76ad4f0e
S		 3389
3390 for (i = 0; i < priv->vector_num; i++) {
3391 tqp_vector = &priv->tqp_vector[i];
3392
2c9dd668
HT		 3393 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3394 continue;
3395
e2152785 3396 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain);
76ad4f0e 3397
e2152785 3398 h->ae_algo->ops->unmap_ring_from_vector(h,
76ad4f0e 3399 tqp_vector->vector_irq, &vector_ring_chain);
76ad4f0e
S		 3400
3401 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3402
ae6017a7 3403 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
ae6017a7
HT		 3404 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3405 free_irq(tqp_vector->vector_irq, tqp_vector);
3406 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
76ad4f0e
S		 3407 }
3408
dd38c726
YL		 3409 hns3_clear_ring_group(&tqp_vector->rx_group);
3410 hns3_clear_ring_group(&tqp_vector->tx_group);
76ad4f0e
S		 3411 netif_napi_del(&priv->tqp_vector[i].napi);
3412 }
dd38c726
YL		 3413}
3414
3415static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3416{
3417 struct hnae3_handle *h = priv->ae_handle;
3418 struct pci_dev *pdev = h->pdev;
3419 int i, ret;
3420
3421 for (i = 0; i < priv->vector_num; i++) {
3422 struct hns3_enet_tqp_vector *tqp_vector;
3423
3424 tqp_vector = &priv->tqp_vector[i];
3425 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3426 if (ret)
3427 return ret;
3428 }
76ad4f0e 3429
dd38c726 3430 devm_kfree(&pdev->dev, priv->tqp_vector);
76ad4f0e
S		 3431 return 0;
3432}
3433
3434static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
ebaf1908 3435 unsigned int ring_type)
76ad4f0e
S		 3436{
3437 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3438 int queue_num = priv->ae_handle->kinfo.num_tqps;
3439 struct pci_dev *pdev = priv->ae_handle->pdev;
3440 struct hns3_enet_ring *ring;
c0425944 3441 int desc_num;
76ad4f0e
S		 3442
3443 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3444 if (!ring)
3445 return -ENOMEM;
3446
3447 if (ring_type == HNAE3_RING_TYPE_TX) {
c0425944 3448 desc_num = priv->ae_handle->kinfo.num_tx_desc;
76ad4f0e 3449 ring_data[q->tqp_index].ring = ring;
66b44730 3450 ring_data[q->tqp_index].queue_index = q->tqp_index;
76ad4f0e
S		 3451 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3452 } else {
c0425944 3453 desc_num = priv->ae_handle->kinfo.num_rx_desc;
76ad4f0e 3454 ring_data[q->tqp_index + queue_num].ring = ring;
66b44730 3455 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
76ad4f0e
S		 3456 ring->io_base = q->io_base;
3457 }
3458
e4e87715 3459 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
76ad4f0e 3460
76ad4f0e
S		 3461 ring->tqp = q;
3462 ring->desc = NULL;
3463 ring->desc_cb = NULL;
3464 ring->dev = priv->dev;
3465 ring->desc_dma_addr = 0;
3466 ring->buf_size = q->buf_size;
2c9dd668 3467 ring->desc_num = desc_num;
76ad4f0e
S		 3468 ring->next_to_use = 0;
3469 ring->next_to_clean = 0;
3470
3471 return 0;
3472}
3473
3474static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3475 struct hns3_nic_priv *priv)
3476{
3477 int ret;
3478
3479 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3480 if (ret)
3481 return ret;
3482
3483 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
73b907a0
HT		 3484 if (ret) {
3485 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
76ad4f0e 3486 return ret;
73b907a0 3487 }
76ad4f0e
S		 3488
3489 return 0;
3490}
3491
3492static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3493{
3494 struct hnae3_handle *h = priv->ae_handle;
3495 struct pci_dev *pdev = h->pdev;
3496 int i, ret;
3497
a86854d0
KC		 3498 priv->ring_data = devm_kzalloc(&pdev->dev,
3499 array3_size(h->kinfo.num_tqps,
3500 sizeof(*priv->ring_data),
3501 2),
76ad4f0e
S		 3502 GFP_KERNEL);
3503 if (!priv->ring_data)
3504 return -ENOMEM;
3505
3506 for (i = 0; i < h->kinfo.num_tqps; i++) {
3507 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3508 if (ret)
3509 goto err;
3510 }
3511
3512 return 0;
3513err:
73b907a0
HT		 3514 while (i--) {
3515 devm_kfree(priv->dev, priv->ring_data[i].ring);
3516 devm_kfree(priv->dev,
3517 priv->ring_data[i + h->kinfo.num_tqps].ring);
3518 }
3519
76ad4f0e 3520 devm_kfree(&pdev->dev, priv->ring_data);
7b8f622e 3521 priv->ring_data = NULL;
76ad4f0e
S		 3522 return ret;
3523}
3524
09f2af64
PL		 3525static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3526{
3527 struct hnae3_handle *h = priv->ae_handle;
3528 int i;
3529
7b8f622e
HT		 3530 if (!priv->ring_data)
3531 return;
3532
09f2af64
PL		 3533 for (i = 0; i < h->kinfo.num_tqps; i++) {
3534 devm_kfree(priv->dev, priv->ring_data[i].ring);
3535 devm_kfree(priv->dev,
3536 priv->ring_data[i + h->kinfo.num_tqps].ring);
3537 }
3538 devm_kfree(priv->dev, priv->ring_data);
7b8f622e 3539 priv->ring_data = NULL;
09f2af64
PL		 3540}
3541
76ad4f0e
S		 3542static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3543{
3544 int ret;
3545
3546 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3547 return -EINVAL;
3548
77296bf6
YL		 3549 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3550 sizeof(ring->desc_cb[0]), GFP_KERNEL);
76ad4f0e
S		 3551 if (!ring->desc_cb) {
3552 ret = -ENOMEM;
3553 goto out;
3554 }
3555
3556 ret = hns3_alloc_desc(ring);
3557 if (ret)
3558 goto out_with_desc_cb;
3559
3560 if (!HNAE3_IS_TX_RING(ring)) {
3561 ret = hns3_alloc_ring_buffers(ring);
3562 if (ret)
3563 goto out_with_desc;
3564 }
3565
3566 return 0;
3567
3568out_with_desc:
3569 hns3_free_desc(ring);
3570out_with_desc_cb:
77296bf6 3571 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3572 ring->desc_cb = NULL;
3573out:
3574 return ret;
3575}
3576
3577static void hns3_fini_ring(struct hns3_enet_ring *ring)
3578{
3579 hns3_free_desc(ring);
77296bf6 3580 devm_kfree(ring_to_dev(ring), ring->desc_cb);
76ad4f0e
S		 3581 ring->desc_cb = NULL;
3582 ring->next_to_clean = 0;
3583 ring->next_to_use = 0;
ac574b80
PL		 3584 ring->pending_buf = 0;
3585 if (ring->skb) {
3586 dev_kfree_skb_any(ring->skb);
3587 ring->skb = NULL;
3588 }
76ad4f0e
S		 3589}
3590
1db9b1bf 3591static int hns3_buf_size2type(u32 buf_size)
76ad4f0e
S		 3592{
3593 int bd_size_type;
3594
3595 switch (buf_size) {
3596 case 512:
3597 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3598 break;
3599 case 1024:
3600 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3601 break;
3602 case 2048:
3603 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3604 break;
3605 case 4096:
3606 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3607 break;
3608 default:
3609 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3610 }
3611
3612 return bd_size_type;
3613}
3614
3615static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3616{
3617 dma_addr_t dma = ring->desc_dma_addr;
3618 struct hnae3_queue *q = ring->tqp;
3619
3620 if (!HNAE3_IS_TX_RING(ring)) {
9b2f3477 3621 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
76ad4f0e
S		 3622 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3623 (u32)((dma >> 31) >> 1));
3624
3625 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3626 hns3_buf_size2type(ring->buf_size));
3627 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3628 ring->desc_num / 8 - 1);
3629
3630 } else {
3631 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3632 (u32)dma);
3633 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3634 (u32)((dma >> 31) >> 1));
3635
76ad4f0e
S		 3636 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3637 ring->desc_num / 8 - 1);
3638 }
3639}
3640
1c772154
YL		 3641static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3642{
3643 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3644 int i;
3645
3646 for (i = 0; i < HNAE3_MAX_TC; i++) {
3647 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3648 int j;
3649
3650 if (!tc_info->enable)
3651 continue;
3652
3653 for (j = 0; j < tc_info->tqp_count; j++) {
3654 struct hnae3_queue *q;
3655
3656 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3657 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3658 tc_info->tc);
3659 }
3660 }
3661}
3662
5668abda 3663int hns3_init_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3664{
3665 struct hnae3_handle *h = priv->ae_handle;
3666 int ring_num = h->kinfo.num_tqps * 2;
3667 int i, j;
3668 int ret;
3669
3670 for (i = 0; i < ring_num; i++) {
3671 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3672 if (ret) {
3673 dev_err(priv->dev,
3674 "Alloc ring memory fail! ret=%d\n", ret);
3675 goto out_when_alloc_ring_memory;
3676 }
3677
76ad4f0e
S		 3678 u64_stats_init(&priv->ring_data[i].ring->syncp);
3679 }
3680
3681 return 0;
3682
3683out_when_alloc_ring_memory:
3684 for (j = i - 1; j >= 0; j--)
ee83f776 3685 hns3_fini_ring(priv->ring_data[j].ring);
76ad4f0e
S		 3686
3687 return -ENOMEM;
3688}
3689
5668abda 3690int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
76ad4f0e
S		 3691{
3692 struct hnae3_handle *h = priv->ae_handle;
3693 int i;
3694
3695 for (i = 0; i < h->kinfo.num_tqps; i++) {
76ad4f0e
S		 3696 hns3_fini_ring(priv->ring_data[i].ring);
3697 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3698 }
76ad4f0e
S		 3699 return 0;
3700}
3701
3702/* Set mac addr if it is configured. or leave it to the AE driver */
7fa6be4f 3703static int hns3_init_mac_addr(struct net_device *netdev, bool init)
76ad4f0e
S		 3704{
3705 struct hns3_nic_priv *priv = netdev_priv(netdev);
3706 struct hnae3_handle *h = priv->ae_handle;
3707 u8 mac_addr_temp[ETH_ALEN];
7fa6be4f 3708 int ret = 0;
76ad4f0e 3709
f09555ff 3710 if (h->ae_algo->ops->get_mac_addr && init) {
76ad4f0e
S		 3711 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3712 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3713 }
3714
3715 /* Check if the MAC address is valid, if not get a random one */
3716 if (!is_valid_ether_addr(netdev->dev_addr)) {
3717 eth_hw_addr_random(netdev);
3718 dev_warn(priv->dev, "using random MAC address %pM\n",
3719 netdev->dev_addr);
76ad4f0e 3720 }
139e8792
L		 3721
3722 if (h->ae_algo->ops->set_mac_addr)
7fa6be4f 3723 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
139e8792 3724
7fa6be4f 3725 return ret;
76ad4f0e
S		 3726}
3727
c8a8045b
HT		 3728static int hns3_init_phy(struct net_device *netdev)
3729{
3730 struct hnae3_handle *h = hns3_get_handle(netdev);
3731 int ret = 0;
3732
3733 if (h->ae_algo->ops->mac_connect_phy)
3734 ret = h->ae_algo->ops->mac_connect_phy(h);
3735
3736 return ret;
3737}
3738
3739static void hns3_uninit_phy(struct net_device *netdev)
3740{
3741 struct hnae3_handle *h = hns3_get_handle(netdev);
3742
3743 if (h->ae_algo->ops->mac_disconnect_phy)
3744 h->ae_algo->ops->mac_disconnect_phy(h);
3745}
3746
6871af29
JS		 3747static int hns3_restore_fd_rules(struct net_device *netdev)
3748{
3749 struct hnae3_handle *h = hns3_get_handle(netdev);
3750 int ret = 0;
3751
3752 if (h->ae_algo->ops->restore_fd_rules)
3753 ret = h->ae_algo->ops->restore_fd_rules(h);
3754
3755 return ret;
3756}
3757
3758static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3759{
3760 struct hnae3_handle *h = hns3_get_handle(netdev);
3761
3762 if (h->ae_algo->ops->del_all_fd_entries)
3763 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3764}
3765
a6d818e3
YL		 3766static int hns3_client_start(struct hnae3_handle *handle)
3767{
3768 if (!handle->ae_algo->ops->client_start)
3769 return 0;
3770
3771 return handle->ae_algo->ops->client_start(handle);
3772}
3773
3774static void hns3_client_stop(struct hnae3_handle *handle)
3775{
3776 if (!handle->ae_algo->ops->client_stop)
3777 return;
3778
3779 handle->ae_algo->ops->client_stop(handle);
3780}
3781
bb87be87
YL		 3782static void hns3_info_show(struct hns3_nic_priv *priv)
3783{
3784 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3785
3786 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3787 dev_info(priv->dev, "Task queue pairs numbers: %d\n", kinfo->num_tqps);
3788 dev_info(priv->dev, "RSS size: %d\n", kinfo->rss_size);
3789 dev_info(priv->dev, "Allocated RSS size: %d\n", kinfo->req_rss_size);
3790 dev_info(priv->dev, "RX buffer length: %d\n", kinfo->rx_buf_len);
3791 dev_info(priv->dev, "Desc num per TX queue: %d\n", kinfo->num_tx_desc);
3792 dev_info(priv->dev, "Desc num per RX queue: %d\n", kinfo->num_rx_desc);
3793 dev_info(priv->dev, "Total number of enabled TCs: %d\n", kinfo->num_tc);
3794 dev_info(priv->dev, "Max mtu size: %d\n", priv->netdev->max_mtu);
3795}
3796
76ad4f0e
S		 3797static int hns3_client_init(struct hnae3_handle *handle)
3798{
3799 struct pci_dev *pdev = handle->pdev;
0d43bf45 3800 u16 alloc_tqps, max_rss_size;
76ad4f0e
S		 3801 struct hns3_nic_priv *priv;
3802 struct net_device *netdev;
3803 int ret;
3804
0d43bf45
HT		 3805 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3806 &max_rss_size);
3807 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
76ad4f0e
S		 3808 if (!netdev)
3809 return -ENOMEM;
3810
3811 priv = netdev_priv(netdev);
3812 priv->dev = &pdev->dev;
3813 priv->netdev = netdev;
3814 priv->ae_handle = handle;
f8fa222c 3815 priv->tx_timeout_count = 0;
b7b585c2 3816 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
76ad4f0e 3817
bb87be87
YL		 3818 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3819
76ad4f0e
S		 3820 handle->kinfo.netdev = netdev;
3821 handle->priv = (void *)priv;
3822
f09555ff 3823 hns3_init_mac_addr(netdev, true);
76ad4f0e
S		 3824
3825 hns3_set_default_feature(netdev);
3826
3827 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3828 netdev->priv_flags |= IFF_UNICAST_FLT;
3829 netdev->netdev_ops = &hns3_nic_netdev_ops;
3830 SET_NETDEV_DEV(netdev, &pdev->dev);
3831 hns3_ethtool_set_ops(netdev);
76ad4f0e
S		 3832
3833 /* Carrier off reporting is important to ethtool even BEFORE open */
3834 netif_carrier_off(netdev);
3835
3836 ret = hns3_get_ring_config(priv);
3837 if (ret) {
3838 ret = -ENOMEM;
3839 goto out_get_ring_cfg;
3840 }
3841
dd38c726
YL		 3842 ret = hns3_nic_alloc_vector_data(priv);
3843 if (ret) {
3844 ret = -ENOMEM;
3845 goto out_alloc_vector_data;
3846 }
3847
76ad4f0e
S		 3848 ret = hns3_nic_init_vector_data(priv);
3849 if (ret) {
3850 ret = -ENOMEM;
3851 goto out_init_vector_data;
3852 }
3853
3854 ret = hns3_init_all_ring(priv);
3855 if (ret) {
3856 ret = -ENOMEM;
3857 goto out_init_ring_data;
3858 }
3859
c8a8045b
HT		 3860 ret = hns3_init_phy(netdev);
3861 if (ret)
3862 goto out_init_phy;
3863
76ad4f0e
S		 3864 ret = register_netdev(netdev);
3865 if (ret) {
3866 dev_err(priv->dev, "probe register netdev fail!\n");
3867 goto out_reg_netdev_fail;
3868 }
3869
a6d818e3
YL		 3870 ret = hns3_client_start(handle);
3871 if (ret) {
3872 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
bf6de231 3873 goto out_client_start;
a6d818e3
YL		 3874 }
3875
986743db
YL		 3876 hns3_dcbnl_setup(handle);
3877
b2292360 3878 hns3_dbg_init(handle);
3879
a0b43717 3880 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
e6d7d79d 3881 netdev->max_mtu = HNS3_MAX_MTU;
a8e8b7ff 3882
814da63c
HT		 3883 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3884
bb87be87
YL		 3885 if (netif_msg_drv(handle))
3886 hns3_info_show(priv);
3887
76ad4f0e
S		 3888 return ret;
3889
18655128
HT		 3890out_client_start:
3891 unregister_netdev(netdev);
76ad4f0e 3892out_reg_netdev_fail:
c8a8045b
HT		 3893 hns3_uninit_phy(netdev);
3894out_init_phy:
3895 hns3_uninit_all_ring(priv);
76ad4f0e 3896out_init_ring_data:
e2152785 3897 hns3_nic_uninit_vector_data(priv);
76ad4f0e 3898out_init_vector_data:
dd38c726
YL		 3899 hns3_nic_dealloc_vector_data(priv);
3900out_alloc_vector_data:
3901 priv->ring_data = NULL;
76ad4f0e
S		 3902out_get_ring_cfg:
3903 priv->ae_handle = NULL;
3904 free_netdev(netdev);
3905 return ret;
3906}
3907
3908static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3909{
3910 struct net_device *netdev = handle->kinfo.netdev;
3911 struct hns3_nic_priv *priv = netdev_priv(netdev);
3912 int ret;
3913
f05e2109
JS		 3914 hns3_remove_hw_addr(netdev);
3915
76ad4f0e
S		 3916 if (netdev->reg_state != NETREG_UNINITIALIZED)
3917 unregister_netdev(netdev);
3918
eb32c896
HT		 3919 hns3_client_stop(handle);
3920
0d2f68c7
HT		 3921 hns3_uninit_phy(netdev);
3922
814da63c
HT		 3923 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3924 netdev_warn(netdev, "already uninitialized\n");
3925 goto out_netdev_free;
3926 }
3927
dc5e6064
JS		 3928 hns3_del_all_fd_rules(netdev, true);
3929
f96315f2 3930 hns3_clear_all_ring(handle, true);
7b763f3f 3931
e2152785 3932 hns3_nic_uninit_vector_data(priv);
76ad4f0e 3933
dd38c726
YL		 3934 ret = hns3_nic_dealloc_vector_data(priv);
3935 if (ret)
3936 netdev_err(netdev, "dealloc vector error\n");
3937
76ad4f0e
S		 3938 ret = hns3_uninit_all_ring(priv);
3939 if (ret)
3940 netdev_err(netdev, "uninit ring error\n");
3941
ec777890
YL		 3942 hns3_put_ring_config(priv);
3943
b2292360 3944 hns3_dbg_uninit(handle);
3945
814da63c 3946out_netdev_free:
76ad4f0e
S		 3947 free_netdev(netdev);
3948}
3949
3950static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3951{
3952 struct net_device *netdev = handle->kinfo.netdev;
3953
3954 if (!netdev)
3955 return;
3956
3957 if (linkup) {
3958 netif_carrier_on(netdev);
3959 netif_tx_wake_all_queues(netdev);
bb87be87
YL		 3960 if (netif_msg_link(handle))
3961 netdev_info(netdev, "link up\n");
76ad4f0e
S		 3962 } else {
3963 netif_carrier_off(netdev);
3964 netif_tx_stop_all_queues(netdev);
bb87be87
YL		 3965 if (netif_msg_link(handle))
3966 netdev_info(netdev, "link down\n");
76ad4f0e
S		 3967 }
3968}
3969
9df8f79a
YL		 3970static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3971{
3972 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3973 struct net_device *ndev = kinfo->netdev;
9df8f79a
YL		 3974
3975 if (tc > HNAE3_MAX_TC)
3976 return -EINVAL;
3977
3978 if (!ndev)
3979 return -ENODEV;
3980
a1ef124e 3981 return hns3_nic_set_real_num_queue(ndev);
9df8f79a
YL		 3982}
3983
7fa6be4f 3984static int hns3_recover_hw_addr(struct net_device *ndev)
bb6b94a8
L		 3985{
3986 struct netdev_hw_addr_list *list;
3987 struct netdev_hw_addr *ha, *tmp;
7fa6be4f 3988 int ret = 0;
bb6b94a8 3989
389775a6 3990 netif_addr_lock_bh(ndev);
bb6b94a8
L		 3991 /* go through and sync uc_addr entries to the device */
3992 list = &ndev->uc;
7fa6be4f
HT		 3993 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3994 ret = hns3_nic_uc_sync(ndev, ha->addr);
3995 if (ret)
389775a6 3996 goto out;
7fa6be4f 3997 }
bb6b94a8
L		 3998
3999 /* go through and sync mc_addr entries to the device */
4000 list = &ndev->mc;
7fa6be4f
HT		 4001 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4002 ret = hns3_nic_mc_sync(ndev, ha->addr);
4003 if (ret)
389775a6 4004 goto out;
7fa6be4f
HT		 4005 }
4006
389775a6
JS		 4007out:
4008 netif_addr_unlock_bh(ndev);
7fa6be4f 4009 return ret;
bb6b94a8
L		 4010}
4011
f05e2109
JS		 4012static void hns3_remove_hw_addr(struct net_device *netdev)
4013{
4014 struct netdev_hw_addr_list *list;
4015 struct netdev_hw_addr *ha, *tmp;
4016
4017 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
4018
389775a6 4019 netif_addr_lock_bh(netdev);
f05e2109
JS		 4020 /* go through and unsync uc_addr entries to the device */
4021 list = &netdev->uc;
4022 list_for_each_entry_safe(ha, tmp, &list->list, list)
4023 hns3_nic_uc_unsync(netdev, ha->addr);
4024
4025 /* go through and unsync mc_addr entries to the device */
4026 list = &netdev->mc;
4027 list_for_each_entry_safe(ha, tmp, &list->list, list)
4028 if (ha->refcount > 1)
4029 hns3_nic_mc_unsync(netdev, ha->addr);
389775a6
JS		 4030
4031 netif_addr_unlock_bh(netdev);
f05e2109
JS		 4032}
4033
beebca3a 4034static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
bb6b94a8 4035{
beebca3a 4036 while (ring->next_to_clean != ring->next_to_use) {
7b763f3f 4037 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
beebca3a
YL		 4038 hns3_free_buffer_detach(ring, ring->next_to_clean);
4039 ring_ptr_move_fw(ring, next_to_clean);
4040 }
4041}
4042
7b763f3f
FL		 4043static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4044{
4045 struct hns3_desc_cb res_cbs;
4046 int ret;
4047
4048 while (ring->next_to_use != ring->next_to_clean) {
4049 /* When a buffer is not reused, it's memory has been
4050 * freed in hns3_handle_rx_bd or will be freed by
4051 * stack, so we need to replace the buffer here.
4052 */
4053 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4054 ret = hns3_reserve_buffer_map(ring, &res_cbs);
4055 if (ret) {
4056 u64_stats_update_begin(&ring->syncp);
4057 ring->stats.sw_err_cnt++;
4058 u64_stats_update_end(&ring->syncp);
4059 /* if alloc new buffer fail, exit directly
4060 * and reclear in up flow.
4061 */
4062 netdev_warn(ring->tqp->handle->kinfo.netdev,
4063 "reserve buffer map failed, ret = %d\n",
4064 ret);
4065 return ret;
4066 }
9b2f3477 4067 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
7b763f3f
FL		 4068 }
4069 ring_ptr_move_fw(ring, next_to_use);
4070 }
4071
cc5ff6e9
PL		 4072 /* Free the pending skb in rx ring */
4073 if (ring->skb) {
4074 dev_kfree_skb_any(ring->skb);
4075 ring->skb = NULL;
4076 ring->pending_buf = 0;
4077 }
4078
7b763f3f
FL		 4079 return 0;
4080}
4081
4082static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
beebca3a 4083{
beebca3a
YL		 4084 while (ring->next_to_use != ring->next_to_clean) {
4085 /* When a buffer is not reused, it's memory has been
4086 * freed in hns3_handle_rx_bd or will be freed by
4087 * stack, so only need to unmap the buffer here.
4088 */
4089 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4090 hns3_unmap_buffer(ring,
4091 &ring->desc_cb[ring->next_to_use]);
4092 ring->desc_cb[ring->next_to_use].dma = 0;
4093 }
4094
4095 ring_ptr_move_fw(ring, next_to_use);
4096 }
bb6b94a8
L		 4097}
4098
f96315f2 4099static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
bb6b94a8
L		 4100{
4101 struct net_device *ndev = h->kinfo.netdev;
4102 struct hns3_nic_priv *priv = netdev_priv(ndev);
4103 u32 i;
4104
4105 for (i = 0; i < h->kinfo.num_tqps; i++) {
bb6b94a8
L		 4106 struct hns3_enet_ring *ring;
4107
4108 ring = priv->ring_data[i].ring;
beebca3a 4109 hns3_clear_tx_ring(ring);
bb6b94a8
L		 4110
4111 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
7b763f3f
FL		 4112 /* Continue to clear other rings even if clearing some
4113 * rings failed.
4114 */
f96315f2
HT		 4115 if (force)
4116 hns3_force_clear_rx_ring(ring);
4117 else
4118 hns3_clear_rx_ring(ring);
bb6b94a8
L		 4119 }
4120}
4121
7b763f3f
FL		 4122int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4123{
4124 struct net_device *ndev = h->kinfo.netdev;
4125 struct hns3_nic_priv *priv = netdev_priv(ndev);
4126 struct hns3_enet_ring *rx_ring;
4127 int i, j;
4128 int ret;
4129
4130 for (i = 0; i < h->kinfo.num_tqps; i++) {
7fa6be4f
HT		 4131 ret = h->ae_algo->ops->reset_queue(h, i);
4132 if (ret)
4133 return ret;
4134
7b763f3f
FL		 4135 hns3_init_ring_hw(priv->ring_data[i].ring);
4136
4137 /* We need to clear tx ring here because self test will
4138 * use the ring and will not run down before up
4139 */
4140 hns3_clear_tx_ring(priv->ring_data[i].ring);
4141 priv->ring_data[i].ring->next_to_clean = 0;
4142 priv->ring_data[i].ring->next_to_use = 0;
4143
4144 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
4145 hns3_init_ring_hw(rx_ring);
4146 ret = hns3_clear_rx_ring(rx_ring);
4147 if (ret)
4148 return ret;
4149
4150 /* We can not know the hardware head and tail when this
4151 * function is called in reset flow, so we reuse all desc.
4152 */
4153 for (j = 0; j < rx_ring->desc_num; j++)
4154 hns3_reuse_buffer(rx_ring, j);
4155
4156 rx_ring->next_to_clean = 0;
4157 rx_ring->next_to_use = 0;
4158 }
4159
1c772154
YL		 4160 hns3_init_tx_ring_tc(priv);
4161
7b763f3f
FL		 4162 return 0;
4163}
4164
e4fd7502
HT		 4165static void hns3_store_coal(struct hns3_nic_priv *priv)
4166{
4167 /* ethtool only support setting and querying one coal
4168 * configuation for now, so save the vector 0' coal
4169 * configuation here in order to restore it.
4170 */
4171 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4172 sizeof(struct hns3_enet_coalesce));
4173 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4174 sizeof(struct hns3_enet_coalesce));
4175}
4176
4177static void hns3_restore_coal(struct hns3_nic_priv *priv)
4178{
4179 u16 vector_num = priv->vector_num;
4180 int i;
4181
4182 for (i = 0; i < vector_num; i++) {
4183 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4184 sizeof(struct hns3_enet_coalesce));
4185 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4186 sizeof(struct hns3_enet_coalesce));
4187 }
4188}
4189
bb6b94a8
L		 4190static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4191{
7edff533 4192 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
bb6b94a8
L		 4193 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4194 struct net_device *ndev = kinfo->netdev;
257e4f29
HT		 4195 struct hns3_nic_priv *priv = netdev_priv(ndev);
4196
4197 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4198 return 0;
bb6b94a8 4199
7edff533
HT		 4200 /* it is cumbersome for hardware to pick-and-choose entries for deletion
4201 * from table space. Hence, for function reset software intervention is
4202 * required to delete the entries
4203 */
4204 if (hns3_dev_ongoing_func_reset(ae_dev)) {
4205 hns3_remove_hw_addr(ndev);
4206 hns3_del_all_fd_rules(ndev, false);
4207 }
4208
bb6b94a8 4209 if (!netif_running(ndev))
6b1385cc 4210 return 0;
bb6b94a8
L		 4211
4212 return hns3_nic_net_stop(ndev);
4213}
4214
4215static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4216{
4217 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
257e4f29 4218 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
bb6b94a8
L		 4219 int ret = 0;
4220
e8884027
HT		 4221 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4222
bb6b94a8 4223 if (netif_running(kinfo->netdev)) {
e8884027 4224 ret = hns3_nic_net_open(kinfo->netdev);
bb6b94a8 4225 if (ret) {
e8884027 4226 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
bb6b94a8 4227 netdev_err(kinfo->netdev,
9b2f3477 4228 "net up fail, ret=%d!\n", ret);
bb6b94a8
L		 4229 return ret;
4230 }
bb6b94a8
L		 4231 }
4232
4233 return ret;
4234}
4235
4236static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4237{
4238 struct net_device *netdev = handle->kinfo.netdev;
4239 struct hns3_nic_priv *priv = netdev_priv(netdev);
4240 int ret;
4241
bb6b94a8
L		 4242 /* Carrier off reporting is important to ethtool even BEFORE open */
4243 netif_carrier_off(netdev);
4244
2c9dd668 4245 ret = hns3_get_ring_config(priv);
862d969a
HT		 4246 if (ret)
4247 return ret;
4248
2c9dd668
HT		 4249 ret = hns3_nic_alloc_vector_data(priv);
4250 if (ret)
4251 goto err_put_ring;
4252
e4fd7502
HT		 4253 hns3_restore_coal(priv);
4254
bb6b94a8
L		 4255 ret = hns3_nic_init_vector_data(priv);
4256 if (ret)
862d969a 4257 goto err_dealloc_vector;
bb6b94a8
L		 4258
4259 ret = hns3_init_all_ring(priv);
862d969a
HT		 4260 if (ret)
4261 goto err_uninit_vector;
bb6b94a8 4262
cd513a69
HT		 4263 ret = hns3_client_start(handle);
4264 if (ret) {
4265 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4266 goto err_uninit_ring;
4267 }
4268
814da63c
HT		 4269 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4270
862d969a
HT		 4271 return ret;
4272
cd513a69
HT		 4273err_uninit_ring:
4274 hns3_uninit_all_ring(priv);
862d969a
HT		 4275err_uninit_vector:
4276 hns3_nic_uninit_vector_data(priv);
862d969a
HT		 4277err_dealloc_vector:
4278 hns3_nic_dealloc_vector_data(priv);
2c9dd668
HT		 4279err_put_ring:
4280 hns3_put_ring_config(priv);
862d969a 4281
bb6b94a8
L		 4282 return ret;
4283}
4284
1f609492
YL		 4285static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4286{
4287 struct net_device *netdev = handle->kinfo.netdev;
4288 bool vlan_filter_enable;
4289 int ret;
4290
4291 ret = hns3_init_mac_addr(netdev, false);
4292 if (ret)
4293 return ret;
4294
4295 ret = hns3_recover_hw_addr(netdev);
4296 if (ret)
4297 return ret;
4298
4299 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4300 if (ret)
4301 return ret;
4302
4303 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4304 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4305
b524b38f
JS		 4306 if (handle->ae_algo->ops->restore_vlan_table)
4307 handle->ae_algo->ops->restore_vlan_table(handle);
1f609492
YL		 4308
4309 return hns3_restore_fd_rules(netdev);
4310}
4311
bb6b94a8
L		 4312static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4313{
4314 struct net_device *netdev = handle->kinfo.netdev;
4315 struct hns3_nic_priv *priv = netdev_priv(netdev);
4316 int ret;
4317
1eeb3367 4318 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
814da63c
HT		 4319 netdev_warn(netdev, "already uninitialized\n");
4320 return 0;
4321 }
4322
f96315f2
HT		 4323 hns3_clear_all_ring(handle, true);
4324 hns3_reset_tx_queue(priv->ae_handle);
bb6b94a8 4325
e2152785 4326 hns3_nic_uninit_vector_data(priv);
bb6b94a8 4327
e4fd7502
HT		 4328 hns3_store_coal(priv);
4329
862d969a
HT		 4330 ret = hns3_nic_dealloc_vector_data(priv);
4331 if (ret)
4332 netdev_err(netdev, "dealloc vector error\n");
4333
bb6b94a8
L		 4334 ret = hns3_uninit_all_ring(priv);
4335 if (ret)
4336 netdev_err(netdev, "uninit ring error\n");
4337
2c9dd668 4338 hns3_put_ring_config(priv);
2c9dd668 4339
bb6b94a8
L		 4340 return ret;
4341}
4342
4343static int hns3_reset_notify(struct hnae3_handle *handle,
4344 enum hnae3_reset_notify_type type)
4345{
4346 int ret = 0;
4347
4348 switch (type) {
4349 case HNAE3_UP_CLIENT:
e1586241
SM		 4350 ret = hns3_reset_notify_up_enet(handle);
4351 break;
bb6b94a8
L		 4352 case HNAE3_DOWN_CLIENT:
4353 ret = hns3_reset_notify_down_enet(handle);
4354 break;
4355 case HNAE3_INIT_CLIENT:
4356 ret = hns3_reset_notify_init_enet(handle);
4357 break;
4358 case HNAE3_UNINIT_CLIENT:
4359 ret = hns3_reset_notify_uninit_enet(handle);
4360 break;
1f609492
YL		 4361 case HNAE3_RESTORE_CLIENT:
4362 ret = hns3_reset_notify_restore_enet(handle);
4363 break;
bb6b94a8
L		 4364 default:
4365 break;
4366 }
4367
4368 return ret;
4369}
4370
09f2af64
PL		 4371int hns3_set_channels(struct net_device *netdev,
4372 struct ethtool_channels *ch)
4373{
09f2af64
PL		 4374 struct hnae3_handle *h = hns3_get_handle(netdev);
4375 struct hnae3_knic_private_info *kinfo = &h->kinfo;
90c68a41 4376 bool rxfh_configured = netif_is_rxfh_configured(netdev);
09f2af64
PL		 4377 u32 new_tqp_num = ch->combined_count;
4378 u16 org_tqp_num;
4379 int ret;
4380
4381 if (ch->rx_count || ch->tx_count)
4382 return -EINVAL;
4383
678335a1 4384 if (new_tqp_num > hns3_get_max_available_channels(h) ||
c78b5b6c 4385 new_tqp_num < 1) {
09f2af64 4386 dev_err(&netdev->dev,
c78b5b6c 4387 "Change tqps fail, the tqp range is from 1 to %d",
678335a1 4388 hns3_get_max_available_channels(h));
09f2af64
PL		 4389 return -EINVAL;
4390 }
4391
c78b5b6c 4392 if (kinfo->rss_size == new_tqp_num)
09f2af64
PL		 4393 return 0;
4394
65749f73
HT		 4395 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4396 if (ret)
4397 return ret;
dd38c726 4398
65749f73
HT		 4399 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4400 if (ret)
4401 return ret;
09f2af64
PL		 4402
4403 org_tqp_num = h->kinfo.num_tqps;
90c68a41 4404 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured);
09f2af64 4405 if (ret) {
90c68a41
YL		 4406 ret = h->ae_algo->ops->set_channels(h, org_tqp_num,
4407 rxfh_configured);
09f2af64
PL		 4408 if (ret) {
4409 /* If revert to old tqp failed, fatal error occurred */
4410 dev_err(&netdev->dev,
4411 "Revert to old tqp num fail, ret=%d", ret);
4412 return ret;
4413 }
4414 dev_info(&netdev->dev,
4415 "Change tqp num fail, Revert to old tqp num");
4416 }
65749f73
HT		 4417 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT);
4418 if (ret)
4419 return ret;
09f2af64 4420
65749f73 4421 return hns3_reset_notify(h, HNAE3_UP_CLIENT);
09f2af64
PL		 4422}
4423
1db9b1bf 4424static const struct hnae3_client_ops client_ops = {
76ad4f0e
S		 4425 .init_instance = hns3_client_init,
4426 .uninit_instance = hns3_client_uninit,
4427 .link_status_change = hns3_link_status_change,
9df8f79a 4428 .setup_tc = hns3_client_setup_tc,
bb6b94a8 4429 .reset_notify = hns3_reset_notify,
76ad4f0e
S		 4430};
4431
4432/* hns3_init_module - Driver registration routine
4433 * hns3_init_module is the first routine called when the driver is
4434 * loaded. All it does is register with the PCI subsystem.
4435 */
4436static int __init hns3_init_module(void)
4437{
4438 int ret;
4439
4440 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4441 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4442
4443 client.type = HNAE3_CLIENT_KNIC;
4444 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4445 hns3_driver_name);
4446
4447 client.ops = &client_ops;
4448
13562d1f
XW		 4449 INIT_LIST_HEAD(&client.node);
4450
b2292360 4451 hns3_dbg_register_debugfs(hns3_driver_name);
4452
76ad4f0e
S		 4453 ret = hnae3_register_client(&client);
4454 if (ret)
b2292360 4455 goto err_reg_client;
76ad4f0e
S		 4456
4457 ret = pci_register_driver(&hns3_driver);
4458 if (ret)
b2292360 4459 goto err_reg_driver;
76ad4f0e
S		 4460
4461 return ret;
b2292360 4462
4463err_reg_driver:
4464 hnae3_unregister_client(&client);
4465err_reg_client:
4466 hns3_dbg_unregister_debugfs();
4467 return ret;
76ad4f0e
S		 4468}
4469module_init(hns3_init_module);
4470
4471/* hns3_exit_module - Driver exit cleanup routine
4472 * hns3_exit_module is called just before the driver is removed
4473 * from memory.
4474 */
4475static void __exit hns3_exit_module(void)
4476{
4477 pci_unregister_driver(&hns3_driver);
4478 hnae3_unregister_client(&client);
b2292360 4479 hns3_dbg_unregister_debugfs();
76ad4f0e
S		 4480}
4481module_exit(hns3_exit_module);
4482
4483MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4484MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4485MODULE_LICENSE("GPL");
4486MODULE_ALIAS("pci:hns-nic");
3c7624d8 4487MODULE_VERSION(HNS3_MOD_VERSION);
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