[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3_enet.h

// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2016-2017 Hisilicon Limited.

#ifndef __HNS3_ENET_H
#define __HNS3_ENET_H

#include <linux/if_vlan.h>

#include "hnae3.h"

#define HNS3_MOD_VERSION "1.0"

extern const char hns3_driver_version[];

enum hns3_nic_state {
	HNS3_NIC_STATE_TESTING,
	HNS3_NIC_STATE_RESETTING,
	HNS3_NIC_STATE_REINITING,
	HNS3_NIC_STATE_DOWN,
	HNS3_NIC_STATE_DISABLED,
	HNS3_NIC_STATE_REMOVING,
	HNS3_NIC_STATE_SERVICE_INITED,
	HNS3_NIC_STATE_SERVICE_SCHED,
	HNS3_NIC_STATE2_RESET_REQUESTED,
	HNS3_NIC_STATE_MAX
};

#define HNS3_RING_RX_RING_BASEADDR_L_REG	0x00000
#define HNS3_RING_RX_RING_BASEADDR_H_REG	0x00004
#define HNS3_RING_RX_RING_BD_NUM_REG		0x00008
#define HNS3_RING_RX_RING_BD_LEN_REG		0x0000C
#define HNS3_RING_RX_RING_TAIL_REG		0x00018
#define HNS3_RING_RX_RING_HEAD_REG		0x0001C
#define HNS3_RING_RX_RING_FBDNUM_REG		0x00020
#define HNS3_RING_RX_RING_PKTNUM_RECORD_REG	0x0002C

#define HNS3_RING_TX_RING_BASEADDR_L_REG	0x00040
#define HNS3_RING_TX_RING_BASEADDR_H_REG	0x00044
#define HNS3_RING_TX_RING_BD_NUM_REG		0x00048
#define HNS3_RING_TX_RING_TC_REG		0x00050
#define HNS3_RING_TX_RING_TAIL_REG		0x00058
#define HNS3_RING_TX_RING_HEAD_REG		0x0005C
#define HNS3_RING_TX_RING_FBDNUM_REG		0x00060
#define HNS3_RING_TX_RING_OFFSET_REG		0x00064
#define HNS3_RING_TX_RING_PKTNUM_RECORD_REG	0x0006C

#define HNS3_RING_PREFETCH_EN_REG		0x0007C
#define HNS3_RING_CFG_VF_NUM_REG		0x00080
#define HNS3_RING_ASID_REG			0x0008C
#define HNS3_RING_RX_VM_REG			0x00090
#define HNS3_RING_T0_BE_RST			0x00094
#define HNS3_RING_COULD_BE_RST			0x00098
#define HNS3_RING_WRR_WEIGHT_REG		0x0009c

#define HNS3_RING_INTMSK_RXWL_REG		0x000A0
#define HNS3_RING_INTSTS_RX_RING_REG		0x000A4
#define HNS3_RX_RING_INT_STS_REG		0x000A8
#define HNS3_RING_INTMSK_TXWL_REG		0x000AC
#define HNS3_RING_INTSTS_TX_RING_REG		0x000B0
#define HNS3_TX_RING_INT_STS_REG		0x000B4
#define HNS3_RING_INTMSK_RX_OVERTIME_REG	0x000B8
#define HNS3_RING_INTSTS_RX_OVERTIME_REG	0x000BC
#define HNS3_RING_INTMSK_TX_OVERTIME_REG	0x000C4
#define HNS3_RING_INTSTS_TX_OVERTIME_REG	0x000C8

#define HNS3_RING_MB_CTRL_REG			0x00100
#define HNS3_RING_MB_DATA_BASE_REG		0x00200

#define HNS3_TX_REG_OFFSET			0x40

#define HNS3_RX_HEAD_SIZE			256

#define HNS3_TX_TIMEOUT (5 * HZ)
#define HNS3_RING_NAME_LEN			16
#define HNS3_BUFFER_SIZE_2048			2048
#define HNS3_RING_MAX_PENDING			32768
#define HNS3_RING_MIN_PENDING			8
#define HNS3_RING_BD_MULTIPLE			8
#define HNS3_MAX_MTU				9728

#define HNS3_BD_SIZE_512_TYPE			0
#define HNS3_BD_SIZE_1024_TYPE			1
#define HNS3_BD_SIZE_2048_TYPE			2
#define HNS3_BD_SIZE_4096_TYPE			3

#define HNS3_RX_FLAG_VLAN_PRESENT		0x1
#define HNS3_RX_FLAG_L3ID_IPV4			0x0
#define HNS3_RX_FLAG_L3ID_IPV6			0x1
#define HNS3_RX_FLAG_L4ID_UDP			0x0
#define HNS3_RX_FLAG_L4ID_TCP			0x1

#define HNS3_RXD_DMAC_S				0
#define HNS3_RXD_DMAC_M				(0x3 << HNS3_RXD_DMAC_S)
#define HNS3_RXD_VLAN_S				2
#define HNS3_RXD_VLAN_M				(0x3 << HNS3_RXD_VLAN_S)
#define HNS3_RXD_L3ID_S				4
#define HNS3_RXD_L3ID_M				(0xf << HNS3_RXD_L3ID_S)
#define HNS3_RXD_L4ID_S				8
#define HNS3_RXD_L4ID_M				(0xf << HNS3_RXD_L4ID_S)
#define HNS3_RXD_FRAG_B				12
#define HNS3_RXD_STRP_TAGP_S			13
#define HNS3_RXD_STRP_TAGP_M			(0x3 << HNS3_RXD_STRP_TAGP_S)

#define HNS3_RXD_L2E_B				16
#define HNS3_RXD_L3E_B				17
#define HNS3_RXD_L4E_B				18
#define HNS3_RXD_TRUNCAT_B			19
#define HNS3_RXD_HOI_B				20
#define HNS3_RXD_DOI_B				21
#define HNS3_RXD_OL3E_B				22
#define HNS3_RXD_OL4E_B				23

#define HNS3_RXD_ODMAC_S			0
#define HNS3_RXD_ODMAC_M			(0x3 << HNS3_RXD_ODMAC_S)
#define HNS3_RXD_OVLAN_S			2
#define HNS3_RXD_OVLAN_M			(0x3 << HNS3_RXD_OVLAN_S)
#define HNS3_RXD_OL3ID_S			4
#define HNS3_RXD_OL3ID_M			(0xf << HNS3_RXD_OL3ID_S)
#define HNS3_RXD_OL4ID_S			8
#define HNS3_RXD_OL4ID_M			(0xf << HNS3_RXD_OL4ID_S)
#define HNS3_RXD_FBHI_S				12
#define HNS3_RXD_FBHI_M				(0x3 << HNS3_RXD_FBHI_S)
#define HNS3_RXD_FBLI_S				14
#define HNS3_RXD_FBLI_M				(0x3 << HNS3_RXD_FBLI_S)

#define HNS3_RXD_BDTYPE_S			0
#define HNS3_RXD_BDTYPE_M			(0xf << HNS3_RXD_BDTYPE_S)
#define HNS3_RXD_VLD_B				4
#define HNS3_RXD_UDP0_B				5
#define HNS3_RXD_EXTEND_B			7
#define HNS3_RXD_FE_B				8
#define HNS3_RXD_LUM_B				9
#define HNS3_RXD_CRCP_B				10
#define HNS3_RXD_L3L4P_B			11
#define HNS3_RXD_TSIND_S			12
#define HNS3_RXD_TSIND_M			(0x7 << HNS3_RXD_TSIND_S)
#define HNS3_RXD_LKBK_B				15
#define HNS3_RXD_HDL_S				16
#define HNS3_RXD_HDL_M				(0x7ff << HNS3_RXD_HDL_S)
#define HNS3_RXD_HSIND_B			31

#define HNS3_TXD_L3T_S				0
#define HNS3_TXD_L3T_M				(0x3 << HNS3_TXD_L3T_S)
#define HNS3_TXD_L4T_S				2
#define HNS3_TXD_L4T_M				(0x3 << HNS3_TXD_L4T_S)
#define HNS3_TXD_L3CS_B				4
#define HNS3_TXD_L4CS_B				5
#define HNS3_TXD_VLAN_B				6
#define HNS3_TXD_TSO_B				7

#define HNS3_TXD_L2LEN_S			8
#define HNS3_TXD_L2LEN_M			(0xff << HNS3_TXD_L2LEN_S)
#define HNS3_TXD_L3LEN_S			16
#define HNS3_TXD_L3LEN_M			(0xff << HNS3_TXD_L3LEN_S)
#define HNS3_TXD_L4LEN_S			24
#define HNS3_TXD_L4LEN_M			(0xff << HNS3_TXD_L4LEN_S)

#define HNS3_TXD_OL3T_S				0
#define HNS3_TXD_OL3T_M				(0x3 << HNS3_TXD_OL3T_S)
#define HNS3_TXD_OVLAN_B			2
#define HNS3_TXD_MACSEC_B			3
#define HNS3_TXD_TUNTYPE_S			4
#define HNS3_TXD_TUNTYPE_M			(0xf << HNS3_TXD_TUNTYPE_S)

#define HNS3_TXD_BDTYPE_S			0
#define HNS3_TXD_BDTYPE_M			(0xf << HNS3_TXD_BDTYPE_S)
#define HNS3_TXD_FE_B				4
#define HNS3_TXD_SC_S				5
#define HNS3_TXD_SC_M				(0x3 << HNS3_TXD_SC_S)
#define HNS3_TXD_EXTEND_B			7
#define HNS3_TXD_VLD_B				8
#define HNS3_TXD_RI_B				9
#define HNS3_TXD_RA_B				10
#define HNS3_TXD_TSYN_B				11
#define HNS3_TXD_DECTTL_S			12
#define HNS3_TXD_DECTTL_M			(0xf << HNS3_TXD_DECTTL_S)

#define HNS3_TXD_MSS_S				0
#define HNS3_TXD_MSS_M				(0x3fff << HNS3_TXD_MSS_S)

#define HNS3_VECTOR_TX_IRQ			BIT_ULL(0)
#define HNS3_VECTOR_RX_IRQ			BIT_ULL(1)

#define HNS3_VECTOR_NOT_INITED			0
#define HNS3_VECTOR_INITED			1

#define HNS3_MAX_BD_SIZE			65535
#define HNS3_MAX_BD_PER_FRAG			8
#define HNS3_MAX_BD_PER_PKT			MAX_SKB_FRAGS

#define HNS3_VECTOR_GL0_OFFSET			0x100
#define HNS3_VECTOR_GL1_OFFSET			0x200
#define HNS3_VECTOR_GL2_OFFSET			0x300
#define HNS3_VECTOR_RL_OFFSET			0x900
#define HNS3_VECTOR_RL_EN_B			6

enum hns3_pkt_l3t_type {
	HNS3_L3T_NONE,
	HNS3_L3T_IPV6,
	HNS3_L3T_IPV4,
	HNS3_L3T_RESERVED
};

enum hns3_pkt_l4t_type {
	HNS3_L4T_UNKNOWN,
	HNS3_L4T_TCP,
	HNS3_L4T_UDP,
	HNS3_L4T_SCTP
};

enum hns3_pkt_ol3t_type {
	HNS3_OL3T_NONE,
	HNS3_OL3T_IPV6,
	HNS3_OL3T_IPV4_NO_CSUM,
	HNS3_OL3T_IPV4_CSUM
};

enum hns3_pkt_tun_type {
	HNS3_TUN_NONE,
	HNS3_TUN_MAC_IN_UDP,
	HNS3_TUN_NVGRE,
	HNS3_TUN_OTHER
};

/* hardware spec ring buffer format */
struct __packed hns3_desc {
	__le64 addr;
	union {
		struct {
			__le16 vlan_tag;
			__le16 send_size;
			union {
				__le32 type_cs_vlan_tso_len;
				struct {
					__u8 type_cs_vlan_tso;
					__u8 l2_len;
					__u8 l3_len;
					__u8 l4_len;
				};
			};
			__le16 outer_vlan_tag;
			__le16 tv;

		union {
			__le32 ol_type_vlan_len_msec;
			struct {
				__u8 ol_type_vlan_msec;
				__u8 ol2_len;
				__u8 ol3_len;
				__u8 ol4_len;
			};
		};

			__le32 paylen;
			__le16 bdtp_fe_sc_vld_ra_ri;
			__le16 mss;
		} tx;

		struct {
			__le32 l234_info;
			__le16 pkt_len;
			__le16 size;

			__le32 rss_hash;
			__le16 fd_id;
			__le16 vlan_tag;

			union {
				__le32 ol_info;
				struct {
					__le16 o_dm_vlan_id_fb;
					__le16 ot_vlan_tag;
				};
			};

			__le32 bd_base_info;
		} rx;
	};
};

struct hns3_desc_cb {
	dma_addr_t dma; /* dma address of this desc */
	void *buf;      /* cpu addr for a desc */

	/* priv data for the desc, e.g. skb when use with ip stack*/
	void *priv;
	u32 page_offset;
	u32 length;     /* length of the buffer */

	u16 reuse_flag;

       /* desc type, used by the ring user to mark the type of the priv data */
	u16 type;
};

enum hns3_pkt_l3type {
	HNS3_L3_TYPE_IPV4,
	HNS3_L3_TYPE_IPV6,
	HNS3_L3_TYPE_ARP,
	HNS3_L3_TYPE_RARP,
	HNS3_L3_TYPE_IPV4_OPT,
	HNS3_L3_TYPE_IPV6_EXT,
	HNS3_L3_TYPE_LLDP,
	HNS3_L3_TYPE_BPDU,
	HNS3_L3_TYPE_MAC_PAUSE,
	HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/

	/* reserved for 0xA~0xB*/

	HNS3_L3_TYPE_CNM = 0xc,

	/* reserved for 0xD~0xE*/

	HNS3_L3_TYPE_PARSE_FAIL	= 0xf /* must be last */
};

enum hns3_pkt_l4type {
	HNS3_L4_TYPE_UDP,
	HNS3_L4_TYPE_TCP,
	HNS3_L4_TYPE_GRE,
	HNS3_L4_TYPE_SCTP,
	HNS3_L4_TYPE_IGMP,
	HNS3_L4_TYPE_ICMP,

	/* reserved for 0x6~0xE */

	HNS3_L4_TYPE_PARSE_FAIL	= 0xf /* must be last */
};

enum hns3_pkt_ol3type {
	HNS3_OL3_TYPE_IPV4 = 0,
	HNS3_OL3_TYPE_IPV6,
	/* reserved for 0x2~0x3 */
	HNS3_OL3_TYPE_IPV4_OPT = 4,
	HNS3_OL3_TYPE_IPV6_EXT,

	/* reserved for 0x6~0xE*/

	HNS3_OL3_TYPE_PARSE_FAIL = 0xf	/* must be last */
};

enum hns3_pkt_ol4type {
	HNS3_OL4_TYPE_NO_TUN,
	HNS3_OL4_TYPE_MAC_IN_UDP,
	HNS3_OL4_TYPE_NVGRE,
	HNS3_OL4_TYPE_UNKNOWN
};

struct ring_stats {
	u64 io_err_cnt;
	u64 sw_err_cnt;
	u64 seg_pkt_cnt;
	union {
		struct {
			u64 tx_pkts;
			u64 tx_bytes;
			u64 tx_err_cnt;
			u64 restart_queue;
			u64 tx_busy;
		};
		struct {
			u64 rx_pkts;
			u64 rx_bytes;
			u64 rx_err_cnt;
			u64 reuse_pg_cnt;
			u64 err_pkt_len;
			u64 non_vld_descs;
			u64 err_bd_num;
			u64 l2_err;
			u64 l3l4_csum_err;
		};
	};
};

struct hns3_enet_ring {
	u8 __iomem *io_base; /* base io address for the ring */
	struct hns3_desc *desc; /* dma map address space */
	struct hns3_desc_cb *desc_cb;
	struct hns3_enet_ring *next;
	struct hns3_enet_tqp_vector *tqp_vector;
	struct hnae3_queue *tqp;
	char ring_name[HNS3_RING_NAME_LEN];
	struct device *dev; /* will be used for DMA mapping of descriptors */

	/* statistic */
	struct ring_stats stats;
	struct u64_stats_sync syncp;

	dma_addr_t desc_dma_addr;
	u32 buf_size;       /* size for hnae_desc->addr, preset by AE */
	u16 desc_num;       /* total number of desc */
	u16 max_desc_num_per_pkt;
	u16 max_raw_data_sz_per_desc;
	u16 max_pkt_size;
	int next_to_use;    /* idx of next spare desc */

	/* idx of lastest sent desc, the ring is empty when equal to
	 * next_to_use
	 */
	int next_to_clean;

	u32 flag;          /* ring attribute */
	int irq_init_flag;

	int numa_node;
	cpumask_t affinity_mask;
};

struct hns_queue;

struct hns3_nic_ring_data {
	struct hns3_enet_ring *ring;
	struct napi_struct napi;
	int queue_index;
	int (*poll_one)(struct hns3_nic_ring_data *, int, void *);
	void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *);
	void (*fini_process)(struct hns3_nic_ring_data *);
};

struct hns3_nic_ops {
	int (*fill_desc)(struct hns3_enet_ring *ring, void *priv,
			 int size, dma_addr_t dma, int frag_end,
			 enum hns_desc_type type);
	int (*maybe_stop_tx)(struct sk_buff **out_skb,
			     int *bnum, struct hns3_enet_ring *ring);
	void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum);
};

enum hns3_flow_level_range {
	HNS3_FLOW_LOW = 0,
	HNS3_FLOW_MID = 1,
	HNS3_FLOW_HIGH = 2,
	HNS3_FLOW_ULTRA = 3,
};

enum hns3_link_mode_bits {
	HNS3_LM_FIBRE_BIT = BIT(0),
	HNS3_LM_AUTONEG_BIT = BIT(1),
	HNS3_LM_TP_BIT = BIT(2),
	HNS3_LM_PAUSE_BIT = BIT(3),
	HNS3_LM_BACKPLANE_BIT = BIT(4),
	HNS3_LM_10BASET_HALF_BIT = BIT(5),
	HNS3_LM_10BASET_FULL_BIT = BIT(6),
	HNS3_LM_100BASET_HALF_BIT = BIT(7),
	HNS3_LM_100BASET_FULL_BIT = BIT(8),
	HNS3_LM_1000BASET_FULL_BIT = BIT(9),
	HNS3_LM_10000BASEKR_FULL_BIT = BIT(10),
	HNS3_LM_25000BASEKR_FULL_BIT = BIT(11),
	HNS3_LM_40000BASELR4_FULL_BIT = BIT(12),
	HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13),
	HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14),
	HNS3_LM_COUNT = 15
};

#define HNS3_INT_GL_MAX			0x1FE0
#define HNS3_INT_GL_50K			0x0014
#define HNS3_INT_GL_20K			0x0032
#define HNS3_INT_GL_18K			0x0036
#define HNS3_INT_GL_8K			0x007C

#define HNS3_INT_RL_MAX			0x00EC
#define HNS3_INT_RL_ENABLE_MASK		0x40

#define HNS3_INT_ADAPT_DOWN_START	100

struct hns3_enet_coalesce {
	u16 int_gl;
	u8 gl_adapt_enable;
	enum hns3_flow_level_range flow_level;
};

struct hns3_enet_ring_group {
	/* array of pointers to rings */
	struct hns3_enet_ring *ring;
	u64 total_bytes;	/* total bytes processed this group */
	u64 total_packets;	/* total packets processed this group */
	u16 count;
	struct hns3_enet_coalesce coal;
};

struct hns3_enet_tqp_vector {
	struct hnae3_handle *handle;
	u8 __iomem *mask_addr;
	int vector_irq;
	int irq_init_flag;

	u16 idx;		/* index in the TQP vector array per handle. */

	struct napi_struct napi;

	struct hns3_enet_ring_group rx_group;
	struct hns3_enet_ring_group tx_group;

	u16 num_tqps;	/* total number of tqps in TQP vector */

	char name[HNAE3_INT_NAME_LEN];

	/* when 0 should adjust interrupt coalesce parameter */
	u8 int_adapt_down;
	unsigned long last_jiffies;
} ____cacheline_internodealigned_in_smp;

enum hns3_udp_tnl_type {
	HNS3_UDP_TNL_VXLAN,
	HNS3_UDP_TNL_GENEVE,
	HNS3_UDP_TNL_MAX,
};

struct hns3_udp_tunnel {
	u16 dst_port;
	int used;
};

struct hns3_nic_priv {
	struct hnae3_handle *ae_handle;
	u32 enet_ver;
	u32 port_id;
	struct net_device *netdev;
	struct device *dev;
	struct hns3_nic_ops ops;

	/**
	 * the cb for nic to manage the ring buffer, the first half of the
	 * array is for tx_ring and vice versa for the second half
	 */
	struct hns3_nic_ring_data *ring_data;
	struct hns3_enet_tqp_vector *tqp_vector;
	u16 vector_num;

	/* The most recently read link state */
	int link;
	u64 tx_timeout_count;

	unsigned long state;

	struct timer_list service_timer;

	struct work_struct service_task;

	struct notifier_block notifier_block;
	/* Vxlan/Geneve information */
	struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
};

union l3_hdr_info {
	struct iphdr *v4;
	struct ipv6hdr *v6;
	unsigned char *hdr;
};

union l4_hdr_info {
	struct tcphdr *tcp;
	struct udphdr *udp;
	unsigned char *hdr;
};

/* the distance between [begin, end) in a ring buffer
 * note: there is a unuse slot between the begin and the end
 */
static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end)
{
	return (end - begin + ring->desc_num) % ring->desc_num;
}

static inline int ring_space(struct hns3_enet_ring *ring)
{
	return ring->desc_num -
		ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1;
}

static inline int is_ring_empty(struct hns3_enet_ring *ring)
{
	return ring->next_to_use == ring->next_to_clean;
}

static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
{
	u8 __iomem *reg_addr = READ_ONCE(base);

	writel(value, reg_addr + reg);
}

#define hns3_write_dev(a, reg, value) \
	hns3_write_reg((a)->io_base, (reg), (value))

#define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
		(tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)

#define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev)

#define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
	DMA_TO_DEVICE : DMA_FROM_DEVICE)

#define tx_ring_data(priv, idx) ((priv)->ring_data[idx])

#define hnae3_buf_size(_ring) ((_ring)->buf_size)
#define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring)))
#define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring))

/* iterator for handling rings in ring group */
#define hns3_for_each_ring(pos, head) \
	for (pos = (head).ring; pos; pos = pos->next)

#define hns3_get_handle(ndev) \
	(((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)

#define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
#define hns3_gl_round_down(int_gl) round_down(int_gl, 2)

#define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
#define hns3_rl_round_down(int_rl) round_down(int_rl, 4)

void hns3_ethtool_set_ops(struct net_device *netdev);
int hns3_set_channels(struct net_device *netdev,
		      struct ethtool_channels *ch);

bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget);
int hns3_init_all_ring(struct hns3_nic_priv *priv);
int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
int hns3_nic_reset_all_ring(struct hnae3_handle *h);
netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
int hns3_clean_rx_ring(
		struct hns3_enet_ring *ring, int budget,
		void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));

void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
				    u32 gl_value);
void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
				    u32 gl_value);
void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
				 u32 rl_value);

#ifdef CONFIG_HNS3_DCB
void hns3_dcbnl_setup(struct hnae3_handle *handle);
#else
static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
#endif

#endif
Commit	Line	Data
d71d8381 JS	1	// SPDX-License-Identifier: GPL-2.0+
d71d8381 JS	2	// Copyright (c) 2016-2017 Hisilicon Limited.
76ad4f0e S	3
	4	#ifndef __HNS3_ENET_H
	5	#define __HNS3_ENET_H
	6
681ec399 YL	7	#include <linux/if_vlan.h>
681ec399 YL	8
76ad4f0e S	9	#include "hnae3.h"
76ad4f0e S	10
3c7624d8 XW	11	#define HNS3_MOD_VERSION "1.0"
3c7624d8 XW	12
76ad4f0e S	13	extern const char hns3_driver_version[];
	14
	15	enum hns3_nic_state {
	16	HNS3_NIC_STATE_TESTING,
	17	HNS3_NIC_STATE_RESETTING,
	18	HNS3_NIC_STATE_REINITING,
	19	HNS3_NIC_STATE_DOWN,
	20	HNS3_NIC_STATE_DISABLED,
	21	HNS3_NIC_STATE_REMOVING,
	22	HNS3_NIC_STATE_SERVICE_INITED,
	23	HNS3_NIC_STATE_SERVICE_SCHED,
	24	HNS3_NIC_STATE2_RESET_REQUESTED,
	25	HNS3_NIC_STATE_MAX
	26	};
	27
	28	#define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
	29	#define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
	30	#define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
	31	#define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
	32	#define HNS3_RING_RX_RING_TAIL_REG 0x00018
	33	#define HNS3_RING_RX_RING_HEAD_REG 0x0001C
	34	#define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
	35	#define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
	36
	37	#define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
	38	#define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
	39	#define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
1c772154	40	#define HNS3_RING_TX_RING_TC_REG 0x00050
76ad4f0e S	41	#define HNS3_RING_TX_RING_TAIL_REG 0x00058
	42	#define HNS3_RING_TX_RING_HEAD_REG 0x0005C
	43	#define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
	44	#define HNS3_RING_TX_RING_OFFSET_REG 0x00064
	45	#define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
	46
	47	#define HNS3_RING_PREFETCH_EN_REG 0x0007C
	48	#define HNS3_RING_CFG_VF_NUM_REG 0x00080
	49	#define HNS3_RING_ASID_REG 0x0008C
	50	#define HNS3_RING_RX_VM_REG 0x00090
	51	#define HNS3_RING_T0_BE_RST 0x00094
	52	#define HNS3_RING_COULD_BE_RST 0x00098
	53	#define HNS3_RING_WRR_WEIGHT_REG 0x0009c
	54
	55	#define HNS3_RING_INTMSK_RXWL_REG 0x000A0
	56	#define HNS3_RING_INTSTS_RX_RING_REG 0x000A4
	57	#define HNS3_RX_RING_INT_STS_REG 0x000A8
	58	#define HNS3_RING_INTMSK_TXWL_REG 0x000AC
	59	#define HNS3_RING_INTSTS_TX_RING_REG 0x000B0
	60	#define HNS3_TX_RING_INT_STS_REG 0x000B4
	61	#define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8
	62	#define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC
	63	#define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4
	64	#define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8
	65
	66	#define HNS3_RING_MB_CTRL_REG 0x00100
	67	#define HNS3_RING_MB_DATA_BASE_REG 0x00200
	68
	69	#define HNS3_TX_REG_OFFSET 0x40
	70
	71	#define HNS3_RX_HEAD_SIZE 256
	72
	73	#define HNS3_TX_TIMEOUT (5 * HZ)
	74	#define HNS3_RING_NAME_LEN 16
	75	#define HNS3_BUFFER_SIZE_2048 2048
	76	#define HNS3_RING_MAX_PENDING 32768
5668abda L	77	#define HNS3_RING_MIN_PENDING 8
5668abda L	78	#define HNS3_RING_BD_MULTIPLE 8
a8e8b7ff	79	#define HNS3_MAX_MTU 9728
76ad4f0e S	80
	81	#define HNS3_BD_SIZE_512_TYPE 0
	82	#define HNS3_BD_SIZE_1024_TYPE 1
	83	#define HNS3_BD_SIZE_2048_TYPE 2
	84	#define HNS3_BD_SIZE_4096_TYPE 3
	85
	86	#define HNS3_RX_FLAG_VLAN_PRESENT 0x1
	87	#define HNS3_RX_FLAG_L3ID_IPV4 0x0
	88	#define HNS3_RX_FLAG_L3ID_IPV6 0x1
	89	#define HNS3_RX_FLAG_L4ID_UDP 0x0
	90	#define HNS3_RX_FLAG_L4ID_TCP 0x1
	91
	92	#define HNS3_RXD_DMAC_S 0
	93	#define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
	94	#define HNS3_RXD_VLAN_S 2
	95	#define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
	96	#define HNS3_RXD_L3ID_S 4
	97	#define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
	98	#define HNS3_RXD_L4ID_S 8
	99	#define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
	100	#define HNS3_RXD_FRAG_B 12
5b5455a9 PL	101	#define HNS3_RXD_STRP_TAGP_S 13
	102	#define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
	103
76ad4f0e S	104	#define HNS3_RXD_L2E_B 16
	105	#define HNS3_RXD_L3E_B 17
	106	#define HNS3_RXD_L4E_B 18
	107	#define HNS3_RXD_TRUNCAT_B 19
	108	#define HNS3_RXD_HOI_B 20
	109	#define HNS3_RXD_DOI_B 21
	110	#define HNS3_RXD_OL3E_B 22
	111	#define HNS3_RXD_OL4E_B 23
	112
	113	#define HNS3_RXD_ODMAC_S 0
	114	#define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
	115	#define HNS3_RXD_OVLAN_S 2
	116	#define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
	117	#define HNS3_RXD_OL3ID_S 4
	118	#define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
	119	#define HNS3_RXD_OL4ID_S 8
	120	#define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
	121	#define HNS3_RXD_FBHI_S 12
	122	#define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
	123	#define HNS3_RXD_FBLI_S 14
	124	#define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
	125
	126	#define HNS3_RXD_BDTYPE_S 0
	127	#define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
	128	#define HNS3_RXD_VLD_B 4
	129	#define HNS3_RXD_UDP0_B 5
	130	#define HNS3_RXD_EXTEND_B 7
	131	#define HNS3_RXD_FE_B 8
	132	#define HNS3_RXD_LUM_B 9
	133	#define HNS3_RXD_CRCP_B 10
	134	#define HNS3_RXD_L3L4P_B 11
	135	#define HNS3_RXD_TSIND_S 12
	136	#define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
	137	#define HNS3_RXD_LKBK_B 15
	138	#define HNS3_RXD_HDL_S 16
	139	#define HNS3_RXD_HDL_M (0x7ff << HNS3_RXD_HDL_S)
	140	#define HNS3_RXD_HSIND_B 31
	141
	142	#define HNS3_TXD_L3T_S 0
	143	#define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
	144	#define HNS3_TXD_L4T_S 2
	145	#define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
	146	#define HNS3_TXD_L3CS_B 4
	147	#define HNS3_TXD_L4CS_B 5
	148	#define HNS3_TXD_VLAN_B 6
	149	#define HNS3_TXD_TSO_B 7
	150
	151	#define HNS3_TXD_L2LEN_S 8
	152	#define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
	153	#define HNS3_TXD_L3LEN_S 16
	154	#define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
	155	#define HNS3_TXD_L4LEN_S 24
	156	#define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
	157
	158	#define HNS3_TXD_OL3T_S 0
	159	#define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
	160	#define HNS3_TXD_OVLAN_B 2
	161	#define HNS3_TXD_MACSEC_B 3
	162	#define HNS3_TXD_TUNTYPE_S 4
	163	#define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
	164
	165	#define HNS3_TXD_BDTYPE_S 0
	166	#define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
	167	#define HNS3_TXD_FE_B 4
168	#define HNS3_TXD_SC_S 5
169	#define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
170	#define HNS3_TXD_EXTEND_B 7
171	#define HNS3_TXD_VLD_B 8
172	#define HNS3_TXD_RI_B 9
173	#define HNS3_TXD_RA_B 10
174	#define HNS3_TXD_TSYN_B 11
175	#define HNS3_TXD_DECTTL_S 12
176	#define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
177
178	#define HNS3_TXD_MSS_S 0
179	#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
180
181	#define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
182	#define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
183
184	#define HNS3_VECTOR_NOT_INITED 0
185	#define HNS3_VECTOR_INITED 1
186
187	#define HNS3_MAX_BD_SIZE 65535
188	#define HNS3_MAX_BD_PER_FRAG 8
189	#define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS
190
191	#define HNS3_VECTOR_GL0_OFFSET 0x100
192	#define HNS3_VECTOR_GL1_OFFSET 0x200
193	#define HNS3_VECTOR_GL2_OFFSET 0x300
194	#define HNS3_VECTOR_RL_OFFSET 0x900
195	#define HNS3_VECTOR_RL_EN_B 6
196
197	enum hns3_pkt_l3t_type {
198	HNS3_L3T_NONE,
199	HNS3_L3T_IPV6,
200	HNS3_L3T_IPV4,
201	HNS3_L3T_RESERVED
202	};
203
204	enum hns3_pkt_l4t_type {
205	HNS3_L4T_UNKNOWN,
206	HNS3_L4T_TCP,
207	HNS3_L4T_UDP,
208	HNS3_L4T_SCTP
209	};
210
211	enum hns3_pkt_ol3t_type {
212	HNS3_OL3T_NONE,
213	HNS3_OL3T_IPV6,
214	HNS3_OL3T_IPV4_NO_CSUM,
215	HNS3_OL3T_IPV4_CSUM
216	};
217
218	enum hns3_pkt_tun_type {
219	HNS3_TUN_NONE,
220	HNS3_TUN_MAC_IN_UDP,
221	HNS3_TUN_NVGRE,
222	HNS3_TUN_OTHER
223	};
224
225	/* hardware spec ring buffer format */
226	struct __packed hns3_desc {
227	__le64 addr;
228	union {
229	struct {
230	__le16 vlan_tag;
231	__le16 send_size;
232	union {
233	__le32 type_cs_vlan_tso_len;
234	struct {
235	__u8 type_cs_vlan_tso;
236	__u8 l2_len;
237	__u8 l3_len;
238	__u8 l4_len;
239	};
240	};
241	__le16 outer_vlan_tag;
242	__le16 tv;
243
244	union {
245	__le32 ol_type_vlan_len_msec;
246	struct {
247	__u8 ol_type_vlan_msec;
248	__u8 ol2_len;
249	__u8 ol3_len;
250	__u8 ol4_len;
251	};
252	};
253
254	__le32 paylen;
255	__le16 bdtp_fe_sc_vld_ra_ri;
256	__le16 mss;
257	} tx;
258
259	struct {
260	__le32 l234_info;
261	__le16 pkt_len;
262	__le16 size;
263
264	__le32 rss_hash;
265	__le16 fd_id;
266	__le16 vlan_tag;
267
268	union {
269	__le32 ol_info;
270	struct {
271	__le16 o_dm_vlan_id_fb;
272	__le16 ot_vlan_tag;
273	};
274	};
275
276	__le32 bd_base_info;
277	} rx;
278	};
279	};
280
281	struct hns3_desc_cb {
282	dma_addr_t dma; /* dma address of this desc */
283	void buf; / cpu addr for a desc */
284
285	/* priv data for the desc, e.g. skb when use with ip stack*/
286	void *priv;
27a59593	287	u32 page_offset;
48d154e7	288	u32 length; /* length of the buffer */
76ad4f0e	289
27a59593 HT	290	u16 reuse_flag;
27a59593 HT	291
76ad4f0e S	292	/* desc type, used by the ring user to mark the type of the priv data */
	293	u16 type;
	294	};
	295
	296	enum hns3_pkt_l3type {
	297	HNS3_L3_TYPE_IPV4,
	298	HNS3_L3_TYPE_IPV6,
	299	HNS3_L3_TYPE_ARP,
	300	HNS3_L3_TYPE_RARP,
	301	HNS3_L3_TYPE_IPV4_OPT,
	302	HNS3_L3_TYPE_IPV6_EXT,
	303	HNS3_L3_TYPE_LLDP,
	304	HNS3_L3_TYPE_BPDU,
	305	HNS3_L3_TYPE_MAC_PAUSE,
	306	HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/
	307
	308	/* reserved for 0xA~0xB*/
	309
	310	HNS3_L3_TYPE_CNM = 0xc,
	311
	312	/* reserved for 0xD~0xE*/
	313
	314	HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */
	315	};
	316
	317	enum hns3_pkt_l4type {
	318	HNS3_L4_TYPE_UDP,
	319	HNS3_L4_TYPE_TCP,
	320	HNS3_L4_TYPE_GRE,
	321	HNS3_L4_TYPE_SCTP,
	322	HNS3_L4_TYPE_IGMP,
	323	HNS3_L4_TYPE_ICMP,
	324
	325	/* reserved for 0x6~0xE */
	326
	327	HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */
	328	};
	329
	330	enum hns3_pkt_ol3type {
	331	HNS3_OL3_TYPE_IPV4 = 0,
	332	HNS3_OL3_TYPE_IPV6,
	333	/* reserved for 0x2~0x3 */
	334	HNS3_OL3_TYPE_IPV4_OPT = 4,
	335	HNS3_OL3_TYPE_IPV6_EXT,
	336
	337	/* reserved for 0x6~0xE*/
	338
	339	HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */
	340	};
	341
	342	enum hns3_pkt_ol4type {
	343	HNS3_OL4_TYPE_NO_TUN,
	344	HNS3_OL4_TYPE_MAC_IN_UDP,
	345	HNS3_OL4_TYPE_NVGRE,
	346	HNS3_OL4_TYPE_UNKNOWN
	347	};
	348
	349	struct ring_stats {
	350	u64 io_err_cnt;
	351	u64 sw_err_cnt;
	352	u64 seg_pkt_cnt;
	353	union {
	354	struct {
	355	u64 tx_pkts;
356	u64 tx_bytes;
357	u64 tx_err_cnt;
358	u64 restart_queue;
359	u64 tx_busy;
360	};
361	struct {
362	u64 rx_pkts;
363	u64 rx_bytes;
364	u64 rx_err_cnt;
365	u64 reuse_pg_cnt;
366	u64 err_pkt_len;
367	u64 non_vld_descs;
368	u64 err_bd_num;
369	u64 l2_err;
370	u64 l3l4_csum_err;
371	};
372	};
373	};
374
375	struct hns3_enet_ring {
376	u8 __iomem io_base; / base io address for the ring */
377	struct hns3_desc desc; / dma map address space */
378	struct hns3_desc_cb *desc_cb;
379	struct hns3_enet_ring *next;
380	struct hns3_enet_tqp_vector *tqp_vector;
381	struct hnae3_queue *tqp;
382	char ring_name[HNS3_RING_NAME_LEN];
383	struct device dev; / will be used for DMA mapping of descriptors */
384
385	/* statistic */
386	struct ring_stats stats;
387	struct u64_stats_sync syncp;
388
389	dma_addr_t desc_dma_addr;
390	u32 buf_size; /* size for hnae_desc->addr, preset by AE */
391	u16 desc_num; /* total number of desc */
392	u16 max_desc_num_per_pkt;
393	u16 max_raw_data_sz_per_desc;
394	u16 max_pkt_size;
395	int next_to_use; /* idx of next spare desc */
396
397	/* idx of lastest sent desc, the ring is empty when equal to
398	* next_to_use
399	*/
400	int next_to_clean;
401
402	u32 flag; /* ring attribute */
403	int irq_init_flag;
404
405	int numa_node;
406	cpumask_t affinity_mask;
407	};
408
409	struct hns_queue;
410
411	struct hns3_nic_ring_data {
412	struct hns3_enet_ring *ring;
413	struct napi_struct napi;
414	int queue_index;
415	int (poll_one)(struct hns3_nic_ring_data , int, void *);
416	void (ex_process)(struct hns3_nic_ring_data , struct sk_buff *);
417	void (fini_process)(struct hns3_nic_ring_data );
418	};
419
420	struct hns3_nic_ops {
421	int (fill_desc)(struct hns3_enet_ring ring, void *priv,
422	int size, dma_addr_t dma, int frag_end,
423	enum hns_desc_type type);
424	int (maybe_stop_tx)(struct sk_buff *out_skb,
425	int bnum, struct hns3_enet_ring ring);
426	void (get_rxd_bnum)(u32 bnum_flag, int out_bnum);
427	};
428
429	enum hns3_flow_level_range {
430	HNS3_FLOW_LOW = 0,
431	HNS3_FLOW_MID = 1,
432	HNS3_FLOW_HIGH = 2,
433	HNS3_FLOW_ULTRA = 3,
434	};
435
436	enum hns3_link_mode_bits {
437	HNS3_LM_FIBRE_BIT = BIT(0),
438	HNS3_LM_AUTONEG_BIT = BIT(1),
439	HNS3_LM_TP_BIT = BIT(2),
440	HNS3_LM_PAUSE_BIT = BIT(3),
441	HNS3_LM_BACKPLANE_BIT = BIT(4),
442	HNS3_LM_10BASET_HALF_BIT = BIT(5),
443	HNS3_LM_10BASET_FULL_BIT = BIT(6),
444	HNS3_LM_100BASET_HALF_BIT = BIT(7),
445	HNS3_LM_100BASET_FULL_BIT = BIT(8),
446	HNS3_LM_1000BASET_FULL_BIT = BIT(9),
447	HNS3_LM_10000BASEKR_FULL_BIT = BIT(10),
448	HNS3_LM_25000BASEKR_FULL_BIT = BIT(11),
449	HNS3_LM_40000BASELR4_FULL_BIT = BIT(12),
450	HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13),
451	HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14),
452	HNS3_LM_COUNT = 15
453	};
454
434776a5	455	#define HNS3_INT_GL_MAX 0x1FE0
b81c59e1 FL	456	#define HNS3_INT_GL_50K 0x0014
	457	#define HNS3_INT_GL_20K 0x0032
	458	#define HNS3_INT_GL_18K 0x0036
	459	#define HNS3_INT_GL_8K 0x007C
76ad4f0e	460
434776a5 FL	461	#define HNS3_INT_RL_MAX 0x00EC
	462	#define HNS3_INT_RL_ENABLE_MASK 0x40
	463
cd9d187b FL	464	#define HNS3_INT_ADAPT_DOWN_START 100
cd9d187b FL	465
9bc727a9 YL	466	struct hns3_enet_coalesce {
	467	u16 int_gl;
	468	u8 gl_adapt_enable;
	469	enum hns3_flow_level_range flow_level;
	470	};
	471
76ad4f0e S	472	struct hns3_enet_ring_group {
	473	/* array of pointers to rings */
	474	struct hns3_enet_ring *ring;
	475	u64 total_bytes; /* total bytes processed this group */
	476	u64 total_packets; /* total packets processed this group */
	477	u16 count;
9bc727a9	478	struct hns3_enet_coalesce coal;
76ad4f0e S	479	};
	480
	481	struct hns3_enet_tqp_vector {
	482	struct hnae3_handle *handle;
	483	u8 __iomem *mask_addr;
	484	int vector_irq;
	485	int irq_init_flag;
	486
	487	u16 idx; /* index in the TQP vector array per handle. */
	488
	489	struct napi_struct napi;
	490
	491	struct hns3_enet_ring_group rx_group;
	492	struct hns3_enet_ring_group tx_group;
	493
	494	u16 num_tqps; /* total number of tqps in TQP vector */
	495
76ad4f0e S	496	char name[HNAE3_INT_NAME_LEN];
	497
	498	/* when 0 should adjust interrupt coalesce parameter */
	499	u8 int_adapt_down;
a95e1f86	500	unsigned long last_jiffies;
76ad4f0e S	501	} ____cacheline_internodealigned_in_smp;
	502
	503	enum hns3_udp_tnl_type {
	504	HNS3_UDP_TNL_VXLAN,
	505	HNS3_UDP_TNL_GENEVE,
	506	HNS3_UDP_TNL_MAX,
	507	};
	508
	509	struct hns3_udp_tunnel {
	510	u16 dst_port;
	511	int used;
	512	};
	513
	514	struct hns3_nic_priv {
	515	struct hnae3_handle *ae_handle;
	516	u32 enet_ver;
	517	u32 port_id;
	518	struct net_device *netdev;
	519	struct device *dev;
	520	struct hns3_nic_ops ops;
	521
	522	/**
	523	* the cb for nic to manage the ring buffer, the first half of the
	524	* array is for tx_ring and vice versa for the second half
	525	*/
	526	struct hns3_nic_ring_data *ring_data;
	527	struct hns3_enet_tqp_vector *tqp_vector;
	528	u16 vector_num;
	529
	530	/* The most recently read link state */
	531	int link;
	532	u64 tx_timeout_count;
	533
	534	unsigned long state;
	535
	536	struct timer_list service_timer;
	537
	538	struct work_struct service_task;
	539
	540	struct notifier_block notifier_block;
	541	/* Vxlan/Geneve information */
	542	struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
681ec399	543	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
76ad4f0e S	544	};
	545
	546	union l3_hdr_info {
	547	struct iphdr *v4;
	548	struct ipv6hdr *v6;
	549	unsigned char *hdr;
	550	};
	551
	552	union l4_hdr_info {
	553	struct tcphdr *tcp;
	554	struct udphdr *udp;
	555	unsigned char *hdr;
	556	};
	557
	558	/* the distance between [begin, end) in a ring buffer
	559	* note: there is a unuse slot between the begin and the end
	560	*/
	561	static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end)
	562	{
	563	return (end - begin + ring->desc_num) % ring->desc_num;
	564	}
	565
	566	static inline int ring_space(struct hns3_enet_ring *ring)
	567	{
	568	return ring->desc_num -
	569	ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1;
	570	}
	571
	572	static inline int is_ring_empty(struct hns3_enet_ring *ring)
	573	{
	574	return ring->next_to_use == ring->next_to_clean;
	575	}
	576
	577	static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
	578	{
	579	u8 __iomem *reg_addr = READ_ONCE(base);
	580
	581	writel(value, reg_addr + reg);
	582	}
	583
	584	#define hns3_write_dev(a, reg, value) \
	585	hns3_write_reg((a)->io_base, (reg), (value))
	586
e4e87715	587	#define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
76ad4f0e S	588	(tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
	589
	590	#define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev)
	591
	592	#define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
	593	DMA_TO_DEVICE : DMA_FROM_DEVICE)
	594
	595	#define tx_ring_data(priv, idx) ((priv)->ring_data[idx])
	596
e4e87715 PL	597	#define hnae3_buf_size(_ring) ((_ring)->buf_size)
	598	#define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring)))
	599	#define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring))
76ad4f0e S	600
	601	/* iterator for handling rings in ring group */
	602	#define hns3_for_each_ring(pos, head) \
	603	for (pos = (head).ring; pos; pos = pos->next)
	604
9780cb97 YL	605	#define hns3_get_handle(ndev) \
	606	(((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
	607
434776a5 FL	608	#define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
	609	#define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
	610
	611	#define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
	612	#define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
	613
76ad4f0e	614	void hns3_ethtool_set_ops(struct net_device *netdev);
09f2af64 PL	615	int hns3_set_channels(struct net_device *netdev,
09f2af64 PL	616	struct ethtool_channels *ch);
76ad4f0e	617
24e750c4	618	bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget);
5668abda L	619	int hns3_init_all_ring(struct hns3_nic_priv *priv);
5668abda L	620	int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
7b763f3f	621	int hns3_nic_reset_all_ring(struct hnae3_handle *h);
d43e5aca YL	622	netdev_tx_t hns3_nic_net_xmit(struct sk_buff skb, struct net_device netdev);
	623	int hns3_clean_rx_ring(
	624	struct hns3_enet_ring *ring, int budget,
	625	void (rx_fn)(struct hns3_enet_ring , struct sk_buff *));
986743db	626
434776a5 FL	627	void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
	628	u32 gl_value);
	629	void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
	630	u32 gl_value);
	631	void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
	632	u32 rl_value);
	633
986743db YL	634	#ifdef CONFIG_HNS3_DCB
	635	void hns3_dcbnl_setup(struct hnae3_handle *handle);
	636	#else
	637	static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
	638	#endif
	639
76ad4f0e	640	#endif