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68c0a5c7 S |
1 | /* |
2 | * Copyright (c) 2016~2017 Hisilicon Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #ifndef __HCLGE_CMD_H | |
11 | #define __HCLGE_CMD_H | |
12 | #include <linux/types.h> | |
13 | #include <linux/io.h> | |
14 | ||
ff824288 | 15 | #define HCLGE_CMDQ_TX_TIMEOUT 30000 |
68c0a5c7 S |
16 | |
17 | struct hclge_dev; | |
18 | struct hclge_desc { | |
19 | __le16 opcode; | |
20 | ||
21 | #define HCLGE_CMDQ_RX_INVLD_B 0 | |
22 | #define HCLGE_CMDQ_RX_OUTVLD_B 1 | |
23 | ||
24 | __le16 flag; | |
25 | __le16 retval; | |
26 | __le16 rsv; | |
27 | __le32 data[6]; | |
28 | }; | |
29 | ||
30 | struct hclge_desc_cb { | |
31 | dma_addr_t dma; | |
32 | void *va; | |
33 | u32 length; | |
34 | }; | |
35 | ||
36 | struct hclge_cmq_ring { | |
37 | dma_addr_t desc_dma_addr; | |
38 | struct hclge_desc *desc; | |
39 | struct hclge_desc_cb *desc_cb; | |
40 | struct hclge_dev *dev; | |
41 | u32 head; | |
42 | u32 tail; | |
43 | ||
44 | u16 buf_size; | |
45 | u16 desc_num; | |
46 | int next_to_use; | |
47 | int next_to_clean; | |
48 | u8 flag; | |
49 | spinlock_t lock; /* Command queue lock */ | |
50 | }; | |
51 | ||
52 | enum hclge_cmd_return_status { | |
53 | HCLGE_CMD_EXEC_SUCCESS = 0, | |
54 | HCLGE_CMD_NO_AUTH = 1, | |
55 | HCLGE_CMD_NOT_EXEC = 2, | |
56 | HCLGE_CMD_QUEUE_FULL = 3, | |
57 | }; | |
58 | ||
59 | enum hclge_cmd_status { | |
60 | HCLGE_STATUS_SUCCESS = 0, | |
61 | HCLGE_ERR_CSQ_FULL = -1, | |
62 | HCLGE_ERR_CSQ_TIMEOUT = -2, | |
63 | HCLGE_ERR_CSQ_ERROR = -3, | |
64 | }; | |
65 | ||
466b0c00 L |
66 | struct hclge_misc_vector { |
67 | u8 __iomem *addr; | |
68 | int vector_irq; | |
69 | }; | |
70 | ||
68c0a5c7 S |
71 | struct hclge_cmq { |
72 | struct hclge_cmq_ring csq; | |
73 | struct hclge_cmq_ring crq; | |
74 | u16 tx_timeout; /* Tx timeout */ | |
75 | enum hclge_cmd_status last_status; | |
76 | }; | |
77 | ||
78 | #define HCLGE_CMD_FLAG_IN_VALID_SHIFT 0 | |
79 | #define HCLGE_CMD_FLAG_OUT_VALID_SHIFT 1 | |
80 | #define HCLGE_CMD_FLAG_NEXT_SHIFT 2 | |
81 | #define HCLGE_CMD_FLAG_WR_OR_RD_SHIFT 3 | |
82 | #define HCLGE_CMD_FLAG_NO_INTR_SHIFT 4 | |
83 | #define HCLGE_CMD_FLAG_ERR_INTR_SHIFT 5 | |
84 | ||
85 | #define HCLGE_CMD_FLAG_IN BIT(HCLGE_CMD_FLAG_IN_VALID_SHIFT) | |
86 | #define HCLGE_CMD_FLAG_OUT BIT(HCLGE_CMD_FLAG_OUT_VALID_SHIFT) | |
87 | #define HCLGE_CMD_FLAG_NEXT BIT(HCLGE_CMD_FLAG_NEXT_SHIFT) | |
88 | #define HCLGE_CMD_FLAG_WR BIT(HCLGE_CMD_FLAG_WR_OR_RD_SHIFT) | |
89 | #define HCLGE_CMD_FLAG_NO_INTR BIT(HCLGE_CMD_FLAG_NO_INTR_SHIFT) | |
90 | #define HCLGE_CMD_FLAG_ERR_INTR BIT(HCLGE_CMD_FLAG_ERR_INTR_SHIFT) | |
91 | ||
92 | enum hclge_opcode_type { | |
93 | /* Generic command */ | |
94 | HCLGE_OPC_QUERY_FW_VER = 0x0001, | |
95 | HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, | |
96 | HCLGE_OPC_GBL_RST_STATUS = 0x0021, | |
97 | HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, | |
98 | HCLGE_OPC_QUERY_PF_RSRC = 0x0023, | |
99 | HCLGE_OPC_QUERY_VF_RSRC = 0x0024, | |
100 | HCLGE_OPC_GET_CFG_PARAM = 0x0025, | |
101 | ||
102 | HCLGE_OPC_STATS_64_BIT = 0x0030, | |
103 | HCLGE_OPC_STATS_32_BIT = 0x0031, | |
104 | HCLGE_OPC_STATS_MAC = 0x0032, | |
db2a3e43 FL |
105 | |
106 | HCLGE_OPC_QUERY_REG_NUM = 0x0040, | |
107 | HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, | |
108 | HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, | |
68c0a5c7 S |
109 | /* Device management command */ |
110 | ||
111 | /* MAC commond */ | |
112 | HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, | |
113 | HCLGE_OPC_CONFIG_AN_MODE = 0x0304, | |
114 | HCLGE_OPC_QUERY_AN_RESULT = 0x0306, | |
115 | HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, | |
116 | HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, | |
117 | HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, | |
fe36292f | 118 | HCLGE_OPC_STATS_MAC_TRAFFIC = 0x0314, |
68c0a5c7 S |
119 | /* MACSEC command */ |
120 | ||
121 | /* PFC/Pause CMD*/ | |
122 | HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, | |
123 | HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, | |
124 | HCLGE_OPC_CFG_MAC_PARA = 0x0703, | |
125 | HCLGE_OPC_CFG_PFC_PARA = 0x0704, | |
126 | HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, | |
127 | HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, | |
128 | HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, | |
129 | HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, | |
130 | HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, | |
131 | HCLGE_OPC_QOS_MAP = 0x070A, | |
132 | ||
133 | /* ETS/scheduler commands */ | |
134 | HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, | |
135 | HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, | |
136 | HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, | |
137 | HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, | |
138 | HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, | |
139 | HCLGE_OPC_TM_PG_WEIGHT = 0x0809, | |
140 | HCLGE_OPC_TM_QS_WEIGHT = 0x080A, | |
141 | HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, | |
142 | HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, | |
143 | HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, | |
144 | HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, | |
145 | HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, | |
146 | HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, | |
147 | HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, | |
148 | HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, | |
149 | HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, | |
150 | HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, | |
151 | ||
152 | /* Packet buffer allocate command */ | |
153 | HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, | |
154 | HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, | |
155 | HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, | |
156 | HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, | |
157 | HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, | |
158 | HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, | |
159 | ||
160 | /* PTP command */ | |
161 | /* TQP management command */ | |
162 | HCLGE_OPC_SET_TQP_MAP = 0x0A01, | |
163 | ||
164 | /* TQP command */ | |
165 | HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, | |
166 | HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, | |
167 | HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, | |
168 | HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, | |
169 | HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, | |
170 | HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, | |
171 | HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, | |
172 | HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, | |
173 | HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, | |
174 | HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, | |
175 | ||
176 | /* TSO cmd */ | |
177 | HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, | |
178 | ||
179 | /* RSS cmd */ | |
180 | HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, | |
181 | HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, | |
182 | HCLGE_OPC_RSS_TC_MODE = 0x0D08, | |
183 | HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, | |
184 | ||
185 | /* Promisuous mode command */ | |
186 | HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, | |
187 | ||
e62f2a6b PL |
188 | /* Vlan offload command */ |
189 | HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, | |
190 | HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, | |
191 | ||
68c0a5c7 S |
192 | /* Interrupts cmd */ |
193 | HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, | |
194 | HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, | |
195 | ||
196 | /* MAC command */ | |
197 | HCLGE_OPC_MAC_VLAN_ADD = 0x1000, | |
198 | HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, | |
199 | HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, | |
200 | HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, | |
201 | HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, | |
202 | HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, | |
6f712727 | 203 | HCLGE_OPC_MAC_VLAN_MASK_SET = 0x1012, |
68c0a5c7 S |
204 | |
205 | /* Multicast linear table cmd */ | |
206 | HCLGE_OPC_MTA_MAC_MODE_CFG = 0x1020, | |
207 | HCLGE_OPC_MTA_MAC_FUNC_CFG = 0x1021, | |
208 | HCLGE_OPC_MTA_TBL_ITEM_CFG = 0x1022, | |
209 | HCLGE_OPC_MTA_TBL_ITEM_QUERY = 0x1023, | |
210 | ||
211 | /* VLAN command */ | |
212 | HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, | |
213 | HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, | |
214 | HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, | |
215 | ||
216 | /* MDIO command */ | |
217 | HCLGE_OPC_MDIO_CONFIG = 0x1900, | |
218 | ||
219 | /* QCN command */ | |
220 | HCLGE_OPC_QCN_MOD_CFG = 0x1A01, | |
221 | HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, | |
222 | HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, | |
223 | HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, | |
224 | HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, | |
225 | HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, | |
226 | HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, | |
227 | HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, | |
228 | ||
229 | /* Mailbox cmd */ | |
230 | HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, | |
d9a0884e JS |
231 | |
232 | /* Led command */ | |
233 | HCLGE_OPC_LED_STATUS_CFG = 0xB000, | |
68c0a5c7 S |
234 | }; |
235 | ||
236 | #define HCLGE_TQP_REG_OFFSET 0x80000 | |
237 | #define HCLGE_TQP_REG_SIZE 0x200 | |
238 | ||
239 | #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 | |
240 | #define HCLGE_RCB_INIT_FLAG_EN_B 0 | |
241 | #define HCLGE_RCB_INIT_FLAG_FINI_B 8 | |
d44f9b63 | 242 | struct hclge_config_rcb_init_cmd { |
68c0a5c7 S |
243 | __le16 rcb_init_flag; |
244 | u8 rsv[22]; | |
245 | }; | |
246 | ||
d44f9b63 | 247 | struct hclge_tqp_map_cmd { |
68c0a5c7 S |
248 | __le16 tqp_id; /* Absolute tqp id for in this pf */ |
249 | u8 tqp_vf; /* VF id */ | |
250 | #define HCLGE_TQP_MAP_TYPE_PF 0 | |
251 | #define HCLGE_TQP_MAP_TYPE_VF 1 | |
252 | #define HCLGE_TQP_MAP_TYPE_B 0 | |
253 | #define HCLGE_TQP_MAP_EN_B 1 | |
254 | u8 tqp_flag; /* Indicate it's pf or vf tqp */ | |
255 | __le16 tqp_vid; /* Virtual id in this pf/vf */ | |
256 | u8 rsv[18]; | |
257 | }; | |
258 | ||
0305b443 | 259 | #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 |
68c0a5c7 S |
260 | |
261 | enum hclge_int_type { | |
262 | HCLGE_INT_TX, | |
263 | HCLGE_INT_RX, | |
264 | HCLGE_INT_EVENT, | |
265 | }; | |
266 | ||
d44f9b63 | 267 | struct hclge_ctrl_vector_chain_cmd { |
68c0a5c7 S |
268 | u8 int_vector_id; |
269 | u8 int_cause_num; | |
270 | #define HCLGE_INT_TYPE_S 0 | |
5392902d | 271 | #define HCLGE_INT_TYPE_M GENMASK(1, 0) |
68c0a5c7 | 272 | #define HCLGE_TQP_ID_S 2 |
5392902d | 273 | #define HCLGE_TQP_ID_M GENMASK(12, 2) |
0305b443 | 274 | #define HCLGE_INT_GL_IDX_S 13 |
5392902d | 275 | #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) |
68c0a5c7 | 276 | __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; |
0305b443 L |
277 | u8 vfid; |
278 | u8 rsv; | |
68c0a5c7 S |
279 | }; |
280 | ||
281 | #define HCLGE_TC_NUM 8 | |
282 | #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ | |
283 | #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ | |
d44f9b63 | 284 | struct hclge_tx_buff_alloc_cmd { |
68c0a5c7 S |
285 | __le16 tx_pkt_buff[HCLGE_TC_NUM]; |
286 | u8 tx_buff_rsv[8]; | |
287 | }; | |
288 | ||
d44f9b63 | 289 | struct hclge_rx_priv_buff_cmd { |
68c0a5c7 | 290 | __le16 buf_num[HCLGE_TC_NUM]; |
b8c8bf47 YL |
291 | __le16 shared_buf; |
292 | u8 rsv[6]; | |
68c0a5c7 S |
293 | }; |
294 | ||
d44f9b63 | 295 | struct hclge_query_version_cmd { |
68c0a5c7 S |
296 | __le32 firmware; |
297 | __le32 firmware_rsv[5]; | |
298 | }; | |
299 | ||
300 | #define HCLGE_RX_PRIV_EN_B 15 | |
301 | #define HCLGE_TC_NUM_ONE_DESC 4 | |
302 | struct hclge_priv_wl { | |
303 | __le16 high; | |
304 | __le16 low; | |
305 | }; | |
306 | ||
307 | struct hclge_rx_priv_wl_buf { | |
308 | struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; | |
309 | }; | |
310 | ||
311 | struct hclge_rx_com_thrd { | |
312 | struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; | |
313 | }; | |
314 | ||
315 | struct hclge_rx_com_wl { | |
316 | struct hclge_priv_wl com_wl; | |
317 | }; | |
318 | ||
319 | struct hclge_waterline { | |
320 | u32 low; | |
321 | u32 high; | |
322 | }; | |
323 | ||
324 | struct hclge_tc_thrd { | |
325 | u32 low; | |
326 | u32 high; | |
327 | }; | |
328 | ||
329 | struct hclge_priv_buf { | |
330 | struct hclge_waterline wl; /* Waterline for low and high*/ | |
331 | u32 buf_size; /* TC private buffer size */ | |
9ffe79a9 | 332 | u32 tx_buf_size; |
68c0a5c7 S |
333 | u32 enable; /* Enable TC private buffer or not */ |
334 | }; | |
335 | ||
336 | #define HCLGE_MAX_TC_NUM 8 | |
337 | struct hclge_shared_buf { | |
338 | struct hclge_waterline self; | |
339 | struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; | |
340 | u32 buf_size; | |
341 | }; | |
342 | ||
acf61ecd YL |
343 | struct hclge_pkt_buf_alloc { |
344 | struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; | |
345 | struct hclge_shared_buf s_buf; | |
346 | }; | |
347 | ||
68c0a5c7 | 348 | #define HCLGE_RX_COM_WL_EN_B 15 |
d44f9b63 | 349 | struct hclge_rx_com_wl_buf_cmd { |
68c0a5c7 S |
350 | __le16 high_wl; |
351 | __le16 low_wl; | |
352 | u8 rsv[20]; | |
353 | }; | |
354 | ||
355 | #define HCLGE_RX_PKT_EN_B 15 | |
d44f9b63 | 356 | struct hclge_rx_pkt_buf_cmd { |
68c0a5c7 S |
357 | __le16 high_pkt; |
358 | __le16 low_pkt; | |
359 | u8 rsv[20]; | |
360 | }; | |
361 | ||
362 | #define HCLGE_PF_STATE_DONE_B 0 | |
363 | #define HCLGE_PF_STATE_MAIN_B 1 | |
364 | #define HCLGE_PF_STATE_BOND_B 2 | |
365 | #define HCLGE_PF_STATE_MAC_N_B 6 | |
366 | #define HCLGE_PF_MAC_NUM_MASK 0x3 | |
367 | #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) | |
368 | #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) | |
d44f9b63 | 369 | struct hclge_func_status_cmd { |
68c0a5c7 S |
370 | __le32 vf_rst_state[4]; |
371 | u8 pf_state; | |
372 | u8 mac_id; | |
373 | u8 rsv1; | |
374 | u8 pf_cnt_in_mac; | |
375 | u8 pf_num; | |
376 | u8 vf_num; | |
377 | u8 rsv[2]; | |
378 | }; | |
379 | ||
d44f9b63 | 380 | struct hclge_pf_res_cmd { |
68c0a5c7 S |
381 | __le16 tqp_num; |
382 | __le16 buf_size; | |
383 | __le16 msixcap_localid_ba_nic; | |
384 | __le16 msixcap_localid_ba_rocee; | |
385 | #define HCLGE_PF_VEC_NUM_S 0 | |
386 | #define HCLGE_PF_VEC_NUM_M (0xff << HCLGE_PF_VEC_NUM_S) | |
387 | __le16 pf_intr_vector_number; | |
388 | __le16 pf_own_fun_number; | |
389 | __le32 rsv[3]; | |
390 | }; | |
391 | ||
392 | #define HCLGE_CFG_OFFSET_S 0 | |
5392902d | 393 | #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) |
68c0a5c7 | 394 | #define HCLGE_CFG_RD_LEN_S 24 |
5392902d | 395 | #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) |
68c0a5c7 S |
396 | #define HCLGE_CFG_RD_LEN_BYTES 16 |
397 | #define HCLGE_CFG_RD_LEN_UNIT 4 | |
398 | ||
399 | #define HCLGE_CFG_VMDQ_S 0 | |
5392902d | 400 | #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) |
68c0a5c7 | 401 | #define HCLGE_CFG_TC_NUM_S 8 |
5392902d | 402 | #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) |
68c0a5c7 | 403 | #define HCLGE_CFG_TQP_DESC_N_S 16 |
5392902d | 404 | #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) |
68c0a5c7 | 405 | #define HCLGE_CFG_PHY_ADDR_S 0 |
39e2151f | 406 | #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) |
68c0a5c7 | 407 | #define HCLGE_CFG_MEDIA_TP_S 8 |
5392902d | 408 | #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) |
68c0a5c7 | 409 | #define HCLGE_CFG_RX_BUF_LEN_S 16 |
5392902d | 410 | #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) |
68c0a5c7 | 411 | #define HCLGE_CFG_MAC_ADDR_H_S 0 |
5392902d | 412 | #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) |
68c0a5c7 | 413 | #define HCLGE_CFG_DEFAULT_SPEED_S 16 |
5392902d | 414 | #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) |
c408e202 PL |
415 | #define HCLGE_CFG_RSS_SIZE_S 24 |
416 | #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) | |
d92ceae9 FL |
417 | #define HCLGE_CFG_SPEED_ABILITY_S 0 |
418 | #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) | |
68c0a5c7 | 419 | |
d44f9b63 | 420 | struct hclge_cfg_param_cmd { |
68c0a5c7 S |
421 | __le32 offset; |
422 | __le32 rsv; | |
423 | __le32 param[4]; | |
424 | }; | |
425 | ||
426 | #define HCLGE_MAC_MODE 0x0 | |
427 | #define HCLGE_DESC_NUM 0x40 | |
428 | ||
429 | #define HCLGE_ALLOC_VALID_B 0 | |
d44f9b63 | 430 | struct hclge_vf_num_cmd { |
68c0a5c7 S |
431 | u8 alloc_valid; |
432 | u8 rsv[23]; | |
433 | }; | |
434 | ||
435 | #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 | |
436 | #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 | |
437 | #define HCLGE_RSS_HASH_KEY_NUM 16 | |
d44f9b63 | 438 | struct hclge_rss_config_cmd { |
68c0a5c7 S |
439 | u8 hash_config; |
440 | u8 rsv[7]; | |
441 | u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; | |
442 | }; | |
443 | ||
d44f9b63 | 444 | struct hclge_rss_input_tuple_cmd { |
68c0a5c7 S |
445 | u8 ipv4_tcp_en; |
446 | u8 ipv4_udp_en; | |
447 | u8 ipv4_sctp_en; | |
448 | u8 ipv4_fragment_en; | |
449 | u8 ipv6_tcp_en; | |
450 | u8 ipv6_udp_en; | |
451 | u8 ipv6_sctp_en; | |
452 | u8 ipv6_fragment_en; | |
453 | u8 rsv[16]; | |
454 | }; | |
455 | ||
456 | #define HCLGE_RSS_CFG_TBL_SIZE 16 | |
457 | ||
d44f9b63 | 458 | struct hclge_rss_indirection_table_cmd { |
a90bb9a5 YL |
459 | __le16 start_table_index; |
460 | __le16 rss_set_bitmap; | |
68c0a5c7 S |
461 | u8 rsv[4]; |
462 | u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; | |
463 | }; | |
464 | ||
465 | #define HCLGE_RSS_TC_OFFSET_S 0 | |
5392902d | 466 | #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) |
68c0a5c7 | 467 | #define HCLGE_RSS_TC_SIZE_S 12 |
5392902d | 468 | #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) |
68c0a5c7 | 469 | #define HCLGE_RSS_TC_VALID_B 15 |
d44f9b63 | 470 | struct hclge_rss_tc_mode_cmd { |
a90bb9a5 | 471 | __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; |
68c0a5c7 S |
472 | u8 rsv[8]; |
473 | }; | |
474 | ||
475 | #define HCLGE_LINK_STS_B 0 | |
476 | #define HCLGE_LINK_STATUS BIT(HCLGE_LINK_STS_B) | |
d44f9b63 | 477 | struct hclge_link_status_cmd { |
68c0a5c7 S |
478 | u8 status; |
479 | u8 rsv[23]; | |
480 | }; | |
481 | ||
482 | struct hclge_promisc_param { | |
483 | u8 vf_id; | |
484 | u8 enable; | |
485 | }; | |
486 | ||
487 | #define HCLGE_PROMISC_EN_B 1 | |
488 | #define HCLGE_PROMISC_EN_ALL 0x7 | |
489 | #define HCLGE_PROMISC_EN_UC 0x1 | |
490 | #define HCLGE_PROMISC_EN_MC 0x2 | |
491 | #define HCLGE_PROMISC_EN_BC 0x4 | |
d44f9b63 | 492 | struct hclge_promisc_cfg_cmd { |
68c0a5c7 S |
493 | u8 flag; |
494 | u8 vf_id; | |
495 | __le16 rsv0; | |
496 | u8 rsv1[20]; | |
497 | }; | |
498 | ||
499 | enum hclge_promisc_type { | |
500 | HCLGE_UNICAST = 1, | |
501 | HCLGE_MULTICAST = 2, | |
502 | HCLGE_BROADCAST = 3, | |
503 | }; | |
504 | ||
505 | #define HCLGE_MAC_TX_EN_B 6 | |
506 | #define HCLGE_MAC_RX_EN_B 7 | |
507 | #define HCLGE_MAC_PAD_TX_B 11 | |
508 | #define HCLGE_MAC_PAD_RX_B 12 | |
509 | #define HCLGE_MAC_1588_TX_B 13 | |
510 | #define HCLGE_MAC_1588_RX_B 14 | |
511 | #define HCLGE_MAC_APP_LP_B 15 | |
512 | #define HCLGE_MAC_LINE_LP_B 16 | |
513 | #define HCLGE_MAC_FCS_TX_B 17 | |
514 | #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 | |
515 | #define HCLGE_MAC_RX_FCS_STRIP_B 19 | |
516 | #define HCLGE_MAC_RX_FCS_B 20 | |
517 | #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 | |
518 | #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 | |
519 | ||
d44f9b63 | 520 | struct hclge_config_mac_mode_cmd { |
68c0a5c7 S |
521 | __le32 txrx_pad_fcs_loop_en; |
522 | u8 rsv[20]; | |
523 | }; | |
524 | ||
525 | #define HCLGE_CFG_SPEED_S 0 | |
5392902d | 526 | #define HCLGE_CFG_SPEED_M GENMASK(5, 0) |
68c0a5c7 S |
527 | |
528 | #define HCLGE_CFG_DUPLEX_B 7 | |
529 | #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) | |
530 | ||
d44f9b63 | 531 | struct hclge_config_mac_speed_dup_cmd { |
68c0a5c7 S |
532 | u8 speed_dup; |
533 | ||
534 | #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 | |
535 | u8 mac_change_fec_en; | |
536 | u8 rsv[22]; | |
537 | }; | |
538 | ||
539 | #define HCLGE_QUERY_SPEED_S 3 | |
540 | #define HCLGE_QUERY_AN_B 0 | |
541 | #define HCLGE_QUERY_DUPLEX_B 2 | |
542 | ||
5392902d | 543 | #define HCLGE_QUERY_SPEED_M GENMASK(4, 0) |
68c0a5c7 S |
544 | #define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B) |
545 | #define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B) | |
546 | ||
d44f9b63 | 547 | struct hclge_query_an_speed_dup_cmd { |
68c0a5c7 S |
548 | u8 an_syn_dup_speed; |
549 | u8 pause; | |
550 | u8 rsv[23]; | |
551 | }; | |
552 | ||
5392902d | 553 | #define HCLGE_RING_ID_MASK GENMASK(9, 0) |
68c0a5c7 S |
554 | #define HCLGE_TQP_ENABLE_B 0 |
555 | ||
556 | #define HCLGE_MAC_CFG_AN_EN_B 0 | |
557 | #define HCLGE_MAC_CFG_AN_INT_EN_B 1 | |
558 | #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 | |
559 | #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 | |
560 | #define HCLGE_MAC_CFG_AN_RST_B 4 | |
561 | ||
562 | #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) | |
563 | ||
d44f9b63 | 564 | struct hclge_config_auto_neg_cmd { |
68c0a5c7 S |
565 | __le32 cfg_an_cmd_flag; |
566 | u8 rsv[20]; | |
567 | }; | |
568 | ||
68c0a5c7 S |
569 | #define HCLGE_MAC_UPLINK_PORT 0x100 |
570 | ||
d44f9b63 | 571 | struct hclge_config_max_frm_size_cmd { |
68c0a5c7 S |
572 | __le16 max_frm_size; |
573 | u8 rsv[22]; | |
574 | }; | |
575 | ||
576 | enum hclge_mac_vlan_tbl_opcode { | |
577 | HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ | |
578 | HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ | |
579 | HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ | |
580 | HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ | |
581 | }; | |
582 | ||
583 | #define HCLGE_MAC_VLAN_BIT0_EN_B 0x0 | |
584 | #define HCLGE_MAC_VLAN_BIT1_EN_B 0x1 | |
585 | #define HCLGE_MAC_EPORT_SW_EN_B 0xc | |
586 | #define HCLGE_MAC_EPORT_TYPE_B 0xb | |
587 | #define HCLGE_MAC_EPORT_VFID_S 0x3 | |
5392902d | 588 | #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) |
68c0a5c7 | 589 | #define HCLGE_MAC_EPORT_PFID_S 0x0 |
5392902d | 590 | #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) |
d44f9b63 | 591 | struct hclge_mac_vlan_tbl_entry_cmd { |
68c0a5c7 S |
592 | u8 flags; |
593 | u8 resp_code; | |
594 | __le16 vlan_tag; | |
595 | __le32 mac_addr_hi32; | |
596 | __le16 mac_addr_lo16; | |
597 | __le16 rsv1; | |
598 | u8 entry_type; | |
599 | u8 mc_mac_en; | |
600 | __le16 egress_port; | |
601 | __le16 egress_queue; | |
602 | u8 rsv2[6]; | |
603 | }; | |
604 | ||
6f712727 PL |
605 | #define HCLGE_VLAN_MASK_EN_B 0x0 |
606 | struct hclge_mac_vlan_mask_entry_cmd { | |
607 | u8 rsv0[2]; | |
608 | u8 vlan_mask; | |
609 | u8 rsv1; | |
610 | u8 mac_mask[6]; | |
611 | u8 rsv2[14]; | |
612 | }; | |
613 | ||
635bfb58 FL |
614 | #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) |
615 | #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) | |
616 | #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) | |
617 | #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc | |
618 | ||
619 | struct hclge_mac_mgr_tbl_entry_cmd { | |
620 | u8 flags; | |
621 | u8 resp_code; | |
622 | __le16 vlan_tag; | |
623 | __le32 mac_addr_hi32; | |
624 | __le16 mac_addr_lo16; | |
625 | __le16 rsv1; | |
626 | __le16 ethter_type; | |
627 | __le16 egress_port; | |
628 | __le16 egress_queue; | |
629 | u8 sw_port_id_aware; | |
630 | u8 rsv2; | |
631 | u8 i_port_bitmap; | |
632 | u8 i_port_direction; | |
633 | u8 rsv3[2]; | |
634 | }; | |
635 | ||
68c0a5c7 | 636 | #define HCLGE_CFG_MTA_MAC_SEL_S 0x0 |
5392902d | 637 | #define HCLGE_CFG_MTA_MAC_SEL_M GENMASK(1, 0) |
68c0a5c7 | 638 | #define HCLGE_CFG_MTA_MAC_EN_B 0x7 |
d44f9b63 | 639 | struct hclge_mta_filter_mode_cmd { |
68c0a5c7 S |
640 | u8 dmac_sel_en; /* Use lowest 2 bit as sel_mode, bit 7 as enable */ |
641 | u8 rsv[23]; | |
642 | }; | |
643 | ||
644 | #define HCLGE_CFG_FUNC_MTA_ACCEPT_B 0x0 | |
d44f9b63 | 645 | struct hclge_cfg_func_mta_filter_cmd { |
68c0a5c7 S |
646 | u8 accept; /* Only used lowest 1 bit */ |
647 | u8 function_id; | |
648 | u8 rsv[22]; | |
649 | }; | |
650 | ||
651 | #define HCLGE_CFG_MTA_ITEM_ACCEPT_B 0x0 | |
652 | #define HCLGE_CFG_MTA_ITEM_IDX_S 0x0 | |
5392902d | 653 | #define HCLGE_CFG_MTA_ITEM_IDX_M GENMASK(11, 0) |
d44f9b63 | 654 | struct hclge_cfg_func_mta_item_cmd { |
a90bb9a5 | 655 | __le16 item_idx; /* Only used lowest 12 bit */ |
68c0a5c7 S |
656 | u8 accept; /* Only used lowest 1 bit */ |
657 | u8 rsv[21]; | |
658 | }; | |
659 | ||
d44f9b63 | 660 | struct hclge_mac_vlan_add_cmd { |
68c0a5c7 S |
661 | __le16 flags; |
662 | __le16 mac_addr_hi16; | |
663 | __le32 mac_addr_lo32; | |
664 | __le32 mac_addr_msk_hi32; | |
665 | __le16 mac_addr_msk_lo16; | |
666 | __le16 vlan_tag; | |
667 | __le16 ingress_port; | |
668 | __le16 egress_port; | |
669 | u8 rsv[4]; | |
670 | }; | |
671 | ||
672 | #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 | |
d44f9b63 | 673 | struct hclge_mac_vlan_remove_cmd { |
68c0a5c7 S |
674 | __le16 flags; |
675 | __le16 mac_addr_hi16; | |
676 | __le32 mac_addr_lo32; | |
677 | __le32 mac_addr_msk_hi32; | |
678 | __le16 mac_addr_msk_lo16; | |
679 | __le16 vlan_tag; | |
680 | __le16 ingress_port; | |
681 | __le16 egress_port; | |
682 | u8 rsv[4]; | |
683 | }; | |
684 | ||
d44f9b63 | 685 | struct hclge_vlan_filter_ctrl_cmd { |
68c0a5c7 S |
686 | u8 vlan_type; |
687 | u8 vlan_fe; | |
688 | u8 rsv[22]; | |
689 | }; | |
690 | ||
d44f9b63 | 691 | struct hclge_vlan_filter_pf_cfg_cmd { |
68c0a5c7 S |
692 | u8 vlan_offset; |
693 | u8 vlan_cfg; | |
694 | u8 rsv[2]; | |
695 | u8 vlan_offset_bitmap[20]; | |
696 | }; | |
697 | ||
d44f9b63 | 698 | struct hclge_vlan_filter_vf_cfg_cmd { |
a90bb9a5 | 699 | __le16 vlan_id; |
68c0a5c7 S |
700 | u8 resp_code; |
701 | u8 rsv; | |
702 | u8 vlan_cfg; | |
703 | u8 rsv1[3]; | |
704 | u8 vf_bitmap[16]; | |
705 | }; | |
706 | ||
b75b1a56 PL |
707 | #define HCLGE_ACCEPT_TAG1_B 0 |
708 | #define HCLGE_ACCEPT_UNTAG1_B 1 | |
e62f2a6b PL |
709 | #define HCLGE_PORT_INS_TAG1_EN_B 2 |
710 | #define HCLGE_PORT_INS_TAG2_EN_B 3 | |
711 | #define HCLGE_CFG_NIC_ROCE_SEL_B 4 | |
b75b1a56 PL |
712 | #define HCLGE_ACCEPT_TAG2_B 5 |
713 | #define HCLGE_ACCEPT_UNTAG2_B 6 | |
714 | ||
e62f2a6b PL |
715 | struct hclge_vport_vtag_tx_cfg_cmd { |
716 | u8 vport_vlan_cfg; | |
717 | u8 vf_offset; | |
718 | u8 rsv1[2]; | |
719 | __le16 def_vlan_tag1; | |
720 | __le16 def_vlan_tag2; | |
721 | u8 vf_bitmap[8]; | |
722 | u8 rsv2[8]; | |
723 | }; | |
724 | ||
725 | #define HCLGE_REM_TAG1_EN_B 0 | |
726 | #define HCLGE_REM_TAG2_EN_B 1 | |
727 | #define HCLGE_SHOW_TAG1_EN_B 2 | |
728 | #define HCLGE_SHOW_TAG2_EN_B 3 | |
729 | struct hclge_vport_vtag_rx_cfg_cmd { | |
730 | u8 vport_vlan_cfg; | |
731 | u8 vf_offset; | |
732 | u8 rsv1[6]; | |
733 | u8 vf_bitmap[8]; | |
734 | u8 rsv2[8]; | |
735 | }; | |
736 | ||
737 | struct hclge_tx_vlan_type_cfg_cmd { | |
738 | __le16 ot_vlan_type; | |
739 | __le16 in_vlan_type; | |
740 | u8 rsv[20]; | |
741 | }; | |
742 | ||
743 | struct hclge_rx_vlan_type_cfg_cmd { | |
744 | __le16 ot_fst_vlan_type; | |
745 | __le16 ot_sec_vlan_type; | |
746 | __le16 in_fst_vlan_type; | |
747 | __le16 in_sec_vlan_type; | |
748 | u8 rsv[16]; | |
749 | }; | |
750 | ||
d44f9b63 | 751 | struct hclge_cfg_com_tqp_queue_cmd { |
68c0a5c7 S |
752 | __le16 tqp_id; |
753 | __le16 stream_id; | |
754 | u8 enable; | |
755 | u8 rsv[19]; | |
756 | }; | |
757 | ||
d44f9b63 | 758 | struct hclge_cfg_tx_queue_pointer_cmd { |
68c0a5c7 S |
759 | __le16 tqp_id; |
760 | __le16 tx_tail; | |
761 | __le16 tx_head; | |
762 | __le16 fbd_num; | |
763 | __le16 ring_offset; | |
764 | u8 rsv[14]; | |
765 | }; | |
766 | ||
767 | #define HCLGE_TSO_MSS_MIN_S 0 | |
5392902d | 768 | #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) |
68c0a5c7 S |
769 | |
770 | #define HCLGE_TSO_MSS_MAX_S 16 | |
5392902d | 771 | #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) |
68c0a5c7 | 772 | |
d44f9b63 | 773 | struct hclge_cfg_tso_status_cmd { |
68c0a5c7 S |
774 | __le16 tso_mss_min; |
775 | __le16 tso_mss_max; | |
776 | u8 rsv[20]; | |
777 | }; | |
778 | ||
779 | #define HCLGE_TSO_MSS_MIN 256 | |
780 | #define HCLGE_TSO_MSS_MAX 9668 | |
781 | ||
782 | #define HCLGE_TQP_RESET_B 0 | |
d44f9b63 | 783 | struct hclge_reset_tqp_queue_cmd { |
68c0a5c7 S |
784 | __le16 tqp_id; |
785 | u8 reset_req; | |
786 | u8 ready_to_reset; | |
787 | u8 rsv[20]; | |
788 | }; | |
789 | ||
4ed340ab L |
790 | #define HCLGE_CFG_RESET_MAC_B 3 |
791 | #define HCLGE_CFG_RESET_FUNC_B 7 | |
792 | struct hclge_reset_cmd { | |
793 | u8 mac_func_reset; | |
794 | u8 fun_reset_vfid; | |
795 | u8 rsv[22]; | |
796 | }; | |
68c0a5c7 S |
797 | #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ |
798 | #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ | |
799 | #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ | |
d221df4e | 800 | #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ |
68c0a5c7 S |
801 | |
802 | #define HCLGE_TYPE_CRQ 0 | |
803 | #define HCLGE_TYPE_CSQ 1 | |
804 | #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 | |
805 | #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 | |
806 | #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 | |
807 | #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 | |
808 | #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 | |
809 | #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 | |
810 | #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c | |
811 | #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 | |
812 | #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 | |
813 | #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 | |
814 | #define HCLGE_NIC_CMQ_EN_B 16 | |
815 | #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) | |
816 | #define HCLGE_NIC_CMQ_DESC_NUM 1024 | |
817 | #define HCLGE_NIC_CMQ_DESC_NUM_S 3 | |
818 | ||
d9a0884e JS |
819 | #define HCLGE_LED_PORT_SPEED_STATE_S 0 |
820 | #define HCLGE_LED_PORT_SPEED_STATE_M GENMASK(5, 0) | |
821 | #define HCLGE_LED_ACTIVITY_STATE_S 0 | |
822 | #define HCLGE_LED_ACTIVITY_STATE_M GENMASK(1, 0) | |
823 | #define HCLGE_LED_LINK_STATE_S 0 | |
824 | #define HCLGE_LED_LINK_STATE_M GENMASK(1, 0) | |
825 | #define HCLGE_LED_LOCATE_STATE_S 0 | |
826 | #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) | |
827 | ||
828 | struct hclge_set_led_state_cmd { | |
829 | u8 port_speed_led_config; | |
830 | u8 link_led_config; | |
831 | u8 activity_led_config; | |
832 | u8 locate_led_config; | |
833 | u8 rsv[20]; | |
834 | }; | |
835 | ||
68c0a5c7 S |
836 | int hclge_cmd_init(struct hclge_dev *hdev); |
837 | static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) | |
838 | { | |
839 | writel(value, base + reg); | |
840 | } | |
841 | ||
842 | #define hclge_write_dev(a, reg, value) \ | |
843 | hclge_write_reg((a)->io_base, (reg), (value)) | |
844 | #define hclge_read_dev(a, reg) \ | |
845 | hclge_read_reg((a)->io_base, (reg)) | |
846 | ||
847 | static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) | |
848 | { | |
849 | u8 __iomem *reg_addr = READ_ONCE(base); | |
850 | ||
851 | return readl(reg_addr + reg); | |
852 | } | |
853 | ||
854 | #define HCLGE_SEND_SYNC(flag) \ | |
855 | ((flag) & HCLGE_CMD_FLAG_NO_INTR) | |
856 | ||
857 | struct hclge_hw; | |
858 | int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); | |
859 | void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, | |
860 | enum hclge_opcode_type opcode, bool is_read); | |
f7db940a | 861 | void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); |
68c0a5c7 S |
862 | |
863 | int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, | |
864 | struct hclge_promisc_param *param); | |
865 | ||
866 | enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, | |
867 | struct hclge_desc *desc); | |
868 | enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, | |
869 | struct hclge_desc *desc); | |
870 | ||
871 | void hclge_destroy_cmd_queue(struct hclge_hw *hw); | |
3efb960f | 872 | int hclge_cmd_queue_init(struct hclge_dev *hdev); |
68c0a5c7 | 873 | #endif |