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Commit | Line | Data |
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ef57c40f JS |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // Copyright (c) 2016-2017 Hisilicon Limited. | |
68c0a5c7 S |
3 | |
4 | #ifndef __HCLGE_CMD_H | |
5 | #define __HCLGE_CMD_H | |
6 | #include <linux/types.h> | |
7 | #include <linux/io.h> | |
8 | ||
ff824288 | 9 | #define HCLGE_CMDQ_TX_TIMEOUT 30000 |
68c0a5c7 S |
10 | |
11 | struct hclge_dev; | |
12 | struct hclge_desc { | |
13 | __le16 opcode; | |
14 | ||
15 | #define HCLGE_CMDQ_RX_INVLD_B 0 | |
16 | #define HCLGE_CMDQ_RX_OUTVLD_B 1 | |
17 | ||
18 | __le16 flag; | |
19 | __le16 retval; | |
20 | __le16 rsv; | |
21 | __le32 data[6]; | |
22 | }; | |
23 | ||
68c0a5c7 S |
24 | struct hclge_cmq_ring { |
25 | dma_addr_t desc_dma_addr; | |
26 | struct hclge_desc *desc; | |
2bf8098b | 27 | struct hclge_dev *dev; |
68c0a5c7 S |
28 | u32 head; |
29 | u32 tail; | |
30 | ||
31 | u16 buf_size; | |
32 | u16 desc_num; | |
33 | int next_to_use; | |
34 | int next_to_clean; | |
5a8b1a40 | 35 | u8 ring_type; /* cmq ring type */ |
68c0a5c7 S |
36 | spinlock_t lock; /* Command queue lock */ |
37 | }; | |
38 | ||
39 | enum hclge_cmd_return_status { | |
40 | HCLGE_CMD_EXEC_SUCCESS = 0, | |
41 | HCLGE_CMD_NO_AUTH = 1, | |
42 | HCLGE_CMD_NOT_EXEC = 2, | |
43 | HCLGE_CMD_QUEUE_FULL = 3, | |
44 | }; | |
45 | ||
46 | enum hclge_cmd_status { | |
47 | HCLGE_STATUS_SUCCESS = 0, | |
48 | HCLGE_ERR_CSQ_FULL = -1, | |
49 | HCLGE_ERR_CSQ_TIMEOUT = -2, | |
50 | HCLGE_ERR_CSQ_ERROR = -3, | |
51 | }; | |
52 | ||
466b0c00 L |
53 | struct hclge_misc_vector { |
54 | u8 __iomem *addr; | |
55 | int vector_irq; | |
56 | }; | |
57 | ||
68c0a5c7 S |
58 | struct hclge_cmq { |
59 | struct hclge_cmq_ring csq; | |
60 | struct hclge_cmq_ring crq; | |
f73c9107 | 61 | u16 tx_timeout; |
68c0a5c7 S |
62 | enum hclge_cmd_status last_status; |
63 | }; | |
64 | ||
e23e21ea JS |
65 | #define HCLGE_CMD_FLAG_IN BIT(0) |
66 | #define HCLGE_CMD_FLAG_OUT BIT(1) | |
67 | #define HCLGE_CMD_FLAG_NEXT BIT(2) | |
68 | #define HCLGE_CMD_FLAG_WR BIT(3) | |
69 | #define HCLGE_CMD_FLAG_NO_INTR BIT(4) | |
70 | #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) | |
68c0a5c7 S |
71 | |
72 | enum hclge_opcode_type { | |
f73c9107 | 73 | /* Generic commands */ |
68c0a5c7 S |
74 | HCLGE_OPC_QUERY_FW_VER = 0x0001, |
75 | HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, | |
76 | HCLGE_OPC_GBL_RST_STATUS = 0x0021, | |
77 | HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, | |
78 | HCLGE_OPC_QUERY_PF_RSRC = 0x0023, | |
79 | HCLGE_OPC_QUERY_VF_RSRC = 0x0024, | |
80 | HCLGE_OPC_GET_CFG_PARAM = 0x0025, | |
81 | ||
82 | HCLGE_OPC_STATS_64_BIT = 0x0030, | |
83 | HCLGE_OPC_STATS_32_BIT = 0x0031, | |
84 | HCLGE_OPC_STATS_MAC = 0x0032, | |
db2a3e43 FL |
85 | |
86 | HCLGE_OPC_QUERY_REG_NUM = 0x0040, | |
87 | HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, | |
88 | HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, | |
68c0a5c7 | 89 | |
f73c9107 | 90 | /* MAC command */ |
68c0a5c7 S |
91 | HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, |
92 | HCLGE_OPC_CONFIG_AN_MODE = 0x0304, | |
93 | HCLGE_OPC_QUERY_AN_RESULT = 0x0306, | |
94 | HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, | |
95 | HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, | |
96 | HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, | |
e006bb00 | 97 | HCLGE_OPC_SERDES_LOOPBACK = 0x0315, |
68c0a5c7 | 98 | |
f73c9107 | 99 | /* PFC/Pause commands */ |
68c0a5c7 S |
100 | HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, |
101 | HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, | |
102 | HCLGE_OPC_CFG_MAC_PARA = 0x0703, | |
103 | HCLGE_OPC_CFG_PFC_PARA = 0x0704, | |
104 | HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, | |
105 | HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, | |
106 | HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, | |
107 | HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, | |
108 | HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, | |
109 | HCLGE_OPC_QOS_MAP = 0x070A, | |
110 | ||
111 | /* ETS/scheduler commands */ | |
112 | HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, | |
113 | HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, | |
114 | HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, | |
115 | HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, | |
116 | HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, | |
117 | HCLGE_OPC_TM_PG_WEIGHT = 0x0809, | |
118 | HCLGE_OPC_TM_QS_WEIGHT = 0x080A, | |
119 | HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, | |
120 | HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, | |
121 | HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, | |
122 | HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, | |
123 | HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, | |
124 | HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, | |
125 | HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, | |
126 | HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, | |
127 | HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, | |
128 | HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, | |
129 | ||
f73c9107 | 130 | /* Packet buffer allocate commands */ |
68c0a5c7 S |
131 | HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, |
132 | HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, | |
133 | HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, | |
134 | HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, | |
135 | HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, | |
136 | HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, | |
137 | ||
68c0a5c7 S |
138 | /* TQP management command */ |
139 | HCLGE_OPC_SET_TQP_MAP = 0x0A01, | |
140 | ||
f73c9107 | 141 | /* TQP commands */ |
68c0a5c7 S |
142 | HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, |
143 | HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, | |
144 | HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, | |
145 | HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, | |
146 | HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, | |
147 | HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, | |
148 | HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, | |
149 | HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, | |
150 | HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, | |
151 | HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, | |
152 | ||
f73c9107 | 153 | /* TSO command */ |
68c0a5c7 S |
154 | HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, |
155 | ||
f73c9107 | 156 | /* RSS commands */ |
68c0a5c7 S |
157 | HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, |
158 | HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, | |
159 | HCLGE_OPC_RSS_TC_MODE = 0x0D08, | |
160 | HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, | |
161 | ||
162 | /* Promisuous mode command */ | |
163 | HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, | |
164 | ||
f73c9107 | 165 | /* Vlan offload commands */ |
e62f2a6b PL |
166 | HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, |
167 | HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, | |
168 | ||
f73c9107 | 169 | /* Interrupts commands */ |
68c0a5c7 S |
170 | HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, |
171 | HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, | |
172 | ||
f73c9107 | 173 | /* MAC commands */ |
68c0a5c7 S |
174 | HCLGE_OPC_MAC_VLAN_ADD = 0x1000, |
175 | HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, | |
176 | HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, | |
177 | HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, | |
2da5ec58 | 178 | HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, |
68c0a5c7 S |
179 | HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, |
180 | HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, | |
181 | ||
f73c9107 | 182 | /* VLAN commands */ |
68c0a5c7 S |
183 | HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, |
184 | HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, | |
185 | HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, | |
186 | ||
10a954bc JS |
187 | /* Flow Director commands */ |
188 | HCLGE_OPC_FD_MODE_CTRL = 0x1200, | |
189 | HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, | |
190 | HCLGE_OPC_FD_KEY_CONFIG = 0x1202, | |
7b829126 JS |
191 | HCLGE_OPC_FD_TCAM_OP = 0x1203, |
192 | HCLGE_OPC_FD_AD_OP = 0x1204, | |
10a954bc | 193 | |
68c0a5c7 S |
194 | /* MDIO command */ |
195 | HCLGE_OPC_MDIO_CONFIG = 0x1900, | |
196 | ||
f73c9107 | 197 | /* QCN commands */ |
68c0a5c7 S |
198 | HCLGE_OPC_QCN_MOD_CFG = 0x1A01, |
199 | HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, | |
200 | HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, | |
201 | HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, | |
202 | HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, | |
203 | HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, | |
204 | HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, | |
205 | HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, | |
206 | ||
f73c9107 | 207 | /* Mailbox command */ |
68c0a5c7 | 208 | HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, |
d9a0884e JS |
209 | |
210 | /* Led command */ | |
211 | HCLGE_OPC_LED_STATUS_CFG = 0xB000, | |
8b684fc7 SJ |
212 | |
213 | /* Error INT commands */ | |
214 | HCLGE_COMMON_ECC_INT_CFG = 0x1505, | |
d5a2e3fc SJ |
215 | HCLGE_IGU_EGU_TNL_INT_QUERY = 0x1802, |
216 | HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, | |
217 | HCLGE_IGU_EGU_TNL_INT_CLR = 0x1804, | |
218 | HCLGE_IGU_COMMON_INT_QUERY = 0x1805, | |
219 | HCLGE_IGU_COMMON_INT_EN = 0x1806, | |
220 | HCLGE_IGU_COMMON_INT_CLR = 0x1807, | |
d1cc1b84 SJ |
221 | HCLGE_PPP_CMD0_INT_CMD = 0x2100, |
222 | HCLGE_PPP_CMD1_INT_CMD = 0x2101, | |
d5a2e3fc SJ |
223 | HCLGE_NCSI_INT_QUERY = 0x2400, |
224 | HCLGE_NCSI_INT_EN = 0x2401, | |
225 | HCLGE_NCSI_INT_CLR = 0x2402, | |
68c0a5c7 S |
226 | }; |
227 | ||
228 | #define HCLGE_TQP_REG_OFFSET 0x80000 | |
229 | #define HCLGE_TQP_REG_SIZE 0x200 | |
230 | ||
231 | #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 | |
232 | #define HCLGE_RCB_INIT_FLAG_EN_B 0 | |
233 | #define HCLGE_RCB_INIT_FLAG_FINI_B 8 | |
d44f9b63 | 234 | struct hclge_config_rcb_init_cmd { |
68c0a5c7 S |
235 | __le16 rcb_init_flag; |
236 | u8 rsv[22]; | |
237 | }; | |
238 | ||
d44f9b63 | 239 | struct hclge_tqp_map_cmd { |
68c0a5c7 S |
240 | __le16 tqp_id; /* Absolute tqp id for in this pf */ |
241 | u8 tqp_vf; /* VF id */ | |
242 | #define HCLGE_TQP_MAP_TYPE_PF 0 | |
243 | #define HCLGE_TQP_MAP_TYPE_VF 1 | |
244 | #define HCLGE_TQP_MAP_TYPE_B 0 | |
245 | #define HCLGE_TQP_MAP_EN_B 1 | |
246 | u8 tqp_flag; /* Indicate it's pf or vf tqp */ | |
247 | __le16 tqp_vid; /* Virtual id in this pf/vf */ | |
248 | u8 rsv[18]; | |
249 | }; | |
250 | ||
0305b443 | 251 | #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 |
68c0a5c7 S |
252 | |
253 | enum hclge_int_type { | |
254 | HCLGE_INT_TX, | |
255 | HCLGE_INT_RX, | |
256 | HCLGE_INT_EVENT, | |
257 | }; | |
258 | ||
d44f9b63 | 259 | struct hclge_ctrl_vector_chain_cmd { |
68c0a5c7 S |
260 | u8 int_vector_id; |
261 | u8 int_cause_num; | |
262 | #define HCLGE_INT_TYPE_S 0 | |
5392902d | 263 | #define HCLGE_INT_TYPE_M GENMASK(1, 0) |
68c0a5c7 | 264 | #define HCLGE_TQP_ID_S 2 |
5392902d | 265 | #define HCLGE_TQP_ID_M GENMASK(12, 2) |
0305b443 | 266 | #define HCLGE_INT_GL_IDX_S 13 |
5392902d | 267 | #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) |
68c0a5c7 | 268 | __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; |
0305b443 L |
269 | u8 vfid; |
270 | u8 rsv; | |
68c0a5c7 S |
271 | }; |
272 | ||
273 | #define HCLGE_TC_NUM 8 | |
274 | #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ | |
275 | #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ | |
d44f9b63 | 276 | struct hclge_tx_buff_alloc_cmd { |
68c0a5c7 S |
277 | __le16 tx_pkt_buff[HCLGE_TC_NUM]; |
278 | u8 tx_buff_rsv[8]; | |
279 | }; | |
280 | ||
d44f9b63 | 281 | struct hclge_rx_priv_buff_cmd { |
68c0a5c7 | 282 | __le16 buf_num[HCLGE_TC_NUM]; |
b8c8bf47 YL |
283 | __le16 shared_buf; |
284 | u8 rsv[6]; | |
68c0a5c7 S |
285 | }; |
286 | ||
d44f9b63 | 287 | struct hclge_query_version_cmd { |
68c0a5c7 S |
288 | __le32 firmware; |
289 | __le32 firmware_rsv[5]; | |
290 | }; | |
291 | ||
292 | #define HCLGE_RX_PRIV_EN_B 15 | |
293 | #define HCLGE_TC_NUM_ONE_DESC 4 | |
294 | struct hclge_priv_wl { | |
295 | __le16 high; | |
296 | __le16 low; | |
297 | }; | |
298 | ||
299 | struct hclge_rx_priv_wl_buf { | |
300 | struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; | |
301 | }; | |
302 | ||
303 | struct hclge_rx_com_thrd { | |
304 | struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; | |
305 | }; | |
306 | ||
307 | struct hclge_rx_com_wl { | |
308 | struct hclge_priv_wl com_wl; | |
309 | }; | |
310 | ||
311 | struct hclge_waterline { | |
312 | u32 low; | |
313 | u32 high; | |
314 | }; | |
315 | ||
316 | struct hclge_tc_thrd { | |
317 | u32 low; | |
318 | u32 high; | |
319 | }; | |
320 | ||
321 | struct hclge_priv_buf { | |
322 | struct hclge_waterline wl; /* Waterline for low and high*/ | |
323 | u32 buf_size; /* TC private buffer size */ | |
9ffe79a9 | 324 | u32 tx_buf_size; |
68c0a5c7 S |
325 | u32 enable; /* Enable TC private buffer or not */ |
326 | }; | |
327 | ||
328 | #define HCLGE_MAX_TC_NUM 8 | |
329 | struct hclge_shared_buf { | |
330 | struct hclge_waterline self; | |
331 | struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; | |
332 | u32 buf_size; | |
333 | }; | |
334 | ||
acf61ecd YL |
335 | struct hclge_pkt_buf_alloc { |
336 | struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; | |
337 | struct hclge_shared_buf s_buf; | |
338 | }; | |
339 | ||
68c0a5c7 | 340 | #define HCLGE_RX_COM_WL_EN_B 15 |
d44f9b63 | 341 | struct hclge_rx_com_wl_buf_cmd { |
68c0a5c7 S |
342 | __le16 high_wl; |
343 | __le16 low_wl; | |
344 | u8 rsv[20]; | |
345 | }; | |
346 | ||
347 | #define HCLGE_RX_PKT_EN_B 15 | |
d44f9b63 | 348 | struct hclge_rx_pkt_buf_cmd { |
68c0a5c7 S |
349 | __le16 high_pkt; |
350 | __le16 low_pkt; | |
351 | u8 rsv[20]; | |
352 | }; | |
353 | ||
354 | #define HCLGE_PF_STATE_DONE_B 0 | |
355 | #define HCLGE_PF_STATE_MAIN_B 1 | |
356 | #define HCLGE_PF_STATE_BOND_B 2 | |
357 | #define HCLGE_PF_STATE_MAC_N_B 6 | |
358 | #define HCLGE_PF_MAC_NUM_MASK 0x3 | |
359 | #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) | |
360 | #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) | |
d44f9b63 | 361 | struct hclge_func_status_cmd { |
68c0a5c7 S |
362 | __le32 vf_rst_state[4]; |
363 | u8 pf_state; | |
364 | u8 mac_id; | |
365 | u8 rsv1; | |
366 | u8 pf_cnt_in_mac; | |
367 | u8 pf_num; | |
368 | u8 vf_num; | |
369 | u8 rsv[2]; | |
370 | }; | |
371 | ||
d44f9b63 | 372 | struct hclge_pf_res_cmd { |
68c0a5c7 S |
373 | __le16 tqp_num; |
374 | __le16 buf_size; | |
375 | __le16 msixcap_localid_ba_nic; | |
376 | __le16 msixcap_localid_ba_rocee; | |
5355e6d3 JS |
377 | #define HCLGE_MSIX_OFT_ROCEE_S 0 |
378 | #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) | |
68c0a5c7 | 379 | #define HCLGE_PF_VEC_NUM_S 0 |
e23e21ea | 380 | #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) |
68c0a5c7 S |
381 | __le16 pf_intr_vector_number; |
382 | __le16 pf_own_fun_number; | |
383 | __le32 rsv[3]; | |
384 | }; | |
385 | ||
386 | #define HCLGE_CFG_OFFSET_S 0 | |
5392902d | 387 | #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) |
68c0a5c7 | 388 | #define HCLGE_CFG_RD_LEN_S 24 |
5392902d | 389 | #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) |
68c0a5c7 S |
390 | #define HCLGE_CFG_RD_LEN_BYTES 16 |
391 | #define HCLGE_CFG_RD_LEN_UNIT 4 | |
392 | ||
393 | #define HCLGE_CFG_VMDQ_S 0 | |
5392902d | 394 | #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) |
68c0a5c7 | 395 | #define HCLGE_CFG_TC_NUM_S 8 |
5392902d | 396 | #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) |
68c0a5c7 | 397 | #define HCLGE_CFG_TQP_DESC_N_S 16 |
5392902d | 398 | #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) |
68c0a5c7 | 399 | #define HCLGE_CFG_PHY_ADDR_S 0 |
39e2151f | 400 | #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) |
68c0a5c7 | 401 | #define HCLGE_CFG_MEDIA_TP_S 8 |
5392902d | 402 | #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) |
68c0a5c7 | 403 | #define HCLGE_CFG_RX_BUF_LEN_S 16 |
5392902d | 404 | #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) |
68c0a5c7 | 405 | #define HCLGE_CFG_MAC_ADDR_H_S 0 |
5392902d | 406 | #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) |
68c0a5c7 | 407 | #define HCLGE_CFG_DEFAULT_SPEED_S 16 |
5392902d | 408 | #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) |
c408e202 PL |
409 | #define HCLGE_CFG_RSS_SIZE_S 24 |
410 | #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) | |
d92ceae9 FL |
411 | #define HCLGE_CFG_SPEED_ABILITY_S 0 |
412 | #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) | |
2da5ec58 JS |
413 | #define HCLGE_CFG_UMV_TBL_SPACE_S 16 |
414 | #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) | |
68c0a5c7 | 415 | |
d44f9b63 | 416 | struct hclge_cfg_param_cmd { |
68c0a5c7 S |
417 | __le32 offset; |
418 | __le32 rsv; | |
419 | __le32 param[4]; | |
420 | }; | |
421 | ||
422 | #define HCLGE_MAC_MODE 0x0 | |
423 | #define HCLGE_DESC_NUM 0x40 | |
424 | ||
425 | #define HCLGE_ALLOC_VALID_B 0 | |
d44f9b63 | 426 | struct hclge_vf_num_cmd { |
68c0a5c7 S |
427 | u8 alloc_valid; |
428 | u8 rsv[23]; | |
429 | }; | |
430 | ||
431 | #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 | |
432 | #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 | |
433 | #define HCLGE_RSS_HASH_KEY_NUM 16 | |
d44f9b63 | 434 | struct hclge_rss_config_cmd { |
68c0a5c7 S |
435 | u8 hash_config; |
436 | u8 rsv[7]; | |
437 | u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; | |
438 | }; | |
439 | ||
d44f9b63 | 440 | struct hclge_rss_input_tuple_cmd { |
68c0a5c7 S |
441 | u8 ipv4_tcp_en; |
442 | u8 ipv4_udp_en; | |
443 | u8 ipv4_sctp_en; | |
444 | u8 ipv4_fragment_en; | |
445 | u8 ipv6_tcp_en; | |
446 | u8 ipv6_udp_en; | |
447 | u8 ipv6_sctp_en; | |
448 | u8 ipv6_fragment_en; | |
449 | u8 rsv[16]; | |
450 | }; | |
451 | ||
452 | #define HCLGE_RSS_CFG_TBL_SIZE 16 | |
453 | ||
d44f9b63 | 454 | struct hclge_rss_indirection_table_cmd { |
a90bb9a5 YL |
455 | __le16 start_table_index; |
456 | __le16 rss_set_bitmap; | |
68c0a5c7 S |
457 | u8 rsv[4]; |
458 | u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; | |
459 | }; | |
460 | ||
461 | #define HCLGE_RSS_TC_OFFSET_S 0 | |
5392902d | 462 | #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) |
68c0a5c7 | 463 | #define HCLGE_RSS_TC_SIZE_S 12 |
5392902d | 464 | #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) |
68c0a5c7 | 465 | #define HCLGE_RSS_TC_VALID_B 15 |
d44f9b63 | 466 | struct hclge_rss_tc_mode_cmd { |
a90bb9a5 | 467 | __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; |
68c0a5c7 S |
468 | u8 rsv[8]; |
469 | }; | |
470 | ||
e23e21ea JS |
471 | #define HCLGE_LINK_STATUS_UP_B 0 |
472 | #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) | |
d44f9b63 | 473 | struct hclge_link_status_cmd { |
68c0a5c7 S |
474 | u8 status; |
475 | u8 rsv[23]; | |
476 | }; | |
477 | ||
478 | struct hclge_promisc_param { | |
479 | u8 vf_id; | |
480 | u8 enable; | |
481 | }; | |
482 | ||
4771e104 PL |
483 | #define HCLGE_PROMISC_TX_EN_B BIT(4) |
484 | #define HCLGE_PROMISC_RX_EN_B BIT(5) | |
68c0a5c7 S |
485 | #define HCLGE_PROMISC_EN_B 1 |
486 | #define HCLGE_PROMISC_EN_ALL 0x7 | |
487 | #define HCLGE_PROMISC_EN_UC 0x1 | |
488 | #define HCLGE_PROMISC_EN_MC 0x2 | |
489 | #define HCLGE_PROMISC_EN_BC 0x4 | |
d44f9b63 | 490 | struct hclge_promisc_cfg_cmd { |
68c0a5c7 S |
491 | u8 flag; |
492 | u8 vf_id; | |
493 | __le16 rsv0; | |
494 | u8 rsv1[20]; | |
495 | }; | |
496 | ||
497 | enum hclge_promisc_type { | |
498 | HCLGE_UNICAST = 1, | |
499 | HCLGE_MULTICAST = 2, | |
500 | HCLGE_BROADCAST = 3, | |
501 | }; | |
502 | ||
503 | #define HCLGE_MAC_TX_EN_B 6 | |
504 | #define HCLGE_MAC_RX_EN_B 7 | |
505 | #define HCLGE_MAC_PAD_TX_B 11 | |
506 | #define HCLGE_MAC_PAD_RX_B 12 | |
507 | #define HCLGE_MAC_1588_TX_B 13 | |
508 | #define HCLGE_MAC_1588_RX_B 14 | |
509 | #define HCLGE_MAC_APP_LP_B 15 | |
510 | #define HCLGE_MAC_LINE_LP_B 16 | |
511 | #define HCLGE_MAC_FCS_TX_B 17 | |
512 | #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 | |
513 | #define HCLGE_MAC_RX_FCS_STRIP_B 19 | |
514 | #define HCLGE_MAC_RX_FCS_B 20 | |
515 | #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 | |
516 | #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 | |
517 | ||
d44f9b63 | 518 | struct hclge_config_mac_mode_cmd { |
68c0a5c7 S |
519 | __le32 txrx_pad_fcs_loop_en; |
520 | u8 rsv[20]; | |
521 | }; | |
522 | ||
523 | #define HCLGE_CFG_SPEED_S 0 | |
5392902d | 524 | #define HCLGE_CFG_SPEED_M GENMASK(5, 0) |
68c0a5c7 S |
525 | |
526 | #define HCLGE_CFG_DUPLEX_B 7 | |
527 | #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) | |
528 | ||
d44f9b63 | 529 | struct hclge_config_mac_speed_dup_cmd { |
68c0a5c7 S |
530 | u8 speed_dup; |
531 | ||
532 | #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 | |
533 | u8 mac_change_fec_en; | |
534 | u8 rsv[22]; | |
535 | }; | |
536 | ||
537 | #define HCLGE_QUERY_SPEED_S 3 | |
538 | #define HCLGE_QUERY_AN_B 0 | |
539 | #define HCLGE_QUERY_DUPLEX_B 2 | |
540 | ||
5392902d | 541 | #define HCLGE_QUERY_SPEED_M GENMASK(4, 0) |
68c0a5c7 S |
542 | #define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B) |
543 | #define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B) | |
544 | ||
d44f9b63 | 545 | struct hclge_query_an_speed_dup_cmd { |
68c0a5c7 S |
546 | u8 an_syn_dup_speed; |
547 | u8 pause; | |
548 | u8 rsv[23]; | |
549 | }; | |
550 | ||
5392902d | 551 | #define HCLGE_RING_ID_MASK GENMASK(9, 0) |
68c0a5c7 S |
552 | #define HCLGE_TQP_ENABLE_B 0 |
553 | ||
554 | #define HCLGE_MAC_CFG_AN_EN_B 0 | |
555 | #define HCLGE_MAC_CFG_AN_INT_EN_B 1 | |
556 | #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 | |
557 | #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 | |
558 | #define HCLGE_MAC_CFG_AN_RST_B 4 | |
559 | ||
560 | #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) | |
561 | ||
d44f9b63 | 562 | struct hclge_config_auto_neg_cmd { |
68c0a5c7 S |
563 | __le32 cfg_an_cmd_flag; |
564 | u8 rsv[20]; | |
565 | }; | |
566 | ||
68c0a5c7 S |
567 | #define HCLGE_MAC_UPLINK_PORT 0x100 |
568 | ||
d44f9b63 | 569 | struct hclge_config_max_frm_size_cmd { |
68c0a5c7 | 570 | __le16 max_frm_size; |
b86fdbf3 JS |
571 | u8 min_frm_size; |
572 | u8 rsv[21]; | |
68c0a5c7 S |
573 | }; |
574 | ||
575 | enum hclge_mac_vlan_tbl_opcode { | |
576 | HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ | |
577 | HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ | |
578 | HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ | |
579 | HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ | |
580 | }; | |
581 | ||
ada89276 JS |
582 | #define HCLGE_MAC_VLAN_BIT0_EN_B 0 |
583 | #define HCLGE_MAC_VLAN_BIT1_EN_B 1 | |
584 | #define HCLGE_MAC_EPORT_SW_EN_B 12 | |
585 | #define HCLGE_MAC_EPORT_TYPE_B 11 | |
586 | #define HCLGE_MAC_EPORT_VFID_S 3 | |
5392902d | 587 | #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) |
ada89276 | 588 | #define HCLGE_MAC_EPORT_PFID_S 0 |
5392902d | 589 | #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) |
d44f9b63 | 590 | struct hclge_mac_vlan_tbl_entry_cmd { |
68c0a5c7 S |
591 | u8 flags; |
592 | u8 resp_code; | |
593 | __le16 vlan_tag; | |
594 | __le32 mac_addr_hi32; | |
595 | __le16 mac_addr_lo16; | |
596 | __le16 rsv1; | |
597 | u8 entry_type; | |
598 | u8 mc_mac_en; | |
599 | __le16 egress_port; | |
600 | __le16 egress_queue; | |
601 | u8 rsv2[6]; | |
602 | }; | |
603 | ||
2da5ec58 JS |
604 | #define HCLGE_UMV_SPC_ALC_B 0 |
605 | struct hclge_umv_spc_alc_cmd { | |
606 | u8 allocate; | |
607 | u8 rsv1[3]; | |
608 | __le32 space_size; | |
609 | u8 rsv2[16]; | |
610 | }; | |
611 | ||
635bfb58 FL |
612 | #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) |
613 | #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) | |
614 | #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) | |
615 | #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc | |
616 | ||
617 | struct hclge_mac_mgr_tbl_entry_cmd { | |
618 | u8 flags; | |
619 | u8 resp_code; | |
620 | __le16 vlan_tag; | |
621 | __le32 mac_addr_hi32; | |
622 | __le16 mac_addr_lo16; | |
623 | __le16 rsv1; | |
624 | __le16 ethter_type; | |
625 | __le16 egress_port; | |
626 | __le16 egress_queue; | |
627 | u8 sw_port_id_aware; | |
628 | u8 rsv2; | |
629 | u8 i_port_bitmap; | |
630 | u8 i_port_direction; | |
631 | u8 rsv3[2]; | |
632 | }; | |
633 | ||
d44f9b63 | 634 | struct hclge_mac_vlan_add_cmd { |
68c0a5c7 S |
635 | __le16 flags; |
636 | __le16 mac_addr_hi16; | |
637 | __le32 mac_addr_lo32; | |
638 | __le32 mac_addr_msk_hi32; | |
639 | __le16 mac_addr_msk_lo16; | |
640 | __le16 vlan_tag; | |
641 | __le16 ingress_port; | |
642 | __le16 egress_port; | |
643 | u8 rsv[4]; | |
644 | }; | |
645 | ||
646 | #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 | |
d44f9b63 | 647 | struct hclge_mac_vlan_remove_cmd { |
68c0a5c7 S |
648 | __le16 flags; |
649 | __le16 mac_addr_hi16; | |
650 | __le32 mac_addr_lo32; | |
651 | __le32 mac_addr_msk_hi32; | |
652 | __le16 mac_addr_msk_lo16; | |
653 | __le16 vlan_tag; | |
654 | __le16 ingress_port; | |
655 | __le16 egress_port; | |
656 | u8 rsv[4]; | |
657 | }; | |
658 | ||
d44f9b63 | 659 | struct hclge_vlan_filter_ctrl_cmd { |
68c0a5c7 S |
660 | u8 vlan_type; |
661 | u8 vlan_fe; | |
662 | u8 rsv[22]; | |
663 | }; | |
664 | ||
d44f9b63 | 665 | struct hclge_vlan_filter_pf_cfg_cmd { |
68c0a5c7 S |
666 | u8 vlan_offset; |
667 | u8 vlan_cfg; | |
668 | u8 rsv[2]; | |
669 | u8 vlan_offset_bitmap[20]; | |
670 | }; | |
671 | ||
d44f9b63 | 672 | struct hclge_vlan_filter_vf_cfg_cmd { |
a90bb9a5 | 673 | __le16 vlan_id; |
68c0a5c7 S |
674 | u8 resp_code; |
675 | u8 rsv; | |
676 | u8 vlan_cfg; | |
677 | u8 rsv1[3]; | |
678 | u8 vf_bitmap[16]; | |
679 | }; | |
680 | ||
b75b1a56 PL |
681 | #define HCLGE_ACCEPT_TAG1_B 0 |
682 | #define HCLGE_ACCEPT_UNTAG1_B 1 | |
e62f2a6b PL |
683 | #define HCLGE_PORT_INS_TAG1_EN_B 2 |
684 | #define HCLGE_PORT_INS_TAG2_EN_B 3 | |
685 | #define HCLGE_CFG_NIC_ROCE_SEL_B 4 | |
b75b1a56 PL |
686 | #define HCLGE_ACCEPT_TAG2_B 5 |
687 | #define HCLGE_ACCEPT_UNTAG2_B 6 | |
688 | ||
e62f2a6b PL |
689 | struct hclge_vport_vtag_tx_cfg_cmd { |
690 | u8 vport_vlan_cfg; | |
691 | u8 vf_offset; | |
692 | u8 rsv1[2]; | |
693 | __le16 def_vlan_tag1; | |
694 | __le16 def_vlan_tag2; | |
695 | u8 vf_bitmap[8]; | |
696 | u8 rsv2[8]; | |
697 | }; | |
698 | ||
699 | #define HCLGE_REM_TAG1_EN_B 0 | |
700 | #define HCLGE_REM_TAG2_EN_B 1 | |
701 | #define HCLGE_SHOW_TAG1_EN_B 2 | |
702 | #define HCLGE_SHOW_TAG2_EN_B 3 | |
703 | struct hclge_vport_vtag_rx_cfg_cmd { | |
704 | u8 vport_vlan_cfg; | |
705 | u8 vf_offset; | |
706 | u8 rsv1[6]; | |
707 | u8 vf_bitmap[8]; | |
708 | u8 rsv2[8]; | |
709 | }; | |
710 | ||
711 | struct hclge_tx_vlan_type_cfg_cmd { | |
712 | __le16 ot_vlan_type; | |
713 | __le16 in_vlan_type; | |
714 | u8 rsv[20]; | |
715 | }; | |
716 | ||
717 | struct hclge_rx_vlan_type_cfg_cmd { | |
718 | __le16 ot_fst_vlan_type; | |
719 | __le16 ot_sec_vlan_type; | |
720 | __le16 in_fst_vlan_type; | |
721 | __le16 in_sec_vlan_type; | |
722 | u8 rsv[16]; | |
723 | }; | |
724 | ||
d44f9b63 | 725 | struct hclge_cfg_com_tqp_queue_cmd { |
68c0a5c7 S |
726 | __le16 tqp_id; |
727 | __le16 stream_id; | |
728 | u8 enable; | |
729 | u8 rsv[19]; | |
730 | }; | |
731 | ||
d44f9b63 | 732 | struct hclge_cfg_tx_queue_pointer_cmd { |
68c0a5c7 S |
733 | __le16 tqp_id; |
734 | __le16 tx_tail; | |
735 | __le16 tx_head; | |
736 | __le16 fbd_num; | |
737 | __le16 ring_offset; | |
738 | u8 rsv[14]; | |
739 | }; | |
740 | ||
741 | #define HCLGE_TSO_MSS_MIN_S 0 | |
5392902d | 742 | #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) |
68c0a5c7 S |
743 | |
744 | #define HCLGE_TSO_MSS_MAX_S 16 | |
5392902d | 745 | #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) |
68c0a5c7 | 746 | |
d44f9b63 | 747 | struct hclge_cfg_tso_status_cmd { |
68c0a5c7 S |
748 | __le16 tso_mss_min; |
749 | __le16 tso_mss_max; | |
750 | u8 rsv[20]; | |
751 | }; | |
752 | ||
753 | #define HCLGE_TSO_MSS_MIN 256 | |
754 | #define HCLGE_TSO_MSS_MAX 9668 | |
755 | ||
756 | #define HCLGE_TQP_RESET_B 0 | |
d44f9b63 | 757 | struct hclge_reset_tqp_queue_cmd { |
68c0a5c7 S |
758 | __le16 tqp_id; |
759 | u8 reset_req; | |
760 | u8 ready_to_reset; | |
761 | u8 rsv[20]; | |
762 | }; | |
763 | ||
4ed340ab L |
764 | #define HCLGE_CFG_RESET_MAC_B 3 |
765 | #define HCLGE_CFG_RESET_FUNC_B 7 | |
766 | struct hclge_reset_cmd { | |
767 | u8 mac_func_reset; | |
768 | u8 fun_reset_vfid; | |
769 | u8 rsv[22]; | |
770 | }; | |
e006bb00 PL |
771 | |
772 | #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) | |
86957272 | 773 | #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) |
e006bb00 PL |
774 | #define HCLGE_CMD_SERDES_DONE_B BIT(0) |
775 | #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) | |
776 | struct hclge_serdes_lb_cmd { | |
777 | u8 mask; | |
778 | u8 enable; | |
779 | u8 result; | |
780 | u8 rsv[21]; | |
781 | }; | |
782 | ||
68c0a5c7 S |
783 | #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ |
784 | #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ | |
785 | #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ | |
d221df4e | 786 | #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ |
68c0a5c7 S |
787 | |
788 | #define HCLGE_TYPE_CRQ 0 | |
789 | #define HCLGE_TYPE_CSQ 1 | |
790 | #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 | |
791 | #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 | |
792 | #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 | |
793 | #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 | |
794 | #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 | |
795 | #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 | |
796 | #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c | |
797 | #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 | |
798 | #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 | |
799 | #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 | |
800 | #define HCLGE_NIC_CMQ_EN_B 16 | |
801 | #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) | |
802 | #define HCLGE_NIC_CMQ_DESC_NUM 1024 | |
803 | #define HCLGE_NIC_CMQ_DESC_NUM_S 3 | |
804 | ||
d9a0884e JS |
805 | #define HCLGE_LED_LOCATE_STATE_S 0 |
806 | #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) | |
807 | ||
808 | struct hclge_set_led_state_cmd { | |
fe3a3e15 | 809 | u8 rsv1[3]; |
d9a0884e | 810 | u8 locate_led_config; |
fe3a3e15 | 811 | u8 rsv2[20]; |
d9a0884e JS |
812 | }; |
813 | ||
10a954bc JS |
814 | struct hclge_get_fd_mode_cmd { |
815 | u8 mode; | |
816 | u8 enable; | |
817 | u8 rsv[22]; | |
818 | }; | |
819 | ||
820 | struct hclge_get_fd_allocation_cmd { | |
821 | __le32 stage1_entry_num; | |
822 | __le32 stage2_entry_num; | |
823 | __le16 stage1_counter_num; | |
824 | __le16 stage2_counter_num; | |
825 | u8 rsv[12]; | |
826 | }; | |
827 | ||
828 | struct hclge_set_fd_key_config_cmd { | |
829 | u8 stage; | |
830 | u8 key_select; | |
831 | u8 inner_sipv6_word_en; | |
832 | u8 inner_dipv6_word_en; | |
833 | u8 outer_sipv6_word_en; | |
834 | u8 outer_dipv6_word_en; | |
835 | u8 rsv1[2]; | |
836 | __le32 tuple_mask; | |
837 | __le32 meta_data_mask; | |
838 | u8 rsv2[8]; | |
839 | }; | |
840 | ||
7b829126 JS |
841 | #define HCLGE_FD_EPORT_SW_EN_B 0 |
842 | struct hclge_fd_tcam_config_1_cmd { | |
843 | u8 stage; | |
844 | u8 xy_sel; | |
845 | u8 port_info; | |
846 | u8 rsv1[1]; | |
847 | __le32 index; | |
848 | u8 entry_vld; | |
849 | u8 rsv2[7]; | |
850 | u8 tcam_data[8]; | |
851 | }; | |
852 | ||
853 | struct hclge_fd_tcam_config_2_cmd { | |
854 | u8 tcam_data[24]; | |
855 | }; | |
856 | ||
857 | struct hclge_fd_tcam_config_3_cmd { | |
858 | u8 tcam_data[20]; | |
859 | u8 rsv[4]; | |
860 | }; | |
861 | ||
862 | #define HCLGE_FD_AD_DROP_B 0 | |
863 | #define HCLGE_FD_AD_DIRECT_QID_B 1 | |
864 | #define HCLGE_FD_AD_QID_S 2 | |
865 | #define HCLGE_FD_AD_QID_M GENMASK(12, 2) | |
866 | #define HCLGE_FD_AD_USE_COUNTER_B 12 | |
867 | #define HCLGE_FD_AD_COUNTER_NUM_S 13 | |
868 | #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) | |
869 | #define HCLGE_FD_AD_NXT_STEP_B 20 | |
870 | #define HCLGE_FD_AD_NXT_KEY_S 21 | |
871 | #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) | |
872 | #define HCLGE_FD_AD_WR_RULE_ID_B 0 | |
873 | #define HCLGE_FD_AD_RULE_ID_S 1 | |
874 | #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) | |
875 | ||
876 | struct hclge_fd_ad_config_cmd { | |
877 | u8 stage; | |
878 | u8 rsv1[3]; | |
879 | __le32 index; | |
880 | __le64 ad_data; | |
881 | u8 rsv2[8]; | |
882 | }; | |
883 | ||
68c0a5c7 S |
884 | int hclge_cmd_init(struct hclge_dev *hdev); |
885 | static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) | |
886 | { | |
887 | writel(value, base + reg); | |
888 | } | |
889 | ||
890 | #define hclge_write_dev(a, reg, value) \ | |
891 | hclge_write_reg((a)->io_base, (reg), (value)) | |
892 | #define hclge_read_dev(a, reg) \ | |
893 | hclge_read_reg((a)->io_base, (reg)) | |
894 | ||
895 | static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) | |
896 | { | |
897 | u8 __iomem *reg_addr = READ_ONCE(base); | |
898 | ||
899 | return readl(reg_addr + reg); | |
900 | } | |
901 | ||
902 | #define HCLGE_SEND_SYNC(flag) \ | |
903 | ((flag) & HCLGE_CMD_FLAG_NO_INTR) | |
904 | ||
905 | struct hclge_hw; | |
906 | int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); | |
907 | void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, | |
908 | enum hclge_opcode_type opcode, bool is_read); | |
f7db940a | 909 | void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); |
68c0a5c7 S |
910 | |
911 | int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, | |
912 | struct hclge_promisc_param *param); | |
913 | ||
914 | enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, | |
915 | struct hclge_desc *desc); | |
916 | enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, | |
917 | struct hclge_desc *desc); | |
918 | ||
919 | void hclge_destroy_cmd_queue(struct hclge_hw *hw); | |
3efb960f | 920 | int hclge_cmd_queue_init(struct hclge_dev *hdev); |
68c0a5c7 | 921 | #endif |