[mirror_ubuntu-kernels.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_err.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*  Copyright (c) 2016-2017 Hisilicon Limited. */

#ifndef __HCLGE_ERR_H
#define __HCLGE_ERR_H

#include "hclge_main.h"
#include "hnae3.h"

#define HCLGE_MPF_RAS_INT_MIN_BD_NUM	10
#define HCLGE_PF_RAS_INT_MIN_BD_NUM	4
#define HCLGE_MPF_MSIX_INT_MIN_BD_NUM	10
#define HCLGE_PF_MSIX_INT_MIN_BD_NUM	4

#define HCLGE_RAS_PF_OTHER_INT_STS_REG   0x20B00
#define HCLGE_RAS_REG_NFE_MASK   0xFF00
#define HCLGE_RAS_REG_ROCEE_ERR_MASK   0x3000000
#define HCLGE_RAS_REG_ERR_MASK \
	(HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK)

#define HCLGE_VECTOR0_REG_MSIX_MASK   0x1FF00

#define HCLGE_IMP_TCM_ECC_ERR_INT_EN	0xFFFF0000
#define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK	0xFFFF0000
#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN	0x300
#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK	0x300
#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN	0xFFFF
#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK	0xFFFF
#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN	0xFFFF0000
#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK	0xFFFF0000
#define HCLGE_IMP_RD_POISON_ERR_INT_EN	0x0100
#define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK	0x0100
#define HCLGE_TQP_ECC_ERR_INT_EN	0x0FFF
#define HCLGE_TQP_ECC_ERR_INT_EN_MASK	0x0FFF
#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK	0x0F000000
#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN	0x0F000000
#define HCLGE_IGU_ERR_INT_EN	0x0000000F
#define HCLGE_IGU_ERR_INT_TYPE	0x00000660
#define HCLGE_IGU_ERR_INT_EN_MASK	0x000F
#define HCLGE_IGU_TNL_ERR_INT_EN    0x0002AABF
#define HCLGE_IGU_TNL_ERR_INT_EN_MASK  0x003F
#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN	0xFFFFFFFF
#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK	0xFFFFFFFF
#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN	0xFFFFFFFF
#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK	0xFFFFFFFF
#define HCLGE_PPP_PF_ERR_INT_EN	0x0003
#define HCLGE_PPP_PF_ERR_INT_EN_MASK	0x0003
#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN	0x003F
#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK	0x003F
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN	0x003F
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK	0x003F
#define HCLGE_TM_SCH_ECC_ERR_INT_EN	0x3
#define HCLGE_TM_QCN_ERR_INT_TYPE	0x29
#define HCLGE_TM_QCN_FIFO_INT_EN	0xFFFF00
#define HCLGE_TM_QCN_MEM_ERR_INT_EN	0xFFFFFF
#define HCLGE_NCSI_ERR_INT_EN	0x3
#define HCLGE_NCSI_ERR_INT_TYPE	0x9
#define HCLGE_MAC_COMMON_ERR_INT_EN		0x107FF
#define HCLGE_MAC_COMMON_ERR_INT_EN_MASK	0x107FF
#define HCLGE_MAC_TNL_INT_EN			GENMASK(9, 0)
#define HCLGE_MAC_TNL_INT_EN_MASK		GENMASK(9, 0)
#define HCLGE_MAC_TNL_INT_CLR			GENMASK(9, 0)
#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN		GENMASK(31, 0)
#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK	GENMASK(31, 0)
#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN		GENMASK(31, 0)
#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK	GENMASK(31, 0)
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN		0x3FFF3FFF
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK	0x3FFF3FFF
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2		0xB
#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK	0xB
#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN		GENMASK(7, 0)
#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK	GENMASK(23, 16)
#define HCLGE_PPU_PF_ABNORMAL_INT_EN		GENMASK(5, 0)
#define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK	GENMASK(5, 0)
#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN		GENMASK(31, 0)
#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK	GENMASK(31, 0)
#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN	GENMASK(31, 0)
#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK	GENMASK(31, 0)
#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN		0x0101
#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK	0x0101
#define HCLGE_SSU_COMMON_INT_EN			GENMASK(9, 0)
#define HCLGE_SSU_COMMON_INT_EN_MASK		GENMASK(9, 0)
#define HCLGE_SSU_PORT_BASED_ERR_INT_EN		0x0BFF
#define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK	0x0BFF0000
#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN	GENMASK(23, 0)
#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK	GENMASK(23, 0)

#define HCLGE_SSU_COMMON_ERR_INT_MASK	GENMASK(9, 0)
#define HCLGE_SSU_PORT_INT_MSIX_MASK	0x7BFF
#define HCLGE_IGU_INT_MASK		GENMASK(3, 0)
#define HCLGE_IGU_EGU_TNL_INT_MASK	GENMASK(5, 0)
#define HCLGE_PPP_MPF_INT_ST3_MASK	GENMASK(5, 0)
#define HCLGE_PPU_MPF_INT_ST3_MASK	GENMASK(7, 0)
#define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK	BIT(29)
#define HCLGE_PPU_PF_INT_RAS_MASK	0x18
#define HCLGE_PPU_PF_INT_MSIX_MASK	0x26
#define HCLGE_PPU_PF_OVER_8BD_ERR_MASK	0x01
#define HCLGE_QCN_FIFO_INT_MASK		GENMASK(17, 0)
#define HCLGE_QCN_ECC_INT_MASK		GENMASK(21, 0)
#define HCLGE_NCSI_ECC_INT_MASK		GENMASK(1, 0)

#define HCLGE_ROCEE_RAS_NFE_INT_EN		0xF
#define HCLGE_ROCEE_RAS_CE_INT_EN		0x1
#define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK		0xF
#define HCLGE_ROCEE_RAS_CE_INT_EN_MASK		0x1
#define HCLGE_ROCEE_RERR_INT_MASK		BIT(0)
#define HCLGE_ROCEE_BERR_INT_MASK		BIT(1)
#define HCLGE_ROCEE_AXI_ERR_INT_MASK		GENMASK(1, 0)
#define HCLGE_ROCEE_ECC_INT_MASK		BIT(2)
#define HCLGE_ROCEE_OVF_INT_MASK		BIT(3)
#define HCLGE_ROCEE_OVF_ERR_INT_MASK		0x10000
#define HCLGE_ROCEE_OVF_ERR_TYPE_MASK		0x3F

#define HCLGE_DESC_DATA_MAX			8
#define HCLGE_REG_NUM_MAX			256
#define HCLGE_DESC_NO_DATA_LEN			8

enum hclge_err_int_type {
	HCLGE_ERR_INT_MSIX = 0,
	HCLGE_ERR_INT_RAS_CE = 1,
	HCLGE_ERR_INT_RAS_NFE = 2,
	HCLGE_ERR_INT_RAS_FE = 3,
};

enum hclge_mod_name_list {
	MODULE_NONE		= 0,
	MODULE_BIOS_COMMON	= 1,
	MODULE_GE		= 2,
	MODULE_IGU_EGU		= 3,
	MODULE_LGE		= 4,
	MODULE_NCSI		= 5,
	MODULE_PPP		= 6,
	MODULE_QCN		= 7,
	MODULE_RCB_RX		= 8,
	MODULE_RTC		= 9,
	MODULE_SSU		= 10,
	MODULE_TM		= 11,
	MODULE_RCB_TX		= 12,
	MODULE_TXDMA		= 13,
	MODULE_MASTER		= 14,
	/* add new MODULE NAME for NIC here in order */
	MODULE_ROCEE_TOP	= 40,
	MODULE_ROCEE_TIMER	= 41,
	MODULE_ROCEE_MDB	= 42,
	MODULE_ROCEE_TSP	= 43,
	MODULE_ROCEE_TRP	= 44,
	MODULE_ROCEE_SCC	= 45,
	MODULE_ROCEE_CAEP	= 46,
	MODULE_ROCEE_GEN_AC	= 47,
	MODULE_ROCEE_QMM	= 48,
	MODULE_ROCEE_LSAN	= 49,
	/* add new MODULE NAME for RoCEE here in order */
};

enum hclge_err_type_list {
	NONE_ERROR		= 0,
	FIFO_ERROR		= 1,
	MEMORY_ERROR		= 2,
	POISON_ERROR		= 3,
	MSIX_ECC_ERROR		= 4,
	TQP_INT_ECC_ERROR	= 5,
	PF_ABNORMAL_INT_ERROR	= 6,
	MPF_ABNORMAL_INT_ERROR	= 7,
	COMMON_ERROR		= 8,
	PORT_ERROR		= 9,
	ETS_ERROR		= 10,
	NCSI_ERROR		= 11,
	GLB_ERROR		= 12,
	/* add new ERROR TYPE for NIC here in order */
	ROCEE_NORMAL_ERR	= 40,
	ROCEE_OVF_ERR		= 41,
	/* add new ERROR TYPE for ROCEE here in order */
};

struct hclge_hw_blk {
	u32 msk;
	const char *name;
	int (*config_err_int)(struct hclge_dev *hdev, bool en);
};

struct hclge_hw_error {
	u32 int_msk;
	const char *msg;
	enum hnae3_reset_type reset_level;
};

struct hclge_hw_module_id {
	enum hclge_mod_name_list module_id;
	const char *msg;
};

struct hclge_hw_type_id {
	enum hclge_err_type_list type_id;
	const char *msg;
};

struct hclge_sum_err_info {
	u8 reset_type;
	u8 mod_num;
	u8 rsv[2];
};

struct hclge_mod_err_info {
	u8 mod_id;
	u8 err_num;
	u8 rsv[2];
};

struct hclge_type_reg_err_info {
	u8 type_id;
	u8 reg_num;
	u8 rsv[2];
	u32 hclge_reg[HCLGE_REG_NUM_MAX];
};

int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);
bool hclge_find_error_source(struct hclge_dev *hdev);
void hclge_handle_occurred_error(struct hclge_dev *hdev);
pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
			       unsigned long *reset_requests);
int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev);
int hclge_handle_mac_tnl(struct hclge_dev *hdev);
#endif
Commit	Line	Data
5a9f0eac SJ	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/* Copyright (c) 2016-2017 Hisilicon Limited. */
	3
	4	#ifndef __HCLGE_ERR_H
	5	#define __HCLGE_ERR_H
	6
	7	#include "hclge_main.h"
a83d2961	8	#include "hnae3.h"
5a9f0eac	9
987b4ae7 WL	10	#define HCLGE_MPF_RAS_INT_MIN_BD_NUM 10
	11	#define HCLGE_PF_RAS_INT_MIN_BD_NUM 4
	12	#define HCLGE_MPF_MSIX_INT_MIN_BD_NUM 10
	13	#define HCLGE_PF_MSIX_INT_MIN_BD_NUM 4
	14
5a9f0eac	15	#define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00
5a9f0eac	16	#define HCLGE_RAS_REG_NFE_MASK 0xFF00
630ba007	17	#define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000
8a95e360 JZ	18	#define HCLGE_RAS_REG_ERR_MASK \
8a95e360 JZ	19	(HCLGE_RAS_REG_NFE_MASK \| HCLGE_RAS_REG_ROCEE_ERR_MASK)
5a9f0eac	20
f6162d44 SM	21	#define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00
f6162d44 SM	22
6d67ee9a SJ	23	#define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
	24	#define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
	25	#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300
	26	#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
	27	#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
	28	#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
	29	#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000
	30	#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000
	31	#define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100
	32	#define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
	33	#define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF
	34	#define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
332fbf57 SJ	35	#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
332fbf57 SJ	36	#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
2867298d YM	37	#define HCLGE_IGU_ERR_INT_EN 0x0000000F
2867298d YM	38	#define HCLGE_IGU_ERR_INT_TYPE 0x00000660
bf1faf94 SJ	39	#define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
	40	#define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
	41	#define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
da2d072a SJ	42	#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
	43	#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
	44	#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
	45	#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
	46	#define HCLGE_PPP_PF_ERR_INT_EN 0x0003
	47	#define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003
	48	#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F
	49	#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
	50	#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F
	51	#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
01865a50	52	#define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3
60484103 JZ	53	#define HCLGE_TM_QCN_ERR_INT_TYPE 0x29
60484103 JZ	54	#define HCLGE_TM_QCN_FIFO_INT_EN 0xFFFF00
01865a50	55	#define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
bf1faf94 SJ	56	#define HCLGE_NCSI_ERR_INT_EN 0x3
bf1faf94 SJ	57	#define HCLGE_NCSI_ERR_INT_TYPE 0x9
d1f55d6b WL	58	#define HCLGE_MAC_COMMON_ERR_INT_EN 0x107FF
d1f55d6b WL	59	#define HCLGE_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
6aa5d07d WL	60	#define HCLGE_MAC_TNL_INT_EN GENMASK(9, 0)
	61	#define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
	62	#define HCLGE_MAC_TNL_INT_CLR GENMASK(9, 0)
f69b10b3 SJ	63	#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
	64	#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
	65	#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
	66	#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
	67	#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
	68	#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
	69	#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB
	70	#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
	71	#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
	72	#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
	73	#define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
	74	#define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
c3529177 SJ	75	#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
	76	#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
	77	#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
	78	#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
	79	#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x0101
	80	#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
	81	#define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0)
	82	#define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
	83	#define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
	84	#define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
	85	#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
	86	#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
6d67ee9a	87
c3529177 SJ	88	#define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
c3529177 SJ	89	#define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF
332fbf57 SJ	90	#define HCLGE_IGU_INT_MASK GENMASK(3, 0)
	91	#define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)
	92	#define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)
f69b10b3	93	#define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0)
9f65e5ef	94	#define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK BIT(29)
747fc3f3	95	#define HCLGE_PPU_PF_INT_RAS_MASK 0x18
0cd86182 WL	96	#define HCLGE_PPU_PF_INT_MSIX_MASK 0x26
0cd86182 WL	97	#define HCLGE_PPU_PF_OVER_8BD_ERR_MASK 0x01
332fbf57 SJ	98	#define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0)
	99	#define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0)
	100	#define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0)
	101
630ba007 SJ	102	#define HCLGE_ROCEE_RAS_NFE_INT_EN 0xF
	103	#define HCLGE_ROCEE_RAS_CE_INT_EN 0x1
	104	#define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK 0xF
	105	#define HCLGE_ROCEE_RAS_CE_INT_EN_MASK 0x1
	106	#define HCLGE_ROCEE_RERR_INT_MASK BIT(0)
	107	#define HCLGE_ROCEE_BERR_INT_MASK BIT(1)
238882c8	108	#define HCLGE_ROCEE_AXI_ERR_INT_MASK GENMASK(1, 0)
630ba007 SJ	109	#define HCLGE_ROCEE_ECC_INT_MASK BIT(2)
	110	#define HCLGE_ROCEE_OVF_INT_MASK BIT(3)
	111	#define HCLGE_ROCEE_OVF_ERR_INT_MASK 0x10000
	112	#define HCLGE_ROCEE_OVF_ERR_TYPE_MASK 0x3F
	113
2e2deee7 JZ	114	#define HCLGE_DESC_DATA_MAX 8
	115	#define HCLGE_REG_NUM_MAX 256
	116	#define HCLGE_DESC_NO_DATA_LEN 8
	117
5a9f0eac SJ	118	enum hclge_err_int_type {
	119	HCLGE_ERR_INT_MSIX = 0,
	120	HCLGE_ERR_INT_RAS_CE = 1,
	121	HCLGE_ERR_INT_RAS_NFE = 2,
	122	HCLGE_ERR_INT_RAS_FE = 3,
	123	};
	124
2e2deee7 JZ	125	enum hclge_mod_name_list {
	126	MODULE_NONE = 0,
	127	MODULE_BIOS_COMMON = 1,
	128	MODULE_GE = 2,
	129	MODULE_IGU_EGU = 3,
	130	MODULE_LGE = 4,
	131	MODULE_NCSI = 5,
	132	MODULE_PPP = 6,
	133	MODULE_QCN = 7,
	134	MODULE_RCB_RX = 8,
	135	MODULE_RTC = 9,
	136	MODULE_SSU = 10,
	137	MODULE_TM = 11,
	138	MODULE_RCB_TX = 12,
	139	MODULE_TXDMA = 13,
	140	MODULE_MASTER = 14,
8a95e360 JZ	141	/* add new MODULE NAME for NIC here in order */
	142	MODULE_ROCEE_TOP = 40,
	143	MODULE_ROCEE_TIMER = 41,
	144	MODULE_ROCEE_MDB = 42,
	145	MODULE_ROCEE_TSP = 43,
	146	MODULE_ROCEE_TRP = 44,
	147	MODULE_ROCEE_SCC = 45,
	148	MODULE_ROCEE_CAEP = 46,
	149	MODULE_ROCEE_GEN_AC = 47,
	150	MODULE_ROCEE_QMM = 48,
	151	MODULE_ROCEE_LSAN = 49,
	152	/* add new MODULE NAME for RoCEE here in order */
2e2deee7 JZ	153	};
	154
	155	enum hclge_err_type_list {
	156	NONE_ERROR = 0,
	157	FIFO_ERROR = 1,
	158	MEMORY_ERROR = 2,
	159	POISON_ERROR = 3,
	160	MSIX_ECC_ERROR = 4,
	161	TQP_INT_ECC_ERROR = 5,
	162	PF_ABNORMAL_INT_ERROR = 6,
	163	MPF_ABNORMAL_INT_ERROR = 7,
	164	COMMON_ERROR = 8,
	165	PORT_ERROR = 9,
	166	ETS_ERROR = 10,
	167	NCSI_ERROR = 11,
	168	GLB_ERROR = 12,
8a95e360 JZ	169	/* add new ERROR TYPE for NIC here in order */
	170	ROCEE_NORMAL_ERR = 40,
	171	ROCEE_OVF_ERR = 41,
	172	/* add new ERROR TYPE for ROCEE here in order */
2e2deee7 JZ	173	};
2e2deee7 JZ	174
5a9f0eac SJ	175	struct hclge_hw_blk {
	176	u32 msk;
	177	const char *name;
98da4027	178	int (config_err_int)(struct hclge_dev hdev, bool en);
5a9f0eac SJ	179	};
5a9f0eac SJ	180
6d67ee9a SJ	181	struct hclge_hw_error {
	182	u32 int_msk;
	183	const char *msg;
c41e672d	184	enum hnae3_reset_type reset_level;
6d67ee9a SJ	185	};
6d67ee9a SJ	186
2e2deee7 JZ	187	struct hclge_hw_module_id {
	188	enum hclge_mod_name_list module_id;
	189	const char *msg;
	190	};
	191
	192	struct hclge_hw_type_id {
	193	enum hclge_err_type_list type_id;
	194	const char *msg;
	195	};
	196
	197	struct hclge_sum_err_info {
	198	u8 reset_type;
	199	u8 mod_num;
	200	u8 rsv[2];
	201	};
	202
	203	struct hclge_mod_err_info {
	204	u8 mod_id;
	205	u8 err_num;
	206	u8 rsv[2];
	207	};
	208
	209	struct hclge_type_reg_err_info {
	210	u8 type_id;
	211	u8 reg_num;
	212	u8 rsv[2];
	213	u32 hclge_reg[HCLGE_REG_NUM_MAX];
	214	};
	215
a6345787	216	int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
00ea6e5f WL	217	int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
00ea6e5f WL	218	int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
e4193e24	219	void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);
1c360a4a JZ	220	bool hclge_find_error_source(struct hclge_dev *hdev);
1c360a4a JZ	221	void hclge_handle_occurred_error(struct hclge_dev *hdev);
381c356e	222	pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
f6162d44 SM	223	int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
f6162d44 SM	224	unsigned long *reset_requests);
2e2deee7 JZ	225	int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev);
2e2deee7 JZ	226	int hclge_handle_mac_tnl(struct hclge_dev *hdev);
5a9f0eac	227	#endif