projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 00bb612a SJ |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* Copyright (c) 2016-2017 Hisilicon Limited. */ | |
| 3 | ||
| 4 | #ifndef __HCLGE_ERR_H | |
| 5 | #define __HCLGE_ERR_H | |
| 6 | ||
| 7 | #include "hclge_main.h" | |
| 8 | ||
| 9 | #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00 | |
| 00bb612a | 10 | #define HCLGE_RAS_REG_NFE_MASK 0xFF00 |
| 00bb612a | 11 | |
| 8b684fc7 SJ |
12 | #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000 |
| 13 | #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000 | |
| 14 | #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300 | |
| 15 | #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300 | |
| 16 | #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF | |
| 17 | #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF | |
| 18 | #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000 | |
| 19 | #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000 | |
| 20 | #define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100 | |
| 21 | #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100 | |
| 22 | #define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF | |
| 23 | #define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF | |
| d5a2e3fc SJ |
24 | #define HCLGE_IGU_ERR_INT_EN 0x0000066F |
| 25 | #define HCLGE_IGU_ERR_INT_EN_MASK 0x000F | |
| 26 | #define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF | |
| 27 | #define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F | |
| d1cc1b84 SJ |
28 | #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF |
| 29 | #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF | |
| 30 | #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF | |
| 31 | #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF | |
| 32 | #define HCLGE_PPP_PF_ERR_INT_EN 0x0003 | |
| 33 | #define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003 | |
| 34 | #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F | |
| 35 | #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F | |
| 36 | #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F | |
| 37 | #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F | |
| 78807a3d SJ |
38 | #define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3 |
| 39 | #define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF | |
| d5a2e3fc SJ |
40 | #define HCLGE_NCSI_ERR_INT_EN 0x3 |
| 41 | #define HCLGE_NCSI_ERR_INT_TYPE 0x9 | |
| 8b684fc7 | 42 | |
| 00bb612a SJ |
43 | enum hclge_err_int_type { |
| 44 | HCLGE_ERR_INT_MSIX = 0, | |
| 45 | HCLGE_ERR_INT_RAS_CE = 1, | |
| 46 | HCLGE_ERR_INT_RAS_NFE = 2, | |
| 47 | HCLGE_ERR_INT_RAS_FE = 3, | |
| 48 | }; | |
| 49 | ||
| 50 | struct hclge_hw_blk { | |
| 51 | u32 msk; | |
| 52 | const char *name; | |
| 9f53588e | 53 | int (*enable_error)(struct hclge_dev *hdev, bool en); |
| 00bb612a SJ |
54 | }; |
| 55 | ||
| 8b684fc7 SJ |
56 | struct hclge_hw_error { |
| 57 | u32 int_msk; | |
| 58 | const char *msg; | |
| 59 | }; | |
| 60 | ||
| 9f53588e | 61 | int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state); |
| 78807a3d | 62 | int hclge_enable_tm_hw_error(struct hclge_dev *hdev, bool en); |
| 00bb612a SJ |
63 | pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev); |
| 64 | #endif |