projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 00bb612a SJ |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* Copyright (c) 2016-2017 Hisilicon Limited. */ | |
| 3 | ||
| 4 | #ifndef __HCLGE_ERR_H | |
| 5 | #define __HCLGE_ERR_H | |
| 6 | ||
| 7 | #include "hclge_main.h" | |
| 8 | ||
| 9 | #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00 | |
| 00bb612a | 10 | #define HCLGE_RAS_REG_NFE_MASK 0xFF00 |
| 00bb612a | 11 | |
| 00029070 SM |
12 | #define HCLGE_VECTOR0_PF_OTHER_INT_STS_REG 0x20800 |
| 13 | #define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00 | |
| 14 | ||
| 8b684fc7 SJ |
15 | #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000 |
| 16 | #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000 | |
| 17 | #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300 | |
| 18 | #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300 | |
| 19 | #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF | |
| 20 | #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF | |
| 21 | #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000 | |
| 22 | #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000 | |
| 23 | #define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100 | |
| 24 | #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100 | |
| 25 | #define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF | |
| 26 | #define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF | |
| 4a76aabc SJ |
27 | #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000 |
| 28 | #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000 | |
| d5a2e3fc SJ |
29 | #define HCLGE_IGU_ERR_INT_EN 0x0000066F |
| 30 | #define HCLGE_IGU_ERR_INT_EN_MASK 0x000F | |
| 31 | #define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF | |
| 32 | #define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F | |
| d1cc1b84 SJ |
33 | #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF |
| 34 | #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF | |
| 35 | #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF | |
| 36 | #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF | |
| 37 | #define HCLGE_PPP_PF_ERR_INT_EN 0x0003 | |
| 38 | #define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003 | |
| 39 | #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F | |
| 40 | #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F | |
| 41 | #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F | |
| 42 | #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F | |
| 78807a3d SJ |
43 | #define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3 |
| 44 | #define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF | |
| d5a2e3fc SJ |
45 | #define HCLGE_NCSI_ERR_INT_EN 0x3 |
| 46 | #define HCLGE_NCSI_ERR_INT_TYPE 0x9 | |
| a3e78d8d SJ |
47 | #define HCLGE_MAC_COMMON_ERR_INT_EN GENMASK(7, 0) |
| 48 | #define HCLGE_MAC_COMMON_ERR_INT_EN_MASK GENMASK(7, 0) | |
| 1df865ea SJ |
49 | #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0) |
| 50 | #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0) | |
| 51 | #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0) | |
| 52 | #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0) | |
| 53 | #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF | |
| 54 | #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF | |
| 55 | #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB | |
| 56 | #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB | |
| 57 | #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0) | |
| 58 | #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16) | |
| 59 | #define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0) | |
| 60 | #define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0) | |
| db07cedf SJ |
61 | #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0) |
| 62 | #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0) | |
| 63 | #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0) | |
| 64 | #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0) | |
| 65 | #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x0101 | |
| 66 | #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101 | |
| 67 | #define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0) | |
| 68 | #define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0) | |
| 69 | #define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF | |
| 70 | #define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000 | |
| 71 | #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0) | |
| 72 | #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0) | |
| 8b684fc7 | 73 | |
| db07cedf SJ |
74 | #define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0) |
| 75 | #define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF | |
| 4a76aabc SJ |
76 | #define HCLGE_IGU_INT_MASK GENMASK(3, 0) |
| 77 | #define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0) | |
| 78 | #define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0) | |
| 1df865ea SJ |
79 | #define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0) |
| 80 | #define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK GENMASK(29, 28) | |
| 81 | #define HCLGE_PPU_PF_INT_MSIX_MASK 0x27 | |
| 4a76aabc SJ |
82 | #define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0) |
| 83 | #define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0) | |
| 84 | #define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0) | |
| 85 | ||
| 00bb612a SJ |
86 | enum hclge_err_int_type { |
| 87 | HCLGE_ERR_INT_MSIX = 0, | |
| 88 | HCLGE_ERR_INT_RAS_CE = 1, | |
| 89 | HCLGE_ERR_INT_RAS_NFE = 2, | |
| 90 | HCLGE_ERR_INT_RAS_FE = 3, | |
| 91 | }; | |
| 92 | ||
| 93 | struct hclge_hw_blk { | |
| 94 | u32 msk; | |
| 95 | const char *name; | |
| 099fa631 | 96 | int (*config_err_int)(struct hclge_dev *hdev, bool en); |
| 00bb612a SJ |
97 | }; |
| 98 | ||
| 8b684fc7 SJ |
99 | struct hclge_hw_error { |
| 100 | u32 int_msk; | |
| 101 | const char *msg; | |
| 102 | }; | |
| 103 | ||
| 9f53588e | 104 | int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state); |
| af72a21f | 105 | pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev); |
| 00029070 SM |
106 | int hclge_handle_hw_msix_error(struct hclge_dev *hdev, |
| 107 | unsigned long *reset_requests); | |
| 00bb612a | 108 | #endif |