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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
d5752031 20#include <net/rtnetlink.h>
46a3df9f 21#include "hclge_cmd.h"
cacde272 22#include "hclge_dcb.h"
46a3df9f 23#include "hclge_main.h"
0cdbdd3e 24#include "hclge_mbx.h"
46a3df9f
S		 25#include "hclge_mdio.h"
26#include "hclge_tm.h"
27#include "hnae3.h"
28
29#define HCLGE_NAME "hclge"
30#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
31#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
32#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
33#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
34
46a3df9f
S		 35static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
36 enum hclge_mta_dmac_sel_type mta_mac_sel,
37 bool enable);
38static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 39static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 40
41static struct hnae3_ae_algo ae_algo;
42
43static const struct pci_device_id ae_algo_pci_tbl[] = {
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 51 /* required last entry */
46a3df9f
S		 52 {0, }
53};
54
55static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
56 "Mac Loopback test",
57 "Serdes Loopback test",
58 "Phy Loopback test"
59};
60
61static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
62 {"igu_rx_oversize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
64 {"igu_rx_undersize_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
66 {"igu_rx_out_all_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
68 {"igu_rx_uni_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
70 {"igu_rx_multi_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
72 {"igu_rx_broad_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
74 {"egu_tx_out_all_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
76 {"egu_tx_uni_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
78 {"egu_tx_multi_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
80 {"egu_tx_broad_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
82 {"ssu_ppp_mac_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
84 {"ssu_ppp_host_key_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
86 {"ppp_ssu_mac_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
88 {"ppp_ssu_host_rlt_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
90 {"ssu_tx_in_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
92 {"ssu_tx_out_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
94 {"ssu_rx_in_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
96 {"ssu_rx_out_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
98};
99
100static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
101 {"igu_rx_err_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
103 {"igu_rx_no_eof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
105 {"igu_rx_no_sof_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
107 {"egu_tx_1588_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
109 {"ssu_full_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
111 {"ssu_part_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
113 {"ppp_key_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
115 {"ppp_rlt_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
117 {"ssu_key_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
119 {"pkt_curr_buf_cnt",
120 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
121 {"qcn_fb_rcv_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
123 {"qcn_fb_drop_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
125 {"qcn_fb_invaild_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
127 {"rx_packet_tc0_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
129 {"rx_packet_tc1_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
131 {"rx_packet_tc2_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
133 {"rx_packet_tc3_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
135 {"rx_packet_tc4_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
137 {"rx_packet_tc5_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
139 {"rx_packet_tc6_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
141 {"rx_packet_tc7_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
143 {"rx_packet_tc0_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
145 {"rx_packet_tc1_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
147 {"rx_packet_tc2_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
149 {"rx_packet_tc3_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
151 {"rx_packet_tc4_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
153 {"rx_packet_tc5_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
155 {"rx_packet_tc6_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
157 {"rx_packet_tc7_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
159 {"tx_packet_tc0_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
161 {"tx_packet_tc1_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
163 {"tx_packet_tc2_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
165 {"tx_packet_tc3_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
167 {"tx_packet_tc4_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
169 {"tx_packet_tc5_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
171 {"tx_packet_tc6_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
173 {"tx_packet_tc7_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
175 {"tx_packet_tc0_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
177 {"tx_packet_tc1_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
179 {"tx_packet_tc2_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
181 {"tx_packet_tc3_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
183 {"tx_packet_tc4_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
185 {"tx_packet_tc5_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
187 {"tx_packet_tc6_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
189 {"tx_packet_tc7_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
191 {"pkt_curr_buf_tc0_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
193 {"pkt_curr_buf_tc1_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
195 {"pkt_curr_buf_tc2_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
197 {"pkt_curr_buf_tc3_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
199 {"pkt_curr_buf_tc4_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
201 {"pkt_curr_buf_tc5_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
203 {"pkt_curr_buf_tc6_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
205 {"pkt_curr_buf_tc7_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
207 {"mb_uncopy_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
209 {"lo_pri_unicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
211 {"hi_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
213 {"lo_pri_multicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
215 {"rx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
217 {"tx_oq_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
219 {"nic_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
221 {"roc_l2_err_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
223};
224
225static const struct hclge_comm_stats_str g_mac_stats_string[] = {
226 {"mac_tx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
228 {"mac_rx_mac_pause_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
230 {"mac_tx_pfc_pri0_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
232 {"mac_tx_pfc_pri1_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
234 {"mac_tx_pfc_pri2_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
236 {"mac_tx_pfc_pri3_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
238 {"mac_tx_pfc_pri4_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
240 {"mac_tx_pfc_pri5_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
242 {"mac_tx_pfc_pri6_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
244 {"mac_tx_pfc_pri7_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
246 {"mac_rx_pfc_pri0_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
248 {"mac_rx_pfc_pri1_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
250 {"mac_rx_pfc_pri2_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
252 {"mac_rx_pfc_pri3_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
254 {"mac_rx_pfc_pri4_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
256 {"mac_rx_pfc_pri5_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
258 {"mac_rx_pfc_pri6_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
260 {"mac_rx_pfc_pri7_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
262 {"mac_tx_total_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
264 {"mac_tx_total_oct_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
266 {"mac_tx_good_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
268 {"mac_tx_bad_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
270 {"mac_tx_good_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
272 {"mac_tx_bad_oct_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
274 {"mac_tx_uni_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
276 {"mac_tx_multi_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
278 {"mac_tx_broad_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
280 {"mac_tx_undersize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
282 {"mac_tx_overrsize_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
284 {"mac_tx_64_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
286 {"mac_tx_65_127_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
288 {"mac_tx_128_255_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
290 {"mac_tx_256_511_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
292 {"mac_tx_512_1023_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
294 {"mac_tx_1024_1518_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
296 {"mac_tx_1519_max_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
298 {"mac_rx_total_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
300 {"mac_rx_total_oct_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
302 {"mac_rx_good_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
304 {"mac_rx_bad_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
306 {"mac_rx_good_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
308 {"mac_rx_bad_oct_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
310 {"mac_rx_uni_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
312 {"mac_rx_multi_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
314 {"mac_rx_broad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
316 {"mac_rx_undersize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
318 {"mac_rx_overrsize_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
320 {"mac_rx_64_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
322 {"mac_rx_65_127_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
324 {"mac_rx_128_255_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
326 {"mac_rx_256_511_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
328 {"mac_rx_512_1023_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
330 {"mac_rx_1024_1518_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
332 {"mac_rx_1519_max_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
334
335 {"mac_trans_fragment_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
337 {"mac_trans_undermin_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
339 {"mac_trans_jabber_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
341 {"mac_trans_err_all_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
343 {"mac_trans_from_app_good_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
345 {"mac_trans_from_app_bad_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
347 {"mac_rcv_fragment_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
349 {"mac_rcv_undermin_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
351 {"mac_rcv_jabber_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
353 {"mac_rcv_fcs_err_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
355 {"mac_rcv_send_app_good_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
357 {"mac_rcv_send_app_bad_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
359};
360
361static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
362{
363#define HCLGE_64_BIT_CMD_NUM 5
364#define HCLGE_64_BIT_RTN_DATANUM 4
365 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
366 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 367 __le64 *desc_data;
46a3df9f
S		 368 int i, k, n;
369 int ret;
370
371 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
372 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
373 if (ret) {
374 dev_err(&hdev->pdev->dev,
375 "Get 64 bit pkt stats fail, status = %d.\n", ret);
376 return ret;
377 }
378
379 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
380 if (unlikely(i == 0)) {
a90bb9a5 381 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 382 n = HCLGE_64_BIT_RTN_DATANUM - 1;
383 } else {
a90bb9a5 384 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 385 n = HCLGE_64_BIT_RTN_DATANUM;
386 }
387 for (k = 0; k < n; k++) {
a90bb9a5 388 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 389 desc_data++;
390 }
391 }
392
393 return 0;
394}
395
396static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
397{
398 stats->pkt_curr_buf_cnt = 0;
399 stats->pkt_curr_buf_tc0_cnt = 0;
400 stats->pkt_curr_buf_tc1_cnt = 0;
401 stats->pkt_curr_buf_tc2_cnt = 0;
402 stats->pkt_curr_buf_tc3_cnt = 0;
403 stats->pkt_curr_buf_tc4_cnt = 0;
404 stats->pkt_curr_buf_tc5_cnt = 0;
405 stats->pkt_curr_buf_tc6_cnt = 0;
406 stats->pkt_curr_buf_tc7_cnt = 0;
407}
408
409static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
410{
411#define HCLGE_32_BIT_CMD_NUM 8
412#define HCLGE_32_BIT_RTN_DATANUM 8
413
414 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
415 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 416 __le32 *desc_data;
46a3df9f
S		 417 int i, k, n;
418 u64 *data;
419 int ret;
420
421 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
422 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
423
424 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
425 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
426 if (ret) {
427 dev_err(&hdev->pdev->dev,
428 "Get 32 bit pkt stats fail, status = %d.\n", ret);
429
430 return ret;
431 }
432
433 hclge_reset_partial_32bit_counter(all_32_bit_stats);
434 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
435 if (unlikely(i == 0)) {
a90bb9a5
YL		 436 __le16 *desc_data_16bit;
437
46a3df9f 438 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 439 le32_to_cpu(desc[i].data[0]);
440
441 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 442 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 443 le16_to_cpu(*desc_data_16bit);
444
445 desc_data_16bit++;
46a3df9f 446 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 447 le16_to_cpu(*desc_data_16bit);
46a3df9f 448
a90bb9a5 449 desc_data = &desc[i].data[2];
46a3df9f
S		 450 n = HCLGE_32_BIT_RTN_DATANUM - 4;
451 } else {
a90bb9a5 452 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 453 n = HCLGE_32_BIT_RTN_DATANUM;
454 }
455 for (k = 0; k < n; k++) {
a90bb9a5 456 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 457 desc_data++;
458 }
459 }
460
461 return 0;
462}
463
464static int hclge_mac_update_stats(struct hclge_dev *hdev)
465{
466#define HCLGE_MAC_CMD_NUM 17
467#define HCLGE_RTN_DATA_NUM 4
468
469 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
470 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 471 __le64 *desc_data;
46a3df9f
S		 472 int i, k, n;
473 int ret;
474
475 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
476 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
477 if (ret) {
478 dev_err(&hdev->pdev->dev,
479 "Get MAC pkt stats fail, status = %d.\n", ret);
480
481 return ret;
482 }
483
484 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
485 if (unlikely(i == 0)) {
a90bb9a5 486 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 487 n = HCLGE_RTN_DATA_NUM - 2;
488 } else {
a90bb9a5 489 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 490 n = HCLGE_RTN_DATA_NUM;
491 }
492 for (k = 0; k < n; k++) {
a90bb9a5 493 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 494 desc_data++;
495 }
496 }
497
498 return 0;
499}
500
501static int hclge_tqps_update_stats(struct hnae3_handle *handle)
502{
503 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
504 struct hclge_vport *vport = hclge_get_vport(handle);
505 struct hclge_dev *hdev = vport->back;
506 struct hnae3_queue *queue;
507 struct hclge_desc desc[1];
508 struct hclge_tqp *tqp;
509 int ret, i;
510
511 for (i = 0; i < kinfo->num_tqps; i++) {
512 queue = handle->kinfo.tqp[i];
513 tqp = container_of(queue, struct hclge_tqp, q);
514 /* command : HCLGE_OPC_QUERY_IGU_STAT */
515 hclge_cmd_setup_basic_desc(&desc[0],
516 HCLGE_OPC_QUERY_RX_STATUS,
517 true);
518
a90bb9a5 519 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 520 ret = hclge_cmd_send(&hdev->hw, desc, 1);
521 if (ret) {
522 dev_err(&hdev->pdev->dev,
523 "Query tqp stat fail, status = %d,queue = %d\n",
524 ret, i);
525 return ret;
526 }
527 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
a90bb9a5 528 le32_to_cpu(desc[0].data[4]);
46a3df9f
S		 529 }
530
531 for (i = 0; i < kinfo->num_tqps; i++) {
532 queue = handle->kinfo.tqp[i];
533 tqp = container_of(queue, struct hclge_tqp, q);
534 /* command : HCLGE_OPC_QUERY_IGU_STAT */
535 hclge_cmd_setup_basic_desc(&desc[0],
536 HCLGE_OPC_QUERY_TX_STATUS,
537 true);
538
a90bb9a5 539 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 540 ret = hclge_cmd_send(&hdev->hw, desc, 1);
541 if (ret) {
542 dev_err(&hdev->pdev->dev,
543 "Query tqp stat fail, status = %d,queue = %d\n",
544 ret, i);
545 return ret;
546 }
547 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
a90bb9a5 548 le32_to_cpu(desc[0].data[4]);
46a3df9f
S		 549 }
550
551 return 0;
552}
553
554static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
555{
556 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
557 struct hclge_tqp *tqp;
558 u64 *buff = data;
559 int i;
560
561 for (i = 0; i < kinfo->num_tqps; i++) {
562 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 563 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 564 }
565
566 for (i = 0; i < kinfo->num_tqps; i++) {
567 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 568 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 569 }
570
571 return buff;
572}
573
574static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
575{
576 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
577
578 return kinfo->num_tqps * (2);
579}
580
581static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
582{
583 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
584 u8 *buff = data;
585 int i = 0;
586
587 for (i = 0; i < kinfo->num_tqps; i++) {
588 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
589 struct hclge_tqp, q);
590 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
591 tqp->index);
592 buff = buff + ETH_GSTRING_LEN;
593 }
594
595 for (i = 0; i < kinfo->num_tqps; i++) {
596 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
597 struct hclge_tqp, q);
598 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
599 tqp->index);
600 buff = buff + ETH_GSTRING_LEN;
601 }
602
603 return buff;
604}
605
606static u64 *hclge_comm_get_stats(void *comm_stats,
607 const struct hclge_comm_stats_str strs[],
608 int size, u64 *data)
609{
610 u64 *buf = data;
611 u32 i;
612
613 for (i = 0; i < size; i++)
614 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
615
616 return buf + size;
617}
618
619static u8 *hclge_comm_get_strings(u32 stringset,
620 const struct hclge_comm_stats_str strs[],
621 int size, u8 *data)
622{
623 char *buff = (char *)data;
624 u32 i;
625
626 if (stringset != ETH_SS_STATS)
627 return buff;
628
629 for (i = 0; i < size; i++) {
630 snprintf(buff, ETH_GSTRING_LEN,
631 strs[i].desc);
632 buff = buff + ETH_GSTRING_LEN;
633 }
634
635 return (u8 *)buff;
636}
637
638static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
639 struct net_device_stats *net_stats)
640{
641 net_stats->tx_dropped = 0;
642 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
643 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
644 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
645
646 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
647 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
648 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
649 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
650 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
651 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
652
653 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
654 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
655
656 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
657 net_stats->rx_length_errors =
658 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
659 net_stats->rx_length_errors +=
660 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
661 net_stats->rx_over_errors =
662 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
663}
664
665static void hclge_update_stats_for_all(struct hclge_dev *hdev)
666{
667 struct hnae3_handle *handle;
668 int status;
669
670 handle = &hdev->vport[0].nic;
671 if (handle->client) {
672 status = hclge_tqps_update_stats(handle);
673 if (status) {
674 dev_err(&hdev->pdev->dev,
675 "Update TQPS stats fail, status = %d.\n",
676 status);
677 }
678 }
679
680 status = hclge_mac_update_stats(hdev);
681 if (status)
682 dev_err(&hdev->pdev->dev,
683 "Update MAC stats fail, status = %d.\n", status);
684
685 status = hclge_32_bit_update_stats(hdev);
686 if (status)
687 dev_err(&hdev->pdev->dev,
688 "Update 32 bit stats fail, status = %d.\n",
689 status);
690
691 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
692}
693
694static void hclge_update_stats(struct hnae3_handle *handle,
695 struct net_device_stats *net_stats)
696{
697 struct hclge_vport *vport = hclge_get_vport(handle);
698 struct hclge_dev *hdev = vport->back;
699 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
700 int status;
701
702 status = hclge_mac_update_stats(hdev);
703 if (status)
704 dev_err(&hdev->pdev->dev,
705 "Update MAC stats fail, status = %d.\n",
706 status);
707
708 status = hclge_32_bit_update_stats(hdev);
709 if (status)
710 dev_err(&hdev->pdev->dev,
711 "Update 32 bit stats fail, status = %d.\n",
712 status);
713
714 status = hclge_64_bit_update_stats(hdev);
715 if (status)
716 dev_err(&hdev->pdev->dev,
717 "Update 64 bit stats fail, status = %d.\n",
718 status);
719
720 status = hclge_tqps_update_stats(handle);
721 if (status)
722 dev_err(&hdev->pdev->dev,
723 "Update TQPS stats fail, status = %d.\n",
724 status);
725
726 hclge_update_netstat(hw_stats, net_stats);
727}
728
729static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
730{
731#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
732
733 struct hclge_vport *vport = hclge_get_vport(handle);
734 struct hclge_dev *hdev = vport->back;
735 int count = 0;
736
737 /* Loopback test support rules:
738 * mac: only GE mode support
739 * serdes: all mac mode will support include GE/XGE/LGE/CGE
740 * phy: only support when phy device exist on board
741 */
742 if (stringset == ETH_SS_TEST) {
743 /* clear loopback bit flags at first */
744 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
745 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
746 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
747 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
748 count += 1;
749 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
750 } else {
751 count = -EOPNOTSUPP;
752 }
753 } else if (stringset == ETH_SS_STATS) {
754 count = ARRAY_SIZE(g_mac_stats_string) +
755 ARRAY_SIZE(g_all_32bit_stats_string) +
756 ARRAY_SIZE(g_all_64bit_stats_string) +
757 hclge_tqps_get_sset_count(handle, stringset);
758 }
759
760 return count;
761}
762
763static void hclge_get_strings(struct hnae3_handle *handle,
764 u32 stringset,
765 u8 *data)
766{
767 u8 *p = (char *)data;
768 int size;
769
770 if (stringset == ETH_SS_STATS) {
771 size = ARRAY_SIZE(g_mac_stats_string);
772 p = hclge_comm_get_strings(stringset,
773 g_mac_stats_string,
774 size,
775 p);
776 size = ARRAY_SIZE(g_all_32bit_stats_string);
777 p = hclge_comm_get_strings(stringset,
778 g_all_32bit_stats_string,
779 size,
780 p);
781 size = ARRAY_SIZE(g_all_64bit_stats_string);
782 p = hclge_comm_get_strings(stringset,
783 g_all_64bit_stats_string,
784 size,
785 p);
786 p = hclge_tqps_get_strings(handle, p);
787 } else if (stringset == ETH_SS_TEST) {
788 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
789 memcpy(p,
790 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
791 ETH_GSTRING_LEN);
792 p += ETH_GSTRING_LEN;
793 }
794 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
795 memcpy(p,
796 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
797 ETH_GSTRING_LEN);
798 p += ETH_GSTRING_LEN;
799 }
800 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
801 memcpy(p,
802 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
803 ETH_GSTRING_LEN);
804 p += ETH_GSTRING_LEN;
805 }
806 }
807}
808
809static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
810{
811 struct hclge_vport *vport = hclge_get_vport(handle);
812 struct hclge_dev *hdev = vport->back;
813 u64 *p;
814
815 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
816 g_mac_stats_string,
817 ARRAY_SIZE(g_mac_stats_string),
818 data);
819 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
820 g_all_32bit_stats_string,
821 ARRAY_SIZE(g_all_32bit_stats_string),
822 p);
823 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
824 g_all_64bit_stats_string,
825 ARRAY_SIZE(g_all_64bit_stats_string),
826 p);
827 p = hclge_tqps_get_stats(handle, p);
828}
829
830static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 831 struct hclge_func_status_cmd *status)
46a3df9f
S		 832{
833 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
834 return -EINVAL;
835
836 /* Set the pf to main pf */
837 if (status->pf_state & HCLGE_PF_STATE_MAIN)
838 hdev->flag |= HCLGE_FLAG_MAIN;
839 else
840 hdev->flag &= ~HCLGE_FLAG_MAIN;
841
46a3df9f
S		 842 return 0;
843}
844
845static int hclge_query_function_status(struct hclge_dev *hdev)
846{
d44f9b63 847 struct hclge_func_status_cmd *req;
46a3df9f
S		 848 struct hclge_desc desc;
849 int timeout = 0;
850 int ret;
851
852 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 853 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 854
855 do {
856 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
857 if (ret) {
858 dev_err(&hdev->pdev->dev,
859 "query function status failed %d.\n",
860 ret);
861
862 return ret;
863 }
864
865 /* Check pf reset is done */
866 if (req->pf_state)
867 break;
868 usleep_range(1000, 2000);
869 } while (timeout++ < 5);
870
871 ret = hclge_parse_func_status(hdev, req);
872
873 return ret;
874}
875
876static int hclge_query_pf_resource(struct hclge_dev *hdev)
877{
d44f9b63 878 struct hclge_pf_res_cmd *req;
46a3df9f
S		 879 struct hclge_desc desc;
880 int ret;
881
882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
883 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
884 if (ret) {
885 dev_err(&hdev->pdev->dev,
886 "query pf resource failed %d.\n", ret);
887 return ret;
888 }
889
d44f9b63 890 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 891 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
892 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
893
e92a0843 894 if (hnae3_dev_roce_supported(hdev)) {
887c3820 895 hdev->num_roce_msi =
46a3df9f
S		 896 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
897 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
898
899 /* PF should have NIC vectors and Roce vectors,
900 * NIC vectors are queued before Roce vectors.
901 */
887c3820 902 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 903 } else {
904 hdev->num_msi =
905 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
906 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
907 }
908
909 return 0;
910}
911
912static int hclge_parse_speed(int speed_cmd, int *speed)
913{
914 switch (speed_cmd) {
915 case 6:
916 *speed = HCLGE_MAC_SPEED_10M;
917 break;
918 case 7:
919 *speed = HCLGE_MAC_SPEED_100M;
920 break;
921 case 0:
922 *speed = HCLGE_MAC_SPEED_1G;
923 break;
924 case 1:
925 *speed = HCLGE_MAC_SPEED_10G;
926 break;
927 case 2:
928 *speed = HCLGE_MAC_SPEED_25G;
929 break;
930 case 3:
931 *speed = HCLGE_MAC_SPEED_40G;
932 break;
933 case 4:
934 *speed = HCLGE_MAC_SPEED_50G;
935 break;
936 case 5:
937 *speed = HCLGE_MAC_SPEED_100G;
938 break;
939 default:
940 return -EINVAL;
941 }
942
943 return 0;
944}
945
946static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
947{
d44f9b63 948 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 949 u64 mac_addr_tmp_high;
950 u64 mac_addr_tmp;
951 int i;
952
d44f9b63 953 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 954
955 /* get the configuration */
956 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
957 HCLGE_CFG_VMDQ_M,
958 HCLGE_CFG_VMDQ_S);
959 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
960 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
961 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
962 HCLGE_CFG_TQP_DESC_N_M,
963 HCLGE_CFG_TQP_DESC_N_S);
964
965 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
966 HCLGE_CFG_PHY_ADDR_M,
967 HCLGE_CFG_PHY_ADDR_S);
968 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
969 HCLGE_CFG_MEDIA_TP_M,
970 HCLGE_CFG_MEDIA_TP_S);
971 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
972 HCLGE_CFG_RX_BUF_LEN_M,
973 HCLGE_CFG_RX_BUF_LEN_S);
974 /* get mac_address */
975 mac_addr_tmp = __le32_to_cpu(req->param[2]);
976 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
977 HCLGE_CFG_MAC_ADDR_H_M,
978 HCLGE_CFG_MAC_ADDR_H_S);
979
980 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
981
982 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
983 HCLGE_CFG_DEFAULT_SPEED_M,
984 HCLGE_CFG_DEFAULT_SPEED_S);
985 for (i = 0; i < ETH_ALEN; i++)
986 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
987
d44f9b63 988 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f
S		 989 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
990}
991
992/* hclge_get_cfg: query the static parameter from flash
993 * @hdev: pointer to struct hclge_dev
994 * @hcfg: the config structure to be getted
995 */
996static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
997{
998 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 999 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1000 int i, ret;
1001
1002 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1003 u32 offset = 0;
1004
d44f9b63 1005 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1006 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1007 true);
a90bb9a5 1008 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
46a3df9f
S		 1009 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1010 /* Len should be united by 4 bytes when send to hardware */
a90bb9a5 1011 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
46a3df9f 1012 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1013 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1014 }
1015
1016 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1017 if (ret) {
1018 dev_err(&hdev->pdev->dev,
1019 "get config failed %d.\n", ret);
1020 return ret;
1021 }
1022
1023 hclge_parse_cfg(hcfg, desc);
1024 return 0;
1025}
1026
1027static int hclge_get_cap(struct hclge_dev *hdev)
1028{
1029 int ret;
1030
1031 ret = hclge_query_function_status(hdev);
1032 if (ret) {
1033 dev_err(&hdev->pdev->dev,
1034 "query function status error %d.\n", ret);
1035 return ret;
1036 }
1037
1038 /* get pf resource */
1039 ret = hclge_query_pf_resource(hdev);
1040 if (ret) {
1041 dev_err(&hdev->pdev->dev,
1042 "query pf resource error %d.\n", ret);
1043 return ret;
1044 }
1045
1046 return 0;
1047}
1048
1049static int hclge_configure(struct hclge_dev *hdev)
1050{
1051 struct hclge_cfg cfg;
1052 int ret, i;
1053
1054 ret = hclge_get_cfg(hdev, &cfg);
1055 if (ret) {
1056 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1057 return ret;
1058 }
1059
1060 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1061 hdev->base_tqp_pid = 0;
1062 hdev->rss_size_max = 1;
1063 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1064 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1065 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1066 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1067 hdev->num_desc = cfg.tqp_desc_num;
1068 hdev->tm_info.num_pg = 1;
cacde272 1069 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1070 hdev->tm_info.hw_pfc_map = 0;
1071
1072 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1073 if (ret) {
1074 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1075 return ret;
1076 }
1077
cacde272
YL		 1078 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1079 (hdev->tc_max < 1)) {
46a3df9f 1080 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1081 hdev->tc_max);
1082 hdev->tc_max = 1;
46a3df9f
S		 1083 }
1084
cacde272
YL		 1085 /* Dev does not support DCB */
1086 if (!hnae3_dev_dcb_supported(hdev)) {
1087 hdev->tc_max = 1;
1088 hdev->pfc_max = 0;
1089 } else {
1090 hdev->pfc_max = hdev->tc_max;
1091 }
1092
1093 hdev->tm_info.num_tc = hdev->tc_max;
1094
46a3df9f 1095 /* Currently not support uncontiuous tc */
cacde272 1096 for (i = 0; i < hdev->tm_info.num_tc; i++)
46a3df9f
S		 1097 hnae_set_bit(hdev->hw_tc_map, i, 1);
1098
1099 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1100 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1101 else
1102 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1103
1104 return ret;
1105}
1106
1107static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1108 int tso_mss_max)
1109{
d44f9b63 1110 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1111 struct hclge_desc desc;
a90bb9a5 1112 u16 tso_mss;
46a3df9f
S		 1113
1114 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1115
d44f9b63 1116 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1117
1118 tso_mss = 0;
1119 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1120 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1121 req->tso_mss_min = cpu_to_le16(tso_mss);
1122
1123 tso_mss = 0;
1124 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1125 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1126 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1127
1128 return hclge_cmd_send(&hdev->hw, &desc, 1);
1129}
1130
1131static int hclge_alloc_tqps(struct hclge_dev *hdev)
1132{
1133 struct hclge_tqp *tqp;
1134 int i;
1135
1136 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1137 sizeof(struct hclge_tqp), GFP_KERNEL);
1138 if (!hdev->htqp)
1139 return -ENOMEM;
1140
1141 tqp = hdev->htqp;
1142
1143 for (i = 0; i < hdev->num_tqps; i++) {
1144 tqp->dev = &hdev->pdev->dev;
1145 tqp->index = i;
1146
1147 tqp->q.ae_algo = &ae_algo;
1148 tqp->q.buf_size = hdev->rx_buf_len;
1149 tqp->q.desc_num = hdev->num_desc;
1150 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1151 i * HCLGE_TQP_REG_SIZE;
1152
1153 tqp++;
1154 }
1155
1156 return 0;
1157}
1158
1159static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1160 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1161{
d44f9b63 1162 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1163 struct hclge_desc desc;
1164 int ret;
1165
1166 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1167
d44f9b63 1168 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1169 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1170 req->tqp_vf = func_id;
46a3df9f
S		 1171 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1172 1 << HCLGE_TQP_MAP_EN_B;
1173 req->tqp_vid = cpu_to_le16(tqp_vid);
1174
1175 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1176 if (ret) {
1177 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1178 ret);
1179 return ret;
1180 }
1181
1182 return 0;
1183}
1184
1185static int hclge_assign_tqp(struct hclge_vport *vport,
1186 struct hnae3_queue **tqp, u16 num_tqps)
1187{
1188 struct hclge_dev *hdev = vport->back;
7df7dad6 1189 int i, alloced;
46a3df9f
S		 1190
1191 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1192 alloced < num_tqps; i++) {
1193 if (!hdev->htqp[i].alloced) {
1194 hdev->htqp[i].q.handle = &vport->nic;
1195 hdev->htqp[i].q.tqp_index = alloced;
1196 tqp[alloced] = &hdev->htqp[i].q;
1197 hdev->htqp[i].alloced = true;
46a3df9f
S		 1198 alloced++;
1199 }
1200 }
1201 vport->alloc_tqps = num_tqps;
1202
1203 return 0;
1204}
1205
1206static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1207{
1208 struct hnae3_handle *nic = &vport->nic;
1209 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1210 struct hclge_dev *hdev = vport->back;
1211 int i, ret;
1212
1213 kinfo->num_desc = hdev->num_desc;
1214 kinfo->rx_buf_len = hdev->rx_buf_len;
1215 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1216 kinfo->rss_size
1217 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1218 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1219
1220 for (i = 0; i < HNAE3_MAX_TC; i++) {
1221 if (hdev->hw_tc_map & BIT(i)) {
1222 kinfo->tc_info[i].enable = true;
1223 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1224 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1225 kinfo->tc_info[i].tc = i;
1226 } else {
1227 /* Set to default queue if TC is disable */
1228 kinfo->tc_info[i].enable = false;
1229 kinfo->tc_info[i].tqp_offset = 0;
1230 kinfo->tc_info[i].tqp_count = 1;
1231 kinfo->tc_info[i].tc = 0;
1232 }
1233 }
1234
1235 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1236 sizeof(struct hnae3_queue *), GFP_KERNEL);
1237 if (!kinfo->tqp)
1238 return -ENOMEM;
1239
1240 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1241 if (ret) {
1242 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1243 return -EINVAL;
1244 }
1245
1246 return 0;
1247}
1248
7df7dad6
L		 1249static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1250 struct hclge_vport *vport)
1251{
1252 struct hnae3_handle *nic = &vport->nic;
1253 struct hnae3_knic_private_info *kinfo;
1254 u16 i;
1255
1256 kinfo = &nic->kinfo;
1257 for (i = 0; i < kinfo->num_tqps; i++) {
1258 struct hclge_tqp *q =
1259 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1260 bool is_pf;
1261 int ret;
1262
1263 is_pf = !(vport->vport_id);
1264 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1265 i, is_pf);
1266 if (ret)
1267 return ret;
1268 }
1269
1270 return 0;
1271}
1272
1273static int hclge_map_tqp(struct hclge_dev *hdev)
1274{
1275 struct hclge_vport *vport = hdev->vport;
1276 u16 i, num_vport;
1277
1278 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1279 for (i = 0; i < num_vport; i++) {
1280 int ret;
1281
1282 ret = hclge_map_tqp_to_vport(hdev, vport);
1283 if (ret)
1284 return ret;
1285
1286 vport++;
1287 }
1288
1289 return 0;
1290}
1291
46a3df9f
S		 1292static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1293{
1294 /* this would be initialized later */
1295}
1296
1297static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1298{
1299 struct hnae3_handle *nic = &vport->nic;
1300 struct hclge_dev *hdev = vport->back;
1301 int ret;
1302
1303 nic->pdev = hdev->pdev;
1304 nic->ae_algo = &ae_algo;
1305 nic->numa_node_mask = hdev->numa_node_mask;
1306
1307 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1308 ret = hclge_knic_setup(vport, num_tqps);
1309 if (ret) {
1310 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1311 ret);
1312 return ret;
1313 }
1314 } else {
1315 hclge_unic_setup(vport, num_tqps);
1316 }
1317
1318 return 0;
1319}
1320
1321static int hclge_alloc_vport(struct hclge_dev *hdev)
1322{
1323 struct pci_dev *pdev = hdev->pdev;
1324 struct hclge_vport *vport;
1325 u32 tqp_main_vport;
1326 u32 tqp_per_vport;
1327 int num_vport, i;
1328 int ret;
1329
1330 /* We need to alloc a vport for main NIC of PF */
1331 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1332
1333 if (hdev->num_tqps < num_vport)
1334 num_vport = hdev->num_tqps;
1335
1336 /* Alloc the same number of TQPs for every vport */
1337 tqp_per_vport = hdev->num_tqps / num_vport;
1338 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1339
1340 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1341 GFP_KERNEL);
1342 if (!vport)
1343 return -ENOMEM;
1344
1345 hdev->vport = vport;
1346 hdev->num_alloc_vport = num_vport;
1347
1348#ifdef CONFIG_PCI_IOV
1349 /* Enable SRIOV */
1350 if (hdev->num_req_vfs) {
1351 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1352 hdev->num_req_vfs);
1353 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1354 if (ret) {
1355 hdev->num_alloc_vfs = 0;
1356 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1357 ret);
1358 return ret;
1359 }
1360 }
1361 hdev->num_alloc_vfs = hdev->num_req_vfs;
1362#endif
1363
1364 for (i = 0; i < num_vport; i++) {
1365 vport->back = hdev;
1366 vport->vport_id = i;
1367
1368 if (i == 0)
1369 ret = hclge_vport_setup(vport, tqp_main_vport);
1370 else
1371 ret = hclge_vport_setup(vport, tqp_per_vport);
1372 if (ret) {
1373 dev_err(&pdev->dev,
1374 "vport setup failed for vport %d, %d\n",
1375 i, ret);
1376 return ret;
1377 }
1378
1379 vport++;
1380 }
1381
1382 return 0;
1383}
1384
acf61ecd
YL		 1385static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1386 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1387{
1388/* TX buffer size is unit by 128 byte */
1389#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1390#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1391 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1392 struct hclge_desc desc;
1393 int ret;
1394 u8 i;
1395
d44f9b63 1396 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1397
1398 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1399 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1400 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1401
46a3df9f
S		 1402 req->tx_pkt_buff[i] =
1403 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1404 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1405 }
46a3df9f
S		 1406
1407 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1408 if (ret) {
1409 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1410 ret);
1411 return ret;
1412 }
1413
1414 return 0;
1415}
1416
acf61ecd
YL		 1417static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1418 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1419{
acf61ecd 1420 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1421
1422 if (ret) {
1423 dev_err(&hdev->pdev->dev,
1424 "tx buffer alloc failed %d\n", ret);
1425 return ret;
1426 }
1427
1428 return 0;
1429}
1430
1431static int hclge_get_tc_num(struct hclge_dev *hdev)
1432{
1433 int i, cnt = 0;
1434
1435 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1436 if (hdev->hw_tc_map & BIT(i))
1437 cnt++;
1438 return cnt;
1439}
1440
1441static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1442{
1443 int i, cnt = 0;
1444
1445 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1446 if (hdev->hw_tc_map & BIT(i) &&
1447 hdev->tm_info.hw_pfc_map & BIT(i))
1448 cnt++;
1449 return cnt;
1450}
1451
1452/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1453static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1454 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1455{
1456 struct hclge_priv_buf *priv;
1457 int i, cnt = 0;
1458
1459 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1460 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1461 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1462 priv->enable)
1463 cnt++;
1464 }
1465
1466 return cnt;
1467}
1468
1469/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1470static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1471 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1472{
1473 struct hclge_priv_buf *priv;
1474 int i, cnt = 0;
1475
1476 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1477 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1478 if (hdev->hw_tc_map & BIT(i) &&
1479 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1480 priv->enable)
1481 cnt++;
1482 }
1483
1484 return cnt;
1485}
1486
acf61ecd 1487static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1488{
1489 struct hclge_priv_buf *priv;
1490 u32 rx_priv = 0;
1491 int i;
1492
1493 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1494 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1495 if (priv->enable)
1496 rx_priv += priv->buf_size;
1497 }
1498 return rx_priv;
1499}
1500
acf61ecd 1501static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1502{
1503 u32 i, total_tx_size = 0;
1504
1505 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1506 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1507
1508 return total_tx_size;
1509}
1510
acf61ecd
YL		 1511static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1512 struct hclge_pkt_buf_alloc *buf_alloc,
1513 u32 rx_all)
46a3df9f
S		 1514{
1515 u32 shared_buf_min, shared_buf_tc, shared_std;
1516 int tc_num, pfc_enable_num;
1517 u32 shared_buf;
1518 u32 rx_priv;
1519 int i;
1520
1521 tc_num = hclge_get_tc_num(hdev);
1522 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1523
d221df4e
YL		 1524 if (hnae3_dev_dcb_supported(hdev))
1525 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1526 else
1527 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1528
46a3df9f
S		 1529 shared_buf_tc = pfc_enable_num * hdev->mps +
1530 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1531 hdev->mps;
1532 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1533
acf61ecd 1534 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1535 if (rx_all <= rx_priv + shared_std)
1536 return false;
1537
1538 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1539 buf_alloc->s_buf.buf_size = shared_buf;
1540 buf_alloc->s_buf.self.high = shared_buf;
1541 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1542
1543 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1544 if ((hdev->hw_tc_map & BIT(i)) &&
1545 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1546 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1547 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1548 } else {
acf61ecd
YL		 1549 buf_alloc->s_buf.tc_thrd[i].low = 0;
1550 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1551 }
1552 }
1553
1554 return true;
1555}
1556
acf61ecd
YL		 1557static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1558 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1559{
1560 u32 i, total_size;
1561
1562 total_size = hdev->pkt_buf_size;
1563
1564 /* alloc tx buffer for all enabled tc */
1565 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1566 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1567
1568 if (total_size < HCLGE_DEFAULT_TX_BUF)
1569 return -ENOMEM;
1570
1571 if (hdev->hw_tc_map & BIT(i))
1572 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1573 else
1574 priv->tx_buf_size = 0;
1575
1576 total_size -= priv->tx_buf_size;
1577 }
1578
1579 return 0;
1580}
1581
46a3df9f
S		 1582/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1583 * @hdev: pointer to struct hclge_dev
acf61ecd 1584 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1585 * @return: 0: calculate sucessful, negative: fail
1586 */
1db9b1bf
YL		 1587static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1588 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1589{
9ffe79a9 1590 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1591 int no_pfc_priv_num, pfc_priv_num;
1592 struct hclge_priv_buf *priv;
1593 int i;
1594
acf61ecd 1595 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1596
d602a525
YL		 1597 /* When DCB is not supported, rx private
1598 * buffer is not allocated.
1599 */
1600 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1601 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1602 return -ENOMEM;
1603
1604 return 0;
1605 }
1606
46a3df9f
S		 1607 /* step 1, try to alloc private buffer for all enabled tc */
1608 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1609 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1610 if (hdev->hw_tc_map & BIT(i)) {
1611 priv->enable = 1;
1612 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1613 priv->wl.low = hdev->mps;
1614 priv->wl.high = priv->wl.low + hdev->mps;
1615 priv->buf_size = priv->wl.high +
1616 HCLGE_DEFAULT_DV;
1617 } else {
1618 priv->wl.low = 0;
1619 priv->wl.high = 2 * hdev->mps;
1620 priv->buf_size = priv->wl.high;
1621 }
bb1fe9ea
YL		 1622 } else {
1623 priv->enable = 0;
1624 priv->wl.low = 0;
1625 priv->wl.high = 0;
1626 priv->buf_size = 0;
46a3df9f
S		 1627 }
1628 }
1629
acf61ecd 1630 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1631 return 0;
1632
1633 /* step 2, try to decrease the buffer size of
1634 * no pfc TC's private buffer
1635 */
1636 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1637 priv = &buf_alloc->priv_buf[i];
46a3df9f 1638
bb1fe9ea
YL		 1639 priv->enable = 0;
1640 priv->wl.low = 0;
1641 priv->wl.high = 0;
1642 priv->buf_size = 0;
1643
1644 if (!(hdev->hw_tc_map & BIT(i)))
1645 continue;
1646
1647 priv->enable = 1;
46a3df9f
S		 1648
1649 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1650 priv->wl.low = 128;
1651 priv->wl.high = priv->wl.low + hdev->mps;
1652 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1653 } else {
1654 priv->wl.low = 0;
1655 priv->wl.high = hdev->mps;
1656 priv->buf_size = priv->wl.high;
1657 }
1658 }
1659
acf61ecd 1660 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1661 return 0;
1662
1663 /* step 3, try to reduce the number of pfc disabled TCs,
1664 * which have private buffer
1665 */
1666 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1667 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1668
1669 /* let the last to be cleared first */
1670 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1671 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1672
1673 if (hdev->hw_tc_map & BIT(i) &&
1674 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1675 /* Clear the no pfc TC private buffer */
1676 priv->wl.low = 0;
1677 priv->wl.high = 0;
1678 priv->buf_size = 0;
1679 priv->enable = 0;
1680 no_pfc_priv_num--;
1681 }
1682
acf61ecd 1683 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1684 no_pfc_priv_num == 0)
1685 break;
1686 }
1687
acf61ecd 1688 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1689 return 0;
1690
1691 /* step 4, try to reduce the number of pfc enabled TCs
1692 * which have private buffer.
1693 */
acf61ecd 1694 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1695
1696 /* let the last to be cleared first */
1697 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1698 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1699
1700 if (hdev->hw_tc_map & BIT(i) &&
1701 hdev->tm_info.hw_pfc_map & BIT(i)) {
1702 /* Reduce the number of pfc TC with private buffer */
1703 priv->wl.low = 0;
1704 priv->enable = 0;
1705 priv->wl.high = 0;
1706 priv->buf_size = 0;
1707 pfc_priv_num--;
1708 }
1709
acf61ecd 1710 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1711 pfc_priv_num == 0)
1712 break;
1713 }
acf61ecd 1714 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1715 return 0;
1716
1717 return -ENOMEM;
1718}
1719
acf61ecd
YL		 1720static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1721 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1722{
d44f9b63 1723 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1724 struct hclge_desc desc;
1725 int ret;
1726 int i;
1727
1728 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1729 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1730
1731 /* Alloc private buffer TCs */
1732 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1733 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1734
1735 req->buf_num[i] =
1736 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1737 req->buf_num[i] |=
5bca3b94 1738 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1739 }
1740
b8c8bf47 1741 req->shared_buf =
acf61ecd 1742 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1743 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1744
46a3df9f
S		 1745 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1746 if (ret) {
1747 dev_err(&hdev->pdev->dev,
1748 "rx private buffer alloc cmd failed %d\n", ret);
1749 return ret;
1750 }
1751
1752 return 0;
1753}
1754
1755#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1756
acf61ecd
YL		 1757static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1758 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1759{
1760 struct hclge_rx_priv_wl_buf *req;
1761 struct hclge_priv_buf *priv;
1762 struct hclge_desc desc[2];
1763 int i, j;
1764 int ret;
1765
1766 for (i = 0; i < 2; i++) {
1767 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1768 false);
1769 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1770
1771 /* The first descriptor set the NEXT bit to 1 */
1772 if (i == 0)
1773 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1774 else
1775 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1776
1777 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1778 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1779
1780 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1781 req->tc_wl[j].high =
1782 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1783 req->tc_wl[j].high |=
1784 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1785 HCLGE_RX_PRIV_EN_B);
1786 req->tc_wl[j].low =
1787 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1788 req->tc_wl[j].low |=
1789 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1790 HCLGE_RX_PRIV_EN_B);
1791 }
1792 }
1793
1794 /* Send 2 descriptor at one time */
1795 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1796 if (ret) {
1797 dev_err(&hdev->pdev->dev,
1798 "rx private waterline config cmd failed %d\n",
1799 ret);
1800 return ret;
1801 }
1802 return 0;
1803}
1804
acf61ecd
YL		 1805static int hclge_common_thrd_config(struct hclge_dev *hdev,
1806 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1807{
acf61ecd 1808 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1809 struct hclge_rx_com_thrd *req;
1810 struct hclge_desc desc[2];
1811 struct hclge_tc_thrd *tc;
1812 int i, j;
1813 int ret;
1814
1815 for (i = 0; i < 2; i++) {
1816 hclge_cmd_setup_basic_desc(&desc[i],
1817 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1818 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1819
1820 /* The first descriptor set the NEXT bit to 1 */
1821 if (i == 0)
1822 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1823 else
1824 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1825
1826 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1827 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1828
1829 req->com_thrd[j].high =
1830 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1831 req->com_thrd[j].high |=
1832 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1833 HCLGE_RX_PRIV_EN_B);
1834 req->com_thrd[j].low =
1835 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1836 req->com_thrd[j].low |=
1837 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1838 HCLGE_RX_PRIV_EN_B);
1839 }
1840 }
1841
1842 /* Send 2 descriptors at one time */
1843 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1844 if (ret) {
1845 dev_err(&hdev->pdev->dev,
1846 "common threshold config cmd failed %d\n", ret);
1847 return ret;
1848 }
1849 return 0;
1850}
1851
acf61ecd
YL		 1852static int hclge_common_wl_config(struct hclge_dev *hdev,
1853 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1854{
acf61ecd 1855 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1856 struct hclge_rx_com_wl *req;
1857 struct hclge_desc desc;
1858 int ret;
1859
1860 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1861
1862 req = (struct hclge_rx_com_wl *)desc.data;
1863 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1864 req->com_wl.high |=
1865 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1866 HCLGE_RX_PRIV_EN_B);
1867
1868 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1869 req->com_wl.low |=
1870 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1871 HCLGE_RX_PRIV_EN_B);
1872
1873 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1874 if (ret) {
1875 dev_err(&hdev->pdev->dev,
1876 "common waterline config cmd failed %d\n", ret);
1877 return ret;
1878 }
1879
1880 return 0;
1881}
1882
1883int hclge_buffer_alloc(struct hclge_dev *hdev)
1884{
acf61ecd 1885 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1886 int ret;
1887
acf61ecd
YL		 1888 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1889 if (!pkt_buf)
46a3df9f
S		 1890 return -ENOMEM;
1891
acf61ecd 1892 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1893 if (ret) {
1894 dev_err(&hdev->pdev->dev,
1895 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1896 goto out;
9ffe79a9
YL		 1897 }
1898
acf61ecd 1899 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1900 if (ret) {
1901 dev_err(&hdev->pdev->dev,
1902 "could not alloc tx buffers %d\n", ret);
acf61ecd 1903 goto out;
46a3df9f
S		 1904 }
1905
acf61ecd 1906 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1907 if (ret) {
1908 dev_err(&hdev->pdev->dev,
1909 "could not calc rx priv buffer size for all TCs %d\n",
1910 ret);
acf61ecd 1911 goto out;
46a3df9f
S		 1912 }
1913
acf61ecd 1914 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1915 if (ret) {
1916 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1917 ret);
acf61ecd 1918 goto out;
46a3df9f
S		 1919 }
1920
2daf4a65 1921 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1922 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1923 if (ret) {
1924 dev_err(&hdev->pdev->dev,
1925 "could not configure rx private waterline %d\n",
1926 ret);
acf61ecd 1927 goto out;
2daf4a65 1928 }
46a3df9f 1929
acf61ecd 1930 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1931 if (ret) {
1932 dev_err(&hdev->pdev->dev,
1933 "could not configure common threshold %d\n",
1934 ret);
acf61ecd 1935 goto out;
2daf4a65 1936 }
46a3df9f
S		 1937 }
1938
acf61ecd
YL		 1939 ret = hclge_common_wl_config(hdev, pkt_buf);
1940 if (ret)
46a3df9f
S		 1941 dev_err(&hdev->pdev->dev,
1942 "could not configure common waterline %d\n", ret);
46a3df9f 1943
acf61ecd
YL		 1944out:
1945 kfree(pkt_buf);
1946 return ret;
46a3df9f
S		 1947}
1948
1949static int hclge_init_roce_base_info(struct hclge_vport *vport)
1950{
1951 struct hnae3_handle *roce = &vport->roce;
1952 struct hnae3_handle *nic = &vport->nic;
1953
887c3820 1954 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1955
1956 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1957 vport->back->num_msi_left == 0)
1958 return -EINVAL;
1959
1960 roce->rinfo.base_vector = vport->back->roce_base_vector;
1961
1962 roce->rinfo.netdev = nic->kinfo.netdev;
1963 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1964
1965 roce->pdev = nic->pdev;
1966 roce->ae_algo = nic->ae_algo;
1967 roce->numa_node_mask = nic->numa_node_mask;
1968
1969 return 0;
1970}
1971
887c3820 1972static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1973{
1974 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1975 int vectors;
1976 int i;
46a3df9f 1977
887c3820
SM		 1978 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1979 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1980 if (vectors < 0) {
1981 dev_err(&pdev->dev,
1982 "failed(%d) to allocate MSI/MSI-X vectors\n",
1983 vectors);
1984 return vectors;
46a3df9f 1985 }
887c3820
SM		 1986 if (vectors < hdev->num_msi)
1987 dev_warn(&hdev->pdev->dev,
1988 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1989 hdev->num_msi, vectors);
46a3df9f 1990
887c3820
SM		 1991 hdev->num_msi = vectors;
1992 hdev->num_msi_left = vectors;
1993 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 1994 hdev->roce_base_vector = hdev->base_msi_vector +
1995 HCLGE_ROCE_VECTOR_OFFSET;
1996
46a3df9f
S		 1997 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1998 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1999 if (!hdev->vector_status) {
2000 pci_free_irq_vectors(pdev);
46a3df9f 2001 return -ENOMEM;
887c3820 2002 }
46a3df9f
S		 2003
2004 for (i = 0; i < hdev->num_msi; i++)
2005 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2006
887c3820
SM		 2007 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2008 sizeof(int), GFP_KERNEL);
2009 if (!hdev->vector_irq) {
2010 pci_free_irq_vectors(pdev);
2011 return -ENOMEM;
46a3df9f 2012 }
46a3df9f
S		 2013
2014 return 0;
2015}
2016
2017static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2018{
2019 struct hclge_mac *mac = &hdev->hw.mac;
2020
2021 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2022 mac->duplex = (u8)duplex;
2023 else
2024 mac->duplex = HCLGE_MAC_FULL;
2025
2026 mac->speed = speed;
2027}
2028
2029int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2030{
d44f9b63 2031 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2032 struct hclge_desc desc;
2033 int ret;
2034
d44f9b63 2035 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2036
2037 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2038
2039 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2040
2041 switch (speed) {
2042 case HCLGE_MAC_SPEED_10M:
2043 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2044 HCLGE_CFG_SPEED_S, 6);
2045 break;
2046 case HCLGE_MAC_SPEED_100M:
2047 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2048 HCLGE_CFG_SPEED_S, 7);
2049 break;
2050 case HCLGE_MAC_SPEED_1G:
2051 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2052 HCLGE_CFG_SPEED_S, 0);
2053 break;
2054 case HCLGE_MAC_SPEED_10G:
2055 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2056 HCLGE_CFG_SPEED_S, 1);
2057 break;
2058 case HCLGE_MAC_SPEED_25G:
2059 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2060 HCLGE_CFG_SPEED_S, 2);
2061 break;
2062 case HCLGE_MAC_SPEED_40G:
2063 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2064 HCLGE_CFG_SPEED_S, 3);
2065 break;
2066 case HCLGE_MAC_SPEED_50G:
2067 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2068 HCLGE_CFG_SPEED_S, 4);
2069 break;
2070 case HCLGE_MAC_SPEED_100G:
2071 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2072 HCLGE_CFG_SPEED_S, 5);
2073 break;
2074 default:
d7629e74 2075 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2076 return -EINVAL;
2077 }
2078
2079 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2080 1);
2081
2082 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2083 if (ret) {
2084 dev_err(&hdev->pdev->dev,
2085 "mac speed/duplex config cmd failed %d.\n", ret);
2086 return ret;
2087 }
2088
2089 hclge_check_speed_dup(hdev, duplex, speed);
2090
2091 return 0;
2092}
2093
2094static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2095 u8 duplex)
2096{
2097 struct hclge_vport *vport = hclge_get_vport(handle);
2098 struct hclge_dev *hdev = vport->back;
2099
2100 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2101}
2102
2103static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2104 u8 *duplex)
2105{
d44f9b63 2106 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2107 struct hclge_desc desc;
2108 int speed_tmp;
2109 int ret;
2110
d44f9b63 2111 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2112
2113 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2114 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2115 if (ret) {
2116 dev_err(&hdev->pdev->dev,
2117 "mac speed/autoneg/duplex query cmd failed %d\n",
2118 ret);
2119 return ret;
2120 }
2121
2122 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2123 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2124 HCLGE_QUERY_SPEED_S);
2125
2126 ret = hclge_parse_speed(speed_tmp, speed);
2127 if (ret) {
2128 dev_err(&hdev->pdev->dev,
2129 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2130 return -EIO;
2131 }
2132
2133 return 0;
2134}
2135
2136static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2137{
2138 struct hclge_mac *mac = &hdev->hw.mac;
d44f9b63 2139 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2140 struct hclge_desc desc;
2141 int ret;
2142
d44f9b63 2143 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2144
2145 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2146 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2147 if (ret) {
2148 dev_err(&hdev->pdev->dev,
2149 "autoneg result query cmd failed %d.\n", ret);
2150 return ret;
2151 }
2152
2153 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2154
2155 return 0;
2156}
2157
2158static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2159{
d44f9b63 2160 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2161 struct hclge_desc desc;
a90bb9a5 2162 u32 flag = 0;
46a3df9f
S		 2163 int ret;
2164
2165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2166
d44f9b63 2167 req = (struct hclge_config_auto_neg_cmd *)desc.data;
a90bb9a5
YL		 2168 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2169 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2170
2171 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2172 if (ret) {
2173 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2174 ret);
2175 return ret;
2176 }
2177
2178 return 0;
2179}
2180
2181static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2182{
2183 struct hclge_vport *vport = hclge_get_vport(handle);
2184 struct hclge_dev *hdev = vport->back;
2185
2186 return hclge_set_autoneg_en(hdev, enable);
2187}
2188
2189static int hclge_get_autoneg(struct hnae3_handle *handle)
2190{
2191 struct hclge_vport *vport = hclge_get_vport(handle);
2192 struct hclge_dev *hdev = vport->back;
2193
2194 hclge_query_autoneg_result(hdev);
2195
2196 return hdev->hw.mac.autoneg;
2197}
2198
2199static int hclge_mac_init(struct hclge_dev *hdev)
2200{
2201 struct hclge_mac *mac = &hdev->hw.mac;
2202 int ret;
2203
2204 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2205 if (ret) {
2206 dev_err(&hdev->pdev->dev,
2207 "Config mac speed dup fail ret=%d\n", ret);
2208 return ret;
2209 }
2210
2211 mac->link = 0;
2212
46a3df9f
S		 2213 /* Initialize the MTA table work mode */
2214 hdev->accept_mta_mc = true;
2215 hdev->enable_mta = true;
2216 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2217
2218 ret = hclge_set_mta_filter_mode(hdev,
2219 hdev->mta_mac_sel_type,
2220 hdev->enable_mta);
2221 if (ret) {
2222 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2223 ret);
2224 return ret;
2225 }
2226
2227 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2228}
2229
ed4a1bb8
SM		 2230static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2231{
2232 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2233 schedule_work(&hdev->rst_service_task);
2234}
2235
46a3df9f
S		 2236static void hclge_task_schedule(struct hclge_dev *hdev)
2237{
2238 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2239 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2240 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2241 (void)schedule_work(&hdev->service_task);
2242}
2243
2244static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2245{
d44f9b63 2246 struct hclge_link_status_cmd *req;
46a3df9f
S		 2247 struct hclge_desc desc;
2248 int link_status;
2249 int ret;
2250
2251 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2252 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2253 if (ret) {
2254 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2255 ret);
2256 return ret;
2257 }
2258
d44f9b63 2259 req = (struct hclge_link_status_cmd *)desc.data;
46a3df9f
S		 2260 link_status = req->status & HCLGE_LINK_STATUS;
2261
2262 return !!link_status;
2263}
2264
2265static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2266{
2267 int mac_state;
2268 int link_stat;
2269
2270 mac_state = hclge_get_mac_link_status(hdev);
2271
2272 if (hdev->hw.mac.phydev) {
2273 if (!genphy_read_status(hdev->hw.mac.phydev))
2274 link_stat = mac_state &
2275 hdev->hw.mac.phydev->link;
2276 else
2277 link_stat = 0;
2278
2279 } else {
2280 link_stat = mac_state;
2281 }
2282
2283 return !!link_stat;
2284}
2285
2286static void hclge_update_link_status(struct hclge_dev *hdev)
2287{
2288 struct hnae3_client *client = hdev->nic_client;
2289 struct hnae3_handle *handle;
2290 int state;
2291 int i;
2292
2293 if (!client)
2294 return;
2295 state = hclge_get_mac_phy_link(hdev);
2296 if (state != hdev->hw.mac.link) {
2297 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2298 handle = &hdev->vport[i].nic;
2299 client->ops->link_status_change(handle, state);
2300 }
2301 hdev->hw.mac.link = state;
2302 }
2303}
2304
2305static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2306{
2307 struct hclge_mac mac = hdev->hw.mac;
2308 u8 duplex;
2309 int speed;
2310 int ret;
2311
2312 /* get the speed and duplex as autoneg'result from mac cmd when phy
2313 * doesn't exit.
2314 */
c040366b 2315 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2316 return 0;
2317
2318 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2319 if (ret) {
2320 dev_err(&hdev->pdev->dev,
2321 "mac autoneg/speed/duplex query failed %d\n", ret);
2322 return ret;
2323 }
2324
2325 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2326 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2327 if (ret) {
2328 dev_err(&hdev->pdev->dev,
2329 "mac speed/duplex config failed %d\n", ret);
2330 return ret;
2331 }
2332 }
2333
2334 return 0;
2335}
2336
2337static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2338{
2339 struct hclge_vport *vport = hclge_get_vport(handle);
2340 struct hclge_dev *hdev = vport->back;
2341
2342 return hclge_update_speed_duplex(hdev);
2343}
2344
2345static int hclge_get_status(struct hnae3_handle *handle)
2346{
2347 struct hclge_vport *vport = hclge_get_vport(handle);
2348 struct hclge_dev *hdev = vport->back;
2349
2350 hclge_update_link_status(hdev);
2351
2352 return hdev->hw.mac.link;
2353}
2354
d039ef68 2355static void hclge_service_timer(struct timer_list *t)
46a3df9f 2356{
d039ef68 2357 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2358
d039ef68 2359 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 2360 hclge_task_schedule(hdev);
2361}
2362
2363static void hclge_service_complete(struct hclge_dev *hdev)
2364{
2365 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2366
2367 /* Flush memory before next watchdog */
2368 smp_mb__before_atomic();
2369 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2370}
2371
202f2014
SM		 2372static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2373{
2374 u32 rst_src_reg;
2375
2376 /* fetch the events from their corresponding regs */
2377 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2378
2379 /* check for vector0 reset event sources */
2380 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2381 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2382 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2383 return HCLGE_VECTOR0_EVENT_RST;
2384 }
2385
2386 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2387 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2388 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2389 return HCLGE_VECTOR0_EVENT_RST;
2390 }
2391
2392 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2393 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2394 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2395 return HCLGE_VECTOR0_EVENT_RST;
2396 }
2397
2398 /* mailbox event sharing vector 0 interrupt would be placed here */
2399
2400 return HCLGE_VECTOR0_EVENT_OTHER;
2401}
2402
2403static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2404 u32 regclr)
2405{
2406 if (event_type == HCLGE_VECTOR0_EVENT_RST)
2407 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2408
2409 /* mailbox event sharing vector 0 interrupt would be placed here */
2410}
2411
466b0c00
L		 2412static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2413{
2414 writel(enable ? 1 : 0, vector->addr);
2415}
2416
2417static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2418{
2419 struct hclge_dev *hdev = data;
202f2014
SM		 2420 u32 event_cause;
2421 u32 clearval;
466b0c00
L		 2422
2423 hclge_enable_vector(&hdev->misc_vector, false);
202f2014
SM		 2424 event_cause = hclge_check_event_cause(hdev, &clearval);
2425
2426 /* vector 0 interrupt is shared with reset and mailbox source events.
2427 * For now, we are not handling mailbox events.
2428 */
2429 switch (event_cause) {
2430 case HCLGE_VECTOR0_EVENT_RST:
ed4a1bb8 2431 hclge_reset_task_schedule(hdev);
202f2014
SM		 2432 break;
2433 default:
2434 dev_dbg(&hdev->pdev->dev,
2435 "received unknown or unhandled event of vector0\n");
2436 break;
2437 }
2438
2439 /* we should clear the source of interrupt */
2440 hclge_clear_event_cause(hdev, event_cause, clearval);
2441 hclge_enable_vector(&hdev->misc_vector, true);
466b0c00
L		 2442
2443 return IRQ_HANDLED;
2444}
2445
2446static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2447{
2448 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2449 hdev->num_msi_left += 1;
2450 hdev->num_msi_used -= 1;
2451}
2452
2453static void hclge_get_misc_vector(struct hclge_dev *hdev)
2454{
2455 struct hclge_misc_vector *vector = &hdev->misc_vector;
2456
2457 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2458
2459 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2460 hdev->vector_status[0] = 0;
2461
2462 hdev->num_msi_left -= 1;
2463 hdev->num_msi_used += 1;
2464}
2465
2466static int hclge_misc_irq_init(struct hclge_dev *hdev)
2467{
2468 int ret;
2469
2470 hclge_get_misc_vector(hdev);
2471
202f2014
SM		 2472 /* this would be explicitly freed in the end */
2473 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2474 0, "hclge_misc", hdev);
466b0c00
L		 2475 if (ret) {
2476 hclge_free_vector(hdev, 0);
2477 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2478 hdev->misc_vector.vector_irq);
2479 }
2480
2481 return ret;
2482}
2483
202f2014
SM		 2484static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2485{
2486 free_irq(hdev->misc_vector.vector_irq, hdev);
2487 hclge_free_vector(hdev, 0);
2488}
2489
4ed340ab
L		 2490static int hclge_notify_client(struct hclge_dev *hdev,
2491 enum hnae3_reset_notify_type type)
2492{
2493 struct hnae3_client *client = hdev->nic_client;
2494 u16 i;
2495
2496 if (!client->ops->reset_notify)
2497 return -EOPNOTSUPP;
2498
2499 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2500 struct hnae3_handle *handle = &hdev->vport[i].nic;
2501 int ret;
2502
2503 ret = client->ops->reset_notify(handle, type);
2504 if (ret)
2505 return ret;
2506 }
2507
2508 return 0;
2509}
2510
2511static int hclge_reset_wait(struct hclge_dev *hdev)
2512{
2513#define HCLGE_RESET_WATI_MS 100
2514#define HCLGE_RESET_WAIT_CNT 5
2515 u32 val, reg, reg_bit;
2516 u32 cnt = 0;
2517
2518 switch (hdev->reset_type) {
2519 case HNAE3_GLOBAL_RESET:
2520 reg = HCLGE_GLOBAL_RESET_REG;
2521 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2522 break;
2523 case HNAE3_CORE_RESET:
2524 reg = HCLGE_GLOBAL_RESET_REG;
2525 reg_bit = HCLGE_CORE_RESET_BIT;
2526 break;
2527 case HNAE3_FUNC_RESET:
2528 reg = HCLGE_FUN_RST_ING;
2529 reg_bit = HCLGE_FUN_RST_ING_B;
2530 break;
2531 default:
2532 dev_err(&hdev->pdev->dev,
2533 "Wait for unsupported reset type: %d\n",
2534 hdev->reset_type);
2535 return -EINVAL;
2536 }
2537
2538 val = hclge_read_dev(&hdev->hw, reg);
2539 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2540 msleep(HCLGE_RESET_WATI_MS);
2541 val = hclge_read_dev(&hdev->hw, reg);
2542 cnt++;
2543 }
2544
4ed340ab
L		 2545 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2546 dev_warn(&hdev->pdev->dev,
2547 "Wait for reset timeout: %d\n", hdev->reset_type);
2548 return -EBUSY;
2549 }
2550
2551 return 0;
2552}
2553
2554static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2555{
2556 struct hclge_desc desc;
2557 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2558 int ret;
2559
2560 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2561 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2562 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2563 req->fun_reset_vfid = func_id;
2564
2565 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2566 if (ret)
2567 dev_err(&hdev->pdev->dev,
2568 "send function reset cmd fail, status =%d\n", ret);
2569
2570 return ret;
2571}
2572
d5752031 2573static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2574{
2575 struct pci_dev *pdev = hdev->pdev;
2576 u32 val;
2577
d5752031 2578 switch (hdev->reset_type) {
4ed340ab
L		 2579 case HNAE3_GLOBAL_RESET:
2580 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2581 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2582 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2583 dev_info(&pdev->dev, "Global Reset requested\n");
2584 break;
2585 case HNAE3_CORE_RESET:
2586 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2587 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2588 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2589 dev_info(&pdev->dev, "Core Reset requested\n");
2590 break;
2591 case HNAE3_FUNC_RESET:
2592 dev_info(&pdev->dev, "PF Reset requested\n");
2593 hclge_func_reset_cmd(hdev, 0);
ed4a1bb8
SM		 2594 /* schedule again to check later */
2595 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2596 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2597 break;
2598 default:
2599 dev_warn(&pdev->dev,
d5752031 2600 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2601 break;
2602 }
2603}
2604
d5752031
SM		 2605static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2606 unsigned long *addr)
2607{
2608 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2609
2610 /* return the highest priority reset level amongst all */
2611 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2612 rst_level = HNAE3_GLOBAL_RESET;
2613 else if (test_bit(HNAE3_CORE_RESET, addr))
2614 rst_level = HNAE3_CORE_RESET;
2615 else if (test_bit(HNAE3_IMP_RESET, addr))
2616 rst_level = HNAE3_IMP_RESET;
2617 else if (test_bit(HNAE3_FUNC_RESET, addr))
2618 rst_level = HNAE3_FUNC_RESET;
2619
2620 /* now, clear all other resets */
2621 clear_bit(HNAE3_GLOBAL_RESET, addr);
2622 clear_bit(HNAE3_CORE_RESET, addr);
2623 clear_bit(HNAE3_IMP_RESET, addr);
2624 clear_bit(HNAE3_FUNC_RESET, addr);
2625
2626 return rst_level;
2627}
2628
2629static void hclge_reset(struct hclge_dev *hdev)
2630{
2631 /* perform reset of the stack & ae device for a client */
2632
2633 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2634
2635 if (!hclge_reset_wait(hdev)) {
2636 rtnl_lock();
2637 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2638 hclge_reset_ae_dev(hdev->ae_dev);
2639 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2640 rtnl_unlock();
2641 } else {
2642 /* schedule again to check pending resets later */
2643 set_bit(hdev->reset_type, &hdev->reset_pending);
2644 hclge_reset_task_schedule(hdev);
2645 }
2646
2647 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2648}
2649
4ed340ab
L		 2650static void hclge_reset_event(struct hnae3_handle *handle,
2651 enum hnae3_reset_type reset)
2652{
2653 struct hclge_vport *vport = hclge_get_vport(handle);
2654 struct hclge_dev *hdev = vport->back;
2655
2656 dev_info(&hdev->pdev->dev,
2657 "Receive reset event , reset_type is %d", reset);
2658
2659 switch (reset) {
2660 case HNAE3_FUNC_RESET:
2661 case HNAE3_CORE_RESET:
2662 case HNAE3_GLOBAL_RESET:
ed4a1bb8
SM		 2663 /* request reset & schedule reset task */
2664 set_bit(reset, &hdev->reset_request);
2665 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2666 break;
2667 default:
2668 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2669 break;
2670 }
2671}
2672
2673static void hclge_reset_subtask(struct hclge_dev *hdev)
2674{
d5752031
SM		 2675 /* check if there is any ongoing reset in the hardware. This status can
2676 * be checked from reset_pending. If there is then, we need to wait for
2677 * hardware to complete reset.
2678 * a. If we are able to figure out in reasonable time that hardware
2679 * has fully resetted then, we can proceed with driver, client
2680 * reset.
2681 * b. else, we can come back later to check this status so re-sched
2682 * now.
2683 */
2684 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2685 if (hdev->reset_type != HNAE3_NONE_RESET)
2686 hclge_reset(hdev);
4ed340ab 2687
d5752031
SM		 2688 /* check if we got any *new* reset requests to be honored */
2689 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2690 if (hdev->reset_type != HNAE3_NONE_RESET)
2691 hclge_do_reset(hdev);
4ed340ab 2692
4ed340ab
L		 2693 hdev->reset_type = HNAE3_NONE_RESET;
2694}
2695
ed4a1bb8 2696static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2697{
ed4a1bb8
SM		 2698 struct hclge_dev *hdev =
2699 container_of(work, struct hclge_dev, rst_service_task);
2700
2701 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2702 return;
2703
2704 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2705
4ed340ab 2706 hclge_reset_subtask(hdev);
ed4a1bb8
SM		 2707
2708 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2709}
2710
46a3df9f
S		 2711static void hclge_service_task(struct work_struct *work)
2712{
2713 struct hclge_dev *hdev =
2714 container_of(work, struct hclge_dev, service_task);
2715
2716 hclge_update_speed_duplex(hdev);
2717 hclge_update_link_status(hdev);
2718 hclge_update_stats_for_all(hdev);
2719 hclge_service_complete(hdev);
2720}
2721
2722static void hclge_disable_sriov(struct hclge_dev *hdev)
2723{
2a32ca13
AB		 2724 /* If our VFs are assigned we cannot shut down SR-IOV
2725 * without causing issues, so just leave the hardware
2726 * available but disabled
2727 */
2728 if (pci_vfs_assigned(hdev->pdev)) {
2729 dev_warn(&hdev->pdev->dev,
2730 "disabling driver while VFs are assigned\n");
2731 return;
2732 }
46a3df9f 2733
2a32ca13 2734 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2735}
2736
2737struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2738{
2739 /* VF handle has no client */
2740 if (!handle->client)
2741 return container_of(handle, struct hclge_vport, nic);
2742 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2743 return container_of(handle, struct hclge_vport, roce);
2744 else
2745 return container_of(handle, struct hclge_vport, nic);
2746}
2747
2748static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2749 struct hnae3_vector_info *vector_info)
2750{
2751 struct hclge_vport *vport = hclge_get_vport(handle);
2752 struct hnae3_vector_info *vector = vector_info;
2753 struct hclge_dev *hdev = vport->back;
2754 int alloc = 0;
2755 int i, j;
2756
2757 vector_num = min(hdev->num_msi_left, vector_num);
2758
2759 for (j = 0; j < vector_num; j++) {
2760 for (i = 1; i < hdev->num_msi; i++) {
2761 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2762 vector->vector = pci_irq_vector(hdev->pdev, i);
2763 vector->io_addr = hdev->hw.io_base +
2764 HCLGE_VECTOR_REG_BASE +
2765 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2766 vport->vport_id *
2767 HCLGE_VECTOR_VF_OFFSET;
2768 hdev->vector_status[i] = vport->vport_id;
887c3820 2769 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2770
2771 vector++;
2772 alloc++;
2773
2774 break;
2775 }
2776 }
2777 }
2778 hdev->num_msi_left -= alloc;
2779 hdev->num_msi_used += alloc;
2780
2781 return alloc;
2782}
2783
2784static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2785{
2786 int i;
2787
887c3820
SM		 2788 for (i = 0; i < hdev->num_msi; i++)
2789 if (vector == hdev->vector_irq[i])
2790 return i;
2791
46a3df9f
S		 2792 return -EINVAL;
2793}
2794
2795static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2796{
2797 return HCLGE_RSS_KEY_SIZE;
2798}
2799
2800static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2801{
2802 return HCLGE_RSS_IND_TBL_SIZE;
2803}
2804
2805static int hclge_get_rss_algo(struct hclge_dev *hdev)
2806{
d44f9b63 2807 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2808 struct hclge_desc desc;
2809 int rss_hash_algo;
2810 int ret;
2811
2812 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2813
2814 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2815 if (ret) {
2816 dev_err(&hdev->pdev->dev,
2817 "Get link status error, status =%d\n", ret);
2818 return ret;
2819 }
2820
d44f9b63 2821 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2822 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2823
2824 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2825 return ETH_RSS_HASH_TOP;
2826
2827 return -EINVAL;
2828}
2829
2830static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2831 const u8 hfunc, const u8 *key)
2832{
d44f9b63 2833 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2834 struct hclge_desc desc;
2835 int key_offset;
2836 int key_size;
2837 int ret;
2838
d44f9b63 2839 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2840
2841 for (key_offset = 0; key_offset < 3; key_offset++) {
2842 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2843 false);
2844
2845 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2846 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2847
2848 if (key_offset == 2)
2849 key_size =
2850 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2851 else
2852 key_size = HCLGE_RSS_HASH_KEY_NUM;
2853
2854 memcpy(req->hash_key,
2855 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2856
2857 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2858 if (ret) {
2859 dev_err(&hdev->pdev->dev,
2860 "Configure RSS config fail, status = %d\n",
2861 ret);
2862 return ret;
2863 }
2864 }
2865 return 0;
2866}
2867
2868static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2869{
d44f9b63 2870 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 2871 struct hclge_desc desc;
2872 int i, j;
2873 int ret;
2874
d44f9b63 2875 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 2876
2877 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2878 hclge_cmd_setup_basic_desc
2879 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2880
a90bb9a5
YL		 2881 req->start_table_index =
2882 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2883 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 2884
2885 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2886 req->rss_result[j] =
2887 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2888
2889 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2890 if (ret) {
2891 dev_err(&hdev->pdev->dev,
2892 "Configure rss indir table fail,status = %d\n",
2893 ret);
2894 return ret;
2895 }
2896 }
2897 return 0;
2898}
2899
2900static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2901 u16 *tc_size, u16 *tc_offset)
2902{
d44f9b63 2903 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 2904 struct hclge_desc desc;
2905 int ret;
2906 int i;
2907
2908 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 2909 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 2910
2911 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 2912 u16 mode = 0;
2913
2914 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2915 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
46a3df9f 2916 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
a90bb9a5 2917 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
46a3df9f 2918 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 2919
2920 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 2921 }
2922
2923 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2924 if (ret) {
2925 dev_err(&hdev->pdev->dev,
2926 "Configure rss tc mode fail, status = %d\n", ret);
2927 return ret;
2928 }
2929
2930 return 0;
2931}
2932
2933static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2934{
d44f9b63 2935 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 2936 struct hclge_desc desc;
2937 int ret;
2938
2939 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2940
d44f9b63 2941 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
46a3df9f
S		 2942 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2943 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2944 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2945 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2946 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2947 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2948 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2949 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2950 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2951 if (ret) {
2952 dev_err(&hdev->pdev->dev,
2953 "Configure rss input fail, status = %d\n", ret);
2954 return ret;
2955 }
2956
2957 return 0;
2958}
2959
2960static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2961 u8 *key, u8 *hfunc)
2962{
2963 struct hclge_vport *vport = hclge_get_vport(handle);
2964 struct hclge_dev *hdev = vport->back;
2965 int i;
2966
2967 /* Get hash algorithm */
2968 if (hfunc)
2969 *hfunc = hclge_get_rss_algo(hdev);
2970
2971 /* Get the RSS Key required by the user */
2972 if (key)
2973 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2974
2975 /* Get indirect table */
2976 if (indir)
2977 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2978 indir[i] = vport->rss_indirection_tbl[i];
2979
2980 return 0;
2981}
2982
2983static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2984 const u8 *key, const u8 hfunc)
2985{
2986 struct hclge_vport *vport = hclge_get_vport(handle);
2987 struct hclge_dev *hdev = vport->back;
2988 u8 hash_algo;
2989 int ret, i;
2990
2991 /* Set the RSS Hash Key if specififed by the user */
2992 if (key) {
2993 /* Update the shadow RSS key with user specified qids */
2994 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2995
2996 if (hfunc == ETH_RSS_HASH_TOP ||
2997 hfunc == ETH_RSS_HASH_NO_CHANGE)
2998 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2999 else
3000 return -EINVAL;
3001 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3002 if (ret)
3003 return ret;
3004 }
3005
3006 /* Update the shadow RSS table with user specified qids */
3007 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3008 vport->rss_indirection_tbl[i] = indir[i];
3009
3010 /* Update the hardware */
3011 ret = hclge_set_rss_indir_table(hdev, indir);
3012 return ret;
3013}
3014
f7db940a
L		 3015static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3016{
3017 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3018
3019 if (nfc->data & RXH_L4_B_2_3)
3020 hash_sets |= HCLGE_D_PORT_BIT;
3021 else
3022 hash_sets &= ~HCLGE_D_PORT_BIT;
3023
3024 if (nfc->data & RXH_IP_SRC)
3025 hash_sets |= HCLGE_S_IP_BIT;
3026 else
3027 hash_sets &= ~HCLGE_S_IP_BIT;
3028
3029 if (nfc->data & RXH_IP_DST)
3030 hash_sets |= HCLGE_D_IP_BIT;
3031 else
3032 hash_sets &= ~HCLGE_D_IP_BIT;
3033
3034 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3035 hash_sets |= HCLGE_V_TAG_BIT;
3036
3037 return hash_sets;
3038}
3039
3040static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3041 struct ethtool_rxnfc *nfc)
3042{
3043 struct hclge_vport *vport = hclge_get_vport(handle);
3044 struct hclge_dev *hdev = vport->back;
3045 struct hclge_rss_input_tuple_cmd *req;
3046 struct hclge_desc desc;
3047 u8 tuple_sets;
3048 int ret;
3049
3050 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3051 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3052 return -EINVAL;
3053
3054 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3055 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3056 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3057 if (ret) {
3058 dev_err(&hdev->pdev->dev,
3059 "Read rss tuple fail, status = %d\n", ret);
3060 return ret;
3061 }
3062
3063 hclge_cmd_reuse_desc(&desc, false);
3064
3065 tuple_sets = hclge_get_rss_hash_bits(nfc);
3066 switch (nfc->flow_type) {
3067 case TCP_V4_FLOW:
3068 req->ipv4_tcp_en = tuple_sets;
3069 break;
3070 case TCP_V6_FLOW:
3071 req->ipv6_tcp_en = tuple_sets;
3072 break;
3073 case UDP_V4_FLOW:
3074 req->ipv4_udp_en = tuple_sets;
3075 break;
3076 case UDP_V6_FLOW:
3077 req->ipv6_udp_en = tuple_sets;
3078 break;
3079 case SCTP_V4_FLOW:
3080 req->ipv4_sctp_en = tuple_sets;
3081 break;
3082 case SCTP_V6_FLOW:
3083 if ((nfc->data & RXH_L4_B_0_1) ||
3084 (nfc->data & RXH_L4_B_2_3))
3085 return -EINVAL;
3086
3087 req->ipv6_sctp_en = tuple_sets;
3088 break;
3089 case IPV4_FLOW:
3090 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3091 break;
3092 case IPV6_FLOW:
3093 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3094 break;
3095 default:
3096 return -EINVAL;
3097 }
3098
3099 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3100 if (ret)
3101 dev_err(&hdev->pdev->dev,
3102 "Set rss tuple fail, status = %d\n", ret);
3103
3104 return ret;
3105}
3106
07d29954
L		 3107static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3108 struct ethtool_rxnfc *nfc)
3109{
3110 struct hclge_vport *vport = hclge_get_vport(handle);
3111 struct hclge_dev *hdev = vport->back;
3112 struct hclge_rss_input_tuple_cmd *req;
3113 struct hclge_desc desc;
3114 u8 tuple_sets;
3115 int ret;
3116
3117 nfc->data = 0;
3118
3119 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3120 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3121 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3122 if (ret) {
3123 dev_err(&hdev->pdev->dev,
3124 "Read rss tuple fail, status = %d\n", ret);
3125 return ret;
3126 }
3127
3128 switch (nfc->flow_type) {
3129 case TCP_V4_FLOW:
3130 tuple_sets = req->ipv4_tcp_en;
3131 break;
3132 case UDP_V4_FLOW:
3133 tuple_sets = req->ipv4_udp_en;
3134 break;
3135 case TCP_V6_FLOW:
3136 tuple_sets = req->ipv6_tcp_en;
3137 break;
3138 case UDP_V6_FLOW:
3139 tuple_sets = req->ipv6_udp_en;
3140 break;
3141 case SCTP_V4_FLOW:
3142 tuple_sets = req->ipv4_sctp_en;
3143 break;
3144 case SCTP_V6_FLOW:
3145 tuple_sets = req->ipv6_sctp_en;
3146 break;
3147 case IPV4_FLOW:
3148 case IPV6_FLOW:
3149 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3150 break;
3151 default:
3152 return -EINVAL;
3153 }
3154
3155 if (!tuple_sets)
3156 return 0;
3157
3158 if (tuple_sets & HCLGE_D_PORT_BIT)
3159 nfc->data |= RXH_L4_B_2_3;
3160 if (tuple_sets & HCLGE_S_PORT_BIT)
3161 nfc->data |= RXH_L4_B_0_1;
3162 if (tuple_sets & HCLGE_D_IP_BIT)
3163 nfc->data |= RXH_IP_DST;
3164 if (tuple_sets & HCLGE_S_IP_BIT)
3165 nfc->data |= RXH_IP_SRC;
3166
3167 return 0;
3168}
3169
46a3df9f
S		 3170static int hclge_get_tc_size(struct hnae3_handle *handle)
3171{
3172 struct hclge_vport *vport = hclge_get_vport(handle);
3173 struct hclge_dev *hdev = vport->back;
3174
3175 return hdev->rss_size_max;
3176}
3177
77f255c1 3178int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f
S		 3179{
3180 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3181 struct hclge_vport *vport = hdev->vport;
3182 u16 tc_offset[HCLGE_MAX_TC_NUM];
3183 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3184 u16 tc_valid[HCLGE_MAX_TC_NUM];
3185 u16 tc_size[HCLGE_MAX_TC_NUM];
3186 u32 *rss_indir = NULL;
68ece54e 3187 u16 rss_size = 0, roundup_size;
46a3df9f
S		 3188 const u8 *key;
3189 int i, ret, j;
3190
3191 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3192 if (!rss_indir)
3193 return -ENOMEM;
3194
3195 /* Get default RSS key */
3196 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3197
3198 /* Initialize RSS indirect table for each vport */
3199 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3200 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3201 vport[j].rss_indirection_tbl[i] =
68ece54e
YL		 3202 i % vport[j].alloc_rss_size;
3203
3204 /* vport 0 is for PF */
3205 if (j != 0)
3206 continue;
3207
3208 rss_size = vport[j].alloc_rss_size;
46a3df9f
S		 3209 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3210 }
3211 }
3212 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3213 if (ret)
3214 goto err;
3215
3216 key = rss_key;
3217 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3218 if (ret)
3219 goto err;
3220
3221 ret = hclge_set_rss_input_tuple(hdev);
3222 if (ret)
3223 goto err;
3224
68ece54e
YL		 3225 /* Each TC have the same queue size, and tc_size set to hardware is
3226 * the log2 of roundup power of two of rss_size, the acutal queue
3227 * size is limited by indirection table.
3228 */
3229 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3230 dev_err(&hdev->pdev->dev,
3231 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3232 rss_size);
81359617
CJ		 3233 ret = -EINVAL;
3234 goto err;
68ece54e
YL		 3235 }
3236
3237 roundup_size = roundup_pow_of_two(rss_size);
3238 roundup_size = ilog2(roundup_size);
3239
46a3df9f 3240 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3241 tc_valid[i] = 0;
46a3df9f 3242
68ece54e
YL		 3243 if (!(hdev->hw_tc_map & BIT(i)))
3244 continue;
3245
3246 tc_valid[i] = 1;
3247 tc_size[i] = roundup_size;
3248 tc_offset[i] = rss_size * i;
46a3df9f 3249 }
68ece54e 3250
46a3df9f
S		 3251 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3252
3253err:
3254 kfree(rss_indir);
3255
3256 return ret;
3257}
3258
3259int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
3260 struct hnae3_ring_chain_node *ring_chain)
3261{
3262 struct hclge_dev *hdev = vport->back;
d44f9b63 3263 struct hclge_ctrl_vector_chain_cmd *req;
46a3df9f
S		 3264 struct hnae3_ring_chain_node *node;
3265 struct hclge_desc desc;
3266 int ret;
3267 int i;
3268
3269 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
3270
d44f9b63 3271 req = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
46a3df9f
S		 3272 req->int_vector_id = vector_id;
3273
3274 i = 0;
3275 for (node = ring_chain; node; node = node->next) {
a90bb9a5
YL		 3276 u16 type_and_id = 0;
3277
3278 hnae_set_field(type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
46a3df9f 3279 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5
YL		 3280 hnae_set_field(type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
3281 node->tqp_index);
3282 hnae_set_field(type_and_id, HCLGE_INT_GL_IDX_M,
0305b443
L		 3283 HCLGE_INT_GL_IDX_S,
3284 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5 3285 req->tqp_type_and_id[i] = cpu_to_le16(type_and_id);
0305b443 3286 req->vfid = vport->vport_id;
46a3df9f
S		 3287
3288 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3289 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3290
3291 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3292 if (ret) {
3293 dev_err(&hdev->pdev->dev,
3294 "Map TQP fail, status is %d.\n",
3295 ret);
3296 return ret;
3297 }
3298 i = 0;
3299
3300 hclge_cmd_setup_basic_desc(&desc,
3301 HCLGE_OPC_ADD_RING_TO_VECTOR,
3302 false);
3303 req->int_vector_id = vector_id;
3304 }
3305 }
3306
3307 if (i > 0) {
3308 req->int_cause_num = i;
3309
3310 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3311 if (ret) {
3312 dev_err(&hdev->pdev->dev,
3313 "Map TQP fail, status is %d.\n", ret);
3314 return ret;
3315 }
3316 }
3317
3318 return 0;
3319}
3320
1db9b1bf
YL		 3321static int hclge_map_handle_ring_to_vector(
3322 struct hnae3_handle *handle, int vector,
3323 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3324{
3325 struct hclge_vport *vport = hclge_get_vport(handle);
3326 struct hclge_dev *hdev = vport->back;
3327 int vector_id;
3328
3329 vector_id = hclge_get_vector_index(hdev, vector);
3330 if (vector_id < 0) {
3331 dev_err(&hdev->pdev->dev,
3332 "Get vector index fail. ret =%d\n", vector_id);
3333 return vector_id;
3334 }
3335
3336 return hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);
3337}
3338
3339static int hclge_unmap_ring_from_vector(
3340 struct hnae3_handle *handle, int vector,
3341 struct hnae3_ring_chain_node *ring_chain)
3342{
3343 struct hclge_vport *vport = hclge_get_vport(handle);
3344 struct hclge_dev *hdev = vport->back;
d44f9b63 3345 struct hclge_ctrl_vector_chain_cmd *req;
46a3df9f
S		 3346 struct hnae3_ring_chain_node *node;
3347 struct hclge_desc desc;
3348 int i, vector_id;
3349 int ret;
3350
3351 vector_id = hclge_get_vector_index(hdev, vector);
3352 if (vector_id < 0) {
3353 dev_err(&handle->pdev->dev,
3354 "Get vector index fail. ret =%d\n", vector_id);
3355 return vector_id;
3356 }
3357
3358 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);
3359
d44f9b63 3360 req = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
46a3df9f
S		 3361 req->int_vector_id = vector_id;
3362
3363 i = 0;
3364 for (node = ring_chain; node; node = node->next) {
a90bb9a5
YL		 3365 u16 type_and_id = 0;
3366
3367 hnae_set_field(type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
46a3df9f 3368 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5
YL		 3369 hnae_set_field(type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
3370 node->tqp_index);
3371 hnae_set_field(type_and_id, HCLGE_INT_GL_IDX_M,
0305b443
L		 3372 HCLGE_INT_GL_IDX_S,
3373 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f 3374
a90bb9a5 3375 req->tqp_type_and_id[i] = cpu_to_le16(type_and_id);
0305b443 3376 req->vfid = vport->vport_id;
46a3df9f
S		 3377
3378 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3379 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3380
3381 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3382 if (ret) {
3383 dev_err(&hdev->pdev->dev,
3384 "Unmap TQP fail, status is %d.\n",
3385 ret);
3386 return ret;
3387 }
3388 i = 0;
3389 hclge_cmd_setup_basic_desc(&desc,
c5b1b975 3390 HCLGE_OPC_DEL_RING_TO_VECTOR,
46a3df9f
S		 3391 false);
3392 req->int_vector_id = vector_id;
3393 }
3394 }
3395
3396 if (i > 0) {
3397 req->int_cause_num = i;
3398
3399 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3400 if (ret) {
3401 dev_err(&hdev->pdev->dev,
3402 "Unmap TQP fail, status is %d.\n", ret);
3403 return ret;
3404 }
3405 }
3406
3407 return 0;
3408}
3409
3410int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3411 struct hclge_promisc_param *param)
3412{
d44f9b63 3413 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3414 struct hclge_desc desc;
3415 int ret;
3416
3417 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3418
d44f9b63 3419 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f
S		 3420 req->vf_id = param->vf_id;
3421 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3422
3423 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3424 if (ret) {
3425 dev_err(&hdev->pdev->dev,
3426 "Set promisc mode fail, status is %d.\n", ret);
3427 return ret;
3428 }
3429 return 0;
3430}
3431
3432void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3433 bool en_mc, bool en_bc, int vport_id)
3434{
3435 if (!param)
3436 return;
3437
3438 memset(param, 0, sizeof(struct hclge_promisc_param));
3439 if (en_uc)
3440 param->enable = HCLGE_PROMISC_EN_UC;
3441 if (en_mc)
3442 param->enable |= HCLGE_PROMISC_EN_MC;
3443 if (en_bc)
3444 param->enable |= HCLGE_PROMISC_EN_BC;
3445 param->vf_id = vport_id;
3446}
3447
3448static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3449{
3450 struct hclge_vport *vport = hclge_get_vport(handle);
3451 struct hclge_dev *hdev = vport->back;
3452 struct hclge_promisc_param param;
3453
3454 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3455 hclge_cmd_set_promisc_mode(hdev, &param);
3456}
3457
3458static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3459{
3460 struct hclge_desc desc;
d44f9b63
YL		 3461 struct hclge_config_mac_mode_cmd *req =
3462 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3463 u32 loop_en = 0;
46a3df9f
S		 3464 int ret;
3465
3466 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
a90bb9a5
YL		 3467 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3468 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3469 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3470 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3471 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3472 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3473 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3474 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3475 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3476 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3477 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3478 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3479 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3480 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3481 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3482
3483 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3484 if (ret)
3485 dev_err(&hdev->pdev->dev,
3486 "mac enable fail, ret =%d.\n", ret);
3487}
3488
c39c4d98
YL		 3489static int hclge_set_loopback(struct hnae3_handle *handle,
3490 enum hnae3_loop loop_mode, bool en)
3491{
3492 struct hclge_vport *vport = hclge_get_vport(handle);
3493 struct hclge_config_mac_mode_cmd *req;
3494 struct hclge_dev *hdev = vport->back;
3495 struct hclge_desc desc;
3496 u32 loop_en;
3497 int ret;
3498
3499 switch (loop_mode) {
3500 case HNAE3_MAC_INTER_LOOP_MAC:
3501 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3502 /* 1 Read out the MAC mode config at first */
3503 hclge_cmd_setup_basic_desc(&desc,
3504 HCLGE_OPC_CONFIG_MAC_MODE,
3505 true);
3506 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3507 if (ret) {
3508 dev_err(&hdev->pdev->dev,
3509 "mac loopback get fail, ret =%d.\n",
3510 ret);
3511 return ret;
3512 }
3513
3514 /* 2 Then setup the loopback flag */
3515 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3516 if (en)
3517 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3518 else
3519 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3520
3521 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3522
3523 /* 3 Config mac work mode with loopback flag
3524 * and its original configure parameters
3525 */
3526 hclge_cmd_reuse_desc(&desc, false);
3527 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3528 if (ret)
3529 dev_err(&hdev->pdev->dev,
3530 "mac loopback set fail, ret =%d.\n", ret);
3531 break;
3532 default:
3533 ret = -ENOTSUPP;
3534 dev_err(&hdev->pdev->dev,
3535 "loop_mode %d is not supported\n", loop_mode);
3536 break;
3537 }
3538
3539 return ret;
3540}
3541
46a3df9f
S		 3542static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3543 int stream_id, bool enable)
3544{
3545 struct hclge_desc desc;
d44f9b63
YL		 3546 struct hclge_cfg_com_tqp_queue_cmd *req =
3547 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3548 int ret;
3549
3550 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3551 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3552 req->stream_id = cpu_to_le16(stream_id);
3553 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3554
3555 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3556 if (ret)
3557 dev_err(&hdev->pdev->dev,
3558 "Tqp enable fail, status =%d.\n", ret);
3559 return ret;
3560}
3561
3562static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3563{
3564 struct hclge_vport *vport = hclge_get_vport(handle);
3565 struct hnae3_queue *queue;
3566 struct hclge_tqp *tqp;
3567 int i;
3568
3569 for (i = 0; i < vport->alloc_tqps; i++) {
3570 queue = handle->kinfo.tqp[i];
3571 tqp = container_of(queue, struct hclge_tqp, q);
3572 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3573 }
3574}
3575
3576static int hclge_ae_start(struct hnae3_handle *handle)
3577{
3578 struct hclge_vport *vport = hclge_get_vport(handle);
3579 struct hclge_dev *hdev = vport->back;
3580 int i, queue_id, ret;
3581
3582 for (i = 0; i < vport->alloc_tqps; i++) {
3583 /* todo clear interrupt */
3584 /* ring enable */
3585 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3586 if (queue_id < 0) {
3587 dev_warn(&hdev->pdev->dev,
3588 "Get invalid queue id, ignore it\n");
3589 continue;
3590 }
3591
3592 hclge_tqp_enable(hdev, queue_id, 0, true);
3593 }
3594 /* mac enable */
3595 hclge_cfg_mac_mode(hdev, true);
3596 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3597 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 3598
3599 ret = hclge_mac_start_phy(hdev);
3600 if (ret)
3601 return ret;
3602
3603 /* reset tqp stats */
3604 hclge_reset_tqp_stats(handle);
3605
3606 return 0;
3607}
3608
3609static void hclge_ae_stop(struct hnae3_handle *handle)
3610{
3611 struct hclge_vport *vport = hclge_get_vport(handle);
3612 struct hclge_dev *hdev = vport->back;
3613 int i, queue_id;
3614
3615 for (i = 0; i < vport->alloc_tqps; i++) {
3616 /* Ring disable */
3617 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3618 if (queue_id < 0) {
3619 dev_warn(&hdev->pdev->dev,
3620 "Get invalid queue id, ignore it\n");
3621 continue;
3622 }
3623
3624 hclge_tqp_enable(hdev, queue_id, 0, false);
3625 }
3626 /* Mac disable */
3627 hclge_cfg_mac_mode(hdev, false);
3628
3629 hclge_mac_stop_phy(hdev);
3630
3631 /* reset tqp stats */
3632 hclge_reset_tqp_stats(handle);
3633}
3634
3635static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3636 u16 cmdq_resp, u8 resp_code,
3637 enum hclge_mac_vlan_tbl_opcode op)
3638{
3639 struct hclge_dev *hdev = vport->back;
3640 int return_status = -EIO;
3641
3642 if (cmdq_resp) {
3643 dev_err(&hdev->pdev->dev,
3644 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3645 cmdq_resp);
3646 return -EIO;
3647 }
3648
3649 if (op == HCLGE_MAC_VLAN_ADD) {
3650 if ((!resp_code) || (resp_code == 1)) {
3651 return_status = 0;
3652 } else if (resp_code == 2) {
3653 return_status = -EIO;
3654 dev_err(&hdev->pdev->dev,
3655 "add mac addr failed for uc_overflow.\n");
3656 } else if (resp_code == 3) {
3657 return_status = -EIO;
3658 dev_err(&hdev->pdev->dev,
3659 "add mac addr failed for mc_overflow.\n");
3660 } else {
3661 dev_err(&hdev->pdev->dev,
3662 "add mac addr failed for undefined, code=%d.\n",
3663 resp_code);
3664 }
3665 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3666 if (!resp_code) {
3667 return_status = 0;
3668 } else if (resp_code == 1) {
3669 return_status = -EIO;
3670 dev_dbg(&hdev->pdev->dev,
3671 "remove mac addr failed for miss.\n");
3672 } else {
3673 dev_err(&hdev->pdev->dev,
3674 "remove mac addr failed for undefined, code=%d.\n",
3675 resp_code);
3676 }
3677 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3678 if (!resp_code) {
3679 return_status = 0;
3680 } else if (resp_code == 1) {
3681 return_status = -EIO;
3682 dev_dbg(&hdev->pdev->dev,
3683 "lookup mac addr failed for miss.\n");
3684 } else {
3685 dev_err(&hdev->pdev->dev,
3686 "lookup mac addr failed for undefined, code=%d.\n",
3687 resp_code);
3688 }
3689 } else {
3690 return_status = -EIO;
3691 dev_err(&hdev->pdev->dev,
3692 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3693 op);
3694 }
3695
3696 return return_status;
3697}
3698
3699static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3700{
3701 int word_num;
3702 int bit_num;
3703
3704 if (vfid > 255 || vfid < 0)
3705 return -EIO;
3706
3707 if (vfid >= 0 && vfid <= 191) {
3708 word_num = vfid / 32;
3709 bit_num = vfid % 32;
3710 if (clr)
a90bb9a5 3711 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3712 else
a90bb9a5 3713 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3714 } else {
3715 word_num = (vfid - 192) / 32;
3716 bit_num = vfid % 32;
3717 if (clr)
a90bb9a5 3718 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3719 else
a90bb9a5 3720 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3721 }
3722
3723 return 0;
3724}
3725
3726static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3727{
3728#define HCLGE_DESC_NUMBER 3
3729#define HCLGE_FUNC_NUMBER_PER_DESC 6
3730 int i, j;
3731
3732 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3733 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3734 if (desc[i].data[j])
3735 return false;
3736
3737 return true;
3738}
3739
d44f9b63 3740static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3741 const u8 *addr)
3742{
3743 const unsigned char *mac_addr = addr;
3744 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3745 (mac_addr[0]) | (mac_addr[1] << 8);
3746 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3747
3748 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3749 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3750}
3751
1db9b1bf
YL		 3752static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3753 const u8 *addr)
46a3df9f
S		 3754{
3755 u16 high_val = addr[1] | (addr[0] << 8);
3756 struct hclge_dev *hdev = vport->back;
3757 u32 rsh = 4 - hdev->mta_mac_sel_type;
3758 u16 ret_val = (high_val >> rsh) & 0xfff;
3759
3760 return ret_val;
3761}
3762
3763static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3764 enum hclge_mta_dmac_sel_type mta_mac_sel,
3765 bool enable)
3766{
d44f9b63 3767 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3768 struct hclge_desc desc;
3769 int ret;
3770
d44f9b63 3771 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3772 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3773
3774 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3775 enable);
3776 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3777 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3778
3779 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3780 if (ret) {
3781 dev_err(&hdev->pdev->dev,
3782 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3783 ret);
3784 return ret;
3785 }
3786
3787 return 0;
3788}
3789
3790int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3791 u8 func_id,
3792 bool enable)
3793{
d44f9b63 3794 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3795 struct hclge_desc desc;
3796 int ret;
3797
d44f9b63 3798 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3799 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3800
3801 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3802 enable);
3803 req->function_id = func_id;
3804
3805 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3806 if (ret) {
3807 dev_err(&hdev->pdev->dev,
3808 "Config func_id enable failed for cmd_send, ret =%d.\n",
3809 ret);
3810 return ret;
3811 }
3812
3813 return 0;
3814}
3815
3816static int hclge_set_mta_table_item(struct hclge_vport *vport,
3817 u16 idx,
3818 bool enable)
3819{
3820 struct hclge_dev *hdev = vport->back;
d44f9b63 3821 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3822 struct hclge_desc desc;
a90bb9a5 3823 u16 item_idx = 0;
46a3df9f
S		 3824 int ret;
3825
d44f9b63 3826 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f
S		 3827 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3828 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3829
a90bb9a5 3830 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
46a3df9f 3831 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3832 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3833
3834 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3835 if (ret) {
3836 dev_err(&hdev->pdev->dev,
3837 "Config mta table item failed for cmd_send, ret =%d.\n",
3838 ret);
3839 return ret;
3840 }
3841
3842 return 0;
3843}
3844
3845static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3846 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3847{
3848 struct hclge_dev *hdev = vport->back;
3849 struct hclge_desc desc;
3850 u8 resp_code;
a90bb9a5 3851 u16 retval;
46a3df9f
S		 3852 int ret;
3853
3854 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3855
d44f9b63 3856 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3857
3858 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3859 if (ret) {
3860 dev_err(&hdev->pdev->dev,
3861 "del mac addr failed for cmd_send, ret =%d.\n",
3862 ret);
3863 return ret;
3864 }
a90bb9a5
YL		 3865 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3866 retval = le16_to_cpu(desc.retval);
46a3df9f 3867
a90bb9a5 3868 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3869 HCLGE_MAC_VLAN_REMOVE);
3870}
3871
3872static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3873 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3874 struct hclge_desc *desc,
3875 bool is_mc)
3876{
3877 struct hclge_dev *hdev = vport->back;
3878 u8 resp_code;
a90bb9a5 3879 u16 retval;
46a3df9f
S		 3880 int ret;
3881
3882 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3883 if (is_mc) {
3884 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3885 memcpy(desc[0].data,
3886 req,
d44f9b63 3887 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3888 hclge_cmd_setup_basic_desc(&desc[1],
3889 HCLGE_OPC_MAC_VLAN_ADD,
3890 true);
3891 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3892 hclge_cmd_setup_basic_desc(&desc[2],
3893 HCLGE_OPC_MAC_VLAN_ADD,
3894 true);
3895 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3896 } else {
3897 memcpy(desc[0].data,
3898 req,
d44f9b63 3899 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3900 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3901 }
3902 if (ret) {
3903 dev_err(&hdev->pdev->dev,
3904 "lookup mac addr failed for cmd_send, ret =%d.\n",
3905 ret);
3906 return ret;
3907 }
a90bb9a5
YL		 3908 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3909 retval = le16_to_cpu(desc[0].retval);
46a3df9f 3910
a90bb9a5 3911 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3912 HCLGE_MAC_VLAN_LKUP);
3913}
3914
3915static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3916 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3917 struct hclge_desc *mc_desc)
3918{
3919 struct hclge_dev *hdev = vport->back;
3920 int cfg_status;
3921 u8 resp_code;
a90bb9a5 3922 u16 retval;
46a3df9f
S		 3923 int ret;
3924
3925 if (!mc_desc) {
3926 struct hclge_desc desc;
3927
3928 hclge_cmd_setup_basic_desc(&desc,
3929 HCLGE_OPC_MAC_VLAN_ADD,
3930 false);
d44f9b63
YL		 3931 memcpy(desc.data, req,
3932 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3933 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 3934 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3935 retval = le16_to_cpu(desc.retval);
3936
3937 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3938 resp_code,
3939 HCLGE_MAC_VLAN_ADD);
3940 } else {
c3b6f755 3941 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 3942 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3943 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 3944 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3945 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 3946 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3947 memcpy(mc_desc[0].data, req,
d44f9b63 3948 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3949 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 3950 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3951 retval = le16_to_cpu(mc_desc[0].retval);
3952
3953 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3954 resp_code,
3955 HCLGE_MAC_VLAN_ADD);
3956 }
3957
3958 if (ret) {
3959 dev_err(&hdev->pdev->dev,
3960 "add mac addr failed for cmd_send, ret =%d.\n",
3961 ret);
3962 return ret;
3963 }
3964
3965 return cfg_status;
3966}
3967
3968static int hclge_add_uc_addr(struct hnae3_handle *handle,
3969 const unsigned char *addr)
3970{
3971 struct hclge_vport *vport = hclge_get_vport(handle);
3972
3973 return hclge_add_uc_addr_common(vport, addr);
3974}
3975
3976int hclge_add_uc_addr_common(struct hclge_vport *vport,
3977 const unsigned char *addr)
3978{
3979 struct hclge_dev *hdev = vport->back;
d44f9b63 3980 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 3981 enum hclge_cmd_status status;
a90bb9a5 3982 u16 egress_port = 0;
46a3df9f
S		 3983
3984 /* mac addr check */
3985 if (is_zero_ether_addr(addr) ||
3986 is_broadcast_ether_addr(addr) ||
3987 is_multicast_ether_addr(addr)) {
3988 dev_err(&hdev->pdev->dev,
3989 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3990 addr,
3991 is_zero_ether_addr(addr),
3992 is_broadcast_ether_addr(addr),
3993 is_multicast_ether_addr(addr));
3994 return -EINVAL;
3995 }
3996
3997 memset(&req, 0, sizeof(req));
3998 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3999 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4000 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4001 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
a90bb9a5
YL		 4002
4003 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4004 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4005 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
46a3df9f 4006 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5 4007 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
46a3df9f 4008 HCLGE_MAC_EPORT_PFID_S, 0);
a90bb9a5
YL		 4009
4010 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4011
4012 hclge_prepare_mac_addr(&req, addr);
4013
4014 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
4015
4016 return status;
4017}
4018
4019static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4020 const unsigned char *addr)
4021{
4022 struct hclge_vport *vport = hclge_get_vport(handle);
4023
4024 return hclge_rm_uc_addr_common(vport, addr);
4025}
4026
4027int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4028 const unsigned char *addr)
4029{
4030 struct hclge_dev *hdev = vport->back;
d44f9b63 4031 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4032 enum hclge_cmd_status status;
4033
4034 /* mac addr check */
4035 if (is_zero_ether_addr(addr) ||
4036 is_broadcast_ether_addr(addr) ||
4037 is_multicast_ether_addr(addr)) {
4038 dev_dbg(&hdev->pdev->dev,
4039 "Remove mac err! invalid mac:%pM.\n",
4040 addr);
4041 return -EINVAL;
4042 }
4043
4044 memset(&req, 0, sizeof(req));
4045 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4046 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4047 hclge_prepare_mac_addr(&req, addr);
4048 status = hclge_remove_mac_vlan_tbl(vport, &req);
4049
4050 return status;
4051}
4052
4053static int hclge_add_mc_addr(struct hnae3_handle *handle,
4054 const unsigned char *addr)
4055{
4056 struct hclge_vport *vport = hclge_get_vport(handle);
4057
4058 return hclge_add_mc_addr_common(vport, addr);
4059}
4060
4061int hclge_add_mc_addr_common(struct hclge_vport *vport,
4062 const unsigned char *addr)
4063{
4064 struct hclge_dev *hdev = vport->back;
d44f9b63 4065 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4066 struct hclge_desc desc[3];
4067 u16 tbl_idx;
4068 int status;
4069
4070 /* mac addr check */
4071 if (!is_multicast_ether_addr(addr)) {
4072 dev_err(&hdev->pdev->dev,
4073 "Add mc mac err! invalid mac:%pM.\n",
4074 addr);
4075 return -EINVAL;
4076 }
4077 memset(&req, 0, sizeof(req));
4078 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4079 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4080 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4081 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4082 hclge_prepare_mac_addr(&req, addr);
4083 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4084 if (!status) {
4085 /* This mac addr exist, update VFID for it */
4086 hclge_update_desc_vfid(desc, vport->vport_id, false);
4087 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4088 } else {
4089 /* This mac addr do not exist, add new entry for it */
4090 memset(desc[0].data, 0, sizeof(desc[0].data));
4091 memset(desc[1].data, 0, sizeof(desc[0].data));
4092 memset(desc[2].data, 0, sizeof(desc[0].data));
4093 hclge_update_desc_vfid(desc, vport->vport_id, false);
4094 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4095 }
4096
4097 /* Set MTA table for this MAC address */
4098 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4099 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4100
4101 return status;
4102}
4103
4104static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4105 const unsigned char *addr)
4106{
4107 struct hclge_vport *vport = hclge_get_vport(handle);
4108
4109 return hclge_rm_mc_addr_common(vport, addr);
4110}
4111
4112int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4113 const unsigned char *addr)
4114{
4115 struct hclge_dev *hdev = vport->back;
d44f9b63 4116 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4117 enum hclge_cmd_status status;
4118 struct hclge_desc desc[3];
4119 u16 tbl_idx;
4120
4121 /* mac addr check */
4122 if (!is_multicast_ether_addr(addr)) {
4123 dev_dbg(&hdev->pdev->dev,
4124 "Remove mc mac err! invalid mac:%pM.\n",
4125 addr);
4126 return -EINVAL;
4127 }
4128
4129 memset(&req, 0, sizeof(req));
4130 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4131 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4132 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4133 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4134 hclge_prepare_mac_addr(&req, addr);
4135 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4136 if (!status) {
4137 /* This mac addr exist, remove this handle's VFID for it */
4138 hclge_update_desc_vfid(desc, vport->vport_id, true);
4139
4140 if (hclge_is_all_function_id_zero(desc))
4141 /* All the vfid is zero, so need to delete this entry */
4142 status = hclge_remove_mac_vlan_tbl(vport, &req);
4143 else
4144 /* Not all the vfid is zero, update the vfid */
4145 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4146
4147 } else {
4148 /* This mac addr do not exist, can't delete it */
4149 dev_err(&hdev->pdev->dev,
d7629e74 4150 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 4151 status);
4152 return -EIO;
4153 }
4154
4155 /* Set MTB table for this MAC address */
4156 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4157 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4158
4159 return status;
4160}
4161
4162static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4163{
4164 struct hclge_vport *vport = hclge_get_vport(handle);
4165 struct hclge_dev *hdev = vport->back;
4166
4167 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4168}
4169
4170static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4171{
4172 const unsigned char *new_addr = (const unsigned char *)p;
4173 struct hclge_vport *vport = hclge_get_vport(handle);
4174 struct hclge_dev *hdev = vport->back;
4175
4176 /* mac addr check */
4177 if (is_zero_ether_addr(new_addr) ||
4178 is_broadcast_ether_addr(new_addr) ||
4179 is_multicast_ether_addr(new_addr)) {
4180 dev_err(&hdev->pdev->dev,
4181 "Change uc mac err! invalid mac:%p.\n",
4182 new_addr);
4183 return -EINVAL;
4184 }
4185
4186 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4187
4188 if (!hclge_add_uc_addr(handle, new_addr)) {
4189 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4190 return 0;
4191 }
4192
4193 return -EIO;
4194}
4195
4196static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4197 bool filter_en)
4198{
d44f9b63 4199 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4200 struct hclge_desc desc;
4201 int ret;
4202
4203 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4204
d44f9b63 4205 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4206 req->vlan_type = vlan_type;
4207 req->vlan_fe = filter_en;
4208
4209 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4210 if (ret) {
4211 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4212 ret);
4213 return ret;
4214 }
4215
4216 return 0;
4217}
4218
4219int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4220 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4221{
4222#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4223 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4224 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4225 struct hclge_desc desc[2];
4226 u8 vf_byte_val;
4227 u8 vf_byte_off;
4228 int ret;
4229
4230 hclge_cmd_setup_basic_desc(&desc[0],
4231 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4232 hclge_cmd_setup_basic_desc(&desc[1],
4233 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4234
4235 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4236
4237 vf_byte_off = vfid / 8;
4238 vf_byte_val = 1 << (vfid % 8);
4239
d44f9b63
YL		 4240 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4241 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4242
a90bb9a5 4243 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4244 req0->vlan_cfg = is_kill;
4245
4246 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4247 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4248 else
4249 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4250
4251 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4252 if (ret) {
4253 dev_err(&hdev->pdev->dev,
4254 "Send vf vlan command fail, ret =%d.\n",
4255 ret);
4256 return ret;
4257 }
4258
4259 if (!is_kill) {
4260 if (!req0->resp_code || req0->resp_code == 1)
4261 return 0;
4262
4263 dev_err(&hdev->pdev->dev,
4264 "Add vf vlan filter fail, ret =%d.\n",
4265 req0->resp_code);
4266 } else {
4267 if (!req0->resp_code)
4268 return 0;
4269
4270 dev_err(&hdev->pdev->dev,
4271 "Kill vf vlan filter fail, ret =%d.\n",
4272 req0->resp_code);
4273 }
4274
4275 return -EIO;
4276}
4277
4278static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4279 __be16 proto, u16 vlan_id,
4280 bool is_kill)
4281{
4282 struct hclge_vport *vport = hclge_get_vport(handle);
4283 struct hclge_dev *hdev = vport->back;
d44f9b63 4284 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4285 struct hclge_desc desc;
4286 u8 vlan_offset_byte_val;
4287 u8 vlan_offset_byte;
4288 u8 vlan_offset_160;
4289 int ret;
4290
4291 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4292
4293 vlan_offset_160 = vlan_id / 160;
4294 vlan_offset_byte = (vlan_id % 160) / 8;
4295 vlan_offset_byte_val = 1 << (vlan_id % 8);
4296
d44f9b63 4297 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4298 req->vlan_offset = vlan_offset_160;
4299 req->vlan_cfg = is_kill;
4300 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4301
4302 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4303 if (ret) {
4304 dev_err(&hdev->pdev->dev,
4305 "port vlan command, send fail, ret =%d.\n",
4306 ret);
4307 return ret;
4308 }
4309
4310 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4311 if (ret) {
4312 dev_err(&hdev->pdev->dev,
4313 "Set pf vlan filter config fail, ret =%d.\n",
4314 ret);
4315 return -EIO;
4316 }
4317
4318 return 0;
4319}
4320
4321static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4322 u16 vlan, u8 qos, __be16 proto)
4323{
4324 struct hclge_vport *vport = hclge_get_vport(handle);
4325 struct hclge_dev *hdev = vport->back;
4326
4327 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4328 return -EINVAL;
4329 if (proto != htons(ETH_P_8021Q))
4330 return -EPROTONOSUPPORT;
4331
4332 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4333}
4334
4335static int hclge_init_vlan_config(struct hclge_dev *hdev)
4336{
4337#define HCLGE_VLAN_TYPE_VF_TABLE 0
4338#define HCLGE_VLAN_TYPE_PORT_TABLE 1
5e43aef8 4339 struct hnae3_handle *handle;
46a3df9f
S		 4340 int ret;
4341
4342 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
4343 true);
4344 if (ret)
4345 return ret;
4346
4347 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
4348 true);
5e43aef8
L		 4349 if (ret)
4350 return ret;
46a3df9f 4351
5e43aef8
L		 4352 handle = &hdev->vport[0].nic;
4353 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4354}
4355
4356static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4357{
4358 struct hclge_vport *vport = hclge_get_vport(handle);
d44f9b63 4359 struct hclge_config_max_frm_size_cmd *req;
46a3df9f
S		 4360 struct hclge_dev *hdev = vport->back;
4361 struct hclge_desc desc;
4362 int ret;
4363
4364 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
4365 return -EINVAL;
4366
4367 hdev->mps = new_mtu;
4368 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4369
d44f9b63 4370 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
46a3df9f
S		 4371 req->max_frm_size = cpu_to_le16(new_mtu);
4372
4373 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4374 if (ret) {
4375 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4376 return ret;
4377 }
4378
4379 return 0;
4380}
4381
4382static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4383 bool enable)
4384{
d44f9b63 4385 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4386 struct hclge_desc desc;
4387 int ret;
4388
4389 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4390
d44f9b63 4391 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4392 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4393 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4394
4395 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4396 if (ret) {
4397 dev_err(&hdev->pdev->dev,
4398 "Send tqp reset cmd error, status =%d\n", ret);
4399 return ret;
4400 }
4401
4402 return 0;
4403}
4404
4405static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4406{
d44f9b63 4407 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4408 struct hclge_desc desc;
4409 int ret;
4410
4411 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4412
d44f9b63 4413 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4414 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4415
4416 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4417 if (ret) {
4418 dev_err(&hdev->pdev->dev,
4419 "Get reset status error, status =%d\n", ret);
4420 return ret;
4421 }
4422
4423 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4424}
4425
4426static void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4427{
4428 struct hclge_vport *vport = hclge_get_vport(handle);
4429 struct hclge_dev *hdev = vport->back;
4430 int reset_try_times = 0;
4431 int reset_status;
4432 int ret;
4433
4434 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4435 if (ret) {
4436 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4437 return;
4438 }
4439
4440 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4441 if (ret) {
4442 dev_warn(&hdev->pdev->dev,
4443 "Send reset tqp cmd fail, ret = %d\n", ret);
4444 return;
4445 }
4446
4447 reset_try_times = 0;
4448 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4449 /* Wait for tqp hw reset */
4450 msleep(20);
4451 reset_status = hclge_get_reset_status(hdev, queue_id);
4452 if (reset_status)
4453 break;
4454 }
4455
4456 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4457 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4458 return;
4459 }
4460
4461 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4462 if (ret) {
4463 dev_warn(&hdev->pdev->dev,
4464 "Deassert the soft reset fail, ret = %d\n", ret);
4465 return;
4466 }
4467}
4468
4469static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4470{
4471 struct hclge_vport *vport = hclge_get_vport(handle);
4472 struct hclge_dev *hdev = vport->back;
4473
4474 return hdev->fw_version;
4475}
4476
4477static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4478 u32 *rx_en, u32 *tx_en)
4479{
4480 struct hclge_vport *vport = hclge_get_vport(handle);
4481 struct hclge_dev *hdev = vport->back;
4482
4483 *auto_neg = hclge_get_autoneg(handle);
4484
4485 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4486 *rx_en = 0;
4487 *tx_en = 0;
4488 return;
4489 }
4490
4491 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4492 *rx_en = 1;
4493 *tx_en = 0;
4494 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4495 *tx_en = 1;
4496 *rx_en = 0;
4497 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4498 *rx_en = 1;
4499 *tx_en = 1;
4500 } else {
4501 *rx_en = 0;
4502 *tx_en = 0;
4503 }
4504}
4505
4506static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
4507 u8 *auto_neg, u32 *speed, u8 *duplex)
4508{
4509 struct hclge_vport *vport = hclge_get_vport(handle);
4510 struct hclge_dev *hdev = vport->back;
4511
4512 if (speed)
4513 *speed = hdev->hw.mac.speed;
4514 if (duplex)
4515 *duplex = hdev->hw.mac.duplex;
4516 if (auto_neg)
4517 *auto_neg = hdev->hw.mac.autoneg;
4518}
4519
4520static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
4521{
4522 struct hclge_vport *vport = hclge_get_vport(handle);
4523 struct hclge_dev *hdev = vport->back;
4524
4525 if (media_type)
4526 *media_type = hdev->hw.mac.media_type;
4527}
4528
4529static void hclge_get_mdix_mode(struct hnae3_handle *handle,
4530 u8 *tp_mdix_ctrl, u8 *tp_mdix)
4531{
4532 struct hclge_vport *vport = hclge_get_vport(handle);
4533 struct hclge_dev *hdev = vport->back;
4534 struct phy_device *phydev = hdev->hw.mac.phydev;
4535 int mdix_ctrl, mdix, retval, is_resolved;
4536
4537 if (!phydev) {
4538 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4539 *tp_mdix = ETH_TP_MDI_INVALID;
4540 return;
4541 }
4542
4543 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
4544
4545 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
4546 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
4547 HCLGE_PHY_MDIX_CTRL_S);
4548
4549 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
4550 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
4551 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
4552
4553 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
4554
4555 switch (mdix_ctrl) {
4556 case 0x0:
4557 *tp_mdix_ctrl = ETH_TP_MDI;
4558 break;
4559 case 0x1:
4560 *tp_mdix_ctrl = ETH_TP_MDI_X;
4561 break;
4562 case 0x3:
4563 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
4564 break;
4565 default:
4566 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4567 break;
4568 }
4569
4570 if (!is_resolved)
4571 *tp_mdix = ETH_TP_MDI_INVALID;
4572 else if (mdix)
4573 *tp_mdix = ETH_TP_MDI_X;
4574 else
4575 *tp_mdix = ETH_TP_MDI;
4576}
4577
4578static int hclge_init_client_instance(struct hnae3_client *client,
4579 struct hnae3_ae_dev *ae_dev)
4580{
4581 struct hclge_dev *hdev = ae_dev->priv;
4582 struct hclge_vport *vport;
4583 int i, ret;
4584
4585 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4586 vport = &hdev->vport[i];
4587
4588 switch (client->type) {
4589 case HNAE3_CLIENT_KNIC:
4590
4591 hdev->nic_client = client;
4592 vport->nic.client = client;
4593 ret = client->ops->init_instance(&vport->nic);
4594 if (ret)
4595 goto err;
4596
4597 if (hdev->roce_client &&
e92a0843 4598 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4599 struct hnae3_client *rc = hdev->roce_client;
4600
4601 ret = hclge_init_roce_base_info(vport);
4602 if (ret)
4603 goto err;
4604
4605 ret = rc->ops->init_instance(&vport->roce);
4606 if (ret)
4607 goto err;
4608 }
4609
4610 break;
4611 case HNAE3_CLIENT_UNIC:
4612 hdev->nic_client = client;
4613 vport->nic.client = client;
4614
4615 ret = client->ops->init_instance(&vport->nic);
4616 if (ret)
4617 goto err;
4618
4619 break;
4620 case HNAE3_CLIENT_ROCE:
e92a0843 4621 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4622 hdev->roce_client = client;
4623 vport->roce.client = client;
4624 }
4625
3a46f34d 4626 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 4627 ret = hclge_init_roce_base_info(vport);
4628 if (ret)
4629 goto err;
4630
4631 ret = client->ops->init_instance(&vport->roce);
4632 if (ret)
4633 goto err;
4634 }
4635 }
4636 }
4637
4638 return 0;
4639err:
4640 return ret;
4641}
4642
4643static void hclge_uninit_client_instance(struct hnae3_client *client,
4644 struct hnae3_ae_dev *ae_dev)
4645{
4646 struct hclge_dev *hdev = ae_dev->priv;
4647 struct hclge_vport *vport;
4648 int i;
4649
4650 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4651 vport = &hdev->vport[i];
a17dcf3f 4652 if (hdev->roce_client) {
46a3df9f
S		 4653 hdev->roce_client->ops->uninit_instance(&vport->roce,
4654 0);
a17dcf3f
L		 4655 hdev->roce_client = NULL;
4656 vport->roce.client = NULL;
4657 }
46a3df9f
S		 4658 if (client->type == HNAE3_CLIENT_ROCE)
4659 return;
a17dcf3f 4660 if (client->ops->uninit_instance) {
46a3df9f 4661 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 4662 hdev->nic_client = NULL;
4663 vport->nic.client = NULL;
4664 }
46a3df9f
S		 4665 }
4666}
4667
4668static int hclge_pci_init(struct hclge_dev *hdev)
4669{
4670 struct pci_dev *pdev = hdev->pdev;
4671 struct hclge_hw *hw;
4672 int ret;
4673
4674 ret = pci_enable_device(pdev);
4675 if (ret) {
4676 dev_err(&pdev->dev, "failed to enable PCI device\n");
4677 goto err_no_drvdata;
4678 }
4679
4680 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4681 if (ret) {
4682 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4683 if (ret) {
4684 dev_err(&pdev->dev,
4685 "can't set consistent PCI DMA");
4686 goto err_disable_device;
4687 }
4688 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4689 }
4690
4691 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4692 if (ret) {
4693 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4694 goto err_disable_device;
4695 }
4696
4697 pci_set_master(pdev);
4698 hw = &hdev->hw;
4699 hw->back = hdev;
4700 hw->io_base = pcim_iomap(pdev, 2, 0);
4701 if (!hw->io_base) {
4702 dev_err(&pdev->dev, "Can't map configuration register space\n");
4703 ret = -ENOMEM;
4704 goto err_clr_master;
4705 }
4706
709eb41a
L		 4707 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
4708
46a3df9f
S		 4709 return 0;
4710err_clr_master:
4711 pci_clear_master(pdev);
4712 pci_release_regions(pdev);
4713err_disable_device:
4714 pci_disable_device(pdev);
4715err_no_drvdata:
4716 pci_set_drvdata(pdev, NULL);
4717
4718 return ret;
4719}
4720
4721static void hclge_pci_uninit(struct hclge_dev *hdev)
4722{
4723 struct pci_dev *pdev = hdev->pdev;
4724
887c3820 4725 pci_free_irq_vectors(pdev);
46a3df9f
S		 4726 pci_clear_master(pdev);
4727 pci_release_mem_regions(pdev);
4728 pci_disable_device(pdev);
4729}
4730
4731static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4732{
4733 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 4734 struct hclge_dev *hdev;
4735 int ret;
4736
4737 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4738 if (!hdev) {
4739 ret = -ENOMEM;
4740 goto err_hclge_dev;
4741 }
4742
46a3df9f
S		 4743 hdev->pdev = pdev;
4744 hdev->ae_dev = ae_dev;
4ed340ab 4745 hdev->reset_type = HNAE3_NONE_RESET;
ed4a1bb8 4746 hdev->reset_request = 0;
202f2014 4747 hdev->reset_pending = 0;
46a3df9f
S		 4748 ae_dev->priv = hdev;
4749
46a3df9f
S		 4750 ret = hclge_pci_init(hdev);
4751 if (ret) {
4752 dev_err(&pdev->dev, "PCI init failed\n");
4753 goto err_pci_init;
4754 }
4755
3efb960f
L		 4756 /* Firmware command queue initialize */
4757 ret = hclge_cmd_queue_init(hdev);
4758 if (ret) {
4759 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
4760 return ret;
4761 }
4762
4763 /* Firmware command initialize */
46a3df9f
S		 4764 ret = hclge_cmd_init(hdev);
4765 if (ret)
4766 goto err_cmd_init;
4767
4768 ret = hclge_get_cap(hdev);
4769 if (ret) {
e00e2197
CIK		 4770 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4771 ret);
46a3df9f
S		 4772 return ret;
4773 }
4774
4775 ret = hclge_configure(hdev);
4776 if (ret) {
4777 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4778 return ret;
4779 }
4780
887c3820 4781 ret = hclge_init_msi(hdev);
46a3df9f 4782 if (ret) {
887c3820 4783 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
46a3df9f
S		 4784 return ret;
4785 }
4786
466b0c00
L		 4787 ret = hclge_misc_irq_init(hdev);
4788 if (ret) {
4789 dev_err(&pdev->dev,
4790 "Misc IRQ(vector0) init error, ret = %d.\n",
4791 ret);
4792 return ret;
4793 }
4794
46a3df9f
S		 4795 ret = hclge_alloc_tqps(hdev);
4796 if (ret) {
4797 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4798 return ret;
4799 }
4800
4801 ret = hclge_alloc_vport(hdev);
4802 if (ret) {
4803 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4804 return ret;
4805 }
4806
7df7dad6
L		 4807 ret = hclge_map_tqp(hdev);
4808 if (ret) {
4809 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4810 return ret;
4811 }
4812
cf9cca2d 4813 ret = hclge_mac_mdio_config(hdev);
4814 if (ret) {
4815 dev_warn(&hdev->pdev->dev,
4816 "mdio config fail ret=%d\n", ret);
4817 return ret;
4818 }
4819
46a3df9f
S		 4820 ret = hclge_mac_init(hdev);
4821 if (ret) {
4822 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4823 return ret;
4824 }
4825 ret = hclge_buffer_alloc(hdev);
4826 if (ret) {
4827 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4828 return ret;
4829 }
4830
4831 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4832 if (ret) {
4833 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4834 return ret;
4835 }
4836
46a3df9f
S		 4837 ret = hclge_init_vlan_config(hdev);
4838 if (ret) {
4839 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4840 return ret;
4841 }
4842
4843 ret = hclge_tm_schd_init(hdev);
4844 if (ret) {
4845 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4846 return ret;
68ece54e
YL		 4847 }
4848
4849 ret = hclge_rss_init_hw(hdev);
4850 if (ret) {
4851 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4852 return ret;
46a3df9f
S		 4853 }
4854
cacde272
YL		 4855 hclge_dcb_ops_set(hdev);
4856
d039ef68 4857 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 4858 INIT_WORK(&hdev->service_task, hclge_service_task);
ed4a1bb8 4859 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
46a3df9f 4860
466b0c00
L		 4861 /* Enable MISC vector(vector0) */
4862 hclge_enable_vector(&hdev->misc_vector, true);
4863
46a3df9f
S		 4864 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4865 set_bit(HCLGE_STATE_DOWN, &hdev->state);
ed4a1bb8
SM		 4866 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
4867 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
46a3df9f
S		 4868
4869 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4870 return 0;
4871
4872err_cmd_init:
4873 pci_release_regions(pdev);
4874err_pci_init:
4875 pci_set_drvdata(pdev, NULL);
4876err_hclge_dev:
4877 return ret;
4878}
4879
c6dc5213 4880static void hclge_stats_clear(struct hclge_dev *hdev)
4881{
4882 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
4883}
4884
4ed340ab
L		 4885static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
4886{
4887 struct hclge_dev *hdev = ae_dev->priv;
4888 struct pci_dev *pdev = ae_dev->pdev;
4889 int ret;
4890
4891 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4892
c6dc5213 4893 hclge_stats_clear(hdev);
4894
4ed340ab
L		 4895 ret = hclge_cmd_init(hdev);
4896 if (ret) {
4897 dev_err(&pdev->dev, "Cmd queue init failed\n");
4898 return ret;
4899 }
4900
4901 ret = hclge_get_cap(hdev);
4902 if (ret) {
4903 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4904 ret);
4905 return ret;
4906 }
4907
4908 ret = hclge_configure(hdev);
4909 if (ret) {
4910 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4911 return ret;
4912 }
4913
4914 ret = hclge_map_tqp(hdev);
4915 if (ret) {
4916 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4917 return ret;
4918 }
4919
4920 ret = hclge_mac_init(hdev);
4921 if (ret) {
4922 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4923 return ret;
4924 }
4925
4926 ret = hclge_buffer_alloc(hdev);
4927 if (ret) {
4928 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4929 return ret;
4930 }
4931
4932 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4933 if (ret) {
4934 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4935 return ret;
4936 }
4937
4938 ret = hclge_init_vlan_config(hdev);
4939 if (ret) {
4940 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4941 return ret;
4942 }
4943
4944 ret = hclge_tm_schd_init(hdev);
4945 if (ret) {
4946 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4947 return ret;
4948 }
4949
4950 ret = hclge_rss_init_hw(hdev);
4951 if (ret) {
4952 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4953 return ret;
4954 }
4955
4956 /* Enable MISC vector(vector0) */
4957 hclge_enable_vector(&hdev->misc_vector, true);
4958
4959 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
4960 HCLGE_DRIVER_NAME);
4961
4962 return 0;
4963}
4964
46a3df9f
S		 4965static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4966{
4967 struct hclge_dev *hdev = ae_dev->priv;
4968 struct hclge_mac *mac = &hdev->hw.mac;
4969
4970 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4971
2a32ca13
AB		 4972 if (IS_ENABLED(CONFIG_PCI_IOV))
4973 hclge_disable_sriov(hdev);
46a3df9f 4974
d039ef68 4975 if (hdev->service_timer.function)
46a3df9f
S		 4976 del_timer_sync(&hdev->service_timer);
4977 if (hdev->service_task.func)
4978 cancel_work_sync(&hdev->service_task);
ed4a1bb8
SM		 4979 if (hdev->rst_service_task.func)
4980 cancel_work_sync(&hdev->rst_service_task);
46a3df9f
S		 4981
4982 if (mac->phydev)
4983 mdiobus_unregister(mac->mdio_bus);
4984
466b0c00
L		 4985 /* Disable MISC vector(vector0) */
4986 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 4987 hclge_destroy_cmd_queue(&hdev->hw);
202f2014 4988 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 4989 hclge_pci_uninit(hdev);
4990 ae_dev->priv = NULL;
4991}
4992
4993static const struct hnae3_ae_ops hclge_ops = {
4994 .init_ae_dev = hclge_init_ae_dev,
4995 .uninit_ae_dev = hclge_uninit_ae_dev,
4996 .init_client_instance = hclge_init_client_instance,
4997 .uninit_client_instance = hclge_uninit_client_instance,
4998 .map_ring_to_vector = hclge_map_handle_ring_to_vector,
4999 .unmap_ring_from_vector = hclge_unmap_ring_from_vector,
5000 .get_vector = hclge_get_vector,
5001 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 5002 .set_loopback = hclge_set_loopback,
46a3df9f
S		 5003 .start = hclge_ae_start,
5004 .stop = hclge_ae_stop,
5005 .get_status = hclge_get_status,
5006 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5007 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5008 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5009 .get_media_type = hclge_get_media_type,
5010 .get_rss_key_size = hclge_get_rss_key_size,
5011 .get_rss_indir_size = hclge_get_rss_indir_size,
5012 .get_rss = hclge_get_rss,
5013 .set_rss = hclge_set_rss,
f7db940a 5014 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 5015 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 5016 .get_tc_size = hclge_get_tc_size,
5017 .get_mac_addr = hclge_get_mac_addr,
5018 .set_mac_addr = hclge_set_mac_addr,
5019 .add_uc_addr = hclge_add_uc_addr,
5020 .rm_uc_addr = hclge_rm_uc_addr,
5021 .add_mc_addr = hclge_add_mc_addr,
5022 .rm_mc_addr = hclge_rm_mc_addr,
5023 .set_autoneg = hclge_set_autoneg,
5024 .get_autoneg = hclge_get_autoneg,
5025 .get_pauseparam = hclge_get_pauseparam,
5026 .set_mtu = hclge_set_mtu,
5027 .reset_queue = hclge_reset_tqp,
5028 .get_stats = hclge_get_stats,
5029 .update_stats = hclge_update_stats,
5030 .get_strings = hclge_get_strings,
5031 .get_sset_count = hclge_get_sset_count,
5032 .get_fw_version = hclge_get_fw_version,
5033 .get_mdix_mode = hclge_get_mdix_mode,
5034 .set_vlan_filter = hclge_set_port_vlan_filter,
5035 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
4ed340ab 5036 .reset_event = hclge_reset_event,
46a3df9f
S		 5037};
5038
5039static struct hnae3_ae_algo ae_algo = {
5040 .ops = &hclge_ops,
5041 .name = HCLGE_NAME,
5042 .pdev_id_table = ae_algo_pci_tbl,
5043};
5044
5045static int hclge_init(void)
5046{
5047 pr_info("%s is initializing\n", HCLGE_NAME);
5048
5049 return hnae3_register_ae_algo(&ae_algo);
5050}
5051
5052static void hclge_exit(void)
5053{
5054 hnae3_unregister_ae_algo(&ae_algo);
5055}
5056module_init(hclge_init);
5057module_exit(hclge_exit);
5058
5059MODULE_LICENSE("GPL");
5060MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5061MODULE_DESCRIPTION("HCLGE Driver");
5062MODULE_VERSION(HCLGE_MOD_VERSION);
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