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net: hns3: Fixes the initialization of MAC address in hardware
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
20
21#include "hclge_cmd.h"
22#include "hclge_main.h"
23#include "hclge_mdio.h"
24#include "hclge_tm.h"
25#include "hnae3.h"
26
27#define HCLGE_NAME "hclge"
28#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
29#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
30#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
31#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
32
33static int hclge_rss_init_hw(struct hclge_dev *hdev);
34static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
35 enum hclge_mta_dmac_sel_type mta_mac_sel,
36 bool enable);
37static int hclge_init_vlan_config(struct hclge_dev *hdev);
38
39static struct hnae3_ae_algo ae_algo;
40
41static const struct pci_device_id ae_algo_pci_tbl[] = {
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
49 /* Required last entry */
50 {0, }
51};
52
53static const struct pci_device_id roce_pci_tbl[] = {
54 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
57 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
58 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
59 /* Required last entry */
60 {0, }
61};
62
63static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
64 "Mac Loopback test",
65 "Serdes Loopback test",
66 "Phy Loopback test"
67};
68
69static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
70 {"igu_rx_oversize_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
72 {"igu_rx_undersize_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
74 {"igu_rx_out_all_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
76 {"igu_rx_uni_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
78 {"igu_rx_multi_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
80 {"igu_rx_broad_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
82 {"egu_tx_out_all_pkt",
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
84 {"egu_tx_uni_pkt",
85 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
86 {"egu_tx_multi_pkt",
87 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
88 {"egu_tx_broad_pkt",
89 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
90 {"ssu_ppp_mac_key_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
92 {"ssu_ppp_host_key_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
94 {"ppp_ssu_mac_rlt_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
96 {"ppp_ssu_host_rlt_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
98 {"ssu_tx_in_num",
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
100 {"ssu_tx_out_num",
101 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
102 {"ssu_rx_in_num",
103 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
104 {"ssu_rx_out_num",
105 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
106};
107
108static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
109 {"igu_rx_err_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
111 {"igu_rx_no_eof_pkt",
112 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
113 {"igu_rx_no_sof_pkt",
114 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
115 {"egu_tx_1588_pkt",
116 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
117 {"ssu_full_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
119 {"ssu_part_drop_num",
120 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
121 {"ppp_key_drop_num",
122 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
123 {"ppp_rlt_drop_num",
124 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
125 {"ssu_key_drop_num",
126 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
127 {"pkt_curr_buf_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
129 {"qcn_fb_rcv_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
131 {"qcn_fb_drop_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
133 {"qcn_fb_invaild_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
135 {"rx_packet_tc0_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
137 {"rx_packet_tc1_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
139 {"rx_packet_tc2_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
141 {"rx_packet_tc3_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
143 {"rx_packet_tc4_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
145 {"rx_packet_tc5_in_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
147 {"rx_packet_tc6_in_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
149 {"rx_packet_tc7_in_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
151 {"rx_packet_tc0_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
153 {"rx_packet_tc1_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
155 {"rx_packet_tc2_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
157 {"rx_packet_tc3_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
159 {"rx_packet_tc4_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
161 {"rx_packet_tc5_out_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
163 {"rx_packet_tc6_out_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
165 {"rx_packet_tc7_out_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
167 {"tx_packet_tc0_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
169 {"tx_packet_tc1_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
171 {"tx_packet_tc2_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
173 {"tx_packet_tc3_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
175 {"tx_packet_tc4_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
177 {"tx_packet_tc5_in_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
179 {"tx_packet_tc6_in_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
181 {"tx_packet_tc7_in_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
183 {"tx_packet_tc0_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
185 {"tx_packet_tc1_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
187 {"tx_packet_tc2_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
189 {"tx_packet_tc3_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
191 {"tx_packet_tc4_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
193 {"tx_packet_tc5_out_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
195 {"tx_packet_tc6_out_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
197 {"tx_packet_tc7_out_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
199 {"pkt_curr_buf_tc0_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
201 {"pkt_curr_buf_tc1_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
203 {"pkt_curr_buf_tc2_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
205 {"pkt_curr_buf_tc3_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
207 {"pkt_curr_buf_tc4_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
209 {"pkt_curr_buf_tc5_cnt",
210 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
211 {"pkt_curr_buf_tc6_cnt",
212 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
213 {"pkt_curr_buf_tc7_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
215 {"mb_uncopy_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
217 {"lo_pri_unicast_rlt_drop_num",
218 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
219 {"hi_pri_multicast_rlt_drop_num",
220 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
221 {"lo_pri_multicast_rlt_drop_num",
222 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
223 {"rx_oq_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
225 {"tx_oq_drop_pkt_cnt",
226 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
227 {"nic_l2_err_drop_pkt_cnt",
228 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
229 {"roc_l2_err_drop_pkt_cnt",
230 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
231};
232
233static const struct hclge_comm_stats_str g_mac_stats_string[] = {
234 {"mac_tx_mac_pause_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
236 {"mac_rx_mac_pause_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
238 {"mac_tx_pfc_pri0_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
240 {"mac_tx_pfc_pri1_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
242 {"mac_tx_pfc_pri2_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
244 {"mac_tx_pfc_pri3_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
246 {"mac_tx_pfc_pri4_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
248 {"mac_tx_pfc_pri5_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
250 {"mac_tx_pfc_pri6_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
252 {"mac_tx_pfc_pri7_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
254 {"mac_rx_pfc_pri0_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
256 {"mac_rx_pfc_pri1_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
258 {"mac_rx_pfc_pri2_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
260 {"mac_rx_pfc_pri3_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
262 {"mac_rx_pfc_pri4_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
264 {"mac_rx_pfc_pri5_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
266 {"mac_rx_pfc_pri6_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
268 {"mac_rx_pfc_pri7_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
270 {"mac_tx_total_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
272 {"mac_tx_total_oct_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
274 {"mac_tx_good_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
276 {"mac_tx_bad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
278 {"mac_tx_good_oct_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
280 {"mac_tx_bad_oct_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
282 {"mac_tx_uni_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
284 {"mac_tx_multi_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
286 {"mac_tx_broad_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
288 {"mac_tx_undersize_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
290 {"mac_tx_overrsize_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
292 {"mac_tx_64_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
294 {"mac_tx_65_127_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
296 {"mac_tx_128_255_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
298 {"mac_tx_256_511_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
300 {"mac_tx_512_1023_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
302 {"mac_tx_1024_1518_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
304 {"mac_tx_1519_max_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
306 {"mac_rx_total_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
308 {"mac_rx_total_oct_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
310 {"mac_rx_good_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
312 {"mac_rx_bad_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
314 {"mac_rx_good_oct_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
316 {"mac_rx_bad_oct_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
318 {"mac_rx_uni_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
320 {"mac_rx_multi_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
322 {"mac_rx_broad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
324 {"mac_rx_undersize_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
326 {"mac_rx_overrsize_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
328 {"mac_rx_64_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
330 {"mac_rx_65_127_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
332 {"mac_rx_128_255_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
334 {"mac_rx_256_511_oct_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
336 {"mac_rx_512_1023_oct_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
338 {"mac_rx_1024_1518_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
340 {"mac_rx_1519_max_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
342
343 {"mac_trans_fragment_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
345 {"mac_trans_undermin_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
347 {"mac_trans_jabber_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
349 {"mac_trans_err_all_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
351 {"mac_trans_from_app_good_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
353 {"mac_trans_from_app_bad_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
355 {"mac_rcv_fragment_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
357 {"mac_rcv_undermin_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
359 {"mac_rcv_jabber_pkt_num",
360 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
361 {"mac_rcv_fcs_err_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
363 {"mac_rcv_send_app_good_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
365 {"mac_rcv_send_app_bad_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
367};
368
369static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
370{
371#define HCLGE_64_BIT_CMD_NUM 5
372#define HCLGE_64_BIT_RTN_DATANUM 4
373 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
374 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
375 u64 *desc_data;
376 int i, k, n;
377 int ret;
378
379 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
380 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
381 if (ret) {
382 dev_err(&hdev->pdev->dev,
383 "Get 64 bit pkt stats fail, status = %d.\n", ret);
384 return ret;
385 }
386
387 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
388 if (unlikely(i == 0)) {
389 desc_data = (u64 *)(&desc[i].data[0]);
390 n = HCLGE_64_BIT_RTN_DATANUM - 1;
391 } else {
392 desc_data = (u64 *)(&desc[i]);
393 n = HCLGE_64_BIT_RTN_DATANUM;
394 }
395 for (k = 0; k < n; k++) {
396 *data++ += cpu_to_le64(*desc_data);
397 desc_data++;
398 }
399 }
400
401 return 0;
402}
403
404static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
405{
406 stats->pkt_curr_buf_cnt = 0;
407 stats->pkt_curr_buf_tc0_cnt = 0;
408 stats->pkt_curr_buf_tc1_cnt = 0;
409 stats->pkt_curr_buf_tc2_cnt = 0;
410 stats->pkt_curr_buf_tc3_cnt = 0;
411 stats->pkt_curr_buf_tc4_cnt = 0;
412 stats->pkt_curr_buf_tc5_cnt = 0;
413 stats->pkt_curr_buf_tc6_cnt = 0;
414 stats->pkt_curr_buf_tc7_cnt = 0;
415}
416
417static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
418{
419#define HCLGE_32_BIT_CMD_NUM 8
420#define HCLGE_32_BIT_RTN_DATANUM 8
421
422 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
423 struct hclge_32_bit_stats *all_32_bit_stats;
424 u32 *desc_data;
425 int i, k, n;
426 u64 *data;
427 int ret;
428
429 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
430 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
431
432 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
433 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
434 if (ret) {
435 dev_err(&hdev->pdev->dev,
436 "Get 32 bit pkt stats fail, status = %d.\n", ret);
437
438 return ret;
439 }
440
441 hclge_reset_partial_32bit_counter(all_32_bit_stats);
442 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
443 if (unlikely(i == 0)) {
444 all_32_bit_stats->igu_rx_err_pkt +=
445 cpu_to_le32(desc[i].data[0]);
446 all_32_bit_stats->igu_rx_no_eof_pkt +=
447 cpu_to_le32(desc[i].data[1] & 0xffff);
448 all_32_bit_stats->igu_rx_no_sof_pkt +=
449 cpu_to_le32((desc[i].data[1] >> 16) & 0xffff);
450
451 desc_data = (u32 *)(&desc[i].data[2]);
452 n = HCLGE_32_BIT_RTN_DATANUM - 4;
453 } else {
454 desc_data = (u32 *)(&desc[i]);
455 n = HCLGE_32_BIT_RTN_DATANUM;
456 }
457 for (k = 0; k < n; k++) {
458 *data++ += cpu_to_le32(*desc_data);
459 desc_data++;
460 }
461 }
462
463 return 0;
464}
465
466static int hclge_mac_update_stats(struct hclge_dev *hdev)
467{
468#define HCLGE_MAC_CMD_NUM 17
469#define HCLGE_RTN_DATA_NUM 4
470
471 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
472 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
473 u64 *desc_data;
474 int i, k, n;
475 int ret;
476
477 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
478 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
479 if (ret) {
480 dev_err(&hdev->pdev->dev,
481 "Get MAC pkt stats fail, status = %d.\n", ret);
482
483 return ret;
484 }
485
486 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
487 if (unlikely(i == 0)) {
488 desc_data = (u64 *)(&desc[i].data[0]);
489 n = HCLGE_RTN_DATA_NUM - 2;
490 } else {
491 desc_data = (u64 *)(&desc[i]);
492 n = HCLGE_RTN_DATA_NUM;
493 }
494 for (k = 0; k < n; k++) {
495 *data++ += cpu_to_le64(*desc_data);
496 desc_data++;
497 }
498 }
499
500 return 0;
501}
502
503static int hclge_tqps_update_stats(struct hnae3_handle *handle)
504{
505 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
506 struct hclge_vport *vport = hclge_get_vport(handle);
507 struct hclge_dev *hdev = vport->back;
508 struct hnae3_queue *queue;
509 struct hclge_desc desc[1];
510 struct hclge_tqp *tqp;
511 int ret, i;
512
513 for (i = 0; i < kinfo->num_tqps; i++) {
514 queue = handle->kinfo.tqp[i];
515 tqp = container_of(queue, struct hclge_tqp, q);
516 /* command : HCLGE_OPC_QUERY_IGU_STAT */
517 hclge_cmd_setup_basic_desc(&desc[0],
518 HCLGE_OPC_QUERY_RX_STATUS,
519 true);
520
521 desc[0].data[0] = (tqp->index & 0x1ff);
522 ret = hclge_cmd_send(&hdev->hw, desc, 1);
523 if (ret) {
524 dev_err(&hdev->pdev->dev,
525 "Query tqp stat fail, status = %d,queue = %d\n",
526 ret, i);
527 return ret;
528 }
529 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
530 cpu_to_le32(desc[0].data[4]);
531 }
532
533 for (i = 0; i < kinfo->num_tqps; i++) {
534 queue = handle->kinfo.tqp[i];
535 tqp = container_of(queue, struct hclge_tqp, q);
536 /* command : HCLGE_OPC_QUERY_IGU_STAT */
537 hclge_cmd_setup_basic_desc(&desc[0],
538 HCLGE_OPC_QUERY_TX_STATUS,
539 true);
540
541 desc[0].data[0] = (tqp->index & 0x1ff);
542 ret = hclge_cmd_send(&hdev->hw, desc, 1);
543 if (ret) {
544 dev_err(&hdev->pdev->dev,
545 "Query tqp stat fail, status = %d,queue = %d\n",
546 ret, i);
547 return ret;
548 }
549 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
550 cpu_to_le32(desc[0].data[4]);
551 }
552
553 return 0;
554}
555
556static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
557{
558 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
559 struct hclge_tqp *tqp;
560 u64 *buff = data;
561 int i;
562
563 for (i = 0; i < kinfo->num_tqps; i++) {
564 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
565 *buff++ = cpu_to_le64(tqp->tqp_stats.rcb_tx_ring_pktnum_rcd);
566 }
567
568 for (i = 0; i < kinfo->num_tqps; i++) {
569 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
570 *buff++ = cpu_to_le64(tqp->tqp_stats.rcb_rx_ring_pktnum_rcd);
571 }
572
573 return buff;
574}
575
576static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
577{
578 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
579
580 return kinfo->num_tqps * (2);
581}
582
583static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
584{
585 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
586 u8 *buff = data;
587 int i = 0;
588
589 for (i = 0; i < kinfo->num_tqps; i++) {
590 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
591 struct hclge_tqp, q);
592 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
593 tqp->index);
594 buff = buff + ETH_GSTRING_LEN;
595 }
596
597 for (i = 0; i < kinfo->num_tqps; i++) {
598 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
599 struct hclge_tqp, q);
600 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
601 tqp->index);
602 buff = buff + ETH_GSTRING_LEN;
603 }
604
605 return buff;
606}
607
608static u64 *hclge_comm_get_stats(void *comm_stats,
609 const struct hclge_comm_stats_str strs[],
610 int size, u64 *data)
611{
612 u64 *buf = data;
613 u32 i;
614
615 for (i = 0; i < size; i++)
616 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
617
618 return buf + size;
619}
620
621static u8 *hclge_comm_get_strings(u32 stringset,
622 const struct hclge_comm_stats_str strs[],
623 int size, u8 *data)
624{
625 char *buff = (char *)data;
626 u32 i;
627
628 if (stringset != ETH_SS_STATS)
629 return buff;
630
631 for (i = 0; i < size; i++) {
632 snprintf(buff, ETH_GSTRING_LEN,
633 strs[i].desc);
634 buff = buff + ETH_GSTRING_LEN;
635 }
636
637 return (u8 *)buff;
638}
639
640static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
641 struct net_device_stats *net_stats)
642{
643 net_stats->tx_dropped = 0;
644 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
645 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
646 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
647
648 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
649 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
650 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
651 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
652 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
653 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
654
655 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
656 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
657
658 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
659 net_stats->rx_length_errors =
660 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
661 net_stats->rx_length_errors +=
662 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
663 net_stats->rx_over_errors =
664 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
665}
666
667static void hclge_update_stats_for_all(struct hclge_dev *hdev)
668{
669 struct hnae3_handle *handle;
670 int status;
671
672 handle = &hdev->vport[0].nic;
673 if (handle->client) {
674 status = hclge_tqps_update_stats(handle);
675 if (status) {
676 dev_err(&hdev->pdev->dev,
677 "Update TQPS stats fail, status = %d.\n",
678 status);
679 }
680 }
681
682 status = hclge_mac_update_stats(hdev);
683 if (status)
684 dev_err(&hdev->pdev->dev,
685 "Update MAC stats fail, status = %d.\n", status);
686
687 status = hclge_32_bit_update_stats(hdev);
688 if (status)
689 dev_err(&hdev->pdev->dev,
690 "Update 32 bit stats fail, status = %d.\n",
691 status);
692
693 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
694}
695
696static void hclge_update_stats(struct hnae3_handle *handle,
697 struct net_device_stats *net_stats)
698{
699 struct hclge_vport *vport = hclge_get_vport(handle);
700 struct hclge_dev *hdev = vport->back;
701 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
702 int status;
703
704 status = hclge_mac_update_stats(hdev);
705 if (status)
706 dev_err(&hdev->pdev->dev,
707 "Update MAC stats fail, status = %d.\n",
708 status);
709
710 status = hclge_32_bit_update_stats(hdev);
711 if (status)
712 dev_err(&hdev->pdev->dev,
713 "Update 32 bit stats fail, status = %d.\n",
714 status);
715
716 status = hclge_64_bit_update_stats(hdev);
717 if (status)
718 dev_err(&hdev->pdev->dev,
719 "Update 64 bit stats fail, status = %d.\n",
720 status);
721
722 status = hclge_tqps_update_stats(handle);
723 if (status)
724 dev_err(&hdev->pdev->dev,
725 "Update TQPS stats fail, status = %d.\n",
726 status);
727
728 hclge_update_netstat(hw_stats, net_stats);
729}
730
731static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
732{
733#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
734
735 struct hclge_vport *vport = hclge_get_vport(handle);
736 struct hclge_dev *hdev = vport->back;
737 int count = 0;
738
739 /* Loopback test support rules:
740 * mac: only GE mode support
741 * serdes: all mac mode will support include GE/XGE/LGE/CGE
742 * phy: only support when phy device exist on board
743 */
744 if (stringset == ETH_SS_TEST) {
745 /* clear loopback bit flags at first */
746 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
747 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
748 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
749 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
750 count += 1;
751 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
752 } else {
753 count = -EOPNOTSUPP;
754 }
755 } else if (stringset == ETH_SS_STATS) {
756 count = ARRAY_SIZE(g_mac_stats_string) +
757 ARRAY_SIZE(g_all_32bit_stats_string) +
758 ARRAY_SIZE(g_all_64bit_stats_string) +
759 hclge_tqps_get_sset_count(handle, stringset);
760 }
761
762 return count;
763}
764
765static void hclge_get_strings(struct hnae3_handle *handle,
766 u32 stringset,
767 u8 *data)
768{
769 u8 *p = (char *)data;
770 int size;
771
772 if (stringset == ETH_SS_STATS) {
773 size = ARRAY_SIZE(g_mac_stats_string);
774 p = hclge_comm_get_strings(stringset,
775 g_mac_stats_string,
776 size,
777 p);
778 size = ARRAY_SIZE(g_all_32bit_stats_string);
779 p = hclge_comm_get_strings(stringset,
780 g_all_32bit_stats_string,
781 size,
782 p);
783 size = ARRAY_SIZE(g_all_64bit_stats_string);
784 p = hclge_comm_get_strings(stringset,
785 g_all_64bit_stats_string,
786 size,
787 p);
788 p = hclge_tqps_get_strings(handle, p);
789 } else if (stringset == ETH_SS_TEST) {
790 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
791 memcpy(p,
792 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
793 ETH_GSTRING_LEN);
794 p += ETH_GSTRING_LEN;
795 }
796 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
797 memcpy(p,
798 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
799 ETH_GSTRING_LEN);
800 p += ETH_GSTRING_LEN;
801 }
802 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
803 memcpy(p,
804 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
805 ETH_GSTRING_LEN);
806 p += ETH_GSTRING_LEN;
807 }
808 }
809}
810
811static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
812{
813 struct hclge_vport *vport = hclge_get_vport(handle);
814 struct hclge_dev *hdev = vport->back;
815 u64 *p;
816
817 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
818 g_mac_stats_string,
819 ARRAY_SIZE(g_mac_stats_string),
820 data);
821 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
822 g_all_32bit_stats_string,
823 ARRAY_SIZE(g_all_32bit_stats_string),
824 p);
825 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
826 g_all_64bit_stats_string,
827 ARRAY_SIZE(g_all_64bit_stats_string),
828 p);
829 p = hclge_tqps_get_stats(handle, p);
830}
831
832static int hclge_parse_func_status(struct hclge_dev *hdev,
833 struct hclge_func_status *status)
834{
835 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
836 return -EINVAL;
837
838 /* Set the pf to main pf */
839 if (status->pf_state & HCLGE_PF_STATE_MAIN)
840 hdev->flag |= HCLGE_FLAG_MAIN;
841 else
842 hdev->flag &= ~HCLGE_FLAG_MAIN;
843
844 hdev->num_req_vfs = status->vf_num / status->pf_num;
845 return 0;
846}
847
848static int hclge_query_function_status(struct hclge_dev *hdev)
849{
850 struct hclge_func_status *req;
851 struct hclge_desc desc;
852 int timeout = 0;
853 int ret;
854
855 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
856 req = (struct hclge_func_status *)desc.data;
857
858 do {
859 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
860 if (ret) {
861 dev_err(&hdev->pdev->dev,
862 "query function status failed %d.\n",
863 ret);
864
865 return ret;
866 }
867
868 /* Check pf reset is done */
869 if (req->pf_state)
870 break;
871 usleep_range(1000, 2000);
872 } while (timeout++ < 5);
873
874 ret = hclge_parse_func_status(hdev, req);
875
876 return ret;
877}
878
879static int hclge_query_pf_resource(struct hclge_dev *hdev)
880{
881 struct hclge_pf_res *req;
882 struct hclge_desc desc;
883 int ret;
884
885 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
886 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
887 if (ret) {
888 dev_err(&hdev->pdev->dev,
889 "query pf resource failed %d.\n", ret);
890 return ret;
891 }
892
893 req = (struct hclge_pf_res *)desc.data;
894 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
895 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
896
897 if (hnae_get_bit(hdev->ae_dev->flag, HNAE_DEV_SUPPORT_ROCE_B)) {
898 hdev->num_roce_msix =
899 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
900 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
901
902 /* PF should have NIC vectors and Roce vectors,
903 * NIC vectors are queued before Roce vectors.
904 */
905 hdev->num_msi = hdev->num_roce_msix + HCLGE_ROCE_VECTOR_OFFSET;
906 } else {
907 hdev->num_msi =
908 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
909 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
910 }
911
912 return 0;
913}
914
915static int hclge_parse_speed(int speed_cmd, int *speed)
916{
917 switch (speed_cmd) {
918 case 6:
919 *speed = HCLGE_MAC_SPEED_10M;
920 break;
921 case 7:
922 *speed = HCLGE_MAC_SPEED_100M;
923 break;
924 case 0:
925 *speed = HCLGE_MAC_SPEED_1G;
926 break;
927 case 1:
928 *speed = HCLGE_MAC_SPEED_10G;
929 break;
930 case 2:
931 *speed = HCLGE_MAC_SPEED_25G;
932 break;
933 case 3:
934 *speed = HCLGE_MAC_SPEED_40G;
935 break;
936 case 4:
937 *speed = HCLGE_MAC_SPEED_50G;
938 break;
939 case 5:
940 *speed = HCLGE_MAC_SPEED_100G;
941 break;
942 default:
943 return -EINVAL;
944 }
945
946 return 0;
947}
948
949static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
950{
951 struct hclge_cfg_param *req;
952 u64 mac_addr_tmp_high;
953 u64 mac_addr_tmp;
954 int i;
955
956 req = (struct hclge_cfg_param *)desc[0].data;
957
958 /* get the configuration */
959 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
960 HCLGE_CFG_VMDQ_M,
961 HCLGE_CFG_VMDQ_S);
962 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
963 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
964 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
965 HCLGE_CFG_TQP_DESC_N_M,
966 HCLGE_CFG_TQP_DESC_N_S);
967
968 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
969 HCLGE_CFG_PHY_ADDR_M,
970 HCLGE_CFG_PHY_ADDR_S);
971 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
972 HCLGE_CFG_MEDIA_TP_M,
973 HCLGE_CFG_MEDIA_TP_S);
974 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
975 HCLGE_CFG_RX_BUF_LEN_M,
976 HCLGE_CFG_RX_BUF_LEN_S);
977 /* get mac_address */
978 mac_addr_tmp = __le32_to_cpu(req->param[2]);
979 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
980 HCLGE_CFG_MAC_ADDR_H_M,
981 HCLGE_CFG_MAC_ADDR_H_S);
982
983 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
984
985 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
986 HCLGE_CFG_DEFAULT_SPEED_M,
987 HCLGE_CFG_DEFAULT_SPEED_S);
988 for (i = 0; i < ETH_ALEN; i++)
989 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
990
991 req = (struct hclge_cfg_param *)desc[1].data;
992 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
993}
994
995/* hclge_get_cfg: query the static parameter from flash
996 * @hdev: pointer to struct hclge_dev
997 * @hcfg: the config structure to be getted
998 */
999static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1000{
1001 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1002 struct hclge_cfg_param *req;
1003 int i, ret;
1004
1005 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1006 req = (struct hclge_cfg_param *)desc[i].data;
1007 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1008 true);
1009 hnae_set_field(req->offset, HCLGE_CFG_OFFSET_M,
1010 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1011 /* Len should be united by 4 bytes when send to hardware */
1012 hnae_set_field(req->offset, HCLGE_CFG_RD_LEN_M,
1013 HCLGE_CFG_RD_LEN_S,
1014 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1015 req->offset = cpu_to_le32(req->offset);
1016 }
1017
1018 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1019 if (ret) {
1020 dev_err(&hdev->pdev->dev,
1021 "get config failed %d.\n", ret);
1022 return ret;
1023 }
1024
1025 hclge_parse_cfg(hcfg, desc);
1026 return 0;
1027}
1028
1029static int hclge_get_cap(struct hclge_dev *hdev)
1030{
1031 int ret;
1032
1033 ret = hclge_query_function_status(hdev);
1034 if (ret) {
1035 dev_err(&hdev->pdev->dev,
1036 "query function status error %d.\n", ret);
1037 return ret;
1038 }
1039
1040 /* get pf resource */
1041 ret = hclge_query_pf_resource(hdev);
1042 if (ret) {
1043 dev_err(&hdev->pdev->dev,
1044 "query pf resource error %d.\n", ret);
1045 return ret;
1046 }
1047
1048 return 0;
1049}
1050
1051static int hclge_configure(struct hclge_dev *hdev)
1052{
1053 struct hclge_cfg cfg;
1054 int ret, i;
1055
1056 ret = hclge_get_cfg(hdev, &cfg);
1057 if (ret) {
1058 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1059 return ret;
1060 }
1061
1062 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1063 hdev->base_tqp_pid = 0;
1064 hdev->rss_size_max = 1;
1065 hdev->rx_buf_len = cfg.rx_buf_len;
1066 for (i = 0; i < ETH_ALEN; i++)
1067 hdev->hw.mac.mac_addr[i] = cfg.mac_addr[i];
1068 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1069 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1070 hdev->num_desc = cfg.tqp_desc_num;
1071 hdev->tm_info.num_pg = 1;
1072 hdev->tm_info.num_tc = cfg.tc_num;
1073 hdev->tm_info.hw_pfc_map = 0;
1074
1075 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1076 if (ret) {
1077 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1078 return ret;
1079 }
1080
1081 if ((hdev->tm_info.num_tc > HNAE3_MAX_TC) ||
1082 (hdev->tm_info.num_tc < 1)) {
1083 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1084 hdev->tm_info.num_tc);
1085 hdev->tm_info.num_tc = 1;
1086 }
1087
1088 /* Currently not support uncontiuous tc */
1089 for (i = 0; i < cfg.tc_num; i++)
1090 hnae_set_bit(hdev->hw_tc_map, i, 1);
1091
1092 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1093 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1094 else
1095 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1096
1097 return ret;
1098}
1099
1100static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1101 int tso_mss_max)
1102{
1103 struct hclge_cfg_tso_status *req;
1104 struct hclge_desc desc;
1105
1106 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1107
1108 req = (struct hclge_cfg_tso_status *)desc.data;
1109 hnae_set_field(req->tso_mss_min, HCLGE_TSO_MSS_MIN_M,
1110 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1111 hnae_set_field(req->tso_mss_max, HCLGE_TSO_MSS_MIN_M,
1112 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1113
1114 return hclge_cmd_send(&hdev->hw, &desc, 1);
1115}
1116
1117static int hclge_alloc_tqps(struct hclge_dev *hdev)
1118{
1119 struct hclge_tqp *tqp;
1120 int i;
1121
1122 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1123 sizeof(struct hclge_tqp), GFP_KERNEL);
1124 if (!hdev->htqp)
1125 return -ENOMEM;
1126
1127 tqp = hdev->htqp;
1128
1129 for (i = 0; i < hdev->num_tqps; i++) {
1130 tqp->dev = &hdev->pdev->dev;
1131 tqp->index = i;
1132
1133 tqp->q.ae_algo = &ae_algo;
1134 tqp->q.buf_size = hdev->rx_buf_len;
1135 tqp->q.desc_num = hdev->num_desc;
1136 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1137 i * HCLGE_TQP_REG_SIZE;
1138
1139 tqp++;
1140 }
1141
1142 return 0;
1143}
1144
1145static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1146 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1147{
1148 struct hclge_tqp_map *req;
1149 struct hclge_desc desc;
1150 int ret;
1151
1152 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1153
1154 req = (struct hclge_tqp_map *)desc.data;
1155 req->tqp_id = cpu_to_le16(tqp_pid);
1156 req->tqp_vf = cpu_to_le16(func_id);
1157 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1158 1 << HCLGE_TQP_MAP_EN_B;
1159 req->tqp_vid = cpu_to_le16(tqp_vid);
1160
1161 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1162 if (ret) {
1163 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1164 ret);
1165 return ret;
1166 }
1167
1168 return 0;
1169}
1170
1171static int hclge_assign_tqp(struct hclge_vport *vport,
1172 struct hnae3_queue **tqp, u16 num_tqps)
1173{
1174 struct hclge_dev *hdev = vport->back;
1175 int i, alloced, func_id, ret;
1176 bool is_pf;
1177
1178 func_id = vport->vport_id;
1179 is_pf = (vport->vport_id == 0) ? true : false;
1180
1181 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1182 alloced < num_tqps; i++) {
1183 if (!hdev->htqp[i].alloced) {
1184 hdev->htqp[i].q.handle = &vport->nic;
1185 hdev->htqp[i].q.tqp_index = alloced;
1186 tqp[alloced] = &hdev->htqp[i].q;
1187 hdev->htqp[i].alloced = true;
1188 ret = hclge_map_tqps_to_func(hdev, func_id,
1189 hdev->htqp[i].index,
1190 alloced, is_pf);
1191 if (ret)
1192 return ret;
1193
1194 alloced++;
1195 }
1196 }
1197 vport->alloc_tqps = num_tqps;
1198
1199 return 0;
1200}
1201
1202static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1203{
1204 struct hnae3_handle *nic = &vport->nic;
1205 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1206 struct hclge_dev *hdev = vport->back;
1207 int i, ret;
1208
1209 kinfo->num_desc = hdev->num_desc;
1210 kinfo->rx_buf_len = hdev->rx_buf_len;
1211 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1212 kinfo->rss_size
1213 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1214 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1215
1216 for (i = 0; i < HNAE3_MAX_TC; i++) {
1217 if (hdev->hw_tc_map & BIT(i)) {
1218 kinfo->tc_info[i].enable = true;
1219 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1220 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1221 kinfo->tc_info[i].tc = i;
1222 } else {
1223 /* Set to default queue if TC is disable */
1224 kinfo->tc_info[i].enable = false;
1225 kinfo->tc_info[i].tqp_offset = 0;
1226 kinfo->tc_info[i].tqp_count = 1;
1227 kinfo->tc_info[i].tc = 0;
1228 }
1229 }
1230
1231 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1232 sizeof(struct hnae3_queue *), GFP_KERNEL);
1233 if (!kinfo->tqp)
1234 return -ENOMEM;
1235
1236 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1237 if (ret) {
1238 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1239 return -EINVAL;
1240 }
1241
1242 return 0;
1243}
1244
1245static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1246{
1247 /* this would be initialized later */
1248}
1249
1250static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1251{
1252 struct hnae3_handle *nic = &vport->nic;
1253 struct hclge_dev *hdev = vport->back;
1254 int ret;
1255
1256 nic->pdev = hdev->pdev;
1257 nic->ae_algo = &ae_algo;
1258 nic->numa_node_mask = hdev->numa_node_mask;
1259
1260 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1261 ret = hclge_knic_setup(vport, num_tqps);
1262 if (ret) {
1263 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1264 ret);
1265 return ret;
1266 }
1267 } else {
1268 hclge_unic_setup(vport, num_tqps);
1269 }
1270
1271 return 0;
1272}
1273
1274static int hclge_alloc_vport(struct hclge_dev *hdev)
1275{
1276 struct pci_dev *pdev = hdev->pdev;
1277 struct hclge_vport *vport;
1278 u32 tqp_main_vport;
1279 u32 tqp_per_vport;
1280 int num_vport, i;
1281 int ret;
1282
1283 /* We need to alloc a vport for main NIC of PF */
1284 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1285
1286 if (hdev->num_tqps < num_vport)
1287 num_vport = hdev->num_tqps;
1288
1289 /* Alloc the same number of TQPs for every vport */
1290 tqp_per_vport = hdev->num_tqps / num_vport;
1291 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1292
1293 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1294 GFP_KERNEL);
1295 if (!vport)
1296 return -ENOMEM;
1297
1298 hdev->vport = vport;
1299 hdev->num_alloc_vport = num_vport;
1300
1301#ifdef CONFIG_PCI_IOV
1302 /* Enable SRIOV */
1303 if (hdev->num_req_vfs) {
1304 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1305 hdev->num_req_vfs);
1306 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1307 if (ret) {
1308 hdev->num_alloc_vfs = 0;
1309 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1310 ret);
1311 return ret;
1312 }
1313 }
1314 hdev->num_alloc_vfs = hdev->num_req_vfs;
1315#endif
1316
1317 for (i = 0; i < num_vport; i++) {
1318 vport->back = hdev;
1319 vport->vport_id = i;
1320
1321 if (i == 0)
1322 ret = hclge_vport_setup(vport, tqp_main_vport);
1323 else
1324 ret = hclge_vport_setup(vport, tqp_per_vport);
1325 if (ret) {
1326 dev_err(&pdev->dev,
1327 "vport setup failed for vport %d, %d\n",
1328 i, ret);
1329 return ret;
1330 }
1331
1332 vport++;
1333 }
1334
1335 return 0;
1336}
1337
1338static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, u16 buf_size)
1339{
1340/* TX buffer size is unit by 128 byte */
1341#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1342#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1343 struct hclge_tx_buff_alloc *req;
1344 struct hclge_desc desc;
1345 int ret;
1346 u8 i;
1347
1348 req = (struct hclge_tx_buff_alloc *)desc.data;
1349
1350 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1351 for (i = 0; i < HCLGE_TC_NUM; i++)
1352 req->tx_pkt_buff[i] =
1353 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1354 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1355
1356 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1357 if (ret) {
1358 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1359 ret);
1360 return ret;
1361 }
1362
1363 return 0;
1364}
1365
1366static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, u32 buf_size)
1367{
1368 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_size);
1369
1370 if (ret) {
1371 dev_err(&hdev->pdev->dev,
1372 "tx buffer alloc failed %d\n", ret);
1373 return ret;
1374 }
1375
1376 return 0;
1377}
1378
1379static int hclge_get_tc_num(struct hclge_dev *hdev)
1380{
1381 int i, cnt = 0;
1382
1383 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1384 if (hdev->hw_tc_map & BIT(i))
1385 cnt++;
1386 return cnt;
1387}
1388
1389static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1390{
1391 int i, cnt = 0;
1392
1393 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1394 if (hdev->hw_tc_map & BIT(i) &&
1395 hdev->tm_info.hw_pfc_map & BIT(i))
1396 cnt++;
1397 return cnt;
1398}
1399
1400/* Get the number of pfc enabled TCs, which have private buffer */
1401static int hclge_get_pfc_priv_num(struct hclge_dev *hdev)
1402{
1403 struct hclge_priv_buf *priv;
1404 int i, cnt = 0;
1405
1406 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1407 priv = &hdev->priv_buf[i];
1408 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1409 priv->enable)
1410 cnt++;
1411 }
1412
1413 return cnt;
1414}
1415
1416/* Get the number of pfc disabled TCs, which have private buffer */
1417static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev)
1418{
1419 struct hclge_priv_buf *priv;
1420 int i, cnt = 0;
1421
1422 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1423 priv = &hdev->priv_buf[i];
1424 if (hdev->hw_tc_map & BIT(i) &&
1425 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1426 priv->enable)
1427 cnt++;
1428 }
1429
1430 return cnt;
1431}
1432
1433static u32 hclge_get_rx_priv_buff_alloced(struct hclge_dev *hdev)
1434{
1435 struct hclge_priv_buf *priv;
1436 u32 rx_priv = 0;
1437 int i;
1438
1439 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1440 priv = &hdev->priv_buf[i];
1441 if (priv->enable)
1442 rx_priv += priv->buf_size;
1443 }
1444 return rx_priv;
1445}
1446
1447static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, u32 rx_all)
1448{
1449 u32 shared_buf_min, shared_buf_tc, shared_std;
1450 int tc_num, pfc_enable_num;
1451 u32 shared_buf;
1452 u32 rx_priv;
1453 int i;
1454
1455 tc_num = hclge_get_tc_num(hdev);
1456 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1457
1458 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1459 shared_buf_tc = pfc_enable_num * hdev->mps +
1460 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1461 hdev->mps;
1462 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1463
1464 rx_priv = hclge_get_rx_priv_buff_alloced(hdev);
1465 if (rx_all <= rx_priv + shared_std)
1466 return false;
1467
1468 shared_buf = rx_all - rx_priv;
1469 hdev->s_buf.buf_size = shared_buf;
1470 hdev->s_buf.self.high = shared_buf;
1471 hdev->s_buf.self.low = 2 * hdev->mps;
1472
1473 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1474 if ((hdev->hw_tc_map & BIT(i)) &&
1475 (hdev->tm_info.hw_pfc_map & BIT(i))) {
1476 hdev->s_buf.tc_thrd[i].low = hdev->mps;
1477 hdev->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1478 } else {
1479 hdev->s_buf.tc_thrd[i].low = 0;
1480 hdev->s_buf.tc_thrd[i].high = hdev->mps;
1481 }
1482 }
1483
1484 return true;
1485}
1486
1487/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1488 * @hdev: pointer to struct hclge_dev
1489 * @tx_size: the allocated tx buffer for all TCs
1490 * @return: 0: calculate sucessful, negative: fail
1491 */
1492int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size)
1493{
1494 u32 rx_all = hdev->pkt_buf_size - tx_size;
1495 int no_pfc_priv_num, pfc_priv_num;
1496 struct hclge_priv_buf *priv;
1497 int i;
1498
1499 /* step 1, try to alloc private buffer for all enabled tc */
1500 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1501 priv = &hdev->priv_buf[i];
1502 if (hdev->hw_tc_map & BIT(i)) {
1503 priv->enable = 1;
1504 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1505 priv->wl.low = hdev->mps;
1506 priv->wl.high = priv->wl.low + hdev->mps;
1507 priv->buf_size = priv->wl.high +
1508 HCLGE_DEFAULT_DV;
1509 } else {
1510 priv->wl.low = 0;
1511 priv->wl.high = 2 * hdev->mps;
1512 priv->buf_size = priv->wl.high;
1513 }
1514 }
1515 }
1516
1517 if (hclge_is_rx_buf_ok(hdev, rx_all))
1518 return 0;
1519
1520 /* step 2, try to decrease the buffer size of
1521 * no pfc TC's private buffer
1522 */
1523 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1524 priv = &hdev->priv_buf[i];
1525
1526 if (hdev->hw_tc_map & BIT(i))
1527 priv->enable = 1;
1528
1529 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1530 priv->wl.low = 128;
1531 priv->wl.high = priv->wl.low + hdev->mps;
1532 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1533 } else {
1534 priv->wl.low = 0;
1535 priv->wl.high = hdev->mps;
1536 priv->buf_size = priv->wl.high;
1537 }
1538 }
1539
1540 if (hclge_is_rx_buf_ok(hdev, rx_all))
1541 return 0;
1542
1543 /* step 3, try to reduce the number of pfc disabled TCs,
1544 * which have private buffer
1545 */
1546 /* get the total no pfc enable TC number, which have private buffer */
1547 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev);
1548
1549 /* let the last to be cleared first */
1550 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1551 priv = &hdev->priv_buf[i];
1552
1553 if (hdev->hw_tc_map & BIT(i) &&
1554 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1555 /* Clear the no pfc TC private buffer */
1556 priv->wl.low = 0;
1557 priv->wl.high = 0;
1558 priv->buf_size = 0;
1559 priv->enable = 0;
1560 no_pfc_priv_num--;
1561 }
1562
1563 if (hclge_is_rx_buf_ok(hdev, rx_all) ||
1564 no_pfc_priv_num == 0)
1565 break;
1566 }
1567
1568 if (hclge_is_rx_buf_ok(hdev, rx_all))
1569 return 0;
1570
1571 /* step 4, try to reduce the number of pfc enabled TCs
1572 * which have private buffer.
1573 */
1574 pfc_priv_num = hclge_get_pfc_priv_num(hdev);
1575
1576 /* let the last to be cleared first */
1577 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1578 priv = &hdev->priv_buf[i];
1579
1580 if (hdev->hw_tc_map & BIT(i) &&
1581 hdev->tm_info.hw_pfc_map & BIT(i)) {
1582 /* Reduce the number of pfc TC with private buffer */
1583 priv->wl.low = 0;
1584 priv->enable = 0;
1585 priv->wl.high = 0;
1586 priv->buf_size = 0;
1587 pfc_priv_num--;
1588 }
1589
1590 if (hclge_is_rx_buf_ok(hdev, rx_all) ||
1591 pfc_priv_num == 0)
1592 break;
1593 }
1594 if (hclge_is_rx_buf_ok(hdev, rx_all))
1595 return 0;
1596
1597 return -ENOMEM;
1598}
1599
1600static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev)
1601{
1602 struct hclge_rx_priv_buff *req;
1603 struct hclge_desc desc;
1604 int ret;
1605 int i;
1606
1607 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1608 req = (struct hclge_rx_priv_buff *)desc.data;
1609
1610 /* Alloc private buffer TCs */
1611 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1612 struct hclge_priv_buf *priv = &hdev->priv_buf[i];
1613
1614 req->buf_num[i] =
1615 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1616 req->buf_num[i] |=
1617 cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B);
1618 }
1619
1620 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1621 if (ret) {
1622 dev_err(&hdev->pdev->dev,
1623 "rx private buffer alloc cmd failed %d\n", ret);
1624 return ret;
1625 }
1626
1627 return 0;
1628}
1629
1630#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1631
1632static int hclge_rx_priv_wl_config(struct hclge_dev *hdev)
1633{
1634 struct hclge_rx_priv_wl_buf *req;
1635 struct hclge_priv_buf *priv;
1636 struct hclge_desc desc[2];
1637 int i, j;
1638 int ret;
1639
1640 for (i = 0; i < 2; i++) {
1641 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1642 false);
1643 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1644
1645 /* The first descriptor set the NEXT bit to 1 */
1646 if (i == 0)
1647 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1648 else
1649 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1650
1651 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1652 priv = &hdev->priv_buf[i * HCLGE_TC_NUM_ONE_DESC + j];
1653 req->tc_wl[j].high =
1654 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1655 req->tc_wl[j].high |=
1656 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1657 HCLGE_RX_PRIV_EN_B);
1658 req->tc_wl[j].low =
1659 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1660 req->tc_wl[j].low |=
1661 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1662 HCLGE_RX_PRIV_EN_B);
1663 }
1664 }
1665
1666 /* Send 2 descriptor at one time */
1667 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1668 if (ret) {
1669 dev_err(&hdev->pdev->dev,
1670 "rx private waterline config cmd failed %d\n",
1671 ret);
1672 return ret;
1673 }
1674 return 0;
1675}
1676
1677static int hclge_common_thrd_config(struct hclge_dev *hdev)
1678{
1679 struct hclge_shared_buf *s_buf = &hdev->s_buf;
1680 struct hclge_rx_com_thrd *req;
1681 struct hclge_desc desc[2];
1682 struct hclge_tc_thrd *tc;
1683 int i, j;
1684 int ret;
1685
1686 for (i = 0; i < 2; i++) {
1687 hclge_cmd_setup_basic_desc(&desc[i],
1688 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1689 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1690
1691 /* The first descriptor set the NEXT bit to 1 */
1692 if (i == 0)
1693 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1694 else
1695 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1696
1697 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1698 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1699
1700 req->com_thrd[j].high =
1701 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1702 req->com_thrd[j].high |=
1703 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1704 HCLGE_RX_PRIV_EN_B);
1705 req->com_thrd[j].low =
1706 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1707 req->com_thrd[j].low |=
1708 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1709 HCLGE_RX_PRIV_EN_B);
1710 }
1711 }
1712
1713 /* Send 2 descriptors at one time */
1714 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1715 if (ret) {
1716 dev_err(&hdev->pdev->dev,
1717 "common threshold config cmd failed %d\n", ret);
1718 return ret;
1719 }
1720 return 0;
1721}
1722
1723static int hclge_common_wl_config(struct hclge_dev *hdev)
1724{
1725 struct hclge_shared_buf *buf = &hdev->s_buf;
1726 struct hclge_rx_com_wl *req;
1727 struct hclge_desc desc;
1728 int ret;
1729
1730 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1731
1732 req = (struct hclge_rx_com_wl *)desc.data;
1733 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1734 req->com_wl.high |=
1735 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1736 HCLGE_RX_PRIV_EN_B);
1737
1738 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1739 req->com_wl.low |=
1740 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1741 HCLGE_RX_PRIV_EN_B);
1742
1743 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1744 if (ret) {
1745 dev_err(&hdev->pdev->dev,
1746 "common waterline config cmd failed %d\n", ret);
1747 return ret;
1748 }
1749
1750 return 0;
1751}
1752
1753int hclge_buffer_alloc(struct hclge_dev *hdev)
1754{
1755 u32 tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1756 int ret;
1757
1758 hdev->priv_buf = devm_kmalloc_array(&hdev->pdev->dev, HCLGE_MAX_TC_NUM,
1759 sizeof(struct hclge_priv_buf),
1760 GFP_KERNEL | __GFP_ZERO);
1761 if (!hdev->priv_buf)
1762 return -ENOMEM;
1763
1764 ret = hclge_tx_buffer_alloc(hdev, tx_buf_size);
1765 if (ret) {
1766 dev_err(&hdev->pdev->dev,
1767 "could not alloc tx buffers %d\n", ret);
1768 return ret;
1769 }
1770
1771 ret = hclge_rx_buffer_calc(hdev, tx_buf_size);
1772 if (ret) {
1773 dev_err(&hdev->pdev->dev,
1774 "could not calc rx priv buffer size for all TCs %d\n",
1775 ret);
1776 return ret;
1777 }
1778
1779 ret = hclge_rx_priv_buf_alloc(hdev);
1780 if (ret) {
1781 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1782 ret);
1783 return ret;
1784 }
1785
1786 ret = hclge_rx_priv_wl_config(hdev);
1787 if (ret) {
1788 dev_err(&hdev->pdev->dev,
1789 "could not configure rx private waterline %d\n", ret);
1790 return ret;
1791 }
1792
1793 ret = hclge_common_thrd_config(hdev);
1794 if (ret) {
1795 dev_err(&hdev->pdev->dev,
1796 "could not configure common threshold %d\n", ret);
1797 return ret;
1798 }
1799
1800 ret = hclge_common_wl_config(hdev);
1801 if (ret) {
1802 dev_err(&hdev->pdev->dev,
1803 "could not configure common waterline %d\n", ret);
1804 return ret;
1805 }
1806
1807 return 0;
1808}
1809
1810static int hclge_init_roce_base_info(struct hclge_vport *vport)
1811{
1812 struct hnae3_handle *roce = &vport->roce;
1813 struct hnae3_handle *nic = &vport->nic;
1814
1815 roce->rinfo.num_vectors = vport->back->num_roce_msix;
1816
1817 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1818 vport->back->num_msi_left == 0)
1819 return -EINVAL;
1820
1821 roce->rinfo.base_vector = vport->back->roce_base_vector;
1822
1823 roce->rinfo.netdev = nic->kinfo.netdev;
1824 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1825
1826 roce->pdev = nic->pdev;
1827 roce->ae_algo = nic->ae_algo;
1828 roce->numa_node_mask = nic->numa_node_mask;
1829
1830 return 0;
1831}
1832
1833static int hclge_init_msix(struct hclge_dev *hdev)
1834{
1835 struct pci_dev *pdev = hdev->pdev;
1836 int ret, i;
1837
1838 hdev->msix_entries = devm_kcalloc(&pdev->dev, hdev->num_msi,
1839 sizeof(struct msix_entry),
1840 GFP_KERNEL);
1841 if (!hdev->msix_entries)
1842 return -ENOMEM;
1843
1844 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1845 sizeof(u16), GFP_KERNEL);
1846 if (!hdev->vector_status)
1847 return -ENOMEM;
1848
1849 for (i = 0; i < hdev->num_msi; i++) {
1850 hdev->msix_entries[i].entry = i;
1851 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1852 }
1853
1854 hdev->num_msi_left = hdev->num_msi;
1855 hdev->base_msi_vector = hdev->pdev->irq;
1856 hdev->roce_base_vector = hdev->base_msi_vector +
1857 HCLGE_ROCE_VECTOR_OFFSET;
1858
1859 ret = pci_enable_msix_range(hdev->pdev, hdev->msix_entries,
1860 hdev->num_msi, hdev->num_msi);
1861 if (ret < 0) {
1862 dev_info(&hdev->pdev->dev,
1863 "MSI-X vector alloc failed: %d\n", ret);
1864 return ret;
1865 }
1866
1867 return 0;
1868}
1869
1870static int hclge_init_msi(struct hclge_dev *hdev)
1871{
1872 struct pci_dev *pdev = hdev->pdev;
1873 int vectors;
1874 int i;
1875
1876 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1877 sizeof(u16), GFP_KERNEL);
1878 if (!hdev->vector_status)
1879 return -ENOMEM;
1880
1881 for (i = 0; i < hdev->num_msi; i++)
1882 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1883
1884 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, PCI_IRQ_MSI);
1885 if (vectors < 0) {
1886 dev_err(&pdev->dev, "MSI vectors enable failed %d\n", vectors);
1887 return -EINVAL;
1888 }
1889 hdev->num_msi = vectors;
1890 hdev->num_msi_left = vectors;
1891 hdev->base_msi_vector = pdev->irq;
1892 hdev->roce_base_vector = hdev->base_msi_vector +
1893 HCLGE_ROCE_VECTOR_OFFSET;
1894
1895 return 0;
1896}
1897
1898static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
1899{
1900 struct hclge_mac *mac = &hdev->hw.mac;
1901
1902 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
1903 mac->duplex = (u8)duplex;
1904 else
1905 mac->duplex = HCLGE_MAC_FULL;
1906
1907 mac->speed = speed;
1908}
1909
1910int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1911{
1912 struct hclge_config_mac_speed_dup *req;
1913 struct hclge_desc desc;
1914 int ret;
1915
1916 req = (struct hclge_config_mac_speed_dup *)desc.data;
1917
1918 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1919
1920 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
1921
1922 switch (speed) {
1923 case HCLGE_MAC_SPEED_10M:
1924 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1925 HCLGE_CFG_SPEED_S, 6);
1926 break;
1927 case HCLGE_MAC_SPEED_100M:
1928 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1929 HCLGE_CFG_SPEED_S, 7);
1930 break;
1931 case HCLGE_MAC_SPEED_1G:
1932 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1933 HCLGE_CFG_SPEED_S, 0);
1934 break;
1935 case HCLGE_MAC_SPEED_10G:
1936 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1937 HCLGE_CFG_SPEED_S, 1);
1938 break;
1939 case HCLGE_MAC_SPEED_25G:
1940 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1941 HCLGE_CFG_SPEED_S, 2);
1942 break;
1943 case HCLGE_MAC_SPEED_40G:
1944 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1945 HCLGE_CFG_SPEED_S, 3);
1946 break;
1947 case HCLGE_MAC_SPEED_50G:
1948 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1949 HCLGE_CFG_SPEED_S, 4);
1950 break;
1951 case HCLGE_MAC_SPEED_100G:
1952 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1953 HCLGE_CFG_SPEED_S, 5);
1954 break;
1955 default:
d7629e74 1956 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 1957 return -EINVAL;
1958 }
1959
1960 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1961 1);
1962
1963 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1964 if (ret) {
1965 dev_err(&hdev->pdev->dev,
1966 "mac speed/duplex config cmd failed %d.\n", ret);
1967 return ret;
1968 }
1969
1970 hclge_check_speed_dup(hdev, duplex, speed);
1971
1972 return 0;
1973}
1974
1975static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1976 u8 duplex)
1977{
1978 struct hclge_vport *vport = hclge_get_vport(handle);
1979 struct hclge_dev *hdev = vport->back;
1980
1981 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1982}
1983
1984static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1985 u8 *duplex)
1986{
1987 struct hclge_query_an_speed_dup *req;
1988 struct hclge_desc desc;
1989 int speed_tmp;
1990 int ret;
1991
1992 req = (struct hclge_query_an_speed_dup *)desc.data;
1993
1994 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1995 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1996 if (ret) {
1997 dev_err(&hdev->pdev->dev,
1998 "mac speed/autoneg/duplex query cmd failed %d\n",
1999 ret);
2000 return ret;
2001 }
2002
2003 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2004 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2005 HCLGE_QUERY_SPEED_S);
2006
2007 ret = hclge_parse_speed(speed_tmp, speed);
2008 if (ret) {
2009 dev_err(&hdev->pdev->dev,
2010 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2011 return -EIO;
2012 }
2013
2014 return 0;
2015}
2016
2017static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2018{
2019 struct hclge_mac *mac = &hdev->hw.mac;
2020 struct hclge_query_an_speed_dup *req;
2021 struct hclge_desc desc;
2022 int ret;
2023
2024 req = (struct hclge_query_an_speed_dup *)desc.data;
2025
2026 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2027 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2028 if (ret) {
2029 dev_err(&hdev->pdev->dev,
2030 "autoneg result query cmd failed %d.\n", ret);
2031 return ret;
2032 }
2033
2034 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2035
2036 return 0;
2037}
2038
2039static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2040{
2041 struct hclge_config_auto_neg *req;
2042 struct hclge_desc desc;
2043 int ret;
2044
2045 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2046
2047 req = (struct hclge_config_auto_neg *)desc.data;
2048 hnae_set_bit(req->cfg_an_cmd_flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2049
2050 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2051 if (ret) {
2052 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2053 ret);
2054 return ret;
2055 }
2056
2057 return 0;
2058}
2059
2060static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2061{
2062 struct hclge_vport *vport = hclge_get_vport(handle);
2063 struct hclge_dev *hdev = vport->back;
2064
2065 return hclge_set_autoneg_en(hdev, enable);
2066}
2067
2068static int hclge_get_autoneg(struct hnae3_handle *handle)
2069{
2070 struct hclge_vport *vport = hclge_get_vport(handle);
2071 struct hclge_dev *hdev = vport->back;
2072
2073 hclge_query_autoneg_result(hdev);
2074
2075 return hdev->hw.mac.autoneg;
2076}
2077
2078static int hclge_mac_init(struct hclge_dev *hdev)
2079{
2080 struct hclge_mac *mac = &hdev->hw.mac;
2081 int ret;
2082
2083 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2084 if (ret) {
2085 dev_err(&hdev->pdev->dev,
2086 "Config mac speed dup fail ret=%d\n", ret);
2087 return ret;
2088 }
2089
2090 mac->link = 0;
2091
2092 ret = hclge_mac_mdio_config(hdev);
2093 if (ret) {
2094 dev_warn(&hdev->pdev->dev,
2095 "mdio config fail ret=%d\n", ret);
2096 return ret;
2097 }
2098
2099 /* Initialize the MTA table work mode */
2100 hdev->accept_mta_mc = true;
2101 hdev->enable_mta = true;
2102 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2103
2104 ret = hclge_set_mta_filter_mode(hdev,
2105 hdev->mta_mac_sel_type,
2106 hdev->enable_mta);
2107 if (ret) {
2108 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2109 ret);
2110 return ret;
2111 }
2112
2113 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2114}
2115
2116static void hclge_task_schedule(struct hclge_dev *hdev)
2117{
2118 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2119 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2120 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2121 (void)schedule_work(&hdev->service_task);
2122}
2123
2124static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2125{
2126 struct hclge_link_status *req;
2127 struct hclge_desc desc;
2128 int link_status;
2129 int ret;
2130
2131 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2132 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2133 if (ret) {
2134 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2135 ret);
2136 return ret;
2137 }
2138
2139 req = (struct hclge_link_status *)desc.data;
2140 link_status = req->status & HCLGE_LINK_STATUS;
2141
2142 return !!link_status;
2143}
2144
2145static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2146{
2147 int mac_state;
2148 int link_stat;
2149
2150 mac_state = hclge_get_mac_link_status(hdev);
2151
2152 if (hdev->hw.mac.phydev) {
2153 if (!genphy_read_status(hdev->hw.mac.phydev))
2154 link_stat = mac_state &
2155 hdev->hw.mac.phydev->link;
2156 else
2157 link_stat = 0;
2158
2159 } else {
2160 link_stat = mac_state;
2161 }
2162
2163 return !!link_stat;
2164}
2165
2166static void hclge_update_link_status(struct hclge_dev *hdev)
2167{
2168 struct hnae3_client *client = hdev->nic_client;
2169 struct hnae3_handle *handle;
2170 int state;
2171 int i;
2172
2173 if (!client)
2174 return;
2175 state = hclge_get_mac_phy_link(hdev);
2176 if (state != hdev->hw.mac.link) {
2177 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2178 handle = &hdev->vport[i].nic;
2179 client->ops->link_status_change(handle, state);
2180 }
2181 hdev->hw.mac.link = state;
2182 }
2183}
2184
2185static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2186{
2187 struct hclge_mac mac = hdev->hw.mac;
2188 u8 duplex;
2189 int speed;
2190 int ret;
2191
2192 /* get the speed and duplex as autoneg'result from mac cmd when phy
2193 * doesn't exit.
2194 */
2195 if (mac.phydev)
2196 return 0;
2197
2198 /* update mac->antoneg. */
2199 ret = hclge_query_autoneg_result(hdev);
2200 if (ret) {
2201 dev_err(&hdev->pdev->dev,
2202 "autoneg result query failed %d\n", ret);
2203 return ret;
2204 }
2205
2206 if (!mac.autoneg)
2207 return 0;
2208
2209 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2210 if (ret) {
2211 dev_err(&hdev->pdev->dev,
2212 "mac autoneg/speed/duplex query failed %d\n", ret);
2213 return ret;
2214 }
2215
2216 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2217 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2218 if (ret) {
2219 dev_err(&hdev->pdev->dev,
2220 "mac speed/duplex config failed %d\n", ret);
2221 return ret;
2222 }
2223 }
2224
2225 return 0;
2226}
2227
2228static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2229{
2230 struct hclge_vport *vport = hclge_get_vport(handle);
2231 struct hclge_dev *hdev = vport->back;
2232
2233 return hclge_update_speed_duplex(hdev);
2234}
2235
2236static int hclge_get_status(struct hnae3_handle *handle)
2237{
2238 struct hclge_vport *vport = hclge_get_vport(handle);
2239 struct hclge_dev *hdev = vport->back;
2240
2241 hclge_update_link_status(hdev);
2242
2243 return hdev->hw.mac.link;
2244}
2245
2246static void hclge_service_timer(unsigned long data)
2247{
2248 struct hclge_dev *hdev = (struct hclge_dev *)data;
2249 (void)mod_timer(&hdev->service_timer, jiffies + HZ);
2250
2251 hclge_task_schedule(hdev);
2252}
2253
2254static void hclge_service_complete(struct hclge_dev *hdev)
2255{
2256 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2257
2258 /* Flush memory before next watchdog */
2259 smp_mb__before_atomic();
2260 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2261}
2262
2263static void hclge_service_task(struct work_struct *work)
2264{
2265 struct hclge_dev *hdev =
2266 container_of(work, struct hclge_dev, service_task);
2267
2268 hclge_update_speed_duplex(hdev);
2269 hclge_update_link_status(hdev);
2270 hclge_update_stats_for_all(hdev);
2271 hclge_service_complete(hdev);
2272}
2273
2274static void hclge_disable_sriov(struct hclge_dev *hdev)
2275{
2a32ca13
AB		 2276 /* If our VFs are assigned we cannot shut down SR-IOV
2277 * without causing issues, so just leave the hardware
2278 * available but disabled
2279 */
2280 if (pci_vfs_assigned(hdev->pdev)) {
2281 dev_warn(&hdev->pdev->dev,
2282 "disabling driver while VFs are assigned\n");
2283 return;
2284 }
46a3df9f 2285
2a32ca13 2286 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2287}
2288
2289struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2290{
2291 /* VF handle has no client */
2292 if (!handle->client)
2293 return container_of(handle, struct hclge_vport, nic);
2294 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2295 return container_of(handle, struct hclge_vport, roce);
2296 else
2297 return container_of(handle, struct hclge_vport, nic);
2298}
2299
2300static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2301 struct hnae3_vector_info *vector_info)
2302{
2303 struct hclge_vport *vport = hclge_get_vport(handle);
2304 struct hnae3_vector_info *vector = vector_info;
2305 struct hclge_dev *hdev = vport->back;
2306 int alloc = 0;
2307 int i, j;
2308
2309 vector_num = min(hdev->num_msi_left, vector_num);
2310
2311 for (j = 0; j < vector_num; j++) {
2312 for (i = 1; i < hdev->num_msi; i++) {
2313 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2314 vector->vector = pci_irq_vector(hdev->pdev, i);
2315 vector->io_addr = hdev->hw.io_base +
2316 HCLGE_VECTOR_REG_BASE +
2317 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2318 vport->vport_id *
2319 HCLGE_VECTOR_VF_OFFSET;
2320 hdev->vector_status[i] = vport->vport_id;
2321
2322 vector++;
2323 alloc++;
2324
2325 break;
2326 }
2327 }
2328 }
2329 hdev->num_msi_left -= alloc;
2330 hdev->num_msi_used += alloc;
2331
2332 return alloc;
2333}
2334
2335static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2336{
2337 int i;
2338
2339 for (i = 0; i < hdev->num_msi; i++) {
2340 if (hdev->msix_entries) {
2341 if (vector == hdev->msix_entries[i].vector)
2342 return i;
2343 } else {
2344 if (vector == (hdev->base_msi_vector + i))
2345 return i;
2346 }
2347 }
2348 return -EINVAL;
2349}
2350
2351static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2352{
2353 return HCLGE_RSS_KEY_SIZE;
2354}
2355
2356static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2357{
2358 return HCLGE_RSS_IND_TBL_SIZE;
2359}
2360
2361static int hclge_get_rss_algo(struct hclge_dev *hdev)
2362{
2363 struct hclge_rss_config *req;
2364 struct hclge_desc desc;
2365 int rss_hash_algo;
2366 int ret;
2367
2368 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2369
2370 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2371 if (ret) {
2372 dev_err(&hdev->pdev->dev,
2373 "Get link status error, status =%d\n", ret);
2374 return ret;
2375 }
2376
2377 req = (struct hclge_rss_config *)desc.data;
2378 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2379
2380 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2381 return ETH_RSS_HASH_TOP;
2382
2383 return -EINVAL;
2384}
2385
2386static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2387 const u8 hfunc, const u8 *key)
2388{
2389 struct hclge_rss_config *req;
2390 struct hclge_desc desc;
2391 int key_offset;
2392 int key_size;
2393 int ret;
2394
2395 req = (struct hclge_rss_config *)desc.data;
2396
2397 for (key_offset = 0; key_offset < 3; key_offset++) {
2398 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2399 false);
2400
2401 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2402 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2403
2404 if (key_offset == 2)
2405 key_size =
2406 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2407 else
2408 key_size = HCLGE_RSS_HASH_KEY_NUM;
2409
2410 memcpy(req->hash_key,
2411 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2412
2413 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2414 if (ret) {
2415 dev_err(&hdev->pdev->dev,
2416 "Configure RSS config fail, status = %d\n",
2417 ret);
2418 return ret;
2419 }
2420 }
2421 return 0;
2422}
2423
2424static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2425{
2426 struct hclge_rss_indirection_table *req;
2427 struct hclge_desc desc;
2428 int i, j;
2429 int ret;
2430
2431 req = (struct hclge_rss_indirection_table *)desc.data;
2432
2433 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2434 hclge_cmd_setup_basic_desc
2435 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2436
2437 req->start_table_index = i * HCLGE_RSS_CFG_TBL_SIZE;
2438 req->rss_set_bitmap = HCLGE_RSS_SET_BITMAP_MSK;
2439
2440 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2441 req->rss_result[j] =
2442 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2443
2444 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2445 if (ret) {
2446 dev_err(&hdev->pdev->dev,
2447 "Configure rss indir table fail,status = %d\n",
2448 ret);
2449 return ret;
2450 }
2451 }
2452 return 0;
2453}
2454
2455static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2456 u16 *tc_size, u16 *tc_offset)
2457{
2458 struct hclge_rss_tc_mode *req;
2459 struct hclge_desc desc;
2460 int ret;
2461 int i;
2462
2463 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
2464 req = (struct hclge_rss_tc_mode *)desc.data;
2465
2466 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2467 hnae_set_bit(req->rss_tc_mode[i], HCLGE_RSS_TC_VALID_B,
2468 (tc_valid[i] & 0x1));
2469 hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_SIZE_M,
2470 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2471 hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_OFFSET_M,
2472 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
2473 }
2474
2475 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2476 if (ret) {
2477 dev_err(&hdev->pdev->dev,
2478 "Configure rss tc mode fail, status = %d\n", ret);
2479 return ret;
2480 }
2481
2482 return 0;
2483}
2484
2485static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2486{
2487#define HCLGE_RSS_INPUT_TUPLE_OTHER 0xf
2488#define HCLGE_RSS_INPUT_TUPLE_SCTP 0x1f
2489 struct hclge_rss_input_tuple *req;
2490 struct hclge_desc desc;
2491 int ret;
2492
2493 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2494
2495 req = (struct hclge_rss_input_tuple *)desc.data;
2496 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2497 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2498 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2499 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2500 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2501 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2502 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2503 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2504 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2505 if (ret) {
2506 dev_err(&hdev->pdev->dev,
2507 "Configure rss input fail, status = %d\n", ret);
2508 return ret;
2509 }
2510
2511 return 0;
2512}
2513
2514static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2515 u8 *key, u8 *hfunc)
2516{
2517 struct hclge_vport *vport = hclge_get_vport(handle);
2518 struct hclge_dev *hdev = vport->back;
2519 int i;
2520
2521 /* Get hash algorithm */
2522 if (hfunc)
2523 *hfunc = hclge_get_rss_algo(hdev);
2524
2525 /* Get the RSS Key required by the user */
2526 if (key)
2527 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2528
2529 /* Get indirect table */
2530 if (indir)
2531 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2532 indir[i] = vport->rss_indirection_tbl[i];
2533
2534 return 0;
2535}
2536
2537static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2538 const u8 *key, const u8 hfunc)
2539{
2540 struct hclge_vport *vport = hclge_get_vport(handle);
2541 struct hclge_dev *hdev = vport->back;
2542 u8 hash_algo;
2543 int ret, i;
2544
2545 /* Set the RSS Hash Key if specififed by the user */
2546 if (key) {
2547 /* Update the shadow RSS key with user specified qids */
2548 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2549
2550 if (hfunc == ETH_RSS_HASH_TOP ||
2551 hfunc == ETH_RSS_HASH_NO_CHANGE)
2552 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2553 else
2554 return -EINVAL;
2555 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2556 if (ret)
2557 return ret;
2558 }
2559
2560 /* Update the shadow RSS table with user specified qids */
2561 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2562 vport->rss_indirection_tbl[i] = indir[i];
2563
2564 /* Update the hardware */
2565 ret = hclge_set_rss_indir_table(hdev, indir);
2566 return ret;
2567}
2568
2569static int hclge_get_tc_size(struct hnae3_handle *handle)
2570{
2571 struct hclge_vport *vport = hclge_get_vport(handle);
2572 struct hclge_dev *hdev = vport->back;
2573
2574 return hdev->rss_size_max;
2575}
2576
2577static int hclge_rss_init_hw(struct hclge_dev *hdev)
2578{
2579 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2580 struct hclge_vport *vport = hdev->vport;
2581 u16 tc_offset[HCLGE_MAX_TC_NUM];
2582 u8 rss_key[HCLGE_RSS_KEY_SIZE];
2583 u16 tc_valid[HCLGE_MAX_TC_NUM];
2584 u16 tc_size[HCLGE_MAX_TC_NUM];
2585 u32 *rss_indir = NULL;
2586 const u8 *key;
2587 int i, ret, j;
2588
2589 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
2590 if (!rss_indir)
2591 return -ENOMEM;
2592
2593 /* Get default RSS key */
2594 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
2595
2596 /* Initialize RSS indirect table for each vport */
2597 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
2598 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
2599 vport[j].rss_indirection_tbl[i] =
2600 i % hdev->rss_size_max;
2601 rss_indir[i] = vport[j].rss_indirection_tbl[i];
2602 }
2603 }
2604 ret = hclge_set_rss_indir_table(hdev, rss_indir);
2605 if (ret)
2606 goto err;
2607
2608 key = rss_key;
2609 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
2610 if (ret)
2611 goto err;
2612
2613 ret = hclge_set_rss_input_tuple(hdev);
2614 if (ret)
2615 goto err;
2616
2617 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2618 if (hdev->hw_tc_map & BIT(i))
2619 tc_valid[i] = 1;
2620 else
2621 tc_valid[i] = 0;
2622
2623 switch (hdev->rss_size_max) {
2624 case HCLGE_RSS_TC_SIZE_0:
2625 tc_size[i] = 0;
2626 break;
2627 case HCLGE_RSS_TC_SIZE_1:
2628 tc_size[i] = 1;
2629 break;
2630 case HCLGE_RSS_TC_SIZE_2:
2631 tc_size[i] = 2;
2632 break;
2633 case HCLGE_RSS_TC_SIZE_3:
2634 tc_size[i] = 3;
2635 break;
2636 case HCLGE_RSS_TC_SIZE_4:
2637 tc_size[i] = 4;
2638 break;
2639 case HCLGE_RSS_TC_SIZE_5:
2640 tc_size[i] = 5;
2641 break;
2642 case HCLGE_RSS_TC_SIZE_6:
2643 tc_size[i] = 6;
2644 break;
2645 case HCLGE_RSS_TC_SIZE_7:
2646 tc_size[i] = 7;
2647 break;
2648 default:
2649 break;
2650 }
2651 tc_offset[i] = hdev->rss_size_max * i;
2652 }
2653 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
2654
2655err:
2656 kfree(rss_indir);
2657
2658 return ret;
2659}
2660
2661int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
2662 struct hnae3_ring_chain_node *ring_chain)
2663{
2664 struct hclge_dev *hdev = vport->back;
2665 struct hclge_ctrl_vector_chain *req;
2666 struct hnae3_ring_chain_node *node;
2667 struct hclge_desc desc;
2668 int ret;
2669 int i;
2670
2671 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
2672
2673 req = (struct hclge_ctrl_vector_chain *)desc.data;
2674 req->int_vector_id = vector_id;
2675
2676 i = 0;
2677 for (node = ring_chain; node; node = node->next) {
2678 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,
2679 HCLGE_INT_TYPE_S,
2680 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2681 hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2682 HCLGE_TQP_ID_S, node->tqp_index);
0305b443
L		 2683 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
2684 HCLGE_INT_GL_IDX_S,
2685 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f 2686 req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
0305b443 2687 req->vfid = vport->vport_id;
46a3df9f
S		 2688
2689 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2690 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
2691
2692 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2693 if (ret) {
2694 dev_err(&hdev->pdev->dev,
2695 "Map TQP fail, status is %d.\n",
2696 ret);
2697 return ret;
2698 }
2699 i = 0;
2700
2701 hclge_cmd_setup_basic_desc(&desc,
2702 HCLGE_OPC_ADD_RING_TO_VECTOR,
2703 false);
2704 req->int_vector_id = vector_id;
2705 }
2706 }
2707
2708 if (i > 0) {
2709 req->int_cause_num = i;
2710
2711 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2712 if (ret) {
2713 dev_err(&hdev->pdev->dev,
2714 "Map TQP fail, status is %d.\n", ret);
2715 return ret;
2716 }
2717 }
2718
2719 return 0;
2720}
2721
2722int hclge_map_handle_ring_to_vector(struct hnae3_handle *handle,
2723 int vector,
2724 struct hnae3_ring_chain_node *ring_chain)
2725{
2726 struct hclge_vport *vport = hclge_get_vport(handle);
2727 struct hclge_dev *hdev = vport->back;
2728 int vector_id;
2729
2730 vector_id = hclge_get_vector_index(hdev, vector);
2731 if (vector_id < 0) {
2732 dev_err(&hdev->pdev->dev,
2733 "Get vector index fail. ret =%d\n", vector_id);
2734 return vector_id;
2735 }
2736
2737 return hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);
2738}
2739
2740static int hclge_unmap_ring_from_vector(
2741 struct hnae3_handle *handle, int vector,
2742 struct hnae3_ring_chain_node *ring_chain)
2743{
2744 struct hclge_vport *vport = hclge_get_vport(handle);
2745 struct hclge_dev *hdev = vport->back;
2746 struct hclge_ctrl_vector_chain *req;
2747 struct hnae3_ring_chain_node *node;
2748 struct hclge_desc desc;
2749 int i, vector_id;
2750 int ret;
2751
2752 vector_id = hclge_get_vector_index(hdev, vector);
2753 if (vector_id < 0) {
2754 dev_err(&handle->pdev->dev,
2755 "Get vector index fail. ret =%d\n", vector_id);
2756 return vector_id;
2757 }
2758
2759 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);
2760
2761 req = (struct hclge_ctrl_vector_chain *)desc.data;
2762 req->int_vector_id = vector_id;
2763
2764 i = 0;
2765 for (node = ring_chain; node; node = node->next) {
2766 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,
2767 HCLGE_INT_TYPE_S,
2768 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2769 hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2770 HCLGE_TQP_ID_S, node->tqp_index);
0305b443
L		 2771 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
2772 HCLGE_INT_GL_IDX_S,
2773 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f
S		 2774
2775 req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
0305b443 2776 req->vfid = vport->vport_id;
46a3df9f
S		 2777
2778 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2779 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
2780
2781 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2782 if (ret) {
2783 dev_err(&hdev->pdev->dev,
2784 "Unmap TQP fail, status is %d.\n",
2785 ret);
2786 return ret;
2787 }
2788 i = 0;
2789 hclge_cmd_setup_basic_desc(&desc,
c5b1b975 2790 HCLGE_OPC_DEL_RING_TO_VECTOR,
46a3df9f
S		 2791 false);
2792 req->int_vector_id = vector_id;
2793 }
2794 }
2795
2796 if (i > 0) {
2797 req->int_cause_num = i;
2798
2799 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2800 if (ret) {
2801 dev_err(&hdev->pdev->dev,
2802 "Unmap TQP fail, status is %d.\n", ret);
2803 return ret;
2804 }
2805 }
2806
2807 return 0;
2808}
2809
2810int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
2811 struct hclge_promisc_param *param)
2812{
2813 struct hclge_promisc_cfg *req;
2814 struct hclge_desc desc;
2815 int ret;
2816
2817 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
2818
2819 req = (struct hclge_promisc_cfg *)desc.data;
2820 req->vf_id = param->vf_id;
2821 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
2822
2823 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2824 if (ret) {
2825 dev_err(&hdev->pdev->dev,
2826 "Set promisc mode fail, status is %d.\n", ret);
2827 return ret;
2828 }
2829 return 0;
2830}
2831
2832void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
2833 bool en_mc, bool en_bc, int vport_id)
2834{
2835 if (!param)
2836 return;
2837
2838 memset(param, 0, sizeof(struct hclge_promisc_param));
2839 if (en_uc)
2840 param->enable = HCLGE_PROMISC_EN_UC;
2841 if (en_mc)
2842 param->enable |= HCLGE_PROMISC_EN_MC;
2843 if (en_bc)
2844 param->enable |= HCLGE_PROMISC_EN_BC;
2845 param->vf_id = vport_id;
2846}
2847
2848static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
2849{
2850 struct hclge_vport *vport = hclge_get_vport(handle);
2851 struct hclge_dev *hdev = vport->back;
2852 struct hclge_promisc_param param;
2853
2854 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
2855 hclge_cmd_set_promisc_mode(hdev, &param);
2856}
2857
2858static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
2859{
2860 struct hclge_desc desc;
2861 struct hclge_config_mac_mode *req =
2862 (struct hclge_config_mac_mode *)desc.data;
2863 int ret;
2864
2865 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
2866 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_TX_EN_B, enable);
2867 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_RX_EN_B, enable);
2868 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_PAD_TX_B, enable);
2869 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_PAD_RX_B, enable);
2870 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_1588_TX_B, 0);
2871 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_1588_RX_B, 0);
2872 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_APP_LP_B, 0);
2873 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_LINE_LP_B, 0);
2874 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_FCS_TX_B, enable);
2875 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_RX_FCS_B, enable);
2876 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2877 HCLGE_MAC_RX_FCS_STRIP_B, enable);
2878 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2879 HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
2880 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2881 HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
2882 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2883 HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
2884
2885 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2886 if (ret)
2887 dev_err(&hdev->pdev->dev,
2888 "mac enable fail, ret =%d.\n", ret);
2889}
2890
2891static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
2892 int stream_id, bool enable)
2893{
2894 struct hclge_desc desc;
2895 struct hclge_cfg_com_tqp_queue *req =
2896 (struct hclge_cfg_com_tqp_queue *)desc.data;
2897 int ret;
2898
2899 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
2900 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
2901 req->stream_id = cpu_to_le16(stream_id);
2902 req->enable |= enable << HCLGE_TQP_ENABLE_B;
2903
2904 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2905 if (ret)
2906 dev_err(&hdev->pdev->dev,
2907 "Tqp enable fail, status =%d.\n", ret);
2908 return ret;
2909}
2910
2911static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
2912{
2913 struct hclge_vport *vport = hclge_get_vport(handle);
2914 struct hnae3_queue *queue;
2915 struct hclge_tqp *tqp;
2916 int i;
2917
2918 for (i = 0; i < vport->alloc_tqps; i++) {
2919 queue = handle->kinfo.tqp[i];
2920 tqp = container_of(queue, struct hclge_tqp, q);
2921 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
2922 }
2923}
2924
2925static int hclge_ae_start(struct hnae3_handle *handle)
2926{
2927 struct hclge_vport *vport = hclge_get_vport(handle);
2928 struct hclge_dev *hdev = vport->back;
2929 int i, queue_id, ret;
2930
2931 for (i = 0; i < vport->alloc_tqps; i++) {
2932 /* todo clear interrupt */
2933 /* ring enable */
2934 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
2935 if (queue_id < 0) {
2936 dev_warn(&hdev->pdev->dev,
2937 "Get invalid queue id, ignore it\n");
2938 continue;
2939 }
2940
2941 hclge_tqp_enable(hdev, queue_id, 0, true);
2942 }
2943 /* mac enable */
2944 hclge_cfg_mac_mode(hdev, true);
2945 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
2946 (void)mod_timer(&hdev->service_timer, jiffies + HZ);
2947
2948 ret = hclge_mac_start_phy(hdev);
2949 if (ret)
2950 return ret;
2951
2952 /* reset tqp stats */
2953 hclge_reset_tqp_stats(handle);
2954
2955 return 0;
2956}
2957
2958static void hclge_ae_stop(struct hnae3_handle *handle)
2959{
2960 struct hclge_vport *vport = hclge_get_vport(handle);
2961 struct hclge_dev *hdev = vport->back;
2962 int i, queue_id;
2963
2964 for (i = 0; i < vport->alloc_tqps; i++) {
2965 /* Ring disable */
2966 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
2967 if (queue_id < 0) {
2968 dev_warn(&hdev->pdev->dev,
2969 "Get invalid queue id, ignore it\n");
2970 continue;
2971 }
2972
2973 hclge_tqp_enable(hdev, queue_id, 0, false);
2974 }
2975 /* Mac disable */
2976 hclge_cfg_mac_mode(hdev, false);
2977
2978 hclge_mac_stop_phy(hdev);
2979
2980 /* reset tqp stats */
2981 hclge_reset_tqp_stats(handle);
2982}
2983
2984static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
2985 u16 cmdq_resp, u8 resp_code,
2986 enum hclge_mac_vlan_tbl_opcode op)
2987{
2988 struct hclge_dev *hdev = vport->back;
2989 int return_status = -EIO;
2990
2991 if (cmdq_resp) {
2992 dev_err(&hdev->pdev->dev,
2993 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
2994 cmdq_resp);
2995 return -EIO;
2996 }
2997
2998 if (op == HCLGE_MAC_VLAN_ADD) {
2999 if ((!resp_code) || (resp_code == 1)) {
3000 return_status = 0;
3001 } else if (resp_code == 2) {
3002 return_status = -EIO;
3003 dev_err(&hdev->pdev->dev,
3004 "add mac addr failed for uc_overflow.\n");
3005 } else if (resp_code == 3) {
3006 return_status = -EIO;
3007 dev_err(&hdev->pdev->dev,
3008 "add mac addr failed for mc_overflow.\n");
3009 } else {
3010 dev_err(&hdev->pdev->dev,
3011 "add mac addr failed for undefined, code=%d.\n",
3012 resp_code);
3013 }
3014 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3015 if (!resp_code) {
3016 return_status = 0;
3017 } else if (resp_code == 1) {
3018 return_status = -EIO;
3019 dev_dbg(&hdev->pdev->dev,
3020 "remove mac addr failed for miss.\n");
3021 } else {
3022 dev_err(&hdev->pdev->dev,
3023 "remove mac addr failed for undefined, code=%d.\n",
3024 resp_code);
3025 }
3026 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3027 if (!resp_code) {
3028 return_status = 0;
3029 } else if (resp_code == 1) {
3030 return_status = -EIO;
3031 dev_dbg(&hdev->pdev->dev,
3032 "lookup mac addr failed for miss.\n");
3033 } else {
3034 dev_err(&hdev->pdev->dev,
3035 "lookup mac addr failed for undefined, code=%d.\n",
3036 resp_code);
3037 }
3038 } else {
3039 return_status = -EIO;
3040 dev_err(&hdev->pdev->dev,
3041 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3042 op);
3043 }
3044
3045 return return_status;
3046}
3047
3048static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3049{
3050 int word_num;
3051 int bit_num;
3052
3053 if (vfid > 255 || vfid < 0)
3054 return -EIO;
3055
3056 if (vfid >= 0 && vfid <= 191) {
3057 word_num = vfid / 32;
3058 bit_num = vfid % 32;
3059 if (clr)
3060 desc[1].data[word_num] &= ~(1 << bit_num);
3061 else
3062 desc[1].data[word_num] |= (1 << bit_num);
3063 } else {
3064 word_num = (vfid - 192) / 32;
3065 bit_num = vfid % 32;
3066 if (clr)
3067 desc[2].data[word_num] &= ~(1 << bit_num);
3068 else
3069 desc[2].data[word_num] |= (1 << bit_num);
3070 }
3071
3072 return 0;
3073}
3074
3075static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3076{
3077#define HCLGE_DESC_NUMBER 3
3078#define HCLGE_FUNC_NUMBER_PER_DESC 6
3079 int i, j;
3080
3081 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3082 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3083 if (desc[i].data[j])
3084 return false;
3085
3086 return true;
3087}
3088
3089static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry *new_req,
3090 const u8 *addr)
3091{
3092 const unsigned char *mac_addr = addr;
3093 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3094 (mac_addr[0]) | (mac_addr[1] << 8);
3095 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3096
3097 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3098 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3099}
3100
3101u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3102 const u8 *addr)
3103{
3104 u16 high_val = addr[1] | (addr[0] << 8);
3105 struct hclge_dev *hdev = vport->back;
3106 u32 rsh = 4 - hdev->mta_mac_sel_type;
3107 u16 ret_val = (high_val >> rsh) & 0xfff;
3108
3109 return ret_val;
3110}
3111
3112static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3113 enum hclge_mta_dmac_sel_type mta_mac_sel,
3114 bool enable)
3115{
3116 struct hclge_mta_filter_mode *req;
3117 struct hclge_desc desc;
3118 int ret;
3119
3120 req = (struct hclge_mta_filter_mode *)desc.data;
3121 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3122
3123 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3124 enable);
3125 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3126 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3127
3128 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3129 if (ret) {
3130 dev_err(&hdev->pdev->dev,
3131 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3132 ret);
3133 return ret;
3134 }
3135
3136 return 0;
3137}
3138
3139int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3140 u8 func_id,
3141 bool enable)
3142{
3143 struct hclge_cfg_func_mta_filter *req;
3144 struct hclge_desc desc;
3145 int ret;
3146
3147 req = (struct hclge_cfg_func_mta_filter *)desc.data;
3148 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3149
3150 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3151 enable);
3152 req->function_id = func_id;
3153
3154 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3155 if (ret) {
3156 dev_err(&hdev->pdev->dev,
3157 "Config func_id enable failed for cmd_send, ret =%d.\n",
3158 ret);
3159 return ret;
3160 }
3161
3162 return 0;
3163}
3164
3165static int hclge_set_mta_table_item(struct hclge_vport *vport,
3166 u16 idx,
3167 bool enable)
3168{
3169 struct hclge_dev *hdev = vport->back;
3170 struct hclge_cfg_func_mta_item *req;
3171 struct hclge_desc desc;
3172 int ret;
3173
3174 req = (struct hclge_cfg_func_mta_item *)desc.data;
3175 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3176 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3177
3178 hnae_set_field(req->item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3179 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
3180 req->item_idx = cpu_to_le16(req->item_idx);
3181
3182 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3183 if (ret) {
3184 dev_err(&hdev->pdev->dev,
3185 "Config mta table item failed for cmd_send, ret =%d.\n",
3186 ret);
3187 return ret;
3188 }
3189
3190 return 0;
3191}
3192
3193static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
3194 struct hclge_mac_vlan_tbl_entry *req)
3195{
3196 struct hclge_dev *hdev = vport->back;
3197 struct hclge_desc desc;
3198 u8 resp_code;
3199 int ret;
3200
3201 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3202
3203 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry));
3204
3205 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3206 if (ret) {
3207 dev_err(&hdev->pdev->dev,
3208 "del mac addr failed for cmd_send, ret =%d.\n",
3209 ret);
3210 return ret;
3211 }
3212 resp_code = (desc.data[0] >> 8) & 0xff;
3213
3214 return hclge_get_mac_vlan_cmd_status(vport, desc.retval, resp_code,
3215 HCLGE_MAC_VLAN_REMOVE);
3216}
3217
3218static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
3219 struct hclge_mac_vlan_tbl_entry *req,
3220 struct hclge_desc *desc,
3221 bool is_mc)
3222{
3223 struct hclge_dev *hdev = vport->back;
3224 u8 resp_code;
3225 int ret;
3226
3227 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3228 if (is_mc) {
3229 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3230 memcpy(desc[0].data,
3231 req,
3232 sizeof(struct hclge_mac_vlan_tbl_entry));
3233 hclge_cmd_setup_basic_desc(&desc[1],
3234 HCLGE_OPC_MAC_VLAN_ADD,
3235 true);
3236 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3237 hclge_cmd_setup_basic_desc(&desc[2],
3238 HCLGE_OPC_MAC_VLAN_ADD,
3239 true);
3240 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3241 } else {
3242 memcpy(desc[0].data,
3243 req,
3244 sizeof(struct hclge_mac_vlan_tbl_entry));
3245 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3246 }
3247 if (ret) {
3248 dev_err(&hdev->pdev->dev,
3249 "lookup mac addr failed for cmd_send, ret =%d.\n",
3250 ret);
3251 return ret;
3252 }
3253 resp_code = (desc[0].data[0] >> 8) & 0xff;
3254
3255 return hclge_get_mac_vlan_cmd_status(vport, desc[0].retval, resp_code,
3256 HCLGE_MAC_VLAN_LKUP);
3257}
3258
3259static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
3260 struct hclge_mac_vlan_tbl_entry *req,
3261 struct hclge_desc *mc_desc)
3262{
3263 struct hclge_dev *hdev = vport->back;
3264 int cfg_status;
3265 u8 resp_code;
3266 int ret;
3267
3268 if (!mc_desc) {
3269 struct hclge_desc desc;
3270
3271 hclge_cmd_setup_basic_desc(&desc,
3272 HCLGE_OPC_MAC_VLAN_ADD,
3273 false);
3274 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry));
3275 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3276 resp_code = (desc.data[0] >> 8) & 0xff;
3277 cfg_status = hclge_get_mac_vlan_cmd_status(vport, desc.retval,
3278 resp_code,
3279 HCLGE_MAC_VLAN_ADD);
3280 } else {
3281 mc_desc[0].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3282 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3283 mc_desc[1].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3284 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3285 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3286 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3287 memcpy(mc_desc[0].data, req,
3288 sizeof(struct hclge_mac_vlan_tbl_entry));
3289 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
3290 resp_code = (mc_desc[0].data[0] >> 8) & 0xff;
3291 cfg_status = hclge_get_mac_vlan_cmd_status(vport,
3292 mc_desc[0].retval,
3293 resp_code,
3294 HCLGE_MAC_VLAN_ADD);
3295 }
3296
3297 if (ret) {
3298 dev_err(&hdev->pdev->dev,
3299 "add mac addr failed for cmd_send, ret =%d.\n",
3300 ret);
3301 return ret;
3302 }
3303
3304 return cfg_status;
3305}
3306
3307static int hclge_add_uc_addr(struct hnae3_handle *handle,
3308 const unsigned char *addr)
3309{
3310 struct hclge_vport *vport = hclge_get_vport(handle);
3311
3312 return hclge_add_uc_addr_common(vport, addr);
3313}
3314
3315int hclge_add_uc_addr_common(struct hclge_vport *vport,
3316 const unsigned char *addr)
3317{
3318 struct hclge_dev *hdev = vport->back;
3319 struct hclge_mac_vlan_tbl_entry req;
3320 enum hclge_cmd_status status;
3321
3322 /* mac addr check */
3323 if (is_zero_ether_addr(addr) ||
3324 is_broadcast_ether_addr(addr) ||
3325 is_multicast_ether_addr(addr)) {
3326 dev_err(&hdev->pdev->dev,
3327 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3328 addr,
3329 is_zero_ether_addr(addr),
3330 is_broadcast_ether_addr(addr),
3331 is_multicast_ether_addr(addr));
3332 return -EINVAL;
3333 }
3334
3335 memset(&req, 0, sizeof(req));
3336 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3337 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3338 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
3339 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3340 hnae_set_bit(req.egress_port,
3341 HCLGE_MAC_EPORT_SW_EN_B, 0);
3342 hnae_set_bit(req.egress_port,
3343 HCLGE_MAC_EPORT_TYPE_B, 0);
3344 hnae_set_field(req.egress_port, HCLGE_MAC_EPORT_VFID_M,
3345 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
3346 hnae_set_field(req.egress_port, HCLGE_MAC_EPORT_PFID_M,
3347 HCLGE_MAC_EPORT_PFID_S, 0);
3348 req.egress_port = cpu_to_le16(req.egress_port);
3349
3350 hclge_prepare_mac_addr(&req, addr);
3351
3352 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
3353
3354 return status;
3355}
3356
3357static int hclge_rm_uc_addr(struct hnae3_handle *handle,
3358 const unsigned char *addr)
3359{
3360 struct hclge_vport *vport = hclge_get_vport(handle);
3361
3362 return hclge_rm_uc_addr_common(vport, addr);
3363}
3364
3365int hclge_rm_uc_addr_common(struct hclge_vport *vport,
3366 const unsigned char *addr)
3367{
3368 struct hclge_dev *hdev = vport->back;
3369 struct hclge_mac_vlan_tbl_entry req;
3370 enum hclge_cmd_status status;
3371
3372 /* mac addr check */
3373 if (is_zero_ether_addr(addr) ||
3374 is_broadcast_ether_addr(addr) ||
3375 is_multicast_ether_addr(addr)) {
3376 dev_dbg(&hdev->pdev->dev,
3377 "Remove mac err! invalid mac:%pM.\n",
3378 addr);
3379 return -EINVAL;
3380 }
3381
3382 memset(&req, 0, sizeof(req));
3383 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3384 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3385 hclge_prepare_mac_addr(&req, addr);
3386 status = hclge_remove_mac_vlan_tbl(vport, &req);
3387
3388 return status;
3389}
3390
3391static int hclge_add_mc_addr(struct hnae3_handle *handle,
3392 const unsigned char *addr)
3393{
3394 struct hclge_vport *vport = hclge_get_vport(handle);
3395
3396 return hclge_add_mc_addr_common(vport, addr);
3397}
3398
3399int hclge_add_mc_addr_common(struct hclge_vport *vport,
3400 const unsigned char *addr)
3401{
3402 struct hclge_dev *hdev = vport->back;
3403 struct hclge_mac_vlan_tbl_entry req;
3404 struct hclge_desc desc[3];
3405 u16 tbl_idx;
3406 int status;
3407
3408 /* mac addr check */
3409 if (!is_multicast_ether_addr(addr)) {
3410 dev_err(&hdev->pdev->dev,
3411 "Add mc mac err! invalid mac:%pM.\n",
3412 addr);
3413 return -EINVAL;
3414 }
3415 memset(&req, 0, sizeof(req));
3416 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3417 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3418 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
3419 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3420 hclge_prepare_mac_addr(&req, addr);
3421 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
3422 if (!status) {
3423 /* This mac addr exist, update VFID for it */
3424 hclge_update_desc_vfid(desc, vport->vport_id, false);
3425 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3426 } else {
3427 /* This mac addr do not exist, add new entry for it */
3428 memset(desc[0].data, 0, sizeof(desc[0].data));
3429 memset(desc[1].data, 0, sizeof(desc[0].data));
3430 memset(desc[2].data, 0, sizeof(desc[0].data));
3431 hclge_update_desc_vfid(desc, vport->vport_id, false);
3432 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3433 }
3434
3435 /* Set MTA table for this MAC address */
3436 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
3437 status = hclge_set_mta_table_item(vport, tbl_idx, true);
3438
3439 return status;
3440}
3441
3442static int hclge_rm_mc_addr(struct hnae3_handle *handle,
3443 const unsigned char *addr)
3444{
3445 struct hclge_vport *vport = hclge_get_vport(handle);
3446
3447 return hclge_rm_mc_addr_common(vport, addr);
3448}
3449
3450int hclge_rm_mc_addr_common(struct hclge_vport *vport,
3451 const unsigned char *addr)
3452{
3453 struct hclge_dev *hdev = vport->back;
3454 struct hclge_mac_vlan_tbl_entry req;
3455 enum hclge_cmd_status status;
3456 struct hclge_desc desc[3];
3457 u16 tbl_idx;
3458
3459 /* mac addr check */
3460 if (!is_multicast_ether_addr(addr)) {
3461 dev_dbg(&hdev->pdev->dev,
3462 "Remove mc mac err! invalid mac:%pM.\n",
3463 addr);
3464 return -EINVAL;
3465 }
3466
3467 memset(&req, 0, sizeof(req));
3468 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3469 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3470 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
3471 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3472 hclge_prepare_mac_addr(&req, addr);
3473 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
3474 if (!status) {
3475 /* This mac addr exist, remove this handle's VFID for it */
3476 hclge_update_desc_vfid(desc, vport->vport_id, true);
3477
3478 if (hclge_is_all_function_id_zero(desc))
3479 /* All the vfid is zero, so need to delete this entry */
3480 status = hclge_remove_mac_vlan_tbl(vport, &req);
3481 else
3482 /* Not all the vfid is zero, update the vfid */
3483 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3484
3485 } else {
3486 /* This mac addr do not exist, can't delete it */
3487 dev_err(&hdev->pdev->dev,
d7629e74 3488 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 3489 status);
3490 return -EIO;
3491 }
3492
3493 /* Set MTB table for this MAC address */
3494 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
3495 status = hclge_set_mta_table_item(vport, tbl_idx, false);
3496
3497 return status;
3498}
3499
3500static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
3501{
3502 struct hclge_vport *vport = hclge_get_vport(handle);
3503 struct hclge_dev *hdev = vport->back;
3504
3505 ether_addr_copy(p, hdev->hw.mac.mac_addr);
3506}
3507
3508static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
3509{
3510 const unsigned char *new_addr = (const unsigned char *)p;
3511 struct hclge_vport *vport = hclge_get_vport(handle);
3512 struct hclge_dev *hdev = vport->back;
3513
3514 /* mac addr check */
3515 if (is_zero_ether_addr(new_addr) ||
3516 is_broadcast_ether_addr(new_addr) ||
3517 is_multicast_ether_addr(new_addr)) {
3518 dev_err(&hdev->pdev->dev,
3519 "Change uc mac err! invalid mac:%p.\n",
3520 new_addr);
3521 return -EINVAL;
3522 }
3523
3524 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
3525
3526 if (!hclge_add_uc_addr(handle, new_addr)) {
3527 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
3528 return 0;
3529 }
3530
3531 return -EIO;
3532}
3533
3534static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
3535 bool filter_en)
3536{
3537 struct hclge_vlan_filter_ctrl *req;
3538 struct hclge_desc desc;
3539 int ret;
3540
3541 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
3542
3543 req = (struct hclge_vlan_filter_ctrl *)desc.data;
3544 req->vlan_type = vlan_type;
3545 req->vlan_fe = filter_en;
3546
3547 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3548 if (ret) {
3549 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
3550 ret);
3551 return ret;
3552 }
3553
3554 return 0;
3555}
3556
3557int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
3558 bool is_kill, u16 vlan, u8 qos, __be16 proto)
3559{
3560#define HCLGE_MAX_VF_BYTES 16
3561 struct hclge_vlan_filter_vf_cfg *req0;
3562 struct hclge_vlan_filter_vf_cfg *req1;
3563 struct hclge_desc desc[2];
3564 u8 vf_byte_val;
3565 u8 vf_byte_off;
3566 int ret;
3567
3568 hclge_cmd_setup_basic_desc(&desc[0],
3569 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
3570 hclge_cmd_setup_basic_desc(&desc[1],
3571 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
3572
3573 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3574
3575 vf_byte_off = vfid / 8;
3576 vf_byte_val = 1 << (vfid % 8);
3577
3578 req0 = (struct hclge_vlan_filter_vf_cfg *)desc[0].data;
3579 req1 = (struct hclge_vlan_filter_vf_cfg *)desc[1].data;
3580
3581 req0->vlan_id = vlan;
3582 req0->vlan_cfg = is_kill;
3583
3584 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
3585 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
3586 else
3587 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
3588
3589 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3590 if (ret) {
3591 dev_err(&hdev->pdev->dev,
3592 "Send vf vlan command fail, ret =%d.\n",
3593 ret);
3594 return ret;
3595 }
3596
3597 if (!is_kill) {
3598 if (!req0->resp_code || req0->resp_code == 1)
3599 return 0;
3600
3601 dev_err(&hdev->pdev->dev,
3602 "Add vf vlan filter fail, ret =%d.\n",
3603 req0->resp_code);
3604 } else {
3605 if (!req0->resp_code)
3606 return 0;
3607
3608 dev_err(&hdev->pdev->dev,
3609 "Kill vf vlan filter fail, ret =%d.\n",
3610 req0->resp_code);
3611 }
3612
3613 return -EIO;
3614}
3615
3616static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
3617 __be16 proto, u16 vlan_id,
3618 bool is_kill)
3619{
3620 struct hclge_vport *vport = hclge_get_vport(handle);
3621 struct hclge_dev *hdev = vport->back;
3622 struct hclge_vlan_filter_pf_cfg *req;
3623 struct hclge_desc desc;
3624 u8 vlan_offset_byte_val;
3625 u8 vlan_offset_byte;
3626 u8 vlan_offset_160;
3627 int ret;
3628
3629 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
3630
3631 vlan_offset_160 = vlan_id / 160;
3632 vlan_offset_byte = (vlan_id % 160) / 8;
3633 vlan_offset_byte_val = 1 << (vlan_id % 8);
3634
3635 req = (struct hclge_vlan_filter_pf_cfg *)desc.data;
3636 req->vlan_offset = vlan_offset_160;
3637 req->vlan_cfg = is_kill;
3638 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
3639
3640 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3641 if (ret) {
3642 dev_err(&hdev->pdev->dev,
3643 "port vlan command, send fail, ret =%d.\n",
3644 ret);
3645 return ret;
3646 }
3647
3648 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
3649 if (ret) {
3650 dev_err(&hdev->pdev->dev,
3651 "Set pf vlan filter config fail, ret =%d.\n",
3652 ret);
3653 return -EIO;
3654 }
3655
3656 return 0;
3657}
3658
3659static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
3660 u16 vlan, u8 qos, __be16 proto)
3661{
3662 struct hclge_vport *vport = hclge_get_vport(handle);
3663 struct hclge_dev *hdev = vport->back;
3664
3665 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
3666 return -EINVAL;
3667 if (proto != htons(ETH_P_8021Q))
3668 return -EPROTONOSUPPORT;
3669
3670 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
3671}
3672
3673static int hclge_init_vlan_config(struct hclge_dev *hdev)
3674{
3675#define HCLGE_VLAN_TYPE_VF_TABLE 0
3676#define HCLGE_VLAN_TYPE_PORT_TABLE 1
3677 int ret;
3678
3679 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
3680 true);
3681 if (ret)
3682 return ret;
3683
3684 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
3685 true);
3686
3687 return ret;
3688}
3689
3690static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
3691{
3692 struct hclge_vport *vport = hclge_get_vport(handle);
3693 struct hclge_config_max_frm_size *req;
3694 struct hclge_dev *hdev = vport->back;
3695 struct hclge_desc desc;
3696 int ret;
3697
3698 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
3699 return -EINVAL;
3700
3701 hdev->mps = new_mtu;
3702 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
3703
3704 req = (struct hclge_config_max_frm_size *)desc.data;
3705 req->max_frm_size = cpu_to_le16(new_mtu);
3706
3707 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3708 if (ret) {
3709 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
3710 return ret;
3711 }
3712
3713 return 0;
3714}
3715
3716static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
3717 bool enable)
3718{
3719 struct hclge_reset_tqp_queue *req;
3720 struct hclge_desc desc;
3721 int ret;
3722
3723 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
3724
3725 req = (struct hclge_reset_tqp_queue *)desc.data;
3726 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
3727 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
3728
3729 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3730 if (ret) {
3731 dev_err(&hdev->pdev->dev,
3732 "Send tqp reset cmd error, status =%d\n", ret);
3733 return ret;
3734 }
3735
3736 return 0;
3737}
3738
3739static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
3740{
3741 struct hclge_reset_tqp_queue *req;
3742 struct hclge_desc desc;
3743 int ret;
3744
3745 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
3746
3747 req = (struct hclge_reset_tqp_queue *)desc.data;
3748 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
3749
3750 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3751 if (ret) {
3752 dev_err(&hdev->pdev->dev,
3753 "Get reset status error, status =%d\n", ret);
3754 return ret;
3755 }
3756
3757 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
3758}
3759
3760static void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
3761{
3762 struct hclge_vport *vport = hclge_get_vport(handle);
3763 struct hclge_dev *hdev = vport->back;
3764 int reset_try_times = 0;
3765 int reset_status;
3766 int ret;
3767
3768 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
3769 if (ret) {
3770 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
3771 return;
3772 }
3773
3774 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
3775 if (ret) {
3776 dev_warn(&hdev->pdev->dev,
3777 "Send reset tqp cmd fail, ret = %d\n", ret);
3778 return;
3779 }
3780
3781 reset_try_times = 0;
3782 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
3783 /* Wait for tqp hw reset */
3784 msleep(20);
3785 reset_status = hclge_get_reset_status(hdev, queue_id);
3786 if (reset_status)
3787 break;
3788 }
3789
3790 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
3791 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
3792 return;
3793 }
3794
3795 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
3796 if (ret) {
3797 dev_warn(&hdev->pdev->dev,
3798 "Deassert the soft reset fail, ret = %d\n", ret);
3799 return;
3800 }
3801}
3802
3803static u32 hclge_get_fw_version(struct hnae3_handle *handle)
3804{
3805 struct hclge_vport *vport = hclge_get_vport(handle);
3806 struct hclge_dev *hdev = vport->back;
3807
3808 return hdev->fw_version;
3809}
3810
3811static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
3812 u32 *rx_en, u32 *tx_en)
3813{
3814 struct hclge_vport *vport = hclge_get_vport(handle);
3815 struct hclge_dev *hdev = vport->back;
3816
3817 *auto_neg = hclge_get_autoneg(handle);
3818
3819 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
3820 *rx_en = 0;
3821 *tx_en = 0;
3822 return;
3823 }
3824
3825 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
3826 *rx_en = 1;
3827 *tx_en = 0;
3828 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
3829 *tx_en = 1;
3830 *rx_en = 0;
3831 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
3832 *rx_en = 1;
3833 *tx_en = 1;
3834 } else {
3835 *rx_en = 0;
3836 *tx_en = 0;
3837 }
3838}
3839
3840static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
3841 u8 *auto_neg, u32 *speed, u8 *duplex)
3842{
3843 struct hclge_vport *vport = hclge_get_vport(handle);
3844 struct hclge_dev *hdev = vport->back;
3845
3846 if (speed)
3847 *speed = hdev->hw.mac.speed;
3848 if (duplex)
3849 *duplex = hdev->hw.mac.duplex;
3850 if (auto_neg)
3851 *auto_neg = hdev->hw.mac.autoneg;
3852}
3853
3854static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
3855{
3856 struct hclge_vport *vport = hclge_get_vport(handle);
3857 struct hclge_dev *hdev = vport->back;
3858
3859 if (media_type)
3860 *media_type = hdev->hw.mac.media_type;
3861}
3862
3863static void hclge_get_mdix_mode(struct hnae3_handle *handle,
3864 u8 *tp_mdix_ctrl, u8 *tp_mdix)
3865{
3866 struct hclge_vport *vport = hclge_get_vport(handle);
3867 struct hclge_dev *hdev = vport->back;
3868 struct phy_device *phydev = hdev->hw.mac.phydev;
3869 int mdix_ctrl, mdix, retval, is_resolved;
3870
3871 if (!phydev) {
3872 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
3873 *tp_mdix = ETH_TP_MDI_INVALID;
3874 return;
3875 }
3876
3877 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
3878
3879 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
3880 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
3881 HCLGE_PHY_MDIX_CTRL_S);
3882
3883 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
3884 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
3885 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
3886
3887 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
3888
3889 switch (mdix_ctrl) {
3890 case 0x0:
3891 *tp_mdix_ctrl = ETH_TP_MDI;
3892 break;
3893 case 0x1:
3894 *tp_mdix_ctrl = ETH_TP_MDI_X;
3895 break;
3896 case 0x3:
3897 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
3898 break;
3899 default:
3900 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
3901 break;
3902 }
3903
3904 if (!is_resolved)
3905 *tp_mdix = ETH_TP_MDI_INVALID;
3906 else if (mdix)
3907 *tp_mdix = ETH_TP_MDI_X;
3908 else
3909 *tp_mdix = ETH_TP_MDI;
3910}
3911
3912static int hclge_init_client_instance(struct hnae3_client *client,
3913 struct hnae3_ae_dev *ae_dev)
3914{
3915 struct hclge_dev *hdev = ae_dev->priv;
3916 struct hclge_vport *vport;
3917 int i, ret;
3918
3919 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3920 vport = &hdev->vport[i];
3921
3922 switch (client->type) {
3923 case HNAE3_CLIENT_KNIC:
3924
3925 hdev->nic_client = client;
3926 vport->nic.client = client;
3927 ret = client->ops->init_instance(&vport->nic);
3928 if (ret)
3929 goto err;
3930
3931 if (hdev->roce_client &&
3932 hnae_get_bit(hdev->ae_dev->flag,
3933 HNAE_DEV_SUPPORT_ROCE_B)) {
3934 struct hnae3_client *rc = hdev->roce_client;
3935
3936 ret = hclge_init_roce_base_info(vport);
3937 if (ret)
3938 goto err;
3939
3940 ret = rc->ops->init_instance(&vport->roce);
3941 if (ret)
3942 goto err;
3943 }
3944
3945 break;
3946 case HNAE3_CLIENT_UNIC:
3947 hdev->nic_client = client;
3948 vport->nic.client = client;
3949
3950 ret = client->ops->init_instance(&vport->nic);
3951 if (ret)
3952 goto err;
3953
3954 break;
3955 case HNAE3_CLIENT_ROCE:
3956 if (hnae_get_bit(hdev->ae_dev->flag,
3957 HNAE_DEV_SUPPORT_ROCE_B)) {
3958 hdev->roce_client = client;
3959 vport->roce.client = client;
3960 }
3961
3962 if (hdev->roce_client) {
3963 ret = hclge_init_roce_base_info(vport);
3964 if (ret)
3965 goto err;
3966
3967 ret = client->ops->init_instance(&vport->roce);
3968 if (ret)
3969 goto err;
3970 }
3971 }
3972 }
3973
3974 return 0;
3975err:
3976 return ret;
3977}
3978
3979static void hclge_uninit_client_instance(struct hnae3_client *client,
3980 struct hnae3_ae_dev *ae_dev)
3981{
3982 struct hclge_dev *hdev = ae_dev->priv;
3983 struct hclge_vport *vport;
3984 int i;
3985
3986 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3987 vport = &hdev->vport[i];
3988 if (hdev->roce_client)
3989 hdev->roce_client->ops->uninit_instance(&vport->roce,
3990 0);
3991 if (client->type == HNAE3_CLIENT_ROCE)
3992 return;
3993 if (client->ops->uninit_instance)
3994 client->ops->uninit_instance(&vport->nic, 0);
3995 }
3996}
3997
3998static int hclge_pci_init(struct hclge_dev *hdev)
3999{
4000 struct pci_dev *pdev = hdev->pdev;
4001 struct hclge_hw *hw;
4002 int ret;
4003
4004 ret = pci_enable_device(pdev);
4005 if (ret) {
4006 dev_err(&pdev->dev, "failed to enable PCI device\n");
4007 goto err_no_drvdata;
4008 }
4009
4010 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4011 if (ret) {
4012 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4013 if (ret) {
4014 dev_err(&pdev->dev,
4015 "can't set consistent PCI DMA");
4016 goto err_disable_device;
4017 }
4018 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4019 }
4020
4021 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4022 if (ret) {
4023 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4024 goto err_disable_device;
4025 }
4026
4027 pci_set_master(pdev);
4028 hw = &hdev->hw;
4029 hw->back = hdev;
4030 hw->io_base = pcim_iomap(pdev, 2, 0);
4031 if (!hw->io_base) {
4032 dev_err(&pdev->dev, "Can't map configuration register space\n");
4033 ret = -ENOMEM;
4034 goto err_clr_master;
4035 }
4036
4037 return 0;
4038err_clr_master:
4039 pci_clear_master(pdev);
4040 pci_release_regions(pdev);
4041err_disable_device:
4042 pci_disable_device(pdev);
4043err_no_drvdata:
4044 pci_set_drvdata(pdev, NULL);
4045
4046 return ret;
4047}
4048
4049static void hclge_pci_uninit(struct hclge_dev *hdev)
4050{
4051 struct pci_dev *pdev = hdev->pdev;
4052
4053 if (hdev->flag & HCLGE_FLAG_USE_MSIX) {
4054 pci_disable_msix(pdev);
4055 devm_kfree(&pdev->dev, hdev->msix_entries);
4056 hdev->msix_entries = NULL;
4057 } else {
4058 pci_disable_msi(pdev);
4059 }
4060
4061 pci_clear_master(pdev);
4062 pci_release_mem_regions(pdev);
4063 pci_disable_device(pdev);
4064}
4065
4066static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4067{
4068 struct pci_dev *pdev = ae_dev->pdev;
4069 const struct pci_device_id *id;
4070 struct hclge_dev *hdev;
4071 int ret;
4072
4073 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4074 if (!hdev) {
4075 ret = -ENOMEM;
4076 goto err_hclge_dev;
4077 }
4078
4079 hdev->flag |= HCLGE_FLAG_USE_MSIX;
4080 hdev->pdev = pdev;
4081 hdev->ae_dev = ae_dev;
4082 ae_dev->priv = hdev;
4083
4084 id = pci_match_id(roce_pci_tbl, ae_dev->pdev);
4085 if (id)
4086 hnae_set_bit(ae_dev->flag, HNAE_DEV_SUPPORT_ROCE_B, 1);
4087
4088 ret = hclge_pci_init(hdev);
4089 if (ret) {
4090 dev_err(&pdev->dev, "PCI init failed\n");
4091 goto err_pci_init;
4092 }
4093
4094 /* Command queue initialize */
4095 ret = hclge_cmd_init(hdev);
4096 if (ret)
4097 goto err_cmd_init;
4098
4099 ret = hclge_get_cap(hdev);
4100 if (ret) {
e00e2197
CIK		 4101 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4102 ret);
46a3df9f
S		 4103 return ret;
4104 }
4105
4106 ret = hclge_configure(hdev);
4107 if (ret) {
4108 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4109 return ret;
4110 }
4111
4112 if (hdev->flag & HCLGE_FLAG_USE_MSIX)
4113 ret = hclge_init_msix(hdev);
4114 else
4115 ret = hclge_init_msi(hdev);
4116 if (ret) {
4117 dev_err(&pdev->dev, "Init msix/msi error, ret = %d.\n", ret);
4118 return ret;
4119 }
4120
4121 ret = hclge_alloc_tqps(hdev);
4122 if (ret) {
4123 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4124 return ret;
4125 }
4126
4127 ret = hclge_alloc_vport(hdev);
4128 if (ret) {
4129 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4130 return ret;
4131 }
4132
4133 ret = hclge_mac_init(hdev);
4134 if (ret) {
4135 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4136 return ret;
4137 }
4138 ret = hclge_buffer_alloc(hdev);
4139 if (ret) {
4140 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4141 return ret;
4142 }
4143
4144 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4145 if (ret) {
4146 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4147 return ret;
4148 }
4149
4150 ret = hclge_rss_init_hw(hdev);
4151 if (ret) {
4152 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4153 return ret;
4154 }
4155
4156 ret = hclge_init_vlan_config(hdev);
4157 if (ret) {
4158 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4159 return ret;
4160 }
4161
4162 ret = hclge_tm_schd_init(hdev);
4163 if (ret) {
4164 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4165 return ret;
4166 }
4167
4168 setup_timer(&hdev->service_timer, hclge_service_timer,
4169 (unsigned long)hdev);
4170 INIT_WORK(&hdev->service_task, hclge_service_task);
4171
4172 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4173 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4174
4175 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4176 return 0;
4177
4178err_cmd_init:
4179 pci_release_regions(pdev);
4180err_pci_init:
4181 pci_set_drvdata(pdev, NULL);
4182err_hclge_dev:
4183 return ret;
4184}
4185
4186static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4187{
4188 struct hclge_dev *hdev = ae_dev->priv;
4189 struct hclge_mac *mac = &hdev->hw.mac;
4190
4191 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4192
2a32ca13
AB		 4193 if (IS_ENABLED(CONFIG_PCI_IOV))
4194 hclge_disable_sriov(hdev);
46a3df9f
S		 4195
4196 if (hdev->service_timer.data)
4197 del_timer_sync(&hdev->service_timer);
4198 if (hdev->service_task.func)
4199 cancel_work_sync(&hdev->service_task);
4200
4201 if (mac->phydev)
4202 mdiobus_unregister(mac->mdio_bus);
4203
4204 hclge_destroy_cmd_queue(&hdev->hw);
4205 hclge_pci_uninit(hdev);
4206 ae_dev->priv = NULL;
4207}
4208
4209static const struct hnae3_ae_ops hclge_ops = {
4210 .init_ae_dev = hclge_init_ae_dev,
4211 .uninit_ae_dev = hclge_uninit_ae_dev,
4212 .init_client_instance = hclge_init_client_instance,
4213 .uninit_client_instance = hclge_uninit_client_instance,
4214 .map_ring_to_vector = hclge_map_handle_ring_to_vector,
4215 .unmap_ring_from_vector = hclge_unmap_ring_from_vector,
4216 .get_vector = hclge_get_vector,
4217 .set_promisc_mode = hclge_set_promisc_mode,
4218 .start = hclge_ae_start,
4219 .stop = hclge_ae_stop,
4220 .get_status = hclge_get_status,
4221 .get_ksettings_an_result = hclge_get_ksettings_an_result,
4222 .update_speed_duplex_h = hclge_update_speed_duplex_h,
4223 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
4224 .get_media_type = hclge_get_media_type,
4225 .get_rss_key_size = hclge_get_rss_key_size,
4226 .get_rss_indir_size = hclge_get_rss_indir_size,
4227 .get_rss = hclge_get_rss,
4228 .set_rss = hclge_set_rss,
4229 .get_tc_size = hclge_get_tc_size,
4230 .get_mac_addr = hclge_get_mac_addr,
4231 .set_mac_addr = hclge_set_mac_addr,
4232 .add_uc_addr = hclge_add_uc_addr,
4233 .rm_uc_addr = hclge_rm_uc_addr,
4234 .add_mc_addr = hclge_add_mc_addr,
4235 .rm_mc_addr = hclge_rm_mc_addr,
4236 .set_autoneg = hclge_set_autoneg,
4237 .get_autoneg = hclge_get_autoneg,
4238 .get_pauseparam = hclge_get_pauseparam,
4239 .set_mtu = hclge_set_mtu,
4240 .reset_queue = hclge_reset_tqp,
4241 .get_stats = hclge_get_stats,
4242 .update_stats = hclge_update_stats,
4243 .get_strings = hclge_get_strings,
4244 .get_sset_count = hclge_get_sset_count,
4245 .get_fw_version = hclge_get_fw_version,
4246 .get_mdix_mode = hclge_get_mdix_mode,
4247 .set_vlan_filter = hclge_set_port_vlan_filter,
4248 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
4249};
4250
4251static struct hnae3_ae_algo ae_algo = {
4252 .ops = &hclge_ops,
4253 .name = HCLGE_NAME,
4254 .pdev_id_table = ae_algo_pci_tbl,
4255};
4256
4257static int hclge_init(void)
4258{
4259 pr_info("%s is initializing\n", HCLGE_NAME);
4260
4261 return hnae3_register_ae_algo(&ae_algo);
4262}
4263
4264static void hclge_exit(void)
4265{
4266 hnae3_unregister_ae_algo(&ae_algo);
4267}
4268module_init(hclge_init);
4269module_exit(hclge_exit);
4270
4271MODULE_LICENSE("GPL");
4272MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4273MODULE_DESCRIPTION("HCLGE Driver");
4274MODULE_VERSION(HCLGE_MOD_VERSION);
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