]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
UBUNTU: SAUCE: {topost} net: hns3: fix for waterline not setting correctly
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
4e2e261d
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
46a3df9f
S		 3
4#include <linux/acpi.h>
5#include <linux/device.h>
6#include <linux/etherdevice.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
7393ed39 14#include <linux/if_vlan.h>
d5752031 15#include <net/rtnetlink.h>
46a3df9f 16#include "hclge_cmd.h"
cacde272 17#include "hclge_dcb.h"
46a3df9f 18#include "hclge_main.h"
0cdbdd3e 19#include "hclge_mbx.h"
46a3df9f
S		 20#include "hclge_mdio.h"
21#include "hclge_tm.h"
22#include "hnae3.h"
23
24#define HCLGE_NAME "hclge"
25#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
26#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
27#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
28#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
29
46a3df9f
S		 30static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
31 enum hclge_mta_dmac_sel_type mta_mac_sel,
32 bool enable);
59bc85ec 33static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 34static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 35static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 36
37static struct hnae3_ae_algo ae_algo;
38
39static const struct pci_device_id ae_algo_pci_tbl[] = {
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 47 /* required last entry */
46a3df9f
S		 48 {0, }
49};
50
28d9cec8
YL		 51MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
52
46a3df9f
S		 53static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
54 "Mac Loopback test",
55 "Serdes Loopback test",
56 "Phy Loopback test"
57};
58
59static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
66 {"igu_rx_uni_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
68 {"igu_rx_multi_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
70 {"igu_rx_broad_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
74 {"egu_tx_uni_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
76 {"egu_tx_multi_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
78 {"egu_tx_broad_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
88 {"ssu_tx_in_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
90 {"ssu_tx_out_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
92 {"ssu_rx_in_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
94 {"ssu_rx_out_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
96};
97
98static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
99 {"igu_rx_err_pkt",
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
105 {"egu_tx_1588_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
111 {"ppp_key_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
113 {"ppp_rlt_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
115 {"ssu_key_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
117 {"pkt_curr_buf_cnt",
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
119 {"qcn_fb_rcv_cnt",
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
121 {"qcn_fb_drop_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
205 {"mb_uncopy_num",
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
221};
222
223static const struct hclge_comm_stats_str g_mac_stats_string[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
f3426583
JS		 280 {"mac_tx_oversize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
b42874e4
JS		 294 {"mac_tx_1519_2047_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
296 {"mac_tx_2048_4095_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
298 {"mac_tx_4096_8191_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
b42874e4
JS		 300 {"mac_tx_8192_9216_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
302 {"mac_tx_9217_12287_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
304 {"mac_tx_12288_16383_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
306 {"mac_tx_1519_max_good_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
308 {"mac_tx_1519_max_bad_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 310 {"mac_rx_total_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
312 {"mac_rx_total_oct_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
314 {"mac_rx_good_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
316 {"mac_rx_bad_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
318 {"mac_rx_good_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
320 {"mac_rx_bad_oct_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
322 {"mac_rx_uni_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
324 {"mac_rx_multi_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
326 {"mac_rx_broad_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
328 {"mac_rx_undersize_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
f3426583
JS		 330 {"mac_rx_oversize_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 332 {"mac_rx_64_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
334 {"mac_rx_65_127_oct_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
336 {"mac_rx_128_255_oct_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
338 {"mac_rx_256_511_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
340 {"mac_rx_512_1023_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
342 {"mac_rx_1024_1518_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
b42874e4
JS		 344 {"mac_rx_1519_2047_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
346 {"mac_rx_2048_4095_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
348 {"mac_rx_4096_8191_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
b42874e4
JS		 350 {"mac_rx_8192_9216_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
352 {"mac_rx_9217_12287_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
354 {"mac_rx_12288_16383_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
356 {"mac_rx_1519_max_good_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
358 {"mac_rx_1519_max_bad_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 360
c36317be
JS		 361 {"mac_tx_fragment_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
363 {"mac_tx_undermin_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
365 {"mac_tx_jabber_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
367 {"mac_tx_err_all_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
369 {"mac_tx_from_app_good_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
371 {"mac_tx_from_app_bad_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
373 {"mac_rx_fragment_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
375 {"mac_rx_undermin_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
377 {"mac_rx_jabber_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
379 {"mac_rx_fcs_err_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
381 {"mac_rx_send_app_good_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
383 {"mac_rx_send_app_bad_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 385};
386
635bfb58
FL		 387static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
388 {
389 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
390 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
391 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
392 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
393 .i_port_bitmap = 0x1,
394 },
395};
396
46a3df9f
S		 397static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
398{
399#define HCLGE_64_BIT_CMD_NUM 5
400#define HCLGE_64_BIT_RTN_DATANUM 4
401 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
402 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 403 __le64 *desc_data;
46a3df9f
S		 404 int i, k, n;
405 int ret;
406
407 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
408 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
409 if (ret) {
410 dev_err(&hdev->pdev->dev,
411 "Get 64 bit pkt stats fail, status = %d.\n", ret);
412 return ret;
413 }
414
415 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
416 if (unlikely(i == 0)) {
a90bb9a5 417 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 418 n = HCLGE_64_BIT_RTN_DATANUM - 1;
419 } else {
a90bb9a5 420 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 421 n = HCLGE_64_BIT_RTN_DATANUM;
422 }
423 for (k = 0; k < n; k++) {
a90bb9a5 424 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 425 desc_data++;
426 }
427 }
428
429 return 0;
430}
431
432static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
433{
434 stats->pkt_curr_buf_cnt = 0;
435 stats->pkt_curr_buf_tc0_cnt = 0;
436 stats->pkt_curr_buf_tc1_cnt = 0;
437 stats->pkt_curr_buf_tc2_cnt = 0;
438 stats->pkt_curr_buf_tc3_cnt = 0;
439 stats->pkt_curr_buf_tc4_cnt = 0;
440 stats->pkt_curr_buf_tc5_cnt = 0;
441 stats->pkt_curr_buf_tc6_cnt = 0;
442 stats->pkt_curr_buf_tc7_cnt = 0;
443}
444
445static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
446{
447#define HCLGE_32_BIT_CMD_NUM 8
448#define HCLGE_32_BIT_RTN_DATANUM 8
449
450 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
451 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 452 __le32 *desc_data;
46a3df9f
S		 453 int i, k, n;
454 u64 *data;
455 int ret;
456
457 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
458 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
459
460 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
461 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
462 if (ret) {
463 dev_err(&hdev->pdev->dev,
464 "Get 32 bit pkt stats fail, status = %d.\n", ret);
465
466 return ret;
467 }
468
469 hclge_reset_partial_32bit_counter(all_32_bit_stats);
470 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
471 if (unlikely(i == 0)) {
a90bb9a5
YL		 472 __le16 *desc_data_16bit;
473
46a3df9f 474 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 475 le32_to_cpu(desc[i].data[0]);
476
477 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 478 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 479 le16_to_cpu(*desc_data_16bit);
480
481 desc_data_16bit++;
46a3df9f 482 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 483 le16_to_cpu(*desc_data_16bit);
46a3df9f 484
a90bb9a5 485 desc_data = &desc[i].data[2];
46a3df9f
S		 486 n = HCLGE_32_BIT_RTN_DATANUM - 4;
487 } else {
a90bb9a5 488 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 489 n = HCLGE_32_BIT_RTN_DATANUM;
490 }
491 for (k = 0; k < n; k++) {
a90bb9a5 492 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 493 desc_data++;
494 }
495 }
496
497 return 0;
498}
499
500static int hclge_mac_update_stats(struct hclge_dev *hdev)
501{
b42874e4 502#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 503#define HCLGE_RTN_DATA_NUM 4
504
505 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
506 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 507 __le64 *desc_data;
46a3df9f
S		 508 int i, k, n;
509 int ret;
510
511 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
512 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
513 if (ret) {
514 dev_err(&hdev->pdev->dev,
515 "Get MAC pkt stats fail, status = %d.\n", ret);
516
517 return ret;
518 }
519
520 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
521 if (unlikely(i == 0)) {
a90bb9a5 522 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 523 n = HCLGE_RTN_DATA_NUM - 2;
524 } else {
a90bb9a5 525 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 526 n = HCLGE_RTN_DATA_NUM;
527 }
528 for (k = 0; k < n; k++) {
a90bb9a5 529 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 530 desc_data++;
531 }
532 }
533
534 return 0;
535}
536
537static int hclge_tqps_update_stats(struct hnae3_handle *handle)
538{
539 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
540 struct hclge_vport *vport = hclge_get_vport(handle);
541 struct hclge_dev *hdev = vport->back;
542 struct hnae3_queue *queue;
543 struct hclge_desc desc[1];
544 struct hclge_tqp *tqp;
545 int ret, i;
546
547 for (i = 0; i < kinfo->num_tqps; i++) {
548 queue = handle->kinfo.tqp[i];
549 tqp = container_of(queue, struct hclge_tqp, q);
550 /* command : HCLGE_OPC_QUERY_IGU_STAT */
551 hclge_cmd_setup_basic_desc(&desc[0],
552 HCLGE_OPC_QUERY_RX_STATUS,
553 true);
554
a90bb9a5 555 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 556 ret = hclge_cmd_send(&hdev->hw, desc, 1);
557 if (ret) {
558 dev_err(&hdev->pdev->dev,
559 "Query tqp stat fail, status = %d,queue = %d\n",
560 ret, i);
561 return ret;
562 }
563 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 564 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 565 }
566
567 for (i = 0; i < kinfo->num_tqps; i++) {
568 queue = handle->kinfo.tqp[i];
569 tqp = container_of(queue, struct hclge_tqp, q);
570 /* command : HCLGE_OPC_QUERY_IGU_STAT */
571 hclge_cmd_setup_basic_desc(&desc[0],
572 HCLGE_OPC_QUERY_TX_STATUS,
573 true);
574
a90bb9a5 575 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 576 ret = hclge_cmd_send(&hdev->hw, desc, 1);
577 if (ret) {
578 dev_err(&hdev->pdev->dev,
579 "Query tqp stat fail, status = %d,queue = %d\n",
580 ret, i);
581 return ret;
582 }
583 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 584 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 585 }
586
587 return 0;
588}
589
590static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
591{
592 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
593 struct hclge_tqp *tqp;
594 u64 *buff = data;
595 int i;
596
597 for (i = 0; i < kinfo->num_tqps; i++) {
598 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 599 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 600 }
601
602 for (i = 0; i < kinfo->num_tqps; i++) {
603 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 604 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 605 }
606
607 return buff;
608}
609
610static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
611{
612 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
613
614 return kinfo->num_tqps * (2);
615}
616
617static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
618{
619 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
620 u8 *buff = data;
621 int i = 0;
622
623 for (i = 0; i < kinfo->num_tqps; i++) {
624 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
625 struct hclge_tqp, q);
c36317be 626 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
46a3df9f
S		 627 tqp->index);
628 buff = buff + ETH_GSTRING_LEN;
629 }
630
631 for (i = 0; i < kinfo->num_tqps; i++) {
632 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
633 struct hclge_tqp, q);
c36317be 634 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
46a3df9f
S		 635 tqp->index);
636 buff = buff + ETH_GSTRING_LEN;
637 }
638
639 return buff;
640}
641
642static u64 *hclge_comm_get_stats(void *comm_stats,
643 const struct hclge_comm_stats_str strs[],
644 int size, u64 *data)
645{
646 u64 *buf = data;
647 u32 i;
648
649 for (i = 0; i < size; i++)
650 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
651
652 return buf + size;
653}
654
655static u8 *hclge_comm_get_strings(u32 stringset,
656 const struct hclge_comm_stats_str strs[],
657 int size, u8 *data)
658{
659 char *buff = (char *)data;
660 u32 i;
661
662 if (stringset != ETH_SS_STATS)
663 return buff;
664
665 for (i = 0; i < size; i++) {
666 snprintf(buff, ETH_GSTRING_LEN,
667 strs[i].desc);
668 buff = buff + ETH_GSTRING_LEN;
669 }
670
671 return (u8 *)buff;
672}
673
674static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
675 struct net_device_stats *net_stats)
676{
677 net_stats->tx_dropped = 0;
678 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
679 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
680 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
681
f3426583 682 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 683 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
46a3df9f
S		 684 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
685 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
c36317be 686 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 687
688 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
689 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
690
c36317be 691 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 692 net_stats->rx_length_errors =
693 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
694 net_stats->rx_length_errors +=
f3426583 695 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 696 net_stats->rx_over_errors =
f3426583 697 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 698}
699
700static void hclge_update_stats_for_all(struct hclge_dev *hdev)
701{
702 struct hnae3_handle *handle;
703 int status;
704
705 handle = &hdev->vport[0].nic;
706 if (handle->client) {
707 status = hclge_tqps_update_stats(handle);
708 if (status) {
709 dev_err(&hdev->pdev->dev,
710 "Update TQPS stats fail, status = %d.\n",
711 status);
712 }
713 }
714
715 status = hclge_mac_update_stats(hdev);
716 if (status)
717 dev_err(&hdev->pdev->dev,
718 "Update MAC stats fail, status = %d.\n", status);
719
720 status = hclge_32_bit_update_stats(hdev);
721 if (status)
722 dev_err(&hdev->pdev->dev,
723 "Update 32 bit stats fail, status = %d.\n",
724 status);
725
726 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
727}
728
729static void hclge_update_stats(struct hnae3_handle *handle,
730 struct net_device_stats *net_stats)
731{
732 struct hclge_vport *vport = hclge_get_vport(handle);
733 struct hclge_dev *hdev = vport->back;
734 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
735 int status;
736
7a5d2a39
JS		 737 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
738 return;
739
46a3df9f
S		 740 status = hclge_mac_update_stats(hdev);
741 if (status)
742 dev_err(&hdev->pdev->dev,
743 "Update MAC stats fail, status = %d.\n",
744 status);
745
746 status = hclge_32_bit_update_stats(hdev);
747 if (status)
748 dev_err(&hdev->pdev->dev,
749 "Update 32 bit stats fail, status = %d.\n",
750 status);
751
752 status = hclge_64_bit_update_stats(hdev);
753 if (status)
754 dev_err(&hdev->pdev->dev,
755 "Update 64 bit stats fail, status = %d.\n",
756 status);
757
758 status = hclge_tqps_update_stats(handle);
759 if (status)
760 dev_err(&hdev->pdev->dev,
761 "Update TQPS stats fail, status = %d.\n",
762 status);
763
764 hclge_update_netstat(hw_stats, net_stats);
7a5d2a39
JS		 765
766 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 767}
768
769static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
770{
771#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
772
773 struct hclge_vport *vport = hclge_get_vport(handle);
774 struct hclge_dev *hdev = vport->back;
775 int count = 0;
776
777 /* Loopback test support rules:
778 * mac: only GE mode support
779 * serdes: all mac mode will support include GE/XGE/LGE/CGE
780 * phy: only support when phy device exist on board
781 */
782 if (stringset == ETH_SS_TEST) {
783 /* clear loopback bit flags at first */
784 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
785 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
786 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
787 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
788 count += 1;
789 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
46a3df9f 790 }
2fd5416a
YL		 791
792 count ++;
793 handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK;
46a3df9f
S		 794 } else if (stringset == ETH_SS_STATS) {
795 count = ARRAY_SIZE(g_mac_stats_string) +
796 ARRAY_SIZE(g_all_32bit_stats_string) +
797 ARRAY_SIZE(g_all_64bit_stats_string) +
798 hclge_tqps_get_sset_count(handle, stringset);
799 }
800
801 return count;
802}
803
804static void hclge_get_strings(struct hnae3_handle *handle,
805 u32 stringset,
806 u8 *data)
807{
808 u8 *p = (char *)data;
809 int size;
810
811 if (stringset == ETH_SS_STATS) {
812 size = ARRAY_SIZE(g_mac_stats_string);
813 p = hclge_comm_get_strings(stringset,
814 g_mac_stats_string,
815 size,
816 p);
817 size = ARRAY_SIZE(g_all_32bit_stats_string);
818 p = hclge_comm_get_strings(stringset,
819 g_all_32bit_stats_string,
820 size,
821 p);
822 size = ARRAY_SIZE(g_all_64bit_stats_string);
823 p = hclge_comm_get_strings(stringset,
824 g_all_64bit_stats_string,
825 size,
826 p);
827 p = hclge_tqps_get_strings(handle, p);
828 } else if (stringset == ETH_SS_TEST) {
829 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
830 memcpy(p,
831 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
832 ETH_GSTRING_LEN);
833 p += ETH_GSTRING_LEN;
834 }
835 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
836 memcpy(p,
837 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
838 ETH_GSTRING_LEN);
839 p += ETH_GSTRING_LEN;
840 }
841 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
842 memcpy(p,
843 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
844 ETH_GSTRING_LEN);
845 p += ETH_GSTRING_LEN;
846 }
847 }
848}
849
850static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
851{
852 struct hclge_vport *vport = hclge_get_vport(handle);
853 struct hclge_dev *hdev = vport->back;
854 u64 *p;
855
856 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
857 g_mac_stats_string,
858 ARRAY_SIZE(g_mac_stats_string),
859 data);
860 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
861 g_all_32bit_stats_string,
862 ARRAY_SIZE(g_all_32bit_stats_string),
863 p);
864 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
865 g_all_64bit_stats_string,
866 ARRAY_SIZE(g_all_64bit_stats_string),
867 p);
868 p = hclge_tqps_get_stats(handle, p);
869}
870
871static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 872 struct hclge_func_status_cmd *status)
46a3df9f
S		 873{
874 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
875 return -EINVAL;
876
877 /* Set the pf to main pf */
878 if (status->pf_state & HCLGE_PF_STATE_MAIN)
879 hdev->flag |= HCLGE_FLAG_MAIN;
880 else
881 hdev->flag &= ~HCLGE_FLAG_MAIN;
882
46a3df9f
S		 883 return 0;
884}
885
886static int hclge_query_function_status(struct hclge_dev *hdev)
887{
d44f9b63 888 struct hclge_func_status_cmd *req;
46a3df9f
S		 889 struct hclge_desc desc;
890 int timeout = 0;
891 int ret;
892
893 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 894 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 895
896 do {
897 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
898 if (ret) {
899 dev_err(&hdev->pdev->dev,
900 "query function status failed %d.\n",
901 ret);
902
903 return ret;
904 }
905
906 /* Check pf reset is done */
907 if (req->pf_state)
908 break;
909 usleep_range(1000, 2000);
910 } while (timeout++ < 5);
911
912 ret = hclge_parse_func_status(hdev, req);
913
914 return ret;
915}
916
917static int hclge_query_pf_resource(struct hclge_dev *hdev)
918{
d44f9b63 919 struct hclge_pf_res_cmd *req;
46a3df9f
S		 920 struct hclge_desc desc;
921 int ret;
922
923 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
924 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
925 if (ret) {
926 dev_err(&hdev->pdev->dev,
927 "query pf resource failed %d.\n", ret);
928 return ret;
929 }
930
d44f9b63 931 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 932 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
933 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
934
e92a0843 935 if (hnae3_dev_roce_supported(hdev)) {
887c3820 936 hdev->num_roce_msi =
e22b531b
HT		 937 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
938 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 939
940 /* PF should have NIC vectors and Roce vectors,
941 * NIC vectors are queued before Roce vectors.
942 */
887c3820 943 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 944 } else {
945 hdev->num_msi =
e22b531b
HT		 946 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
947 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 948 }
949
950 return 0;
951}
952
953static int hclge_parse_speed(int speed_cmd, int *speed)
954{
955 switch (speed_cmd) {
956 case 6:
957 *speed = HCLGE_MAC_SPEED_10M;
958 break;
959 case 7:
960 *speed = HCLGE_MAC_SPEED_100M;
961 break;
962 case 0:
963 *speed = HCLGE_MAC_SPEED_1G;
964 break;
965 case 1:
966 *speed = HCLGE_MAC_SPEED_10G;
967 break;
968 case 2:
969 *speed = HCLGE_MAC_SPEED_25G;
970 break;
971 case 3:
972 *speed = HCLGE_MAC_SPEED_40G;
973 break;
974 case 4:
975 *speed = HCLGE_MAC_SPEED_50G;
976 break;
977 case 5:
978 *speed = HCLGE_MAC_SPEED_100G;
979 break;
980 default:
981 return -EINVAL;
982 }
983
984 return 0;
985}
986
d92ceae9
FL		 987static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
988 u8 speed_ability)
989{
990 unsigned long *supported = hdev->hw.mac.supported;
991
992 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
993 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
994 supported);
995
996 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
997 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
998 supported);
999
1000 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1001 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1002 supported);
1003
1004 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1005 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1006 supported);
1007
1008 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1009 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1010 supported);
1011
1012 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
1013 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1014}
1015
1016static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
1017{
1018 u8 media_type = hdev->hw.mac.media_type;
1019
1020 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
1021 return;
1022
1023 hclge_parse_fiber_link_mode(hdev, speed_ability);
1024}
1025
46a3df9f
S		 1026static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1027{
d44f9b63 1028 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1029 u64 mac_addr_tmp_high;
1030 u64 mac_addr_tmp;
1031 int i;
1032
d44f9b63 1033 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 1034
1035 /* get the configuration */
e22b531b
HT		 1036 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1037 HCLGE_CFG_VMDQ_M,
1038 HCLGE_CFG_VMDQ_S);
1039 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1040 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1041 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1042 HCLGE_CFG_TQP_DESC_N_M,
1043 HCLGE_CFG_TQP_DESC_N_S);
1044
1045 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1046 HCLGE_CFG_PHY_ADDR_M,
1047 HCLGE_CFG_PHY_ADDR_S);
1048 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1049 HCLGE_CFG_MEDIA_TP_M,
1050 HCLGE_CFG_MEDIA_TP_S);
1051 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1052 HCLGE_CFG_RX_BUF_LEN_M,
1053 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 1054 /* get mac_address */
1055 mac_addr_tmp = __le32_to_cpu(req->param[2]);
e22b531b
HT		 1056 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1057 HCLGE_CFG_MAC_ADDR_H_M,
1058 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 1059
1060 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1061
e22b531b
HT		 1062 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1063 HCLGE_CFG_DEFAULT_SPEED_M,
1064 HCLGE_CFG_DEFAULT_SPEED_S);
1065 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1066 HCLGE_CFG_RSS_SIZE_M,
1067 HCLGE_CFG_RSS_SIZE_S);
c408e202 1068
46a3df9f
S		 1069 for (i = 0; i < ETH_ALEN; i++)
1070 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1071
d44f9b63 1072 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 1073 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
d92ceae9 1074
e22b531b
HT		 1075 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1076 HCLGE_CFG_SPEED_ABILITY_M,
1077 HCLGE_CFG_SPEED_ABILITY_S);
46a3df9f
S		 1078}
1079
1080/* hclge_get_cfg: query the static parameter from flash
1081 * @hdev: pointer to struct hclge_dev
1082 * @hcfg: the config structure to be getted
1083 */
1084static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1085{
1086 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 1087 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1088 int i, ret;
1089
1090 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1091 u32 offset = 0;
1092
d44f9b63 1093 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1094 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1095 true);
e22b531b
HT		 1096 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1097 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 1098 /* Len should be united by 4 bytes when send to hardware */
e22b531b
HT		 1099 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1100 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1101 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1102 }
1103
1104 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1105 if (ret) {
e125295a 1106 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
46a3df9f
S		 1107 return ret;
1108 }
1109
1110 hclge_parse_cfg(hcfg, desc);
e125295a 1111
46a3df9f
S		 1112 return 0;
1113}
1114
1115static int hclge_get_cap(struct hclge_dev *hdev)
1116{
1117 int ret;
1118
1119 ret = hclge_query_function_status(hdev);
1120 if (ret) {
1121 dev_err(&hdev->pdev->dev,
1122 "query function status error %d.\n", ret);
1123 return ret;
1124 }
1125
1126 /* get pf resource */
1127 ret = hclge_query_pf_resource(hdev);
e125295a
JS		 1128 if (ret)
1129 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
46a3df9f 1130
e125295a 1131 return ret;
46a3df9f
S		 1132}
1133
1134static int hclge_configure(struct hclge_dev *hdev)
1135{
1136 struct hclge_cfg cfg;
1137 int ret, i;
1138
1139 ret = hclge_get_cfg(hdev, &cfg);
1140 if (ret) {
1141 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1142 return ret;
1143 }
1144
1145 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1146 hdev->base_tqp_pid = 0;
c408e202 1147 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 1148 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1149 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1150 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1151 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1152 hdev->num_desc = cfg.tqp_desc_num;
1153 hdev->tm_info.num_pg = 1;
cacde272 1154 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1155 hdev->tm_info.hw_pfc_map = 0;
1156
1157 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1158 if (ret) {
1159 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1160 return ret;
1161 }
1162
d92ceae9
FL		 1163 hclge_parse_link_mode(hdev, cfg.speed_ability);
1164
cacde272
YL		 1165 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1166 (hdev->tc_max < 1)) {
46a3df9f 1167 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1168 hdev->tc_max);
1169 hdev->tc_max = 1;
46a3df9f
S		 1170 }
1171
cacde272
YL		 1172 /* Dev does not support DCB */
1173 if (!hnae3_dev_dcb_supported(hdev)) {
1174 hdev->tc_max = 1;
1175 hdev->pfc_max = 0;
1176 } else {
1177 hdev->pfc_max = hdev->tc_max;
1178 }
1179
1180 hdev->tm_info.num_tc = hdev->tc_max;
1181
46a3df9f 1182 /* Currently not support uncontiuous tc */
cacde272 1183 for (i = 0; i < hdev->tm_info.num_tc; i++)
e22b531b 1184 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 1185
f8362fe1 1186 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 1187
1188 return ret;
1189}
1190
1191static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1192 int tso_mss_max)
1193{
d44f9b63 1194 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1195 struct hclge_desc desc;
a90bb9a5 1196 u16 tso_mss;
46a3df9f
S		 1197
1198 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1199
d44f9b63 1200 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1201
1202 tso_mss = 0;
e22b531b
HT		 1203 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1204 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1205 req->tso_mss_min = cpu_to_le16(tso_mss);
1206
1207 tso_mss = 0;
e22b531b
HT		 1208 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1209 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1210 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1211
1212 return hclge_cmd_send(&hdev->hw, &desc, 1);
1213}
1214
1215static int hclge_alloc_tqps(struct hclge_dev *hdev)
1216{
1217 struct hclge_tqp *tqp;
1218 int i;
1219
1220 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1221 sizeof(struct hclge_tqp), GFP_KERNEL);
1222 if (!hdev->htqp)
1223 return -ENOMEM;
1224
1225 tqp = hdev->htqp;
1226
1227 for (i = 0; i < hdev->num_tqps; i++) {
1228 tqp->dev = &hdev->pdev->dev;
1229 tqp->index = i;
1230
1231 tqp->q.ae_algo = &ae_algo;
1232 tqp->q.buf_size = hdev->rx_buf_len;
1233 tqp->q.desc_num = hdev->num_desc;
1234 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1235 i * HCLGE_TQP_REG_SIZE;
1236
1237 tqp++;
1238 }
1239
1240 return 0;
1241}
1242
1243static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1244 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1245{
d44f9b63 1246 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1247 struct hclge_desc desc;
1248 int ret;
1249
1250 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1251
d44f9b63 1252 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1253 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1254 req->tqp_vf = func_id;
46a3df9f
S		 1255 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1256 1 << HCLGE_TQP_MAP_EN_B;
1257 req->tqp_vid = cpu_to_le16(tqp_vid);
1258
1259 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a
JS		 1260 if (ret)
1261 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
46a3df9f 1262
e125295a 1263 return ret;
46a3df9f
S		 1264}
1265
1266static int hclge_assign_tqp(struct hclge_vport *vport,
1267 struct hnae3_queue **tqp, u16 num_tqps)
1268{
1269 struct hclge_dev *hdev = vport->back;
7df7dad6 1270 int i, alloced;
46a3df9f
S		 1271
1272 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1273 alloced < num_tqps; i++) {
1274 if (!hdev->htqp[i].alloced) {
1275 hdev->htqp[i].q.handle = &vport->nic;
1276 hdev->htqp[i].q.tqp_index = alloced;
1277 tqp[alloced] = &hdev->htqp[i].q;
1278 hdev->htqp[i].alloced = true;
46a3df9f
S		 1279 alloced++;
1280 }
1281 }
1282 vport->alloc_tqps = num_tqps;
1283
1284 return 0;
1285}
1286
1287static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1288{
1289 struct hnae3_handle *nic = &vport->nic;
1290 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1291 struct hclge_dev *hdev = vport->back;
1292 int i, ret;
1293
1294 kinfo->num_desc = hdev->num_desc;
1295 kinfo->rx_buf_len = hdev->rx_buf_len;
1296 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1297 kinfo->rss_size
1298 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1299 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1300
1301 for (i = 0; i < HNAE3_MAX_TC; i++) {
1302 if (hdev->hw_tc_map & BIT(i)) {
1303 kinfo->tc_info[i].enable = true;
1304 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1305 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1306 kinfo->tc_info[i].tc = i;
1307 } else {
1308 /* Set to default queue if TC is disable */
1309 kinfo->tc_info[i].enable = false;
1310 kinfo->tc_info[i].tqp_offset = 0;
1311 kinfo->tc_info[i].tqp_count = 1;
1312 kinfo->tc_info[i].tc = 0;
1313 }
1314 }
1315
1316 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1317 sizeof(struct hnae3_queue *), GFP_KERNEL);
1318 if (!kinfo->tqp)
1319 return -ENOMEM;
1320
1321 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
e125295a 1322 if (ret)
46a3df9f 1323 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
46a3df9f 1324
e125295a 1325 return ret;
46a3df9f
S		 1326}
1327
7df7dad6
L		 1328static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1329 struct hclge_vport *vport)
1330{
1331 struct hnae3_handle *nic = &vport->nic;
1332 struct hnae3_knic_private_info *kinfo;
1333 u16 i;
1334
1335 kinfo = &nic->kinfo;
1336 for (i = 0; i < kinfo->num_tqps; i++) {
1337 struct hclge_tqp *q =
1338 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1339 bool is_pf;
1340 int ret;
1341
1342 is_pf = !(vport->vport_id);
1343 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1344 i, is_pf);
1345 if (ret)
1346 return ret;
1347 }
1348
1349 return 0;
1350}
1351
1352static int hclge_map_tqp(struct hclge_dev *hdev)
1353{
1354 struct hclge_vport *vport = hdev->vport;
1355 u16 i, num_vport;
1356
1357 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1358 for (i = 0; i < num_vport; i++) {
1359 int ret;
1360
1361 ret = hclge_map_tqp_to_vport(hdev, vport);
1362 if (ret)
1363 return ret;
1364
1365 vport++;
1366 }
1367
1368 return 0;
1369}
1370
46a3df9f
S		 1371static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1372{
1373 /* this would be initialized later */
1374}
1375
1376static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1377{
1378 struct hnae3_handle *nic = &vport->nic;
1379 struct hclge_dev *hdev = vport->back;
1380 int ret;
1381
1382 nic->pdev = hdev->pdev;
1383 nic->ae_algo = &ae_algo;
1384 nic->numa_node_mask = hdev->numa_node_mask;
1385
1386 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1387 ret = hclge_knic_setup(vport, num_tqps);
1388 if (ret) {
1389 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1390 ret);
1391 return ret;
1392 }
1393 } else {
1394 hclge_unic_setup(vport, num_tqps);
1395 }
1396
1397 return 0;
1398}
1399
1400static int hclge_alloc_vport(struct hclge_dev *hdev)
1401{
1402 struct pci_dev *pdev = hdev->pdev;
1403 struct hclge_vport *vport;
1404 u32 tqp_main_vport;
1405 u32 tqp_per_vport;
1406 int num_vport, i;
1407 int ret;
1408
1409 /* We need to alloc a vport for main NIC of PF */
1410 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1411
b76edfb2
HT		 1412 if (hdev->num_tqps < num_vport) {
1413 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1414 hdev->num_tqps, num_vport);
1415 return -EINVAL;
1416 }
46a3df9f
S		 1417
1418 /* Alloc the same number of TQPs for every vport */
1419 tqp_per_vport = hdev->num_tqps / num_vport;
1420 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1421
1422 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1423 GFP_KERNEL);
1424 if (!vport)
1425 return -ENOMEM;
1426
1427 hdev->vport = vport;
1428 hdev->num_alloc_vport = num_vport;
1429
bc59f827
FL		 1430 if (IS_ENABLED(CONFIG_PCI_IOV))
1431 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1432
1433 for (i = 0; i < num_vport; i++) {
1434 vport->back = hdev;
1435 vport->vport_id = i;
1436
1437 if (i == 0)
1438 ret = hclge_vport_setup(vport, tqp_main_vport);
1439 else
1440 ret = hclge_vport_setup(vport, tqp_per_vport);
1441 if (ret) {
1442 dev_err(&pdev->dev,
1443 "vport setup failed for vport %d, %d\n",
1444 i, ret);
1445 return ret;
1446 }
1447
1448 vport++;
1449 }
1450
1451 return 0;
1452}
1453
acf61ecd
YL		 1454static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1455 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1456{
1457/* TX buffer size is unit by 128 byte */
1458#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1459#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1460 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1461 struct hclge_desc desc;
1462 int ret;
1463 u8 i;
1464
d44f9b63 1465 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1466
1467 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1468 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1469 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1470
46a3df9f
S		 1471 req->tx_pkt_buff[i] =
1472 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1473 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1474 }
46a3df9f
S		 1475
1476 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 1477 if (ret)
46a3df9f
S		 1478 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1479 ret);
46a3df9f 1480
e125295a 1481 return ret;
46a3df9f
S		 1482}
1483
acf61ecd
YL		 1484static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1485 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1486{
acf61ecd 1487 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1488
e125295a
JS		 1489 if (ret)
1490 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
46a3df9f 1491
e125295a 1492 return ret;
46a3df9f
S		 1493}
1494
1495static int hclge_get_tc_num(struct hclge_dev *hdev)
1496{
1497 int i, cnt = 0;
1498
1499 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1500 if (hdev->hw_tc_map & BIT(i))
1501 cnt++;
1502 return cnt;
1503}
1504
1505static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1506{
1507 int i, cnt = 0;
1508
1509 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1510 if (hdev->hw_tc_map & BIT(i) &&
1511 hdev->tm_info.hw_pfc_map & BIT(i))
1512 cnt++;
1513 return cnt;
1514}
1515
1516/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1517static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1518 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1519{
1520 struct hclge_priv_buf *priv;
1521 int i, cnt = 0;
1522
1523 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1524 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1525 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1526 priv->enable)
1527 cnt++;
1528 }
1529
1530 return cnt;
1531}
1532
1533/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1534static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1535 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1536{
1537 struct hclge_priv_buf *priv;
1538 int i, cnt = 0;
1539
1540 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1541 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1542 if (hdev->hw_tc_map & BIT(i) &&
1543 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1544 priv->enable)
1545 cnt++;
1546 }
1547
1548 return cnt;
1549}
1550
acf61ecd 1551static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1552{
1553 struct hclge_priv_buf *priv;
1554 u32 rx_priv = 0;
1555 int i;
1556
1557 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1558 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1559 if (priv->enable)
1560 rx_priv += priv->buf_size;
1561 }
1562 return rx_priv;
1563}
1564
acf61ecd 1565static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1566{
1567 u32 i, total_tx_size = 0;
1568
1569 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1570 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1571
1572 return total_tx_size;
1573}
1574
acf61ecd
YL		 1575static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1576 struct hclge_pkt_buf_alloc *buf_alloc,
1577 u32 rx_all)
46a3df9f
S		 1578{
1579 u32 shared_buf_min, shared_buf_tc, shared_std;
1580 int tc_num, pfc_enable_num;
1581 u32 shared_buf;
1582 u32 rx_priv;
1583 int i;
1584
1585 tc_num = hclge_get_tc_num(hdev);
1586 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1587
d221df4e
YL		 1588 if (hnae3_dev_dcb_supported(hdev))
1589 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1590 else
1591 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1592
46a3df9f
S		 1593 shared_buf_tc = pfc_enable_num * hdev->mps +
1594 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1595 hdev->mps;
1596 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1597
acf61ecd 1598 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1599 if (rx_all <= rx_priv + shared_std)
1600 return false;
1601
1602 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1603 buf_alloc->s_buf.buf_size = shared_buf;
1604 buf_alloc->s_buf.self.high = shared_buf;
1605 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1606
1607 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1608 if ((hdev->hw_tc_map & BIT(i)) &&
1609 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1610 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1611 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1612 } else {
acf61ecd
YL		 1613 buf_alloc->s_buf.tc_thrd[i].low = 0;
1614 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1615 }
1616 }
1617
1618 return true;
1619}
1620
acf61ecd
YL		 1621static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1622 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1623{
1624 u32 i, total_size;
1625
1626 total_size = hdev->pkt_buf_size;
1627
1628 /* alloc tx buffer for all enabled tc */
1629 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1630 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1631
1632 if (total_size < HCLGE_DEFAULT_TX_BUF)
1633 return -ENOMEM;
1634
1635 if (hdev->hw_tc_map & BIT(i))
1636 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1637 else
1638 priv->tx_buf_size = 0;
1639
1640 total_size -= priv->tx_buf_size;
1641 }
1642
1643 return 0;
1644}
1645
46a3df9f
S		 1646/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1647 * @hdev: pointer to struct hclge_dev
acf61ecd 1648 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1649 * @return: 0: calculate sucessful, negative: fail
1650 */
1db9b1bf
YL		 1651static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1652 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1653{
9ffe79a9 1654 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1655 int no_pfc_priv_num, pfc_priv_num;
1656 struct hclge_priv_buf *priv;
1657 int i;
1658
acf61ecd 1659 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1660
d602a525
YL		 1661 /* When DCB is not supported, rx private
1662 * buffer is not allocated.
1663 */
1664 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1665 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1666 return -ENOMEM;
1667
1668 return 0;
1669 }
1670
46a3df9f
S		 1671 /* step 1, try to alloc private buffer for all enabled tc */
1672 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1673 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1674 if (hdev->hw_tc_map & BIT(i)) {
1675 priv->enable = 1;
1676 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1677 priv->wl.low = hdev->mps;
1678 priv->wl.high = priv->wl.low + hdev->mps;
1679 priv->buf_size = priv->wl.high +
1680 HCLGE_DEFAULT_DV;
1681 } else {
1682 priv->wl.low = 0;
1683 priv->wl.high = 2 * hdev->mps;
1684 priv->buf_size = priv->wl.high;
1685 }
bb1fe9ea
YL		 1686 } else {
1687 priv->enable = 0;
1688 priv->wl.low = 0;
1689 priv->wl.high = 0;
1690 priv->buf_size = 0;
46a3df9f
S		 1691 }
1692 }
1693
acf61ecd 1694 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1695 return 0;
1696
1697 /* step 2, try to decrease the buffer size of
1698 * no pfc TC's private buffer
1699 */
1700 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1701 priv = &buf_alloc->priv_buf[i];
46a3df9f 1702
bb1fe9ea
YL		 1703 priv->enable = 0;
1704 priv->wl.low = 0;
1705 priv->wl.high = 0;
1706 priv->buf_size = 0;
1707
1708 if (!(hdev->hw_tc_map & BIT(i)))
1709 continue;
1710
1711 priv->enable = 1;
46a3df9f
S		 1712
1713 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1714 priv->wl.low = 128;
1715 priv->wl.high = priv->wl.low + hdev->mps;
1716 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1717 } else {
1718 priv->wl.low = 0;
1719 priv->wl.high = hdev->mps;
1720 priv->buf_size = priv->wl.high;
1721 }
1722 }
1723
acf61ecd 1724 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1725 return 0;
1726
1727 /* step 3, try to reduce the number of pfc disabled TCs,
1728 * which have private buffer
1729 */
1730 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1731 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1732
1733 /* let the last to be cleared first */
1734 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1735 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1736
1737 if (hdev->hw_tc_map & BIT(i) &&
1738 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1739 /* Clear the no pfc TC private buffer */
1740 priv->wl.low = 0;
1741 priv->wl.high = 0;
1742 priv->buf_size = 0;
1743 priv->enable = 0;
1744 no_pfc_priv_num--;
1745 }
1746
acf61ecd 1747 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1748 no_pfc_priv_num == 0)
1749 break;
1750 }
1751
acf61ecd 1752 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1753 return 0;
1754
1755 /* step 4, try to reduce the number of pfc enabled TCs
1756 * which have private buffer.
1757 */
acf61ecd 1758 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1759
1760 /* let the last to be cleared first */
1761 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1762 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1763
1764 if (hdev->hw_tc_map & BIT(i) &&
1765 hdev->tm_info.hw_pfc_map & BIT(i)) {
1766 /* Reduce the number of pfc TC with private buffer */
1767 priv->wl.low = 0;
1768 priv->enable = 0;
1769 priv->wl.high = 0;
1770 priv->buf_size = 0;
1771 pfc_priv_num--;
1772 }
1773
acf61ecd 1774 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1775 pfc_priv_num == 0)
1776 break;
1777 }
acf61ecd 1778 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1779 return 0;
1780
1781 return -ENOMEM;
1782}
1783
acf61ecd
YL		 1784static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1785 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1786{
d44f9b63 1787 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1788 struct hclge_desc desc;
1789 int ret;
1790 int i;
1791
1792 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1793 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1794
1795 /* Alloc private buffer TCs */
1796 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1797 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1798
1799 req->buf_num[i] =
1800 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1801 req->buf_num[i] |=
5bca3b94 1802 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1803 }
1804
b8c8bf47 1805 req->shared_buf =
acf61ecd 1806 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1807 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1808
46a3df9f 1809 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 1810 if (ret)
46a3df9f
S		 1811 dev_err(&hdev->pdev->dev,
1812 "rx private buffer alloc cmd failed %d\n", ret);
46a3df9f 1813
e125295a 1814 return ret;
46a3df9f
S		 1815}
1816
acf61ecd
YL		 1817static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1818 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1819{
1820 struct hclge_rx_priv_wl_buf *req;
1821 struct hclge_priv_buf *priv;
1822 struct hclge_desc desc[2];
1823 int i, j;
1824 int ret;
1825
1826 for (i = 0; i < 2; i++) {
1827 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1828 false);
1829 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1830
1831 /* The first descriptor set the NEXT bit to 1 */
1832 if (i == 0)
1833 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1834 else
1835 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1836
1837 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1838 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1839
1840 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1841 req->tc_wl[j].high =
1842 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1843 req->tc_wl[j].high |=
1b9980c7 1844 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1845 req->tc_wl[j].low =
1846 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1847 req->tc_wl[j].low |=
1b9980c7 1848 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1849 }
1850 }
1851
1852 /* Send 2 descriptor at one time */
1853 ret = hclge_cmd_send(&hdev->hw, desc, 2);
e125295a 1854 if (ret)
46a3df9f
S		 1855 dev_err(&hdev->pdev->dev,
1856 "rx private waterline config cmd failed %d\n",
1857 ret);
e125295a 1858 return ret;
46a3df9f
S		 1859}
1860
acf61ecd
YL		 1861static int hclge_common_thrd_config(struct hclge_dev *hdev,
1862 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1863{
acf61ecd 1864 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1865 struct hclge_rx_com_thrd *req;
1866 struct hclge_desc desc[2];
1867 struct hclge_tc_thrd *tc;
1868 int i, j;
1869 int ret;
1870
1871 for (i = 0; i < 2; i++) {
1872 hclge_cmd_setup_basic_desc(&desc[i],
1873 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1874 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1875
1876 /* The first descriptor set the NEXT bit to 1 */
1877 if (i == 0)
1878 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1879 else
1880 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1881
1882 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1883 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1884
1885 req->com_thrd[j].high =
1886 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1887 req->com_thrd[j].high |=
1b9980c7 1888 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1889 req->com_thrd[j].low =
1890 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1891 req->com_thrd[j].low |=
1b9980c7 1892 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1893 }
1894 }
1895
1896 /* Send 2 descriptors at one time */
1897 ret = hclge_cmd_send(&hdev->hw, desc, 2);
e125295a 1898 if (ret)
46a3df9f
S		 1899 dev_err(&hdev->pdev->dev,
1900 "common threshold config cmd failed %d\n", ret);
e125295a 1901 return ret;
46a3df9f
S		 1902}
1903
acf61ecd
YL		 1904static int hclge_common_wl_config(struct hclge_dev *hdev,
1905 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1906{
acf61ecd 1907 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1908 struct hclge_rx_com_wl *req;
1909 struct hclge_desc desc;
1910 int ret;
1911
1912 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1913
1914 req = (struct hclge_rx_com_wl *)desc.data;
1915 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1b9980c7 1916 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1917
1918 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1b9980c7 1919 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1920
1921 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 1922 if (ret)
46a3df9f
S		 1923 dev_err(&hdev->pdev->dev,
1924 "common waterline config cmd failed %d\n", ret);
e125295a 1925 return ret;
46a3df9f
S		 1926}
1927
1928int hclge_buffer_alloc(struct hclge_dev *hdev)
1929{
acf61ecd 1930 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1931 int ret;
1932
acf61ecd
YL		 1933 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1934 if (!pkt_buf)
46a3df9f
S		 1935 return -ENOMEM;
1936
acf61ecd 1937 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1938 if (ret) {
1939 dev_err(&hdev->pdev->dev,
1940 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1941 goto out;
9ffe79a9
YL		 1942 }
1943
acf61ecd 1944 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1945 if (ret) {
1946 dev_err(&hdev->pdev->dev,
1947 "could not alloc tx buffers %d\n", ret);
acf61ecd 1948 goto out;
46a3df9f
S		 1949 }
1950
acf61ecd 1951 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1952 if (ret) {
1953 dev_err(&hdev->pdev->dev,
1954 "could not calc rx priv buffer size for all TCs %d\n",
1955 ret);
acf61ecd 1956 goto out;
46a3df9f
S		 1957 }
1958
acf61ecd 1959 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1960 if (ret) {
1961 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1962 ret);
acf61ecd 1963 goto out;
46a3df9f
S		 1964 }
1965
2daf4a65 1966 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1967 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1968 if (ret) {
1969 dev_err(&hdev->pdev->dev,
1970 "could not configure rx private waterline %d\n",
1971 ret);
acf61ecd 1972 goto out;
2daf4a65 1973 }
46a3df9f 1974
acf61ecd 1975 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1976 if (ret) {
1977 dev_err(&hdev->pdev->dev,
1978 "could not configure common threshold %d\n",
1979 ret);
acf61ecd 1980 goto out;
2daf4a65 1981 }
46a3df9f
S		 1982 }
1983
acf61ecd
YL		 1984 ret = hclge_common_wl_config(hdev, pkt_buf);
1985 if (ret)
46a3df9f
S		 1986 dev_err(&hdev->pdev->dev,
1987 "could not configure common waterline %d\n", ret);
46a3df9f 1988
acf61ecd
YL		 1989out:
1990 kfree(pkt_buf);
1991 return ret;
46a3df9f
S		 1992}
1993
1994static int hclge_init_roce_base_info(struct hclge_vport *vport)
1995{
1996 struct hnae3_handle *roce = &vport->roce;
1997 struct hnae3_handle *nic = &vport->nic;
1998
887c3820 1999 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 2000
2001 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2002 vport->back->num_msi_left == 0)
2003 return -EINVAL;
2004
2005 roce->rinfo.base_vector = vport->back->roce_base_vector;
2006
2007 roce->rinfo.netdev = nic->kinfo.netdev;
2008 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2009
2010 roce->pdev = nic->pdev;
2011 roce->ae_algo = nic->ae_algo;
2012 roce->numa_node_mask = nic->numa_node_mask;
2013
2014 return 0;
2015}
2016
887c3820 2017static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 2018{
2019 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 2020 int vectors;
2021 int i;
46a3df9f 2022
887c3820
SM		 2023 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2024 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2025 if (vectors < 0) {
2026 dev_err(&pdev->dev,
2027 "failed(%d) to allocate MSI/MSI-X vectors\n",
2028 vectors);
2029 return vectors;
46a3df9f 2030 }
887c3820
SM		 2031 if (vectors < hdev->num_msi)
2032 dev_warn(&hdev->pdev->dev,
2033 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2034 hdev->num_msi, vectors);
46a3df9f 2035
887c3820
SM		 2036 hdev->num_msi = vectors;
2037 hdev->num_msi_left = vectors;
2038 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 2039 hdev->roce_base_vector = hdev->base_msi_vector +
2040 HCLGE_ROCE_VECTOR_OFFSET;
2041
46a3df9f
S		 2042 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2043 sizeof(u16), GFP_KERNEL);
887c3820
SM		 2044 if (!hdev->vector_status) {
2045 pci_free_irq_vectors(pdev);
46a3df9f 2046 return -ENOMEM;
887c3820 2047 }
46a3df9f
S		 2048
2049 for (i = 0; i < hdev->num_msi; i++)
2050 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2051
887c3820
SM		 2052 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2053 sizeof(int), GFP_KERNEL);
2054 if (!hdev->vector_irq) {
2055 pci_free_irq_vectors(pdev);
2056 return -ENOMEM;
46a3df9f 2057 }
46a3df9f
S		 2058
2059 return 0;
2060}
2061
2062static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2063{
2064 struct hclge_mac *mac = &hdev->hw.mac;
2065
2066 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2067 mac->duplex = (u8)duplex;
2068 else
2069 mac->duplex = HCLGE_MAC_FULL;
2070
2071 mac->speed = speed;
2072}
2073
2074int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2075{
d44f9b63 2076 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2077 struct hclge_desc desc;
2078 int ret;
2079
d44f9b63 2080 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2081
2082 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2083
e22b531b 2084 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 2085
2086 switch (speed) {
2087 case HCLGE_MAC_SPEED_10M:
e22b531b
HT		 2088 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2089 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 2090 break;
2091 case HCLGE_MAC_SPEED_100M:
e22b531b
HT		 2092 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2093 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 2094 break;
2095 case HCLGE_MAC_SPEED_1G:
e22b531b
HT		 2096 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2097 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 2098 break;
2099 case HCLGE_MAC_SPEED_10G:
e22b531b
HT		 2100 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2101 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 2102 break;
2103 case HCLGE_MAC_SPEED_25G:
e22b531b
HT		 2104 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2105 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 2106 break;
2107 case HCLGE_MAC_SPEED_40G:
e22b531b
HT		 2108 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2109 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 2110 break;
2111 case HCLGE_MAC_SPEED_50G:
e22b531b
HT		 2112 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2113 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 2114 break;
2115 case HCLGE_MAC_SPEED_100G:
e22b531b
HT		 2116 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2117 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 2118 break;
2119 default:
d7629e74 2120 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2121 return -EINVAL;
2122 }
2123
e22b531b
HT		 2124 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2125 1);
46a3df9f
S		 2126
2127 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2128 if (ret) {
2129 dev_err(&hdev->pdev->dev,
2130 "mac speed/duplex config cmd failed %d.\n", ret);
2131 return ret;
2132 }
2133
2134 hclge_check_speed_dup(hdev, duplex, speed);
2135
2136 return 0;
2137}
2138
2139static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2140 u8 duplex)
2141{
2142 struct hclge_vport *vport = hclge_get_vport(handle);
2143 struct hclge_dev *hdev = vport->back;
2144
2145 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2146}
2147
2148static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2149 u8 *duplex)
2150{
d44f9b63 2151 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2152 struct hclge_desc desc;
2153 int speed_tmp;
2154 int ret;
2155
d44f9b63 2156 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2157
2158 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2159 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2160 if (ret) {
2161 dev_err(&hdev->pdev->dev,
2162 "mac speed/autoneg/duplex query cmd failed %d\n",
2163 ret);
2164 return ret;
2165 }
2166
e22b531b
HT		 2167 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2168 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2169 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 2170
2171 ret = hclge_parse_speed(speed_tmp, speed);
e125295a 2172 if (ret)
46a3df9f
S		 2173 dev_err(&hdev->pdev->dev,
2174 "could not parse speed(=%d), %d\n", speed_tmp, ret);
46a3df9f 2175
e125295a 2176 return ret;
46a3df9f
S		 2177}
2178
46a3df9f
S		 2179static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2180{
d44f9b63 2181 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2182 struct hclge_desc desc;
a90bb9a5 2183 u32 flag = 0;
46a3df9f
S		 2184 int ret;
2185
2186 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2187
d44f9b63 2188 req = (struct hclge_config_auto_neg_cmd *)desc.data;
e22b531b 2189 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 2190 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2191
2192 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 2193 if (ret)
46a3df9f
S		 2194 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2195 ret);
46a3df9f 2196
e125295a 2197 return ret;
46a3df9f
S		 2198}
2199
2200static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2201{
2202 struct hclge_vport *vport = hclge_get_vport(handle);
2203 struct hclge_dev *hdev = vport->back;
2204
2205 return hclge_set_autoneg_en(hdev, enable);
2206}
2207
2208static int hclge_get_autoneg(struct hnae3_handle *handle)
2209{
2210 struct hclge_vport *vport = hclge_get_vport(handle);
2211 struct hclge_dev *hdev = vport->back;
9ff804ee
FL		 2212 struct phy_device *phydev = hdev->hw.mac.phydev;
2213
2214 if (phydev)
2215 return phydev->autoneg;
46a3df9f
S		 2216
2217 return hdev->hw.mac.autoneg;
2218}
2219
6f712727
PL		 2220static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2221 bool mask_vlan,
2222 u8 *mac_mask)
2223{
2224 struct hclge_mac_vlan_mask_entry_cmd *req;
2225 struct hclge_desc desc;
2226 int status;
2227
2228 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2229 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2230
e22b531b
HT		 2231 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2232 mask_vlan ? 1 : 0);
6f712727
PL		 2233 ether_addr_copy(req->mac_mask, mac_mask);
2234
2235 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2236 if (status)
2237 dev_err(&hdev->pdev->dev,
2238 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2239 status);
2240
2241 return status;
2242}
2243
46a3df9f
S		 2244static int hclge_mac_init(struct hclge_dev *hdev)
2245{
59bc85ec
FL		 2246 struct hnae3_handle *handle = &hdev->vport[0].nic;
2247 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 2248 struct hclge_mac *mac = &hdev->hw.mac;
6f712727 2249 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
a832d8b5 2250 struct hclge_vport *vport;
59bc85ec 2251 int mtu;
46a3df9f 2252 int ret;
a832d8b5 2253 int i;
46a3df9f
S		 2254
2255 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2256 if (ret) {
2257 dev_err(&hdev->pdev->dev,
2258 "Config mac speed dup fail ret=%d\n", ret);
2259 return ret;
2260 }
2261
2262 mac->link = 0;
2263
46a3df9f 2264 /* Initialize the MTA table work mode */
46a3df9f
S		 2265 hdev->enable_mta = true;
2266 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2267
2268 ret = hclge_set_mta_filter_mode(hdev,
2269 hdev->mta_mac_sel_type,
2270 hdev->enable_mta);
2271 if (ret) {
2272 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2273 ret);
2274 return ret;
2275 }
2276
a832d8b5
XW		 2277 for (i = 0; i < hdev->num_alloc_vport; i++) {
2278 vport = &hdev->vport[i];
2279 vport->accept_mta_mc = false;
2280
2281 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2282 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2283 if (ret) {
2284 dev_err(&hdev->pdev->dev,
2285 "set mta filter mode fail ret=%d\n", ret);
2286 return ret;
2287 }
6f712727
PL		 2288 }
2289
2290 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
59bc85ec 2291 if (ret) {
6f712727
PL		 2292 dev_err(&hdev->pdev->dev,
2293 "set default mac_vlan_mask fail ret=%d\n", ret);
59bc85ec
FL		 2294 return ret;
2295 }
6f712727 2296
59bc85ec
FL		 2297 if (netdev)
2298 mtu = netdev->mtu;
2299 else
2300 mtu = ETH_DATA_LEN;
2301
2302 ret = hclge_set_mtu(handle, mtu);
e125295a 2303 if (ret)
59bc85ec
FL		 2304 dev_err(&hdev->pdev->dev,
2305 "set mtu failed ret=%d\n", ret);
59bc85ec 2306
e125295a 2307 return ret;
46a3df9f
S		 2308}
2309
22fd3468
SM		 2310static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2311{
2312 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2313 schedule_work(&hdev->mbx_service_task);
2314}
2315
ed4a1bb8
SM		 2316static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2317{
2318 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2319 schedule_work(&hdev->rst_service_task);
2320}
2321
46a3df9f
S		 2322static void hclge_task_schedule(struct hclge_dev *hdev)
2323{
2324 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2325 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2326 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2327 (void)schedule_work(&hdev->service_task);
2328}
2329
2330static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2331{
d44f9b63 2332 struct hclge_link_status_cmd *req;
46a3df9f
S		 2333 struct hclge_desc desc;
2334 int link_status;
2335 int ret;
2336
2337 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2338 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2339 if (ret) {
2340 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2341 ret);
2342 return ret;
2343 }
2344
d44f9b63 2345 req = (struct hclge_link_status_cmd *)desc.data;
b28556c9 2346 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
46a3df9f
S		 2347
2348 return !!link_status;
2349}
2350
2351static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2352{
2353 int mac_state;
2354 int link_stat;
2355
2356 mac_state = hclge_get_mac_link_status(hdev);
2357
2358 if (hdev->hw.mac.phydev) {
2359 if (!genphy_read_status(hdev->hw.mac.phydev))
2360 link_stat = mac_state &
2361 hdev->hw.mac.phydev->link;
2362 else
2363 link_stat = 0;
2364
2365 } else {
2366 link_stat = mac_state;
2367 }
2368
2369 return !!link_stat;
2370}
2371
2372static void hclge_update_link_status(struct hclge_dev *hdev)
2373{
15a50665 2374 struct hnae3_client *rclient = hdev->roce_client;
46a3df9f
S		 2375 struct hnae3_client *client = hdev->nic_client;
2376 struct hnae3_handle *handle;
2377 int state;
2378 int i;
2379
2380 if (!client)
2381 return;
2382 state = hclge_get_mac_phy_link(hdev);
2383 if (state != hdev->hw.mac.link) {
2384 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2385 handle = &hdev->vport[i].nic;
2386 client->ops->link_status_change(handle, state);
15a50665
WHX		 2387 if (rclient && rclient->ops->link_status_change)
2388 rclient->ops->link_status_change(handle, state);
46a3df9f
S		 2389 }
2390 hdev->hw.mac.link = state;
2391 }
2392}
2393
2394static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2395{
2396 struct hclge_mac mac = hdev->hw.mac;
2397 u8 duplex;
2398 int speed;
2399 int ret;
2400
2401 /* get the speed and duplex as autoneg'result from mac cmd when phy
2402 * doesn't exit.
2403 */
c040366b 2404 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2405 return 0;
2406
2407 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2408 if (ret) {
2409 dev_err(&hdev->pdev->dev,
2410 "mac autoneg/speed/duplex query failed %d\n", ret);
2411 return ret;
2412 }
2413
2414 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2415 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2416 if (ret) {
2417 dev_err(&hdev->pdev->dev,
2418 "mac speed/duplex config failed %d\n", ret);
2419 return ret;
2420 }
2421 }
2422
2423 return 0;
2424}
2425
2426static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2427{
2428 struct hclge_vport *vport = hclge_get_vport(handle);
2429 struct hclge_dev *hdev = vport->back;
2430
2431 return hclge_update_speed_duplex(hdev);
2432}
2433
2434static int hclge_get_status(struct hnae3_handle *handle)
2435{
2436 struct hclge_vport *vport = hclge_get_vport(handle);
2437 struct hclge_dev *hdev = vport->back;
2438
2439 hclge_update_link_status(hdev);
2440
2441 return hdev->hw.mac.link;
2442}
2443
d039ef68 2444static void hclge_service_timer(struct timer_list *t)
46a3df9f 2445{
d039ef68 2446 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2447
d039ef68 2448 mod_timer(&hdev->service_timer, jiffies + HZ);
7a5d2a39 2449 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2450 hclge_task_schedule(hdev);
2451}
2452
2453static void hclge_service_complete(struct hclge_dev *hdev)
2454{
2455 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2456
2457 /* Flush memory before next watchdog */
2458 smp_mb__before_atomic();
2459 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2460}
2461
202f2014
SM		 2462static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2463{
2464 u32 rst_src_reg;
22fd3468 2465 u32 cmdq_src_reg;
202f2014
SM		 2466
2467 /* fetch the events from their corresponding regs */
2468 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
22fd3468
SM		 2469 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2470
2471 /* Assumption: If by any chance reset and mailbox events are reported
2472 * together then we will only process reset event in this go and will
2473 * defer the processing of the mailbox events. Since, we would have not
2474 * cleared RX CMDQ event this time we would receive again another
2475 * interrupt from H/W just for the mailbox.
2476 */
202f2014
SM		 2477
2478 /* check for vector0 reset event sources */
2479 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2480 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2481 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2482 return HCLGE_VECTOR0_EVENT_RST;
2483 }
2484
2485 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2486 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2487 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2488 return HCLGE_VECTOR0_EVENT_RST;
2489 }
2490
2491 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2492 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2493 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2494 return HCLGE_VECTOR0_EVENT_RST;
2495 }
2496
22fd3468
SM		 2497 /* check for vector0 mailbox(=CMDQ RX) event source */
2498 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2499 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2500 *clearval = cmdq_src_reg;
2501 return HCLGE_VECTOR0_EVENT_MBX;
2502 }
202f2014
SM		 2503
2504 return HCLGE_VECTOR0_EVENT_OTHER;
2505}
2506
2507static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2508 u32 regclr)
2509{
22fd3468
SM		 2510 switch (event_type) {
2511 case HCLGE_VECTOR0_EVENT_RST:
202f2014 2512 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
22fd3468
SM		 2513 break;
2514 case HCLGE_VECTOR0_EVENT_MBX:
2515 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2516 break;
2517 }
202f2014
SM		 2518}
2519
466b0c00
L		 2520static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2521{
2522 writel(enable ? 1 : 0, vector->addr);
2523}
2524
2525static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2526{
2527 struct hclge_dev *hdev = data;
202f2014
SM		 2528 u32 event_cause;
2529 u32 clearval;
466b0c00
L		 2530
2531 hclge_enable_vector(&hdev->misc_vector, false);
202f2014
SM		 2532 event_cause = hclge_check_event_cause(hdev, &clearval);
2533
22fd3468 2534 /* vector 0 interrupt is shared with reset and mailbox source events.*/
202f2014
SM		 2535 switch (event_cause) {
2536 case HCLGE_VECTOR0_EVENT_RST:
ed4a1bb8 2537 hclge_reset_task_schedule(hdev);
202f2014 2538 break;
22fd3468
SM		 2539 case HCLGE_VECTOR0_EVENT_MBX:
2540 /* If we are here then,
2541 * 1. Either we are not handling any mbx task and we are not
2542 * scheduled as well
2543 * OR
2544 * 2. We could be handling a mbx task but nothing more is
2545 * scheduled.
2546 * In both cases, we should schedule mbx task as there are more
2547 * mbx messages reported by this interrupt.
2548 */
2549 hclge_mbx_task_schedule(hdev);
40ee4b71 2550 break;
202f2014 2551 default:
40ee4b71
YL		 2552 dev_warn(&hdev->pdev->dev,
2553 "received unknown or unhandled event of vector0\n");
202f2014
SM		 2554 break;
2555 }
2556
e9a50d09
YL		 2557 /* clear the source of interrupt if it is not cause by reset */
2558 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2559 hclge_clear_event_cause(hdev, event_cause, clearval);
2560 hclge_enable_vector(&hdev->misc_vector, true);
2561 }
466b0c00
L		 2562
2563 return IRQ_HANDLED;
2564}
2565
2566static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2567{
617cb5a2
PL		 2568 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2569 dev_warn(&hdev->pdev->dev,
2570 "vector(vector_id %d) has been freed.\n", vector_id);
2571 return;
2572 }
2573
466b0c00
L		 2574 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2575 hdev->num_msi_left += 1;
2576 hdev->num_msi_used -= 1;
2577}
2578
2579static void hclge_get_misc_vector(struct hclge_dev *hdev)
2580{
2581 struct hclge_misc_vector *vector = &hdev->misc_vector;
2582
2583 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2584
2585 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2586 hdev->vector_status[0] = 0;
2587
2588 hdev->num_msi_left -= 1;
2589 hdev->num_msi_used += 1;
2590}
2591
2592static int hclge_misc_irq_init(struct hclge_dev *hdev)
2593{
2594 int ret;
2595
2596 hclge_get_misc_vector(hdev);
2597
202f2014
SM		 2598 /* this would be explicitly freed in the end */
2599 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2600 0, "hclge_misc", hdev);
466b0c00
L		 2601 if (ret) {
2602 hclge_free_vector(hdev, 0);
2603 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2604 hdev->misc_vector.vector_irq);
2605 }
2606
2607 return ret;
2608}
2609
202f2014
SM		 2610static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2611{
2612 free_irq(hdev->misc_vector.vector_irq, hdev);
2613 hclge_free_vector(hdev, 0);
2614}
2615
4ed340ab
L		 2616static int hclge_notify_client(struct hclge_dev *hdev,
2617 enum hnae3_reset_notify_type type)
2618{
2e5ed0d2 2619 struct hnae3_client *rclient = hdev->roce_client;
4ed340ab 2620 struct hnae3_client *client = hdev->nic_client;
d3f5c892
LO		 2621 struct hnae3_handle *handle;
2622 int ret;
4ed340ab
L		 2623 u16 i;
2624
2625 if (!client->ops->reset_notify)
2626 return -EOPNOTSUPP;
2627
2628 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
d3f5c892 2629 handle = &hdev->vport[i].nic;
4ed340ab 2630 ret = client->ops->reset_notify(handle, type);
2e5ed0d2
WHX		 2631 if (ret) {
2632 dev_err(&hdev->pdev->dev,
2633 "notify nic client failed %d", ret);
4ed340ab 2634 return ret;
2e5ed0d2 2635 }
d3f5c892 2636
2e5ed0d2 2637 if (rclient && rclient->ops->reset_notify) {
d3f5c892 2638 handle = &hdev->vport[i].roce;
2e5ed0d2
WHX		 2639 ret = rclient->ops->reset_notify(handle, type);
2640 if (ret) {
2641 dev_err(&hdev->pdev->dev,
2642 "notify roce client failed %d", ret);
2643 return ret;
2644 }
d3f5c892 2645 }
4ed340ab
L		 2646 }
2647
2648 return 0;
2649}
2650
2651static int hclge_reset_wait(struct hclge_dev *hdev)
2652{
2653#define HCLGE_RESET_WATI_MS 100
2654#define HCLGE_RESET_WAIT_CNT 5
2655 u32 val, reg, reg_bit;
2656 u32 cnt = 0;
2657
2658 switch (hdev->reset_type) {
2659 case HNAE3_GLOBAL_RESET:
2660 reg = HCLGE_GLOBAL_RESET_REG;
2661 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2662 break;
2663 case HNAE3_CORE_RESET:
2664 reg = HCLGE_GLOBAL_RESET_REG;
2665 reg_bit = HCLGE_CORE_RESET_BIT;
2666 break;
2667 case HNAE3_FUNC_RESET:
2668 reg = HCLGE_FUN_RST_ING;
2669 reg_bit = HCLGE_FUN_RST_ING_B;
2670 break;
2671 default:
2672 dev_err(&hdev->pdev->dev,
2673 "Wait for unsupported reset type: %d\n",
2674 hdev->reset_type);
2675 return -EINVAL;
2676 }
2677
2678 val = hclge_read_dev(&hdev->hw, reg);
e22b531b
HT		 2679 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT &&
2680 test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
4ed340ab
L		 2681 msleep(HCLGE_RESET_WATI_MS);
2682 val = hclge_read_dev(&hdev->hw, reg);
2683 cnt++;
2684 }
2685
4ed340ab
L		 2686 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2687 dev_warn(&hdev->pdev->dev,
2688 "Wait for reset timeout: %d\n", hdev->reset_type);
2689 return -EBUSY;
2690 }
2691
2692 return 0;
2693}
2694
13a86fae 2695int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2696{
2697 struct hclge_desc desc;
2698 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2699 int ret;
2700
2701 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
e22b531b 2702 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2703 req->fun_reset_vfid = func_id;
2704
2705 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2706 if (ret)
2707 dev_err(&hdev->pdev->dev,
2708 "send function reset cmd fail, status =%d\n", ret);
2709
2710 return ret;
2711}
2712
d5752031 2713static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2714{
2715 struct pci_dev *pdev = hdev->pdev;
2716 u32 val;
2717
d5752031 2718 switch (hdev->reset_type) {
4ed340ab
L		 2719 case HNAE3_GLOBAL_RESET:
2720 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e22b531b 2721 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2722 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2723 dev_info(&pdev->dev, "Global Reset requested\n");
2724 break;
2725 case HNAE3_CORE_RESET:
2726 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e22b531b 2727 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2728 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2729 dev_info(&pdev->dev, "Core Reset requested\n");
2730 break;
2731 case HNAE3_FUNC_RESET:
2732 dev_info(&pdev->dev, "PF Reset requested\n");
2733 hclge_func_reset_cmd(hdev, 0);
ed4a1bb8
SM		 2734 /* schedule again to check later */
2735 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2736 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2737 break;
2738 default:
2739 dev_warn(&pdev->dev,
d5752031 2740 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2741 break;
2742 }
2743}
2744
d5752031
SM		 2745static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2746 unsigned long *addr)
2747{
2748 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2749
2750 /* return the highest priority reset level amongst all */
2751 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2752 rst_level = HNAE3_GLOBAL_RESET;
2753 else if (test_bit(HNAE3_CORE_RESET, addr))
2754 rst_level = HNAE3_CORE_RESET;
2755 else if (test_bit(HNAE3_IMP_RESET, addr))
2756 rst_level = HNAE3_IMP_RESET;
2757 else if (test_bit(HNAE3_FUNC_RESET, addr))
2758 rst_level = HNAE3_FUNC_RESET;
2759
2760 /* now, clear all other resets */
2761 clear_bit(HNAE3_GLOBAL_RESET, addr);
2762 clear_bit(HNAE3_CORE_RESET, addr);
2763 clear_bit(HNAE3_IMP_RESET, addr);
2764 clear_bit(HNAE3_FUNC_RESET, addr);
2765
2766 return rst_level;
2767}
2768
e9a50d09
YL		 2769static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2770{
2771 u32 clearval = 0;
2772
2773 switch (hdev->reset_type) {
2774 case HNAE3_IMP_RESET:
2775 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2776 break;
2777 case HNAE3_GLOBAL_RESET:
2778 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2779 break;
2780 case HNAE3_CORE_RESET:
2781 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2782 break;
2783 default:
2784 dev_warn(&hdev->pdev->dev, "Unsupported reset event to clear:%d",
2785 hdev->reset_type);
2786 break;
2787 }
2788
2789 if (!clearval)
2790 return;
2791
2792 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2793 hclge_enable_vector(&hdev->misc_vector, true);
2794}
2795
d5752031
SM		 2796static void hclge_reset(struct hclge_dev *hdev)
2797{
2798 /* perform reset of the stack & ae device for a client */
2799
2800 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2801
2802 if (!hclge_reset_wait(hdev)) {
2803 rtnl_lock();
2804 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2805 hclge_reset_ae_dev(hdev->ae_dev);
2806 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2807 rtnl_unlock();
e9a50d09
YL		 2808
2809 hclge_clear_reset_cause(hdev);
d5752031
SM		 2810 } else {
2811 /* schedule again to check pending resets later */
2812 set_bit(hdev->reset_type, &hdev->reset_pending);
2813 hclge_reset_task_schedule(hdev);
2814 }
2815
2816 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2817}
2818
4aef908d 2819static void hclge_reset_event(struct hnae3_handle *handle)
4ed340ab
L		 2820{
2821 struct hclge_vport *vport = hclge_get_vport(handle);
2822 struct hclge_dev *hdev = vport->back;
2823
4aef908d
SM		 2824 /* check if this is a new reset request and we are not here just because
2825 * last reset attempt did not succeed and watchdog hit us again. We will
2826 * know this if last reset request did not occur very recently (watchdog
2827 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2828 * In case of new request we reset the "reset level" to PF reset.
2829 */
2830 if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
2831 handle->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2832
4aef908d
SM		 2833 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2834 handle->reset_level);
2835
2836 /* request reset & schedule reset task */
2837 set_bit(handle->reset_level, &hdev->reset_request);
2838 hclge_reset_task_schedule(hdev);
2839
2840 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2841 handle->reset_level++;
2842
2843 handle->last_reset_time = jiffies;
4ed340ab
L		 2844}
2845
2846static void hclge_reset_subtask(struct hclge_dev *hdev)
2847{
d5752031
SM		 2848 /* check if there is any ongoing reset in the hardware. This status can
2849 * be checked from reset_pending. If there is then, we need to wait for
2850 * hardware to complete reset.
2851 * a. If we are able to figure out in reasonable time that hardware
2852 * has fully resetted then, we can proceed with driver, client
2853 * reset.
2854 * b. else, we can come back later to check this status so re-sched
2855 * now.
2856 */
2857 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2858 if (hdev->reset_type != HNAE3_NONE_RESET)
2859 hclge_reset(hdev);
4ed340ab 2860
d5752031
SM		 2861 /* check if we got any *new* reset requests to be honored */
2862 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2863 if (hdev->reset_type != HNAE3_NONE_RESET)
2864 hclge_do_reset(hdev);
4ed340ab 2865
4ed340ab
L		 2866 hdev->reset_type = HNAE3_NONE_RESET;
2867}
2868
ed4a1bb8 2869static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2870{
ed4a1bb8
SM		 2871 struct hclge_dev *hdev =
2872 container_of(work, struct hclge_dev, rst_service_task);
2873
2874 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2875 return;
2876
2877 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2878
4ed340ab 2879 hclge_reset_subtask(hdev);
ed4a1bb8
SM		 2880
2881 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2882}
2883
22fd3468
SM		 2884static void hclge_mailbox_service_task(struct work_struct *work)
2885{
2886 struct hclge_dev *hdev =
2887 container_of(work, struct hclge_dev, mbx_service_task);
2888
2889 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2890 return;
2891
2892 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2893
2894 hclge_mbx_handler(hdev);
2895
2896 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2897}
2898
46a3df9f
S		 2899static void hclge_service_task(struct work_struct *work)
2900{
2901 struct hclge_dev *hdev =
2902 container_of(work, struct hclge_dev, service_task);
2903
7a5d2a39
JS		 2904 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2905 hclge_update_stats_for_all(hdev);
2906 hdev->hw_stats.stats_timer = 0;
2907 }
2908
46a3df9f
S		 2909 hclge_update_speed_duplex(hdev);
2910 hclge_update_link_status(hdev);
46a3df9f
S		 2911 hclge_service_complete(hdev);
2912}
2913
46a3df9f
S		 2914struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2915{
2916 /* VF handle has no client */
2917 if (!handle->client)
2918 return container_of(handle, struct hclge_vport, nic);
2919 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2920 return container_of(handle, struct hclge_vport, roce);
2921 else
2922 return container_of(handle, struct hclge_vport, nic);
2923}
2924
2925static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2926 struct hnae3_vector_info *vector_info)
2927{
2928 struct hclge_vport *vport = hclge_get_vport(handle);
2929 struct hnae3_vector_info *vector = vector_info;
2930 struct hclge_dev *hdev = vport->back;
2931 int alloc = 0;
2932 int i, j;
2933
2934 vector_num = min(hdev->num_msi_left, vector_num);
2935
2936 for (j = 0; j < vector_num; j++) {
2937 for (i = 1; i < hdev->num_msi; i++) {
2938 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2939 vector->vector = pci_irq_vector(hdev->pdev, i);
2940 vector->io_addr = hdev->hw.io_base +
2941 HCLGE_VECTOR_REG_BASE +
2942 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2943 vport->vport_id *
2944 HCLGE_VECTOR_VF_OFFSET;
2945 hdev->vector_status[i] = vport->vport_id;
887c3820 2946 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2947
2948 vector++;
2949 alloc++;
2950
2951 break;
2952 }
2953 }
2954 }
2955 hdev->num_msi_left -= alloc;
2956 hdev->num_msi_used += alloc;
2957
2958 return alloc;
2959}
2960
2961static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2962{
2963 int i;
2964
887c3820
SM		 2965 for (i = 0; i < hdev->num_msi; i++)
2966 if (vector == hdev->vector_irq[i])
2967 return i;
2968
46a3df9f
S		 2969 return -EINVAL;
2970}
2971
7412200c
YL		 2972static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2973{
2974 struct hclge_vport *vport = hclge_get_vport(handle);
2975 struct hclge_dev *hdev = vport->back;
2976 int vector_id;
2977
2978 vector_id = hclge_get_vector_index(hdev, vector);
2979 if (vector_id < 0) {
2980 dev_err(&hdev->pdev->dev,
2981 "Get vector index fail. vector_id =%d\n", vector_id);
2982 return vector_id;
2983 }
2984
2985 hclge_free_vector(hdev, vector_id);
2986
2987 return 0;
2988}
2989
46a3df9f
S		 2990static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2991{
2992 return HCLGE_RSS_KEY_SIZE;
2993}
2994
2995static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2996{
2997 return HCLGE_RSS_IND_TBL_SIZE;
2998}
2999
46a3df9f
S		 3000static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3001 const u8 hfunc, const u8 *key)
3002{
d44f9b63 3003 struct hclge_rss_config_cmd *req;
46a3df9f
S		 3004 struct hclge_desc desc;
3005 int key_offset;
3006 int key_size;
3007 int ret;
3008
d44f9b63 3009 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 3010
3011 for (key_offset = 0; key_offset < 3; key_offset++) {
3012 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3013 false);
3014
3015 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3016 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3017
3018 if (key_offset == 2)
3019 key_size =
3020 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3021 else
3022 key_size = HCLGE_RSS_HASH_KEY_NUM;
3023
3024 memcpy(req->hash_key,
3025 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3026
3027 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3028 if (ret) {
3029 dev_err(&hdev->pdev->dev,
3030 "Configure RSS config fail, status = %d\n",
3031 ret);
3032 return ret;
3033 }
3034 }
3035 return 0;
3036}
3037
dcd4ef5e 3038static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3039{
d44f9b63 3040 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3041 struct hclge_desc desc;
3042 int i, j;
3043 int ret;
3044
d44f9b63 3045 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3046
3047 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3048 hclge_cmd_setup_basic_desc
3049 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3050
a90bb9a5
YL		 3051 req->start_table_index =
3052 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3053 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3054
3055 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3056 req->rss_result[j] =
3057 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3058
3059 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3060 if (ret) {
3061 dev_err(&hdev->pdev->dev,
3062 "Configure rss indir table fail,status = %d\n",
3063 ret);
3064 return ret;
3065 }
3066 }
3067 return 0;
3068}
3069
3070static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3071 u16 *tc_size, u16 *tc_offset)
3072{
d44f9b63 3073 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3074 struct hclge_desc desc;
3075 int ret;
3076 int i;
3077
3078 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3079 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3080
3081 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3082 u16 mode = 0;
3083
e22b531b
HT		 3084 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3085 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3086 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3087 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3088 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3089
3090 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3091 }
3092
3093 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3094 if (ret)
46a3df9f
S		 3095 dev_err(&hdev->pdev->dev,
3096 "Configure rss tc mode fail, status = %d\n", ret);
46a3df9f 3097
e125295a 3098 return ret;
46a3df9f
S		 3099}
3100
3101static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3102{
d44f9b63 3103 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3104 struct hclge_desc desc;
3105 int ret;
3106
3107 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3108
d44f9b63 3109 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef
YL		 3110
3111 /* Get the tuple cfg from pf */
3112 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3113 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3114 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3115 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3116 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3117 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3118 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3119 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
46a3df9f 3120 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3121 if (ret)
46a3df9f
S		 3122 dev_err(&hdev->pdev->dev,
3123 "Configure rss input fail, status = %d\n", ret);
e125295a 3124 return ret;
46a3df9f
S		 3125}
3126
3127static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3128 u8 *key, u8 *hfunc)
3129{
3130 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3131 int i;
3132
3133 /* Get hash algorithm */
3134 if (hfunc)
dcd4ef5e 3135 *hfunc = vport->rss_algo;
46a3df9f
S		 3136
3137 /* Get the RSS Key required by the user */
3138 if (key)
3139 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3140
3141 /* Get indirect table */
3142 if (indir)
3143 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3144 indir[i] = vport->rss_indirection_tbl[i];
3145
3146 return 0;
3147}
3148
3149static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3150 const u8 *key, const u8 hfunc)
3151{
3152 struct hclge_vport *vport = hclge_get_vport(handle);
3153 struct hclge_dev *hdev = vport->back;
3154 u8 hash_algo;
3155 int ret, i;
3156
3157 /* Set the RSS Hash Key if specififed by the user */
3158 if (key) {
46a3df9f
S		 3159
3160 if (hfunc == ETH_RSS_HASH_TOP ||
3161 hfunc == ETH_RSS_HASH_NO_CHANGE)
3162 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3163 else
3164 return -EINVAL;
3165 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3166 if (ret)
3167 return ret;
dcd4ef5e
YL		 3168
3169 /* Update the shadow RSS key with user specified qids */
3170 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3171 vport->rss_algo = hash_algo;
46a3df9f
S		 3172 }
3173
3174 /* Update the shadow RSS table with user specified qids */
3175 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3176 vport->rss_indirection_tbl[i] = indir[i];
3177
3178 /* Update the hardware */
dcd4ef5e 3179 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3180}
3181
f7db940a
L		 3182static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3183{
3184 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3185
3186 if (nfc->data & RXH_L4_B_2_3)
3187 hash_sets |= HCLGE_D_PORT_BIT;
3188 else
3189 hash_sets &= ~HCLGE_D_PORT_BIT;
3190
3191 if (nfc->data & RXH_IP_SRC)
3192 hash_sets |= HCLGE_S_IP_BIT;
3193 else
3194 hash_sets &= ~HCLGE_S_IP_BIT;
3195
3196 if (nfc->data & RXH_IP_DST)
3197 hash_sets |= HCLGE_D_IP_BIT;
3198 else
3199 hash_sets &= ~HCLGE_D_IP_BIT;
3200
3201 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3202 hash_sets |= HCLGE_V_TAG_BIT;
3203
3204 return hash_sets;
3205}
3206
3207static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3208 struct ethtool_rxnfc *nfc)
3209{
3210 struct hclge_vport *vport = hclge_get_vport(handle);
3211 struct hclge_dev *hdev = vport->back;
3212 struct hclge_rss_input_tuple_cmd *req;
3213 struct hclge_desc desc;
3214 u8 tuple_sets;
3215 int ret;
3216
3217 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3218 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3219 return -EINVAL;
3220
3221 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef 3222 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 3223
637053ef
YL		 3224 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3225 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3226 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3227 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3228 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3229 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3230 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3231 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 3232
3233 tuple_sets = hclge_get_rss_hash_bits(nfc);
3234 switch (nfc->flow_type) {
3235 case TCP_V4_FLOW:
3236 req->ipv4_tcp_en = tuple_sets;
3237 break;
3238 case TCP_V6_FLOW:
3239 req->ipv6_tcp_en = tuple_sets;
3240 break;
3241 case UDP_V4_FLOW:
3242 req->ipv4_udp_en = tuple_sets;
3243 break;
3244 case UDP_V6_FLOW:
3245 req->ipv6_udp_en = tuple_sets;
3246 break;
3247 case SCTP_V4_FLOW:
3248 req->ipv4_sctp_en = tuple_sets;
3249 break;
3250 case SCTP_V6_FLOW:
3251 if ((nfc->data & RXH_L4_B_0_1) ||
3252 (nfc->data & RXH_L4_B_2_3))
3253 return -EINVAL;
3254
3255 req->ipv6_sctp_en = tuple_sets;
3256 break;
3257 case IPV4_FLOW:
3258 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3259 break;
3260 case IPV6_FLOW:
3261 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3262 break;
3263 default:
3264 return -EINVAL;
3265 }
3266
3267 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
637053ef 3268 if (ret) {
f7db940a
L		 3269 dev_err(&hdev->pdev->dev,
3270 "Set rss tuple fail, status = %d\n", ret);
637053ef
YL		 3271 return ret;
3272 }
f7db940a 3273
637053ef
YL		 3274 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3275 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3276 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3277 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3278 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3279 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3280 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3281 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3282 return 0;
f7db940a
L		 3283}
3284
07d29954
L		 3285static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3286 struct ethtool_rxnfc *nfc)
3287{
3288 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3289 u8 tuple_sets;
07d29954
L		 3290
3291 nfc->data = 0;
3292
07d29954
L		 3293 switch (nfc->flow_type) {
3294 case TCP_V4_FLOW:
637053ef 3295 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3296 break;
3297 case UDP_V4_FLOW:
637053ef 3298 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3299 break;
3300 case TCP_V6_FLOW:
637053ef 3301 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3302 break;
3303 case UDP_V6_FLOW:
637053ef 3304 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3305 break;
3306 case SCTP_V4_FLOW:
637053ef 3307 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3308 break;
3309 case SCTP_V6_FLOW:
637053ef 3310 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3311 break;
3312 case IPV4_FLOW:
3313 case IPV6_FLOW:
3314 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3315 break;
3316 default:
3317 return -EINVAL;
3318 }
3319
3320 if (!tuple_sets)
3321 return 0;
3322
3323 if (tuple_sets & HCLGE_D_PORT_BIT)
3324 nfc->data |= RXH_L4_B_2_3;
3325 if (tuple_sets & HCLGE_S_PORT_BIT)
3326 nfc->data |= RXH_L4_B_0_1;
3327 if (tuple_sets & HCLGE_D_IP_BIT)
3328 nfc->data |= RXH_IP_DST;
3329 if (tuple_sets & HCLGE_S_IP_BIT)
3330 nfc->data |= RXH_IP_SRC;
3331
3332 return 0;
3333}
3334
46a3df9f
S		 3335static int hclge_get_tc_size(struct hnae3_handle *handle)
3336{
3337 struct hclge_vport *vport = hclge_get_vport(handle);
3338 struct hclge_dev *hdev = vport->back;
3339
3340 return hdev->rss_size_max;
3341}
3342
77f255c1 3343int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3344{
46a3df9f 3345 struct hclge_vport *vport = hdev->vport;
8015bb74
YL		 3346 u8 *rss_indir = vport[0].rss_indirection_tbl;
3347 u16 rss_size = vport[0].alloc_rss_size;
3348 u8 *key = vport[0].rss_hash_key;
3349 u8 hfunc = vport[0].rss_algo;
46a3df9f 3350 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3351 u16 tc_valid[HCLGE_MAX_TC_NUM];
3352 u16 tc_size[HCLGE_MAX_TC_NUM];
8015bb74
YL		 3353 u16 roundup_size;
3354 int i, ret;
68ece54e 3355
46a3df9f
S		 3356 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3357 if (ret)
8015bb74 3358 return ret;
46a3df9f 3359
46a3df9f
S		 3360 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3361 if (ret)
8015bb74 3362 return ret;
46a3df9f
S		 3363
3364 ret = hclge_set_rss_input_tuple(hdev);
3365 if (ret)
8015bb74 3366 return ret;
46a3df9f 3367
68ece54e
YL		 3368 /* Each TC have the same queue size, and tc_size set to hardware is
3369 * the log2 of roundup power of two of rss_size, the acutal queue
3370 * size is limited by indirection table.
3371 */
3372 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3373 dev_err(&hdev->pdev->dev,
3374 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3375 rss_size);
8015bb74 3376 return -EINVAL;
68ece54e
YL		 3377 }
3378
3379 roundup_size = roundup_pow_of_two(rss_size);
3380 roundup_size = ilog2(roundup_size);
3381
46a3df9f 3382 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3383 tc_valid[i] = 0;
46a3df9f 3384
68ece54e
YL		 3385 if (!(hdev->hw_tc_map & BIT(i)))
3386 continue;
3387
3388 tc_valid[i] = 1;
3389 tc_size[i] = roundup_size;
3390 tc_offset[i] = rss_size * i;
46a3df9f 3391 }
68ece54e 3392
8015bb74
YL		 3393 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3394}
46a3df9f 3395
8015bb74
YL		 3396void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3397{
3398 struct hclge_vport *vport = hdev->vport;
3399 int i, j;
46a3df9f 3400
8015bb74
YL		 3401 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3402 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3403 vport[j].rss_indirection_tbl[i] =
3404 i % vport[j].alloc_rss_size;
3405 }
3406}
3407
3408static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3409{
3410 struct hclge_vport *vport = hdev->vport;
3411 int i;
3412
8015bb74
YL		 3413 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3414 vport[i].rss_tuple_sets.ipv4_tcp_en =
3415 HCLGE_RSS_INPUT_TUPLE_OTHER;
3416 vport[i].rss_tuple_sets.ipv4_udp_en =
3417 HCLGE_RSS_INPUT_TUPLE_OTHER;
3418 vport[i].rss_tuple_sets.ipv4_sctp_en =
3419 HCLGE_RSS_INPUT_TUPLE_SCTP;
3420 vport[i].rss_tuple_sets.ipv4_fragment_en =
3421 HCLGE_RSS_INPUT_TUPLE_OTHER;
3422 vport[i].rss_tuple_sets.ipv6_tcp_en =
3423 HCLGE_RSS_INPUT_TUPLE_OTHER;
3424 vport[i].rss_tuple_sets.ipv6_udp_en =
3425 HCLGE_RSS_INPUT_TUPLE_OTHER;
3426 vport[i].rss_tuple_sets.ipv6_sctp_en =
3427 HCLGE_RSS_INPUT_TUPLE_SCTP;
3428 vport[i].rss_tuple_sets.ipv6_fragment_en =
3429 HCLGE_RSS_INPUT_TUPLE_OTHER;
3430
3431 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
823fe868
FL		 3432
3433 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
8015bb74
YL		 3434 }
3435
3436 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3437}
3438
63d7e66f
SM		 3439int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3440 int vector_id, bool en,
3441 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3442{
3443 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3444 struct hnae3_ring_chain_node *node;
3445 struct hclge_desc desc;
63d7e66f
SM		 3446 struct hclge_ctrl_vector_chain_cmd *req
3447 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3448 enum hclge_cmd_status status;
3449 enum hclge_opcode_type op;
3450 u16 tqp_type_and_id;
46a3df9f
S		 3451 int i;
3452
63d7e66f
SM		 3453 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3454 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3455 req->int_vector_id = vector_id;
3456
3457 i = 0;
3458 for (node = ring_chain; node; node = node->next) {
63d7e66f 3459 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
e22b531b
HT		 3460 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3461 HCLGE_INT_TYPE_S,
3462 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3463 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3464 HCLGE_TQP_ID_S, node->tqp_index);
3465 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3466 HCLGE_INT_GL_IDX_S,
3467 hnae3_get_field(node->int_gl_idx,
3468 HNAE3_RING_GL_IDX_M,
3469 HNAE3_RING_GL_IDX_S));
63d7e66f 3470 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3471 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3472 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
63d7e66f 3473 req->vfid = vport->vport_id;
46a3df9f 3474
63d7e66f
SM		 3475 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3476 if (status) {
46a3df9f
S		 3477 dev_err(&hdev->pdev->dev,
3478 "Map TQP fail, status is %d.\n",
63d7e66f
SM		 3479 status);
3480 return -EIO;
46a3df9f
S		 3481 }
3482 i = 0;
3483
3484 hclge_cmd_setup_basic_desc(&desc,
63d7e66f 3485 op,
46a3df9f
S		 3486 false);
3487 req->int_vector_id = vector_id;
3488 }
3489 }
3490
3491 if (i > 0) {
3492 req->int_cause_num = i;
63d7e66f
SM		 3493 req->vfid = vport->vport_id;
3494 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3495 if (status) {
46a3df9f 3496 dev_err(&hdev->pdev->dev,
63d7e66f
SM		 3497 "Map TQP fail, status is %d.\n", status);
3498 return -EIO;
46a3df9f
S		 3499 }
3500 }
3501
3502 return 0;
3503}
3504
63d7e66f
SM		 3505static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3506 int vector,
3507 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3508{
3509 struct hclge_vport *vport = hclge_get_vport(handle);
3510 struct hclge_dev *hdev = vport->back;
3511 int vector_id;
3512
3513 vector_id = hclge_get_vector_index(hdev, vector);
3514 if (vector_id < 0) {
3515 dev_err(&hdev->pdev->dev,
63d7e66f 3516 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3517 return vector_id;
3518 }
3519
63d7e66f 3520 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3521}
3522
63d7e66f
SM		 3523static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3524 int vector,
3525 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3526{
3527 struct hclge_vport *vport = hclge_get_vport(handle);
3528 struct hclge_dev *hdev = vport->back;
63d7e66f 3529 int vector_id, ret;
46a3df9f 3530
f9637cc2
PL		 3531 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3532 return 0;
3533
46a3df9f
S		 3534 vector_id = hclge_get_vector_index(hdev, vector);
3535 if (vector_id < 0) {
3536 dev_err(&handle->pdev->dev,
3537 "Get vector index fail. ret =%d\n", vector_id);
3538 return vector_id;
3539 }
3540
63d7e66f 3541 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
7412200c 3542 if (ret)
63d7e66f
SM		 3543 dev_err(&handle->pdev->dev,
3544 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3545 vector_id,
3546 ret);
46a3df9f 3547
7412200c 3548 return ret;
46a3df9f
S		 3549}
3550
3551int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3552 struct hclge_promisc_param *param)
3553{
d44f9b63 3554 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3555 struct hclge_desc desc;
3556 int ret;
3557
3558 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3559
d44f9b63 3560 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3561 req->vf_id = param->vf_id;
4771e104
PL		 3562
3563 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3564 * pdev revision(0x20), new revision support them. The
3565 * value of this two fields will not return error when driver
3566 * send command to fireware in revision(0x20).
3567 */
3568 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3569 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3570
3571 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3572 if (ret)
46a3df9f
S		 3573 dev_err(&hdev->pdev->dev,
3574 "Set promisc mode fail, status is %d.\n", ret);
e125295a
JS		 3575
3576 return ret;
46a3df9f
S		 3577}
3578
3579void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3580 bool en_mc, bool en_bc, int vport_id)
3581{
3582 if (!param)
3583 return;
3584
3585 memset(param, 0, sizeof(struct hclge_promisc_param));
3586 if (en_uc)
3587 param->enable = HCLGE_PROMISC_EN_UC;
3588 if (en_mc)
3589 param->enable |= HCLGE_PROMISC_EN_MC;
3590 if (en_bc)
3591 param->enable |= HCLGE_PROMISC_EN_BC;
3592 param->vf_id = vport_id;
3593}
3594
e8600a3d
PL		 3595static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3596 bool en_mc_pmc)
46a3df9f
S		 3597{
3598 struct hclge_vport *vport = hclge_get_vport(handle);
3599 struct hclge_dev *hdev = vport->back;
3600 struct hclge_promisc_param param;
3601
e8600a3d
PL		 3602 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3603 vport->vport_id);
46a3df9f
S		 3604 hclge_cmd_set_promisc_mode(hdev, &param);
3605}
3606
3607static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3608{
3609 struct hclge_desc desc;
d44f9b63
YL		 3610 struct hclge_config_mac_mode_cmd *req =
3611 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3612 u32 loop_en = 0;
46a3df9f
S		 3613 int ret;
3614
3615 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
e22b531b
HT		 3616 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3617 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3618 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3619 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3620 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3621 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3622 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3623 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3624 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3625 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3626 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3627 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3628 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3629 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 3630 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3631
3632 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3633 if (ret)
3634 dev_err(&hdev->pdev->dev,
3635 "mac enable fail, ret =%d.\n", ret);
3636}
3637
e67d9ce9 3638static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 3639{
c39c4d98 3640 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 3641 struct hclge_desc desc;
3642 u32 loop_en;
3643 int ret;
3644
e67d9ce9
YL		 3645 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3646 /* 1 Read out the MAC mode config at first */
3647 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3648 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3649 if (ret) {
3650 dev_err(&hdev->pdev->dev,
3651 "mac loopback get fail, ret =%d.\n", ret);
3652 return ret;
3653 }
c39c4d98 3654
e67d9ce9
YL		 3655 /* 2 Then setup the loopback flag */
3656 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
e22b531b 3657 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
e67d9ce9
YL		 3658
3659 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 3660
e67d9ce9
YL		 3661 /* 3 Config mac work mode with loopback flag
3662 * and its original configure parameters
3663 */
3664 hclge_cmd_reuse_desc(&desc, false);
3665 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3666 if (ret)
3667 dev_err(&hdev->pdev->dev,
3668 "mac loopback set fail, ret =%d.\n", ret);
3669 return ret;
3670}
c39c4d98 3671
2fd5416a
YL		 3672static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en)
3673{
3674#define HCLGE_SERDES_RETRY_MS 10
3675#define HCLGE_SERDES_RETRY_NUM 100
3676 struct hclge_serdes_lb_cmd *req;
3677 struct hclge_desc desc;
3678 int ret, i = 0;
3679
3680 req = (struct hclge_serdes_lb_cmd *)&desc.data[0];
3681 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
3682
3683 if (en) {
3684 req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3685 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3686 } else {
3687 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3688 }
3689
3690 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3691 if (ret) {
3692 dev_err(&hdev->pdev->dev,
3693 "serdes loopback set fail, ret = %d\n", ret);
3694 return ret;
3695 }
3696
3697 do {
3698 msleep(HCLGE_SERDES_RETRY_MS);
3699 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3700 true);
3701 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3702 if (ret) {
3703 dev_err(&hdev->pdev->dev,
3704 "serdes loopback get, ret = %d\n", ret);
3705 return ret;
3706 }
3707 } while (++i < HCLGE_SERDES_RETRY_NUM &&
3708 !(req->result & HCLGE_CMD_SERDES_DONE_B));
3709
3710 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3711 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3712 return -EBUSY;
3713 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3714 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3715 return -EIO;
3716 }
3717
3718 return 0;
3719}
3720
e67d9ce9
YL		 3721static int hclge_set_loopback(struct hnae3_handle *handle,
3722 enum hnae3_loop loop_mode, bool en)
3723{
3724 struct hclge_vport *vport = hclge_get_vport(handle);
3725 struct hclge_dev *hdev = vport->back;
3726 int ret;
3727
3728 switch (loop_mode) {
3729 case HNAE3_MAC_INTER_LOOP_MAC:
3730 ret = hclge_set_mac_loopback(hdev, en);
c39c4d98 3731 break;
2fd5416a
YL		 3732 case HNAE3_MAC_INTER_LOOP_SERDES:
3733 ret = hclge_set_serdes_loopback(hdev, en);
3734 break;
c39c4d98
YL		 3735 default:
3736 ret = -ENOTSUPP;
3737 dev_err(&hdev->pdev->dev,
3738 "loop_mode %d is not supported\n", loop_mode);
3739 break;
3740 }
3741
3742 return ret;
3743}
3744
46a3df9f
S		 3745static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3746 int stream_id, bool enable)
3747{
3748 struct hclge_desc desc;
d44f9b63
YL		 3749 struct hclge_cfg_com_tqp_queue_cmd *req =
3750 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3751 int ret;
3752
3753 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3754 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3755 req->stream_id = cpu_to_le16(stream_id);
3756 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3757
3758 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3759 if (ret)
3760 dev_err(&hdev->pdev->dev,
3761 "Tqp enable fail, status =%d.\n", ret);
3762 return ret;
3763}
3764
3765static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3766{
3767 struct hclge_vport *vport = hclge_get_vport(handle);
3768 struct hnae3_queue *queue;
3769 struct hclge_tqp *tqp;
3770 int i;
3771
3772 for (i = 0; i < vport->alloc_tqps; i++) {
3773 queue = handle->kinfo.tqp[i];
3774 tqp = container_of(queue, struct hclge_tqp, q);
3775 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3776 }
3777}
3778
3779static int hclge_ae_start(struct hnae3_handle *handle)
3780{
3781 struct hclge_vport *vport = hclge_get_vport(handle);
3782 struct hclge_dev *hdev = vport->back;
e5e89cda 3783 int i, ret;
46a3df9f 3784
e5e89cda
PL		 3785 for (i = 0; i < vport->alloc_tqps; i++)
3786 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3787
46a3df9f
S		 3788 /* mac enable */
3789 hclge_cfg_mac_mode(hdev, true);
3790 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3791 mod_timer(&hdev->service_timer, jiffies + HZ);
3ae84019 3792 hdev->hw.mac.link = 0;
46a3df9f 3793
f9637cc2
PL		 3794 /* reset tqp stats */
3795 hclge_reset_tqp_stats(handle);
3796
46a3df9f
S		 3797 ret = hclge_mac_start_phy(hdev);
3798 if (ret)
3799 return ret;
3800
46a3df9f
S		 3801 return 0;
3802}
3803
3804static void hclge_ae_stop(struct hnae3_handle *handle)
3805{
3806 struct hclge_vport *vport = hclge_get_vport(handle);
3807 struct hclge_dev *hdev = vport->back;
e5e89cda 3808 int i;
46a3df9f 3809
f9637cc2
PL		 3810 del_timer_sync(&hdev->service_timer);
3811 cancel_work_sync(&hdev->service_task);
42b11ab7 3812 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
f9637cc2 3813
4486f5c9
YL		 3814 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3815 hclge_mac_stop_phy(hdev);
f9637cc2 3816 return;
4486f5c9 3817 }
f9637cc2 3818
e5e89cda
PL		 3819 for (i = 0; i < vport->alloc_tqps; i++)
3820 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3821
46a3df9f
S		 3822 /* Mac disable */
3823 hclge_cfg_mac_mode(hdev, false);
3824
3825 hclge_mac_stop_phy(hdev);
3826
3827 /* reset tqp stats */
3828 hclge_reset_tqp_stats(handle);
b91fb71c
FL		 3829 del_timer_sync(&hdev->service_timer);
3830 cancel_work_sync(&hdev->service_task);
3831 hclge_update_link_status(hdev);
46a3df9f
S		 3832}
3833
3834static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3835 u16 cmdq_resp, u8 resp_code,
3836 enum hclge_mac_vlan_tbl_opcode op)
3837{
3838 struct hclge_dev *hdev = vport->back;
3839 int return_status = -EIO;
3840
3841 if (cmdq_resp) {
3842 dev_err(&hdev->pdev->dev,
3843 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3844 cmdq_resp);
3845 return -EIO;
3846 }
3847
3848 if (op == HCLGE_MAC_VLAN_ADD) {
3849 if ((!resp_code) || (resp_code == 1)) {
3850 return_status = 0;
3851 } else if (resp_code == 2) {
2f894c5b 3852 return_status = -ENOSPC;
46a3df9f
S		 3853 dev_err(&hdev->pdev->dev,
3854 "add mac addr failed for uc_overflow.\n");
3855 } else if (resp_code == 3) {
2f894c5b 3856 return_status = -ENOSPC;
46a3df9f
S		 3857 dev_err(&hdev->pdev->dev,
3858 "add mac addr failed for mc_overflow.\n");
3859 } else {
3860 dev_err(&hdev->pdev->dev,
3861 "add mac addr failed for undefined, code=%d.\n",
3862 resp_code);
3863 }
3864 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3865 if (!resp_code) {
3866 return_status = 0;
3867 } else if (resp_code == 1) {
2f894c5b 3868 return_status = -ENOENT;
46a3df9f
S		 3869 dev_dbg(&hdev->pdev->dev,
3870 "remove mac addr failed for miss.\n");
3871 } else {
3872 dev_err(&hdev->pdev->dev,
3873 "remove mac addr failed for undefined, code=%d.\n",
3874 resp_code);
3875 }
3876 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3877 if (!resp_code) {
3878 return_status = 0;
3879 } else if (resp_code == 1) {
2f894c5b 3880 return_status = -ENOENT;
46a3df9f
S		 3881 dev_dbg(&hdev->pdev->dev,
3882 "lookup mac addr failed for miss.\n");
3883 } else {
3884 dev_err(&hdev->pdev->dev,
3885 "lookup mac addr failed for undefined, code=%d.\n",
3886 resp_code);
3887 }
3888 } else {
2f894c5b 3889 return_status = -EINVAL;
46a3df9f
S		 3890 dev_err(&hdev->pdev->dev,
3891 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3892 op);
3893 }
3894
3895 return return_status;
3896}
3897
3898static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3899{
3900 int word_num;
3901 int bit_num;
3902
3903 if (vfid > 255 || vfid < 0)
3904 return -EIO;
3905
3906 if (vfid >= 0 && vfid <= 191) {
3907 word_num = vfid / 32;
3908 bit_num = vfid % 32;
3909 if (clr)
a90bb9a5 3910 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3911 else
a90bb9a5 3912 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3913 } else {
3914 word_num = (vfid - 192) / 32;
3915 bit_num = vfid % 32;
3916 if (clr)
a90bb9a5 3917 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3918 else
a90bb9a5 3919 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3920 }
3921
3922 return 0;
3923}
3924
3925static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3926{
3927#define HCLGE_DESC_NUMBER 3
3928#define HCLGE_FUNC_NUMBER_PER_DESC 6
3929 int i, j;
3930
3931 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3932 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3933 if (desc[i].data[j])
3934 return false;
3935
3936 return true;
3937}
3938
d44f9b63 3939static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3940 const u8 *addr)
3941{
3942 const unsigned char *mac_addr = addr;
3943 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3944 (mac_addr[0]) | (mac_addr[1] << 8);
3945 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3946
3947 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3948 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3949}
3950
1db9b1bf
YL		 3951static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3952 const u8 *addr)
46a3df9f
S		 3953{
3954 u16 high_val = addr[1] | (addr[0] << 8);
3955 struct hclge_dev *hdev = vport->back;
3956 u32 rsh = 4 - hdev->mta_mac_sel_type;
3957 u16 ret_val = (high_val >> rsh) & 0xfff;
3958
3959 return ret_val;
3960}
3961
3962static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3963 enum hclge_mta_dmac_sel_type mta_mac_sel,
3964 bool enable)
3965{
d44f9b63 3966 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3967 struct hclge_desc desc;
3968 int ret;
3969
d44f9b63 3970 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3971 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3972
e22b531b
HT		 3973 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3974 enable);
3975 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3976 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
46a3df9f
S		 3977
3978 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3979 if (ret)
46a3df9f
S		 3980 dev_err(&hdev->pdev->dev,
3981 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3982 ret);
46a3df9f 3983
e125295a 3984 return ret;
46a3df9f
S		 3985}
3986
3987int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3988 u8 func_id,
3989 bool enable)
3990{
d44f9b63 3991 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3992 struct hclge_desc desc;
3993 int ret;
3994
d44f9b63 3995 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3996 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3997
e22b531b
HT		 3998 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3999 enable);
46a3df9f
S		 4000 req->function_id = func_id;
4001
4002 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 4003 if (ret)
46a3df9f
S		 4004 dev_err(&hdev->pdev->dev,
4005 "Config func_id enable failed for cmd_send, ret =%d.\n",
4006 ret);
46a3df9f 4007
e125295a 4008 return ret;
46a3df9f
S		 4009}
4010
4011static int hclge_set_mta_table_item(struct hclge_vport *vport,
4012 u16 idx,
4013 bool enable)
4014{
4015 struct hclge_dev *hdev = vport->back;
d44f9b63 4016 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 4017 struct hclge_desc desc;
a90bb9a5 4018 u16 item_idx = 0;
46a3df9f
S		 4019 int ret;
4020
d44f9b63 4021 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f 4022 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
e22b531b 4023 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
46a3df9f 4024
e22b531b
HT		 4025 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
4026 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 4027 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 4028
4029 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4030 if (ret) {
4031 dev_err(&hdev->pdev->dev,
4032 "Config mta table item failed for cmd_send, ret =%d.\n",
4033 ret);
4034 return ret;
4035 }
4036
a832d8b5
XW		 4037 if (enable)
4038 set_bit(idx, vport->mta_shadow);
4039 else
4040 clear_bit(idx, vport->mta_shadow);
4041
46a3df9f
S		 4042 return 0;
4043}
4044
a832d8b5
XW		 4045static int hclge_update_mta_status(struct hnae3_handle *handle)
4046{
4047 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
4048 struct hclge_vport *vport = hclge_get_vport(handle);
4049 struct net_device *netdev = handle->kinfo.netdev;
4050 struct netdev_hw_addr *ha;
4051 u16 tbl_idx;
4052
4053 memset(mta_status, 0, sizeof(mta_status));
4054
4055 /* update mta_status from mc addr list */
4056 netdev_for_each_mc_addr(ha, netdev) {
4057 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
4058 set_bit(tbl_idx, mta_status);
4059 }
4060
4061 return hclge_update_mta_status_common(vport, mta_status,
4062 0, HCLGE_MTA_TBL_SIZE, true);
4063}
4064
4065int hclge_update_mta_status_common(struct hclge_vport *vport,
4066 unsigned long *status,
4067 u16 idx,
4068 u16 count,
4069 bool update_filter)
4070{
4071 struct hclge_dev *hdev = vport->back;
4072 u16 update_max = idx + count;
4073 u16 check_max;
4074 int ret = 0;
4075 bool used;
4076 u16 i;
4077
4078 /* setup mta check range */
4079 if (update_filter) {
4080 i = 0;
4081 check_max = HCLGE_MTA_TBL_SIZE;
4082 } else {
4083 i = idx;
4084 check_max = update_max;
4085 }
4086
4087 used = false;
4088 /* check and update all mta item */
4089 for (; i < check_max; i++) {
4090 /* ignore unused item */
4091 if (!test_bit(i, vport->mta_shadow))
4092 continue;
4093
4094 /* if i in update range then update it */
4095 if (i >= idx && i < update_max)
4096 if (!test_bit(i - idx, status))
4097 hclge_set_mta_table_item(vport, i, false);
4098
4099 if (!used && test_bit(i, vport->mta_shadow))
4100 used = true;
4101 }
4102
4103 /* no longer use mta, disable it */
4104 if (vport->accept_mta_mc && update_filter && !used) {
4105 ret = hclge_cfg_func_mta_filter(hdev,
4106 vport->vport_id,
4107 false);
4108 if (ret)
4109 dev_err(&hdev->pdev->dev,
4110 "disable func mta filter fail ret=%d\n",
4111 ret);
4112 else
4113 vport->accept_mta_mc = false;
4114 }
4115
4116 return ret;
4117}
4118
46a3df9f 4119static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4120 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 4121{
4122 struct hclge_dev *hdev = vport->back;
4123 struct hclge_desc desc;
4124 u8 resp_code;
a90bb9a5 4125 u16 retval;
46a3df9f
S		 4126 int ret;
4127
4128 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4129
d44f9b63 4130 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4131
4132 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4133 if (ret) {
4134 dev_err(&hdev->pdev->dev,
4135 "del mac addr failed for cmd_send, ret =%d.\n",
4136 ret);
4137 return ret;
4138 }
a90bb9a5
YL		 4139 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4140 retval = le16_to_cpu(desc.retval);
46a3df9f 4141
a90bb9a5 4142 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4143 HCLGE_MAC_VLAN_REMOVE);
4144}
4145
4146static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4147 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4148 struct hclge_desc *desc,
4149 bool is_mc)
4150{
4151 struct hclge_dev *hdev = vport->back;
4152 u8 resp_code;
a90bb9a5 4153 u16 retval;
46a3df9f
S		 4154 int ret;
4155
4156 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4157 if (is_mc) {
4158 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4159 memcpy(desc[0].data,
4160 req,
d44f9b63 4161 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4162 hclge_cmd_setup_basic_desc(&desc[1],
4163 HCLGE_OPC_MAC_VLAN_ADD,
4164 true);
4165 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4166 hclge_cmd_setup_basic_desc(&desc[2],
4167 HCLGE_OPC_MAC_VLAN_ADD,
4168 true);
4169 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4170 } else {
4171 memcpy(desc[0].data,
4172 req,
d44f9b63 4173 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4174 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4175 }
4176 if (ret) {
4177 dev_err(&hdev->pdev->dev,
4178 "lookup mac addr failed for cmd_send, ret =%d.\n",
4179 ret);
4180 return ret;
4181 }
a90bb9a5
YL		 4182 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4183 retval = le16_to_cpu(desc[0].retval);
46a3df9f 4184
a90bb9a5 4185 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4186 HCLGE_MAC_VLAN_LKUP);
4187}
4188
4189static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4190 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4191 struct hclge_desc *mc_desc)
4192{
4193 struct hclge_dev *hdev = vport->back;
4194 int cfg_status;
4195 u8 resp_code;
a90bb9a5 4196 u16 retval;
46a3df9f
S		 4197 int ret;
4198
4199 if (!mc_desc) {
4200 struct hclge_desc desc;
4201
4202 hclge_cmd_setup_basic_desc(&desc,
4203 HCLGE_OPC_MAC_VLAN_ADD,
4204 false);
d44f9b63
YL		 4205 memcpy(desc.data, req,
4206 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4207 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 4208 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4209 retval = le16_to_cpu(desc.retval);
4210
4211 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4212 resp_code,
4213 HCLGE_MAC_VLAN_ADD);
4214 } else {
c3b6f755 4215 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 4216 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4217 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 4218 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4219 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 4220 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4221 memcpy(mc_desc[0].data, req,
d44f9b63 4222 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4223 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 4224 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4225 retval = le16_to_cpu(mc_desc[0].retval);
4226
4227 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4228 resp_code,
4229 HCLGE_MAC_VLAN_ADD);
4230 }
4231
4232 if (ret) {
4233 dev_err(&hdev->pdev->dev,
4234 "add mac addr failed for cmd_send, ret =%d.\n",
4235 ret);
4236 return ret;
4237 }
4238
4239 return cfg_status;
4240}
4241
4242static int hclge_add_uc_addr(struct hnae3_handle *handle,
4243 const unsigned char *addr)
4244{
4245 struct hclge_vport *vport = hclge_get_vport(handle);
4246
4247 return hclge_add_uc_addr_common(vport, addr);
4248}
4249
4250int hclge_add_uc_addr_common(struct hclge_vport *vport,
4251 const unsigned char *addr)
4252{
4253 struct hclge_dev *hdev = vport->back;
d44f9b63 4254 struct hclge_mac_vlan_tbl_entry_cmd req;
bf88f41f 4255 struct hclge_desc desc;
a90bb9a5 4256 u16 egress_port = 0;
04f0c72a 4257 int ret;
46a3df9f
S		 4258
4259 /* mac addr check */
4260 if (is_zero_ether_addr(addr) ||
4261 is_broadcast_ether_addr(addr) ||
4262 is_multicast_ether_addr(addr)) {
4263 dev_err(&hdev->pdev->dev,
4264 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4265 addr,
4266 is_zero_ether_addr(addr),
4267 is_broadcast_ether_addr(addr),
4268 is_multicast_ether_addr(addr));
4269 return -EINVAL;
4270 }
4271
4272 memset(&req, 0, sizeof(req));
e22b531b 4273 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 4274
e22b531b
HT		 4275 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4276 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 4277
4278 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4279
4280 hclge_prepare_mac_addr(&req, addr);
4281
bf88f41f
JS		 4282 /* Lookup the mac address in the mac_vlan table, and add
4283 * it if the entry is inexistent. Repeated unicast entry
4284 * is not allowed in the mac vlan table.
4285 */
4286 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4287 if (ret == -ENOENT)
4288 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4289
4290 /* check if we just hit the duplicate */
4291 if (!ret)
4292 ret = -EINVAL;
4293
4294 dev_err(&hdev->pdev->dev,
4295 "PF failed to add unicast entry(%pM) in the MAC table\n",
4296 addr);
46a3df9f 4297
04f0c72a 4298 return ret;
46a3df9f
S		 4299}
4300
4301static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4302 const unsigned char *addr)
4303{
4304 struct hclge_vport *vport = hclge_get_vport(handle);
4305
4306 return hclge_rm_uc_addr_common(vport, addr);
4307}
4308
4309int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4310 const unsigned char *addr)
4311{
4312 struct hclge_dev *hdev = vport->back;
d44f9b63 4313 struct hclge_mac_vlan_tbl_entry_cmd req;
04f0c72a 4314 int ret;
46a3df9f
S		 4315
4316 /* mac addr check */
4317 if (is_zero_ether_addr(addr) ||
4318 is_broadcast_ether_addr(addr) ||
4319 is_multicast_ether_addr(addr)) {
4320 dev_dbg(&hdev->pdev->dev,
4321 "Remove mac err! invalid mac:%pM.\n",
4322 addr);
4323 return -EINVAL;
4324 }
4325
4326 memset(&req, 0, sizeof(req));
e22b531b
HT		 4327 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4328 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 4329 hclge_prepare_mac_addr(&req, addr);
04f0c72a 4330 ret = hclge_remove_mac_vlan_tbl(vport, &req);
46a3df9f 4331
04f0c72a 4332 return ret;
46a3df9f
S		 4333}
4334
4335static int hclge_add_mc_addr(struct hnae3_handle *handle,
4336 const unsigned char *addr)
4337{
4338 struct hclge_vport *vport = hclge_get_vport(handle);
4339
de4116e0 4340 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 4341}
4342
4343int hclge_add_mc_addr_common(struct hclge_vport *vport,
4344 const unsigned char *addr)
4345{
4346 struct hclge_dev *hdev = vport->back;
d44f9b63 4347 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4348 struct hclge_desc desc[3];
4349 u16 tbl_idx;
4350 int status;
4351
4352 /* mac addr check */
4353 if (!is_multicast_ether_addr(addr)) {
4354 dev_err(&hdev->pdev->dev,
4355 "Add mc mac err! invalid mac:%pM.\n",
4356 addr);
4357 return -EINVAL;
4358 }
4359 memset(&req, 0, sizeof(req));
e22b531b
HT		 4360 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4361 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4362 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4363 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f
S		 4364 hclge_prepare_mac_addr(&req, addr);
4365 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4366 if (!status) {
4367 /* This mac addr exist, update VFID for it */
4368 hclge_update_desc_vfid(desc, vport->vport_id, false);
4369 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4370 } else {
4371 /* This mac addr do not exist, add new entry for it */
4372 memset(desc[0].data, 0, sizeof(desc[0].data));
4373 memset(desc[1].data, 0, sizeof(desc[0].data));
4374 memset(desc[2].data, 0, sizeof(desc[0].data));
4375 hclge_update_desc_vfid(desc, vport->vport_id, false);
4376 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4377 }
4378
a832d8b5
XW		 4379 /* If mc mac vlan table is full, use MTA table */
4380 if (status == -ENOSPC) {
4381 if (!vport->accept_mta_mc) {
4382 status = hclge_cfg_func_mta_filter(hdev,
4383 vport->vport_id,
4384 true);
4385 if (status) {
4386 dev_err(&hdev->pdev->dev,
4387 "set mta filter mode fail ret=%d\n",
4388 status);
4389 return status;
4390 }
4391 vport->accept_mta_mc = true;
4392 }
4393
4394 /* Set MTA table for this MAC address */
4395 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4396 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4397 }
46a3df9f
S		 4398
4399 return status;
4400}
4401
4402static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4403 const unsigned char *addr)
4404{
4405 struct hclge_vport *vport = hclge_get_vport(handle);
4406
4407 return hclge_rm_mc_addr_common(vport, addr);
4408}
4409
4410int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4411 const unsigned char *addr)
4412{
4413 struct hclge_dev *hdev = vport->back;
d44f9b63 4414 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4415 enum hclge_cmd_status status;
4416 struct hclge_desc desc[3];
46a3df9f
S		 4417
4418 /* mac addr check */
4419 if (!is_multicast_ether_addr(addr)) {
4420 dev_dbg(&hdev->pdev->dev,
4421 "Remove mc mac err! invalid mac:%pM.\n",
4422 addr);
4423 return -EINVAL;
4424 }
4425
4426 memset(&req, 0, sizeof(req));
e22b531b
HT		 4427 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4428 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4429 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4430 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f
S		 4431 hclge_prepare_mac_addr(&req, addr);
4432 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4433 if (!status) {
4434 /* This mac addr exist, remove this handle's VFID for it */
4435 hclge_update_desc_vfid(desc, vport->vport_id, true);
4436
4437 if (hclge_is_all_function_id_zero(desc))
4438 /* All the vfid is zero, so need to delete this entry */
4439 status = hclge_remove_mac_vlan_tbl(vport, &req);
4440 else
4441 /* Not all the vfid is zero, update the vfid */
4442 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4443
4444 } else {
a832d8b5
XW		 4445 /* Maybe this mac address is in mta table, but it cannot be
4446 * deleted here because an entry of mta represents an address
4447 * range rather than a specific address. the delete action to
4448 * all entries will take effect in update_mta_status called by
4449 * hns3_nic_set_rx_mode.
4450 */
4451 status = 0;
46a3df9f
S		 4452 }
4453
46a3df9f
S		 4454 return status;
4455}
4456
635bfb58
FL		 4457static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4458 u16 cmdq_resp, u8 resp_code)
4459{
4460#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4461#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4462#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4463#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4464
4465 int return_status;
4466
4467 if (cmdq_resp) {
4468 dev_err(&hdev->pdev->dev,
4469 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4470 cmdq_resp);
4471 return -EIO;
4472 }
4473
4474 switch (resp_code) {
4475 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4476 case HCLGE_ETHERTYPE_ALREADY_ADD:
4477 return_status = 0;
4478 break;
4479 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4480 dev_err(&hdev->pdev->dev,
4481 "add mac ethertype failed for manager table overflow.\n");
4482 return_status = -EIO;
4483 break;
4484 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4485 dev_err(&hdev->pdev->dev,
4486 "add mac ethertype failed for key conflict.\n");
4487 return_status = -EIO;
4488 break;
4489 default:
4490 dev_err(&hdev->pdev->dev,
4491 "add mac ethertype failed for undefined, code=%d.\n",
4492 resp_code);
4493 return_status = -EIO;
4494 }
4495
4496 return return_status;
4497}
4498
4499static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4500 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4501{
4502 struct hclge_desc desc;
4503 u8 resp_code;
4504 u16 retval;
4505 int ret;
4506
4507 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4508 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4509
4510 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4511 if (ret) {
4512 dev_err(&hdev->pdev->dev,
4513 "add mac ethertype failed for cmd_send, ret =%d.\n",
4514 ret);
4515 return ret;
4516 }
4517
4518 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4519 retval = le16_to_cpu(desc.retval);
4520
4521 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4522}
4523
4524static int init_mgr_tbl(struct hclge_dev *hdev)
4525{
4526 int ret;
4527 int i;
4528
4529 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4530 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4531 if (ret) {
4532 dev_err(&hdev->pdev->dev,
4533 "add mac ethertype failed, ret =%d.\n",
4534 ret);
4535 return ret;
4536 }
4537 }
4538
4539 return 0;
4540}
4541
46a3df9f
S		 4542static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4543{
4544 struct hclge_vport *vport = hclge_get_vport(handle);
4545 struct hclge_dev *hdev = vport->back;
4546
4547 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4548}
4549
3cbf5e2d
FL		 4550static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4551 bool is_first)
46a3df9f
S		 4552{
4553 const unsigned char *new_addr = (const unsigned char *)p;
4554 struct hclge_vport *vport = hclge_get_vport(handle);
4555 struct hclge_dev *hdev = vport->back;
20a5c4c0 4556 int ret;
46a3df9f
S		 4557
4558 /* mac addr check */
4559 if (is_zero_ether_addr(new_addr) ||
4560 is_broadcast_ether_addr(new_addr) ||
4561 is_multicast_ether_addr(new_addr)) {
4562 dev_err(&hdev->pdev->dev,
4563 "Change uc mac err! invalid mac:%p.\n",
4564 new_addr);
4565 return -EINVAL;
4566 }
4567
3cbf5e2d 4568 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 4569 dev_warn(&hdev->pdev->dev,
3cbf5e2d 4570 "remove old uc mac address fail.\n");
46a3df9f 4571
20a5c4c0
FL		 4572 ret = hclge_add_uc_addr(handle, new_addr);
4573 if (ret) {
4574 dev_err(&hdev->pdev->dev,
4575 "add uc mac address fail, ret =%d.\n",
4576 ret);
4577
3cbf5e2d
FL		 4578 if (!is_first &&
4579 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 4580 dev_err(&hdev->pdev->dev,
3cbf5e2d 4581 "restore uc mac address fail.\n");
20a5c4c0
FL		 4582
4583 return -EIO;
46a3df9f
S		 4584 }
4585
532fdd5e 4586 ret = hclge_pause_addr_cfg(hdev, new_addr);
20a5c4c0
FL		 4587 if (ret) {
4588 dev_err(&hdev->pdev->dev,
4589 "configure mac pause address fail, ret =%d.\n",
4590 ret);
4591 return -EIO;
4592 }
4593
4594 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4595
4596 return 0;
46a3df9f
S		 4597}
4598
4599static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4600 bool filter_en)
4601{
d44f9b63 4602 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4603 struct hclge_desc desc;
4604 int ret;
4605
4606 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4607
d44f9b63 4608 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4609 req->vlan_type = vlan_type;
4610 req->vlan_fe = filter_en;
4611
4612 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 4613 if (ret)
46a3df9f
S		 4614 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4615 ret);
46a3df9f 4616
e125295a 4617 return ret;
46a3df9f
S		 4618}
4619
d818396d
JS		 4620#define HCLGE_FILTER_TYPE_VF 0
4621#define HCLGE_FILTER_TYPE_PORT 1
4622
4623static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4624{
4625 struct hclge_vport *vport = hclge_get_vport(handle);
4626 struct hclge_dev *hdev = vport->back;
4627
4628 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4629}
4630
4e66632d
YL		 4631static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4632 bool is_kill, u16 vlan, u8 qos,
4633 __be16 proto)
46a3df9f
S		 4634{
4635#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4636 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4637 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4638 struct hclge_desc desc[2];
4639 u8 vf_byte_val;
4640 u8 vf_byte_off;
4641 int ret;
4642
4643 hclge_cmd_setup_basic_desc(&desc[0],
4644 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4645 hclge_cmd_setup_basic_desc(&desc[1],
4646 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4647
4648 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4649
4650 vf_byte_off = vfid / 8;
4651 vf_byte_val = 1 << (vfid % 8);
4652
d44f9b63
YL		 4653 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4654 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4655
a90bb9a5 4656 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4657 req0->vlan_cfg = is_kill;
4658
4659 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4660 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4661 else
4662 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4663
4664 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4665 if (ret) {
4666 dev_err(&hdev->pdev->dev,
4667 "Send vf vlan command fail, ret =%d.\n",
4668 ret);
4669 return ret;
4670 }
4671
4672 if (!is_kill) {
715d610d 4673#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 4674 if (!req0->resp_code || req0->resp_code == 1)
4675 return 0;
4676
715d610d
YL		 4677 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4678 dev_warn(&hdev->pdev->dev,
4679 "vf vlan table is full, vf vlan filter is disabled\n");
4680 return 0;
4681 }
4682
46a3df9f
S		 4683 dev_err(&hdev->pdev->dev,
4684 "Add vf vlan filter fail, ret =%d.\n",
4685 req0->resp_code);
4686 } else {
4687 if (!req0->resp_code)
4688 return 0;
4689
4690 dev_err(&hdev->pdev->dev,
4691 "Kill vf vlan filter fail, ret =%d.\n",
4692 req0->resp_code);
4693 }
4694
4695 return -EIO;
4696}
4697
4e66632d
YL		 4698static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4699 u16 vlan_id, bool is_kill)
46a3df9f 4700{
d44f9b63 4701 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4702 struct hclge_desc desc;
4703 u8 vlan_offset_byte_val;
4704 u8 vlan_offset_byte;
4705 u8 vlan_offset_160;
4706 int ret;
4707
4708 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4709
4710 vlan_offset_160 = vlan_id / 160;
4711 vlan_offset_byte = (vlan_id % 160) / 8;
4712 vlan_offset_byte_val = 1 << (vlan_id % 8);
4713
d44f9b63 4714 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4715 req->vlan_offset = vlan_offset_160;
4716 req->vlan_cfg = is_kill;
4717 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4718
4719 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4e66632d
YL		 4720 if (ret)
4721 dev_err(&hdev->pdev->dev,
4722 "port vlan command, send fail, ret =%d.\n", ret);
4723 return ret;
4724}
4725
4726static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4727 u16 vport_id, u16 vlan_id, u8 qos,
4728 bool is_kill)
4729{
4730 u16 vport_idx, vport_num = 0;
4731 int ret;
4732
4733 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4734 0, proto);
46a3df9f
S		 4735 if (ret) {
4736 dev_err(&hdev->pdev->dev,
4e66632d
YL		 4737 "Set %d vport vlan filter config fail, ret =%d.\n",
4738 vport_id, ret);
46a3df9f
S		 4739 return ret;
4740 }
4741
4e66632d
YL		 4742 /* vlan 0 may be added twice when 8021q module is enabled */
4743 if (!is_kill && !vlan_id &&
4744 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4745 return 0;
4746
4747 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 4748 dev_err(&hdev->pdev->dev,
4e66632d
YL		 4749 "Add port vlan failed, vport %d is already in vlan %d\n",
4750 vport_id, vlan_id);
4751 return -EINVAL;
46a3df9f
S		 4752 }
4753
4e66632d
YL		 4754 if (is_kill &&
4755 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4756 dev_err(&hdev->pdev->dev,
4757 "Delete port vlan failed, vport %d is not in vlan %d\n",
4758 vport_id, vlan_id);
4759 return -EINVAL;
4760 }
4761
4762 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID)
4763 vport_num++;
4764
4765 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4766 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4767 is_kill);
4768
4769 return ret;
4770}
4771
4772int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4773 u16 vlan_id, bool is_kill)
4774{
4775 struct hclge_vport *vport = hclge_get_vport(handle);
4776 struct hclge_dev *hdev = vport->back;
4777
4778 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4779 0, is_kill);
46a3df9f
S		 4780}
4781
4782static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4783 u16 vlan, u8 qos, __be16 proto)
4784{
4785 struct hclge_vport *vport = hclge_get_vport(handle);
4786 struct hclge_dev *hdev = vport->back;
4787
4788 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4789 return -EINVAL;
4790 if (proto != htons(ETH_P_8021Q))
4791 return -EPROTONOSUPPORT;
4792
4e66632d 4793 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 4794}
4795
e62f2a6b
PL		 4796static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4797{
4798 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4799 struct hclge_vport_vtag_tx_cfg_cmd *req;
4800 struct hclge_dev *hdev = vport->back;
4801 struct hclge_desc desc;
4802 int status;
4803
4804 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4805
4806 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4807 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4808 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
e22b531b 4809 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
b75b1a56 4810 vcfg->accept_tag1 ? 1 : 0);
e22b531b 4811 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
b75b1a56 4812 vcfg->accept_untag1 ? 1 : 0);
e22b531b 4813 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
b75b1a56 4814 vcfg->accept_tag2 ? 1 : 0);
e22b531b 4815 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
b75b1a56 4816 vcfg->accept_untag2 ? 1 : 0);
e22b531b 4817 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
e62f2a6b 4818 vcfg->insert_tag1_en ? 1 : 0);
e22b531b 4819 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
e62f2a6b 4820 vcfg->insert_tag2_en ? 1 : 0);
e22b531b 4821 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
e62f2a6b
PL		 4822
4823 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4824 req->vf_bitmap[req->vf_offset] =
4825 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4826
4827 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4828 if (status)
4829 dev_err(&hdev->pdev->dev,
4830 "Send port txvlan cfg command fail, ret =%d\n",
4831 status);
4832
4833 return status;
4834}
4835
4836static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4837{
4838 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4839 struct hclge_vport_vtag_rx_cfg_cmd *req;
4840 struct hclge_dev *hdev = vport->back;
4841 struct hclge_desc desc;
4842 int status;
4843
4844 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4845
4846 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
e22b531b
HT		 4847 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4848 vcfg->strip_tag1_en ? 1 : 0);
4849 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4850 vcfg->strip_tag2_en ? 1 : 0);
4851 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4852 vcfg->vlan1_vlan_prionly ? 1 : 0);
4853 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4854 vcfg->vlan2_vlan_prionly ? 1 : 0);
e62f2a6b
PL		 4855
4856 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4857 req->vf_bitmap[req->vf_offset] =
4858 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4859
4860 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4861 if (status)
4862 dev_err(&hdev->pdev->dev,
4863 "Send port rxvlan cfg command fail, ret =%d\n",
4864 status);
4865
4866 return status;
4867}
4868
4869static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4870{
4871 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4872 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4873 struct hclge_desc desc;
4874 int status;
4875
4876 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4877 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4878 rx_req->ot_fst_vlan_type =
4879 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4880 rx_req->ot_sec_vlan_type =
4881 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4882 rx_req->in_fst_vlan_type =
4883 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4884 rx_req->in_sec_vlan_type =
4885 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4886
4887 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4888 if (status) {
4889 dev_err(&hdev->pdev->dev,
4890 "Send rxvlan protocol type command fail, ret =%d\n",
4891 status);
4892 return status;
4893 }
4894
4895 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4896
4897 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4898 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4899 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4900
4901 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4902 if (status)
4903 dev_err(&hdev->pdev->dev,
4904 "Send txvlan protocol type command fail, ret =%d\n",
4905 status);
4906
4907 return status;
4908}
4909
46a3df9f
S		 4910static int hclge_init_vlan_config(struct hclge_dev *hdev)
4911{
e62f2a6b
PL		 4912#define HCLGE_DEF_VLAN_TYPE 0x8100
4913
5e43aef8 4914 struct hnae3_handle *handle;
e62f2a6b 4915 struct hclge_vport *vport;
46a3df9f 4916 int ret;
e62f2a6b
PL		 4917 int i;
4918
4919 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4920 if (ret)
4921 return ret;
46a3df9f 4922
e62f2a6b 4923 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4924 if (ret)
4925 return ret;
4926
e62f2a6b
PL		 4927 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4928 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4929 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4930 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4931 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4932 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4933
4934 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4935 if (ret)
4936 return ret;
46a3df9f 4937
e62f2a6b
PL		 4938 for (i = 0; i < hdev->num_alloc_vport; i++) {
4939 vport = &hdev->vport[i];
b75b1a56
PL		 4940 vport->txvlan_cfg.accept_tag1 = true;
4941 vport->txvlan_cfg.accept_untag1 = true;
4942
4943 /* accept_tag2 and accept_untag2 are not supported on
4944 * pdev revision(0x20), new revision support them. The
4945 * value of this two fields will not return error when driver
4946 * send command to fireware in revision(0x20).
4947 * This two fields can not configured by user.
4948 */
4949 vport->txvlan_cfg.accept_tag2 = true;
4950 vport->txvlan_cfg.accept_untag2 = true;
4951
e62f2a6b
PL		 4952 vport->txvlan_cfg.insert_tag1_en = false;
4953 vport->txvlan_cfg.insert_tag2_en = false;
4954 vport->txvlan_cfg.default_tag1 = 0;
4955 vport->txvlan_cfg.default_tag2 = 0;
4956
4957 ret = hclge_set_vlan_tx_offload_cfg(vport);
4958 if (ret)
4959 return ret;
4960
4961 vport->rxvlan_cfg.strip_tag1_en = false;
4962 vport->rxvlan_cfg.strip_tag2_en = true;
4963 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4964 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4965
4966 ret = hclge_set_vlan_rx_offload_cfg(vport);
4967 if (ret)
4968 return ret;
4969 }
4970
5e43aef8 4971 handle = &hdev->vport[0].nic;
4e66632d 4972 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4973}
4974
3849d494 4975int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
5f9a7732
PL		 4976{
4977 struct hclge_vport *vport = hclge_get_vport(handle);
4978
4979 vport->rxvlan_cfg.strip_tag1_en = false;
4980 vport->rxvlan_cfg.strip_tag2_en = enable;
4981 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4982 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4983
4984 return hclge_set_vlan_rx_offload_cfg(vport);
4985}
4986
12341881 4987static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 4988{
d44f9b63 4989 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 4990 struct hclge_desc desc;
7393ed39 4991 int max_frm_size;
46a3df9f
S		 4992 int ret;
4993
7393ed39
FL		 4994 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4995
4996 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4997 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 4998 return -EINVAL;
4999
7393ed39
FL		 5000 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
5001
46a3df9f
S		 5002 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
5003
d44f9b63 5004 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
7393ed39 5005 req->max_frm_size = cpu_to_le16(max_frm_size);
46a3df9f
S		 5006
5007 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 5008 if (ret)
46a3df9f 5009 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
e125295a
JS		 5010 else
5011 hdev->mps = max_frm_size;
7393ed39 5012
e125295a 5013 return ret;
46a3df9f
S		 5014}
5015
12341881
FL		 5016static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
5017{
5018 struct hclge_vport *vport = hclge_get_vport(handle);
5019 struct hclge_dev *hdev = vport->back;
5020 int ret;
5021
5022 ret = hclge_set_mac_mtu(hdev, new_mtu);
5023 if (ret) {
5024 dev_err(&hdev->pdev->dev,
5025 "Change mtu fail, ret =%d\n", ret);
5026 return ret;
5027 }
5028
5029 ret = hclge_buffer_alloc(hdev);
5030 if (ret)
5031 dev_err(&hdev->pdev->dev,
5032 "Allocate buffer fail, ret =%d\n", ret);
5033
5034 return ret;
5035}
5036
46a3df9f
S		 5037static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
5038 bool enable)
5039{
d44f9b63 5040 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5041 struct hclge_desc desc;
5042 int ret;
5043
5044 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
5045
d44f9b63 5046 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 5047 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
e22b531b 5048 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 5049
5050 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5051 if (ret) {
5052 dev_err(&hdev->pdev->dev,
5053 "Send tqp reset cmd error, status =%d\n", ret);
5054 return ret;
5055 }
5056
5057 return 0;
5058}
5059
5060static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
5061{
d44f9b63 5062 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5063 struct hclge_desc desc;
5064 int ret;
5065
5066 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
5067
d44f9b63 5068 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 5069 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5070
5071 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5072 if (ret) {
5073 dev_err(&hdev->pdev->dev,
5074 "Get reset status error, status =%d\n", ret);
5075 return ret;
5076 }
5077
e22b531b 5078 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 5079}
5080
e5e89cda
PL		 5081static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
5082 u16 queue_id)
5083{
5084 struct hnae3_queue *queue;
5085 struct hclge_tqp *tqp;
5086
5087 queue = handle->kinfo.tqp[queue_id];
5088 tqp = container_of(queue, struct hclge_tqp, q);
5089
5090 return tqp->index;
5091}
5092
63d7e66f 5093void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 5094{
5095 struct hclge_vport *vport = hclge_get_vport(handle);
5096 struct hclge_dev *hdev = vport->back;
5097 int reset_try_times = 0;
5098 int reset_status;
e5e89cda 5099 u16 queue_gid;
46a3df9f
S		 5100 int ret;
5101
f9637cc2
PL		 5102 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5103 return;
5104
e5e89cda
PL		 5105 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
5106
46a3df9f
S		 5107 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
5108 if (ret) {
5109 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
5110 return;
5111 }
5112
e5e89cda 5113 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 5114 if (ret) {
5115 dev_warn(&hdev->pdev->dev,
5116 "Send reset tqp cmd fail, ret = %d\n", ret);
5117 return;
5118 }
5119
5120 reset_try_times = 0;
5121 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5122 /* Wait for tqp hw reset */
5123 msleep(20);
e5e89cda 5124 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 5125 if (reset_status)
5126 break;
5127 }
5128
5129 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5130 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5131 return;
5132 }
5133
e5e89cda 5134 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 5135 if (ret) {
5136 dev_warn(&hdev->pdev->dev,
5137 "Deassert the soft reset fail, ret = %d\n", ret);
5138 return;
5139 }
5140}
5141
d3ea7fc4
PL		 5142void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
5143{
5144 struct hclge_dev *hdev = vport->back;
5145 int reset_try_times = 0;
5146 int reset_status;
5147 u16 queue_gid;
5148 int ret;
5149
5150 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
5151
5152 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5153 if (ret) {
5154 dev_warn(&hdev->pdev->dev,
5155 "Send reset tqp cmd fail, ret = %d\n", ret);
5156 return;
5157 }
5158
5159 reset_try_times = 0;
5160 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5161 /* Wait for tqp hw reset */
5162 msleep(20);
5163 reset_status = hclge_get_reset_status(hdev, queue_gid);
5164 if (reset_status)
5165 break;
5166 }
5167
5168 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5169 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5170 return;
5171 }
5172
5173 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5174 if (ret)
5175 dev_warn(&hdev->pdev->dev,
5176 "Deassert the soft reset fail, ret = %d\n", ret);
5177}
5178
46a3df9f
S		 5179static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5180{
5181 struct hclge_vport *vport = hclge_get_vport(handle);
5182 struct hclge_dev *hdev = vport->back;
5183
5184 return hdev->fw_version;
5185}
5186
a2cfbadb
PL		 5187static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5188 u32 *flowctrl_adv)
5189{
5190 struct hclge_vport *vport = hclge_get_vport(handle);
5191 struct hclge_dev *hdev = vport->back;
5192 struct phy_device *phydev = hdev->hw.mac.phydev;
5193
5194 if (!phydev)
5195 return;
5196
5197 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5198 (phydev->advertising & ADVERTISED_Asym_Pause);
5199}
5200
09ea401e
PL		 5201static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5202{
5203 struct phy_device *phydev = hdev->hw.mac.phydev;
5204
5205 if (!phydev)
5206 return;
5207
5208 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
5209
5210 if (rx_en)
5211 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5212
5213 if (tx_en)
5214 phydev->advertising ^= ADVERTISED_Asym_Pause;
5215}
5216
5217static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5218{
09ea401e
PL		 5219 int ret;
5220
5221 if (rx_en && tx_en)
7a28a82a 5222 hdev->fc_mode_last_time = HCLGE_FC_FULL;
09ea401e 5223 else if (rx_en && !tx_en)
7a28a82a 5224 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
09ea401e 5225 else if (!rx_en && tx_en)
7a28a82a 5226 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
09ea401e 5227 else
7a28a82a 5228 hdev->fc_mode_last_time = HCLGE_FC_NONE;
09ea401e 5229
7a28a82a 5230 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
09ea401e 5231 return 0;
09ea401e
PL		 5232
5233 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
5234 if (ret) {
5235 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
5236 ret);
5237 return ret;
5238 }
5239
7a28a82a 5240 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
09ea401e
PL		 5241
5242 return 0;
5243}
5244
6282f2ea
PL		 5245int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5246{
5247 struct phy_device *phydev = hdev->hw.mac.phydev;
5248 u16 remote_advertising = 0;
5249 u16 local_advertising = 0;
5250 u32 rx_pause, tx_pause;
5251 u8 flowctl;
5252
5253 if (!phydev->link || !phydev->autoneg)
5254 return 0;
5255
5256 if (phydev->advertising & ADVERTISED_Pause)
5257 local_advertising = ADVERTISE_PAUSE_CAP;
5258
5259 if (phydev->advertising & ADVERTISED_Asym_Pause)
5260 local_advertising |= ADVERTISE_PAUSE_ASYM;
5261
5262 if (phydev->pause)
5263 remote_advertising = LPA_PAUSE_CAP;
5264
5265 if (phydev->asym_pause)
5266 remote_advertising |= LPA_PAUSE_ASYM;
5267
5268 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5269 remote_advertising);
5270 tx_pause = flowctl & FLOW_CTRL_TX;
5271 rx_pause = flowctl & FLOW_CTRL_RX;
5272
5273 if (phydev->duplex == HCLGE_MAC_HALF) {
5274 tx_pause = 0;
5275 rx_pause = 0;
5276 }
5277
5278 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5279}
5280
46a3df9f
S		 5281static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5282 u32 *rx_en, u32 *tx_en)
5283{
5284 struct hclge_vport *vport = hclge_get_vport(handle);
5285 struct hclge_dev *hdev = vport->back;
5286
5287 *auto_neg = hclge_get_autoneg(handle);
5288
5289 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5290 *rx_en = 0;
5291 *tx_en = 0;
5292 return;
5293 }
5294
5295 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5296 *rx_en = 1;
5297 *tx_en = 0;
5298 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5299 *tx_en = 1;
5300 *rx_en = 0;
5301 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5302 *rx_en = 1;
5303 *tx_en = 1;
5304 } else {
5305 *rx_en = 0;
5306 *tx_en = 0;
5307 }
5308}
5309
09ea401e
PL		 5310static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5311 u32 rx_en, u32 tx_en)
5312{
5313 struct hclge_vport *vport = hclge_get_vport(handle);
5314 struct hclge_dev *hdev = vport->back;
5315 struct phy_device *phydev = hdev->hw.mac.phydev;
5316 u32 fc_autoneg;
5317
09ea401e
PL		 5318 fc_autoneg = hclge_get_autoneg(handle);
5319 if (auto_neg != fc_autoneg) {
5320 dev_info(&hdev->pdev->dev,
5321 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5322 return -EOPNOTSUPP;
5323 }
5324
5325 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5326 dev_info(&hdev->pdev->dev,
5327 "Priority flow control enabled. Cannot set link flow control.\n");
5328 return -EOPNOTSUPP;
5329 }
5330
5331 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5332
5333 if (!fc_autoneg)
5334 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5335
bef24782
FL		 5336 /* Only support flow control negotiation for netdev with
5337 * phy attached for now.
5338 */
5339 if (!phydev)
5340 return -EOPNOTSUPP;
5341
09ea401e
PL		 5342 return phy_start_aneg(phydev);
5343}
5344
46a3df9f
S		 5345static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5346 u8 *auto_neg, u32 *speed, u8 *duplex)
5347{
5348 struct hclge_vport *vport = hclge_get_vport(handle);
5349 struct hclge_dev *hdev = vport->back;
5350
5351 if (speed)
5352 *speed = hdev->hw.mac.speed;
5353 if (duplex)
5354 *duplex = hdev->hw.mac.duplex;
5355 if (auto_neg)
5356 *auto_neg = hdev->hw.mac.autoneg;
5357}
5358
5359static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5360{
5361 struct hclge_vport *vport = hclge_get_vport(handle);
5362 struct hclge_dev *hdev = vport->back;
5363
5364 if (media_type)
5365 *media_type = hdev->hw.mac.media_type;
5366}
5367
5368static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5369 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5370{
5371 struct hclge_vport *vport = hclge_get_vport(handle);
5372 struct hclge_dev *hdev = vport->back;
5373 struct phy_device *phydev = hdev->hw.mac.phydev;
5374 int mdix_ctrl, mdix, retval, is_resolved;
5375
5376 if (!phydev) {
5377 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5378 *tp_mdix = ETH_TP_MDI_INVALID;
5379 return;
5380 }
5381
5382 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5383
5384 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
e22b531b
HT		 5385 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5386 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 5387
5388 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
e22b531b
HT		 5389 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5390 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 5391
5392 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5393
5394 switch (mdix_ctrl) {
5395 case 0x0:
5396 *tp_mdix_ctrl = ETH_TP_MDI;
5397 break;
5398 case 0x1:
5399 *tp_mdix_ctrl = ETH_TP_MDI_X;
5400 break;
5401 case 0x3:
5402 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5403 break;
5404 default:
5405 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5406 break;
5407 }
5408
5409 if (!is_resolved)
5410 *tp_mdix = ETH_TP_MDI_INVALID;
5411 else if (mdix)
5412 *tp_mdix = ETH_TP_MDI_X;
5413 else
5414 *tp_mdix = ETH_TP_MDI;
5415}
5416
5417static int hclge_init_client_instance(struct hnae3_client *client,
5418 struct hnae3_ae_dev *ae_dev)
5419{
5420 struct hclge_dev *hdev = ae_dev->priv;
5421 struct hclge_vport *vport;
5422 int i, ret;
5423
5424 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5425 vport = &hdev->vport[i];
5426
5427 switch (client->type) {
5428 case HNAE3_CLIENT_KNIC:
5429
5430 hdev->nic_client = client;
5431 vport->nic.client = client;
5432 ret = client->ops->init_instance(&vport->nic);
5433 if (ret)
6f636872 5434 return ret;
46a3df9f
S		 5435
5436 if (hdev->roce_client &&
e92a0843 5437 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5438 struct hnae3_client *rc = hdev->roce_client;
5439
5440 ret = hclge_init_roce_base_info(vport);
5441 if (ret)
6f636872 5442 return ret;
46a3df9f
S		 5443
5444 ret = rc->ops->init_instance(&vport->roce);
5445 if (ret)
6f636872 5446 return ret;
46a3df9f
S		 5447 }
5448
5449 break;
5450 case HNAE3_CLIENT_UNIC:
5451 hdev->nic_client = client;
5452 vport->nic.client = client;
5453
5454 ret = client->ops->init_instance(&vport->nic);
5455 if (ret)
6f636872 5456 return ret;
46a3df9f
S		 5457
5458 break;
5459 case HNAE3_CLIENT_ROCE:
e92a0843 5460 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5461 hdev->roce_client = client;
5462 vport->roce.client = client;
5463 }
5464
3a46f34d 5465 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5466 ret = hclge_init_roce_base_info(vport);
5467 if (ret)
6f636872 5468 return ret;
46a3df9f
S		 5469
5470 ret = client->ops->init_instance(&vport->roce);
5471 if (ret)
6f636872 5472 return ret;
46a3df9f
S		 5473 }
5474 }
5475 }
5476
5477 return 0;
46a3df9f
S		 5478}
5479
5480static void hclge_uninit_client_instance(struct hnae3_client *client,
5481 struct hnae3_ae_dev *ae_dev)
5482{
5483 struct hclge_dev *hdev = ae_dev->priv;
5484 struct hclge_vport *vport;
5485 int i;
5486
5487 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5488 vport = &hdev->vport[i];
a17dcf3f 5489 if (hdev->roce_client) {
46a3df9f
S		 5490 hdev->roce_client->ops->uninit_instance(&vport->roce,
5491 0);
a17dcf3f
L		 5492 hdev->roce_client = NULL;
5493 vport->roce.client = NULL;
5494 }
46a3df9f
S		 5495 if (client->type == HNAE3_CLIENT_ROCE)
5496 return;
a17dcf3f 5497 if (client->ops->uninit_instance) {
46a3df9f 5498 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5499 hdev->nic_client = NULL;
5500 vport->nic.client = NULL;
5501 }
46a3df9f
S		 5502 }
5503}
5504
5505static int hclge_pci_init(struct hclge_dev *hdev)
5506{
5507 struct pci_dev *pdev = hdev->pdev;
5508 struct hclge_hw *hw;
5509 int ret;
5510
5511 ret = pci_enable_device(pdev);
5512 if (ret) {
5513 dev_err(&pdev->dev, "failed to enable PCI device\n");
6c46284e 5514 return ret;
46a3df9f
S		 5515 }
5516
5517 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5518 if (ret) {
5519 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5520 if (ret) {
5521 dev_err(&pdev->dev,
5522 "can't set consistent PCI DMA");
5523 goto err_disable_device;
5524 }
5525 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5526 }
5527
5528 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5529 if (ret) {
5530 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5531 goto err_disable_device;
5532 }
5533
5534 pci_set_master(pdev);
5535 hw = &hdev->hw;
46a3df9f
S		 5536 hw->io_base = pcim_iomap(pdev, 2, 0);
5537 if (!hw->io_base) {
5538 dev_err(&pdev->dev, "Can't map configuration register space\n");
5539 ret = -ENOMEM;
5540 goto err_clr_master;
5541 }
5542
709eb41a
L		 5543 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5544
46a3df9f
S		 5545 return 0;
5546err_clr_master:
5547 pci_clear_master(pdev);
5548 pci_release_regions(pdev);
5549err_disable_device:
5550 pci_disable_device(pdev);
46a3df9f
S		 5551
5552 return ret;
5553}
5554
5555static void hclge_pci_uninit(struct hclge_dev *hdev)
5556{
5557 struct pci_dev *pdev = hdev->pdev;
5558
7d6d639b 5559 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 5560 pci_free_irq_vectors(pdev);
46a3df9f
S		 5561 pci_clear_master(pdev);
5562 pci_release_mem_regions(pdev);
5563 pci_disable_device(pdev);
5564}
5565
71d7e8ea
PL		 5566static void hclge_state_init(struct hclge_dev *hdev)
5567{
5568 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5569 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5570 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5571 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5572 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5573 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5574}
5575
5576static void hclge_state_uninit(struct hclge_dev *hdev)
5577{
5578 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5579
5580 if (hdev->service_timer.function)
5581 del_timer_sync(&hdev->service_timer);
5582 if (hdev->service_task.func)
5583 cancel_work_sync(&hdev->service_task);
5584 if (hdev->rst_service_task.func)
5585 cancel_work_sync(&hdev->rst_service_task);
5586 if (hdev->mbx_service_task.func)
5587 cancel_work_sync(&hdev->mbx_service_task);
5588}
5589
46a3df9f
S		 5590static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5591{
5592 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5593 struct hclge_dev *hdev;
5594 int ret;
5595
5596 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5597 if (!hdev) {
5598 ret = -ENOMEM;
e0027501 5599 goto out;
46a3df9f
S		 5600 }
5601
46a3df9f
S		 5602 hdev->pdev = pdev;
5603 hdev->ae_dev = ae_dev;
4ed340ab 5604 hdev->reset_type = HNAE3_NONE_RESET;
46a3df9f
S		 5605 ae_dev->priv = hdev;
5606
46a3df9f
S		 5607 ret = hclge_pci_init(hdev);
5608 if (ret) {
5609 dev_err(&pdev->dev, "PCI init failed\n");
e0027501 5610 goto out;
46a3df9f
S		 5611 }
5612
3efb960f
L		 5613 /* Firmware command queue initialize */
5614 ret = hclge_cmd_queue_init(hdev);
5615 if (ret) {
5616 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
e0027501 5617 goto err_pci_uninit;
3efb960f
L		 5618 }
5619
5620 /* Firmware command initialize */
46a3df9f
S		 5621 ret = hclge_cmd_init(hdev);
5622 if (ret)
e0027501 5623 goto err_cmd_uninit;
46a3df9f
S		 5624
5625 ret = hclge_get_cap(hdev);
5626 if (ret) {
e00e2197
CIK		 5627 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5628 ret);
e0027501 5629 goto err_cmd_uninit;
46a3df9f
S		 5630 }
5631
5632 ret = hclge_configure(hdev);
5633 if (ret) {
5634 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
e0027501 5635 goto err_cmd_uninit;
46a3df9f
S		 5636 }
5637
887c3820 5638 ret = hclge_init_msi(hdev);
46a3df9f 5639 if (ret) {
887c3820 5640 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
e0027501 5641 goto err_cmd_uninit;
46a3df9f
S		 5642 }
5643
466b0c00
L		 5644 ret = hclge_misc_irq_init(hdev);
5645 if (ret) {
5646 dev_err(&pdev->dev,
5647 "Misc IRQ(vector0) init error, ret = %d.\n",
5648 ret);
e0027501 5649 goto err_msi_uninit;
466b0c00
L		 5650 }
5651
46a3df9f
S		 5652 ret = hclge_alloc_tqps(hdev);
5653 if (ret) {
5654 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
e0027501 5655 goto err_msi_irq_uninit;
46a3df9f
S		 5656 }
5657
5658 ret = hclge_alloc_vport(hdev);
5659 if (ret) {
5660 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
e0027501 5661 goto err_msi_irq_uninit;
46a3df9f
S		 5662 }
5663
7df7dad6
L		 5664 ret = hclge_map_tqp(hdev);
5665 if (ret) {
5666 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
bc59f827 5667 goto err_msi_irq_uninit;
7df7dad6
L		 5668 }
5669
dea9a821
HT		 5670 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5671 ret = hclge_mac_mdio_config(hdev);
5672 if (ret) {
5673 dev_err(&hdev->pdev->dev,
5674 "mdio config fail ret=%d\n", ret);
bc59f827 5675 goto err_msi_irq_uninit;
dea9a821 5676 }
cf9cca2d 5677 }
5678
46a3df9f
S		 5679 ret = hclge_mac_init(hdev);
5680 if (ret) {
5681 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
e0027501 5682 goto err_mdiobus_unreg;
46a3df9f 5683 }
46a3df9f
S		 5684
5685 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5686 if (ret) {
5687 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
e0027501 5688 goto err_mdiobus_unreg;
46a3df9f
S		 5689 }
5690
46a3df9f
S		 5691 ret = hclge_init_vlan_config(hdev);
5692 if (ret) {
5693 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
e0027501 5694 goto err_mdiobus_unreg;
46a3df9f
S		 5695 }
5696
5697 ret = hclge_tm_schd_init(hdev);
5698 if (ret) {
5699 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
e0027501 5700 goto err_mdiobus_unreg;
68ece54e
YL		 5701 }
5702
8015bb74 5703 hclge_rss_init_cfg(hdev);
68ece54e
YL		 5704 ret = hclge_rss_init_hw(hdev);
5705 if (ret) {
5706 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
e0027501 5707 goto err_mdiobus_unreg;
46a3df9f
S		 5708 }
5709
635bfb58
FL		 5710 ret = init_mgr_tbl(hdev);
5711 if (ret) {
5712 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
e0027501 5713 goto err_mdiobus_unreg;
635bfb58
FL		 5714 }
5715
cacde272
YL		 5716 hclge_dcb_ops_set(hdev);
5717
d039ef68 5718 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5719 INIT_WORK(&hdev->service_task, hclge_service_task);
ed4a1bb8 5720 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
22fd3468 5721 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5722
466b0c00
L		 5723 /* Enable MISC vector(vector0) */
5724 hclge_enable_vector(&hdev->misc_vector, true);
5725
71d7e8ea 5726 hclge_state_init(hdev);
46a3df9f
S		 5727
5728 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5729 return 0;
5730
e0027501
HT		 5731err_mdiobus_unreg:
5732 if (hdev->hw.mac.phydev)
5733 mdiobus_unregister(hdev->hw.mac.mdio_bus);
e0027501
HT		 5734err_msi_irq_uninit:
5735 hclge_misc_irq_uninit(hdev);
5736err_msi_uninit:
5737 pci_free_irq_vectors(pdev);
5738err_cmd_uninit:
5739 hclge_destroy_cmd_queue(&hdev->hw);
5740err_pci_uninit:
7d6d639b 5741 pcim_iounmap(pdev, hdev->hw.io_base);
e0027501 5742 pci_clear_master(pdev);
46a3df9f 5743 pci_release_regions(pdev);
e0027501 5744 pci_disable_device(pdev);
e0027501 5745out:
46a3df9f
S		 5746 return ret;
5747}
5748
c6dc5213 5749static void hclge_stats_clear(struct hclge_dev *hdev)
5750{
5751 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5752}
5753
4ed340ab
L		 5754static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5755{
5756 struct hclge_dev *hdev = ae_dev->priv;
5757 struct pci_dev *pdev = ae_dev->pdev;
5758 int ret;
5759
5760 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5761
c6dc5213 5762 hclge_stats_clear(hdev);
4e66632d 5763 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 5764
4ed340ab
L		 5765 ret = hclge_cmd_init(hdev);
5766 if (ret) {
5767 dev_err(&pdev->dev, "Cmd queue init failed\n");
5768 return ret;
5769 }
5770
5771 ret = hclge_get_cap(hdev);
5772 if (ret) {
5773 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5774 ret);
5775 return ret;
5776 }
5777
5778 ret = hclge_configure(hdev);
5779 if (ret) {
5780 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5781 return ret;
5782 }
5783
5784 ret = hclge_map_tqp(hdev);
5785 if (ret) {
5786 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5787 return ret;
5788 }
5789
5790 ret = hclge_mac_init(hdev);
5791 if (ret) {
5792 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5793 return ret;
5794 }
5795
4ed340ab
L		 5796 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5797 if (ret) {
5798 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5799 return ret;
5800 }
5801
5802 ret = hclge_init_vlan_config(hdev);
5803 if (ret) {
5804 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5805 return ret;
5806 }
5807
d85f1ab5 5808 ret = hclge_tm_init_hw(hdev);
4ed340ab 5809 if (ret) {
d85f1ab5 5810 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 5811 return ret;
5812 }
5813
5814 ret = hclge_rss_init_hw(hdev);
5815 if (ret) {
5816 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5817 return ret;
5818 }
5819
4ed340ab
L		 5820 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5821 HCLGE_DRIVER_NAME);
5822
5823 return 0;
5824}
5825
46a3df9f
S		 5826static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5827{
5828 struct hclge_dev *hdev = ae_dev->priv;
5829 struct hclge_mac *mac = &hdev->hw.mac;
5830
71d7e8ea 5831 hclge_state_uninit(hdev);
46a3df9f
S		 5832
5833 if (mac->phydev)
5834 mdiobus_unregister(mac->mdio_bus);
5835
466b0c00
L		 5836 /* Disable MISC vector(vector0) */
5837 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 5838 hclge_destroy_cmd_queue(&hdev->hw);
202f2014 5839 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5840 hclge_pci_uninit(hdev);
5841 ae_dev->priv = NULL;
5842}
5843
4f645a90
PL		 5844static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5845{
5846 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5847 struct hclge_vport *vport = hclge_get_vport(handle);
5848 struct hclge_dev *hdev = vport->back;
5849
5850 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5851}
5852
5853static void hclge_get_channels(struct hnae3_handle *handle,
5854 struct ethtool_channels *ch)
5855{
5856 struct hclge_vport *vport = hclge_get_vport(handle);
5857
5858 ch->max_combined = hclge_get_max_channels(handle);
5859 ch->other_count = 1;
5860 ch->max_other = 1;
5861 ch->combined_count = vport->alloc_tqps;
5862}
5863
f1f779ce
PL		 5864static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5865 u16 *free_tqps, u16 *max_rss_size)
5866{
5867 struct hclge_vport *vport = hclge_get_vport(handle);
5868 struct hclge_dev *hdev = vport->back;
5869 u16 temp_tqps = 0;
5870 int i;
5871
5872 for (i = 0; i < hdev->num_tqps; i++) {
5873 if (!hdev->htqp[i].alloced)
5874 temp_tqps++;
5875 }
5876 *free_tqps = temp_tqps;
5877 *max_rss_size = hdev->rss_size_max;
5878}
5879
5880static void hclge_release_tqp(struct hclge_vport *vport)
5881{
5882 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5883 struct hclge_dev *hdev = vport->back;
5884 int i;
5885
5886 for (i = 0; i < kinfo->num_tqps; i++) {
5887 struct hclge_tqp *tqp =
5888 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5889
5890 tqp->q.handle = NULL;
5891 tqp->q.tqp_index = 0;
5892 tqp->alloced = false;
5893 }
5894
5895 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5896 kinfo->tqp = NULL;
5897}
5898
5899static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5900{
5901 struct hclge_vport *vport = hclge_get_vport(handle);
5902 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5903 struct hclge_dev *hdev = vport->back;
5904 int cur_rss_size = kinfo->rss_size;
5905 int cur_tqps = kinfo->num_tqps;
5906 u16 tc_offset[HCLGE_MAX_TC_NUM];
5907 u16 tc_valid[HCLGE_MAX_TC_NUM];
5908 u16 tc_size[HCLGE_MAX_TC_NUM];
5909 u16 roundup_size;
5910 u32 *rss_indir;
5911 int ret, i;
5912
ec7a62b9 5913 /* Free old tqps, and reallocate with new tqp number when nic setup */
f1f779ce
PL		 5914 hclge_release_tqp(vport);
5915
5916 ret = hclge_knic_setup(vport, new_tqps_num);
5917 if (ret) {
5918 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5919 return ret;
5920 }
5921
5922 ret = hclge_map_tqp_to_vport(hdev, vport);
5923 if (ret) {
5924 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5925 return ret;
5926 }
5927
5928 ret = hclge_tm_schd_init(hdev);
5929 if (ret) {
5930 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5931 return ret;
5932 }
5933
5934 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5935 roundup_size = ilog2(roundup_size);
5936 /* Set the RSS TC mode according to the new RSS size */
5937 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5938 tc_valid[i] = 0;
5939
5940 if (!(hdev->hw_tc_map & BIT(i)))
5941 continue;
5942
5943 tc_valid[i] = 1;
5944 tc_size[i] = roundup_size;
5945 tc_offset[i] = kinfo->rss_size * i;
5946 }
5947 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5948 if (ret)
5949 return ret;
5950
5951 /* Reinitializes the rss indirect table according to the new RSS size */
5952 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5953 if (!rss_indir)
5954 return -ENOMEM;
5955
5956 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5957 rss_indir[i] = i % kinfo->rss_size;
5958
5959 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5960 if (ret)
5961 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5962 ret);
5963
5964 kfree(rss_indir);
5965
5966 if (!ret)
5967 dev_info(&hdev->pdev->dev,
5968 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5969 cur_rss_size, kinfo->rss_size,
5970 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5971
5972 return ret;
5973}
5974
db2a3e43
FL		 5975static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5976 u32 *regs_num_64_bit)
5977{
5978 struct hclge_desc desc;
5979 u32 total_num;
5980 int ret;
5981
5982 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5983 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5984 if (ret) {
5985 dev_err(&hdev->pdev->dev,
5986 "Query register number cmd failed, ret = %d.\n", ret);
5987 return ret;
5988 }
5989
5990 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5991 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5992
5993 total_num = *regs_num_32_bit + *regs_num_64_bit;
5994 if (!total_num)
5995 return -EINVAL;
5996
5997 return 0;
5998}
5999
6000static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6001 void *data)
6002{
6003#define HCLGE_32_BIT_REG_RTN_DATANUM 8
6004
6005 struct hclge_desc *desc;
6006 u32 *reg_val = data;
6007 __le32 *desc_data;
6008 int cmd_num;
6009 int i, k, n;
6010 int ret;
6011
6012 if (regs_num == 0)
6013 return 0;
6014
6015 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
6016 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6017 if (!desc)
6018 return -ENOMEM;
6019
6020 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
6021 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6022 if (ret) {
6023 dev_err(&hdev->pdev->dev,
6024 "Query 32 bit register cmd failed, ret = %d.\n", ret);
6025 kfree(desc);
6026 return ret;
6027 }
6028
6029 for (i = 0; i < cmd_num; i++) {
6030 if (i == 0) {
6031 desc_data = (__le32 *)(&desc[i].data[0]);
6032 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
6033 } else {
6034 desc_data = (__le32 *)(&desc[i]);
6035 n = HCLGE_32_BIT_REG_RTN_DATANUM;
6036 }
6037 for (k = 0; k < n; k++) {
6038 *reg_val++ = le32_to_cpu(*desc_data++);
6039
6040 regs_num--;
6041 if (!regs_num)
6042 break;
6043 }
6044 }
6045
6046 kfree(desc);
6047 return 0;
6048}
6049
6050static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6051 void *data)
6052{
6053#define HCLGE_64_BIT_REG_RTN_DATANUM 4
6054
6055 struct hclge_desc *desc;
6056 u64 *reg_val = data;
6057 __le64 *desc_data;
6058 int cmd_num;
6059 int i, k, n;
6060 int ret;
6061
6062 if (regs_num == 0)
6063 return 0;
6064
6065 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
6066 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6067 if (!desc)
6068 return -ENOMEM;
6069
6070 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
6071 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6072 if (ret) {
6073 dev_err(&hdev->pdev->dev,
6074 "Query 64 bit register cmd failed, ret = %d.\n", ret);
6075 kfree(desc);
6076 return ret;
6077 }
6078
6079 for (i = 0; i < cmd_num; i++) {
6080 if (i == 0) {
6081 desc_data = (__le64 *)(&desc[i].data[0]);
6082 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
6083 } else {
6084 desc_data = (__le64 *)(&desc[i]);
6085 n = HCLGE_64_BIT_REG_RTN_DATANUM;
6086 }
6087 for (k = 0; k < n; k++) {
6088 *reg_val++ = le64_to_cpu(*desc_data++);
6089
6090 regs_num--;
6091 if (!regs_num)
6092 break;
6093 }
6094 }
6095
6096 kfree(desc);
6097 return 0;
6098}
6099
6100static int hclge_get_regs_len(struct hnae3_handle *handle)
6101{
6102 struct hclge_vport *vport = hclge_get_vport(handle);
6103 struct hclge_dev *hdev = vport->back;
6104 u32 regs_num_32_bit, regs_num_64_bit;
6105 int ret;
6106
6107 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6108 if (ret) {
6109 dev_err(&hdev->pdev->dev,
6110 "Get register number failed, ret = %d.\n", ret);
6111 return -EOPNOTSUPP;
6112 }
6113
6114 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
6115}
6116
6117static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
6118 void *data)
6119{
6120 struct hclge_vport *vport = hclge_get_vport(handle);
6121 struct hclge_dev *hdev = vport->back;
6122 u32 regs_num_32_bit, regs_num_64_bit;
6123 int ret;
6124
6125 *version = hdev->fw_version;
6126
6127 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6128 if (ret) {
6129 dev_err(&hdev->pdev->dev,
6130 "Get register number failed, ret = %d.\n", ret);
6131 return;
6132 }
6133
6134 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
6135 if (ret) {
6136 dev_err(&hdev->pdev->dev,
6137 "Get 32 bit register failed, ret = %d.\n", ret);
6138 return;
6139 }
6140
6141 data = (u32 *)data + regs_num_32_bit;
6142 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
6143 data);
6144 if (ret)
6145 dev_err(&hdev->pdev->dev,
6146 "Get 64 bit register failed, ret = %d.\n", ret);
6147}
6148
fe3a3e15 6149static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
d9a0884e
JS		 6150{
6151 struct hclge_set_led_state_cmd *req;
6152 struct hclge_desc desc;
6153 int ret;
6154
6155 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
6156
6157 req = (struct hclge_set_led_state_cmd *)desc.data;
e22b531b 6158 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
d9a0884e
JS		 6159 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6160
6161 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6162 if (ret)
6163 dev_err(&hdev->pdev->dev,
6164 "Send set led state cmd error, ret =%d\n", ret);
6165
6166 return ret;
6167}
6168
6169enum hclge_led_status {
6170 HCLGE_LED_OFF,
6171 HCLGE_LED_ON,
6172 HCLGE_LED_NO_CHANGE = 0xFF,
6173};
6174
6175static int hclge_set_led_id(struct hnae3_handle *handle,
6176 enum ethtool_phys_id_state status)
6177{
d9a0884e
JS		 6178 struct hclge_vport *vport = hclge_get_vport(handle);
6179 struct hclge_dev *hdev = vport->back;
d9a0884e
JS		 6180
6181 switch (status) {
6182 case ETHTOOL_ID_ACTIVE:
fe3a3e15 6183 return hclge_set_led_status(hdev, HCLGE_LED_ON);
d9a0884e 6184 case ETHTOOL_ID_INACTIVE:
fe3a3e15 6185 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
d9a0884e 6186 default:
fe3a3e15 6187 return -EINVAL;
d9a0884e 6188 }
d9a0884e
JS		 6189}
6190
d92ceae9
FL		 6191static void hclge_get_link_mode(struct hnae3_handle *handle,
6192 unsigned long *supported,
6193 unsigned long *advertising)
6194{
6195 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
6196 struct hclge_vport *vport = hclge_get_vport(handle);
6197 struct hclge_dev *hdev = vport->back;
6198 unsigned int idx = 0;
6199
6200 for (; idx < size; idx++) {
6201 supported[idx] = hdev->hw.mac.supported[idx];
6202 advertising[idx] = hdev->hw.mac.advertising[idx];
6203 }
6204}
6205
6206static void hclge_get_port_type(struct hnae3_handle *handle,
6207 u8 *port_type)
6208{
6209 struct hclge_vport *vport = hclge_get_vport(handle);
6210 struct hclge_dev *hdev = vport->back;
6211 u8 media_type = hdev->hw.mac.media_type;
6212
6213 switch (media_type) {
6214 case HNAE3_MEDIA_TYPE_FIBER:
6215 *port_type = PORT_FIBRE;
6216 break;
6217 case HNAE3_MEDIA_TYPE_COPPER:
6218 *port_type = PORT_TP;
6219 break;
6220 case HNAE3_MEDIA_TYPE_UNKNOWN:
6221 default:
6222 *port_type = PORT_OTHER;
6223 break;
6224 }
6225}
6226
46a3df9f
S		 6227static const struct hnae3_ae_ops hclge_ops = {
6228 .init_ae_dev = hclge_init_ae_dev,
6229 .uninit_ae_dev = hclge_uninit_ae_dev,
6230 .init_client_instance = hclge_init_client_instance,
6231 .uninit_client_instance = hclge_uninit_client_instance,
63d7e66f
SM		 6232 .map_ring_to_vector = hclge_map_ring_to_vector,
6233 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 6234 .get_vector = hclge_get_vector,
7412200c 6235 .put_vector = hclge_put_vector,
46a3df9f 6236 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 6237 .set_loopback = hclge_set_loopback,
46a3df9f
S		 6238 .start = hclge_ae_start,
6239 .stop = hclge_ae_stop,
6240 .get_status = hclge_get_status,
6241 .get_ksettings_an_result = hclge_get_ksettings_an_result,
6242 .update_speed_duplex_h = hclge_update_speed_duplex_h,
6243 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6244 .get_media_type = hclge_get_media_type,
6245 .get_rss_key_size = hclge_get_rss_key_size,
6246 .get_rss_indir_size = hclge_get_rss_indir_size,
6247 .get_rss = hclge_get_rss,
6248 .set_rss = hclge_set_rss,
f7db940a 6249 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 6250 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 6251 .get_tc_size = hclge_get_tc_size,
6252 .get_mac_addr = hclge_get_mac_addr,
6253 .set_mac_addr = hclge_set_mac_addr,
6254 .add_uc_addr = hclge_add_uc_addr,
6255 .rm_uc_addr = hclge_rm_uc_addr,
6256 .add_mc_addr = hclge_add_mc_addr,
6257 .rm_mc_addr = hclge_rm_mc_addr,
a832d8b5 6258 .update_mta_status = hclge_update_mta_status,
46a3df9f
S		 6259 .set_autoneg = hclge_set_autoneg,
6260 .get_autoneg = hclge_get_autoneg,
6261 .get_pauseparam = hclge_get_pauseparam,
09ea401e 6262 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6263 .set_mtu = hclge_set_mtu,
6264 .reset_queue = hclge_reset_tqp,
6265 .get_stats = hclge_get_stats,
6266 .update_stats = hclge_update_stats,
6267 .get_strings = hclge_get_strings,
6268 .get_sset_count = hclge_get_sset_count,
6269 .get_fw_version = hclge_get_fw_version,
6270 .get_mdix_mode = hclge_get_mdix_mode,
d818396d 6271 .enable_vlan_filter = hclge_enable_vlan_filter,
4e66632d 6272 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 6273 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5f9a7732 6274 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6275 .reset_event = hclge_reset_event,
f1f779ce
PL		 6276 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6277 .set_channels = hclge_set_channels,
4f645a90 6278 .get_channels = hclge_get_channels,
a2cfbadb 6279 .get_flowctrl_adv = hclge_get_flowctrl_adv,
db2a3e43
FL		 6280 .get_regs_len = hclge_get_regs_len,
6281 .get_regs = hclge_get_regs,
d9a0884e 6282 .set_led_id = hclge_set_led_id,
d92ceae9
FL		 6283 .get_link_mode = hclge_get_link_mode,
6284 .get_port_type = hclge_get_port_type,
46a3df9f
S		 6285};
6286
6287static struct hnae3_ae_algo ae_algo = {
6288 .ops = &hclge_ops,
46a3df9f
S		 6289 .pdev_id_table = ae_algo_pci_tbl,
6290};
6291
6292static int hclge_init(void)
6293{
6294 pr_info("%s is initializing\n", HCLGE_NAME);
6295
a4d090cc
FL		 6296 hnae3_register_ae_algo(&ae_algo);
6297
6298 return 0;
46a3df9f
S		 6299}
6300
6301static void hclge_exit(void)
6302{
6303 hnae3_unregister_ae_algo(&ae_algo);
6304}
6305module_init(hclge_init);
6306module_exit(hclge_exit);
6307
6308MODULE_LICENSE("GPL");
6309MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6310MODULE_DESCRIPTION("HCLGE Driver");
6311MODULE_VERSION(HCLGE_MOD_VERSION);
ubuntu-bionic-kernel mirror