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net: hns3: add set_default_reset_request in the hnae3_ae_ops
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
ef57c40f
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
46a3df9f
S		 3
4#include <linux/acpi.h>
5#include <linux/device.h>
6#include <linux/etherdevice.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
7393ed39 14#include <linux/if_vlan.h>
d5752031 15#include <net/rtnetlink.h>
46a3df9f 16#include "hclge_cmd.h"
cacde272 17#include "hclge_dcb.h"
46a3df9f 18#include "hclge_main.h"
0cdbdd3e 19#include "hclge_mbx.h"
46a3df9f
S		 20#include "hclge_mdio.h"
21#include "hclge_tm.h"
00bb612a 22#include "hclge_err.h"
46a3df9f
S		 23#include "hnae3.h"
24
25#define HCLGE_NAME "hclge"
26#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
27#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
46a3df9f 28
59bc85ec 29static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 30static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 31static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
2da5ec58
JS		 32static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
33 u16 *allocated_size, bool is_alloc);
46a3df9f
S		 34
35static struct hnae3_ae_algo ae_algo;
36
37static const struct pci_device_id ae_algo_pci_tbl[] = {
38 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
39 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 45 /* required last entry */
46a3df9f
S		 46 {0, }
47};
48
28d9cec8
YL		 49MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
50
46a3df9f 51static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
67b8c316 52 "App Loopback test",
86957272
FL		 53 "Serdes serial Loopback test",
54 "Serdes parallel Loopback test",
46a3df9f
S		 55 "Phy Loopback test"
56};
57
46a3df9f
S		 58static const struct hclge_comm_stats_str g_mac_stats_string[] = {
59 {"mac_tx_mac_pause_num",
60 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
61 {"mac_rx_mac_pause_num",
62 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
63 {"mac_tx_pfc_pri0_pkt_num",
64 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
65 {"mac_tx_pfc_pri1_pkt_num",
66 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
67 {"mac_tx_pfc_pri2_pkt_num",
68 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
69 {"mac_tx_pfc_pri3_pkt_num",
70 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
71 {"mac_tx_pfc_pri4_pkt_num",
72 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
73 {"mac_tx_pfc_pri5_pkt_num",
74 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
75 {"mac_tx_pfc_pri6_pkt_num",
76 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
77 {"mac_tx_pfc_pri7_pkt_num",
78 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
79 {"mac_rx_pfc_pri0_pkt_num",
80 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
81 {"mac_rx_pfc_pri1_pkt_num",
82 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
83 {"mac_rx_pfc_pri2_pkt_num",
84 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
85 {"mac_rx_pfc_pri3_pkt_num",
86 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
87 {"mac_rx_pfc_pri4_pkt_num",
88 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
89 {"mac_rx_pfc_pri5_pkt_num",
90 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
91 {"mac_rx_pfc_pri6_pkt_num",
92 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
93 {"mac_rx_pfc_pri7_pkt_num",
94 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
95 {"mac_tx_total_pkt_num",
96 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
97 {"mac_tx_total_oct_num",
98 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
99 {"mac_tx_good_pkt_num",
100 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
101 {"mac_tx_bad_pkt_num",
102 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
103 {"mac_tx_good_oct_num",
104 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
105 {"mac_tx_bad_oct_num",
106 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
107 {"mac_tx_uni_pkt_num",
108 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
109 {"mac_tx_multi_pkt_num",
110 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
111 {"mac_tx_broad_pkt_num",
112 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
113 {"mac_tx_undersize_pkt_num",
114 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
f3426583
JS		 115 {"mac_tx_oversize_pkt_num",
116 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 117 {"mac_tx_64_oct_pkt_num",
118 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
119 {"mac_tx_65_127_oct_pkt_num",
120 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
121 {"mac_tx_128_255_oct_pkt_num",
122 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
123 {"mac_tx_256_511_oct_pkt_num",
124 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
125 {"mac_tx_512_1023_oct_pkt_num",
126 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
127 {"mac_tx_1024_1518_oct_pkt_num",
128 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
b42874e4
JS		 129 {"mac_tx_1519_2047_oct_pkt_num",
130 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
131 {"mac_tx_2048_4095_oct_pkt_num",
132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
133 {"mac_tx_4096_8191_oct_pkt_num",
134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
b42874e4
JS		 135 {"mac_tx_8192_9216_oct_pkt_num",
136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
137 {"mac_tx_9217_12287_oct_pkt_num",
138 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
139 {"mac_tx_12288_16383_oct_pkt_num",
140 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
141 {"mac_tx_1519_max_good_pkt_num",
142 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
143 {"mac_tx_1519_max_bad_pkt_num",
144 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 145 {"mac_rx_total_pkt_num",
146 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
147 {"mac_rx_total_oct_num",
148 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
149 {"mac_rx_good_pkt_num",
150 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
151 {"mac_rx_bad_pkt_num",
152 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
153 {"mac_rx_good_oct_num",
154 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
155 {"mac_rx_bad_oct_num",
156 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
157 {"mac_rx_uni_pkt_num",
158 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
159 {"mac_rx_multi_pkt_num",
160 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
161 {"mac_rx_broad_pkt_num",
162 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
163 {"mac_rx_undersize_pkt_num",
164 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
f3426583
JS		 165 {"mac_rx_oversize_pkt_num",
166 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 167 {"mac_rx_64_oct_pkt_num",
168 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
169 {"mac_rx_65_127_oct_pkt_num",
170 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
171 {"mac_rx_128_255_oct_pkt_num",
172 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
173 {"mac_rx_256_511_oct_pkt_num",
174 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
175 {"mac_rx_512_1023_oct_pkt_num",
176 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
177 {"mac_rx_1024_1518_oct_pkt_num",
178 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
b42874e4
JS		 179 {"mac_rx_1519_2047_oct_pkt_num",
180 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
181 {"mac_rx_2048_4095_oct_pkt_num",
182 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
183 {"mac_rx_4096_8191_oct_pkt_num",
184 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
b42874e4
JS		 185 {"mac_rx_8192_9216_oct_pkt_num",
186 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
187 {"mac_rx_9217_12287_oct_pkt_num",
188 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
189 {"mac_rx_12288_16383_oct_pkt_num",
190 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
191 {"mac_rx_1519_max_good_pkt_num",
192 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
193 {"mac_rx_1519_max_bad_pkt_num",
194 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 195
c36317be
JS		 196 {"mac_tx_fragment_pkt_num",
197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
198 {"mac_tx_undermin_pkt_num",
199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
200 {"mac_tx_jabber_pkt_num",
201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
202 {"mac_tx_err_all_pkt_num",
203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
204 {"mac_tx_from_app_good_pkt_num",
205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
206 {"mac_tx_from_app_bad_pkt_num",
207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
208 {"mac_rx_fragment_pkt_num",
209 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
210 {"mac_rx_undermin_pkt_num",
211 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
212 {"mac_rx_jabber_pkt_num",
213 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
214 {"mac_rx_fcs_err_pkt_num",
215 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
216 {"mac_rx_send_app_good_pkt_num",
217 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
218 {"mac_rx_send_app_bad_pkt_num",
219 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 220};
221
635bfb58
FL		 222static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
223 {
224 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
225 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
226 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
227 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
228 .i_port_bitmap = 0x1,
229 },
230};
231
46a3df9f
S		 232static int hclge_mac_update_stats(struct hclge_dev *hdev)
233{
b42874e4 234#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 235#define HCLGE_RTN_DATA_NUM 4
236
237 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
238 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 239 __le64 *desc_data;
46a3df9f
S		 240 int i, k, n;
241 int ret;
242
243 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
244 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
245 if (ret) {
246 dev_err(&hdev->pdev->dev,
247 "Get MAC pkt stats fail, status = %d.\n", ret);
248
249 return ret;
250 }
251
252 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
253 if (unlikely(i == 0)) {
a90bb9a5 254 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 255 n = HCLGE_RTN_DATA_NUM - 2;
256 } else {
a90bb9a5 257 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 258 n = HCLGE_RTN_DATA_NUM;
259 }
260 for (k = 0; k < n; k++) {
a90bb9a5 261 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 262 desc_data++;
263 }
264 }
265
266 return 0;
267}
268
269static int hclge_tqps_update_stats(struct hnae3_handle *handle)
270{
271 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
272 struct hclge_vport *vport = hclge_get_vport(handle);
273 struct hclge_dev *hdev = vport->back;
274 struct hnae3_queue *queue;
275 struct hclge_desc desc[1];
276 struct hclge_tqp *tqp;
277 int ret, i;
278
279 for (i = 0; i < kinfo->num_tqps; i++) {
280 queue = handle->kinfo.tqp[i];
281 tqp = container_of(queue, struct hclge_tqp, q);
282 /* command : HCLGE_OPC_QUERY_IGU_STAT */
283 hclge_cmd_setup_basic_desc(&desc[0],
284 HCLGE_OPC_QUERY_RX_STATUS,
285 true);
286
a90bb9a5 287 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 288 ret = hclge_cmd_send(&hdev->hw, desc, 1);
289 if (ret) {
290 dev_err(&hdev->pdev->dev,
291 "Query tqp stat fail, status = %d,queue = %d\n",
292 ret, i);
293 return ret;
294 }
295 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 296 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 297 }
298
299 for (i = 0; i < kinfo->num_tqps; i++) {
300 queue = handle->kinfo.tqp[i];
301 tqp = container_of(queue, struct hclge_tqp, q);
302 /* command : HCLGE_OPC_QUERY_IGU_STAT */
303 hclge_cmd_setup_basic_desc(&desc[0],
304 HCLGE_OPC_QUERY_TX_STATUS,
305 true);
306
a90bb9a5 307 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 308 ret = hclge_cmd_send(&hdev->hw, desc, 1);
309 if (ret) {
310 dev_err(&hdev->pdev->dev,
311 "Query tqp stat fail, status = %d,queue = %d\n",
312 ret, i);
313 return ret;
314 }
315 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 316 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 317 }
318
319 return 0;
320}
321
322static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
323{
324 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
325 struct hclge_tqp *tqp;
326 u64 *buff = data;
327 int i;
328
329 for (i = 0; i < kinfo->num_tqps; i++) {
330 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 331 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 332 }
333
334 for (i = 0; i < kinfo->num_tqps; i++) {
335 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 336 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 337 }
338
339 return buff;
340}
341
342static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
343{
344 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
345
346 return kinfo->num_tqps * (2);
347}
348
349static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
350{
351 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
352 u8 *buff = data;
353 int i = 0;
354
355 for (i = 0; i < kinfo->num_tqps; i++) {
356 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
357 struct hclge_tqp, q);
eedff8c0 358 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
46a3df9f
S		 359 tqp->index);
360 buff = buff + ETH_GSTRING_LEN;
361 }
362
363 for (i = 0; i < kinfo->num_tqps; i++) {
364 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
365 struct hclge_tqp, q);
eedff8c0 366 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
46a3df9f
S		 367 tqp->index);
368 buff = buff + ETH_GSTRING_LEN;
369 }
370
371 return buff;
372}
373
374static u64 *hclge_comm_get_stats(void *comm_stats,
375 const struct hclge_comm_stats_str strs[],
376 int size, u64 *data)
377{
378 u64 *buf = data;
379 u32 i;
380
381 for (i = 0; i < size; i++)
382 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
383
384 return buf + size;
385}
386
387static u8 *hclge_comm_get_strings(u32 stringset,
388 const struct hclge_comm_stats_str strs[],
389 int size, u8 *data)
390{
391 char *buff = (char *)data;
392 u32 i;
393
394 if (stringset != ETH_SS_STATS)
395 return buff;
396
397 for (i = 0; i < size; i++) {
398 snprintf(buff, ETH_GSTRING_LEN,
399 strs[i].desc);
400 buff = buff + ETH_GSTRING_LEN;
401 }
402
403 return (u8 *)buff;
404}
405
406static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
407 struct net_device_stats *net_stats)
408{
409 net_stats->tx_dropped = 0;
f3426583 410 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 411 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
c36317be 412 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 413
414 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
415 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
416
c36317be 417 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 418 net_stats->rx_length_errors =
419 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
420 net_stats->rx_length_errors +=
f3426583 421 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 422 net_stats->rx_over_errors =
f3426583 423 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 424}
425
426static void hclge_update_stats_for_all(struct hclge_dev *hdev)
427{
428 struct hnae3_handle *handle;
429 int status;
430
431 handle = &hdev->vport[0].nic;
432 if (handle->client) {
433 status = hclge_tqps_update_stats(handle);
434 if (status) {
435 dev_err(&hdev->pdev->dev,
436 "Update TQPS stats fail, status = %d.\n",
437 status);
438 }
439 }
440
441 status = hclge_mac_update_stats(hdev);
442 if (status)
443 dev_err(&hdev->pdev->dev,
444 "Update MAC stats fail, status = %d.\n", status);
445
46a3df9f
S		 446 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
447}
448
449static void hclge_update_stats(struct hnae3_handle *handle,
450 struct net_device_stats *net_stats)
451{
452 struct hclge_vport *vport = hclge_get_vport(handle);
453 struct hclge_dev *hdev = vport->back;
454 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
455 int status;
456
7a5d2a39
JS		 457 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
458 return;
459
46a3df9f
S		 460 status = hclge_mac_update_stats(hdev);
461 if (status)
462 dev_err(&hdev->pdev->dev,
463 "Update MAC stats fail, status = %d.\n",
464 status);
465
46a3df9f
S		 466 status = hclge_tqps_update_stats(handle);
467 if (status)
468 dev_err(&hdev->pdev->dev,
469 "Update TQPS stats fail, status = %d.\n",
470 status);
471
472 hclge_update_netstat(hw_stats, net_stats);
7a5d2a39
JS		 473
474 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 475}
476
477static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
478{
86957272
FL		 479#define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
480 HNAE3_SUPPORT_PHY_LOOPBACK |\
481 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
482 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
46a3df9f
S		 483
484 struct hclge_vport *vport = hclge_get_vport(handle);
485 struct hclge_dev *hdev = vport->back;
486 int count = 0;
487
488 /* Loopback test support rules:
489 * mac: only GE mode support
490 * serdes: all mac mode will support include GE/XGE/LGE/CGE
491 * phy: only support when phy device exist on board
492 */
493 if (stringset == ETH_SS_TEST) {
494 /* clear loopback bit flags at first */
495 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
735f1df8 496 if (hdev->pdev->revision >= 0x21 ||
86957272 497 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
46a3df9f
S		 498 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
499 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
500 count += 1;
67b8c316 501 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
46a3df9f 502 }
e006bb00 503
86957272
FL		 504 count += 2;
505 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
506 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
46a3df9f
S		 507 } else if (stringset == ETH_SS_STATS) {
508 count = ARRAY_SIZE(g_mac_stats_string) +
46a3df9f
S		 509 hclge_tqps_get_sset_count(handle, stringset);
510 }
511
512 return count;
513}
514
515static void hclge_get_strings(struct hnae3_handle *handle,
516 u32 stringset,
517 u8 *data)
518{
519 u8 *p = (char *)data;
520 int size;
521
522 if (stringset == ETH_SS_STATS) {
523 size = ARRAY_SIZE(g_mac_stats_string);
524 p = hclge_comm_get_strings(stringset,
525 g_mac_stats_string,
526 size,
527 p);
46a3df9f
S		 528 p = hclge_tqps_get_strings(handle, p);
529 } else if (stringset == ETH_SS_TEST) {
67b8c316 530 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
46a3df9f 531 memcpy(p,
67b8c316 532 hns3_nic_test_strs[HNAE3_LOOP_APP],
46a3df9f
S		 533 ETH_GSTRING_LEN);
534 p += ETH_GSTRING_LEN;
535 }
86957272 536 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
46a3df9f 537 memcpy(p,
86957272
FL		 538 hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
539 ETH_GSTRING_LEN);
540 p += ETH_GSTRING_LEN;
541 }
542 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
543 memcpy(p,
544 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
46a3df9f
S		 545 ETH_GSTRING_LEN);
546 p += ETH_GSTRING_LEN;
547 }
548 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
549 memcpy(p,
e05cfaaf 550 hns3_nic_test_strs[HNAE3_LOOP_PHY],
46a3df9f
S		 551 ETH_GSTRING_LEN);
552 p += ETH_GSTRING_LEN;
553 }
554 }
555}
556
557static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
558{
559 struct hclge_vport *vport = hclge_get_vport(handle);
560 struct hclge_dev *hdev = vport->back;
561 u64 *p;
562
563 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
564 g_mac_stats_string,
565 ARRAY_SIZE(g_mac_stats_string),
566 data);
46a3df9f
S		 567 p = hclge_tqps_get_stats(handle, p);
568}
569
570static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 571 struct hclge_func_status_cmd *status)
46a3df9f
S		 572{
573 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
574 return -EINVAL;
575
576 /* Set the pf to main pf */
577 if (status->pf_state & HCLGE_PF_STATE_MAIN)
578 hdev->flag |= HCLGE_FLAG_MAIN;
579 else
580 hdev->flag &= ~HCLGE_FLAG_MAIN;
581
46a3df9f
S		 582 return 0;
583}
584
585static int hclge_query_function_status(struct hclge_dev *hdev)
586{
d44f9b63 587 struct hclge_func_status_cmd *req;
46a3df9f
S		 588 struct hclge_desc desc;
589 int timeout = 0;
590 int ret;
591
592 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 593 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 594
595 do {
596 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
597 if (ret) {
598 dev_err(&hdev->pdev->dev,
599 "query function status failed %d.\n",
600 ret);
601
602 return ret;
603 }
604
605 /* Check pf reset is done */
606 if (req->pf_state)
607 break;
608 usleep_range(1000, 2000);
609 } while (timeout++ < 5);
610
611 ret = hclge_parse_func_status(hdev, req);
612
613 return ret;
614}
615
616static int hclge_query_pf_resource(struct hclge_dev *hdev)
617{
d44f9b63 618 struct hclge_pf_res_cmd *req;
46a3df9f
S		 619 struct hclge_desc desc;
620 int ret;
621
622 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
623 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
624 if (ret) {
625 dev_err(&hdev->pdev->dev,
626 "query pf resource failed %d.\n", ret);
627 return ret;
628 }
629
d44f9b63 630 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 631 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
632 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
633
e92a0843 634 if (hnae3_dev_roce_supported(hdev)) {
5355e6d3
JS		 635 hdev->roce_base_msix_offset =
636 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
637 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
887c3820 638 hdev->num_roce_msi =
ccc23ef3
PL		 639 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
640 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 641
642 /* PF should have NIC vectors and Roce vectors,
643 * NIC vectors are queued before Roce vectors.
644 */
5355e6d3
JS		 645 hdev->num_msi = hdev->num_roce_msi +
646 hdev->roce_base_msix_offset;
46a3df9f
S		 647 } else {
648 hdev->num_msi =
ccc23ef3
PL		 649 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
650 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 651 }
652
653 return 0;
654}
655
656static int hclge_parse_speed(int speed_cmd, int *speed)
657{
658 switch (speed_cmd) {
659 case 6:
660 *speed = HCLGE_MAC_SPEED_10M;
661 break;
662 case 7:
663 *speed = HCLGE_MAC_SPEED_100M;
664 break;
665 case 0:
666 *speed = HCLGE_MAC_SPEED_1G;
667 break;
668 case 1:
669 *speed = HCLGE_MAC_SPEED_10G;
670 break;
671 case 2:
672 *speed = HCLGE_MAC_SPEED_25G;
673 break;
674 case 3:
675 *speed = HCLGE_MAC_SPEED_40G;
676 break;
677 case 4:
678 *speed = HCLGE_MAC_SPEED_50G;
679 break;
680 case 5:
681 *speed = HCLGE_MAC_SPEED_100G;
682 break;
683 default:
684 return -EINVAL;
685 }
686
687 return 0;
688}
689
d92ceae9
FL		 690static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
691 u8 speed_ability)
692{
693 unsigned long *supported = hdev->hw.mac.supported;
694
695 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
696 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
697 supported);
698
699 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
700 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
701 supported);
702
703 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
704 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
705 supported);
706
707 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
708 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
709 supported);
710
711 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
712 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
713 supported);
714
715 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
716 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
717}
718
719static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
720{
721 u8 media_type = hdev->hw.mac.media_type;
722
723 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
724 return;
725
726 hclge_parse_fiber_link_mode(hdev, speed_ability);
727}
728
46a3df9f
S		 729static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
730{
d44f9b63 731 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 732 u64 mac_addr_tmp_high;
733 u64 mac_addr_tmp;
734 int i;
735
d44f9b63 736 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 737
738 /* get the configuration */
ccc23ef3
PL		 739 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
740 HCLGE_CFG_VMDQ_M,
741 HCLGE_CFG_VMDQ_S);
742 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
743 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
744 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
745 HCLGE_CFG_TQP_DESC_N_M,
746 HCLGE_CFG_TQP_DESC_N_S);
747
748 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
749 HCLGE_CFG_PHY_ADDR_M,
750 HCLGE_CFG_PHY_ADDR_S);
751 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
752 HCLGE_CFG_MEDIA_TP_M,
753 HCLGE_CFG_MEDIA_TP_S);
754 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
755 HCLGE_CFG_RX_BUF_LEN_M,
756 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 757 /* get mac_address */
758 mac_addr_tmp = __le32_to_cpu(req->param[2]);
ccc23ef3
PL		 759 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
760 HCLGE_CFG_MAC_ADDR_H_M,
761 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 762
763 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
764
ccc23ef3
PL		 765 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
766 HCLGE_CFG_DEFAULT_SPEED_M,
767 HCLGE_CFG_DEFAULT_SPEED_S);
768 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
769 HCLGE_CFG_RSS_SIZE_M,
770 HCLGE_CFG_RSS_SIZE_S);
c408e202 771
46a3df9f
S		 772 for (i = 0; i < ETH_ALEN; i++)
773 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
774
d44f9b63 775 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 776 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
d92ceae9 777
ccc23ef3
PL		 778 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
779 HCLGE_CFG_SPEED_ABILITY_M,
780 HCLGE_CFG_SPEED_ABILITY_S);
2da5ec58
JS		 781 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
782 HCLGE_CFG_UMV_TBL_SPACE_M,
783 HCLGE_CFG_UMV_TBL_SPACE_S);
784 if (!cfg->umv_space)
785 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
46a3df9f
S		 786}
787
788/* hclge_get_cfg: query the static parameter from flash
789 * @hdev: pointer to struct hclge_dev
790 * @hcfg: the config structure to be getted
791 */
792static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
793{
794 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 795 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 796 int i, ret;
797
798 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 799 u32 offset = 0;
800
d44f9b63 801 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 802 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
803 true);
ccc23ef3
PL		 804 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
805 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 806 /* Len should be united by 4 bytes when send to hardware */
ccc23ef3
PL		 807 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
808 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 809 req->offset = cpu_to_le32(offset);
46a3df9f
S		 810 }
811
812 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
813 if (ret) {
90415e85 814 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
46a3df9f
S		 815 return ret;
816 }
817
818 hclge_parse_cfg(hcfg, desc);
90415e85 819
46a3df9f
S		 820 return 0;
821}
822
823static int hclge_get_cap(struct hclge_dev *hdev)
824{
825 int ret;
826
827 ret = hclge_query_function_status(hdev);
828 if (ret) {
829 dev_err(&hdev->pdev->dev,
830 "query function status error %d.\n", ret);
831 return ret;
832 }
833
834 /* get pf resource */
835 ret = hclge_query_pf_resource(hdev);
90415e85
JS		 836 if (ret)
837 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
46a3df9f 838
90415e85 839 return ret;
46a3df9f
S		 840}
841
842static int hclge_configure(struct hclge_dev *hdev)
843{
844 struct hclge_cfg cfg;
845 int ret, i;
846
847 ret = hclge_get_cfg(hdev, &cfg);
848 if (ret) {
849 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
850 return ret;
851 }
852
853 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
854 hdev->base_tqp_pid = 0;
c408e202 855 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 856 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 857 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 858 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 859 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 860 hdev->num_desc = cfg.tqp_desc_num;
861 hdev->tm_info.num_pg = 1;
cacde272 862 hdev->tc_max = cfg.tc_num;
46a3df9f 863 hdev->tm_info.hw_pfc_map = 0;
2da5ec58 864 hdev->wanted_umv_size = cfg.umv_space;
46a3df9f
S		 865
866 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
867 if (ret) {
868 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
869 return ret;
870 }
871
d92ceae9
FL		 872 hclge_parse_link_mode(hdev, cfg.speed_ability);
873
cacde272
YL		 874 if ((hdev->tc_max > HNAE3_MAX_TC) ||
875 (hdev->tc_max < 1)) {
46a3df9f 876 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 877 hdev->tc_max);
878 hdev->tc_max = 1;
46a3df9f
S		 879 }
880
cacde272
YL		 881 /* Dev does not support DCB */
882 if (!hnae3_dev_dcb_supported(hdev)) {
883 hdev->tc_max = 1;
884 hdev->pfc_max = 0;
885 } else {
886 hdev->pfc_max = hdev->tc_max;
887 }
888
889 hdev->tm_info.num_tc = hdev->tc_max;
890
46a3df9f 891 /* Currently not support uncontiuous tc */
cacde272 892 for (i = 0; i < hdev->tm_info.num_tc; i++)
ccc23ef3 893 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 894
f8362fe1 895 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 896
897 return ret;
898}
899
900static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
901 int tso_mss_max)
902{
d44f9b63 903 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 904 struct hclge_desc desc;
a90bb9a5 905 u16 tso_mss;
46a3df9f
S		 906
907 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
908
d44f9b63 909 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 910
911 tso_mss = 0;
ccc23ef3
PL		 912 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
913 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 914 req->tso_mss_min = cpu_to_le16(tso_mss);
915
916 tso_mss = 0;
ccc23ef3
PL		 917 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
918 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 919 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 920
921 return hclge_cmd_send(&hdev->hw, &desc, 1);
922}
923
924static int hclge_alloc_tqps(struct hclge_dev *hdev)
925{
926 struct hclge_tqp *tqp;
927 int i;
928
929 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
930 sizeof(struct hclge_tqp), GFP_KERNEL);
931 if (!hdev->htqp)
932 return -ENOMEM;
933
934 tqp = hdev->htqp;
935
936 for (i = 0; i < hdev->num_tqps; i++) {
937 tqp->dev = &hdev->pdev->dev;
938 tqp->index = i;
939
940 tqp->q.ae_algo = &ae_algo;
941 tqp->q.buf_size = hdev->rx_buf_len;
942 tqp->q.desc_num = hdev->num_desc;
943 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
944 i * HCLGE_TQP_REG_SIZE;
945
946 tqp++;
947 }
948
949 return 0;
950}
951
952static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
953 u16 tqp_pid, u16 tqp_vid, bool is_pf)
954{
d44f9b63 955 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 956 struct hclge_desc desc;
957 int ret;
958
959 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
960
d44f9b63 961 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 962 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 963 req->tqp_vf = func_id;
46a3df9f
S		 964 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
965 1 << HCLGE_TQP_MAP_EN_B;
966 req->tqp_vid = cpu_to_le16(tqp_vid);
967
968 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85
JS		 969 if (ret)
970 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
46a3df9f 971
90415e85 972 return ret;
46a3df9f
S		 973}
974
81356b1f 975static int hclge_assign_tqp(struct hclge_vport *vport)
46a3df9f 976{
81356b1f 977 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
46a3df9f 978 struct hclge_dev *hdev = vport->back;
7df7dad6 979 int i, alloced;
46a3df9f
S		 980
981 for (i = 0, alloced = 0; i < hdev->num_tqps &&
81356b1f 982 alloced < kinfo->num_tqps; i++) {
46a3df9f
S		 983 if (!hdev->htqp[i].alloced) {
984 hdev->htqp[i].q.handle = &vport->nic;
985 hdev->htqp[i].q.tqp_index = alloced;
81356b1f
YL		 986 hdev->htqp[i].q.desc_num = kinfo->num_desc;
987 kinfo->tqp[alloced] = &hdev->htqp[i].q;
46a3df9f 988 hdev->htqp[i].alloced = true;
46a3df9f
S		 989 alloced++;
990 }
991 }
81356b1f 992 vport->alloc_tqps = kinfo->num_tqps;
46a3df9f
S		 993
994 return 0;
995}
996
81356b1f
YL		 997static int hclge_knic_setup(struct hclge_vport *vport,
998 u16 num_tqps, u16 num_desc)
46a3df9f
S		 999{
1000 struct hnae3_handle *nic = &vport->nic;
1001 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1002 struct hclge_dev *hdev = vport->back;
1003 int i, ret;
1004
81356b1f 1005 kinfo->num_desc = num_desc;
46a3df9f
S		 1006 kinfo->rx_buf_len = hdev->rx_buf_len;
1007 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1008 kinfo->rss_size
1009 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1010 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1011
1012 for (i = 0; i < HNAE3_MAX_TC; i++) {
1013 if (hdev->hw_tc_map & BIT(i)) {
1014 kinfo->tc_info[i].enable = true;
1015 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1016 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1017 kinfo->tc_info[i].tc = i;
1018 } else {
1019 /* Set to default queue if TC is disable */
1020 kinfo->tc_info[i].enable = false;
1021 kinfo->tc_info[i].tqp_offset = 0;
1022 kinfo->tc_info[i].tqp_count = 1;
1023 kinfo->tc_info[i].tc = 0;
1024 }
1025 }
1026
1027 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1028 sizeof(struct hnae3_queue *), GFP_KERNEL);
1029 if (!kinfo->tqp)
1030 return -ENOMEM;
1031
81356b1f 1032 ret = hclge_assign_tqp(vport);
90415e85 1033 if (ret)
46a3df9f 1034 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
46a3df9f 1035
90415e85 1036 return ret;
46a3df9f
S		 1037}
1038
7df7dad6
L		 1039static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1040 struct hclge_vport *vport)
1041{
1042 struct hnae3_handle *nic = &vport->nic;
1043 struct hnae3_knic_private_info *kinfo;
1044 u16 i;
1045
1046 kinfo = &nic->kinfo;
1047 for (i = 0; i < kinfo->num_tqps; i++) {
1048 struct hclge_tqp *q =
1049 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1050 bool is_pf;
1051 int ret;
1052
1053 is_pf = !(vport->vport_id);
1054 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1055 i, is_pf);
1056 if (ret)
1057 return ret;
1058 }
1059
1060 return 0;
1061}
1062
1063static int hclge_map_tqp(struct hclge_dev *hdev)
1064{
1065 struct hclge_vport *vport = hdev->vport;
1066 u16 i, num_vport;
1067
1068 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1069 for (i = 0; i < num_vport; i++) {
1070 int ret;
1071
1072 ret = hclge_map_tqp_to_vport(hdev, vport);
1073 if (ret)
1074 return ret;
1075
1076 vport++;
1077 }
1078
1079 return 0;
1080}
1081
46a3df9f
S		 1082static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1083{
1084 /* this would be initialized later */
1085}
1086
1087static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1088{
1089 struct hnae3_handle *nic = &vport->nic;
1090 struct hclge_dev *hdev = vport->back;
1091 int ret;
1092
1093 nic->pdev = hdev->pdev;
1094 nic->ae_algo = &ae_algo;
1095 nic->numa_node_mask = hdev->numa_node_mask;
1096
1097 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
81356b1f 1098 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
46a3df9f
S		 1099 if (ret) {
1100 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1101 ret);
1102 return ret;
1103 }
1104 } else {
1105 hclge_unic_setup(vport, num_tqps);
1106 }
1107
1108 return 0;
1109}
1110
1111static int hclge_alloc_vport(struct hclge_dev *hdev)
1112{
1113 struct pci_dev *pdev = hdev->pdev;
1114 struct hclge_vport *vport;
1115 u32 tqp_main_vport;
1116 u32 tqp_per_vport;
1117 int num_vport, i;
1118 int ret;
1119
1120 /* We need to alloc a vport for main NIC of PF */
1121 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1122
b76edfb2
HT		 1123 if (hdev->num_tqps < num_vport) {
1124 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1125 hdev->num_tqps, num_vport);
1126 return -EINVAL;
1127 }
46a3df9f
S		 1128
1129 /* Alloc the same number of TQPs for every vport */
1130 tqp_per_vport = hdev->num_tqps / num_vport;
1131 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1132
1133 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1134 GFP_KERNEL);
1135 if (!vport)
1136 return -ENOMEM;
1137
1138 hdev->vport = vport;
1139 hdev->num_alloc_vport = num_vport;
1140
bc59f827
FL		 1141 if (IS_ENABLED(CONFIG_PCI_IOV))
1142 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1143
1144 for (i = 0; i < num_vport; i++) {
1145 vport->back = hdev;
1146 vport->vport_id = i;
1147
1148 if (i == 0)
1149 ret = hclge_vport_setup(vport, tqp_main_vport);
1150 else
1151 ret = hclge_vport_setup(vport, tqp_per_vport);
1152 if (ret) {
1153 dev_err(&pdev->dev,
1154 "vport setup failed for vport %d, %d\n",
1155 i, ret);
1156 return ret;
1157 }
1158
1159 vport++;
1160 }
1161
1162 return 0;
1163}
1164
acf61ecd
YL		 1165static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1166 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1167{
1168/* TX buffer size is unit by 128 byte */
1169#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1170#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1171 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1172 struct hclge_desc desc;
1173 int ret;
1174 u8 i;
1175
d44f9b63 1176 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1177
1178 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1179 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1180 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1181
46a3df9f
S		 1182 req->tx_pkt_buff[i] =
1183 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1184 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1185 }
46a3df9f
S		 1186
1187 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 1188 if (ret)
46a3df9f
S		 1189 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1190 ret);
46a3df9f 1191
90415e85 1192 return ret;
46a3df9f
S		 1193}
1194
acf61ecd
YL		 1195static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1196 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1197{
acf61ecd 1198 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1199
90415e85
JS		 1200 if (ret)
1201 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
46a3df9f 1202
90415e85 1203 return ret;
46a3df9f
S		 1204}
1205
1206static int hclge_get_tc_num(struct hclge_dev *hdev)
1207{
1208 int i, cnt = 0;
1209
1210 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1211 if (hdev->hw_tc_map & BIT(i))
1212 cnt++;
1213 return cnt;
1214}
1215
1216static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1217{
1218 int i, cnt = 0;
1219
1220 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1221 if (hdev->hw_tc_map & BIT(i) &&
1222 hdev->tm_info.hw_pfc_map & BIT(i))
1223 cnt++;
1224 return cnt;
1225}
1226
1227/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1228static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1229 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1230{
1231 struct hclge_priv_buf *priv;
1232 int i, cnt = 0;
1233
1234 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1235 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1236 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1237 priv->enable)
1238 cnt++;
1239 }
1240
1241 return cnt;
1242}
1243
1244/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1245static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1246 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1247{
1248 struct hclge_priv_buf *priv;
1249 int i, cnt = 0;
1250
1251 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1252 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1253 if (hdev->hw_tc_map & BIT(i) &&
1254 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1255 priv->enable)
1256 cnt++;
1257 }
1258
1259 return cnt;
1260}
1261
acf61ecd 1262static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1263{
1264 struct hclge_priv_buf *priv;
1265 u32 rx_priv = 0;
1266 int i;
1267
1268 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1269 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1270 if (priv->enable)
1271 rx_priv += priv->buf_size;
1272 }
1273 return rx_priv;
1274}
1275
acf61ecd 1276static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1277{
1278 u32 i, total_tx_size = 0;
1279
1280 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1281 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1282
1283 return total_tx_size;
1284}
1285
acf61ecd
YL		 1286static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1287 struct hclge_pkt_buf_alloc *buf_alloc,
1288 u32 rx_all)
46a3df9f
S		 1289{
1290 u32 shared_buf_min, shared_buf_tc, shared_std;
1291 int tc_num, pfc_enable_num;
1292 u32 shared_buf;
1293 u32 rx_priv;
1294 int i;
1295
1296 tc_num = hclge_get_tc_num(hdev);
1297 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1298
d221df4e
YL		 1299 if (hnae3_dev_dcb_supported(hdev))
1300 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1301 else
1302 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1303
46a3df9f
S		 1304 shared_buf_tc = pfc_enable_num * hdev->mps +
1305 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1306 hdev->mps;
1307 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1308
acf61ecd 1309 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1310 if (rx_all <= rx_priv + shared_std)
1311 return false;
1312
1313 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1314 buf_alloc->s_buf.buf_size = shared_buf;
1315 buf_alloc->s_buf.self.high = shared_buf;
1316 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1317
1318 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1319 if ((hdev->hw_tc_map & BIT(i)) &&
1320 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1321 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1322 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1323 } else {
acf61ecd
YL		 1324 buf_alloc->s_buf.tc_thrd[i].low = 0;
1325 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1326 }
1327 }
1328
1329 return true;
1330}
1331
acf61ecd
YL		 1332static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1333 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1334{
1335 u32 i, total_size;
1336
1337 total_size = hdev->pkt_buf_size;
1338
1339 /* alloc tx buffer for all enabled tc */
1340 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1341 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1342
1343 if (total_size < HCLGE_DEFAULT_TX_BUF)
1344 return -ENOMEM;
1345
1346 if (hdev->hw_tc_map & BIT(i))
1347 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1348 else
1349 priv->tx_buf_size = 0;
1350
1351 total_size -= priv->tx_buf_size;
1352 }
1353
1354 return 0;
1355}
1356
46a3df9f
S		 1357/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1358 * @hdev: pointer to struct hclge_dev
acf61ecd 1359 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1360 * @return: 0: calculate sucessful, negative: fail
1361 */
1db9b1bf
YL		 1362static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1363 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1364{
d748274d
YL		 1365#define HCLGE_BUF_SIZE_UNIT 128
1366 u32 rx_all = hdev->pkt_buf_size, aligned_mps;
46a3df9f
S		 1367 int no_pfc_priv_num, pfc_priv_num;
1368 struct hclge_priv_buf *priv;
1369 int i;
1370
d748274d 1371 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
acf61ecd 1372 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1373
d602a525
YL		 1374 /* When DCB is not supported, rx private
1375 * buffer is not allocated.
1376 */
1377 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1378 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1379 return -ENOMEM;
1380
1381 return 0;
1382 }
1383
46a3df9f
S		 1384 /* step 1, try to alloc private buffer for all enabled tc */
1385 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1386 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1387 if (hdev->hw_tc_map & BIT(i)) {
1388 priv->enable = 1;
1389 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
d748274d
YL		 1390 priv->wl.low = aligned_mps;
1391 priv->wl.high = priv->wl.low + aligned_mps;
46a3df9f
S		 1392 priv->buf_size = priv->wl.high +
1393 HCLGE_DEFAULT_DV;
1394 } else {
1395 priv->wl.low = 0;
d748274d 1396 priv->wl.high = 2 * aligned_mps;
46a3df9f
S		 1397 priv->buf_size = priv->wl.high;
1398 }
bb1fe9ea
YL		 1399 } else {
1400 priv->enable = 0;
1401 priv->wl.low = 0;
1402 priv->wl.high = 0;
1403 priv->buf_size = 0;
46a3df9f
S		 1404 }
1405 }
1406
acf61ecd 1407 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1408 return 0;
1409
1410 /* step 2, try to decrease the buffer size of
1411 * no pfc TC's private buffer
1412 */
1413 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1414 priv = &buf_alloc->priv_buf[i];
46a3df9f 1415
bb1fe9ea
YL		 1416 priv->enable = 0;
1417 priv->wl.low = 0;
1418 priv->wl.high = 0;
1419 priv->buf_size = 0;
1420
1421 if (!(hdev->hw_tc_map & BIT(i)))
1422 continue;
1423
1424 priv->enable = 1;
46a3df9f
S		 1425
1426 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1427 priv->wl.low = 128;
d748274d 1428 priv->wl.high = priv->wl.low + aligned_mps;
46a3df9f
S		 1429 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1430 } else {
1431 priv->wl.low = 0;
d748274d 1432 priv->wl.high = aligned_mps;
46a3df9f
S		 1433 priv->buf_size = priv->wl.high;
1434 }
1435 }
1436
acf61ecd 1437 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1438 return 0;
1439
1440 /* step 3, try to reduce the number of pfc disabled TCs,
1441 * which have private buffer
1442 */
1443 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1444 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1445
1446 /* let the last to be cleared first */
1447 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1448 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1449
1450 if (hdev->hw_tc_map & BIT(i) &&
1451 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1452 /* Clear the no pfc TC private buffer */
1453 priv->wl.low = 0;
1454 priv->wl.high = 0;
1455 priv->buf_size = 0;
1456 priv->enable = 0;
1457 no_pfc_priv_num--;
1458 }
1459
acf61ecd 1460 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1461 no_pfc_priv_num == 0)
1462 break;
1463 }
1464
acf61ecd 1465 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1466 return 0;
1467
1468 /* step 4, try to reduce the number of pfc enabled TCs
1469 * which have private buffer.
1470 */
acf61ecd 1471 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1472
1473 /* let the last to be cleared first */
1474 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1475 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1476
1477 if (hdev->hw_tc_map & BIT(i) &&
1478 hdev->tm_info.hw_pfc_map & BIT(i)) {
1479 /* Reduce the number of pfc TC with private buffer */
1480 priv->wl.low = 0;
1481 priv->enable = 0;
1482 priv->wl.high = 0;
1483 priv->buf_size = 0;
1484 pfc_priv_num--;
1485 }
1486
acf61ecd 1487 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1488 pfc_priv_num == 0)
1489 break;
1490 }
acf61ecd 1491 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1492 return 0;
1493
1494 return -ENOMEM;
1495}
1496
acf61ecd
YL		 1497static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1498 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1499{
d44f9b63 1500 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1501 struct hclge_desc desc;
1502 int ret;
1503 int i;
1504
1505 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1506 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1507
1508 /* Alloc private buffer TCs */
1509 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1510 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1511
1512 req->buf_num[i] =
1513 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1514 req->buf_num[i] |=
5bca3b94 1515 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1516 }
1517
b8c8bf47 1518 req->shared_buf =
acf61ecd 1519 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1520 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1521
46a3df9f 1522 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 1523 if (ret)
46a3df9f
S		 1524 dev_err(&hdev->pdev->dev,
1525 "rx private buffer alloc cmd failed %d\n", ret);
46a3df9f 1526
90415e85 1527 return ret;
46a3df9f
S		 1528}
1529
acf61ecd
YL		 1530static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1531 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1532{
1533 struct hclge_rx_priv_wl_buf *req;
1534 struct hclge_priv_buf *priv;
1535 struct hclge_desc desc[2];
1536 int i, j;
1537 int ret;
1538
1539 for (i = 0; i < 2; i++) {
1540 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1541 false);
1542 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1543
1544 /* The first descriptor set the NEXT bit to 1 */
1545 if (i == 0)
1546 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1547 else
1548 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1549
1550 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1551 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1552
1553 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1554 req->tc_wl[j].high =
1555 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1556 req->tc_wl[j].high |=
ee6b549b 1557 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1558 req->tc_wl[j].low =
1559 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1560 req->tc_wl[j].low |=
ee6b549b 1561 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1562 }
1563 }
1564
1565 /* Send 2 descriptor at one time */
1566 ret = hclge_cmd_send(&hdev->hw, desc, 2);
90415e85 1567 if (ret)
46a3df9f
S		 1568 dev_err(&hdev->pdev->dev,
1569 "rx private waterline config cmd failed %d\n",
1570 ret);
90415e85 1571 return ret;
46a3df9f
S		 1572}
1573
acf61ecd
YL		 1574static int hclge_common_thrd_config(struct hclge_dev *hdev,
1575 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1576{
acf61ecd 1577 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1578 struct hclge_rx_com_thrd *req;
1579 struct hclge_desc desc[2];
1580 struct hclge_tc_thrd *tc;
1581 int i, j;
1582 int ret;
1583
1584 for (i = 0; i < 2; i++) {
1585 hclge_cmd_setup_basic_desc(&desc[i],
1586 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1587 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1588
1589 /* The first descriptor set the NEXT bit to 1 */
1590 if (i == 0)
1591 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1592 else
1593 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1594
1595 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1596 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1597
1598 req->com_thrd[j].high =
1599 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1600 req->com_thrd[j].high |=
ee6b549b 1601 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1602 req->com_thrd[j].low =
1603 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1604 req->com_thrd[j].low |=
ee6b549b 1605 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1606 }
1607 }
1608
1609 /* Send 2 descriptors at one time */
1610 ret = hclge_cmd_send(&hdev->hw, desc, 2);
90415e85 1611 if (ret)
46a3df9f
S		 1612 dev_err(&hdev->pdev->dev,
1613 "common threshold config cmd failed %d\n", ret);
90415e85 1614 return ret;
46a3df9f
S		 1615}
1616
acf61ecd
YL		 1617static int hclge_common_wl_config(struct hclge_dev *hdev,
1618 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1619{
acf61ecd 1620 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1621 struct hclge_rx_com_wl *req;
1622 struct hclge_desc desc;
1623 int ret;
1624
1625 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1626
1627 req = (struct hclge_rx_com_wl *)desc.data;
1628 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
ee6b549b 1629 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1630
1631 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
ee6b549b 1632 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1633
1634 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 1635 if (ret)
46a3df9f
S		 1636 dev_err(&hdev->pdev->dev,
1637 "common waterline config cmd failed %d\n", ret);
930ff2f6 1638
90415e85 1639 return ret;
46a3df9f
S		 1640}
1641
1642int hclge_buffer_alloc(struct hclge_dev *hdev)
1643{
acf61ecd 1644 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1645 int ret;
1646
acf61ecd
YL		 1647 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1648 if (!pkt_buf)
46a3df9f
S		 1649 return -ENOMEM;
1650
acf61ecd 1651 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1652 if (ret) {
1653 dev_err(&hdev->pdev->dev,
1654 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1655 goto out;
9ffe79a9
YL		 1656 }
1657
acf61ecd 1658 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1659 if (ret) {
1660 dev_err(&hdev->pdev->dev,
1661 "could not alloc tx buffers %d\n", ret);
acf61ecd 1662 goto out;
46a3df9f
S		 1663 }
1664
acf61ecd 1665 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1666 if (ret) {
1667 dev_err(&hdev->pdev->dev,
1668 "could not calc rx priv buffer size for all TCs %d\n",
1669 ret);
acf61ecd 1670 goto out;
46a3df9f
S		 1671 }
1672
acf61ecd 1673 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1674 if (ret) {
1675 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1676 ret);
acf61ecd 1677 goto out;
46a3df9f
S		 1678 }
1679
2daf4a65 1680 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1681 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1682 if (ret) {
1683 dev_err(&hdev->pdev->dev,
1684 "could not configure rx private waterline %d\n",
1685 ret);
acf61ecd 1686 goto out;
2daf4a65 1687 }
46a3df9f 1688
acf61ecd 1689 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1690 if (ret) {
1691 dev_err(&hdev->pdev->dev,
1692 "could not configure common threshold %d\n",
1693 ret);
acf61ecd 1694 goto out;
2daf4a65 1695 }
46a3df9f
S		 1696 }
1697
acf61ecd
YL		 1698 ret = hclge_common_wl_config(hdev, pkt_buf);
1699 if (ret)
46a3df9f
S		 1700 dev_err(&hdev->pdev->dev,
1701 "could not configure common waterline %d\n", ret);
46a3df9f 1702
acf61ecd
YL		 1703out:
1704 kfree(pkt_buf);
1705 return ret;
46a3df9f
S		 1706}
1707
1708static int hclge_init_roce_base_info(struct hclge_vport *vport)
1709{
1710 struct hnae3_handle *roce = &vport->roce;
1711 struct hnae3_handle *nic = &vport->nic;
1712
887c3820 1713 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1714
1715 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1716 vport->back->num_msi_left == 0)
1717 return -EINVAL;
1718
1719 roce->rinfo.base_vector = vport->back->roce_base_vector;
1720
1721 roce->rinfo.netdev = nic->kinfo.netdev;
1722 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1723
1724 roce->pdev = nic->pdev;
1725 roce->ae_algo = nic->ae_algo;
1726 roce->numa_node_mask = nic->numa_node_mask;
1727
1728 return 0;
1729}
1730
887c3820 1731static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1732{
1733 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1734 int vectors;
1735 int i;
46a3df9f 1736
887c3820
SM		 1737 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1738 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1739 if (vectors < 0) {
1740 dev_err(&pdev->dev,
1741 "failed(%d) to allocate MSI/MSI-X vectors\n",
1742 vectors);
1743 return vectors;
46a3df9f 1744 }
887c3820
SM		 1745 if (vectors < hdev->num_msi)
1746 dev_warn(&hdev->pdev->dev,
1747 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1748 hdev->num_msi, vectors);
46a3df9f 1749
887c3820
SM		 1750 hdev->num_msi = vectors;
1751 hdev->num_msi_left = vectors;
1752 hdev->base_msi_vector = pdev->irq;
46a3df9f 1753 hdev->roce_base_vector = hdev->base_msi_vector +
5355e6d3 1754 hdev->roce_base_msix_offset;
46a3df9f 1755
46a3df9f
S		 1756 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1757 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1758 if (!hdev->vector_status) {
1759 pci_free_irq_vectors(pdev);
46a3df9f 1760 return -ENOMEM;
887c3820 1761 }
46a3df9f
S		 1762
1763 for (i = 0; i < hdev->num_msi; i++)
1764 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1765
887c3820
SM		 1766 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1767 sizeof(int), GFP_KERNEL);
1768 if (!hdev->vector_irq) {
1769 pci_free_irq_vectors(pdev);
1770 return -ENOMEM;
46a3df9f 1771 }
46a3df9f
S		 1772
1773 return 0;
1774}
1775
1c780066 1776static u8 hclge_check_speed_dup(u8 duplex, int speed)
46a3df9f 1777{
46a3df9f 1778
1c780066
YL		 1779 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1780 duplex = HCLGE_MAC_FULL;
46a3df9f 1781
1c780066 1782 return duplex;
46a3df9f
S		 1783}
1784
1c780066
YL		 1785static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1786 u8 duplex)
46a3df9f 1787{
d44f9b63 1788 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 1789 struct hclge_desc desc;
1790 int ret;
1791
d44f9b63 1792 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 1793
1794 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1795
ccc23ef3 1796 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 1797
1798 switch (speed) {
1799 case HCLGE_MAC_SPEED_10M:
ccc23ef3
PL		 1800 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1801 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 1802 break;
1803 case HCLGE_MAC_SPEED_100M:
ccc23ef3
PL		 1804 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1805 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 1806 break;
1807 case HCLGE_MAC_SPEED_1G:
ccc23ef3
PL		 1808 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1809 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 1810 break;
1811 case HCLGE_MAC_SPEED_10G:
ccc23ef3
PL		 1812 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1813 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 1814 break;
1815 case HCLGE_MAC_SPEED_25G:
ccc23ef3
PL		 1816 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1817 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 1818 break;
1819 case HCLGE_MAC_SPEED_40G:
ccc23ef3
PL		 1820 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1821 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 1822 break;
1823 case HCLGE_MAC_SPEED_50G:
ccc23ef3
PL		 1824 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1825 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 1826 break;
1827 case HCLGE_MAC_SPEED_100G:
ccc23ef3
PL		 1828 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1829 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 1830 break;
1831 default:
d7629e74 1832 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 1833 return -EINVAL;
1834 }
1835
ccc23ef3
PL		 1836 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1837 1);
46a3df9f
S		 1838
1839 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1840 if (ret) {
1841 dev_err(&hdev->pdev->dev,
1842 "mac speed/duplex config cmd failed %d.\n", ret);
1843 return ret;
1844 }
1845
1c780066
YL		 1846 return 0;
1847}
1848
1849int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1850{
1851 int ret;
1852
1853 duplex = hclge_check_speed_dup(duplex, speed);
1854 if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1855 return 0;
1856
1857 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1858 if (ret)
1859 return ret;
1860
1861 hdev->hw.mac.speed = speed;
1862 hdev->hw.mac.duplex = duplex;
46a3df9f
S		 1863
1864 return 0;
1865}
1866
1867static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1868 u8 duplex)
1869{
1870 struct hclge_vport *vport = hclge_get_vport(handle);
1871 struct hclge_dev *hdev = vport->back;
1872
1873 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1874}
1875
1876static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1877 u8 *duplex)
1878{
d44f9b63 1879 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 1880 struct hclge_desc desc;
1881 int speed_tmp;
1882 int ret;
1883
d44f9b63 1884 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 1885
1886 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1887 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1888 if (ret) {
1889 dev_err(&hdev->pdev->dev,
1890 "mac speed/autoneg/duplex query cmd failed %d\n",
1891 ret);
1892 return ret;
1893 }
1894
ccc23ef3
PL		 1895 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
1896 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
1897 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 1898
1899 ret = hclge_parse_speed(speed_tmp, speed);
90415e85 1900 if (ret)
46a3df9f
S		 1901 dev_err(&hdev->pdev->dev,
1902 "could not parse speed(=%d), %d\n", speed_tmp, ret);
46a3df9f 1903
90415e85 1904 return ret;
46a3df9f
S		 1905}
1906
46a3df9f
S		 1907static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1908{
d44f9b63 1909 struct hclge_config_auto_neg_cmd *req;
46a3df9f 1910 struct hclge_desc desc;
a90bb9a5 1911 u32 flag = 0;
46a3df9f
S		 1912 int ret;
1913
1914 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1915
d44f9b63 1916 req = (struct hclge_config_auto_neg_cmd *)desc.data;
ccc23ef3 1917 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 1918 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 1919
1920 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 1921 if (ret)
46a3df9f
S		 1922 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
1923 ret);
46a3df9f 1924
90415e85 1925 return ret;
46a3df9f
S		 1926}
1927
1928static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
1929{
1930 struct hclge_vport *vport = hclge_get_vport(handle);
1931 struct hclge_dev *hdev = vport->back;
1932
1933 return hclge_set_autoneg_en(hdev, enable);
1934}
1935
1936static int hclge_get_autoneg(struct hnae3_handle *handle)
1937{
1938 struct hclge_vport *vport = hclge_get_vport(handle);
1939 struct hclge_dev *hdev = vport->back;
9ff804ee
FL		 1940 struct phy_device *phydev = hdev->hw.mac.phydev;
1941
1942 if (phydev)
1943 return phydev->autoneg;
46a3df9f
S		 1944
1945 return hdev->hw.mac.autoneg;
1946}
1947
1948static int hclge_mac_init(struct hclge_dev *hdev)
1949{
59bc85ec
FL		 1950 struct hnae3_handle *handle = &hdev->vport[0].nic;
1951 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 1952 struct hclge_mac *mac = &hdev->hw.mac;
59bc85ec 1953 int mtu;
46a3df9f
S		 1954 int ret;
1955
1c780066
YL		 1956 hdev->hw.mac.duplex = HCLGE_MAC_FULL;
1957 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
1958 hdev->hw.mac.duplex);
46a3df9f
S		 1959 if (ret) {
1960 dev_err(&hdev->pdev->dev,
1961 "Config mac speed dup fail ret=%d\n", ret);
1962 return ret;
1963 }
1964
1965 mac->link = 0;
1966
59bc85ec
FL		 1967 if (netdev)
1968 mtu = netdev->mtu;
1969 else
1970 mtu = ETH_DATA_LEN;
1971
1972 ret = hclge_set_mtu(handle, mtu);
90415e85 1973 if (ret)
59bc85ec
FL		 1974 dev_err(&hdev->pdev->dev,
1975 "set mtu failed ret=%d\n", ret);
59bc85ec 1976
90415e85 1977 return ret;
46a3df9f
S		 1978}
1979
22fd3468
SM		 1980static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
1981{
1982 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
1983 schedule_work(&hdev->mbx_service_task);
1984}
1985
ed4a1bb8
SM		 1986static void hclge_reset_task_schedule(struct hclge_dev *hdev)
1987{
1988 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
1989 schedule_work(&hdev->rst_service_task);
1990}
1991
46a3df9f
S		 1992static void hclge_task_schedule(struct hclge_dev *hdev)
1993{
1994 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
1995 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
1996 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
1997 (void)schedule_work(&hdev->service_task);
1998}
1999
2000static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2001{
d44f9b63 2002 struct hclge_link_status_cmd *req;
46a3df9f
S		 2003 struct hclge_desc desc;
2004 int link_status;
2005 int ret;
2006
2007 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2008 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2009 if (ret) {
2010 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2011 ret);
2012 return ret;
2013 }
2014
d44f9b63 2015 req = (struct hclge_link_status_cmd *)desc.data;
e23e21ea 2016 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
46a3df9f
S		 2017
2018 return !!link_status;
2019}
2020
2021static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2022{
2023 int mac_state;
2024 int link_stat;
2025
ed6acb33
PL		 2026 if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2027 return 0;
2028
46a3df9f
S		 2029 mac_state = hclge_get_mac_link_status(hdev);
2030
2031 if (hdev->hw.mac.phydev) {
7ce8e698 2032 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
46a3df9f
S		 2033 link_stat = mac_state &
2034 hdev->hw.mac.phydev->link;
2035 else
2036 link_stat = 0;
2037
2038 } else {
2039 link_stat = mac_state;
2040 }
2041
2042 return !!link_stat;
2043}
2044
2045static void hclge_update_link_status(struct hclge_dev *hdev)
2046{
2047 struct hnae3_client *client = hdev->nic_client;
2048 struct hnae3_handle *handle;
2049 int state;
2050 int i;
2051
2052 if (!client)
2053 return;
2054 state = hclge_get_mac_phy_link(hdev);
2055 if (state != hdev->hw.mac.link) {
2056 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2057 handle = &hdev->vport[i].nic;
2058 client->ops->link_status_change(handle, state);
2059 }
2060 hdev->hw.mac.link = state;
2061 }
2062}
2063
2064static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2065{
2066 struct hclge_mac mac = hdev->hw.mac;
2067 u8 duplex;
2068 int speed;
2069 int ret;
2070
2071 /* get the speed and duplex as autoneg'result from mac cmd when phy
2072 * doesn't exit.
2073 */
c040366b 2074 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2075 return 0;
2076
2077 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2078 if (ret) {
2079 dev_err(&hdev->pdev->dev,
2080 "mac autoneg/speed/duplex query failed %d\n", ret);
2081 return ret;
2082 }
2083
1c780066
YL		 2084 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2085 if (ret) {
2086 dev_err(&hdev->pdev->dev,
2087 "mac speed/duplex config failed %d\n", ret);
2088 return ret;
46a3df9f
S		 2089 }
2090
2091 return 0;
2092}
2093
2094static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2095{
2096 struct hclge_vport *vport = hclge_get_vport(handle);
2097 struct hclge_dev *hdev = vport->back;
2098
2099 return hclge_update_speed_duplex(hdev);
2100}
2101
2102static int hclge_get_status(struct hnae3_handle *handle)
2103{
2104 struct hclge_vport *vport = hclge_get_vport(handle);
2105 struct hclge_dev *hdev = vport->back;
2106
2107 hclge_update_link_status(hdev);
2108
2109 return hdev->hw.mac.link;
2110}
2111
d039ef68 2112static void hclge_service_timer(struct timer_list *t)
46a3df9f 2113{
d039ef68 2114 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2115
d039ef68 2116 mod_timer(&hdev->service_timer, jiffies + HZ);
7a5d2a39 2117 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2118 hclge_task_schedule(hdev);
2119}
2120
2121static void hclge_service_complete(struct hclge_dev *hdev)
2122{
2123 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2124
2125 /* Flush memory before next watchdog */
2126 smp_mb__before_atomic();
2127 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2128}
2129
202f2014
SM		 2130static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2131{
2132 u32 rst_src_reg;
22fd3468 2133 u32 cmdq_src_reg;
202f2014
SM		 2134
2135 /* fetch the events from their corresponding regs */
0bcc9ba1 2136 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
22fd3468
SM		 2137 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2138
2139 /* Assumption: If by any chance reset and mailbox events are reported
2140 * together then we will only process reset event in this go and will
2141 * defer the processing of the mailbox events. Since, we would have not
2142 * cleared RX CMDQ event this time we would receive again another
2143 * interrupt from H/W just for the mailbox.
2144 */
202f2014
SM		 2145
2146 /* check for vector0 reset event sources */
2147 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
7edef4ce 2148 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
202f2014
SM		 2149 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2150 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2151 return HCLGE_VECTOR0_EVENT_RST;
2152 }
2153
2154 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
7edef4ce 2155 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
202f2014
SM		 2156 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2157 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2158 return HCLGE_VECTOR0_EVENT_RST;
2159 }
2160
2161 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2162 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2163 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2164 return HCLGE_VECTOR0_EVENT_RST;
2165 }
2166
22fd3468
SM		 2167 /* check for vector0 mailbox(=CMDQ RX) event source */
2168 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2169 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2170 *clearval = cmdq_src_reg;
2171 return HCLGE_VECTOR0_EVENT_MBX;
2172 }
202f2014
SM		 2173
2174 return HCLGE_VECTOR0_EVENT_OTHER;
2175}
2176
2177static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2178 u32 regclr)
2179{
22fd3468
SM		 2180 switch (event_type) {
2181 case HCLGE_VECTOR0_EVENT_RST:
202f2014 2182 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
22fd3468
SM		 2183 break;
2184 case HCLGE_VECTOR0_EVENT_MBX:
2185 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2186 break;
085920ba
JS		 2187 default:
2188 break;
22fd3468 2189 }
202f2014
SM		 2190}
2191
9ab4ad14
XW		 2192static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2193{
2194 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2195 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2196 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2197 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2198 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2199}
2200
466b0c00
L		 2201static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2202{
2203 writel(enable ? 1 : 0, vector->addr);
2204}
2205
2206static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2207{
2208 struct hclge_dev *hdev = data;
202f2014
SM		 2209 u32 event_cause;
2210 u32 clearval;
466b0c00
L		 2211
2212 hclge_enable_vector(&hdev->misc_vector, false);
202f2014
SM		 2213 event_cause = hclge_check_event_cause(hdev, &clearval);
2214
22fd3468 2215 /* vector 0 interrupt is shared with reset and mailbox source events.*/
202f2014
SM		 2216 switch (event_cause) {
2217 case HCLGE_VECTOR0_EVENT_RST:
ed4a1bb8 2218 hclge_reset_task_schedule(hdev);
202f2014 2219 break;
22fd3468
SM		 2220 case HCLGE_VECTOR0_EVENT_MBX:
2221 /* If we are here then,
2222 * 1. Either we are not handling any mbx task and we are not
2223 * scheduled as well
2224 * OR
2225 * 2. We could be handling a mbx task but nothing more is
2226 * scheduled.
2227 * In both cases, we should schedule mbx task as there are more
2228 * mbx messages reported by this interrupt.
2229 */
2230 hclge_mbx_task_schedule(hdev);
40ee4b71 2231 break;
202f2014 2232 default:
40ee4b71
YL		 2233 dev_warn(&hdev->pdev->dev,
2234 "received unknown or unhandled event of vector0\n");
202f2014
SM		 2235 break;
2236 }
2237
e9a50d09 2238 /* clear the source of interrupt if it is not cause by reset */
c9fc48dc 2239 if (event_cause == HCLGE_VECTOR0_EVENT_MBX) {
e9a50d09
YL		 2240 hclge_clear_event_cause(hdev, event_cause, clearval);
2241 hclge_enable_vector(&hdev->misc_vector, true);
2242 }
466b0c00
L		 2243
2244 return IRQ_HANDLED;
2245}
2246
2247static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2248{
1dc5378f
PL		 2249 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2250 dev_warn(&hdev->pdev->dev,
2251 "vector(vector_id %d) has been freed.\n", vector_id);
2252 return;
2253 }
2254
466b0c00
L		 2255 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2256 hdev->num_msi_left += 1;
2257 hdev->num_msi_used -= 1;
2258}
2259
2260static void hclge_get_misc_vector(struct hclge_dev *hdev)
2261{
2262 struct hclge_misc_vector *vector = &hdev->misc_vector;
2263
2264 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2265
2266 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2267 hdev->vector_status[0] = 0;
2268
2269 hdev->num_msi_left -= 1;
2270 hdev->num_msi_used += 1;
2271}
2272
2273static int hclge_misc_irq_init(struct hclge_dev *hdev)
2274{
2275 int ret;
2276
2277 hclge_get_misc_vector(hdev);
2278
202f2014
SM		 2279 /* this would be explicitly freed in the end */
2280 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2281 0, "hclge_misc", hdev);
466b0c00
L		 2282 if (ret) {
2283 hclge_free_vector(hdev, 0);
2284 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2285 hdev->misc_vector.vector_irq);
2286 }
2287
2288 return ret;
2289}
2290
202f2014
SM		 2291static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2292{
2293 free_irq(hdev->misc_vector.vector_irq, hdev);
2294 hclge_free_vector(hdev, 0);
2295}
2296
4ed340ab
L		 2297static int hclge_notify_client(struct hclge_dev *hdev,
2298 enum hnae3_reset_notify_type type)
2299{
2300 struct hnae3_client *client = hdev->nic_client;
2301 u16 i;
2302
2303 if (!client->ops->reset_notify)
2304 return -EOPNOTSUPP;
2305
2306 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
ad7c82fe 2307 struct hnae3_handle *handle = &hdev->vport[i].nic;
2308 int ret;
b38db544 2309
4ed340ab 2310 ret = client->ops->reset_notify(handle, type);
b38db544 2311 if (ret)
4ed340ab
L		 2312 return ret;
2313 }
2314
6060dc84 2315 return 0;
4ed340ab
L		 2316}
2317
2318static int hclge_reset_wait(struct hclge_dev *hdev)
2319{
2320#define HCLGE_RESET_WATI_MS 100
2321#define HCLGE_RESET_WAIT_CNT 5
2322 u32 val, reg, reg_bit;
2323 u32 cnt = 0;
2324
2325 switch (hdev->reset_type) {
2326 case HNAE3_GLOBAL_RESET:
2327 reg = HCLGE_GLOBAL_RESET_REG;
2328 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2329 break;
2330 case HNAE3_CORE_RESET:
2331 reg = HCLGE_GLOBAL_RESET_REG;
2332 reg_bit = HCLGE_CORE_RESET_BIT;
2333 break;
2334 case HNAE3_FUNC_RESET:
2335 reg = HCLGE_FUN_RST_ING;
2336 reg_bit = HCLGE_FUN_RST_ING_B;
2337 break;
2338 default:
2339 dev_err(&hdev->pdev->dev,
2340 "Wait for unsupported reset type: %d\n",
2341 hdev->reset_type);
2342 return -EINVAL;
2343 }
2344
2345 val = hclge_read_dev(&hdev->hw, reg);
ccc23ef3 2346 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
4ed340ab
L		 2347 msleep(HCLGE_RESET_WATI_MS);
2348 val = hclge_read_dev(&hdev->hw, reg);
2349 cnt++;
2350 }
2351
4ed340ab
L		 2352 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2353 dev_warn(&hdev->pdev->dev,
2354 "Wait for reset timeout: %d\n", hdev->reset_type);
2355 return -EBUSY;
2356 }
2357
2358 return 0;
2359}
2360
13a86fae 2361int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2362{
2363 struct hclge_desc desc;
2364 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2365 int ret;
2366
2367 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
ccc23ef3 2368 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2369 req->fun_reset_vfid = func_id;
2370
2371 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2372 if (ret)
2373 dev_err(&hdev->pdev->dev,
2374 "send function reset cmd fail, status =%d\n", ret);
2375
2376 return ret;
2377}
2378
d5752031 2379static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2380{
2381 struct pci_dev *pdev = hdev->pdev;
2382 u32 val;
2383
d5752031 2384 switch (hdev->reset_type) {
4ed340ab
L		 2385 case HNAE3_GLOBAL_RESET:
2386 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
ccc23ef3 2387 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2388 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2389 dev_info(&pdev->dev, "Global Reset requested\n");
2390 break;
2391 case HNAE3_CORE_RESET:
2392 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
ccc23ef3 2393 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2394 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2395 dev_info(&pdev->dev, "Core Reset requested\n");
2396 break;
2397 case HNAE3_FUNC_RESET:
2398 dev_info(&pdev->dev, "PF Reset requested\n");
2399 hclge_func_reset_cmd(hdev, 0);
ed4a1bb8
SM		 2400 /* schedule again to check later */
2401 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2402 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2403 break;
2404 default:
2405 dev_warn(&pdev->dev,
d5752031 2406 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2407 break;
2408 }
2409}
2410
d5752031
SM		 2411static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2412 unsigned long *addr)
2413{
2414 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2415
2416 /* return the highest priority reset level amongst all */
2417 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2418 rst_level = HNAE3_GLOBAL_RESET;
2419 else if (test_bit(HNAE3_CORE_RESET, addr))
2420 rst_level = HNAE3_CORE_RESET;
2421 else if (test_bit(HNAE3_IMP_RESET, addr))
2422 rst_level = HNAE3_IMP_RESET;
2423 else if (test_bit(HNAE3_FUNC_RESET, addr))
2424 rst_level = HNAE3_FUNC_RESET;
2425
2426 /* now, clear all other resets */
2427 clear_bit(HNAE3_GLOBAL_RESET, addr);
2428 clear_bit(HNAE3_CORE_RESET, addr);
2429 clear_bit(HNAE3_IMP_RESET, addr);
2430 clear_bit(HNAE3_FUNC_RESET, addr);
2431
2432 return rst_level;
2433}
2434
e9a50d09
YL		 2435static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2436{
2437 u32 clearval = 0;
2438
2439 switch (hdev->reset_type) {
2440 case HNAE3_IMP_RESET:
2441 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2442 break;
2443 case HNAE3_GLOBAL_RESET:
2444 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2445 break;
2446 case HNAE3_CORE_RESET:
2447 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2448 break;
2449 default:
e9a50d09
YL		 2450 break;
2451 }
2452
2453 if (!clearval)
2454 return;
2455
2456 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2457 hclge_enable_vector(&hdev->misc_vector, true);
2458}
2459
d5752031
SM		 2460static void hclge_reset(struct hclge_dev *hdev)
2461{
7ce98982 2462 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1a45360a
HT		 2463 struct hnae3_handle *handle;
2464
7ce98982
JS		 2465 /* Initialize ae_dev reset status as well, in case enet layer wants to
2466 * know if device is undergoing reset
2467 */
2468 ae_dev->reset_type = hdev->reset_type;
d5752031 2469 /* perform reset of the stack & ae device for a client */
1a45360a 2470 handle = &hdev->vport[0].nic;
47622dc9 2471 rtnl_lock();
d5752031 2472 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
a4d93aee 2473 rtnl_unlock();
d5752031
SM		 2474
2475 if (!hclge_reset_wait(hdev)) {
a4d93aee 2476 rtnl_lock();
d5752031
SM		 2477 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2478 hclge_reset_ae_dev(hdev->ae_dev);
2479 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
e9a50d09
YL		 2480
2481 hclge_clear_reset_cause(hdev);
d5752031 2482 } else {
a4d93aee 2483 rtnl_lock();
d5752031
SM		 2484 /* schedule again to check pending resets later */
2485 set_bit(hdev->reset_type, &hdev->reset_pending);
2486 hclge_reset_task_schedule(hdev);
2487 }
2488
2489 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
1a45360a 2490 handle->last_reset_time = jiffies;
47622dc9 2491 rtnl_unlock();
7ce98982 2492 ae_dev->reset_type = HNAE3_NONE_RESET;
d5752031
SM		 2493}
2494
538d8ba0
SJ		 2495static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
2496{
2497 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2498 struct hclge_dev *hdev = ae_dev->priv;
2499
2500 /* We might end up getting called broadly because of 2 below cases:
2501 * 1. Recoverable error was conveyed through APEI and only way to bring
2502 * normalcy is to reset.
2503 * 2. A new reset request from the stack due to timeout
2504 *
2505 * For the first case,error event might not have ae handle available.
2506 * check if this is a new reset request and we are not here just because
4aef908d
SM		 2507 * last reset attempt did not succeed and watchdog hit us again. We will
2508 * know this if last reset request did not occur very recently (watchdog
2509 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2510 * In case of new request we reset the "reset level" to PF reset.
1a45360a
HT		 2511 * And if it is a repeat reset request of the most recent one then we
2512 * want to make sure we throttle the reset request. Therefore, we will
2513 * not allow it again before 3*HZ times.
4aef908d 2514 */
538d8ba0
SJ		 2515 if (!handle)
2516 handle = &hdev->vport[0].nic;
2517
1a45360a
HT		 2518 if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2519 return;
2c883d73
HT		 2520 else if (hdev->default_reset_request)
2521 handle->reset_level =
2522 hclge_get_reset_level(hdev,
2523 &hdev->default_reset_request);
1a45360a 2524 else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
4aef908d 2525 handle->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2526
4aef908d
SM		 2527 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2528 handle->reset_level);
2529
2530 /* request reset & schedule reset task */
2531 set_bit(handle->reset_level, &hdev->reset_request);
2532 hclge_reset_task_schedule(hdev);
2533
2534 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2535 handle->reset_level++;
4ed340ab
L		 2536}
2537
2c883d73
HT		 2538static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2539 enum hnae3_reset_type rst_type)
2540{
2541 struct hclge_dev *hdev = ae_dev->priv;
2542
2543 set_bit(rst_type, &hdev->default_reset_request);
2544}
2545
4ed340ab
L		 2546static void hclge_reset_subtask(struct hclge_dev *hdev)
2547{
d5752031
SM		 2548 /* check if there is any ongoing reset in the hardware. This status can
2549 * be checked from reset_pending. If there is then, we need to wait for
2550 * hardware to complete reset.
2551 * a. If we are able to figure out in reasonable time that hardware
2552 * has fully resetted then, we can proceed with driver, client
2553 * reset.
2554 * b. else, we can come back later to check this status so re-sched
2555 * now.
2556 */
2557 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2558 if (hdev->reset_type != HNAE3_NONE_RESET)
2559 hclge_reset(hdev);
4ed340ab 2560
d5752031
SM		 2561 /* check if we got any *new* reset requests to be honored */
2562 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2563 if (hdev->reset_type != HNAE3_NONE_RESET)
2564 hclge_do_reset(hdev);
4ed340ab 2565
4ed340ab
L		 2566 hdev->reset_type = HNAE3_NONE_RESET;
2567}
2568
ed4a1bb8 2569static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2570{
ed4a1bb8
SM		 2571 struct hclge_dev *hdev =
2572 container_of(work, struct hclge_dev, rst_service_task);
2573
2574 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2575 return;
2576
2577 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2578
4ed340ab 2579 hclge_reset_subtask(hdev);
ed4a1bb8
SM		 2580
2581 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2582}
2583
22fd3468
SM		 2584static void hclge_mailbox_service_task(struct work_struct *work)
2585{
2586 struct hclge_dev *hdev =
2587 container_of(work, struct hclge_dev, mbx_service_task);
2588
2589 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2590 return;
2591
2592 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2593
2594 hclge_mbx_handler(hdev);
2595
2596 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2597}
2598
46a3df9f
S		 2599static void hclge_service_task(struct work_struct *work)
2600{
2601 struct hclge_dev *hdev =
2602 container_of(work, struct hclge_dev, service_task);
2603
7a5d2a39
JS		 2604 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2605 hclge_update_stats_for_all(hdev);
2606 hdev->hw_stats.stats_timer = 0;
2607 }
2608
46a3df9f
S		 2609 hclge_update_speed_duplex(hdev);
2610 hclge_update_link_status(hdev);
46a3df9f
S		 2611 hclge_service_complete(hdev);
2612}
2613
46a3df9f
S		 2614struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2615{
2616 /* VF handle has no client */
2617 if (!handle->client)
2618 return container_of(handle, struct hclge_vport, nic);
2619 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2620 return container_of(handle, struct hclge_vport, roce);
2621 else
2622 return container_of(handle, struct hclge_vport, nic);
2623}
2624
2625static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2626 struct hnae3_vector_info *vector_info)
2627{
2628 struct hclge_vport *vport = hclge_get_vport(handle);
2629 struct hnae3_vector_info *vector = vector_info;
2630 struct hclge_dev *hdev = vport->back;
2631 int alloc = 0;
2632 int i, j;
2633
2634 vector_num = min(hdev->num_msi_left, vector_num);
2635
2636 for (j = 0; j < vector_num; j++) {
2637 for (i = 1; i < hdev->num_msi; i++) {
2638 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2639 vector->vector = pci_irq_vector(hdev->pdev, i);
2640 vector->io_addr = hdev->hw.io_base +
2641 HCLGE_VECTOR_REG_BASE +
2642 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2643 vport->vport_id *
2644 HCLGE_VECTOR_VF_OFFSET;
2645 hdev->vector_status[i] = vport->vport_id;
887c3820 2646 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2647
2648 vector++;
2649 alloc++;
2650
2651 break;
2652 }
2653 }
2654 }
2655 hdev->num_msi_left -= alloc;
2656 hdev->num_msi_used += alloc;
2657
2658 return alloc;
2659}
2660
2661static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2662{
2663 int i;
2664
887c3820
SM		 2665 for (i = 0; i < hdev->num_msi; i++)
2666 if (vector == hdev->vector_irq[i])
2667 return i;
2668
46a3df9f
S		 2669 return -EINVAL;
2670}
2671
7412200c
YL		 2672static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2673{
2674 struct hclge_vport *vport = hclge_get_vport(handle);
2675 struct hclge_dev *hdev = vport->back;
2676 int vector_id;
2677
2678 vector_id = hclge_get_vector_index(hdev, vector);
2679 if (vector_id < 0) {
2680 dev_err(&hdev->pdev->dev,
2681 "Get vector index fail. vector_id =%d\n", vector_id);
2682 return vector_id;
2683 }
2684
2685 hclge_free_vector(hdev, vector_id);
2686
2687 return 0;
2688}
2689
46a3df9f
S		 2690static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2691{
2692 return HCLGE_RSS_KEY_SIZE;
2693}
2694
2695static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2696{
2697 return HCLGE_RSS_IND_TBL_SIZE;
2698}
2699
46a3df9f
S		 2700static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2701 const u8 hfunc, const u8 *key)
2702{
d44f9b63 2703 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2704 struct hclge_desc desc;
2705 int key_offset;
2706 int key_size;
2707 int ret;
2708
d44f9b63 2709 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2710
2711 for (key_offset = 0; key_offset < 3; key_offset++) {
2712 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2713 false);
2714
2715 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2716 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2717
2718 if (key_offset == 2)
2719 key_size =
2720 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2721 else
2722 key_size = HCLGE_RSS_HASH_KEY_NUM;
2723
2724 memcpy(req->hash_key,
2725 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2726
2727 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2728 if (ret) {
2729 dev_err(&hdev->pdev->dev,
2730 "Configure RSS config fail, status = %d\n",
2731 ret);
2732 return ret;
2733 }
2734 }
2735 return 0;
2736}
2737
dcd4ef5e 2738static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 2739{
d44f9b63 2740 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 2741 struct hclge_desc desc;
2742 int i, j;
2743 int ret;
2744
d44f9b63 2745 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 2746
2747 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2748 hclge_cmd_setup_basic_desc
2749 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2750
a90bb9a5
YL		 2751 req->start_table_index =
2752 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2753 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 2754
2755 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2756 req->rss_result[j] =
2757 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2758
2759 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2760 if (ret) {
2761 dev_err(&hdev->pdev->dev,
2762 "Configure rss indir table fail,status = %d\n",
2763 ret);
2764 return ret;
2765 }
2766 }
2767 return 0;
2768}
2769
2770static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2771 u16 *tc_size, u16 *tc_offset)
2772{
d44f9b63 2773 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 2774 struct hclge_desc desc;
2775 int ret;
2776 int i;
2777
2778 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 2779 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 2780
2781 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 2782 u16 mode = 0;
2783
ccc23ef3
PL		 2784 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2785 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
2786 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2787 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
2788 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 2789
2790 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 2791 }
2792
2793 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 2794 if (ret)
46a3df9f
S		 2795 dev_err(&hdev->pdev->dev,
2796 "Configure rss tc mode fail, status = %d\n", ret);
46a3df9f 2797
90415e85 2798 return ret;
46a3df9f
S		 2799}
2800
8e4c877d
PL		 2801static void hclge_get_rss_type(struct hclge_vport *vport)
2802{
2803 if (vport->rss_tuple_sets.ipv4_tcp_en ||
2804 vport->rss_tuple_sets.ipv4_udp_en ||
2805 vport->rss_tuple_sets.ipv4_sctp_en ||
2806 vport->rss_tuple_sets.ipv6_tcp_en ||
2807 vport->rss_tuple_sets.ipv6_udp_en ||
2808 vport->rss_tuple_sets.ipv6_sctp_en)
2809 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4;
2810 else if (vport->rss_tuple_sets.ipv4_fragment_en ||
2811 vport->rss_tuple_sets.ipv6_fragment_en)
2812 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3;
2813 else
2814 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE;
2815}
2816
46a3df9f
S		 2817static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2818{
d44f9b63 2819 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 2820 struct hclge_desc desc;
2821 int ret;
2822
2823 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2824
d44f9b63 2825 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef
YL		 2826
2827 /* Get the tuple cfg from pf */
2828 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
2829 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
2830 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
2831 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
2832 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
2833 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
2834 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
2835 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
8e4c877d 2836 hclge_get_rss_type(&hdev->vport[0]);
46a3df9f 2837 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 2838 if (ret)
46a3df9f
S		 2839 dev_err(&hdev->pdev->dev,
2840 "Configure rss input fail, status = %d\n", ret);
90415e85 2841 return ret;
46a3df9f
S		 2842}
2843
2844static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2845 u8 *key, u8 *hfunc)
2846{
2847 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 2848 int i;
2849
2850 /* Get hash algorithm */
6868d695
JS		 2851 if (hfunc) {
2852 switch (vport->rss_algo) {
2853 case HCLGE_RSS_HASH_ALGO_TOEPLITZ:
2854 *hfunc = ETH_RSS_HASH_TOP;
2855 break;
2856 case HCLGE_RSS_HASH_ALGO_SIMPLE:
2857 *hfunc = ETH_RSS_HASH_XOR;
2858 break;
2859 default:
2860 *hfunc = ETH_RSS_HASH_UNKNOWN;
2861 break;
2862 }
2863 }
46a3df9f
S		 2864
2865 /* Get the RSS Key required by the user */
2866 if (key)
2867 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2868
2869 /* Get indirect table */
2870 if (indir)
2871 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2872 indir[i] = vport->rss_indirection_tbl[i];
2873
2874 return 0;
2875}
2876
2877static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2878 const u8 *key, const u8 hfunc)
2879{
2880 struct hclge_vport *vport = hclge_get_vport(handle);
2881 struct hclge_dev *hdev = vport->back;
2882 u8 hash_algo;
2883 int ret, i;
2884
2885 /* Set the RSS Hash Key if specififed by the user */
2886 if (key) {
6868d695
JS		 2887 switch (hfunc) {
2888 case ETH_RSS_HASH_TOP:
46a3df9f 2889 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
6868d695
JS		 2890 break;
2891 case ETH_RSS_HASH_XOR:
2892 hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
2893 break;
2894 case ETH_RSS_HASH_NO_CHANGE:
2895 hash_algo = vport->rss_algo;
2896 break;
2897 default:
46a3df9f 2898 return -EINVAL;
6868d695
JS		 2899 }
2900
46a3df9f
S		 2901 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2902 if (ret)
2903 return ret;
dcd4ef5e
YL		 2904
2905 /* Update the shadow RSS key with user specified qids */
2906 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2907 vport->rss_algo = hash_algo;
46a3df9f
S		 2908 }
2909
2910 /* Update the shadow RSS table with user specified qids */
2911 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2912 vport->rss_indirection_tbl[i] = indir[i];
2913
2914 /* Update the hardware */
dcd4ef5e 2915 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 2916}
2917
f7db940a
L		 2918static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
2919{
2920 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
2921
2922 if (nfc->data & RXH_L4_B_2_3)
2923 hash_sets |= HCLGE_D_PORT_BIT;
2924 else
2925 hash_sets &= ~HCLGE_D_PORT_BIT;
2926
2927 if (nfc->data & RXH_IP_SRC)
2928 hash_sets |= HCLGE_S_IP_BIT;
2929 else
2930 hash_sets &= ~HCLGE_S_IP_BIT;
2931
2932 if (nfc->data & RXH_IP_DST)
2933 hash_sets |= HCLGE_D_IP_BIT;
2934 else
2935 hash_sets &= ~HCLGE_D_IP_BIT;
2936
2937 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
2938 hash_sets |= HCLGE_V_TAG_BIT;
2939
2940 return hash_sets;
2941}
2942
2943static int hclge_set_rss_tuple(struct hnae3_handle *handle,
2944 struct ethtool_rxnfc *nfc)
2945{
2946 struct hclge_vport *vport = hclge_get_vport(handle);
2947 struct hclge_dev *hdev = vport->back;
2948 struct hclge_rss_input_tuple_cmd *req;
2949 struct hclge_desc desc;
2950 u8 tuple_sets;
2951 int ret;
2952
2953 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2954 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2955 return -EINVAL;
2956
2957 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef 2958 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 2959
637053ef
YL		 2960 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
2961 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
2962 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
2963 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
2964 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
2965 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
2966 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
2967 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 2968
2969 tuple_sets = hclge_get_rss_hash_bits(nfc);
2970 switch (nfc->flow_type) {
2971 case TCP_V4_FLOW:
2972 req->ipv4_tcp_en = tuple_sets;
2973 break;
2974 case TCP_V6_FLOW:
2975 req->ipv6_tcp_en = tuple_sets;
2976 break;
2977 case UDP_V4_FLOW:
2978 req->ipv4_udp_en = tuple_sets;
2979 break;
2980 case UDP_V6_FLOW:
2981 req->ipv6_udp_en = tuple_sets;
2982 break;
2983 case SCTP_V4_FLOW:
2984 req->ipv4_sctp_en = tuple_sets;
2985 break;
2986 case SCTP_V6_FLOW:
2987 if ((nfc->data & RXH_L4_B_0_1) ||
2988 (nfc->data & RXH_L4_B_2_3))
2989 return -EINVAL;
2990
2991 req->ipv6_sctp_en = tuple_sets;
2992 break;
2993 case IPV4_FLOW:
2994 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2995 break;
2996 case IPV6_FLOW:
2997 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2998 break;
2999 default:
3000 return -EINVAL;
3001 }
3002
3003 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
637053ef 3004 if (ret) {
f7db940a
L		 3005 dev_err(&hdev->pdev->dev,
3006 "Set rss tuple fail, status = %d\n", ret);
637053ef
YL		 3007 return ret;
3008 }
f7db940a 3009
637053ef
YL		 3010 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3011 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3012 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3013 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3014 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3015 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3016 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3017 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
8e4c877d 3018 hclge_get_rss_type(vport);
637053ef 3019 return 0;
f7db940a
L		 3020}
3021
07d29954
L		 3022static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3023 struct ethtool_rxnfc *nfc)
3024{
3025 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3026 u8 tuple_sets;
07d29954
L		 3027
3028 nfc->data = 0;
3029
07d29954
L		 3030 switch (nfc->flow_type) {
3031 case TCP_V4_FLOW:
637053ef 3032 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3033 break;
3034 case UDP_V4_FLOW:
637053ef 3035 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3036 break;
3037 case TCP_V6_FLOW:
637053ef 3038 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3039 break;
3040 case UDP_V6_FLOW:
637053ef 3041 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3042 break;
3043 case SCTP_V4_FLOW:
637053ef 3044 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3045 break;
3046 case SCTP_V6_FLOW:
637053ef 3047 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3048 break;
3049 case IPV4_FLOW:
3050 case IPV6_FLOW:
3051 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3052 break;
3053 default:
3054 return -EINVAL;
3055 }
3056
3057 if (!tuple_sets)
3058 return 0;
3059
3060 if (tuple_sets & HCLGE_D_PORT_BIT)
3061 nfc->data |= RXH_L4_B_2_3;
3062 if (tuple_sets & HCLGE_S_PORT_BIT)
3063 nfc->data |= RXH_L4_B_0_1;
3064 if (tuple_sets & HCLGE_D_IP_BIT)
3065 nfc->data |= RXH_IP_DST;
3066 if (tuple_sets & HCLGE_S_IP_BIT)
3067 nfc->data |= RXH_IP_SRC;
3068
3069 return 0;
3070}
3071
46a3df9f
S		 3072static int hclge_get_tc_size(struct hnae3_handle *handle)
3073{
3074 struct hclge_vport *vport = hclge_get_vport(handle);
3075 struct hclge_dev *hdev = vport->back;
3076
3077 return hdev->rss_size_max;
3078}
3079
77f255c1 3080int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3081{
46a3df9f 3082 struct hclge_vport *vport = hdev->vport;
8015bb74
YL		 3083 u8 *rss_indir = vport[0].rss_indirection_tbl;
3084 u16 rss_size = vport[0].alloc_rss_size;
3085 u8 *key = vport[0].rss_hash_key;
3086 u8 hfunc = vport[0].rss_algo;
46a3df9f 3087 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3088 u16 tc_valid[HCLGE_MAX_TC_NUM];
3089 u16 tc_size[HCLGE_MAX_TC_NUM];
8015bb74
YL		 3090 u16 roundup_size;
3091 int i, ret;
68ece54e 3092
46a3df9f
S		 3093 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3094 if (ret)
8015bb74 3095 return ret;
46a3df9f 3096
46a3df9f
S		 3097 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3098 if (ret)
8015bb74 3099 return ret;
46a3df9f
S		 3100
3101 ret = hclge_set_rss_input_tuple(hdev);
3102 if (ret)
8015bb74 3103 return ret;
46a3df9f 3104
68ece54e
YL		 3105 /* Each TC have the same queue size, and tc_size set to hardware is
3106 * the log2 of roundup power of two of rss_size, the acutal queue
3107 * size is limited by indirection table.
3108 */
3109 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3110 dev_err(&hdev->pdev->dev,
3111 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3112 rss_size);
8015bb74 3113 return -EINVAL;
68ece54e
YL		 3114 }
3115
3116 roundup_size = roundup_pow_of_two(rss_size);
3117 roundup_size = ilog2(roundup_size);
3118
46a3df9f 3119 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3120 tc_valid[i] = 0;
46a3df9f 3121
68ece54e
YL		 3122 if (!(hdev->hw_tc_map & BIT(i)))
3123 continue;
3124
3125 tc_valid[i] = 1;
3126 tc_size[i] = roundup_size;
3127 tc_offset[i] = rss_size * i;
46a3df9f 3128 }
68ece54e 3129
8015bb74
YL		 3130 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3131}
46a3df9f 3132
8015bb74
YL		 3133void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3134{
3135 struct hclge_vport *vport = hdev->vport;
3136 int i, j;
46a3df9f 3137
8015bb74
YL		 3138 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3139 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3140 vport[j].rss_indirection_tbl[i] =
3141 i % vport[j].alloc_rss_size;
3142 }
3143}
3144
3145static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3146{
3147 struct hclge_vport *vport = hdev->vport;
3148 int i;
3149
8015bb74
YL		 3150 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3151 vport[i].rss_tuple_sets.ipv4_tcp_en =
3152 HCLGE_RSS_INPUT_TUPLE_OTHER;
3153 vport[i].rss_tuple_sets.ipv4_udp_en =
3154 HCLGE_RSS_INPUT_TUPLE_OTHER;
3155 vport[i].rss_tuple_sets.ipv4_sctp_en =
3156 HCLGE_RSS_INPUT_TUPLE_SCTP;
3157 vport[i].rss_tuple_sets.ipv4_fragment_en =
3158 HCLGE_RSS_INPUT_TUPLE_OTHER;
3159 vport[i].rss_tuple_sets.ipv6_tcp_en =
3160 HCLGE_RSS_INPUT_TUPLE_OTHER;
3161 vport[i].rss_tuple_sets.ipv6_udp_en =
3162 HCLGE_RSS_INPUT_TUPLE_OTHER;
3163 vport[i].rss_tuple_sets.ipv6_sctp_en =
3164 HCLGE_RSS_INPUT_TUPLE_SCTP;
3165 vport[i].rss_tuple_sets.ipv6_fragment_en =
3166 HCLGE_RSS_INPUT_TUPLE_OTHER;
3167
3168 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
823fe868
FL		 3169
3170 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
8015bb74
YL		 3171 }
3172
3173 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3174}
3175
63d7e66f
SM		 3176int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3177 int vector_id, bool en,
3178 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3179{
3180 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3181 struct hnae3_ring_chain_node *node;
3182 struct hclge_desc desc;
63d7e66f
SM		 3183 struct hclge_ctrl_vector_chain_cmd *req
3184 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3185 enum hclge_cmd_status status;
3186 enum hclge_opcode_type op;
3187 u16 tqp_type_and_id;
46a3df9f
S		 3188 int i;
3189
63d7e66f
SM		 3190 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3191 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3192 req->int_vector_id = vector_id;
3193
3194 i = 0;
3195 for (node = ring_chain; node; node = node->next) {
63d7e66f 3196 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
ccc23ef3
PL		 3197 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3198 HCLGE_INT_TYPE_S,
3199 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3200 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3201 HCLGE_TQP_ID_S, node->tqp_index);
3202 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3203 HCLGE_INT_GL_IDX_S,
3204 hnae3_get_field(node->int_gl_idx,
3205 HNAE3_RING_GL_IDX_M,
3206 HNAE3_RING_GL_IDX_S));
63d7e66f 3207 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3208 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3209 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
63d7e66f 3210 req->vfid = vport->vport_id;
46a3df9f 3211
63d7e66f
SM		 3212 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3213 if (status) {
46a3df9f
S		 3214 dev_err(&hdev->pdev->dev,
3215 "Map TQP fail, status is %d.\n",
63d7e66f
SM		 3216 status);
3217 return -EIO;
46a3df9f
S		 3218 }
3219 i = 0;
3220
3221 hclge_cmd_setup_basic_desc(&desc,
63d7e66f 3222 op,
46a3df9f
S		 3223 false);
3224 req->int_vector_id = vector_id;
3225 }
3226 }
3227
3228 if (i > 0) {
3229 req->int_cause_num = i;
63d7e66f
SM		 3230 req->vfid = vport->vport_id;
3231 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3232 if (status) {
46a3df9f 3233 dev_err(&hdev->pdev->dev,
63d7e66f
SM		 3234 "Map TQP fail, status is %d.\n", status);
3235 return -EIO;
46a3df9f
S		 3236 }
3237 }
3238
3239 return 0;
3240}
3241
63d7e66f
SM		 3242static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3243 int vector,
3244 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3245{
3246 struct hclge_vport *vport = hclge_get_vport(handle);
3247 struct hclge_dev *hdev = vport->back;
3248 int vector_id;
3249
3250 vector_id = hclge_get_vector_index(hdev, vector);
3251 if (vector_id < 0) {
3252 dev_err(&hdev->pdev->dev,
63d7e66f 3253 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3254 return vector_id;
3255 }
3256
63d7e66f 3257 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3258}
3259
63d7e66f
SM		 3260static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3261 int vector,
3262 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3263{
3264 struct hclge_vport *vport = hclge_get_vport(handle);
3265 struct hclge_dev *hdev = vport->back;
63d7e66f 3266 int vector_id, ret;
46a3df9f 3267
f9637cc2
PL		 3268 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3269 return 0;
3270
46a3df9f
S		 3271 vector_id = hclge_get_vector_index(hdev, vector);
3272 if (vector_id < 0) {
3273 dev_err(&handle->pdev->dev,
3274 "Get vector index fail. ret =%d\n", vector_id);
3275 return vector_id;
3276 }
3277
63d7e66f 3278 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
7412200c 3279 if (ret)
63d7e66f
SM		 3280 dev_err(&handle->pdev->dev,
3281 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3282 vector_id,
3283 ret);
46a3df9f 3284
7412200c 3285 return ret;
46a3df9f
S		 3286}
3287
3288int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3289 struct hclge_promisc_param *param)
3290{
d44f9b63 3291 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3292 struct hclge_desc desc;
3293 int ret;
3294
3295 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3296
d44f9b63 3297 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3298 req->vf_id = param->vf_id;
4771e104
PL		 3299
3300 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3301 * pdev revision(0x20), new revision support them. The
3302 * value of this two fields will not return error when driver
3303 * send command to fireware in revision(0x20).
3304 */
3305 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3306 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3307
3308 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 3309 if (ret)
46a3df9f
S		 3310 dev_err(&hdev->pdev->dev,
3311 "Set promisc mode fail, status is %d.\n", ret);
90415e85
JS		 3312
3313 return ret;
46a3df9f
S		 3314}
3315
3316void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3317 bool en_mc, bool en_bc, int vport_id)
3318{
3319 if (!param)
3320 return;
3321
3322 memset(param, 0, sizeof(struct hclge_promisc_param));
3323 if (en_uc)
3324 param->enable = HCLGE_PROMISC_EN_UC;
3325 if (en_mc)
3326 param->enable |= HCLGE_PROMISC_EN_MC;
3327 if (en_bc)
3328 param->enable |= HCLGE_PROMISC_EN_BC;
3329 param->vf_id = vport_id;
3330}
3331
abe62a63
HT		 3332static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3333 bool en_mc_pmc)
46a3df9f
S		 3334{
3335 struct hclge_vport *vport = hclge_get_vport(handle);
3336 struct hclge_dev *hdev = vport->back;
3337 struct hclge_promisc_param param;
3338
e8600a3d
PL		 3339 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3340 vport->vport_id);
abe62a63 3341 return hclge_cmd_set_promisc_mode(hdev, &param);
46a3df9f
S		 3342}
3343
10a954bc
JS		 3344static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
3345{
3346 struct hclge_get_fd_mode_cmd *req;
3347 struct hclge_desc desc;
3348 int ret;
3349
3350 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
3351
3352 req = (struct hclge_get_fd_mode_cmd *)desc.data;
3353
3354 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3355 if (ret) {
3356 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
3357 return ret;
3358 }
3359
3360 *fd_mode = req->mode;
3361
3362 return ret;
3363}
3364
3365static int hclge_get_fd_allocation(struct hclge_dev *hdev,
3366 u32 *stage1_entry_num,
3367 u32 *stage2_entry_num,
3368 u16 *stage1_counter_num,
3369 u16 *stage2_counter_num)
3370{
3371 struct hclge_get_fd_allocation_cmd *req;
3372 struct hclge_desc desc;
3373 int ret;
3374
3375 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
3376
3377 req = (struct hclge_get_fd_allocation_cmd *)desc.data;
3378
3379 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3380 if (ret) {
3381 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
3382 ret);
3383 return ret;
3384 }
3385
3386 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
3387 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
3388 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
3389 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
3390
3391 return ret;
3392}
3393
3394static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num)
3395{
3396 struct hclge_set_fd_key_config_cmd *req;
3397 struct hclge_fd_key_cfg *stage;
3398 struct hclge_desc desc;
3399 int ret;
3400
3401 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
3402
3403 req = (struct hclge_set_fd_key_config_cmd *)desc.data;
3404 stage = &hdev->fd_cfg.key_cfg[stage_num];
3405 req->stage = stage_num;
3406 req->key_select = stage->key_sel;
3407 req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
3408 req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
3409 req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
3410 req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
3411 req->tuple_mask = cpu_to_le32(~stage->tuple_active);
3412 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
3413
3414 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3415 if (ret)
3416 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
3417
3418 return ret;
3419}
3420
3421static int hclge_init_fd_config(struct hclge_dev *hdev)
3422{
3423#define LOW_2_WORDS 0x03
3424 struct hclge_fd_key_cfg *key_cfg;
3425 int ret;
3426
3427 if (!hnae3_dev_fd_supported(hdev))
3428 return 0;
3429
3430 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
3431 if (ret)
3432 return ret;
3433
3434 switch (hdev->fd_cfg.fd_mode) {
3435 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
3436 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
3437 break;
3438 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
3439 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
3440 break;
3441 default:
3442 dev_err(&hdev->pdev->dev,
3443 "Unsupported flow director mode %d\n",
3444 hdev->fd_cfg.fd_mode);
3445 return -EOPNOTSUPP;
3446 }
3447
3448 hdev->fd_cfg.fd_en = true;
3449 hdev->fd_cfg.proto_support =
3450 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW |
3451 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW;
3452 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
3453 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE,
3454 key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
3455 key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
3456 key_cfg->outer_sipv6_word_en = 0;
3457 key_cfg->outer_dipv6_word_en = 0;
3458
3459 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
3460 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
3461 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3462 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3463
3464 /* If use max 400bit key, we can support tuples for ether type */
3465 if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) {
3466 hdev->fd_cfg.proto_support |= ETHER_FLOW;
3467 key_cfg->tuple_active |=
3468 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
3469 }
3470
3471 /* roce_type is used to filter roce frames
3472 * dst_vport is used to specify the rule
3473 */
3474 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
3475
3476 ret = hclge_get_fd_allocation(hdev,
3477 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
3478 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
3479 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
3480 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
3481 if (ret)
3482 return ret;
3483
3484 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
3485}
3486
7b829126
JS		 3487static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
3488 int loc, u8 *key, bool is_add)
3489{
3490 struct hclge_fd_tcam_config_1_cmd *req1;
3491 struct hclge_fd_tcam_config_2_cmd *req2;
3492 struct hclge_fd_tcam_config_3_cmd *req3;
3493 struct hclge_desc desc[3];
3494 int ret;
3495
3496 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
3497 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3498 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
3499 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3500 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
3501
3502 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
3503 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
3504 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
3505
3506 req1->stage = stage;
3507 req1->xy_sel = sel_x ? 1 : 0;
3508 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
3509 req1->index = cpu_to_le32(loc);
3510 req1->entry_vld = sel_x ? is_add : 0;
3511
3512 if (key) {
3513 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
3514 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
3515 sizeof(req2->tcam_data));
3516 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
3517 sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
3518 }
3519
3520 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3521 if (ret)
3522 dev_err(&hdev->pdev->dev,
3523 "config tcam key fail, ret=%d\n",
3524 ret);
3525
3526 return ret;
3527}
3528
3529static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
3530 struct hclge_fd_ad_data *action)
3531{
3532 struct hclge_fd_ad_config_cmd *req;
3533 struct hclge_desc desc;
3534 u64 ad_data = 0;
3535 int ret;
3536
3537 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
3538
3539 req = (struct hclge_fd_ad_config_cmd *)desc.data;
3540 req->index = cpu_to_le32(loc);
3541 req->stage = stage;
3542
3543 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
3544 action->write_rule_id_to_bd);
3545 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
3546 action->rule_id);
3547 ad_data <<= 32;
3548 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
3549 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
3550 action->forward_to_direct_queue);
3551 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
3552 action->queue_id);
3553 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
3554 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
3555 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
3556 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
3557 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
3558 action->counter_id);
3559
3560 req->ad_data = cpu_to_le64(ad_data);
3561 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3562 if (ret)
3563 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
3564
3565 return ret;
3566}
3567
3568static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
3569 struct hclge_fd_rule *rule)
3570{
3571 u16 tmp_x_s, tmp_y_s;
3572 u32 tmp_x_l, tmp_y_l;
3573 int i;
3574
3575 if (rule->unused_tuple & tuple_bit)
3576 return true;
3577
3578 switch (tuple_bit) {
3579 case 0:
3580 return false;
3581 case BIT(INNER_DST_MAC):
3582 for (i = 0; i < 6; i++) {
3583 calc_x(key_x[5 - i], rule->tuples.dst_mac[i],
3584 rule->tuples_mask.dst_mac[i]);
3585 calc_y(key_y[5 - i], rule->tuples.dst_mac[i],
3586 rule->tuples_mask.dst_mac[i]);
3587 }
3588
3589 return true;
3590 case BIT(INNER_SRC_MAC):
3591 for (i = 0; i < 6; i++) {
3592 calc_x(key_x[5 - i], rule->tuples.src_mac[i],
3593 rule->tuples.src_mac[i]);
3594 calc_y(key_y[5 - i], rule->tuples.src_mac[i],
3595 rule->tuples.src_mac[i]);
3596 }
3597
3598 return true;
3599 case BIT(INNER_VLAN_TAG_FST):
3600 calc_x(tmp_x_s, rule->tuples.vlan_tag1,
3601 rule->tuples_mask.vlan_tag1);
3602 calc_y(tmp_y_s, rule->tuples.vlan_tag1,
3603 rule->tuples_mask.vlan_tag1);
3604 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3605 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3606
3607 return true;
3608 case BIT(INNER_ETH_TYPE):
3609 calc_x(tmp_x_s, rule->tuples.ether_proto,
3610 rule->tuples_mask.ether_proto);
3611 calc_y(tmp_y_s, rule->tuples.ether_proto,
3612 rule->tuples_mask.ether_proto);
3613 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3614 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3615
3616 return true;
3617 case BIT(INNER_IP_TOS):
3618 calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3619 calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3620
3621 return true;
3622 case BIT(INNER_IP_PROTO):
3623 calc_x(*key_x, rule->tuples.ip_proto,
3624 rule->tuples_mask.ip_proto);
3625 calc_y(*key_y, rule->tuples.ip_proto,
3626 rule->tuples_mask.ip_proto);
3627
3628 return true;
3629 case BIT(INNER_SRC_IP):
3630 calc_x(tmp_x_l, rule->tuples.src_ip[3],
3631 rule->tuples_mask.src_ip[3]);
3632 calc_y(tmp_y_l, rule->tuples.src_ip[3],
3633 rule->tuples_mask.src_ip[3]);
3634 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3635 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3636
3637 return true;
3638 case BIT(INNER_DST_IP):
3639 calc_x(tmp_x_l, rule->tuples.dst_ip[3],
3640 rule->tuples_mask.dst_ip[3]);
3641 calc_y(tmp_y_l, rule->tuples.dst_ip[3],
3642 rule->tuples_mask.dst_ip[3]);
3643 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3644 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3645
3646 return true;
3647 case BIT(INNER_SRC_PORT):
3648 calc_x(tmp_x_s, rule->tuples.src_port,
3649 rule->tuples_mask.src_port);
3650 calc_y(tmp_y_s, rule->tuples.src_port,
3651 rule->tuples_mask.src_port);
3652 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3653 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3654
3655 return true;
3656 case BIT(INNER_DST_PORT):
3657 calc_x(tmp_x_s, rule->tuples.dst_port,
3658 rule->tuples_mask.dst_port);
3659 calc_y(tmp_y_s, rule->tuples.dst_port,
3660 rule->tuples_mask.dst_port);
3661 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3662 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3663
3664 return true;
3665 default:
3666 return false;
3667 }
3668}
3669
3670static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
3671 u8 vf_id, u8 network_port_id)
3672{
3673 u32 port_number = 0;
3674
3675 if (port_type == HOST_PORT) {
3676 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
3677 pf_id);
3678 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
3679 vf_id);
3680 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
3681 } else {
3682 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
3683 HCLGE_NETWORK_PORT_ID_S, network_port_id);
3684 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
3685 }
3686
3687 return port_number;
3688}
3689
3690static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
3691 __le32 *key_x, __le32 *key_y,
3692 struct hclge_fd_rule *rule)
3693{
3694 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
3695 u8 cur_pos = 0, tuple_size, shift_bits;
3696 int i;
3697
3698 for (i = 0; i < MAX_META_DATA; i++) {
3699 tuple_size = meta_data_key_info[i].key_length;
3700 tuple_bit = key_cfg->meta_data_active & BIT(i);
3701
3702 switch (tuple_bit) {
3703 case BIT(ROCE_TYPE):
3704 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
3705 cur_pos += tuple_size;
3706 break;
3707 case BIT(DST_VPORT):
3708 port_number = hclge_get_port_number(HOST_PORT, 0,
3709 rule->vf_id, 0);
3710 hnae3_set_field(meta_data,
3711 GENMASK(cur_pos + tuple_size, cur_pos),
3712 cur_pos, port_number);
3713 cur_pos += tuple_size;
3714 break;
3715 default:
3716 break;
3717 }
3718 }
3719
3720 calc_x(tmp_x, meta_data, 0xFFFFFFFF);
3721 calc_y(tmp_y, meta_data, 0xFFFFFFFF);
3722 shift_bits = sizeof(meta_data) * 8 - cur_pos;
3723
3724 *key_x = cpu_to_le32(tmp_x << shift_bits);
3725 *key_y = cpu_to_le32(tmp_y << shift_bits);
3726}
3727
3728/* A complete key is combined with meta data key and tuple key.
3729 * Meta data key is stored at the MSB region, and tuple key is stored at
3730 * the LSB region, unused bits will be filled 0.
3731 */
3732static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
3733 struct hclge_fd_rule *rule)
3734{
3735 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
3736 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
3737 u8 *cur_key_x, *cur_key_y;
3738 int i, ret, tuple_size;
3739 u8 meta_data_region;
3740
3741 memset(key_x, 0, sizeof(key_x));
3742 memset(key_y, 0, sizeof(key_y));
3743 cur_key_x = key_x;
3744 cur_key_y = key_y;
3745
3746 for (i = 0 ; i < MAX_TUPLE; i++) {
3747 bool tuple_valid;
3748 u32 check_tuple;
3749
3750 tuple_size = tuple_key_info[i].key_length / 8;
3751 check_tuple = key_cfg->tuple_active & BIT(i);
3752
3753 tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
3754 cur_key_y, rule);
3755 if (tuple_valid) {
3756 cur_key_x += tuple_size;
3757 cur_key_y += tuple_size;
3758 }
3759 }
3760
3761 meta_data_region = hdev->fd_cfg.max_key_length / 8 -
3762 MAX_META_DATA_LENGTH / 8;
3763
3764 hclge_fd_convert_meta_data(key_cfg,
3765 (__le32 *)(key_x + meta_data_region),
3766 (__le32 *)(key_y + meta_data_region),
3767 rule);
3768
3769 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
3770 true);
3771 if (ret) {
3772 dev_err(&hdev->pdev->dev,
3773 "fd key_y config fail, loc=%d, ret=%d\n",
3774 rule->queue_id, ret);
3775 return ret;
3776 }
3777
3778 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
3779 true);
3780 if (ret)
3781 dev_err(&hdev->pdev->dev,
3782 "fd key_x config fail, loc=%d, ret=%d\n",
3783 rule->queue_id, ret);
3784 return ret;
3785}
3786
3787static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
3788 struct hclge_fd_rule *rule)
3789{
3790 struct hclge_fd_ad_data ad_data;
3791
3792 ad_data.ad_id = rule->location;
3793
3794 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
3795 ad_data.drop_packet = true;
3796 ad_data.forward_to_direct_queue = false;
3797 ad_data.queue_id = 0;
3798 } else {
3799 ad_data.drop_packet = false;
3800 ad_data.forward_to_direct_queue = true;
3801 ad_data.queue_id = rule->queue_id;
3802 }
3803
3804 ad_data.use_counter = false;
3805 ad_data.counter_id = 0;
3806
3807 ad_data.use_next_stage = false;
3808 ad_data.next_input_key = 0;
3809
3810 ad_data.write_rule_id_to_bd = true;
3811 ad_data.rule_id = rule->location;
3812
3813 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
3814}
3815
3ca8e27c
JS		 3816static int hclge_fd_check_spec(struct hclge_dev *hdev,
3817 struct ethtool_rx_flow_spec *fs, u32 *unused)
3818{
3819 struct ethtool_tcpip4_spec *tcp_ip4_spec;
3820 struct ethtool_usrip4_spec *usr_ip4_spec;
3821 struct ethtool_tcpip6_spec *tcp_ip6_spec;
3822 struct ethtool_usrip6_spec *usr_ip6_spec;
3823 struct ethhdr *ether_spec;
3824
3825 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
3826 return -EINVAL;
3827
3828 if (!(fs->flow_type & hdev->fd_cfg.proto_support))
3829 return -EOPNOTSUPP;
3830
3831 if ((fs->flow_type & FLOW_EXT) &&
3832 (fs->h_ext.data[0] != 0 || fs->h_ext.data[1] != 0)) {
3833 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
3834 return -EOPNOTSUPP;
3835 }
3836
3837 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
3838 case SCTP_V4_FLOW:
3839 case TCP_V4_FLOW:
3840 case UDP_V4_FLOW:
3841 tcp_ip4_spec = &fs->h_u.tcp_ip4_spec;
3842 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
3843
3844 if (!tcp_ip4_spec->ip4src)
3845 *unused |= BIT(INNER_SRC_IP);
3846
3847 if (!tcp_ip4_spec->ip4dst)
3848 *unused |= BIT(INNER_DST_IP);
3849
3850 if (!tcp_ip4_spec->psrc)
3851 *unused |= BIT(INNER_SRC_PORT);
3852
3853 if (!tcp_ip4_spec->pdst)
3854 *unused |= BIT(INNER_DST_PORT);
3855
3856 if (!tcp_ip4_spec->tos)
3857 *unused |= BIT(INNER_IP_TOS);
3858
3859 break;
3860 case IP_USER_FLOW:
3861 usr_ip4_spec = &fs->h_u.usr_ip4_spec;
3862 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
3863 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3864
3865 if (!usr_ip4_spec->ip4src)
3866 *unused |= BIT(INNER_SRC_IP);
3867
3868 if (!usr_ip4_spec->ip4dst)
3869 *unused |= BIT(INNER_DST_IP);
3870
3871 if (!usr_ip4_spec->tos)
3872 *unused |= BIT(INNER_IP_TOS);
3873
3874 if (!usr_ip4_spec->proto)
3875 *unused |= BIT(INNER_IP_PROTO);
3876
3877 if (usr_ip4_spec->l4_4_bytes)
3878 return -EOPNOTSUPP;
3879
3880 if (usr_ip4_spec->ip_ver != ETH_RX_NFC_IP4)
3881 return -EOPNOTSUPP;
3882
3883 break;
3884 case SCTP_V6_FLOW:
3885 case TCP_V6_FLOW:
3886 case UDP_V6_FLOW:
3887 tcp_ip6_spec = &fs->h_u.tcp_ip6_spec;
3888 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
3889 BIT(INNER_IP_TOS);
3890
3891 if (!tcp_ip6_spec->ip6src[0] && !tcp_ip6_spec->ip6src[1] &&
3892 !tcp_ip6_spec->ip6src[2] && !tcp_ip6_spec->ip6src[3])
3893 *unused |= BIT(INNER_SRC_IP);
3894
3895 if (!tcp_ip6_spec->ip6dst[0] && !tcp_ip6_spec->ip6dst[1] &&
3896 !tcp_ip6_spec->ip6dst[2] && !tcp_ip6_spec->ip6dst[3])
3897 *unused |= BIT(INNER_DST_IP);
3898
3899 if (!tcp_ip6_spec->psrc)
3900 *unused |= BIT(INNER_SRC_PORT);
3901
3902 if (!tcp_ip6_spec->pdst)
3903 *unused |= BIT(INNER_DST_PORT);
3904
3905 if (tcp_ip6_spec->tclass)
3906 return -EOPNOTSUPP;
3907
3908 break;
3909 case IPV6_USER_FLOW:
3910 usr_ip6_spec = &fs->h_u.usr_ip6_spec;
3911 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
3912 BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) |
3913 BIT(INNER_DST_PORT);
3914
3915 if (!usr_ip6_spec->ip6src[0] && !usr_ip6_spec->ip6src[1] &&
3916 !usr_ip6_spec->ip6src[2] && !usr_ip6_spec->ip6src[3])
3917 *unused |= BIT(INNER_SRC_IP);
3918
3919 if (!usr_ip6_spec->ip6dst[0] && !usr_ip6_spec->ip6dst[1] &&
3920 !usr_ip6_spec->ip6dst[2] && !usr_ip6_spec->ip6dst[3])
3921 *unused |= BIT(INNER_DST_IP);
3922
3923 if (!usr_ip6_spec->l4_proto)
3924 *unused |= BIT(INNER_IP_PROTO);
3925
3926 if (usr_ip6_spec->tclass)
3927 return -EOPNOTSUPP;
3928
3929 if (usr_ip6_spec->l4_4_bytes)
3930 return -EOPNOTSUPP;
3931
3932 break;
3933 case ETHER_FLOW:
3934 ether_spec = &fs->h_u.ether_spec;
3935 *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3936 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
3937 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
3938
3939 if (is_zero_ether_addr(ether_spec->h_source))
3940 *unused |= BIT(INNER_SRC_MAC);
3941
3942 if (is_zero_ether_addr(ether_spec->h_dest))
3943 *unused |= BIT(INNER_DST_MAC);
3944
3945 if (!ether_spec->h_proto)
3946 *unused |= BIT(INNER_ETH_TYPE);
3947
3948 break;
3949 default:
3950 return -EOPNOTSUPP;
3951 }
3952
3953 if ((fs->flow_type & FLOW_EXT)) {
3954 if (fs->h_ext.vlan_etype)
3955 return -EOPNOTSUPP;
3956 if (!fs->h_ext.vlan_tci)
3957 *unused |= BIT(INNER_VLAN_TAG_FST);
3958
3959 if (fs->m_ext.vlan_tci) {
3960 if (be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID)
3961 return -EINVAL;
3962 }
3963 } else {
3964 *unused |= BIT(INNER_VLAN_TAG_FST);
3965 }
3966
3967 if (fs->flow_type & FLOW_MAC_EXT) {
3968 if (!(hdev->fd_cfg.proto_support & ETHER_FLOW))
3969 return -EOPNOTSUPP;
3970
3971 if (is_zero_ether_addr(fs->h_ext.h_dest))
3972 *unused |= BIT(INNER_DST_MAC);
3973 else
3974 *unused &= ~(BIT(INNER_DST_MAC));
3975 }
3976
3977 return 0;
3978}
3979
3980static bool hclge_fd_rule_exist(struct hclge_dev *hdev, u16 location)
3981{
3982 struct hclge_fd_rule *rule = NULL;
3983 struct hlist_node *node2;
3984
3985 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
3986 if (rule->location >= location)
3987 break;
3988 }
3989
3990 return rule && rule->location == location;
3991}
3992
3993static int hclge_fd_update_rule_list(struct hclge_dev *hdev,
3994 struct hclge_fd_rule *new_rule,
3995 u16 location,
3996 bool is_add)
3997{
3998 struct hclge_fd_rule *rule = NULL, *parent = NULL;
3999 struct hlist_node *node2;
4000
4001 if (is_add && !new_rule)
4002 return -EINVAL;
4003
4004 hlist_for_each_entry_safe(rule, node2,
4005 &hdev->fd_rule_list, rule_node) {
4006 if (rule->location >= location)
4007 break;
4008 parent = rule;
4009 }
4010
4011 if (rule && rule->location == location) {
4012 hlist_del(&rule->rule_node);
4013 kfree(rule);
4014 hdev->hclge_fd_rule_num--;
4015
4016 if (!is_add)
4017 return 0;
4018
4019 } else if (!is_add) {
4020 dev_err(&hdev->pdev->dev,
4021 "delete fail, rule %d is inexistent\n",
4022 location);
4023 return -EINVAL;
4024 }
4025
4026 INIT_HLIST_NODE(&new_rule->rule_node);
4027
4028 if (parent)
4029 hlist_add_behind(&new_rule->rule_node, &parent->rule_node);
4030 else
4031 hlist_add_head(&new_rule->rule_node, &hdev->fd_rule_list);
4032
4033 hdev->hclge_fd_rule_num++;
4034
4035 return 0;
4036}
4037
4038static int hclge_fd_get_tuple(struct hclge_dev *hdev,
4039 struct ethtool_rx_flow_spec *fs,
4040 struct hclge_fd_rule *rule)
4041{
4042 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
4043
4044 switch (flow_type) {
4045 case SCTP_V4_FLOW:
4046 case TCP_V4_FLOW:
4047 case UDP_V4_FLOW:
4048 rule->tuples.src_ip[3] =
4049 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
4050 rule->tuples_mask.src_ip[3] =
4051 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
4052
4053 rule->tuples.dst_ip[3] =
4054 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
4055 rule->tuples_mask.dst_ip[3] =
4056 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
4057
4058 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
4059 rule->tuples_mask.src_port =
4060 be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
4061
4062 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
4063 rule->tuples_mask.dst_port =
4064 be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
4065
4066 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
4067 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
4068
4069 rule->tuples.ether_proto = ETH_P_IP;
4070 rule->tuples_mask.ether_proto = 0xFFFF;
4071
4072 break;
4073 case IP_USER_FLOW:
4074 rule->tuples.src_ip[3] =
4075 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
4076 rule->tuples_mask.src_ip[3] =
4077 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
4078
4079 rule->tuples.dst_ip[3] =
4080 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
4081 rule->tuples_mask.dst_ip[3] =
4082 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
4083
4084 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
4085 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
4086
4087 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
4088 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
4089
4090 rule->tuples.ether_proto = ETH_P_IP;
4091 rule->tuples_mask.ether_proto = 0xFFFF;
4092
4093 break;
4094 case SCTP_V6_FLOW:
4095 case TCP_V6_FLOW:
4096 case UDP_V6_FLOW:
4097 be32_to_cpu_array(rule->tuples.src_ip,
4098 fs->h_u.tcp_ip6_spec.ip6src, 4);
4099 be32_to_cpu_array(rule->tuples_mask.src_ip,
4100 fs->m_u.tcp_ip6_spec.ip6src, 4);
4101
4102 be32_to_cpu_array(rule->tuples.dst_ip,
4103 fs->h_u.tcp_ip6_spec.ip6dst, 4);
4104 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4105 fs->m_u.tcp_ip6_spec.ip6dst, 4);
4106
4107 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
4108 rule->tuples_mask.src_port =
4109 be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
4110
4111 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
4112 rule->tuples_mask.dst_port =
4113 be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
4114
4115 rule->tuples.ether_proto = ETH_P_IPV6;
4116 rule->tuples_mask.ether_proto = 0xFFFF;
4117
4118 break;
4119 case IPV6_USER_FLOW:
4120 be32_to_cpu_array(rule->tuples.src_ip,
4121 fs->h_u.usr_ip6_spec.ip6src, 4);
4122 be32_to_cpu_array(rule->tuples_mask.src_ip,
4123 fs->m_u.usr_ip6_spec.ip6src, 4);
4124
4125 be32_to_cpu_array(rule->tuples.dst_ip,
4126 fs->h_u.usr_ip6_spec.ip6dst, 4);
4127 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4128 fs->m_u.usr_ip6_spec.ip6dst, 4);
4129
4130 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
4131 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
4132
4133 rule->tuples.ether_proto = ETH_P_IPV6;
4134 rule->tuples_mask.ether_proto = 0xFFFF;
4135
4136 break;
4137 case ETHER_FLOW:
4138 ether_addr_copy(rule->tuples.src_mac,
4139 fs->h_u.ether_spec.h_source);
4140 ether_addr_copy(rule->tuples_mask.src_mac,
4141 fs->m_u.ether_spec.h_source);
4142
4143 ether_addr_copy(rule->tuples.dst_mac,
4144 fs->h_u.ether_spec.h_dest);
4145 ether_addr_copy(rule->tuples_mask.dst_mac,
4146 fs->m_u.ether_spec.h_dest);
4147
4148 rule->tuples.ether_proto =
4149 be16_to_cpu(fs->h_u.ether_spec.h_proto);
4150 rule->tuples_mask.ether_proto =
4151 be16_to_cpu(fs->m_u.ether_spec.h_proto);
4152
4153 break;
4154 default:
4155 return -EOPNOTSUPP;
4156 }
4157
4158 switch (flow_type) {
4159 case SCTP_V4_FLOW:
4160 case SCTP_V6_FLOW:
4161 rule->tuples.ip_proto = IPPROTO_SCTP;
4162 rule->tuples_mask.ip_proto = 0xFF;
4163 break;
4164 case TCP_V4_FLOW:
4165 case TCP_V6_FLOW:
4166 rule->tuples.ip_proto = IPPROTO_TCP;
4167 rule->tuples_mask.ip_proto = 0xFF;
4168 break;
4169 case UDP_V4_FLOW:
4170 case UDP_V6_FLOW:
4171 rule->tuples.ip_proto = IPPROTO_UDP;
4172 rule->tuples_mask.ip_proto = 0xFF;
4173 break;
4174 default:
4175 break;
4176 }
4177
4178 if ((fs->flow_type & FLOW_EXT)) {
4179 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
4180 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
4181 }
4182
4183 if (fs->flow_type & FLOW_MAC_EXT) {
4184 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
4185 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
4186 }
4187
4188 return 0;
4189}
4190
4191static int hclge_add_fd_entry(struct hnae3_handle *handle,
4192 struct ethtool_rxnfc *cmd)
4193{
4194 struct hclge_vport *vport = hclge_get_vport(handle);
4195 struct hclge_dev *hdev = vport->back;
4196 u16 dst_vport_id = 0, q_index = 0;
4197 struct ethtool_rx_flow_spec *fs;
4198 struct hclge_fd_rule *rule;
4199 u32 unused = 0;
4200 u8 action;
4201 int ret;
4202
4203 if (!hnae3_dev_fd_supported(hdev))
4204 return -EOPNOTSUPP;
4205
4206 if (!hdev->fd_cfg.fd_en) {
4207 dev_warn(&hdev->pdev->dev,
4208 "Please enable flow director first\n");
4209 return -EOPNOTSUPP;
4210 }
4211
4212 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4213
4214 ret = hclge_fd_check_spec(hdev, fs, &unused);
4215 if (ret) {
4216 dev_err(&hdev->pdev->dev, "Check fd spec failed\n");
4217 return ret;
4218 }
4219
4220 if (fs->ring_cookie == RX_CLS_FLOW_DISC) {
4221 action = HCLGE_FD_ACTION_DROP_PACKET;
4222 } else {
4223 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
4224 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
4225 u16 tqps;
4226
4227 dst_vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
4228 tqps = vf ? hdev->vport[vf].alloc_tqps : vport->alloc_tqps;
4229
4230 if (ring >= tqps) {
4231 dev_err(&hdev->pdev->dev,
4232 "Error: queue id (%d) > max tqp num (%d)\n",
4233 ring, tqps - 1);
4234 return -EINVAL;
4235 }
4236
4237 if (vf > hdev->num_req_vfs) {
4238 dev_err(&hdev->pdev->dev,
4239 "Error: vf id (%d) > max vf num (%d)\n",
4240 vf, hdev->num_req_vfs);
4241 return -EINVAL;
4242 }
4243
4244 action = HCLGE_FD_ACTION_ACCEPT_PACKET;
4245 q_index = ring;
4246 }
4247
4248 rule = kzalloc(sizeof(*rule), GFP_KERNEL);
4249 if (!rule)
4250 return -ENOMEM;
4251
4252 ret = hclge_fd_get_tuple(hdev, fs, rule);
4253 if (ret)
4254 goto free_rule;
4255
4256 rule->flow_type = fs->flow_type;
4257
4258 rule->location = fs->location;
4259 rule->unused_tuple = unused;
4260 rule->vf_id = dst_vport_id;
4261 rule->queue_id = q_index;
4262 rule->action = action;
4263
4264 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4265 if (ret)
4266 goto free_rule;
4267
4268 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4269 if (ret)
4270 goto free_rule;
4271
4272 ret = hclge_fd_update_rule_list(hdev, rule, fs->location, true);
4273 if (ret)
4274 goto free_rule;
4275
4276 return ret;
4277
4278free_rule:
4279 kfree(rule);
4280 return ret;
4281}
4282
4283static int hclge_del_fd_entry(struct hnae3_handle *handle,
4284 struct ethtool_rxnfc *cmd)
4285{
4286 struct hclge_vport *vport = hclge_get_vport(handle);
4287 struct hclge_dev *hdev = vport->back;
4288 struct ethtool_rx_flow_spec *fs;
4289 int ret;
4290
4291 if (!hnae3_dev_fd_supported(hdev))
4292 return -EOPNOTSUPP;
4293
4294 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4295
4296 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4297 return -EINVAL;
4298
4299 if (!hclge_fd_rule_exist(hdev, fs->location)) {
4300 dev_err(&hdev->pdev->dev,
4301 "Delete fail, rule %d is inexistent\n",
4302 fs->location);
4303 return -ENOENT;
4304 }
4305
4306 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4307 fs->location, NULL, false);
4308 if (ret)
4309 return ret;
4310
4311 return hclge_fd_update_rule_list(hdev, NULL, fs->location,
4312 false);
4313}
4314
7ce98982
JS		 4315static void hclge_del_all_fd_entries(struct hnae3_handle *handle,
4316 bool clear_list)
4317{
4318 struct hclge_vport *vport = hclge_get_vport(handle);
4319 struct hclge_dev *hdev = vport->back;
4320 struct hclge_fd_rule *rule;
4321 struct hlist_node *node;
4322
4323 if (!hnae3_dev_fd_supported(hdev))
4324 return;
4325
4326 if (clear_list) {
4327 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4328 rule_node) {
4329 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4330 rule->location, NULL, false);
4331 hlist_del(&rule->rule_node);
4332 kfree(rule);
4333 hdev->hclge_fd_rule_num--;
4334 }
4335 } else {
4336 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4337 rule_node)
4338 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4339 rule->location, NULL, false);
4340 }
4341}
4342
4343static int hclge_restore_fd_entries(struct hnae3_handle *handle)
4344{
4345 struct hclge_vport *vport = hclge_get_vport(handle);
4346 struct hclge_dev *hdev = vport->back;
4347 struct hclge_fd_rule *rule;
4348 struct hlist_node *node;
4349 int ret;
4350
4351 if (!hnae3_dev_fd_supported(hdev))
4352 return -EOPNOTSUPP;
4353
4354 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
4355 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4356 if (!ret)
4357 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4358
4359 if (ret) {
4360 dev_warn(&hdev->pdev->dev,
4361 "Restore rule %d failed, remove it\n",
4362 rule->location);
4363 hlist_del(&rule->rule_node);
4364 kfree(rule);
4365 hdev->hclge_fd_rule_num--;
4366 }
4367 }
4368 return 0;
4369}
4370
295043a7
JS		 4371static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
4372 struct ethtool_rxnfc *cmd)
4373{
4374 struct hclge_vport *vport = hclge_get_vport(handle);
4375 struct hclge_dev *hdev = vport->back;
4376
4377 if (!hnae3_dev_fd_supported(hdev))
4378 return -EOPNOTSUPP;
4379
4380 cmd->rule_cnt = hdev->hclge_fd_rule_num;
4381 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4382
4383 return 0;
4384}
4385
4386static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
4387 struct ethtool_rxnfc *cmd)
4388{
4389 struct hclge_vport *vport = hclge_get_vport(handle);
4390 struct hclge_fd_rule *rule = NULL;
4391 struct hclge_dev *hdev = vport->back;
4392 struct ethtool_rx_flow_spec *fs;
4393 struct hlist_node *node2;
4394
4395 if (!hnae3_dev_fd_supported(hdev))
4396 return -EOPNOTSUPP;
4397
4398 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4399
4400 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4401 if (rule->location >= fs->location)
4402 break;
4403 }
4404
4405 if (!rule || fs->location != rule->location)
4406 return -ENOENT;
4407
4408 fs->flow_type = rule->flow_type;
4409 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4410 case SCTP_V4_FLOW:
4411 case TCP_V4_FLOW:
4412 case UDP_V4_FLOW:
4413 fs->h_u.tcp_ip4_spec.ip4src =
4414 cpu_to_be32(rule->tuples.src_ip[3]);
4415 fs->m_u.tcp_ip4_spec.ip4src =
4416 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4417 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4418
4419 fs->h_u.tcp_ip4_spec.ip4dst =
4420 cpu_to_be32(rule->tuples.dst_ip[3]);
4421 fs->m_u.tcp_ip4_spec.ip4dst =
4422 rule->unused_tuple & BIT(INNER_DST_IP) ?
4423 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4424
4425 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4426 fs->m_u.tcp_ip4_spec.psrc =
4427 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4428 0 : cpu_to_be16(rule->tuples_mask.src_port);
4429
4430 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4431 fs->m_u.tcp_ip4_spec.pdst =
4432 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4433 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4434
4435 fs->h_u.tcp_ip4_spec.tos = rule->tuples.ip_tos;
4436 fs->m_u.tcp_ip4_spec.tos =
4437 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4438 0 : rule->tuples_mask.ip_tos;
4439
4440 break;
4441 case IP_USER_FLOW:
4442 fs->h_u.usr_ip4_spec.ip4src =
4443 cpu_to_be32(rule->tuples.src_ip[3]);
4444 fs->m_u.tcp_ip4_spec.ip4src =
4445 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4446 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4447
4448 fs->h_u.usr_ip4_spec.ip4dst =
4449 cpu_to_be32(rule->tuples.dst_ip[3]);
4450 fs->m_u.usr_ip4_spec.ip4dst =
4451 rule->unused_tuple & BIT(INNER_DST_IP) ?
4452 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4453
4454 fs->h_u.usr_ip4_spec.tos = rule->tuples.ip_tos;
4455 fs->m_u.usr_ip4_spec.tos =
4456 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4457 0 : rule->tuples_mask.ip_tos;
4458
4459 fs->h_u.usr_ip4_spec.proto = rule->tuples.ip_proto;
4460 fs->m_u.usr_ip4_spec.proto =
4461 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4462 0 : rule->tuples_mask.ip_proto;
4463
4464 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
4465
4466 break;
4467 case SCTP_V6_FLOW:
4468 case TCP_V6_FLOW:
4469 case UDP_V6_FLOW:
4470 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6src,
4471 rule->tuples.src_ip, 4);
4472 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4473 memset(fs->m_u.tcp_ip6_spec.ip6src, 0, sizeof(int) * 4);
4474 else
4475 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6src,
4476 rule->tuples_mask.src_ip, 4);
4477
4478 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6dst,
4479 rule->tuples.dst_ip, 4);
4480 if (rule->unused_tuple & BIT(INNER_DST_IP))
4481 memset(fs->m_u.tcp_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4482 else
4483 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6dst,
4484 rule->tuples_mask.dst_ip, 4);
4485
4486 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4487 fs->m_u.tcp_ip6_spec.psrc =
4488 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4489 0 : cpu_to_be16(rule->tuples_mask.src_port);
4490
4491 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4492 fs->m_u.tcp_ip6_spec.pdst =
4493 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4494 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4495
4496 break;
4497 case IPV6_USER_FLOW:
4498 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6src,
4499 rule->tuples.src_ip, 4);
4500 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4501 memset(fs->m_u.usr_ip6_spec.ip6src, 0, sizeof(int) * 4);
4502 else
4503 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6src,
4504 rule->tuples_mask.src_ip, 4);
4505
4506 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6dst,
4507 rule->tuples.dst_ip, 4);
4508 if (rule->unused_tuple & BIT(INNER_DST_IP))
4509 memset(fs->m_u.usr_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4510 else
4511 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6dst,
4512 rule->tuples_mask.dst_ip, 4);
4513
4514 fs->h_u.usr_ip6_spec.l4_proto = rule->tuples.ip_proto;
4515 fs->m_u.usr_ip6_spec.l4_proto =
4516 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4517 0 : rule->tuples_mask.ip_proto;
4518
4519 break;
4520 case ETHER_FLOW:
4521 ether_addr_copy(fs->h_u.ether_spec.h_source,
4522 rule->tuples.src_mac);
4523 if (rule->unused_tuple & BIT(INNER_SRC_MAC))
4524 eth_zero_addr(fs->m_u.ether_spec.h_source);
4525 else
4526 ether_addr_copy(fs->m_u.ether_spec.h_source,
4527 rule->tuples_mask.src_mac);
4528
4529 ether_addr_copy(fs->h_u.ether_spec.h_dest,
4530 rule->tuples.dst_mac);
4531 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4532 eth_zero_addr(fs->m_u.ether_spec.h_dest);
4533 else
4534 ether_addr_copy(fs->m_u.ether_spec.h_dest,
4535 rule->tuples_mask.dst_mac);
4536
4537 fs->h_u.ether_spec.h_proto =
4538 cpu_to_be16(rule->tuples.ether_proto);
4539 fs->m_u.ether_spec.h_proto =
4540 rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
4541 0 : cpu_to_be16(rule->tuples_mask.ether_proto);
4542
4543 break;
4544 default:
4545 return -EOPNOTSUPP;
4546 }
4547
4548 if (fs->flow_type & FLOW_EXT) {
4549 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
4550 fs->m_ext.vlan_tci =
4551 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
4552 cpu_to_be16(VLAN_VID_MASK) :
4553 cpu_to_be16(rule->tuples_mask.vlan_tag1);
4554 }
4555
4556 if (fs->flow_type & FLOW_MAC_EXT) {
4557 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
4558 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4559 eth_zero_addr(fs->m_u.ether_spec.h_dest);
4560 else
4561 ether_addr_copy(fs->m_u.ether_spec.h_dest,
4562 rule->tuples_mask.dst_mac);
4563 }
4564
4565 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4566 fs->ring_cookie = RX_CLS_FLOW_DISC;
4567 } else {
4568 u64 vf_id;
4569
4570 fs->ring_cookie = rule->queue_id;
4571 vf_id = rule->vf_id;
4572 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
4573 fs->ring_cookie |= vf_id;
4574 }
4575
4576 return 0;
4577}
4578
4579static int hclge_get_all_rules(struct hnae3_handle *handle,
4580 struct ethtool_rxnfc *cmd, u32 *rule_locs)
4581{
4582 struct hclge_vport *vport = hclge_get_vport(handle);
4583 struct hclge_dev *hdev = vport->back;
4584 struct hclge_fd_rule *rule;
4585 struct hlist_node *node2;
4586 int cnt = 0;
4587
4588 if (!hnae3_dev_fd_supported(hdev))
4589 return -EOPNOTSUPP;
4590
4591 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4592
4593 hlist_for_each_entry_safe(rule, node2,
4594 &hdev->fd_rule_list, rule_node) {
4595 if (cnt == cmd->rule_cnt)
4596 return -EMSGSIZE;
4597
4598 rule_locs[cnt] = rule->location;
4599 cnt++;
4600 }
4601
4602 cmd->rule_cnt = cnt;
4603
4604 return 0;
4605}
4606
d1f04a80
JS		 4607static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
4608{
4609 struct hclge_vport *vport = hclge_get_vport(handle);
4610 struct hclge_dev *hdev = vport->back;
4611
4612 hdev->fd_cfg.fd_en = enable;
4613 if (!enable)
4614 hclge_del_all_fd_entries(handle, false);
4615 else
4616 hclge_restore_fd_entries(handle);
4617}
4618
46a3df9f
S		 4619static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
4620{
4621 struct hclge_desc desc;
d44f9b63
YL		 4622 struct hclge_config_mac_mode_cmd *req =
4623 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 4624 u32 loop_en = 0;
46a3df9f
S		 4625 int ret;
4626
4627 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
ccc23ef3
PL		 4628 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
4629 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
4630 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
4631 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
4632 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
4633 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
4634 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
4635 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
4636 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
4637 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
4638 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
4639 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
4640 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
4641 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 4642 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 4643
4644 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4645 if (ret)
4646 dev_err(&hdev->pdev->dev,
4647 "mac enable fail, ret =%d.\n", ret);
4648}
4649
67b8c316 4650static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 4651{
c39c4d98 4652 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 4653 struct hclge_desc desc;
4654 u32 loop_en;
4655 int ret;
4656
e67d9ce9
YL		 4657 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
4658 /* 1 Read out the MAC mode config at first */
4659 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
4660 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4661 if (ret) {
4662 dev_err(&hdev->pdev->dev,
4663 "mac loopback get fail, ret =%d.\n", ret);
4664 return ret;
4665 }
c39c4d98 4666
e67d9ce9
YL		 4667 /* 2 Then setup the loopback flag */
4668 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
ccc23ef3 4669 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
3ebc5e0b
YL		 4670 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
4671 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
e67d9ce9
YL		 4672
4673 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 4674
e67d9ce9
YL		 4675 /* 3 Config mac work mode with loopback flag
4676 * and its original configure parameters
4677 */
4678 hclge_cmd_reuse_desc(&desc, false);
4679 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4680 if (ret)
4681 dev_err(&hdev->pdev->dev,
4682 "mac loopback set fail, ret =%d.\n", ret);
4683 return ret;
4684}
c39c4d98 4685
86957272
FL		 4686static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
4687 enum hnae3_loop loop_mode)
e006bb00
PL		 4688{
4689#define HCLGE_SERDES_RETRY_MS 10
4690#define HCLGE_SERDES_RETRY_NUM 100
4691 struct hclge_serdes_lb_cmd *req;
4692 struct hclge_desc desc;
4693 int ret, i = 0;
86957272 4694 u8 loop_mode_b;
e006bb00 4695
855f03fb 4696 req = (struct hclge_serdes_lb_cmd *)desc.data;
e006bb00
PL		 4697 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
4698
86957272
FL		 4699 switch (loop_mode) {
4700 case HNAE3_LOOP_SERIAL_SERDES:
4701 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
4702 break;
4703 case HNAE3_LOOP_PARALLEL_SERDES:
4704 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
4705 break;
4706 default:
4707 dev_err(&hdev->pdev->dev,
4708 "unsupported serdes loopback mode %d\n", loop_mode);
4709 return -ENOTSUPP;
4710 }
4711
e006bb00 4712 if (en) {
86957272
FL		 4713 req->enable = loop_mode_b;
4714 req->mask = loop_mode_b;
e006bb00 4715 } else {
86957272 4716 req->mask = loop_mode_b;
e006bb00
PL		 4717 }
4718
4719 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4720 if (ret) {
4721 dev_err(&hdev->pdev->dev,
4722 "serdes loopback set fail, ret = %d\n", ret);
4723 return ret;
4724 }
4725
4726 do {
4727 msleep(HCLGE_SERDES_RETRY_MS);
4728 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
4729 true);
4730 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4731 if (ret) {
4732 dev_err(&hdev->pdev->dev,
4733 "serdes loopback get, ret = %d\n", ret);
4734 return ret;
4735 }
4736 } while (++i < HCLGE_SERDES_RETRY_NUM &&
4737 !(req->result & HCLGE_CMD_SERDES_DONE_B));
4738
4739 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
4740 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
4741 return -EBUSY;
4742 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
4743 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
4744 return -EIO;
4745 }
4746
3ebc5e0b 4747 hclge_cfg_mac_mode(hdev, en);
e006bb00
PL		 4748 return 0;
4749}
4750
3ebc5e0b
YL		 4751static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
4752 int stream_id, bool enable)
4753{
4754 struct hclge_desc desc;
4755 struct hclge_cfg_com_tqp_queue_cmd *req =
4756 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
4757 int ret;
4758
4759 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
4760 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
4761 req->stream_id = cpu_to_le16(stream_id);
4762 req->enable |= enable << HCLGE_TQP_ENABLE_B;
4763
4764 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4765 if (ret)
4766 dev_err(&hdev->pdev->dev,
4767 "Tqp enable fail, status =%d.\n", ret);
4768 return ret;
4769}
4770
e67d9ce9
YL		 4771static int hclge_set_loopback(struct hnae3_handle *handle,
4772 enum hnae3_loop loop_mode, bool en)
4773{
4774 struct hclge_vport *vport = hclge_get_vport(handle);
4775 struct hclge_dev *hdev = vport->back;
3ebc5e0b 4776 int i, ret;
e67d9ce9
YL		 4777
4778 switch (loop_mode) {
67b8c316
FL		 4779 case HNAE3_LOOP_APP:
4780 ret = hclge_set_app_loopback(hdev, en);
c39c4d98 4781 break;
86957272
FL		 4782 case HNAE3_LOOP_SERIAL_SERDES:
4783 case HNAE3_LOOP_PARALLEL_SERDES:
4784 ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
e006bb00 4785 break;
c39c4d98
YL		 4786 default:
4787 ret = -ENOTSUPP;
4788 dev_err(&hdev->pdev->dev,
4789 "loop_mode %d is not supported\n", loop_mode);
4790 break;
4791 }
4792
3ebc5e0b
YL		 4793 for (i = 0; i < vport->alloc_tqps; i++) {
4794 ret = hclge_tqp_enable(hdev, i, 0, en);
4795 if (ret)
4796 return ret;
4797 }
46a3df9f 4798
3ebc5e0b 4799 return 0;
46a3df9f
S		 4800}
4801
4802static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
4803{
4804 struct hclge_vport *vport = hclge_get_vport(handle);
4805 struct hnae3_queue *queue;
4806 struct hclge_tqp *tqp;
4807 int i;
4808
4809 for (i = 0; i < vport->alloc_tqps; i++) {
4810 queue = handle->kinfo.tqp[i];
4811 tqp = container_of(queue, struct hclge_tqp, q);
4812 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
4813 }
4814}
4815
4816static int hclge_ae_start(struct hnae3_handle *handle)
4817{
4818 struct hclge_vport *vport = hclge_get_vport(handle);
4819 struct hclge_dev *hdev = vport->back;
dda6b7d5 4820 int i;
46a3df9f 4821
e5e89cda
PL		 4822 for (i = 0; i < vport->alloc_tqps; i++)
4823 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 4824
46a3df9f
S		 4825 /* mac enable */
4826 hclge_cfg_mac_mode(hdev, true);
4827 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 4828 mod_timer(&hdev->service_timer, jiffies + HZ);
3ae84019 4829 hdev->hw.mac.link = 0;
46a3df9f 4830
f9637cc2
PL		 4831 /* reset tqp stats */
4832 hclge_reset_tqp_stats(handle);
4833
dda6b7d5 4834 hclge_mac_start_phy(hdev);
46a3df9f 4835
46a3df9f
S		 4836 return 0;
4837}
4838
4839static void hclge_ae_stop(struct hnae3_handle *handle)
4840{
4841 struct hclge_vport *vport = hclge_get_vport(handle);
4842 struct hclge_dev *hdev = vport->back;
e5e89cda 4843 int i;
46a3df9f 4844
4ee3e5a8
FL		 4845 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4846
f9637cc2
PL		 4847 del_timer_sync(&hdev->service_timer);
4848 cancel_work_sync(&hdev->service_task);
42b11ab7 4849 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
f9637cc2 4850
4486f5c9
YL		 4851 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
4852 hclge_mac_stop_phy(hdev);
f9637cc2 4853 return;
4486f5c9 4854 }
f9637cc2 4855
e5e89cda
PL		 4856 for (i = 0; i < vport->alloc_tqps; i++)
4857 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 4858
46a3df9f
S		 4859 /* Mac disable */
4860 hclge_cfg_mac_mode(hdev, false);
4861
4862 hclge_mac_stop_phy(hdev);
4863
4864 /* reset tqp stats */
4865 hclge_reset_tqp_stats(handle);
b91fb71c
FL		 4866 del_timer_sync(&hdev->service_timer);
4867 cancel_work_sync(&hdev->service_task);
4868 hclge_update_link_status(hdev);
46a3df9f
S		 4869}
4870
4871static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
4872 u16 cmdq_resp, u8 resp_code,
4873 enum hclge_mac_vlan_tbl_opcode op)
4874{
4875 struct hclge_dev *hdev = vport->back;
4876 int return_status = -EIO;
4877
4878 if (cmdq_resp) {
4879 dev_err(&hdev->pdev->dev,
4880 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
4881 cmdq_resp);
4882 return -EIO;
4883 }
4884
4885 if (op == HCLGE_MAC_VLAN_ADD) {
4886 if ((!resp_code) || (resp_code == 1)) {
4887 return_status = 0;
4888 } else if (resp_code == 2) {
2f894c5b 4889 return_status = -ENOSPC;
46a3df9f
S		 4890 dev_err(&hdev->pdev->dev,
4891 "add mac addr failed for uc_overflow.\n");
4892 } else if (resp_code == 3) {
2f894c5b 4893 return_status = -ENOSPC;
46a3df9f
S		 4894 dev_err(&hdev->pdev->dev,
4895 "add mac addr failed for mc_overflow.\n");
4896 } else {
4897 dev_err(&hdev->pdev->dev,
4898 "add mac addr failed for undefined, code=%d.\n",
4899 resp_code);
4900 }
4901 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
4902 if (!resp_code) {
4903 return_status = 0;
4904 } else if (resp_code == 1) {
2f894c5b 4905 return_status = -ENOENT;
46a3df9f
S		 4906 dev_dbg(&hdev->pdev->dev,
4907 "remove mac addr failed for miss.\n");
4908 } else {
4909 dev_err(&hdev->pdev->dev,
4910 "remove mac addr failed for undefined, code=%d.\n",
4911 resp_code);
4912 }
4913 } else if (op == HCLGE_MAC_VLAN_LKUP) {
4914 if (!resp_code) {
4915 return_status = 0;
4916 } else if (resp_code == 1) {
2f894c5b 4917 return_status = -ENOENT;
46a3df9f
S		 4918 dev_dbg(&hdev->pdev->dev,
4919 "lookup mac addr failed for miss.\n");
4920 } else {
4921 dev_err(&hdev->pdev->dev,
4922 "lookup mac addr failed for undefined, code=%d.\n",
4923 resp_code);
4924 }
4925 } else {
2f894c5b 4926 return_status = -EINVAL;
46a3df9f
S		 4927 dev_err(&hdev->pdev->dev,
4928 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
4929 op);
4930 }
4931
4932 return return_status;
4933}
4934
4935static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
4936{
4937 int word_num;
4938 int bit_num;
4939
4940 if (vfid > 255 || vfid < 0)
4941 return -EIO;
4942
4943 if (vfid >= 0 && vfid <= 191) {
4944 word_num = vfid / 32;
4945 bit_num = vfid % 32;
4946 if (clr)
a90bb9a5 4947 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 4948 else
a90bb9a5 4949 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 4950 } else {
4951 word_num = (vfid - 192) / 32;
4952 bit_num = vfid % 32;
4953 if (clr)
a90bb9a5 4954 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 4955 else
a90bb9a5 4956 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 4957 }
4958
4959 return 0;
4960}
4961
4962static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
4963{
4964#define HCLGE_DESC_NUMBER 3
4965#define HCLGE_FUNC_NUMBER_PER_DESC 6
4966 int i, j;
4967
4968 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
4969 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
4970 if (desc[i].data[j])
4971 return false;
4972
4973 return true;
4974}
4975
d44f9b63 4976static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 4977 const u8 *addr)
4978{
4979 const unsigned char *mac_addr = addr;
4980 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
4981 (mac_addr[0]) | (mac_addr[1] << 8);
4982 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
4983
4984 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
4985 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
4986}
4987
46a3df9f 4988static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4989 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 4990{
4991 struct hclge_dev *hdev = vport->back;
4992 struct hclge_desc desc;
4993 u8 resp_code;
a90bb9a5 4994 u16 retval;
46a3df9f
S		 4995 int ret;
4996
4997 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4998
d44f9b63 4999 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5000
5001 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5002 if (ret) {
5003 dev_err(&hdev->pdev->dev,
5004 "del mac addr failed for cmd_send, ret =%d.\n",
5005 ret);
5006 return ret;
5007 }
a90bb9a5
YL		 5008 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5009 retval = le16_to_cpu(desc.retval);
46a3df9f 5010
a90bb9a5 5011 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 5012 HCLGE_MAC_VLAN_REMOVE);
5013}
5014
5015static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5016 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 5017 struct hclge_desc *desc,
5018 bool is_mc)
5019{
5020 struct hclge_dev *hdev = vport->back;
5021 u8 resp_code;
a90bb9a5 5022 u16 retval;
46a3df9f
S		 5023 int ret;
5024
5025 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
5026 if (is_mc) {
5027 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5028 memcpy(desc[0].data,
5029 req,
d44f9b63 5030 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5031 hclge_cmd_setup_basic_desc(&desc[1],
5032 HCLGE_OPC_MAC_VLAN_ADD,
5033 true);
5034 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5035 hclge_cmd_setup_basic_desc(&desc[2],
5036 HCLGE_OPC_MAC_VLAN_ADD,
5037 true);
5038 ret = hclge_cmd_send(&hdev->hw, desc, 3);
5039 } else {
5040 memcpy(desc[0].data,
5041 req,
d44f9b63 5042 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5043 ret = hclge_cmd_send(&hdev->hw, desc, 1);
5044 }
5045 if (ret) {
5046 dev_err(&hdev->pdev->dev,
5047 "lookup mac addr failed for cmd_send, ret =%d.\n",
5048 ret);
5049 return ret;
5050 }
a90bb9a5
YL		 5051 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
5052 retval = le16_to_cpu(desc[0].retval);
46a3df9f 5053
a90bb9a5 5054 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 5055 HCLGE_MAC_VLAN_LKUP);
5056}
5057
5058static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5059 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 5060 struct hclge_desc *mc_desc)
5061{
5062 struct hclge_dev *hdev = vport->back;
5063 int cfg_status;
5064 u8 resp_code;
a90bb9a5 5065 u16 retval;
46a3df9f
S		 5066 int ret;
5067
5068 if (!mc_desc) {
5069 struct hclge_desc desc;
5070
5071 hclge_cmd_setup_basic_desc(&desc,
5072 HCLGE_OPC_MAC_VLAN_ADD,
5073 false);
d44f9b63
YL		 5074 memcpy(desc.data, req,
5075 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 5076 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 5077 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5078 retval = le16_to_cpu(desc.retval);
5079
5080 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 5081 resp_code,
5082 HCLGE_MAC_VLAN_ADD);
5083 } else {
c3b6f755 5084 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 5085 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 5086 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 5087 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 5088 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 5089 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
5090 memcpy(mc_desc[0].data, req,
d44f9b63 5091 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 5092 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 5093 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
5094 retval = le16_to_cpu(mc_desc[0].retval);
5095
5096 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 5097 resp_code,
5098 HCLGE_MAC_VLAN_ADD);
5099 }
5100
5101 if (ret) {
5102 dev_err(&hdev->pdev->dev,
5103 "add mac addr failed for cmd_send, ret =%d.\n",
5104 ret);
5105 return ret;
5106 }
5107
5108 return cfg_status;
5109}
5110
2da5ec58
JS		 5111static int hclge_init_umv_space(struct hclge_dev *hdev)
5112{
5113 u16 allocated_size = 0;
5114 int ret;
5115
5116 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size,
5117 true);
5118 if (ret)
5119 return ret;
5120
5121 if (allocated_size < hdev->wanted_umv_size)
5122 dev_warn(&hdev->pdev->dev,
5123 "Alloc umv space failed, want %d, get %d\n",
5124 hdev->wanted_umv_size, allocated_size);
5125
5126 mutex_init(&hdev->umv_mutex);
5127 hdev->max_umv_size = allocated_size;
5128 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_req_vfs + 2);
5129 hdev->share_umv_size = hdev->priv_umv_size +
5130 hdev->max_umv_size % (hdev->num_req_vfs + 2);
5131
5132 return 0;
5133}
5134
5135static int hclge_uninit_umv_space(struct hclge_dev *hdev)
5136{
5137 int ret;
5138
5139 if (hdev->max_umv_size > 0) {
5140 ret = hclge_set_umv_space(hdev, hdev->max_umv_size, NULL,
5141 false);
5142 if (ret)
5143 return ret;
5144 hdev->max_umv_size = 0;
5145 }
5146 mutex_destroy(&hdev->umv_mutex);
5147
5148 return 0;
5149}
5150
5151static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
5152 u16 *allocated_size, bool is_alloc)
5153{
5154 struct hclge_umv_spc_alc_cmd *req;
5155 struct hclge_desc desc;
5156 int ret;
5157
5158 req = (struct hclge_umv_spc_alc_cmd *)desc.data;
5159 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
5160 hnae3_set_bit(req->allocate, HCLGE_UMV_SPC_ALC_B, !is_alloc);
5161 req->space_size = cpu_to_le32(space_size);
5162
5163 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5164 if (ret) {
5165 dev_err(&hdev->pdev->dev,
5166 "%s umv space failed for cmd_send, ret =%d\n",
5167 is_alloc ? "allocate" : "free", ret);
5168 return ret;
5169 }
5170
5171 if (is_alloc && allocated_size)
5172 *allocated_size = le32_to_cpu(desc.data[1]);
5173
5174 return 0;
5175}
5176
5177static void hclge_reset_umv_space(struct hclge_dev *hdev)
5178{
5179 struct hclge_vport *vport;
5180 int i;
5181
5182 for (i = 0; i < hdev->num_alloc_vport; i++) {
5183 vport = &hdev->vport[i];
5184 vport->used_umv_num = 0;
5185 }
5186
5187 mutex_lock(&hdev->umv_mutex);
5188 hdev->share_umv_size = hdev->priv_umv_size +
5189 hdev->max_umv_size % (hdev->num_req_vfs + 2);
5190 mutex_unlock(&hdev->umv_mutex);
5191}
5192
5193static bool hclge_is_umv_space_full(struct hclge_vport *vport)
5194{
5195 struct hclge_dev *hdev = vport->back;
5196 bool is_full;
5197
5198 mutex_lock(&hdev->umv_mutex);
5199 is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
5200 hdev->share_umv_size == 0);
5201 mutex_unlock(&hdev->umv_mutex);
5202
5203 return is_full;
5204}
5205
5206static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
5207{
5208 struct hclge_dev *hdev = vport->back;
5209
5210 mutex_lock(&hdev->umv_mutex);
5211 if (is_free) {
5212 if (vport->used_umv_num > hdev->priv_umv_size)
5213 hdev->share_umv_size++;
5214 vport->used_umv_num--;
5215 } else {
5216 if (vport->used_umv_num >= hdev->priv_umv_size)
5217 hdev->share_umv_size--;
5218 vport->used_umv_num++;
5219 }
5220 mutex_unlock(&hdev->umv_mutex);
5221}
5222
46a3df9f
S		 5223static int hclge_add_uc_addr(struct hnae3_handle *handle,
5224 const unsigned char *addr)
5225{
5226 struct hclge_vport *vport = hclge_get_vport(handle);
5227
5228 return hclge_add_uc_addr_common(vport, addr);
5229}
5230
5231int hclge_add_uc_addr_common(struct hclge_vport *vport,
5232 const unsigned char *addr)
5233{
5234 struct hclge_dev *hdev = vport->back;
d44f9b63 5235 struct hclge_mac_vlan_tbl_entry_cmd req;
bf88f41f 5236 struct hclge_desc desc;
a90bb9a5 5237 u16 egress_port = 0;
04f0c72a 5238 int ret;
46a3df9f
S		 5239
5240 /* mac addr check */
5241 if (is_zero_ether_addr(addr) ||
5242 is_broadcast_ether_addr(addr) ||
5243 is_multicast_ether_addr(addr)) {
5244 dev_err(&hdev->pdev->dev,
5245 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
5246 addr,
5247 is_zero_ether_addr(addr),
5248 is_broadcast_ether_addr(addr),
5249 is_multicast_ether_addr(addr));
5250 return -EINVAL;
5251 }
5252
5253 memset(&req, 0, sizeof(req));
ccc23ef3 5254 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 5255
ccc23ef3
PL		 5256 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
5257 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 5258
5259 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 5260
5261 hclge_prepare_mac_addr(&req, addr);
5262
bf88f41f
JS		 5263 /* Lookup the mac address in the mac_vlan table, and add
5264 * it if the entry is inexistent. Repeated unicast entry
5265 * is not allowed in the mac vlan table.
5266 */
5267 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
2da5ec58
JS		 5268 if (ret == -ENOENT) {
5269 if (!hclge_is_umv_space_full(vport)) {
5270 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
5271 if (!ret)
5272 hclge_update_umv_space(vport, false);
5273 return ret;
5274 }
5275
5276 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
5277 hdev->priv_umv_size);
5278
5279 return -ENOSPC;
5280 }
bf88f41f
JS		 5281
5282 /* check if we just hit the duplicate */
5283 if (!ret)
5284 ret = -EINVAL;
5285
5286 dev_err(&hdev->pdev->dev,
5287 "PF failed to add unicast entry(%pM) in the MAC table\n",
5288 addr);
46a3df9f 5289
04f0c72a 5290 return ret;
46a3df9f
S		 5291}
5292
5293static int hclge_rm_uc_addr(struct hnae3_handle *handle,
5294 const unsigned char *addr)
5295{
5296 struct hclge_vport *vport = hclge_get_vport(handle);
5297
5298 return hclge_rm_uc_addr_common(vport, addr);
5299}
5300
5301int hclge_rm_uc_addr_common(struct hclge_vport *vport,
5302 const unsigned char *addr)
5303{
5304 struct hclge_dev *hdev = vport->back;
d44f9b63 5305 struct hclge_mac_vlan_tbl_entry_cmd req;
04f0c72a 5306 int ret;
46a3df9f
S		 5307
5308 /* mac addr check */
5309 if (is_zero_ether_addr(addr) ||
5310 is_broadcast_ether_addr(addr) ||
5311 is_multicast_ether_addr(addr)) {
5312 dev_dbg(&hdev->pdev->dev,
5313 "Remove mac err! invalid mac:%pM.\n",
5314 addr);
5315 return -EINVAL;
5316 }
5317
5318 memset(&req, 0, sizeof(req));
ccc23ef3
PL		 5319 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5320 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 5321 hclge_prepare_mac_addr(&req, addr);
04f0c72a 5322 ret = hclge_remove_mac_vlan_tbl(vport, &req);
2da5ec58
JS		 5323 if (!ret)
5324 hclge_update_umv_space(vport, true);
46a3df9f 5325
04f0c72a 5326 return ret;
46a3df9f
S		 5327}
5328
5329static int hclge_add_mc_addr(struct hnae3_handle *handle,
5330 const unsigned char *addr)
5331{
5332 struct hclge_vport *vport = hclge_get_vport(handle);
5333
2bf8098b 5334 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 5335}
5336
5337int hclge_add_mc_addr_common(struct hclge_vport *vport,
5338 const unsigned char *addr)
5339{
5340 struct hclge_dev *hdev = vport->back;
d44f9b63 5341 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 5342 struct hclge_desc desc[3];
46a3df9f
S		 5343 int status;
5344
5345 /* mac addr check */
5346 if (!is_multicast_ether_addr(addr)) {
5347 dev_err(&hdev->pdev->dev,
5348 "Add mc mac err! invalid mac:%pM.\n",
5349 addr);
5350 return -EINVAL;
5351 }
5352 memset(&req, 0, sizeof(req));
ccc23ef3
PL		 5353 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5354 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5355 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
738a3401 5356 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 5357 hclge_prepare_mac_addr(&req, addr);
5358 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5359 if (!status) {
5360 /* This mac addr exist, update VFID for it */
5361 hclge_update_desc_vfid(desc, vport->vport_id, false);
5362 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5363 } else {
5364 /* This mac addr do not exist, add new entry for it */
5365 memset(desc[0].data, 0, sizeof(desc[0].data));
5366 memset(desc[1].data, 0, sizeof(desc[0].data));
5367 memset(desc[2].data, 0, sizeof(desc[0].data));
5368 hclge_update_desc_vfid(desc, vport->vport_id, false);
5369 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5370 }
5371
55b049be
JS		 5372 if (status == -ENOSPC)
5373 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
46a3df9f
S		 5374
5375 return status;
5376}
5377
5378static int hclge_rm_mc_addr(struct hnae3_handle *handle,
5379 const unsigned char *addr)
5380{
5381 struct hclge_vport *vport = hclge_get_vport(handle);
5382
5383 return hclge_rm_mc_addr_common(vport, addr);
5384}
5385
5386int hclge_rm_mc_addr_common(struct hclge_vport *vport,
5387 const unsigned char *addr)
5388{
5389 struct hclge_dev *hdev = vport->back;
d44f9b63 5390 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 5391 enum hclge_cmd_status status;
5392 struct hclge_desc desc[3];
46a3df9f
S		 5393
5394 /* mac addr check */
5395 if (!is_multicast_ether_addr(addr)) {
5396 dev_dbg(&hdev->pdev->dev,
5397 "Remove mc mac err! invalid mac:%pM.\n",
5398 addr);
5399 return -EINVAL;
5400 }
5401
5402 memset(&req, 0, sizeof(req));
ccc23ef3
PL		 5403 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5404 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5405 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
738a3401 5406 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 5407 hclge_prepare_mac_addr(&req, addr);
5408 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5409 if (!status) {
5410 /* This mac addr exist, remove this handle's VFID for it */
5411 hclge_update_desc_vfid(desc, vport->vport_id, true);
5412
5413 if (hclge_is_all_function_id_zero(desc))
5414 /* All the vfid is zero, so need to delete this entry */
5415 status = hclge_remove_mac_vlan_tbl(vport, &req);
5416 else
5417 /* Not all the vfid is zero, update the vfid */
5418 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5419
5420 } else {
a832d8b5
XW		 5421 /* Maybe this mac address is in mta table, but it cannot be
5422 * deleted here because an entry of mta represents an address
5423 * range rather than a specific address. the delete action to
5424 * all entries will take effect in update_mta_status called by
5425 * hns3_nic_set_rx_mode.
5426 */
5427 status = 0;
46a3df9f
S		 5428 }
5429
46a3df9f
S		 5430 return status;
5431}
5432
635bfb58
FL		 5433static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
5434 u16 cmdq_resp, u8 resp_code)
5435{
5436#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
5437#define HCLGE_ETHERTYPE_ALREADY_ADD 1
5438#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
5439#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
5440
5441 int return_status;
5442
5443 if (cmdq_resp) {
5444 dev_err(&hdev->pdev->dev,
5445 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
5446 cmdq_resp);
5447 return -EIO;
5448 }
5449
5450 switch (resp_code) {
5451 case HCLGE_ETHERTYPE_SUCCESS_ADD:
5452 case HCLGE_ETHERTYPE_ALREADY_ADD:
5453 return_status = 0;
5454 break;
5455 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
5456 dev_err(&hdev->pdev->dev,
5457 "add mac ethertype failed for manager table overflow.\n");
5458 return_status = -EIO;
5459 break;
5460 case HCLGE_ETHERTYPE_KEY_CONFLICT:
5461 dev_err(&hdev->pdev->dev,
5462 "add mac ethertype failed for key conflict.\n");
5463 return_status = -EIO;
5464 break;
5465 default:
5466 dev_err(&hdev->pdev->dev,
5467 "add mac ethertype failed for undefined, code=%d.\n",
5468 resp_code);
5469 return_status = -EIO;
5470 }
5471
5472 return return_status;
5473}
5474
5475static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
5476 const struct hclge_mac_mgr_tbl_entry_cmd *req)
5477{
5478 struct hclge_desc desc;
5479 u8 resp_code;
5480 u16 retval;
5481 int ret;
5482
5483 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
5484 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
5485
5486 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5487 if (ret) {
5488 dev_err(&hdev->pdev->dev,
5489 "add mac ethertype failed for cmd_send, ret =%d.\n",
5490 ret);
5491 return ret;
5492 }
5493
5494 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5495 retval = le16_to_cpu(desc.retval);
5496
5497 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
5498}
5499
5500static int init_mgr_tbl(struct hclge_dev *hdev)
5501{
5502 int ret;
5503 int i;
5504
5505 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
5506 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
5507 if (ret) {
5508 dev_err(&hdev->pdev->dev,
5509 "add mac ethertype failed, ret =%d.\n",
5510 ret);
5511 return ret;
5512 }
5513 }
5514
5515 return 0;
5516}
5517
46a3df9f
S		 5518static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
5519{
5520 struct hclge_vport *vport = hclge_get_vport(handle);
5521 struct hclge_dev *hdev = vport->back;
5522
5523 ether_addr_copy(p, hdev->hw.mac.mac_addr);
5524}
5525
3cbf5e2d
FL		 5526static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
5527 bool is_first)
46a3df9f
S		 5528{
5529 const unsigned char *new_addr = (const unsigned char *)p;
5530 struct hclge_vport *vport = hclge_get_vport(handle);
5531 struct hclge_dev *hdev = vport->back;
20a5c4c0 5532 int ret;
46a3df9f
S		 5533
5534 /* mac addr check */
5535 if (is_zero_ether_addr(new_addr) ||
5536 is_broadcast_ether_addr(new_addr) ||
5537 is_multicast_ether_addr(new_addr)) {
5538 dev_err(&hdev->pdev->dev,
5539 "Change uc mac err! invalid mac:%p.\n",
5540 new_addr);
5541 return -EINVAL;
5542 }
5543
3cbf5e2d 5544 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 5545 dev_warn(&hdev->pdev->dev,
3cbf5e2d 5546 "remove old uc mac address fail.\n");
46a3df9f 5547
20a5c4c0
FL		 5548 ret = hclge_add_uc_addr(handle, new_addr);
5549 if (ret) {
5550 dev_err(&hdev->pdev->dev,
5551 "add uc mac address fail, ret =%d.\n",
5552 ret);
5553
3cbf5e2d
FL		 5554 if (!is_first &&
5555 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 5556 dev_err(&hdev->pdev->dev,
3cbf5e2d 5557 "restore uc mac address fail.\n");
20a5c4c0
FL		 5558
5559 return -EIO;
46a3df9f
S		 5560 }
5561
532fdd5e 5562 ret = hclge_pause_addr_cfg(hdev, new_addr);
20a5c4c0
FL		 5563 if (ret) {
5564 dev_err(&hdev->pdev->dev,
5565 "configure mac pause address fail, ret =%d.\n",
5566 ret);
5567 return -EIO;
5568 }
5569
5570 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
5571
5572 return 0;
46a3df9f
S		 5573}
5574
a185d723
XW		 5575static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
5576 int cmd)
5577{
5578 struct hclge_vport *vport = hclge_get_vport(handle);
5579 struct hclge_dev *hdev = vport->back;
5580
5581 if (!hdev->hw.mac.phydev)
5582 return -EOPNOTSUPP;
5583
5584 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
5585}
5586
46a3df9f 5587static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
0e44d430 5588 u8 fe_type, bool filter_en)
46a3df9f 5589{
d44f9b63 5590 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 5591 struct hclge_desc desc;
5592 int ret;
5593
5594 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
5595
d44f9b63 5596 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f 5597 req->vlan_type = vlan_type;
0e44d430 5598 req->vlan_fe = filter_en ? fe_type : 0;
46a3df9f
S		 5599
5600 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 5601 if (ret)
46a3df9f
S		 5602 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
5603 ret);
46a3df9f 5604
90415e85 5605 return ret;
46a3df9f
S		 5606}
5607
d818396d
JS		 5608#define HCLGE_FILTER_TYPE_VF 0
5609#define HCLGE_FILTER_TYPE_PORT 1
0e44d430
ZL		 5610#define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0)
5611#define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0)
5612#define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1)
5613#define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2)
5614#define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3)
5615#define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \
5616 | HCLGE_FILTER_FE_ROCE_EGRESS_B)
5617#define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \
5618 | HCLGE_FILTER_FE_ROCE_INGRESS_B)
d818396d
JS		 5619
5620static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
5621{
5622 struct hclge_vport *vport = hclge_get_vport(handle);
5623 struct hclge_dev *hdev = vport->back;
5624
0e44d430
ZL		 5625 if (hdev->pdev->revision >= 0x21) {
5626 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5627 HCLGE_FILTER_FE_EGRESS, enable);
5628 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
5629 HCLGE_FILTER_FE_INGRESS, enable);
5630 } else {
5631 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5632 HCLGE_FILTER_FE_EGRESS_V1_B, enable);
5633 }
1e3653db
JS		 5634 if (enable)
5635 handle->netdev_flags |= HNAE3_VLAN_FLTR;
5636 else
5637 handle->netdev_flags &= ~HNAE3_VLAN_FLTR;
d818396d
JS		 5638}
5639
4e66632d
YL		 5640static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
5641 bool is_kill, u16 vlan, u8 qos,
5642 __be16 proto)
46a3df9f
S		 5643{
5644#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 5645 struct hclge_vlan_filter_vf_cfg_cmd *req0;
5646 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 5647 struct hclge_desc desc[2];
5648 u8 vf_byte_val;
5649 u8 vf_byte_off;
5650 int ret;
5651
5652 hclge_cmd_setup_basic_desc(&desc[0],
5653 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
5654 hclge_cmd_setup_basic_desc(&desc[1],
5655 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
5656
5657 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5658
5659 vf_byte_off = vfid / 8;
5660 vf_byte_val = 1 << (vfid % 8);
5661
d44f9b63
YL		 5662 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
5663 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 5664
a90bb9a5 5665 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 5666 req0->vlan_cfg = is_kill;
5667
5668 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
5669 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
5670 else
5671 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
5672
5673 ret = hclge_cmd_send(&hdev->hw, desc, 2);
5674 if (ret) {
5675 dev_err(&hdev->pdev->dev,
5676 "Send vf vlan command fail, ret =%d.\n",
5677 ret);
5678 return ret;
5679 }
5680
5681 if (!is_kill) {
715d610d 5682#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 5683 if (!req0->resp_code || req0->resp_code == 1)
5684 return 0;
5685
715d610d
YL		 5686 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
5687 dev_warn(&hdev->pdev->dev,
5688 "vf vlan table is full, vf vlan filter is disabled\n");
5689 return 0;
5690 }
5691
46a3df9f
S		 5692 dev_err(&hdev->pdev->dev,
5693 "Add vf vlan filter fail, ret =%d.\n",
5694 req0->resp_code);
5695 } else {
29d3a843 5696#define HCLGE_VF_VLAN_DEL_NO_FOUND 1
46a3df9f
S		 5697 if (!req0->resp_code)
5698 return 0;
5699
29d3a843
YL		 5700 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
5701 dev_warn(&hdev->pdev->dev,
5702 "vlan %d filter is not in vf vlan table\n",
5703 vlan);
5704 return 0;
5705 }
5706
46a3df9f
S		 5707 dev_err(&hdev->pdev->dev,
5708 "Kill vf vlan filter fail, ret =%d.\n",
5709 req0->resp_code);
5710 }
5711
5712 return -EIO;
5713}
5714
4e66632d
YL		 5715static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
5716 u16 vlan_id, bool is_kill)
46a3df9f 5717{
d44f9b63 5718 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 5719 struct hclge_desc desc;
5720 u8 vlan_offset_byte_val;
5721 u8 vlan_offset_byte;
5722 u8 vlan_offset_160;
5723 int ret;
5724
5725 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
5726
5727 vlan_offset_160 = vlan_id / 160;
5728 vlan_offset_byte = (vlan_id % 160) / 8;
5729 vlan_offset_byte_val = 1 << (vlan_id % 8);
5730
d44f9b63 5731 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 5732 req->vlan_offset = vlan_offset_160;
5733 req->vlan_cfg = is_kill;
5734 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
5735
5736 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4e66632d
YL		 5737 if (ret)
5738 dev_err(&hdev->pdev->dev,
5739 "port vlan command, send fail, ret =%d.\n", ret);
5740 return ret;
5741}
5742
5743static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
5744 u16 vport_id, u16 vlan_id, u8 qos,
5745 bool is_kill)
5746{
5747 u16 vport_idx, vport_num = 0;
5748 int ret;
5749
4935129c
YL		 5750 if (is_kill && !vlan_id)
5751 return 0;
5752
4e66632d
YL		 5753 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
5754 0, proto);
46a3df9f
S		 5755 if (ret) {
5756 dev_err(&hdev->pdev->dev,
4e66632d
YL		 5757 "Set %d vport vlan filter config fail, ret =%d.\n",
5758 vport_id, ret);
46a3df9f
S		 5759 return ret;
5760 }
5761
4e66632d
YL		 5762 /* vlan 0 may be added twice when 8021q module is enabled */
5763 if (!is_kill && !vlan_id &&
5764 test_bit(vport_id, hdev->vlan_table[vlan_id]))
5765 return 0;
5766
5767 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 5768 dev_err(&hdev->pdev->dev,
4e66632d
YL		 5769 "Add port vlan failed, vport %d is already in vlan %d\n",
5770 vport_id, vlan_id);
5771 return -EINVAL;
46a3df9f
S		 5772 }
5773
4e66632d
YL		 5774 if (is_kill &&
5775 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
5776 dev_err(&hdev->pdev->dev,
5777 "Delete port vlan failed, vport %d is not in vlan %d\n",
5778 vport_id, vlan_id);
5779 return -EINVAL;
5780 }
5781
3c6d4f43 5782 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
4e66632d
YL		 5783 vport_num++;
5784
5785 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
5786 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
5787 is_kill);
5788
5789 return ret;
5790}
5791
5792int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
5793 u16 vlan_id, bool is_kill)
5794{
5795 struct hclge_vport *vport = hclge_get_vport(handle);
5796 struct hclge_dev *hdev = vport->back;
5797
5798 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
5799 0, is_kill);
46a3df9f
S		 5800}
5801
5802static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
5803 u16 vlan, u8 qos, __be16 proto)
5804{
5805 struct hclge_vport *vport = hclge_get_vport(handle);
5806 struct hclge_dev *hdev = vport->back;
5807
5808 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
5809 return -EINVAL;
5810 if (proto != htons(ETH_P_8021Q))
5811 return -EPROTONOSUPPORT;
5812
4e66632d 5813 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 5814}
5815
e62f2a6b
PL		 5816static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
5817{
5818 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
5819 struct hclge_vport_vtag_tx_cfg_cmd *req;
5820 struct hclge_dev *hdev = vport->back;
5821 struct hclge_desc desc;
5822 int status;
5823
5824 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
5825
5826 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
5827 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
5828 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
ccc23ef3
PL		 5829 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
5830 vcfg->accept_tag1 ? 1 : 0);
5831 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
5832 vcfg->accept_untag1 ? 1 : 0);
5833 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
5834 vcfg->accept_tag2 ? 1 : 0);
5835 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
5836 vcfg->accept_untag2 ? 1 : 0);
5837 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
5838 vcfg->insert_tag1_en ? 1 : 0);
5839 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
5840 vcfg->insert_tag2_en ? 1 : 0);
5841 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
e62f2a6b
PL		 5842
5843 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
5844 req->vf_bitmap[req->vf_offset] =
5845 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
5846
5847 status = hclge_cmd_send(&hdev->hw, &desc, 1);
5848 if (status)
5849 dev_err(&hdev->pdev->dev,
5850 "Send port txvlan cfg command fail, ret =%d\n",
5851 status);
5852
5853 return status;
5854}
5855
5856static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
5857{
5858 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
5859 struct hclge_vport_vtag_rx_cfg_cmd *req;
5860 struct hclge_dev *hdev = vport->back;
5861 struct hclge_desc desc;
5862 int status;
5863
5864 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
5865
5866 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
ccc23ef3
PL		 5867 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
5868 vcfg->strip_tag1_en ? 1 : 0);
5869 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
5870 vcfg->strip_tag2_en ? 1 : 0);
5871 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
5872 vcfg->vlan1_vlan_prionly ? 1 : 0);
5873 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
5874 vcfg->vlan2_vlan_prionly ? 1 : 0);
e62f2a6b
PL		 5875
5876 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
5877 req->vf_bitmap[req->vf_offset] =
5878 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
5879
5880 status = hclge_cmd_send(&hdev->hw, &desc, 1);
5881 if (status)
5882 dev_err(&hdev->pdev->dev,
5883 "Send port rxvlan cfg command fail, ret =%d\n",
5884 status);
5885
5886 return status;
5887}
5888
5889static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
5890{
5891 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
5892 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
5893 struct hclge_desc desc;
5894 int status;
5895
5896 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
5897 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
5898 rx_req->ot_fst_vlan_type =
5899 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
5900 rx_req->ot_sec_vlan_type =
5901 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
5902 rx_req->in_fst_vlan_type =
5903 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
5904 rx_req->in_sec_vlan_type =
5905 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
5906
5907 status = hclge_cmd_send(&hdev->hw, &desc, 1);
5908 if (status) {
5909 dev_err(&hdev->pdev->dev,
5910 "Send rxvlan protocol type command fail, ret =%d\n",
5911 status);
5912 return status;
5913 }
5914
5915 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
5916
855f03fb 5917 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
e62f2a6b
PL		 5918 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
5919 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
5920
5921 status = hclge_cmd_send(&hdev->hw, &desc, 1);
5922 if (status)
5923 dev_err(&hdev->pdev->dev,
5924 "Send txvlan protocol type command fail, ret =%d\n",
5925 status);
5926
5927 return status;
5928}
5929
46a3df9f
S		 5930static int hclge_init_vlan_config(struct hclge_dev *hdev)
5931{
e62f2a6b
PL		 5932#define HCLGE_DEF_VLAN_TYPE 0x8100
5933
1e3653db 5934 struct hnae3_handle *handle = &hdev->vport[0].nic;
e62f2a6b 5935 struct hclge_vport *vport;
46a3df9f 5936 int ret;
e62f2a6b
PL		 5937 int i;
5938
0e44d430
ZL		 5939 if (hdev->pdev->revision >= 0x21) {
5940 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5941 HCLGE_FILTER_FE_EGRESS, true);
5942 if (ret)
5943 return ret;
46a3df9f 5944
0e44d430
ZL		 5945 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
5946 HCLGE_FILTER_FE_INGRESS, true);
5947 if (ret)
5948 return ret;
5949 } else {
5950 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5951 HCLGE_FILTER_FE_EGRESS_V1_B,
5952 true);
5953 if (ret)
5954 return ret;
5955 }
46a3df9f 5956
1e3653db
JS		 5957 handle->netdev_flags |= HNAE3_VLAN_FLTR;
5958
e62f2a6b
PL		 5959 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
5960 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
5961 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
5962 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
5963 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
5964 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
5965
5966 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 5967 if (ret)
5968 return ret;
46a3df9f 5969
e62f2a6b
PL		 5970 for (i = 0; i < hdev->num_alloc_vport; i++) {
5971 vport = &hdev->vport[i];
b75b1a56
PL		 5972 vport->txvlan_cfg.accept_tag1 = true;
5973 vport->txvlan_cfg.accept_untag1 = true;
5974
5975 /* accept_tag2 and accept_untag2 are not supported on
5976 * pdev revision(0x20), new revision support them. The
5977 * value of this two fields will not return error when driver
5978 * send command to fireware in revision(0x20).
5979 * This two fields can not configured by user.
5980 */
5981 vport->txvlan_cfg.accept_tag2 = true;
5982 vport->txvlan_cfg.accept_untag2 = true;
5983
e62f2a6b
PL		 5984 vport->txvlan_cfg.insert_tag1_en = false;
5985 vport->txvlan_cfg.insert_tag2_en = false;
5986 vport->txvlan_cfg.default_tag1 = 0;
5987 vport->txvlan_cfg.default_tag2 = 0;
5988
5989 ret = hclge_set_vlan_tx_offload_cfg(vport);
5990 if (ret)
5991 return ret;
5992
5993 vport->rxvlan_cfg.strip_tag1_en = false;
5994 vport->rxvlan_cfg.strip_tag2_en = true;
5995 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
5996 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
5997
5998 ret = hclge_set_vlan_rx_offload_cfg(vport);
5999 if (ret)
6000 return ret;
6001 }
6002
4e66632d 6003 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 6004}
6005
3849d494 6006int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
5f9a7732
PL		 6007{
6008 struct hclge_vport *vport = hclge_get_vport(handle);
6009
6010 vport->rxvlan_cfg.strip_tag1_en = false;
6011 vport->rxvlan_cfg.strip_tag2_en = enable;
6012 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6013 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6014
6015 return hclge_set_vlan_rx_offload_cfg(vport);
6016}
6017
12341881 6018static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 6019{
d44f9b63 6020 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 6021 struct hclge_desc desc;
7393ed39 6022 int max_frm_size;
46a3df9f
S		 6023 int ret;
6024
7393ed39
FL		 6025 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
6026
6027 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
6028 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 6029 return -EINVAL;
6030
7393ed39
FL		 6031 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
6032
46a3df9f
S		 6033 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
6034
d44f9b63 6035 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
7393ed39 6036 req->max_frm_size = cpu_to_le16(max_frm_size);
b86fdbf3 6037 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
46a3df9f
S		 6038
6039 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 6040 if (ret)
46a3df9f 6041 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
90415e85
JS		 6042 else
6043 hdev->mps = max_frm_size;
930ff2f6 6044
90415e85 6045 return ret;
46a3df9f
S		 6046}
6047
12341881
FL		 6048static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
6049{
6050 struct hclge_vport *vport = hclge_get_vport(handle);
6051 struct hclge_dev *hdev = vport->back;
6052 int ret;
6053
6054 ret = hclge_set_mac_mtu(hdev, new_mtu);
6055 if (ret) {
6056 dev_err(&hdev->pdev->dev,
6057 "Change mtu fail, ret =%d\n", ret);
6058 return ret;
6059 }
6060
6061 ret = hclge_buffer_alloc(hdev);
6062 if (ret)
6063 dev_err(&hdev->pdev->dev,
6064 "Allocate buffer fail, ret =%d\n", ret);
6065
6066 return ret;
6067}
6068
46a3df9f
S		 6069static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
6070 bool enable)
6071{
d44f9b63 6072 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 6073 struct hclge_desc desc;
6074 int ret;
6075
6076 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
6077
d44f9b63 6078 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 6079 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
ccc23ef3 6080 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 6081
6082 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6083 if (ret) {
6084 dev_err(&hdev->pdev->dev,
6085 "Send tqp reset cmd error, status =%d\n", ret);
6086 return ret;
6087 }
6088
6089 return 0;
6090}
6091
6092static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
6093{
d44f9b63 6094 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 6095 struct hclge_desc desc;
6096 int ret;
6097
6098 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
6099
d44f9b63 6100 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 6101 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6102
6103 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6104 if (ret) {
6105 dev_err(&hdev->pdev->dev,
6106 "Get reset status error, status =%d\n", ret);
6107 return ret;
6108 }
6109
ccc23ef3 6110 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 6111}
6112
e5e89cda
PL		 6113static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
6114 u16 queue_id)
6115{
6116 struct hnae3_queue *queue;
6117 struct hclge_tqp *tqp;
6118
6119 queue = handle->kinfo.tqp[queue_id];
6120 tqp = container_of(queue, struct hclge_tqp, q);
6121
6122 return tqp->index;
6123}
6124
abe62a63 6125int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 6126{
6127 struct hclge_vport *vport = hclge_get_vport(handle);
6128 struct hclge_dev *hdev = vport->back;
6129 int reset_try_times = 0;
6130 int reset_status;
e5e89cda 6131 u16 queue_gid;
abe62a63 6132 int ret = 0;
46a3df9f 6133
e5e89cda
PL		 6134 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
6135
46a3df9f
S		 6136 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
6137 if (ret) {
abe62a63
HT		 6138 dev_err(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
6139 return ret;
46a3df9f
S		 6140 }
6141
e5e89cda 6142 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f 6143 if (ret) {
abe62a63
HT		 6144 dev_err(&hdev->pdev->dev,
6145 "Send reset tqp cmd fail, ret = %d\n", ret);
6146 return ret;
46a3df9f
S		 6147 }
6148
6149 reset_try_times = 0;
6150 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6151 /* Wait for tqp hw reset */
6152 msleep(20);
e5e89cda 6153 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 6154 if (reset_status)
6155 break;
6156 }
6157
6158 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
abe62a63
HT		 6159 dev_err(&hdev->pdev->dev, "Reset TQP fail\n");
6160 return ret;
46a3df9f
S		 6161 }
6162
e5e89cda 6163 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
abe62a63
HT		 6164 if (ret)
6165 dev_err(&hdev->pdev->dev,
6166 "Deassert the soft reset fail, ret = %d\n", ret);
6167
6168 return ret;
46a3df9f
S		 6169}
6170
d3ea7fc4
PL		 6171void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
6172{
6173 struct hclge_dev *hdev = vport->back;
6174 int reset_try_times = 0;
6175 int reset_status;
6176 u16 queue_gid;
6177 int ret;
6178
6179 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
6180
6181 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6182 if (ret) {
6183 dev_warn(&hdev->pdev->dev,
6184 "Send reset tqp cmd fail, ret = %d\n", ret);
6185 return;
6186 }
6187
6188 reset_try_times = 0;
6189 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6190 /* Wait for tqp hw reset */
6191 msleep(20);
6192 reset_status = hclge_get_reset_status(hdev, queue_gid);
6193 if (reset_status)
6194 break;
6195 }
6196
6197 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6198 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
6199 return;
6200 }
6201
6202 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6203 if (ret)
6204 dev_warn(&hdev->pdev->dev,
6205 "Deassert the soft reset fail, ret = %d\n", ret);
6206}
6207
46a3df9f
S		 6208static u32 hclge_get_fw_version(struct hnae3_handle *handle)
6209{
6210 struct hclge_vport *vport = hclge_get_vport(handle);
6211 struct hclge_dev *hdev = vport->back;
6212
6213 return hdev->fw_version;
6214}
6215
09ea401e
PL		 6216static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6217{
6218 struct phy_device *phydev = hdev->hw.mac.phydev;
6219
6220 if (!phydev)
6221 return;
6222
6223 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
6224
6225 if (rx_en)
6226 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
6227
6228 if (tx_en)
6229 phydev->advertising ^= ADVERTISED_Asym_Pause;
6230}
6231
6232static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6233{
09ea401e
PL		 6234 int ret;
6235
6236 if (rx_en && tx_en)
7a28a82a 6237 hdev->fc_mode_last_time = HCLGE_FC_FULL;
09ea401e 6238 else if (rx_en && !tx_en)
7a28a82a 6239 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
09ea401e 6240 else if (!rx_en && tx_en)
7a28a82a 6241 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
09ea401e 6242 else
7a28a82a 6243 hdev->fc_mode_last_time = HCLGE_FC_NONE;
09ea401e 6244
7a28a82a 6245 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
09ea401e 6246 return 0;
09ea401e
PL		 6247
6248 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
6249 if (ret) {
6250 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
6251 ret);
6252 return ret;
6253 }
6254
7a28a82a 6255 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
09ea401e
PL		 6256
6257 return 0;
6258}
6259
6282f2ea
PL		 6260int hclge_cfg_flowctrl(struct hclge_dev *hdev)
6261{
6262 struct phy_device *phydev = hdev->hw.mac.phydev;
6263 u16 remote_advertising = 0;
6264 u16 local_advertising = 0;
6265 u32 rx_pause, tx_pause;
6266 u8 flowctl;
6267
6268 if (!phydev->link || !phydev->autoneg)
6269 return 0;
6270
6271 if (phydev->advertising & ADVERTISED_Pause)
6272 local_advertising = ADVERTISE_PAUSE_CAP;
6273
6274 if (phydev->advertising & ADVERTISED_Asym_Pause)
6275 local_advertising |= ADVERTISE_PAUSE_ASYM;
6276
6277 if (phydev->pause)
6278 remote_advertising = LPA_PAUSE_CAP;
6279
6280 if (phydev->asym_pause)
6281 remote_advertising |= LPA_PAUSE_ASYM;
6282
6283 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
6284 remote_advertising);
6285 tx_pause = flowctl & FLOW_CTRL_TX;
6286 rx_pause = flowctl & FLOW_CTRL_RX;
6287
6288 if (phydev->duplex == HCLGE_MAC_HALF) {
6289 tx_pause = 0;
6290 rx_pause = 0;
6291 }
6292
6293 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
6294}
6295
46a3df9f
S		 6296static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
6297 u32 *rx_en, u32 *tx_en)
6298{
6299 struct hclge_vport *vport = hclge_get_vport(handle);
6300 struct hclge_dev *hdev = vport->back;
6301
6302 *auto_neg = hclge_get_autoneg(handle);
6303
6304 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6305 *rx_en = 0;
6306 *tx_en = 0;
6307 return;
6308 }
6309
6310 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
6311 *rx_en = 1;
6312 *tx_en = 0;
6313 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
6314 *tx_en = 1;
6315 *rx_en = 0;
6316 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
6317 *rx_en = 1;
6318 *tx_en = 1;
6319 } else {
6320 *rx_en = 0;
6321 *tx_en = 0;
6322 }
6323}
6324
09ea401e
PL		 6325static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
6326 u32 rx_en, u32 tx_en)
6327{
6328 struct hclge_vport *vport = hclge_get_vport(handle);
6329 struct hclge_dev *hdev = vport->back;
6330 struct phy_device *phydev = hdev->hw.mac.phydev;
6331 u32 fc_autoneg;
6332
09ea401e
PL		 6333 fc_autoneg = hclge_get_autoneg(handle);
6334 if (auto_neg != fc_autoneg) {
6335 dev_info(&hdev->pdev->dev,
6336 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
6337 return -EOPNOTSUPP;
6338 }
6339
6340 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6341 dev_info(&hdev->pdev->dev,
6342 "Priority flow control enabled. Cannot set link flow control.\n");
6343 return -EOPNOTSUPP;
6344 }
6345
6346 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
6347
6348 if (!fc_autoneg)
6349 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
6350
bef24782
FL		 6351 /* Only support flow control negotiation for netdev with
6352 * phy attached for now.
6353 */
6354 if (!phydev)
6355 return -EOPNOTSUPP;
6356
09ea401e
PL		 6357 return phy_start_aneg(phydev);
6358}
6359
46a3df9f
S		 6360static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
6361 u8 *auto_neg, u32 *speed, u8 *duplex)
6362{
6363 struct hclge_vport *vport = hclge_get_vport(handle);
6364 struct hclge_dev *hdev = vport->back;
6365
6366 if (speed)
6367 *speed = hdev->hw.mac.speed;
6368 if (duplex)
6369 *duplex = hdev->hw.mac.duplex;
6370 if (auto_neg)
6371 *auto_neg = hdev->hw.mac.autoneg;
6372}
6373
6374static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
6375{
6376 struct hclge_vport *vport = hclge_get_vport(handle);
6377 struct hclge_dev *hdev = vport->back;
6378
6379 if (media_type)
6380 *media_type = hdev->hw.mac.media_type;
6381}
6382
6383static void hclge_get_mdix_mode(struct hnae3_handle *handle,
6384 u8 *tp_mdix_ctrl, u8 *tp_mdix)
6385{
6386 struct hclge_vport *vport = hclge_get_vport(handle);
6387 struct hclge_dev *hdev = vport->back;
6388 struct phy_device *phydev = hdev->hw.mac.phydev;
6389 int mdix_ctrl, mdix, retval, is_resolved;
6390
6391 if (!phydev) {
6392 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6393 *tp_mdix = ETH_TP_MDI_INVALID;
6394 return;
6395 }
6396
6397 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
6398
6399 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
ccc23ef3
PL		 6400 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
6401 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 6402
6403 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
ccc23ef3
PL		 6404 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
6405 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 6406
6407 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
6408
6409 switch (mdix_ctrl) {
6410 case 0x0:
6411 *tp_mdix_ctrl = ETH_TP_MDI;
6412 break;
6413 case 0x1:
6414 *tp_mdix_ctrl = ETH_TP_MDI_X;
6415 break;
6416 case 0x3:
6417 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
6418 break;
6419 default:
6420 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6421 break;
6422 }
6423
6424 if (!is_resolved)
6425 *tp_mdix = ETH_TP_MDI_INVALID;
6426 else if (mdix)
6427 *tp_mdix = ETH_TP_MDI_X;
6428 else
6429 *tp_mdix = ETH_TP_MDI;
6430}
6431
dda6b7d5
FL		 6432static int hclge_init_instance_hw(struct hclge_dev *hdev)
6433{
6434 return hclge_mac_connect_phy(hdev);
6435}
6436
6437static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
6438{
6439 hclge_mac_disconnect_phy(hdev);
6440}
6441
46a3df9f
S		 6442static int hclge_init_client_instance(struct hnae3_client *client,
6443 struct hnae3_ae_dev *ae_dev)
6444{
6445 struct hclge_dev *hdev = ae_dev->priv;
6446 struct hclge_vport *vport;
6447 int i, ret;
6448
6449 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
6450 vport = &hdev->vport[i];
6451
6452 switch (client->type) {
6453 case HNAE3_CLIENT_KNIC:
6454
6455 hdev->nic_client = client;
6456 vport->nic.client = client;
6457 ret = client->ops->init_instance(&vport->nic);
6458 if (ret)
2f59de78 6459 goto clear_nic;
46a3df9f 6460
dda6b7d5
FL		 6461 ret = hclge_init_instance_hw(hdev);
6462 if (ret) {
6463 client->ops->uninit_instance(&vport->nic,
6464 0);
2f59de78 6465 goto clear_nic;
dda6b7d5
FL		 6466 }
6467
8ed41eeb
JS		 6468 hnae3_set_client_init_flag(client, ae_dev, 1);
6469
46a3df9f 6470 if (hdev->roce_client &&
e92a0843 6471 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 6472 struct hnae3_client *rc = hdev->roce_client;
6473
6474 ret = hclge_init_roce_base_info(vport);
6475 if (ret)
2f59de78 6476 goto clear_roce;
46a3df9f
S		 6477
6478 ret = rc->ops->init_instance(&vport->roce);
6479 if (ret)
2f59de78 6480 goto clear_roce;
8ed41eeb
JS		 6481
6482 hnae3_set_client_init_flag(hdev->roce_client,
6483 ae_dev, 1);
46a3df9f
S		 6484 }
6485
6486 break;
6487 case HNAE3_CLIENT_UNIC:
6488 hdev->nic_client = client;
6489 vport->nic.client = client;
6490
6491 ret = client->ops->init_instance(&vport->nic);
6492 if (ret)
2f59de78 6493 goto clear_nic;
46a3df9f 6494
8ed41eeb
JS		 6495 hnae3_set_client_init_flag(client, ae_dev, 1);
6496
46a3df9f
S		 6497 break;
6498 case HNAE3_CLIENT_ROCE:
e92a0843 6499 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 6500 hdev->roce_client = client;
6501 vport->roce.client = client;
6502 }
6503
3a46f34d 6504 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 6505 ret = hclge_init_roce_base_info(vport);
6506 if (ret)
2f59de78 6507 goto clear_roce;
46a3df9f
S		 6508
6509 ret = client->ops->init_instance(&vport->roce);
6510 if (ret)
2f59de78 6511 goto clear_roce;
8ed41eeb
JS		 6512
6513 hnae3_set_client_init_flag(client, ae_dev, 1);
46a3df9f 6514 }
085920ba
JS		 6515
6516 break;
6517 default:
6518 return -EINVAL;
46a3df9f
S		 6519 }
6520 }
6521
6522 return 0;
2f59de78
JS		 6523
6524clear_nic:
6525 hdev->nic_client = NULL;
6526 vport->nic.client = NULL;
6527 return ret;
6528clear_roce:
6529 hdev->roce_client = NULL;
6530 vport->roce.client = NULL;
6531 return ret;
46a3df9f
S		 6532}
6533
6534static void hclge_uninit_client_instance(struct hnae3_client *client,
6535 struct hnae3_ae_dev *ae_dev)
6536{
6537 struct hclge_dev *hdev = ae_dev->priv;
6538 struct hclge_vport *vport;
6539 int i;
6540
6541 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
6542 vport = &hdev->vport[i];
a17dcf3f 6543 if (hdev->roce_client) {
46a3df9f
S		 6544 hdev->roce_client->ops->uninit_instance(&vport->roce,
6545 0);
a17dcf3f
L		 6546 hdev->roce_client = NULL;
6547 vport->roce.client = NULL;
6548 }
46a3df9f
S		 6549 if (client->type == HNAE3_CLIENT_ROCE)
6550 return;
2f59de78 6551 if (hdev->nic_client && client->ops->uninit_instance) {
dda6b7d5 6552 hclge_uninit_instance_hw(hdev);
46a3df9f 6553 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 6554 hdev->nic_client = NULL;
6555 vport->nic.client = NULL;
6556 }
46a3df9f
S		 6557 }
6558}
6559
6560static int hclge_pci_init(struct hclge_dev *hdev)
6561{
6562 struct pci_dev *pdev = hdev->pdev;
6563 struct hclge_hw *hw;
6564 int ret;
6565
6566 ret = pci_enable_device(pdev);
6567 if (ret) {
6568 dev_err(&pdev->dev, "failed to enable PCI device\n");
6c46284e 6569 return ret;
46a3df9f
S		 6570 }
6571
6572 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6573 if (ret) {
6574 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
6575 if (ret) {
6576 dev_err(&pdev->dev,
6577 "can't set consistent PCI DMA");
6578 goto err_disable_device;
6579 }
6580 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
6581 }
6582
6583 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
6584 if (ret) {
6585 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
6586 goto err_disable_device;
6587 }
6588
6589 pci_set_master(pdev);
6590 hw = &hdev->hw;
46a3df9f
S		 6591 hw->io_base = pcim_iomap(pdev, 2, 0);
6592 if (!hw->io_base) {
6593 dev_err(&pdev->dev, "Can't map configuration register space\n");
6594 ret = -ENOMEM;
6595 goto err_clr_master;
6596 }
6597
709eb41a
L		 6598 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
6599
46a3df9f
S		 6600 return 0;
6601err_clr_master:
6602 pci_clear_master(pdev);
6603 pci_release_regions(pdev);
6604err_disable_device:
6605 pci_disable_device(pdev);
46a3df9f
S		 6606
6607 return ret;
6608}
6609
6610static void hclge_pci_uninit(struct hclge_dev *hdev)
6611{
6612 struct pci_dev *pdev = hdev->pdev;
6613
7d6d639b 6614 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 6615 pci_free_irq_vectors(pdev);
46a3df9f
S		 6616 pci_clear_master(pdev);
6617 pci_release_mem_regions(pdev);
6618 pci_disable_device(pdev);
6619}
6620
2ec3d9f0
PL		 6621static void hclge_state_init(struct hclge_dev *hdev)
6622{
6623 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
6624 set_bit(HCLGE_STATE_DOWN, &hdev->state);
6625 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
6626 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
6627 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
6628 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
6629}
6630
6631static void hclge_state_uninit(struct hclge_dev *hdev)
6632{
6633 set_bit(HCLGE_STATE_DOWN, &hdev->state);
6634
6635 if (hdev->service_timer.function)
6636 del_timer_sync(&hdev->service_timer);
6637 if (hdev->service_task.func)
6638 cancel_work_sync(&hdev->service_task);
6639 if (hdev->rst_service_task.func)
6640 cancel_work_sync(&hdev->rst_service_task);
6641 if (hdev->mbx_service_task.func)
6642 cancel_work_sync(&hdev->mbx_service_task);
6643}
6644
46a3df9f
S		 6645static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
6646{
6647 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 6648 struct hclge_dev *hdev;
6649 int ret;
6650
6651 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
6652 if (!hdev) {
6653 ret = -ENOMEM;
e0027501 6654 goto out;
46a3df9f
S		 6655 }
6656
46a3df9f
S		 6657 hdev->pdev = pdev;
6658 hdev->ae_dev = ae_dev;
4ed340ab 6659 hdev->reset_type = HNAE3_NONE_RESET;
46a3df9f
S		 6660 ae_dev->priv = hdev;
6661
46a3df9f
S		 6662 ret = hclge_pci_init(hdev);
6663 if (ret) {
6664 dev_err(&pdev->dev, "PCI init failed\n");
e0027501 6665 goto out;
46a3df9f
S		 6666 }
6667
3efb960f
L		 6668 /* Firmware command queue initialize */
6669 ret = hclge_cmd_queue_init(hdev);
6670 if (ret) {
6671 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
e0027501 6672 goto err_pci_uninit;
3efb960f
L		 6673 }
6674
6675 /* Firmware command initialize */
46a3df9f
S		 6676 ret = hclge_cmd_init(hdev);
6677 if (ret)
e0027501 6678 goto err_cmd_uninit;
46a3df9f
S		 6679
6680 ret = hclge_get_cap(hdev);
6681 if (ret) {
e00e2197
CIK		 6682 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
6683 ret);
e0027501 6684 goto err_cmd_uninit;
46a3df9f
S		 6685 }
6686
6687 ret = hclge_configure(hdev);
6688 if (ret) {
6689 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
e0027501 6690 goto err_cmd_uninit;
46a3df9f
S		 6691 }
6692
887c3820 6693 ret = hclge_init_msi(hdev);
46a3df9f 6694 if (ret) {
887c3820 6695 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
e0027501 6696 goto err_cmd_uninit;
46a3df9f
S		 6697 }
6698
466b0c00
L		 6699 ret = hclge_misc_irq_init(hdev);
6700 if (ret) {
6701 dev_err(&pdev->dev,
6702 "Misc IRQ(vector0) init error, ret = %d.\n",
6703 ret);
e0027501 6704 goto err_msi_uninit;
466b0c00
L		 6705 }
6706
46a3df9f
S		 6707 ret = hclge_alloc_tqps(hdev);
6708 if (ret) {
6709 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
e0027501 6710 goto err_msi_irq_uninit;
46a3df9f
S		 6711 }
6712
6713 ret = hclge_alloc_vport(hdev);
6714 if (ret) {
6715 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
e0027501 6716 goto err_msi_irq_uninit;
46a3df9f
S		 6717 }
6718
7df7dad6
L		 6719 ret = hclge_map_tqp(hdev);
6720 if (ret) {
6721 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
bc59f827 6722 goto err_msi_irq_uninit;
7df7dad6
L		 6723 }
6724
dea9a821
HT		 6725 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
6726 ret = hclge_mac_mdio_config(hdev);
6727 if (ret) {
6728 dev_err(&hdev->pdev->dev,
6729 "mdio config fail ret=%d\n", ret);
bc59f827 6730 goto err_msi_irq_uninit;
dea9a821 6731 }
cf9cca2d 6732 }
6733
2da5ec58
JS		 6734 ret = hclge_init_umv_space(hdev);
6735 if (ret) {
6736 dev_err(&pdev->dev, "umv space init error, ret=%d.\n", ret);
6737 goto err_msi_irq_uninit;
6738 }
6739
46a3df9f
S		 6740 ret = hclge_mac_init(hdev);
6741 if (ret) {
6742 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
e0027501 6743 goto err_mdiobus_unreg;
46a3df9f 6744 }
46a3df9f
S		 6745
6746 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
6747 if (ret) {
6748 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
e0027501 6749 goto err_mdiobus_unreg;
46a3df9f
S		 6750 }
6751
46a3df9f
S		 6752 ret = hclge_init_vlan_config(hdev);
6753 if (ret) {
6754 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
e0027501 6755 goto err_mdiobus_unreg;
46a3df9f
S		 6756 }
6757
6758 ret = hclge_tm_schd_init(hdev);
6759 if (ret) {
6760 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
e0027501 6761 goto err_mdiobus_unreg;
68ece54e
YL		 6762 }
6763
8015bb74 6764 hclge_rss_init_cfg(hdev);
68ece54e
YL		 6765 ret = hclge_rss_init_hw(hdev);
6766 if (ret) {
6767 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
e0027501 6768 goto err_mdiobus_unreg;
46a3df9f
S		 6769 }
6770
635bfb58
FL		 6771 ret = init_mgr_tbl(hdev);
6772 if (ret) {
6773 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
e0027501 6774 goto err_mdiobus_unreg;
635bfb58
FL		 6775 }
6776
10a954bc
JS		 6777 ret = hclge_init_fd_config(hdev);
6778 if (ret) {
6779 dev_err(&pdev->dev,
6780 "fd table init fail, ret=%d\n", ret);
6781 goto err_mdiobus_unreg;
6782 }
6783
9f53588e
SJ		 6784 ret = hclge_hw_error_set_state(hdev, true);
6785 if (ret) {
6786 dev_err(&pdev->dev,
6787 "hw error interrupts enable failed, ret =%d\n", ret);
6788 goto err_mdiobus_unreg;
6789 }
6790
cacde272
YL		 6791 hclge_dcb_ops_set(hdev);
6792
d039ef68 6793 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 6794 INIT_WORK(&hdev->service_task, hclge_service_task);
ed4a1bb8 6795 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
22fd3468 6796 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 6797
9ab4ad14
XW		 6798 hclge_clear_all_event_cause(hdev);
6799
466b0c00
L		 6800 /* Enable MISC vector(vector0) */
6801 hclge_enable_vector(&hdev->misc_vector, true);
6802
2ec3d9f0 6803 hclge_state_init(hdev);
46a3df9f
S		 6804
6805 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
6806 return 0;
6807
e0027501
HT		 6808err_mdiobus_unreg:
6809 if (hdev->hw.mac.phydev)
6810 mdiobus_unregister(hdev->hw.mac.mdio_bus);
e0027501
HT		 6811err_msi_irq_uninit:
6812 hclge_misc_irq_uninit(hdev);
6813err_msi_uninit:
6814 pci_free_irq_vectors(pdev);
6815err_cmd_uninit:
6816 hclge_destroy_cmd_queue(&hdev->hw);
6817err_pci_uninit:
7d6d639b 6818 pcim_iounmap(pdev, hdev->hw.io_base);
e0027501 6819 pci_clear_master(pdev);
46a3df9f 6820 pci_release_regions(pdev);
e0027501 6821 pci_disable_device(pdev);
e0027501 6822out:
46a3df9f
S		 6823 return ret;
6824}
6825
c6dc5213 6826static void hclge_stats_clear(struct hclge_dev *hdev)
6827{
6828 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
6829}
6830
4ed340ab
L		 6831static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
6832{
6833 struct hclge_dev *hdev = ae_dev->priv;
6834 struct pci_dev *pdev = ae_dev->pdev;
6835 int ret;
6836
6837 set_bit(HCLGE_STATE_DOWN, &hdev->state);
6838
c6dc5213 6839 hclge_stats_clear(hdev);
4e66632d 6840 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 6841
4ed340ab
L		 6842 ret = hclge_cmd_init(hdev);
6843 if (ret) {
6844 dev_err(&pdev->dev, "Cmd queue init failed\n");
6845 return ret;
6846 }
6847
6848 ret = hclge_get_cap(hdev);
6849 if (ret) {
6850 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
6851 ret);
6852 return ret;
6853 }
6854
6855 ret = hclge_configure(hdev);
6856 if (ret) {
6857 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
6858 return ret;
6859 }
6860
6861 ret = hclge_map_tqp(hdev);
6862 if (ret) {
6863 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
6864 return ret;
6865 }
6866
2da5ec58
JS		 6867 hclge_reset_umv_space(hdev);
6868
4ed340ab
L		 6869 ret = hclge_mac_init(hdev);
6870 if (ret) {
6871 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
6872 return ret;
6873 }
6874
4ed340ab
L		 6875 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
6876 if (ret) {
6877 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
6878 return ret;
6879 }
6880
6881 ret = hclge_init_vlan_config(hdev);
6882 if (ret) {
6883 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
6884 return ret;
6885 }
6886
d85f1ab5 6887 ret = hclge_tm_init_hw(hdev);
4ed340ab 6888 if (ret) {
d85f1ab5 6889 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 6890 return ret;
6891 }
6892
6893 ret = hclge_rss_init_hw(hdev);
6894 if (ret) {
6895 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
6896 return ret;
6897 }
6898
10a954bc
JS		 6899 ret = hclge_init_fd_config(hdev);
6900 if (ret) {
6901 dev_err(&pdev->dev,
6902 "fd table init fail, ret=%d\n", ret);
6903 return ret;
6904 }
6905
78807a3d
SJ		 6906 /* Re-enable the TM hw error interrupts because
6907 * they get disabled on core/global reset.
6908 */
6909 if (hclge_enable_tm_hw_error(hdev, true))
6910 dev_err(&pdev->dev, "failed to enable TM hw error interrupts\n");
6911
4ed340ab
L		 6912 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
6913 HCLGE_DRIVER_NAME);
6914
6915 return 0;
6916}
6917
46a3df9f
S		 6918static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
6919{
6920 struct hclge_dev *hdev = ae_dev->priv;
6921 struct hclge_mac *mac = &hdev->hw.mac;
6922
2ec3d9f0 6923 hclge_state_uninit(hdev);
46a3df9f
S		 6924
6925 if (mac->phydev)
6926 mdiobus_unregister(mac->mdio_bus);
6927
2da5ec58
JS		 6928 hclge_uninit_umv_space(hdev);
6929
466b0c00
L		 6930 /* Disable MISC vector(vector0) */
6931 hclge_enable_vector(&hdev->misc_vector, false);
9ab4ad14
XW		 6932 synchronize_irq(hdev->misc_vector.vector_irq);
6933
9f53588e 6934 hclge_hw_error_set_state(hdev, false);
46a3df9f 6935 hclge_destroy_cmd_queue(&hdev->hw);
202f2014 6936 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 6937 hclge_pci_uninit(hdev);
6938 ae_dev->priv = NULL;
6939}
6940
4f645a90
PL		 6941static u32 hclge_get_max_channels(struct hnae3_handle *handle)
6942{
6943 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
6944 struct hclge_vport *vport = hclge_get_vport(handle);
6945 struct hclge_dev *hdev = vport->back;
6946
6947 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
6948}
6949
6950static void hclge_get_channels(struct hnae3_handle *handle,
6951 struct ethtool_channels *ch)
6952{
6953 struct hclge_vport *vport = hclge_get_vport(handle);
6954
6955 ch->max_combined = hclge_get_max_channels(handle);
6956 ch->other_count = 1;
6957 ch->max_other = 1;
6958 ch->combined_count = vport->alloc_tqps;
6959}
6960
f1f779ce 6961static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
08ca3d58 6962 u16 *alloc_tqps, u16 *max_rss_size)
f1f779ce
PL		 6963{
6964 struct hclge_vport *vport = hclge_get_vport(handle);
6965 struct hclge_dev *hdev = vport->back;
f1f779ce 6966
08ca3d58 6967 *alloc_tqps = vport->alloc_tqps;
f1f779ce
PL		 6968 *max_rss_size = hdev->rss_size_max;
6969}
6970
6971static void hclge_release_tqp(struct hclge_vport *vport)
6972{
6973 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
6974 struct hclge_dev *hdev = vport->back;
6975 int i;
6976
6977 for (i = 0; i < kinfo->num_tqps; i++) {
6978 struct hclge_tqp *tqp =
6979 container_of(kinfo->tqp[i], struct hclge_tqp, q);
6980
6981 tqp->q.handle = NULL;
6982 tqp->q.tqp_index = 0;
6983 tqp->alloced = false;
6984 }
6985
6986 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
6987 kinfo->tqp = NULL;
6988}
6989
6990static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
6991{
6992 struct hclge_vport *vport = hclge_get_vport(handle);
6993 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
6994 struct hclge_dev *hdev = vport->back;
6995 int cur_rss_size = kinfo->rss_size;
6996 int cur_tqps = kinfo->num_tqps;
6997 u16 tc_offset[HCLGE_MAX_TC_NUM];
6998 u16 tc_valid[HCLGE_MAX_TC_NUM];
6999 u16 tc_size[HCLGE_MAX_TC_NUM];
7000 u16 roundup_size;
7001 u32 *rss_indir;
7002 int ret, i;
7003
f73c9107 7004 /* Free old tqps, and reallocate with new tqp number when nic setup */
f1f779ce
PL		 7005 hclge_release_tqp(vport);
7006
81356b1f 7007 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
f1f779ce
PL		 7008 if (ret) {
7009 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
7010 return ret;
7011 }
7012
7013 ret = hclge_map_tqp_to_vport(hdev, vport);
7014 if (ret) {
7015 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
7016 return ret;
7017 }
7018
7019 ret = hclge_tm_schd_init(hdev);
7020 if (ret) {
7021 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
7022 return ret;
7023 }
7024
7025 roundup_size = roundup_pow_of_two(kinfo->rss_size);
7026 roundup_size = ilog2(roundup_size);
7027 /* Set the RSS TC mode according to the new RSS size */
7028 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
7029 tc_valid[i] = 0;
7030
7031 if (!(hdev->hw_tc_map & BIT(i)))
7032 continue;
7033
7034 tc_valid[i] = 1;
7035 tc_size[i] = roundup_size;
7036 tc_offset[i] = kinfo->rss_size * i;
7037 }
7038 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
7039 if (ret)
7040 return ret;
7041
7042 /* Reinitializes the rss indirect table according to the new RSS size */
7043 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
7044 if (!rss_indir)
7045 return -ENOMEM;
7046
7047 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
7048 rss_indir[i] = i % kinfo->rss_size;
7049
7050 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
7051 if (ret)
7052 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
7053 ret);
7054
7055 kfree(rss_indir);
7056
7057 if (!ret)
7058 dev_info(&hdev->pdev->dev,
7059 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
7060 cur_rss_size, kinfo->rss_size,
7061 cur_tqps, kinfo->rss_size * kinfo->num_tc);
7062
7063 return ret;
7064}
7065
db2a3e43
FL		 7066static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
7067 u32 *regs_num_64_bit)
7068{
7069 struct hclge_desc desc;
7070 u32 total_num;
7071 int ret;
7072
7073 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
7074 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7075 if (ret) {
7076 dev_err(&hdev->pdev->dev,
7077 "Query register number cmd failed, ret = %d.\n", ret);
7078 return ret;
7079 }
7080
7081 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
7082 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
7083
7084 total_num = *regs_num_32_bit + *regs_num_64_bit;
7085 if (!total_num)
7086 return -EINVAL;
7087
7088 return 0;
7089}
7090
7091static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7092 void *data)
7093{
7094#define HCLGE_32_BIT_REG_RTN_DATANUM 8
7095
7096 struct hclge_desc *desc;
7097 u32 *reg_val = data;
7098 __le32 *desc_data;
7099 int cmd_num;
7100 int i, k, n;
7101 int ret;
7102
7103 if (regs_num == 0)
7104 return 0;
7105
7106 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
7107 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7108 if (!desc)
7109 return -ENOMEM;
7110
7111 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
7112 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7113 if (ret) {
7114 dev_err(&hdev->pdev->dev,
7115 "Query 32 bit register cmd failed, ret = %d.\n", ret);
7116 kfree(desc);
7117 return ret;
7118 }
7119
7120 for (i = 0; i < cmd_num; i++) {
7121 if (i == 0) {
7122 desc_data = (__le32 *)(&desc[i].data[0]);
7123 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
7124 } else {
7125 desc_data = (__le32 *)(&desc[i]);
7126 n = HCLGE_32_BIT_REG_RTN_DATANUM;
7127 }
7128 for (k = 0; k < n; k++) {
7129 *reg_val++ = le32_to_cpu(*desc_data++);
7130
7131 regs_num--;
7132 if (!regs_num)
7133 break;
7134 }
7135 }
7136
7137 kfree(desc);
7138 return 0;
7139}
7140
7141static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7142 void *data)
7143{
7144#define HCLGE_64_BIT_REG_RTN_DATANUM 4
7145
7146 struct hclge_desc *desc;
7147 u64 *reg_val = data;
7148 __le64 *desc_data;
7149 int cmd_num;
7150 int i, k, n;
7151 int ret;
7152
7153 if (regs_num == 0)
7154 return 0;
7155
7156 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
7157 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7158 if (!desc)
7159 return -ENOMEM;
7160
7161 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
7162 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7163 if (ret) {
7164 dev_err(&hdev->pdev->dev,
7165 "Query 64 bit register cmd failed, ret = %d.\n", ret);
7166 kfree(desc);
7167 return ret;
7168 }
7169
7170 for (i = 0; i < cmd_num; i++) {
7171 if (i == 0) {
7172 desc_data = (__le64 *)(&desc[i].data[0]);
7173 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
7174 } else {
7175 desc_data = (__le64 *)(&desc[i]);
7176 n = HCLGE_64_BIT_REG_RTN_DATANUM;
7177 }
7178 for (k = 0; k < n; k++) {
7179 *reg_val++ = le64_to_cpu(*desc_data++);
7180
7181 regs_num--;
7182 if (!regs_num)
7183 break;
7184 }
7185 }
7186
7187 kfree(desc);
7188 return 0;
7189}
7190
7191static int hclge_get_regs_len(struct hnae3_handle *handle)
7192{
7193 struct hclge_vport *vport = hclge_get_vport(handle);
7194 struct hclge_dev *hdev = vport->back;
7195 u32 regs_num_32_bit, regs_num_64_bit;
7196 int ret;
7197
7198 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7199 if (ret) {
7200 dev_err(&hdev->pdev->dev,
7201 "Get register number failed, ret = %d.\n", ret);
7202 return -EOPNOTSUPP;
7203 }
7204
7205 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
7206}
7207
7208static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
7209 void *data)
7210{
7211 struct hclge_vport *vport = hclge_get_vport(handle);
7212 struct hclge_dev *hdev = vport->back;
7213 u32 regs_num_32_bit, regs_num_64_bit;
7214 int ret;
7215
7216 *version = hdev->fw_version;
7217
7218 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7219 if (ret) {
7220 dev_err(&hdev->pdev->dev,
7221 "Get register number failed, ret = %d.\n", ret);
7222 return;
7223 }
7224
7225 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
7226 if (ret) {
7227 dev_err(&hdev->pdev->dev,
7228 "Get 32 bit register failed, ret = %d.\n", ret);
7229 return;
7230 }
7231
7232 data = (u32 *)data + regs_num_32_bit;
7233 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
7234 data);
7235 if (ret)
7236 dev_err(&hdev->pdev->dev,
7237 "Get 64 bit register failed, ret = %d.\n", ret);
7238}
7239
fe3a3e15 7240static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
d9a0884e
JS		 7241{
7242 struct hclge_set_led_state_cmd *req;
7243 struct hclge_desc desc;
7244 int ret;
7245
7246 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
7247
7248 req = (struct hclge_set_led_state_cmd *)desc.data;
ccc23ef3
PL		 7249 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
7250 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
d9a0884e
JS		 7251
7252 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7253 if (ret)
7254 dev_err(&hdev->pdev->dev,
7255 "Send set led state cmd error, ret =%d\n", ret);
7256
7257 return ret;
7258}
7259
7260enum hclge_led_status {
7261 HCLGE_LED_OFF,
7262 HCLGE_LED_ON,
7263 HCLGE_LED_NO_CHANGE = 0xFF,
7264};
7265
7266static int hclge_set_led_id(struct hnae3_handle *handle,
7267 enum ethtool_phys_id_state status)
7268{
d9a0884e
JS		 7269 struct hclge_vport *vport = hclge_get_vport(handle);
7270 struct hclge_dev *hdev = vport->back;
d9a0884e
JS		 7271
7272 switch (status) {
7273 case ETHTOOL_ID_ACTIVE:
fe3a3e15 7274 return hclge_set_led_status(hdev, HCLGE_LED_ON);
d9a0884e 7275 case ETHTOOL_ID_INACTIVE:
fe3a3e15 7276 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
d9a0884e 7277 default:
fe3a3e15 7278 return -EINVAL;
d9a0884e 7279 }
d9a0884e
JS		 7280}
7281
d92ceae9
FL		 7282static void hclge_get_link_mode(struct hnae3_handle *handle,
7283 unsigned long *supported,
7284 unsigned long *advertising)
7285{
7286 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
7287 struct hclge_vport *vport = hclge_get_vport(handle);
7288 struct hclge_dev *hdev = vport->back;
7289 unsigned int idx = 0;
7290
7291 for (; idx < size; idx++) {
7292 supported[idx] = hdev->hw.mac.supported[idx];
7293 advertising[idx] = hdev->hw.mac.advertising[idx];
7294 }
7295}
7296
46a3df9f
S		 7297static const struct hnae3_ae_ops hclge_ops = {
7298 .init_ae_dev = hclge_init_ae_dev,
7299 .uninit_ae_dev = hclge_uninit_ae_dev,
7300 .init_client_instance = hclge_init_client_instance,
7301 .uninit_client_instance = hclge_uninit_client_instance,
63d7e66f
SM		 7302 .map_ring_to_vector = hclge_map_ring_to_vector,
7303 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 7304 .get_vector = hclge_get_vector,
7412200c 7305 .put_vector = hclge_put_vector,
46a3df9f 7306 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 7307 .set_loopback = hclge_set_loopback,
46a3df9f
S		 7308 .start = hclge_ae_start,
7309 .stop = hclge_ae_stop,
7310 .get_status = hclge_get_status,
7311 .get_ksettings_an_result = hclge_get_ksettings_an_result,
7312 .update_speed_duplex_h = hclge_update_speed_duplex_h,
7313 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
7314 .get_media_type = hclge_get_media_type,
7315 .get_rss_key_size = hclge_get_rss_key_size,
7316 .get_rss_indir_size = hclge_get_rss_indir_size,
7317 .get_rss = hclge_get_rss,
7318 .set_rss = hclge_set_rss,
f7db940a 7319 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 7320 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 7321 .get_tc_size = hclge_get_tc_size,
7322 .get_mac_addr = hclge_get_mac_addr,
7323 .set_mac_addr = hclge_set_mac_addr,
a185d723 7324 .do_ioctl = hclge_do_ioctl,
46a3df9f
S		 7325 .add_uc_addr = hclge_add_uc_addr,
7326 .rm_uc_addr = hclge_rm_uc_addr,
7327 .add_mc_addr = hclge_add_mc_addr,
7328 .rm_mc_addr = hclge_rm_mc_addr,
7329 .set_autoneg = hclge_set_autoneg,
7330 .get_autoneg = hclge_get_autoneg,
7331 .get_pauseparam = hclge_get_pauseparam,
09ea401e 7332 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 7333 .set_mtu = hclge_set_mtu,
7334 .reset_queue = hclge_reset_tqp,
7335 .get_stats = hclge_get_stats,
7336 .update_stats = hclge_update_stats,
7337 .get_strings = hclge_get_strings,
7338 .get_sset_count = hclge_get_sset_count,
7339 .get_fw_version = hclge_get_fw_version,
7340 .get_mdix_mode = hclge_get_mdix_mode,
d818396d 7341 .enable_vlan_filter = hclge_enable_vlan_filter,
4e66632d 7342 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 7343 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5f9a7732 7344 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 7345 .reset_event = hclge_reset_event,
2c883d73 7346 .set_default_reset_request = hclge_set_def_reset_request,
f1f779ce
PL		 7347 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
7348 .set_channels = hclge_set_channels,
4f645a90 7349 .get_channels = hclge_get_channels,
db2a3e43
FL		 7350 .get_regs_len = hclge_get_regs_len,
7351 .get_regs = hclge_get_regs,
d9a0884e 7352 .set_led_id = hclge_set_led_id,
d92ceae9 7353 .get_link_mode = hclge_get_link_mode,
3ca8e27c
JS		 7354 .add_fd_entry = hclge_add_fd_entry,
7355 .del_fd_entry = hclge_del_fd_entry,
7ce98982 7356 .del_all_fd_entries = hclge_del_all_fd_entries,
295043a7
JS		 7357 .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
7358 .get_fd_rule_info = hclge_get_fd_rule_info,
7359 .get_fd_all_rules = hclge_get_all_rules,
7ce98982 7360 .restore_fd_rules = hclge_restore_fd_entries,
d1f04a80 7361 .enable_fd = hclge_enable_fd,
00bb612a 7362 .process_hw_error = hclge_process_ras_hw_error,
46a3df9f
S		 7363};
7364
7365static struct hnae3_ae_algo ae_algo = {
7366 .ops = &hclge_ops,
46a3df9f
S		 7367 .pdev_id_table = ae_algo_pci_tbl,
7368};
7369
7370static int hclge_init(void)
7371{
7372 pr_info("%s is initializing\n", HCLGE_NAME);
7373
a4d090cc
FL		 7374 hnae3_register_ae_algo(&ae_algo);
7375
7376 return 0;
46a3df9f
S		 7377}
7378
7379static void hclge_exit(void)
7380{
7381 hnae3_unregister_ae_algo(&ae_algo);
7382}
7383module_init(hclge_init);
7384module_exit(hclge_exit);
7385
7386MODULE_LICENSE("GPL");
7387MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
7388MODULE_DESCRIPTION("HCLGE Driver");
7389MODULE_VERSION(HCLGE_MOD_VERSION);
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