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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
f2b4a171 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
46a3df9f
S		 9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
7393ed39 20#include <linux/if_vlan.h>
d5752031 21#include <net/rtnetlink.h>
46a3df9f 22#include "hclge_cmd.h"
cacde272 23#include "hclge_dcb.h"
46a3df9f 24#include "hclge_main.h"
0cdbdd3e 25#include "hclge_mbx.h"
46a3df9f
S		 26#include "hclge_mdio.h"
27#include "hclge_tm.h"
28#include "hnae3.h"
29
30#define HCLGE_NAME "hclge"
31#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35
46a3df9f
S		 36static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
37 enum hclge_mta_dmac_sel_type mta_mac_sel,
38 bool enable);
59bc85ec 39static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 40static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 41static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 42
43static struct hnae3_ae_algo ae_algo;
44
45static const struct pci_device_id ae_algo_pci_tbl[] = {
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 53 /* required last entry */
46a3df9f
S		 54 {0, }
55};
56
28d9cec8
YL		 57MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
58
46a3df9f
S		 59static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
60 "Mac Loopback test",
61 "Serdes Loopback test",
62 "Phy Loopback test"
63};
64
65static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
66 {"igu_rx_oversize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
68 {"igu_rx_undersize_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
70 {"igu_rx_out_all_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
72 {"igu_rx_uni_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
74 {"igu_rx_multi_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
76 {"igu_rx_broad_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
78 {"egu_tx_out_all_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
80 {"egu_tx_uni_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
82 {"egu_tx_multi_pkt",
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
84 {"egu_tx_broad_pkt",
85 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
86 {"ssu_ppp_mac_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
88 {"ssu_ppp_host_key_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
90 {"ppp_ssu_mac_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
92 {"ppp_ssu_host_rlt_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
94 {"ssu_tx_in_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
96 {"ssu_tx_out_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
98 {"ssu_rx_in_num",
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
100 {"ssu_rx_out_num",
101 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
102};
103
104static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
105 {"igu_rx_err_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
107 {"igu_rx_no_eof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
109 {"igu_rx_no_sof_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
111 {"egu_tx_1588_pkt",
112 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
113 {"ssu_full_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
115 {"ssu_part_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
117 {"ppp_key_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
119 {"ppp_rlt_drop_num",
120 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
121 {"ssu_key_drop_num",
122 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
123 {"pkt_curr_buf_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
125 {"qcn_fb_rcv_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
127 {"qcn_fb_drop_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
129 {"qcn_fb_invaild_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
131 {"rx_packet_tc0_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
133 {"rx_packet_tc1_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
135 {"rx_packet_tc2_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
137 {"rx_packet_tc3_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
139 {"rx_packet_tc4_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
141 {"rx_packet_tc5_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
143 {"rx_packet_tc6_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
145 {"rx_packet_tc7_in_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
147 {"rx_packet_tc0_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
149 {"rx_packet_tc1_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
151 {"rx_packet_tc2_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
153 {"rx_packet_tc3_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
155 {"rx_packet_tc4_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
157 {"rx_packet_tc5_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
159 {"rx_packet_tc6_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
161 {"rx_packet_tc7_out_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
163 {"tx_packet_tc0_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
165 {"tx_packet_tc1_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
167 {"tx_packet_tc2_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
169 {"tx_packet_tc3_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
171 {"tx_packet_tc4_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
173 {"tx_packet_tc5_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
175 {"tx_packet_tc6_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
177 {"tx_packet_tc7_in_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
179 {"tx_packet_tc0_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
181 {"tx_packet_tc1_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
183 {"tx_packet_tc2_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
185 {"tx_packet_tc3_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
187 {"tx_packet_tc4_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
189 {"tx_packet_tc5_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
191 {"tx_packet_tc6_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
193 {"tx_packet_tc7_out_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
195 {"pkt_curr_buf_tc0_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
197 {"pkt_curr_buf_tc1_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
199 {"pkt_curr_buf_tc2_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
201 {"pkt_curr_buf_tc3_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
203 {"pkt_curr_buf_tc4_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
205 {"pkt_curr_buf_tc5_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
207 {"pkt_curr_buf_tc6_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
209 {"pkt_curr_buf_tc7_cnt",
210 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
211 {"mb_uncopy_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
213 {"lo_pri_unicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
215 {"hi_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
217 {"lo_pri_multicast_rlt_drop_num",
218 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
219 {"rx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
221 {"tx_oq_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
223 {"nic_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
225 {"roc_l2_err_drop_pkt_cnt",
226 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
227};
228
229static const struct hclge_comm_stats_str g_mac_stats_string[] = {
230 {"mac_tx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
232 {"mac_rx_mac_pause_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
234 {"mac_tx_pfc_pri0_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
236 {"mac_tx_pfc_pri1_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
238 {"mac_tx_pfc_pri2_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
240 {"mac_tx_pfc_pri3_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
242 {"mac_tx_pfc_pri4_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
244 {"mac_tx_pfc_pri5_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
246 {"mac_tx_pfc_pri6_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
248 {"mac_tx_pfc_pri7_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
250 {"mac_rx_pfc_pri0_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
252 {"mac_rx_pfc_pri1_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
254 {"mac_rx_pfc_pri2_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
256 {"mac_rx_pfc_pri3_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
258 {"mac_rx_pfc_pri4_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
260 {"mac_rx_pfc_pri5_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
262 {"mac_rx_pfc_pri6_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
264 {"mac_rx_pfc_pri7_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
266 {"mac_tx_total_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
268 {"mac_tx_total_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
270 {"mac_tx_good_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
272 {"mac_tx_bad_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
274 {"mac_tx_good_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
276 {"mac_tx_bad_oct_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
278 {"mac_tx_uni_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
280 {"mac_tx_multi_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
282 {"mac_tx_broad_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
284 {"mac_tx_undersize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
f3426583
JS		 286 {"mac_tx_oversize_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 288 {"mac_tx_64_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
290 {"mac_tx_65_127_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
292 {"mac_tx_128_255_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
294 {"mac_tx_256_511_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
296 {"mac_tx_512_1023_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
298 {"mac_tx_1024_1518_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
b42874e4
JS		 300 {"mac_tx_1519_2047_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
302 {"mac_tx_2048_4095_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
304 {"mac_tx_4096_8191_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
b42874e4
JS		 306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
f3426583
JS		 336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
b42874e4
JS		 350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
b42874e4
JS		 356 {"mac_rx_8192_9216_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
358 {"mac_rx_9217_12287_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
360 {"mac_rx_12288_16383_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
362 {"mac_rx_1519_max_good_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
364 {"mac_rx_1519_max_bad_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 366
c36317be
JS		 367 {"mac_tx_fragment_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
369 {"mac_tx_undermin_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
371 {"mac_tx_jabber_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
373 {"mac_tx_err_all_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
375 {"mac_tx_from_app_good_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
377 {"mac_tx_from_app_bad_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
379 {"mac_rx_fragment_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
381 {"mac_rx_undermin_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
383 {"mac_rx_jabber_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
385 {"mac_rx_fcs_err_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
387 {"mac_rx_send_app_good_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
389 {"mac_rx_send_app_bad_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 391};
392
635bfb58
FL		 393static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
394 {
395 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
396 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
397 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
398 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
399 .i_port_bitmap = 0x1,
400 },
401};
402
46a3df9f
S		 403static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
404{
405#define HCLGE_64_BIT_CMD_NUM 5
406#define HCLGE_64_BIT_RTN_DATANUM 4
407 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
408 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 409 __le64 *desc_data;
46a3df9f
S		 410 int i, k, n;
411 int ret;
412
413 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
414 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
415 if (ret) {
416 dev_err(&hdev->pdev->dev,
417 "Get 64 bit pkt stats fail, status = %d.\n", ret);
418 return ret;
419 }
420
421 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
422 if (unlikely(i == 0)) {
a90bb9a5 423 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 424 n = HCLGE_64_BIT_RTN_DATANUM - 1;
425 } else {
a90bb9a5 426 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 427 n = HCLGE_64_BIT_RTN_DATANUM;
428 }
429 for (k = 0; k < n; k++) {
a90bb9a5 430 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 431 desc_data++;
432 }
433 }
434
435 return 0;
436}
437
438static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
439{
440 stats->pkt_curr_buf_cnt = 0;
441 stats->pkt_curr_buf_tc0_cnt = 0;
442 stats->pkt_curr_buf_tc1_cnt = 0;
443 stats->pkt_curr_buf_tc2_cnt = 0;
444 stats->pkt_curr_buf_tc3_cnt = 0;
445 stats->pkt_curr_buf_tc4_cnt = 0;
446 stats->pkt_curr_buf_tc5_cnt = 0;
447 stats->pkt_curr_buf_tc6_cnt = 0;
448 stats->pkt_curr_buf_tc7_cnt = 0;
449}
450
451static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
452{
453#define HCLGE_32_BIT_CMD_NUM 8
454#define HCLGE_32_BIT_RTN_DATANUM 8
455
456 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
457 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 458 __le32 *desc_data;
46a3df9f
S		 459 int i, k, n;
460 u64 *data;
461 int ret;
462
463 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
464 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
465
466 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
467 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
468 if (ret) {
469 dev_err(&hdev->pdev->dev,
470 "Get 32 bit pkt stats fail, status = %d.\n", ret);
471
472 return ret;
473 }
474
475 hclge_reset_partial_32bit_counter(all_32_bit_stats);
476 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
477 if (unlikely(i == 0)) {
a90bb9a5
YL		 478 __le16 *desc_data_16bit;
479
46a3df9f 480 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 481 le32_to_cpu(desc[i].data[0]);
482
483 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 484 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 485 le16_to_cpu(*desc_data_16bit);
486
487 desc_data_16bit++;
46a3df9f 488 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 489 le16_to_cpu(*desc_data_16bit);
46a3df9f 490
a90bb9a5 491 desc_data = &desc[i].data[2];
46a3df9f
S		 492 n = HCLGE_32_BIT_RTN_DATANUM - 4;
493 } else {
a90bb9a5 494 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 495 n = HCLGE_32_BIT_RTN_DATANUM;
496 }
497 for (k = 0; k < n; k++) {
a90bb9a5 498 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 499 desc_data++;
500 }
501 }
502
503 return 0;
504}
505
506static int hclge_mac_update_stats(struct hclge_dev *hdev)
507{
b42874e4 508#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 509#define HCLGE_RTN_DATA_NUM 4
510
511 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
512 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 513 __le64 *desc_data;
46a3df9f
S		 514 int i, k, n;
515 int ret;
516
517 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
518 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
519 if (ret) {
520 dev_err(&hdev->pdev->dev,
521 "Get MAC pkt stats fail, status = %d.\n", ret);
522
523 return ret;
524 }
525
526 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
527 if (unlikely(i == 0)) {
a90bb9a5 528 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 529 n = HCLGE_RTN_DATA_NUM - 2;
530 } else {
a90bb9a5 531 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 532 n = HCLGE_RTN_DATA_NUM;
533 }
534 for (k = 0; k < n; k++) {
a90bb9a5 535 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 536 desc_data++;
537 }
538 }
539
540 return 0;
541}
542
543static int hclge_tqps_update_stats(struct hnae3_handle *handle)
544{
545 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
546 struct hclge_vport *vport = hclge_get_vport(handle);
547 struct hclge_dev *hdev = vport->back;
548 struct hnae3_queue *queue;
549 struct hclge_desc desc[1];
550 struct hclge_tqp *tqp;
551 int ret, i;
552
553 for (i = 0; i < kinfo->num_tqps; i++) {
554 queue = handle->kinfo.tqp[i];
555 tqp = container_of(queue, struct hclge_tqp, q);
556 /* command : HCLGE_OPC_QUERY_IGU_STAT */
557 hclge_cmd_setup_basic_desc(&desc[0],
558 HCLGE_OPC_QUERY_RX_STATUS,
559 true);
560
a90bb9a5 561 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 562 ret = hclge_cmd_send(&hdev->hw, desc, 1);
563 if (ret) {
564 dev_err(&hdev->pdev->dev,
565 "Query tqp stat fail, status = %d,queue = %d\n",
566 ret, i);
567 return ret;
568 }
569 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 570 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 571 }
572
573 for (i = 0; i < kinfo->num_tqps; i++) {
574 queue = handle->kinfo.tqp[i];
575 tqp = container_of(queue, struct hclge_tqp, q);
576 /* command : HCLGE_OPC_QUERY_IGU_STAT */
577 hclge_cmd_setup_basic_desc(&desc[0],
578 HCLGE_OPC_QUERY_TX_STATUS,
579 true);
580
a90bb9a5 581 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 582 ret = hclge_cmd_send(&hdev->hw, desc, 1);
583 if (ret) {
584 dev_err(&hdev->pdev->dev,
585 "Query tqp stat fail, status = %d,queue = %d\n",
586 ret, i);
587 return ret;
588 }
589 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 590 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 591 }
592
593 return 0;
594}
595
596static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
597{
598 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
599 struct hclge_tqp *tqp;
600 u64 *buff = data;
601 int i;
602
603 for (i = 0; i < kinfo->num_tqps; i++) {
604 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 605 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 606 }
607
608 for (i = 0; i < kinfo->num_tqps; i++) {
609 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 610 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 611 }
612
613 return buff;
614}
615
616static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
617{
618 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
619
620 return kinfo->num_tqps * (2);
621}
622
623static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
624{
625 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
626 u8 *buff = data;
627 int i = 0;
628
629 for (i = 0; i < kinfo->num_tqps; i++) {
630 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
631 struct hclge_tqp, q);
c36317be 632 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
46a3df9f
S		 633 tqp->index);
634 buff = buff + ETH_GSTRING_LEN;
635 }
636
637 for (i = 0; i < kinfo->num_tqps; i++) {
638 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
639 struct hclge_tqp, q);
c36317be 640 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
46a3df9f
S		 641 tqp->index);
642 buff = buff + ETH_GSTRING_LEN;
643 }
644
645 return buff;
646}
647
648static u64 *hclge_comm_get_stats(void *comm_stats,
649 const struct hclge_comm_stats_str strs[],
650 int size, u64 *data)
651{
652 u64 *buf = data;
653 u32 i;
654
655 for (i = 0; i < size; i++)
656 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
657
658 return buf + size;
659}
660
661static u8 *hclge_comm_get_strings(u32 stringset,
662 const struct hclge_comm_stats_str strs[],
663 int size, u8 *data)
664{
665 char *buff = (char *)data;
666 u32 i;
667
668 if (stringset != ETH_SS_STATS)
669 return buff;
670
671 for (i = 0; i < size; i++) {
672 snprintf(buff, ETH_GSTRING_LEN,
673 strs[i].desc);
674 buff = buff + ETH_GSTRING_LEN;
675 }
676
677 return (u8 *)buff;
678}
679
680static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
681 struct net_device_stats *net_stats)
682{
683 net_stats->tx_dropped = 0;
684 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
685 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
686 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
687
f3426583 688 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 689 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
46a3df9f
S		 690 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
691 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
c36317be 692 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 693
694 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
695 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
696
c36317be 697 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 698 net_stats->rx_length_errors =
699 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
700 net_stats->rx_length_errors +=
f3426583 701 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 702 net_stats->rx_over_errors =
f3426583 703 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 704}
705
706static void hclge_update_stats_for_all(struct hclge_dev *hdev)
707{
708 struct hnae3_handle *handle;
709 int status;
710
711 handle = &hdev->vport[0].nic;
712 if (handle->client) {
713 status = hclge_tqps_update_stats(handle);
714 if (status) {
715 dev_err(&hdev->pdev->dev,
716 "Update TQPS stats fail, status = %d.\n",
717 status);
718 }
719 }
720
721 status = hclge_mac_update_stats(hdev);
722 if (status)
723 dev_err(&hdev->pdev->dev,
724 "Update MAC stats fail, status = %d.\n", status);
725
726 status = hclge_32_bit_update_stats(hdev);
727 if (status)
728 dev_err(&hdev->pdev->dev,
729 "Update 32 bit stats fail, status = %d.\n",
730 status);
731
732 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
733}
734
735static void hclge_update_stats(struct hnae3_handle *handle,
736 struct net_device_stats *net_stats)
737{
738 struct hclge_vport *vport = hclge_get_vport(handle);
739 struct hclge_dev *hdev = vport->back;
740 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
741 int status;
742
7a5d2a39
JS		 743 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
744 return;
745
46a3df9f
S		 746 status = hclge_mac_update_stats(hdev);
747 if (status)
748 dev_err(&hdev->pdev->dev,
749 "Update MAC stats fail, status = %d.\n",
750 status);
751
752 status = hclge_32_bit_update_stats(hdev);
753 if (status)
754 dev_err(&hdev->pdev->dev,
755 "Update 32 bit stats fail, status = %d.\n",
756 status);
757
758 status = hclge_64_bit_update_stats(hdev);
759 if (status)
760 dev_err(&hdev->pdev->dev,
761 "Update 64 bit stats fail, status = %d.\n",
762 status);
763
764 status = hclge_tqps_update_stats(handle);
765 if (status)
766 dev_err(&hdev->pdev->dev,
767 "Update TQPS stats fail, status = %d.\n",
768 status);
769
770 hclge_update_netstat(hw_stats, net_stats);
7a5d2a39
JS		 771
772 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 773}
774
775static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
776{
777#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
778
779 struct hclge_vport *vport = hclge_get_vport(handle);
780 struct hclge_dev *hdev = vport->back;
781 int count = 0;
782
783 /* Loopback test support rules:
784 * mac: only GE mode support
785 * serdes: all mac mode will support include GE/XGE/LGE/CGE
786 * phy: only support when phy device exist on board
787 */
788 if (stringset == ETH_SS_TEST) {
789 /* clear loopback bit flags at first */
790 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
791 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
792 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
793 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
794 count += 1;
795 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
300967c5 796 } else {
797 count = -EOPNOTSUPP;
46a3df9f
S		 798 }
799 } else if (stringset == ETH_SS_STATS) {
800 count = ARRAY_SIZE(g_mac_stats_string) +
801 ARRAY_SIZE(g_all_32bit_stats_string) +
802 ARRAY_SIZE(g_all_64bit_stats_string) +
803 hclge_tqps_get_sset_count(handle, stringset);
804 }
805
806 return count;
807}
808
809static void hclge_get_strings(struct hnae3_handle *handle,
810 u32 stringset,
811 u8 *data)
812{
813 u8 *p = (char *)data;
814 int size;
815
816 if (stringset == ETH_SS_STATS) {
817 size = ARRAY_SIZE(g_mac_stats_string);
818 p = hclge_comm_get_strings(stringset,
819 g_mac_stats_string,
820 size,
821 p);
822 size = ARRAY_SIZE(g_all_32bit_stats_string);
823 p = hclge_comm_get_strings(stringset,
824 g_all_32bit_stats_string,
825 size,
826 p);
827 size = ARRAY_SIZE(g_all_64bit_stats_string);
828 p = hclge_comm_get_strings(stringset,
829 g_all_64bit_stats_string,
830 size,
831 p);
832 p = hclge_tqps_get_strings(handle, p);
833 } else if (stringset == ETH_SS_TEST) {
834 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
835 memcpy(p,
836 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
837 ETH_GSTRING_LEN);
838 p += ETH_GSTRING_LEN;
839 }
840 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
841 memcpy(p,
842 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
843 ETH_GSTRING_LEN);
844 p += ETH_GSTRING_LEN;
845 }
846 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
847 memcpy(p,
848 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
849 ETH_GSTRING_LEN);
850 p += ETH_GSTRING_LEN;
851 }
852 }
853}
854
855static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
856{
857 struct hclge_vport *vport = hclge_get_vport(handle);
858 struct hclge_dev *hdev = vport->back;
859 u64 *p;
860
861 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
862 g_mac_stats_string,
863 ARRAY_SIZE(g_mac_stats_string),
864 data);
865 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
866 g_all_32bit_stats_string,
867 ARRAY_SIZE(g_all_32bit_stats_string),
868 p);
869 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
870 g_all_64bit_stats_string,
871 ARRAY_SIZE(g_all_64bit_stats_string),
872 p);
873 p = hclge_tqps_get_stats(handle, p);
874}
875
876static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 877 struct hclge_func_status_cmd *status)
46a3df9f
S		 878{
879 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
880 return -EINVAL;
881
882 /* Set the pf to main pf */
883 if (status->pf_state & HCLGE_PF_STATE_MAIN)
884 hdev->flag |= HCLGE_FLAG_MAIN;
885 else
886 hdev->flag &= ~HCLGE_FLAG_MAIN;
887
46a3df9f
S		 888 return 0;
889}
890
891static int hclge_query_function_status(struct hclge_dev *hdev)
892{
d44f9b63 893 struct hclge_func_status_cmd *req;
46a3df9f
S		 894 struct hclge_desc desc;
895 int timeout = 0;
896 int ret;
897
898 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 899 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 900
901 do {
902 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
903 if (ret) {
904 dev_err(&hdev->pdev->dev,
905 "query function status failed %d.\n",
906 ret);
907
908 return ret;
909 }
910
911 /* Check pf reset is done */
912 if (req->pf_state)
913 break;
914 usleep_range(1000, 2000);
915 } while (timeout++ < 5);
916
917 ret = hclge_parse_func_status(hdev, req);
918
919 return ret;
920}
921
922static int hclge_query_pf_resource(struct hclge_dev *hdev)
923{
d44f9b63 924 struct hclge_pf_res_cmd *req;
46a3df9f
S		 925 struct hclge_desc desc;
926 int ret;
927
928 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
929 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930 if (ret) {
931 dev_err(&hdev->pdev->dev,
932 "query pf resource failed %d.\n", ret);
933 return ret;
934 }
935
d44f9b63 936 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 937 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
938 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
939
e92a0843 940 if (hnae3_dev_roce_supported(hdev)) {
887c3820 941 hdev->num_roce_msi =
928d369a 942 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
943 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 944
945 /* PF should have NIC vectors and Roce vectors,
946 * NIC vectors are queued before Roce vectors.
947 */
887c3820 948 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 949 } else {
950 hdev->num_msi =
928d369a 951 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
952 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 953 }
954
955 return 0;
956}
957
958static int hclge_parse_speed(int speed_cmd, int *speed)
959{
960 switch (speed_cmd) {
961 case 6:
962 *speed = HCLGE_MAC_SPEED_10M;
963 break;
964 case 7:
965 *speed = HCLGE_MAC_SPEED_100M;
966 break;
967 case 0:
968 *speed = HCLGE_MAC_SPEED_1G;
969 break;
970 case 1:
971 *speed = HCLGE_MAC_SPEED_10G;
972 break;
973 case 2:
974 *speed = HCLGE_MAC_SPEED_25G;
975 break;
976 case 3:
977 *speed = HCLGE_MAC_SPEED_40G;
978 break;
979 case 4:
980 *speed = HCLGE_MAC_SPEED_50G;
981 break;
982 case 5:
983 *speed = HCLGE_MAC_SPEED_100G;
984 break;
985 default:
986 return -EINVAL;
987 }
988
989 return 0;
990}
991
d92ceae9
FL		 992static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
993 u8 speed_ability)
994{
995 unsigned long *supported = hdev->hw.mac.supported;
996
997 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
998 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
999 supported);
1000
1001 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1002 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1003 supported);
1004
1005 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1006 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1007 supported);
1008
1009 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1010 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1011 supported);
1012
1013 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1014 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1015 supported);
1016
1017 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
1018 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1019}
1020
1021static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
1022{
1023 u8 media_type = hdev->hw.mac.media_type;
1024
1025 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
1026 return;
1027
1028 hclge_parse_fiber_link_mode(hdev, speed_ability);
1029}
1030
46a3df9f
S		 1031static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1032{
d44f9b63 1033 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1034 u64 mac_addr_tmp_high;
1035 u64 mac_addr_tmp;
1036 int i;
1037
d44f9b63 1038 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 1039
1040 /* get the configuration */
928d369a 1041 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1042 HCLGE_CFG_VMDQ_M,
1043 HCLGE_CFG_VMDQ_S);
1044 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1045 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1046 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1047 HCLGE_CFG_TQP_DESC_N_M,
1048 HCLGE_CFG_TQP_DESC_N_S);
1049
1050 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
1051 HCLGE_CFG_PHY_ADDR_M,
1052 HCLGE_CFG_PHY_ADDR_S);
1053 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
1054 HCLGE_CFG_MEDIA_TP_M,
1055 HCLGE_CFG_MEDIA_TP_S);
1056 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
1057 HCLGE_CFG_RX_BUF_LEN_M,
1058 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 1059 /* get mac_address */
1060 mac_addr_tmp = __le32_to_cpu(req->param[2]);
928d369a 1061 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
1062 HCLGE_CFG_MAC_ADDR_H_M,
1063 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 1064
1065 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1066
928d369a 1067 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
1068 HCLGE_CFG_DEFAULT_SPEED_M,
1069 HCLGE_CFG_DEFAULT_SPEED_S);
1070 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]),
1071 HCLGE_CFG_RSS_SIZE_M,
1072 HCLGE_CFG_RSS_SIZE_S);
c408e202 1073
46a3df9f
S		 1074 for (i = 0; i < ETH_ALEN; i++)
1075 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1076
d44f9b63 1077 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 1078 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
d92ceae9 1079
928d369a 1080 cfg->speed_ability = hnae_get_field(__le32_to_cpu(req->param[1]),
1081 HCLGE_CFG_SPEED_ABILITY_M,
1082 HCLGE_CFG_SPEED_ABILITY_S);
46a3df9f
S		 1083}
1084
1085/* hclge_get_cfg: query the static parameter from flash
1086 * @hdev: pointer to struct hclge_dev
1087 * @hcfg: the config structure to be getted
1088 */
1089static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1090{
1091 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 1092 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1093 int i, ret;
1094
1095 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1096 u32 offset = 0;
1097
d44f9b63 1098 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1099 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1100 true);
928d369a 1101 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
1102 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 1103 /* Len should be united by 4 bytes when send to hardware */
928d369a 1104 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1105 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1106 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1107 }
1108
1109 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1110 if (ret) {
930ff2f6 1111 dev_err(&hdev->pdev->dev,
1112 "get config failed %d.\n", ret);
46a3df9f
S		 1113 return ret;
1114 }
1115
1116 hclge_parse_cfg(hcfg, desc);
1117 return 0;
1118}
1119
1120static int hclge_get_cap(struct hclge_dev *hdev)
1121{
1122 int ret;
1123
1124 ret = hclge_query_function_status(hdev);
1125 if (ret) {
1126 dev_err(&hdev->pdev->dev,
1127 "query function status error %d.\n", ret);
1128 return ret;
1129 }
1130
1131 /* get pf resource */
1132 ret = hclge_query_pf_resource(hdev);
930ff2f6 1133 if (ret) {
1134 dev_err(&hdev->pdev->dev,
1135 "query pf resource error %d.\n", ret);
1136 return ret;
1137 }
46a3df9f 1138
930ff2f6 1139 return 0;
46a3df9f
S		 1140}
1141
1142static int hclge_configure(struct hclge_dev *hdev)
1143{
1144 struct hclge_cfg cfg;
1145 int ret, i;
1146
1147 ret = hclge_get_cfg(hdev, &cfg);
1148 if (ret) {
1149 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1150 return ret;
1151 }
1152
1153 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1154 hdev->base_tqp_pid = 0;
c408e202 1155 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 1156 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1157 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1158 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1159 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1160 hdev->num_desc = cfg.tqp_desc_num;
1161 hdev->tm_info.num_pg = 1;
cacde272 1162 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1163 hdev->tm_info.hw_pfc_map = 0;
1164
1165 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1166 if (ret) {
1167 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1168 return ret;
1169 }
1170
d92ceae9
FL		 1171 hclge_parse_link_mode(hdev, cfg.speed_ability);
1172
cacde272
YL		 1173 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1174 (hdev->tc_max < 1)) {
46a3df9f 1175 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1176 hdev->tc_max);
1177 hdev->tc_max = 1;
46a3df9f
S		 1178 }
1179
cacde272
YL		 1180 /* Dev does not support DCB */
1181 if (!hnae3_dev_dcb_supported(hdev)) {
1182 hdev->tc_max = 1;
1183 hdev->pfc_max = 0;
1184 } else {
1185 hdev->pfc_max = hdev->tc_max;
1186 }
1187
1188 hdev->tm_info.num_tc = hdev->tc_max;
1189
46a3df9f 1190 /* Currently not support uncontiuous tc */
cacde272 1191 for (i = 0; i < hdev->tm_info.num_tc; i++)
928d369a 1192 hnae_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 1193
f8362fe1 1194 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 1195
1196 return ret;
1197}
1198
1199static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1200 int tso_mss_max)
1201{
d44f9b63 1202 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1203 struct hclge_desc desc;
a90bb9a5 1204 u16 tso_mss;
46a3df9f
S		 1205
1206 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1207
d44f9b63 1208 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1209
1210 tso_mss = 0;
928d369a 1211 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1212 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1213 req->tso_mss_min = cpu_to_le16(tso_mss);
1214
1215 tso_mss = 0;
928d369a 1216 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1217 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1218 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1219
1220 return hclge_cmd_send(&hdev->hw, &desc, 1);
1221}
1222
1223static int hclge_alloc_tqps(struct hclge_dev *hdev)
1224{
1225 struct hclge_tqp *tqp;
1226 int i;
1227
1228 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1229 sizeof(struct hclge_tqp), GFP_KERNEL);
1230 if (!hdev->htqp)
1231 return -ENOMEM;
1232
1233 tqp = hdev->htqp;
1234
1235 for (i = 0; i < hdev->num_tqps; i++) {
1236 tqp->dev = &hdev->pdev->dev;
1237 tqp->index = i;
1238
1239 tqp->q.ae_algo = &ae_algo;
1240 tqp->q.buf_size = hdev->rx_buf_len;
1241 tqp->q.desc_num = hdev->num_desc;
1242 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1243 i * HCLGE_TQP_REG_SIZE;
1244
1245 tqp++;
1246 }
1247
1248 return 0;
1249}
1250
1251static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1252 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1253{
d44f9b63 1254 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1255 struct hclge_desc desc;
1256 int ret;
1257
1258 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1259
d44f9b63 1260 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1261 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1262 req->tqp_vf = func_id;
46a3df9f
S		 1263 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1264 1 << HCLGE_TQP_MAP_EN_B;
1265 req->tqp_vid = cpu_to_le16(tqp_vid);
1266
1267 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 1268 if (ret) {
1269 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1270 ret);
1271 return ret;
1272 }
46a3df9f 1273
930ff2f6 1274 return 0;
46a3df9f
S		 1275}
1276
1277static int hclge_assign_tqp(struct hclge_vport *vport,
1278 struct hnae3_queue **tqp, u16 num_tqps)
1279{
1280 struct hclge_dev *hdev = vport->back;
7df7dad6 1281 int i, alloced;
46a3df9f
S		 1282
1283 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1284 alloced < num_tqps; i++) {
1285 if (!hdev->htqp[i].alloced) {
1286 hdev->htqp[i].q.handle = &vport->nic;
1287 hdev->htqp[i].q.tqp_index = alloced;
1288 tqp[alloced] = &hdev->htqp[i].q;
1289 hdev->htqp[i].alloced = true;
46a3df9f
S		 1290 alloced++;
1291 }
1292 }
1293 vport->alloc_tqps = num_tqps;
1294
1295 return 0;
1296}
1297
1298static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1299{
1300 struct hnae3_handle *nic = &vport->nic;
1301 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1302 struct hclge_dev *hdev = vport->back;
1303 int i, ret;
1304
1305 kinfo->num_desc = hdev->num_desc;
1306 kinfo->rx_buf_len = hdev->rx_buf_len;
1307 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1308 kinfo->rss_size
1309 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1310 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1311
1312 for (i = 0; i < HNAE3_MAX_TC; i++) {
1313 if (hdev->hw_tc_map & BIT(i)) {
1314 kinfo->tc_info[i].enable = true;
1315 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1316 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1317 kinfo->tc_info[i].tc = i;
1318 } else {
1319 /* Set to default queue if TC is disable */
1320 kinfo->tc_info[i].enable = false;
1321 kinfo->tc_info[i].tqp_offset = 0;
1322 kinfo->tc_info[i].tqp_count = 1;
1323 kinfo->tc_info[i].tc = 0;
1324 }
1325 }
1326
1327 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1328 sizeof(struct hnae3_queue *), GFP_KERNEL);
1329 if (!kinfo->tqp)
1330 return -ENOMEM;
1331
1332 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
930ff2f6 1333 if (ret) {
46a3df9f 1334 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
930ff2f6 1335 return -EINVAL;
1336 }
46a3df9f 1337
930ff2f6 1338 return 0;
46a3df9f
S		 1339}
1340
7df7dad6
L		 1341static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1342 struct hclge_vport *vport)
1343{
1344 struct hnae3_handle *nic = &vport->nic;
1345 struct hnae3_knic_private_info *kinfo;
1346 u16 i;
1347
1348 kinfo = &nic->kinfo;
1349 for (i = 0; i < kinfo->num_tqps; i++) {
1350 struct hclge_tqp *q =
1351 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1352 bool is_pf;
1353 int ret;
1354
1355 is_pf = !(vport->vport_id);
1356 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1357 i, is_pf);
1358 if (ret)
1359 return ret;
1360 }
1361
1362 return 0;
1363}
1364
1365static int hclge_map_tqp(struct hclge_dev *hdev)
1366{
1367 struct hclge_vport *vport = hdev->vport;
1368 u16 i, num_vport;
1369
1370 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1371 for (i = 0; i < num_vport; i++) {
1372 int ret;
1373
1374 ret = hclge_map_tqp_to_vport(hdev, vport);
1375 if (ret)
1376 return ret;
1377
1378 vport++;
1379 }
1380
1381 return 0;
1382}
1383
46a3df9f
S		 1384static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1385{
1386 /* this would be initialized later */
1387}
1388
1389static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1390{
1391 struct hnae3_handle *nic = &vport->nic;
1392 struct hclge_dev *hdev = vport->back;
1393 int ret;
1394
1395 nic->pdev = hdev->pdev;
1396 nic->ae_algo = &ae_algo;
1397 nic->numa_node_mask = hdev->numa_node_mask;
1398
1399 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1400 ret = hclge_knic_setup(vport, num_tqps);
1401 if (ret) {
1402 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1403 ret);
1404 return ret;
1405 }
1406 } else {
1407 hclge_unic_setup(vport, num_tqps);
1408 }
1409
1410 return 0;
1411}
1412
1413static int hclge_alloc_vport(struct hclge_dev *hdev)
1414{
1415 struct pci_dev *pdev = hdev->pdev;
1416 struct hclge_vport *vport;
1417 u32 tqp_main_vport;
1418 u32 tqp_per_vport;
1419 int num_vport, i;
1420 int ret;
1421
1422 /* We need to alloc a vport for main NIC of PF */
1423 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1424
b76edfb2
HT		 1425 if (hdev->num_tqps < num_vport) {
1426 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1427 hdev->num_tqps, num_vport);
1428 return -EINVAL;
1429 }
46a3df9f
S		 1430
1431 /* Alloc the same number of TQPs for every vport */
1432 tqp_per_vport = hdev->num_tqps / num_vport;
1433 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1434
1435 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1436 GFP_KERNEL);
1437 if (!vport)
1438 return -ENOMEM;
1439
1440 hdev->vport = vport;
1441 hdev->num_alloc_vport = num_vport;
1442
bc59f827
FL		 1443 if (IS_ENABLED(CONFIG_PCI_IOV))
1444 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1445
1446 for (i = 0; i < num_vport; i++) {
1447 vport->back = hdev;
1448 vport->vport_id = i;
1449
1450 if (i == 0)
1451 ret = hclge_vport_setup(vport, tqp_main_vport);
1452 else
1453 ret = hclge_vport_setup(vport, tqp_per_vport);
1454 if (ret) {
1455 dev_err(&pdev->dev,
1456 "vport setup failed for vport %d, %d\n",
1457 i, ret);
1458 return ret;
1459 }
1460
1461 vport++;
1462 }
1463
1464 return 0;
1465}
1466
acf61ecd
YL		 1467static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1468 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1469{
1470/* TX buffer size is unit by 128 byte */
1471#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1472#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1473 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1474 struct hclge_desc desc;
1475 int ret;
1476 u8 i;
1477
d44f9b63 1478 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1479
1480 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1481 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1482 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1483
46a3df9f
S		 1484 req->tx_pkt_buff[i] =
1485 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1486 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1487 }
46a3df9f
S		 1488
1489 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 1490 if (ret) {
46a3df9f
S		 1491 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1492 ret);
930ff2f6 1493 return ret;
1494 }
46a3df9f 1495
930ff2f6 1496 return 0;
46a3df9f
S		 1497}
1498
acf61ecd
YL		 1499static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1500 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1501{
acf61ecd 1502 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1503
930ff2f6 1504 if (ret) {
1505 dev_err(&hdev->pdev->dev,
1506 "tx buffer alloc failed %d\n", ret);
1507 return ret;
1508 }
46a3df9f 1509
930ff2f6 1510 return 0;
46a3df9f
S		 1511}
1512
1513static int hclge_get_tc_num(struct hclge_dev *hdev)
1514{
1515 int i, cnt = 0;
1516
1517 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1518 if (hdev->hw_tc_map & BIT(i))
1519 cnt++;
1520 return cnt;
1521}
1522
1523static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1524{
1525 int i, cnt = 0;
1526
1527 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1528 if (hdev->hw_tc_map & BIT(i) &&
1529 hdev->tm_info.hw_pfc_map & BIT(i))
1530 cnt++;
1531 return cnt;
1532}
1533
1534/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1535static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1536 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1537{
1538 struct hclge_priv_buf *priv;
1539 int i, cnt = 0;
1540
1541 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1542 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1543 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1544 priv->enable)
1545 cnt++;
1546 }
1547
1548 return cnt;
1549}
1550
1551/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1552static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1553 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1554{
1555 struct hclge_priv_buf *priv;
1556 int i, cnt = 0;
1557
1558 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1559 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1560 if (hdev->hw_tc_map & BIT(i) &&
1561 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1562 priv->enable)
1563 cnt++;
1564 }
1565
1566 return cnt;
1567}
1568
acf61ecd 1569static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1570{
1571 struct hclge_priv_buf *priv;
1572 u32 rx_priv = 0;
1573 int i;
1574
1575 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1576 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1577 if (priv->enable)
1578 rx_priv += priv->buf_size;
1579 }
1580 return rx_priv;
1581}
1582
acf61ecd 1583static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1584{
1585 u32 i, total_tx_size = 0;
1586
1587 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1588 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1589
1590 return total_tx_size;
1591}
1592
acf61ecd
YL		 1593static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1594 struct hclge_pkt_buf_alloc *buf_alloc,
1595 u32 rx_all)
46a3df9f
S		 1596{
1597 u32 shared_buf_min, shared_buf_tc, shared_std;
1598 int tc_num, pfc_enable_num;
1599 u32 shared_buf;
1600 u32 rx_priv;
1601 int i;
1602
1603 tc_num = hclge_get_tc_num(hdev);
1604 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1605
d221df4e
YL		 1606 if (hnae3_dev_dcb_supported(hdev))
1607 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1608 else
1609 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1610
46a3df9f
S		 1611 shared_buf_tc = pfc_enable_num * hdev->mps +
1612 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1613 hdev->mps;
1614 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1615
acf61ecd 1616 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1617 if (rx_all <= rx_priv + shared_std)
1618 return false;
1619
1620 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1621 buf_alloc->s_buf.buf_size = shared_buf;
1622 buf_alloc->s_buf.self.high = shared_buf;
1623 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1624
1625 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1626 if ((hdev->hw_tc_map & BIT(i)) &&
1627 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1628 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1629 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1630 } else {
acf61ecd
YL		 1631 buf_alloc->s_buf.tc_thrd[i].low = 0;
1632 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1633 }
1634 }
1635
1636 return true;
1637}
1638
acf61ecd
YL		 1639static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1640 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1641{
1642 u32 i, total_size;
1643
1644 total_size = hdev->pkt_buf_size;
1645
1646 /* alloc tx buffer for all enabled tc */
1647 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1648 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1649
1650 if (total_size < HCLGE_DEFAULT_TX_BUF)
1651 return -ENOMEM;
1652
1653 if (hdev->hw_tc_map & BIT(i))
1654 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1655 else
1656 priv->tx_buf_size = 0;
1657
1658 total_size -= priv->tx_buf_size;
1659 }
1660
1661 return 0;
1662}
1663
46a3df9f
S		 1664/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1665 * @hdev: pointer to struct hclge_dev
acf61ecd 1666 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1667 * @return: 0: calculate sucessful, negative: fail
1668 */
1db9b1bf
YL		 1669static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1670 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1671{
9ffe79a9 1672 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1673 int no_pfc_priv_num, pfc_priv_num;
1674 struct hclge_priv_buf *priv;
1675 int i;
1676
acf61ecd 1677 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1678
d602a525
YL		 1679 /* When DCB is not supported, rx private
1680 * buffer is not allocated.
1681 */
1682 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1683 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1684 return -ENOMEM;
1685
1686 return 0;
1687 }
1688
46a3df9f
S		 1689 /* step 1, try to alloc private buffer for all enabled tc */
1690 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1691 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1692 if (hdev->hw_tc_map & BIT(i)) {
1693 priv->enable = 1;
1694 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1695 priv->wl.low = hdev->mps;
1696 priv->wl.high = priv->wl.low + hdev->mps;
1697 priv->buf_size = priv->wl.high +
1698 HCLGE_DEFAULT_DV;
1699 } else {
1700 priv->wl.low = 0;
1701 priv->wl.high = 2 * hdev->mps;
1702 priv->buf_size = priv->wl.high;
1703 }
bb1fe9ea
YL		 1704 } else {
1705 priv->enable = 0;
1706 priv->wl.low = 0;
1707 priv->wl.high = 0;
1708 priv->buf_size = 0;
46a3df9f
S		 1709 }
1710 }
1711
acf61ecd 1712 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1713 return 0;
1714
1715 /* step 2, try to decrease the buffer size of
1716 * no pfc TC's private buffer
1717 */
1718 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1719 priv = &buf_alloc->priv_buf[i];
46a3df9f 1720
bb1fe9ea
YL		 1721 priv->enable = 0;
1722 priv->wl.low = 0;
1723 priv->wl.high = 0;
1724 priv->buf_size = 0;
1725
1726 if (!(hdev->hw_tc_map & BIT(i)))
1727 continue;
1728
1729 priv->enable = 1;
46a3df9f
S		 1730
1731 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1732 priv->wl.low = 128;
1733 priv->wl.high = priv->wl.low + hdev->mps;
1734 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1735 } else {
1736 priv->wl.low = 0;
1737 priv->wl.high = hdev->mps;
1738 priv->buf_size = priv->wl.high;
1739 }
1740 }
1741
acf61ecd 1742 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1743 return 0;
1744
1745 /* step 3, try to reduce the number of pfc disabled TCs,
1746 * which have private buffer
1747 */
1748 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1749 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1750
1751 /* let the last to be cleared first */
1752 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1753 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1754
1755 if (hdev->hw_tc_map & BIT(i) &&
1756 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1757 /* Clear the no pfc TC private buffer */
1758 priv->wl.low = 0;
1759 priv->wl.high = 0;
1760 priv->buf_size = 0;
1761 priv->enable = 0;
1762 no_pfc_priv_num--;
1763 }
1764
acf61ecd 1765 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1766 no_pfc_priv_num == 0)
1767 break;
1768 }
1769
acf61ecd 1770 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1771 return 0;
1772
1773 /* step 4, try to reduce the number of pfc enabled TCs
1774 * which have private buffer.
1775 */
acf61ecd 1776 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1777
1778 /* let the last to be cleared first */
1779 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1780 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1781
1782 if (hdev->hw_tc_map & BIT(i) &&
1783 hdev->tm_info.hw_pfc_map & BIT(i)) {
1784 /* Reduce the number of pfc TC with private buffer */
1785 priv->wl.low = 0;
1786 priv->enable = 0;
1787 priv->wl.high = 0;
1788 priv->buf_size = 0;
1789 pfc_priv_num--;
1790 }
1791
acf61ecd 1792 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1793 pfc_priv_num == 0)
1794 break;
1795 }
acf61ecd 1796 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1797 return 0;
1798
1799 return -ENOMEM;
1800}
1801
acf61ecd
YL		 1802static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1803 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1804{
d44f9b63 1805 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1806 struct hclge_desc desc;
1807 int ret;
1808 int i;
1809
1810 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1811 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1812
1813 /* Alloc private buffer TCs */
1814 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1815 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1816
1817 req->buf_num[i] =
1818 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1819 req->buf_num[i] |=
5bca3b94 1820 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1821 }
1822
b8c8bf47 1823 req->shared_buf =
acf61ecd 1824 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1825 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1826
46a3df9f 1827 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 1828 if (ret) {
46a3df9f
S		 1829 dev_err(&hdev->pdev->dev,
1830 "rx private buffer alloc cmd failed %d\n", ret);
930ff2f6 1831 return ret;
1832 }
46a3df9f 1833
930ff2f6 1834 return 0;
46a3df9f
S		 1835}
1836
8cc87583 1837#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1838
acf61ecd
YL		 1839static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1840 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1841{
1842 struct hclge_rx_priv_wl_buf *req;
1843 struct hclge_priv_buf *priv;
1844 struct hclge_desc desc[2];
1845 int i, j;
1846 int ret;
1847
1848 for (i = 0; i < 2; i++) {
1849 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1850 false);
1851 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1852
1853 /* The first descriptor set the NEXT bit to 1 */
1854 if (i == 0)
1855 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1856 else
1857 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1858
1859 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1860 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1861
1862 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1863 req->tc_wl[j].high =
1864 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1865 req->tc_wl[j].high |=
8cc87583 1866 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1867 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1868 req->tc_wl[j].low =
1869 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1870 req->tc_wl[j].low |=
8cc87583 1871 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1872 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1873 }
1874 }
1875
1876 /* Send 2 descriptor at one time */
1877 ret = hclge_cmd_send(&hdev->hw, desc, 2);
930ff2f6 1878 if (ret) {
46a3df9f
S		 1879 dev_err(&hdev->pdev->dev,
1880 "rx private waterline config cmd failed %d\n",
1881 ret);
930ff2f6 1882 return ret;
1883 }
1884 return 0;
46a3df9f
S		 1885}
1886
acf61ecd
YL		 1887static int hclge_common_thrd_config(struct hclge_dev *hdev,
1888 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1889{
acf61ecd 1890 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1891 struct hclge_rx_com_thrd *req;
1892 struct hclge_desc desc[2];
1893 struct hclge_tc_thrd *tc;
1894 int i, j;
1895 int ret;
1896
1897 for (i = 0; i < 2; i++) {
1898 hclge_cmd_setup_basic_desc(&desc[i],
1899 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1900 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1901
1902 /* The first descriptor set the NEXT bit to 1 */
1903 if (i == 0)
1904 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1905 else
1906 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1907
1908 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1909 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1910
1911 req->com_thrd[j].high =
1912 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1913 req->com_thrd[j].high |=
8cc87583 1914 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1915 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1916 req->com_thrd[j].low =
1917 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1918 req->com_thrd[j].low |=
8cc87583 1919 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1920 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1921 }
1922 }
1923
1924 /* Send 2 descriptors at one time */
1925 ret = hclge_cmd_send(&hdev->hw, desc, 2);
930ff2f6 1926 if (ret) {
46a3df9f
S		 1927 dev_err(&hdev->pdev->dev,
1928 "common threshold config cmd failed %d\n", ret);
930ff2f6 1929 return ret;
1930 }
1931 return 0;
46a3df9f
S		 1932}
1933
acf61ecd
YL		 1934static int hclge_common_wl_config(struct hclge_dev *hdev,
1935 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1936{
acf61ecd 1937 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1938 struct hclge_rx_com_wl *req;
1939 struct hclge_desc desc;
1940 int ret;
1941
1942 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1943
1944 req = (struct hclge_rx_com_wl *)desc.data;
1945 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
8cc87583 1946 req->com_wl.high |=
1947 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1948 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1949
1950 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
8cc87583 1951 req->com_wl.low |=
1952 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1953 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1954
1955 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 1956 if (ret) {
46a3df9f
S		 1957 dev_err(&hdev->pdev->dev,
1958 "common waterline config cmd failed %d\n", ret);
930ff2f6 1959 return ret;
1960 }
1961
1962 return 0;
46a3df9f
S		 1963}
1964
1965int hclge_buffer_alloc(struct hclge_dev *hdev)
1966{
acf61ecd 1967 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1968 int ret;
1969
acf61ecd
YL		 1970 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1971 if (!pkt_buf)
46a3df9f
S		 1972 return -ENOMEM;
1973
acf61ecd 1974 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1975 if (ret) {
1976 dev_err(&hdev->pdev->dev,
1977 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1978 goto out;
9ffe79a9
YL		 1979 }
1980
acf61ecd 1981 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1982 if (ret) {
1983 dev_err(&hdev->pdev->dev,
1984 "could not alloc tx buffers %d\n", ret);
acf61ecd 1985 goto out;
46a3df9f
S		 1986 }
1987
acf61ecd 1988 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1989 if (ret) {
1990 dev_err(&hdev->pdev->dev,
1991 "could not calc rx priv buffer size for all TCs %d\n",
1992 ret);
acf61ecd 1993 goto out;
46a3df9f
S		 1994 }
1995
acf61ecd 1996 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1997 if (ret) {
1998 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1999 ret);
acf61ecd 2000 goto out;
46a3df9f
S		 2001 }
2002
2daf4a65 2003 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 2004 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 2005 if (ret) {
2006 dev_err(&hdev->pdev->dev,
2007 "could not configure rx private waterline %d\n",
2008 ret);
acf61ecd 2009 goto out;
2daf4a65 2010 }
46a3df9f 2011
acf61ecd 2012 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 2013 if (ret) {
2014 dev_err(&hdev->pdev->dev,
2015 "could not configure common threshold %d\n",
2016 ret);
acf61ecd 2017 goto out;
2daf4a65 2018 }
46a3df9f
S		 2019 }
2020
acf61ecd
YL		 2021 ret = hclge_common_wl_config(hdev, pkt_buf);
2022 if (ret)
46a3df9f
S		 2023 dev_err(&hdev->pdev->dev,
2024 "could not configure common waterline %d\n", ret);
46a3df9f 2025
acf61ecd
YL		 2026out:
2027 kfree(pkt_buf);
2028 return ret;
46a3df9f
S		 2029}
2030
2031static int hclge_init_roce_base_info(struct hclge_vport *vport)
2032{
2033 struct hnae3_handle *roce = &vport->roce;
2034 struct hnae3_handle *nic = &vport->nic;
2035
887c3820 2036 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 2037
2038 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2039 vport->back->num_msi_left == 0)
2040 return -EINVAL;
2041
2042 roce->rinfo.base_vector = vport->back->roce_base_vector;
2043
2044 roce->rinfo.netdev = nic->kinfo.netdev;
2045 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2046
2047 roce->pdev = nic->pdev;
2048 roce->ae_algo = nic->ae_algo;
2049 roce->numa_node_mask = nic->numa_node_mask;
2050
2051 return 0;
2052}
2053
887c3820 2054static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 2055{
2056 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 2057 int vectors;
2058 int i;
46a3df9f 2059
887c3820
SM		 2060 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2061 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2062 if (vectors < 0) {
2063 dev_err(&pdev->dev,
2064 "failed(%d) to allocate MSI/MSI-X vectors\n",
2065 vectors);
2066 return vectors;
46a3df9f 2067 }
887c3820
SM		 2068 if (vectors < hdev->num_msi)
2069 dev_warn(&hdev->pdev->dev,
2070 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2071 hdev->num_msi, vectors);
46a3df9f 2072
887c3820
SM		 2073 hdev->num_msi = vectors;
2074 hdev->num_msi_left = vectors;
2075 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 2076 hdev->roce_base_vector = hdev->base_msi_vector +
2077 HCLGE_ROCE_VECTOR_OFFSET;
2078
46a3df9f
S		 2079 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2080 sizeof(u16), GFP_KERNEL);
887c3820
SM		 2081 if (!hdev->vector_status) {
2082 pci_free_irq_vectors(pdev);
46a3df9f 2083 return -ENOMEM;
887c3820 2084 }
46a3df9f
S		 2085
2086 for (i = 0; i < hdev->num_msi; i++)
2087 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2088
887c3820
SM		 2089 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2090 sizeof(int), GFP_KERNEL);
2091 if (!hdev->vector_irq) {
2092 pci_free_irq_vectors(pdev);
2093 return -ENOMEM;
46a3df9f 2094 }
46a3df9f
S		 2095
2096 return 0;
2097}
2098
2099static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2100{
2101 struct hclge_mac *mac = &hdev->hw.mac;
2102
2103 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2104 mac->duplex = (u8)duplex;
2105 else
2106 mac->duplex = HCLGE_MAC_FULL;
2107
2108 mac->speed = speed;
2109}
2110
2111int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2112{
d44f9b63 2113 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2114 struct hclge_desc desc;
2115 int ret;
2116
d44f9b63 2117 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2118
2119 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2120
928d369a 2121 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 2122
2123 switch (speed) {
2124 case HCLGE_MAC_SPEED_10M:
928d369a 2125 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2126 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 2127 break;
2128 case HCLGE_MAC_SPEED_100M:
928d369a 2129 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2130 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 2131 break;
2132 case HCLGE_MAC_SPEED_1G:
928d369a 2133 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2134 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 2135 break;
2136 case HCLGE_MAC_SPEED_10G:
928d369a 2137 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2138 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 2139 break;
2140 case HCLGE_MAC_SPEED_25G:
928d369a 2141 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2142 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 2143 break;
2144 case HCLGE_MAC_SPEED_40G:
928d369a 2145 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2146 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 2147 break;
2148 case HCLGE_MAC_SPEED_50G:
928d369a 2149 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2150 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 2151 break;
2152 case HCLGE_MAC_SPEED_100G:
928d369a 2153 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2154 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 2155 break;
2156 default:
d7629e74 2157 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2158 return -EINVAL;
2159 }
2160
928d369a 2161 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2162 1);
46a3df9f
S		 2163
2164 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2165 if (ret) {
2166 dev_err(&hdev->pdev->dev,
2167 "mac speed/duplex config cmd failed %d.\n", ret);
2168 return ret;
2169 }
2170
2171 hclge_check_speed_dup(hdev, duplex, speed);
2172
2173 return 0;
2174}
2175
2176static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2177 u8 duplex)
2178{
2179 struct hclge_vport *vport = hclge_get_vport(handle);
2180 struct hclge_dev *hdev = vport->back;
2181
2182 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2183}
2184
2185static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2186 u8 *duplex)
2187{
d44f9b63 2188 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2189 struct hclge_desc desc;
2190 int speed_tmp;
2191 int ret;
2192
d44f9b63 2193 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2194
2195 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2196 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2197 if (ret) {
2198 dev_err(&hdev->pdev->dev,
2199 "mac speed/autoneg/duplex query cmd failed %d\n",
2200 ret);
2201 return ret;
2202 }
2203
928d369a 2204 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2205 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2206 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 2207
2208 ret = hclge_parse_speed(speed_tmp, speed);
930ff2f6 2209 if (ret) {
46a3df9f
S		 2210 dev_err(&hdev->pdev->dev,
2211 "could not parse speed(=%d), %d\n", speed_tmp, ret);
930ff2f6 2212 return -EIO;
2213 }
46a3df9f 2214
930ff2f6 2215 return 0;
46a3df9f
S		 2216}
2217
46a3df9f
S		 2218static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2219{
d44f9b63 2220 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2221 struct hclge_desc desc;
a90bb9a5 2222 u32 flag = 0;
46a3df9f
S		 2223 int ret;
2224
2225 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2226
d44f9b63 2227 req = (struct hclge_config_auto_neg_cmd *)desc.data;
928d369a 2228 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 2229 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2230
2231 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 2232 if (ret) {
46a3df9f
S		 2233 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2234 ret);
930ff2f6 2235 return ret;
2236 }
46a3df9f 2237
930ff2f6 2238 return 0;
46a3df9f
S		 2239}
2240
2241static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2242{
2243 struct hclge_vport *vport = hclge_get_vport(handle);
2244 struct hclge_dev *hdev = vport->back;
2245
2246 return hclge_set_autoneg_en(hdev, enable);
2247}
2248
2249static int hclge_get_autoneg(struct hnae3_handle *handle)
2250{
2251 struct hclge_vport *vport = hclge_get_vport(handle);
2252 struct hclge_dev *hdev = vport->back;
9ff804ee
FL		 2253 struct phy_device *phydev = hdev->hw.mac.phydev;
2254
2255 if (phydev)
2256 return phydev->autoneg;
46a3df9f
S		 2257
2258 return hdev->hw.mac.autoneg;
2259}
2260
6f712727
PL		 2261static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2262 bool mask_vlan,
2263 u8 *mac_mask)
2264{
2265 struct hclge_mac_vlan_mask_entry_cmd *req;
2266 struct hclge_desc desc;
2267 int status;
2268
2269 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2270 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2271
928d369a 2272 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2273 mask_vlan ? 1 : 0);
6f712727
PL		 2274 ether_addr_copy(req->mac_mask, mac_mask);
2275
2276 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2277 if (status)
2278 dev_err(&hdev->pdev->dev,
2279 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2280 status);
2281
2282 return status;
2283}
2284
46a3df9f
S		 2285static int hclge_mac_init(struct hclge_dev *hdev)
2286{
59bc85ec
FL		 2287 struct hnae3_handle *handle = &hdev->vport[0].nic;
2288 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 2289 struct hclge_mac *mac = &hdev->hw.mac;
6f712727 2290 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
a832d8b5 2291 struct hclge_vport *vport;
59bc85ec 2292 int mtu;
46a3df9f 2293 int ret;
a832d8b5 2294 int i;
46a3df9f
S		 2295
2296 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2297 if (ret) {
2298 dev_err(&hdev->pdev->dev,
2299 "Config mac speed dup fail ret=%d\n", ret);
2300 return ret;
2301 }
2302
2303 mac->link = 0;
2304
46a3df9f 2305 /* Initialize the MTA table work mode */
46a3df9f
S		 2306 hdev->enable_mta = true;
2307 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2308
2309 ret = hclge_set_mta_filter_mode(hdev,
2310 hdev->mta_mac_sel_type,
2311 hdev->enable_mta);
2312 if (ret) {
2313 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2314 ret);
2315 return ret;
2316 }
2317
a832d8b5
XW		 2318 for (i = 0; i < hdev->num_alloc_vport; i++) {
2319 vport = &hdev->vport[i];
2320 vport->accept_mta_mc = false;
2321
2322 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2323 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2324 if (ret) {
2325 dev_err(&hdev->pdev->dev,
2326 "set mta filter mode fail ret=%d\n", ret);
2327 return ret;
2328 }
6f712727
PL		 2329 }
2330
2331 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
59bc85ec 2332 if (ret) {
6f712727
PL		 2333 dev_err(&hdev->pdev->dev,
2334 "set default mac_vlan_mask fail ret=%d\n", ret);
59bc85ec
FL		 2335 return ret;
2336 }
6f712727 2337
59bc85ec
FL		 2338 if (netdev)
2339 mtu = netdev->mtu;
2340 else
2341 mtu = ETH_DATA_LEN;
2342
2343 ret = hclge_set_mtu(handle, mtu);
930ff2f6 2344 if (ret) {
59bc85ec
FL		 2345 dev_err(&hdev->pdev->dev,
2346 "set mtu failed ret=%d\n", ret);
930ff2f6 2347 return ret;
2348 }
59bc85ec 2349
930ff2f6 2350 return 0;
46a3df9f
S		 2351}
2352
22fd3468
SM		 2353static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2354{
2355 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2356 schedule_work(&hdev->mbx_service_task);
2357}
2358
ed4a1bb8
SM		 2359static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2360{
2361 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2362 schedule_work(&hdev->rst_service_task);
2363}
2364
46a3df9f
S		 2365static void hclge_task_schedule(struct hclge_dev *hdev)
2366{
2367 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2368 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2369 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2370 (void)schedule_work(&hdev->service_task);
2371}
2372
2373static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2374{
d44f9b63 2375 struct hclge_link_status_cmd *req;
46a3df9f
S		 2376 struct hclge_desc desc;
2377 int link_status;
2378 int ret;
2379
2380 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2381 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2382 if (ret) {
2383 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2384 ret);
2385 return ret;
2386 }
2387
d44f9b63 2388 req = (struct hclge_link_status_cmd *)desc.data;
717523d0 2389 link_status = req->status & HCLGE_LINK_STATUS;
46a3df9f
S		 2390
2391 return !!link_status;
2392}
2393
2394static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2395{
2396 int mac_state;
2397 int link_stat;
2398
2399 mac_state = hclge_get_mac_link_status(hdev);
2400
2401 if (hdev->hw.mac.phydev) {
2402 if (!genphy_read_status(hdev->hw.mac.phydev))
2403 link_stat = mac_state &
2404 hdev->hw.mac.phydev->link;
2405 else
2406 link_stat = 0;
2407
2408 } else {
2409 link_stat = mac_state;
2410 }
2411
2412 return !!link_stat;
2413}
2414
2415static void hclge_update_link_status(struct hclge_dev *hdev)
2416{
15a50665 2417 struct hnae3_client *rclient = hdev->roce_client;
46a3df9f 2418 struct hnae3_client *client = hdev->nic_client;
bc0b7416 2419 struct hnae3_handle *rhandle;
46a3df9f
S		 2420 struct hnae3_handle *handle;
2421 int state;
2422 int i;
2423
2424 if (!client)
2425 return;
2426 state = hclge_get_mac_phy_link(hdev);
2427 if (state != hdev->hw.mac.link) {
2428 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2429 handle = &hdev->vport[i].nic;
2430 client->ops->link_status_change(handle, state);
bc0b7416 2431 rhandle = &hdev->vport[i].roce;
15a50665 2432 if (rclient && rclient->ops->link_status_change)
bc0b7416
WHX		 2433 rclient->ops->link_status_change(rhandle,
2434 state);
46a3df9f
S		 2435 }
2436 hdev->hw.mac.link = state;
2437 }
2438}
2439
2440static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2441{
2442 struct hclge_mac mac = hdev->hw.mac;
2443 u8 duplex;
2444 int speed;
2445 int ret;
2446
2447 /* get the speed and duplex as autoneg'result from mac cmd when phy
2448 * doesn't exit.
2449 */
c040366b 2450 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2451 return 0;
2452
2453 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2454 if (ret) {
2455 dev_err(&hdev->pdev->dev,
2456 "mac autoneg/speed/duplex query failed %d\n", ret);
2457 return ret;
2458 }
2459
2460 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2461 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2462 if (ret) {
2463 dev_err(&hdev->pdev->dev,
2464 "mac speed/duplex config failed %d\n", ret);
2465 return ret;
2466 }
2467 }
2468
2469 return 0;
2470}
2471
2472static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2473{
2474 struct hclge_vport *vport = hclge_get_vport(handle);
2475 struct hclge_dev *hdev = vport->back;
2476
2477 return hclge_update_speed_duplex(hdev);
2478}
2479
2480static int hclge_get_status(struct hnae3_handle *handle)
2481{
2482 struct hclge_vport *vport = hclge_get_vport(handle);
2483 struct hclge_dev *hdev = vport->back;
2484
2485 hclge_update_link_status(hdev);
2486
2487 return hdev->hw.mac.link;
2488}
2489
d039ef68 2490static void hclge_service_timer(struct timer_list *t)
46a3df9f 2491{
d039ef68 2492 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2493
d039ef68 2494 mod_timer(&hdev->service_timer, jiffies + HZ);
7a5d2a39 2495 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2496 hclge_task_schedule(hdev);
2497}
2498
2499static void hclge_service_complete(struct hclge_dev *hdev)
2500{
2501 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2502
2503 /* Flush memory before next watchdog */
2504 smp_mb__before_atomic();
2505 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2506}
2507
202f2014
SM		 2508static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2509{
2510 u32 rst_src_reg;
22fd3468 2511 u32 cmdq_src_reg;
202f2014
SM		 2512
2513 /* fetch the events from their corresponding regs */
82bd1bef 2514 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
22fd3468
SM		 2515 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2516
2517 /* Assumption: If by any chance reset and mailbox events are reported
2518 * together then we will only process reset event in this go and will
2519 * defer the processing of the mailbox events. Since, we would have not
2520 * cleared RX CMDQ event this time we would receive again another
2521 * interrupt from H/W just for the mailbox.
2522 */
202f2014
SM		 2523
2524 /* check for vector0 reset event sources */
2525 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2526 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2527 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2528 return HCLGE_VECTOR0_EVENT_RST;
2529 }
2530
2531 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2532 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2533 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2534 return HCLGE_VECTOR0_EVENT_RST;
2535 }
2536
2537 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2538 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2539 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2540 return HCLGE_VECTOR0_EVENT_RST;
2541 }
2542
22fd3468
SM		 2543 /* check for vector0 mailbox(=CMDQ RX) event source */
2544 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2545 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2546 *clearval = cmdq_src_reg;
2547 return HCLGE_VECTOR0_EVENT_MBX;
2548 }
202f2014
SM		 2549
2550 return HCLGE_VECTOR0_EVENT_OTHER;
2551}
2552
2553static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2554 u32 regclr)
2555{
22fd3468
SM		 2556 switch (event_type) {
2557 case HCLGE_VECTOR0_EVENT_RST:
202f2014 2558 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
22fd3468
SM		 2559 break;
2560 case HCLGE_VECTOR0_EVENT_MBX:
2561 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2562 break;
2563 }
202f2014
SM		 2564}
2565
9ab4ad14
XW		 2566static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2567{
2568 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2569 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2570 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2571 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2572 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2573}
2574
466b0c00
L		 2575static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2576{
2577 writel(enable ? 1 : 0, vector->addr);
2578}
2579
2580static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2581{
2582 struct hclge_dev *hdev = data;
202f2014
SM		 2583 u32 event_cause;
2584 u32 clearval;
466b0c00
L		 2585
2586 hclge_enable_vector(&hdev->misc_vector, false);
202f2014
SM		 2587 event_cause = hclge_check_event_cause(hdev, &clearval);
2588
22fd3468 2589 /* vector 0 interrupt is shared with reset and mailbox source events.*/
202f2014
SM		 2590 switch (event_cause) {
2591 case HCLGE_VECTOR0_EVENT_RST:
ed4a1bb8 2592 hclge_reset_task_schedule(hdev);
202f2014 2593 break;
22fd3468
SM		 2594 case HCLGE_VECTOR0_EVENT_MBX:
2595 /* If we are here then,
2596 * 1. Either we are not handling any mbx task and we are not
2597 * scheduled as well
2598 * OR
2599 * 2. We could be handling a mbx task but nothing more is
2600 * scheduled.
2601 * In both cases, we should schedule mbx task as there are more
2602 * mbx messages reported by this interrupt.
2603 */
2604 hclge_mbx_task_schedule(hdev);
40ee4b71 2605 break;
202f2014 2606 default:
40ee4b71
YL		 2607 dev_warn(&hdev->pdev->dev,
2608 "received unknown or unhandled event of vector0\n");
202f2014
SM		 2609 break;
2610 }
2611
e9a50d09
YL		 2612 /* clear the source of interrupt if it is not cause by reset */
2613 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2614 hclge_clear_event_cause(hdev, event_cause, clearval);
2615 hclge_enable_vector(&hdev->misc_vector, true);
2616 }
466b0c00
L		 2617
2618 return IRQ_HANDLED;
2619}
2620
2621static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2622{
1dc5378f
PL		 2623 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2624 dev_warn(&hdev->pdev->dev,
2625 "vector(vector_id %d) has been freed.\n", vector_id);
2626 return;
2627 }
2628
466b0c00
L		 2629 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2630 hdev->num_msi_left += 1;
2631 hdev->num_msi_used -= 1;
2632}
2633
2634static void hclge_get_misc_vector(struct hclge_dev *hdev)
2635{
2636 struct hclge_misc_vector *vector = &hdev->misc_vector;
2637
2638 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2639
2640 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2641 hdev->vector_status[0] = 0;
2642
2643 hdev->num_msi_left -= 1;
2644 hdev->num_msi_used += 1;
2645}
2646
2647static int hclge_misc_irq_init(struct hclge_dev *hdev)
2648{
2649 int ret;
2650
2651 hclge_get_misc_vector(hdev);
2652
202f2014
SM		 2653 /* this would be explicitly freed in the end */
2654 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2655 0, "hclge_misc", hdev);
466b0c00
L		 2656 if (ret) {
2657 hclge_free_vector(hdev, 0);
2658 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2659 hdev->misc_vector.vector_irq);
2660 }
2661
2662 return ret;
2663}
2664
202f2014
SM		 2665static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2666{
2667 free_irq(hdev->misc_vector.vector_irq, hdev);
2668 hclge_free_vector(hdev, 0);
2669}
2670
4ed340ab
L		 2671static int hclge_notify_client(struct hclge_dev *hdev,
2672 enum hnae3_reset_notify_type type)
2673{
3628abd0 2674 struct hnae3_client *rclient = hdev->roce_client;
4ed340ab 2675 struct hnae3_client *client = hdev->nic_client;
d3f5c892
LO		 2676 struct hnae3_handle *handle;
2677 int ret;
4ed340ab
L		 2678 u16 i;
2679
2680 if (!client->ops->reset_notify)
2681 return -EOPNOTSUPP;
2682
2683 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
d3f5c892 2684 handle = &hdev->vport[i].nic;
4ed340ab 2685 ret = client->ops->reset_notify(handle, type);
2e5ed0d2
WHX		 2686 if (ret) {
2687 dev_err(&hdev->pdev->dev,
2688 "notify nic client failed %d", ret);
4ed340ab 2689 return ret;
2e5ed0d2 2690 }
0520c2e5 2691
3628abd0 2692 if (rclient && rclient->ops->reset_notify) {
2693 handle = &hdev->vport[i].roce;
2694 ret = rclient->ops->reset_notify(handle, type);
2695 if (ret) {
2696 dev_err(&hdev->pdev->dev,
2697 "notify roce client failed %d", ret);
2698 return ret;
2699 }
d3f5c892 2700 }
4ed340ab
L		 2701 }
2702
3628abd0 2703 return 0;
4ed340ab
L		 2704}
2705
2706static int hclge_reset_wait(struct hclge_dev *hdev)
2707{
2708#define HCLGE_RESET_WATI_MS 100
2709#define HCLGE_RESET_WAIT_CNT 5
2710 u32 val, reg, reg_bit;
2711 u32 cnt = 0;
2712
2713 switch (hdev->reset_type) {
2714 case HNAE3_GLOBAL_RESET:
2715 reg = HCLGE_GLOBAL_RESET_REG;
2716 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2717 break;
2718 case HNAE3_CORE_RESET:
2719 reg = HCLGE_GLOBAL_RESET_REG;
2720 reg_bit = HCLGE_CORE_RESET_BIT;
2721 break;
2722 case HNAE3_FUNC_RESET:
2723 reg = HCLGE_FUN_RST_ING;
2724 reg_bit = HCLGE_FUN_RST_ING_B;
2725 break;
2726 default:
2727 dev_err(&hdev->pdev->dev,
2728 "Wait for unsupported reset type: %d\n",
2729 hdev->reset_type);
2730 return -EINVAL;
2731 }
2732
2733 val = hclge_read_dev(&hdev->hw, reg);
928d369a 2734 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
4ed340ab
L		 2735 msleep(HCLGE_RESET_WATI_MS);
2736 val = hclge_read_dev(&hdev->hw, reg);
2737 cnt++;
2738 }
2739
4ed340ab
L		 2740 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2741 dev_warn(&hdev->pdev->dev,
2742 "Wait for reset timeout: %d\n", hdev->reset_type);
2743 return -EBUSY;
2744 }
2745
2746 return 0;
2747}
2748
13a86fae 2749int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2750{
2751 struct hclge_desc desc;
2752 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2753 int ret;
2754
2755 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
98529d42 2756 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
928d369a 2757 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2758 req->fun_reset_vfid = func_id;
2759
2760 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2761 if (ret)
2762 dev_err(&hdev->pdev->dev,
2763 "send function reset cmd fail, status =%d\n", ret);
2764
2765 return ret;
2766}
2767
d5752031 2768static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2769{
2770 struct pci_dev *pdev = hdev->pdev;
2771 u32 val;
2772
d5752031 2773 switch (hdev->reset_type) {
4ed340ab
L		 2774 case HNAE3_GLOBAL_RESET:
2775 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
928d369a 2776 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2777 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2778 dev_info(&pdev->dev, "Global Reset requested\n");
2779 break;
2780 case HNAE3_CORE_RESET:
2781 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
928d369a 2782 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2783 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2784 dev_info(&pdev->dev, "Core Reset requested\n");
2785 break;
2786 case HNAE3_FUNC_RESET:
2787 dev_info(&pdev->dev, "PF Reset requested\n");
2788 hclge_func_reset_cmd(hdev, 0);
ed4a1bb8
SM		 2789 /* schedule again to check later */
2790 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2791 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2792 break;
2793 default:
2794 dev_warn(&pdev->dev,
d5752031 2795 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2796 break;
2797 }
2798}
2799
d5752031
SM		 2800static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2801 unsigned long *addr)
2802{
2803 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2804
2805 /* return the highest priority reset level amongst all */
2806 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2807 rst_level = HNAE3_GLOBAL_RESET;
2808 else if (test_bit(HNAE3_CORE_RESET, addr))
2809 rst_level = HNAE3_CORE_RESET;
2810 else if (test_bit(HNAE3_IMP_RESET, addr))
2811 rst_level = HNAE3_IMP_RESET;
2812 else if (test_bit(HNAE3_FUNC_RESET, addr))
2813 rst_level = HNAE3_FUNC_RESET;
2814
2815 /* now, clear all other resets */
2816 clear_bit(HNAE3_GLOBAL_RESET, addr);
2817 clear_bit(HNAE3_CORE_RESET, addr);
2818 clear_bit(HNAE3_IMP_RESET, addr);
2819 clear_bit(HNAE3_FUNC_RESET, addr);
2820
2821 return rst_level;
2822}
2823
e9a50d09
YL		 2824static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2825{
2826 u32 clearval = 0;
2827
2828 switch (hdev->reset_type) {
2829 case HNAE3_IMP_RESET:
2830 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2831 break;
2832 case HNAE3_GLOBAL_RESET:
2833 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2834 break;
2835 case HNAE3_CORE_RESET:
2836 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2837 break;
2838 default:
abcbcae3 2839 dev_warn(&hdev->pdev->dev, "Unsupported reset event to clear:%d",
2840 hdev->reset_type);
e9a50d09
YL		 2841 break;
2842 }
2843
2844 if (!clearval)
2845 return;
2846
2847 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2848 hclge_enable_vector(&hdev->misc_vector, true);
2849}
2850
d5752031
SM		 2851static void hclge_reset(struct hclge_dev *hdev)
2852{
2853 /* perform reset of the stack & ae device for a client */
c07b029f 2854
d5752031
SM		 2855 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2856
2857 if (!hclge_reset_wait(hdev)) {
c07b029f 2858 rtnl_lock();
d5752031
SM		 2859 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2860 hclge_reset_ae_dev(hdev->ae_dev);
2861 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
c07b029f 2862 rtnl_unlock();
e9a50d09
YL		 2863
2864 hclge_clear_reset_cause(hdev);
d5752031
SM		 2865 } else {
2866 /* schedule again to check pending resets later */
2867 set_bit(hdev->reset_type, &hdev->reset_pending);
2868 hclge_reset_task_schedule(hdev);
2869 }
2870
2871 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2872}
2873
4aef908d 2874static void hclge_reset_event(struct hnae3_handle *handle)
4ed340ab
L		 2875{
2876 struct hclge_vport *vport = hclge_get_vport(handle);
2877 struct hclge_dev *hdev = vport->back;
2878
4aef908d
SM		 2879 /* check if this is a new reset request and we are not here just because
2880 * last reset attempt did not succeed and watchdog hit us again. We will
2881 * know this if last reset request did not occur very recently (watchdog
2882 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2883 * In case of new request we reset the "reset level" to PF reset.
2884 */
0324e7bd 2885 if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
4aef908d 2886 handle->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2887
4aef908d
SM		 2888 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2889 handle->reset_level);
2890
2891 /* request reset & schedule reset task */
2892 set_bit(handle->reset_level, &hdev->reset_request);
2893 hclge_reset_task_schedule(hdev);
2894
2895 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2896 handle->reset_level++;
0324e7bd 2897
2898 handle->last_reset_time = jiffies;
4ed340ab
L		 2899}
2900
2901static void hclge_reset_subtask(struct hclge_dev *hdev)
2902{
d5752031
SM		 2903 /* check if there is any ongoing reset in the hardware. This status can
2904 * be checked from reset_pending. If there is then, we need to wait for
2905 * hardware to complete reset.
2906 * a. If we are able to figure out in reasonable time that hardware
2907 * has fully resetted then, we can proceed with driver, client
2908 * reset.
2909 * b. else, we can come back later to check this status so re-sched
2910 * now.
2911 */
2912 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2913 if (hdev->reset_type != HNAE3_NONE_RESET)
2914 hclge_reset(hdev);
4ed340ab 2915
d5752031
SM		 2916 /* check if we got any *new* reset requests to be honored */
2917 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2918 if (hdev->reset_type != HNAE3_NONE_RESET)
2919 hclge_do_reset(hdev);
4ed340ab 2920
4ed340ab
L		 2921 hdev->reset_type = HNAE3_NONE_RESET;
2922}
2923
ed4a1bb8 2924static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2925{
ed4a1bb8
SM		 2926 struct hclge_dev *hdev =
2927 container_of(work, struct hclge_dev, rst_service_task);
2928
2929 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2930 return;
2931
2932 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2933
4ed340ab 2934 hclge_reset_subtask(hdev);
ed4a1bb8
SM		 2935
2936 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2937}
2938
22fd3468
SM		 2939static void hclge_mailbox_service_task(struct work_struct *work)
2940{
2941 struct hclge_dev *hdev =
2942 container_of(work, struct hclge_dev, mbx_service_task);
2943
2944 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2945 return;
2946
2947 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2948
2949 hclge_mbx_handler(hdev);
2950
2951 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2952}
2953
46a3df9f
S		 2954static void hclge_service_task(struct work_struct *work)
2955{
2956 struct hclge_dev *hdev =
2957 container_of(work, struct hclge_dev, service_task);
2958
7a5d2a39
JS		 2959 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2960 hclge_update_stats_for_all(hdev);
2961 hdev->hw_stats.stats_timer = 0;
2962 }
2963
46a3df9f
S		 2964 hclge_update_speed_duplex(hdev);
2965 hclge_update_link_status(hdev);
46a3df9f
S		 2966 hclge_service_complete(hdev);
2967}
2968
46a3df9f
S		 2969struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2970{
2971 /* VF handle has no client */
2972 if (!handle->client)
2973 return container_of(handle, struct hclge_vport, nic);
2974 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2975 return container_of(handle, struct hclge_vport, roce);
2976 else
2977 return container_of(handle, struct hclge_vport, nic);
2978}
2979
2980static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2981 struct hnae3_vector_info *vector_info)
2982{
2983 struct hclge_vport *vport = hclge_get_vport(handle);
2984 struct hnae3_vector_info *vector = vector_info;
2985 struct hclge_dev *hdev = vport->back;
2986 int alloc = 0;
2987 int i, j;
2988
2989 vector_num = min(hdev->num_msi_left, vector_num);
2990
2991 for (j = 0; j < vector_num; j++) {
2992 for (i = 1; i < hdev->num_msi; i++) {
2993 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2994 vector->vector = pci_irq_vector(hdev->pdev, i);
2995 vector->io_addr = hdev->hw.io_base +
2996 HCLGE_VECTOR_REG_BASE +
2997 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2998 vport->vport_id *
2999 HCLGE_VECTOR_VF_OFFSET;
3000 hdev->vector_status[i] = vport->vport_id;
887c3820 3001 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 3002
3003 vector++;
3004 alloc++;
3005
3006 break;
3007 }
3008 }
3009 }
3010 hdev->num_msi_left -= alloc;
3011 hdev->num_msi_used += alloc;
3012
3013 return alloc;
3014}
3015
3016static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
3017{
3018 int i;
3019
887c3820
SM		 3020 for (i = 0; i < hdev->num_msi; i++)
3021 if (vector == hdev->vector_irq[i])
3022 return i;
3023
46a3df9f
S		 3024 return -EINVAL;
3025}
3026
7412200c
YL		 3027static int hclge_put_vector(struct hnae3_handle *handle, int vector)
3028{
3029 struct hclge_vport *vport = hclge_get_vport(handle);
3030 struct hclge_dev *hdev = vport->back;
3031 int vector_id;
3032
3033 vector_id = hclge_get_vector_index(hdev, vector);
3034 if (vector_id < 0) {
3035 dev_err(&hdev->pdev->dev,
3036 "Get vector index fail. vector_id =%d\n", vector_id);
3037 return vector_id;
3038 }
3039
3040 hclge_free_vector(hdev, vector_id);
3041
3042 return 0;
3043}
3044
46a3df9f
S		 3045static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
3046{
3047 return HCLGE_RSS_KEY_SIZE;
3048}
3049
3050static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3051{
3052 return HCLGE_RSS_IND_TBL_SIZE;
3053}
3054
46a3df9f
S		 3055static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3056 const u8 hfunc, const u8 *key)
3057{
d44f9b63 3058 struct hclge_rss_config_cmd *req;
46a3df9f
S		 3059 struct hclge_desc desc;
3060 int key_offset;
3061 int key_size;
3062 int ret;
3063
d44f9b63 3064 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 3065
3066 for (key_offset = 0; key_offset < 3; key_offset++) {
3067 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3068 false);
3069
3070 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3071 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3072
3073 if (key_offset == 2)
3074 key_size =
3075 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3076 else
3077 key_size = HCLGE_RSS_HASH_KEY_NUM;
3078
3079 memcpy(req->hash_key,
3080 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3081
3082 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3083 if (ret) {
3084 dev_err(&hdev->pdev->dev,
3085 "Configure RSS config fail, status = %d\n",
3086 ret);
3087 return ret;
3088 }
3089 }
3090 return 0;
3091}
3092
dcd4ef5e 3093static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3094{
d44f9b63 3095 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3096 struct hclge_desc desc;
3097 int i, j;
3098 int ret;
3099
d44f9b63 3100 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3101
3102 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3103 hclge_cmd_setup_basic_desc
3104 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3105
a90bb9a5
YL		 3106 req->start_table_index =
3107 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3108 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3109
3110 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3111 req->rss_result[j] =
3112 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3113
3114 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3115 if (ret) {
3116 dev_err(&hdev->pdev->dev,
3117 "Configure rss indir table fail,status = %d\n",
3118 ret);
3119 return ret;
3120 }
3121 }
3122 return 0;
3123}
3124
3125static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3126 u16 *tc_size, u16 *tc_offset)
3127{
d44f9b63 3128 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3129 struct hclge_desc desc;
3130 int ret;
3131 int i;
3132
3133 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3134 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3135
3136 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3137 u16 mode = 0;
3138
928d369a 3139 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3140 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3141 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3142 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3143 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3144
3145 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3146 }
3147
3148 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 3149 if (ret) {
46a3df9f
S		 3150 dev_err(&hdev->pdev->dev,
3151 "Configure rss tc mode fail, status = %d\n", ret);
930ff2f6 3152 return ret;
3153 }
46a3df9f 3154
930ff2f6 3155 return 0;
46a3df9f
S		 3156}
3157
3158static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3159{
d44f9b63 3160 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3161 struct hclge_desc desc;
3162 int ret;
3163
3164 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3165
d44f9b63 3166 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef
YL		 3167
3168 /* Get the tuple cfg from pf */
3169 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3170 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3171 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3172 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3173 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3174 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3175 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3176 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
46a3df9f 3177 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 3178 if (ret) {
46a3df9f
S		 3179 dev_err(&hdev->pdev->dev,
3180 "Configure rss input fail, status = %d\n", ret);
930ff2f6 3181 return ret;
3182 }
3183
3184 return 0;
46a3df9f
S		 3185}
3186
3187static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3188 u8 *key, u8 *hfunc)
3189{
3190 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3191 int i;
3192
3193 /* Get hash algorithm */
3194 if (hfunc)
dcd4ef5e 3195 *hfunc = vport->rss_algo;
46a3df9f
S		 3196
3197 /* Get the RSS Key required by the user */
3198 if (key)
3199 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3200
3201 /* Get indirect table */
3202 if (indir)
3203 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3204 indir[i] = vport->rss_indirection_tbl[i];
3205
3206 return 0;
3207}
3208
3209static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3210 const u8 *key, const u8 hfunc)
3211{
3212 struct hclge_vport *vport = hclge_get_vport(handle);
3213 struct hclge_dev *hdev = vport->back;
3214 u8 hash_algo;
3215 int ret, i;
3216
3217 /* Set the RSS Hash Key if specififed by the user */
3218 if (key) {
46a3df9f
S		 3219
3220 if (hfunc == ETH_RSS_HASH_TOP ||
3221 hfunc == ETH_RSS_HASH_NO_CHANGE)
3222 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3223 else
3224 return -EINVAL;
3225 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3226 if (ret)
3227 return ret;
dcd4ef5e
YL		 3228
3229 /* Update the shadow RSS key with user specified qids */
3230 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3231 vport->rss_algo = hash_algo;
46a3df9f
S		 3232 }
3233
3234 /* Update the shadow RSS table with user specified qids */
3235 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3236 vport->rss_indirection_tbl[i] = indir[i];
3237
3238 /* Update the hardware */
dcd4ef5e 3239 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3240}
3241
f7db940a
L		 3242static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3243{
3244 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3245
3246 if (nfc->data & RXH_L4_B_2_3)
3247 hash_sets |= HCLGE_D_PORT_BIT;
3248 else
3249 hash_sets &= ~HCLGE_D_PORT_BIT;
3250
3251 if (nfc->data & RXH_IP_SRC)
3252 hash_sets |= HCLGE_S_IP_BIT;
3253 else
3254 hash_sets &= ~HCLGE_S_IP_BIT;
3255
3256 if (nfc->data & RXH_IP_DST)
3257 hash_sets |= HCLGE_D_IP_BIT;
3258 else
3259 hash_sets &= ~HCLGE_D_IP_BIT;
3260
3261 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3262 hash_sets |= HCLGE_V_TAG_BIT;
3263
3264 return hash_sets;
3265}
3266
3267static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3268 struct ethtool_rxnfc *nfc)
3269{
3270 struct hclge_vport *vport = hclge_get_vport(handle);
3271 struct hclge_dev *hdev = vport->back;
3272 struct hclge_rss_input_tuple_cmd *req;
3273 struct hclge_desc desc;
3274 u8 tuple_sets;
3275 int ret;
3276
3277 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3278 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3279 return -EINVAL;
3280
3281 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef 3282 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 3283
637053ef
YL		 3284 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3285 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3286 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3287 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3288 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3289 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3290 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3291 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 3292
3293 tuple_sets = hclge_get_rss_hash_bits(nfc);
3294 switch (nfc->flow_type) {
3295 case TCP_V4_FLOW:
3296 req->ipv4_tcp_en = tuple_sets;
3297 break;
3298 case TCP_V6_FLOW:
3299 req->ipv6_tcp_en = tuple_sets;
3300 break;
3301 case UDP_V4_FLOW:
3302 req->ipv4_udp_en = tuple_sets;
3303 break;
3304 case UDP_V6_FLOW:
3305 req->ipv6_udp_en = tuple_sets;
3306 break;
3307 case SCTP_V4_FLOW:
3308 req->ipv4_sctp_en = tuple_sets;
3309 break;
3310 case SCTP_V6_FLOW:
3311 if ((nfc->data & RXH_L4_B_0_1) ||
3312 (nfc->data & RXH_L4_B_2_3))
3313 return -EINVAL;
3314
3315 req->ipv6_sctp_en = tuple_sets;
3316 break;
3317 case IPV4_FLOW:
3318 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3319 break;
3320 case IPV6_FLOW:
3321 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3322 break;
3323 default:
3324 return -EINVAL;
3325 }
3326
3327 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
637053ef 3328 if (ret) {
f7db940a
L		 3329 dev_err(&hdev->pdev->dev,
3330 "Set rss tuple fail, status = %d\n", ret);
637053ef
YL		 3331 return ret;
3332 }
f7db940a 3333
637053ef
YL		 3334 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3335 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3336 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3337 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3338 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3339 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3340 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3341 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3342 return 0;
f7db940a
L		 3343}
3344
07d29954
L		 3345static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3346 struct ethtool_rxnfc *nfc)
3347{
3348 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3349 u8 tuple_sets;
07d29954
L		 3350
3351 nfc->data = 0;
3352
07d29954
L		 3353 switch (nfc->flow_type) {
3354 case TCP_V4_FLOW:
637053ef 3355 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3356 break;
3357 case UDP_V4_FLOW:
637053ef 3358 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3359 break;
3360 case TCP_V6_FLOW:
637053ef 3361 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3362 break;
3363 case UDP_V6_FLOW:
637053ef 3364 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3365 break;
3366 case SCTP_V4_FLOW:
637053ef 3367 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3368 break;
3369 case SCTP_V6_FLOW:
637053ef 3370 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3371 break;
3372 case IPV4_FLOW:
3373 case IPV6_FLOW:
3374 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3375 break;
3376 default:
3377 return -EINVAL;
3378 }
3379
3380 if (!tuple_sets)
3381 return 0;
3382
3383 if (tuple_sets & HCLGE_D_PORT_BIT)
3384 nfc->data |= RXH_L4_B_2_3;
3385 if (tuple_sets & HCLGE_S_PORT_BIT)
3386 nfc->data |= RXH_L4_B_0_1;
3387 if (tuple_sets & HCLGE_D_IP_BIT)
3388 nfc->data |= RXH_IP_DST;
3389 if (tuple_sets & HCLGE_S_IP_BIT)
3390 nfc->data |= RXH_IP_SRC;
3391
3392 return 0;
3393}
3394
46a3df9f
S		 3395static int hclge_get_tc_size(struct hnae3_handle *handle)
3396{
3397 struct hclge_vport *vport = hclge_get_vport(handle);
3398 struct hclge_dev *hdev = vport->back;
3399
3400 return hdev->rss_size_max;
3401}
3402
77f255c1 3403int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3404{
46a3df9f 3405 struct hclge_vport *vport = hdev->vport;
8015bb74
YL		 3406 u8 *rss_indir = vport[0].rss_indirection_tbl;
3407 u16 rss_size = vport[0].alloc_rss_size;
3408 u8 *key = vport[0].rss_hash_key;
3409 u8 hfunc = vport[0].rss_algo;
46a3df9f 3410 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3411 u16 tc_valid[HCLGE_MAX_TC_NUM];
3412 u16 tc_size[HCLGE_MAX_TC_NUM];
8015bb74
YL		 3413 u16 roundup_size;
3414 int i, ret;
68ece54e 3415
46a3df9f
S		 3416 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3417 if (ret)
8015bb74 3418 return ret;
46a3df9f 3419
46a3df9f
S		 3420 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3421 if (ret)
8015bb74 3422 return ret;
46a3df9f
S		 3423
3424 ret = hclge_set_rss_input_tuple(hdev);
3425 if (ret)
8015bb74 3426 return ret;
46a3df9f 3427
68ece54e
YL		 3428 /* Each TC have the same queue size, and tc_size set to hardware is
3429 * the log2 of roundup power of two of rss_size, the acutal queue
3430 * size is limited by indirection table.
3431 */
3432 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3433 dev_err(&hdev->pdev->dev,
3434 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3435 rss_size);
8015bb74 3436 return -EINVAL;
68ece54e
YL		 3437 }
3438
3439 roundup_size = roundup_pow_of_two(rss_size);
3440 roundup_size = ilog2(roundup_size);
3441
46a3df9f 3442 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3443 tc_valid[i] = 0;
46a3df9f 3444
68ece54e
YL		 3445 if (!(hdev->hw_tc_map & BIT(i)))
3446 continue;
3447
3448 tc_valid[i] = 1;
3449 tc_size[i] = roundup_size;
3450 tc_offset[i] = rss_size * i;
46a3df9f 3451 }
68ece54e 3452
8015bb74
YL		 3453 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3454}
46a3df9f 3455
8015bb74
YL		 3456void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3457{
3458 struct hclge_vport *vport = hdev->vport;
3459 int i, j;
46a3df9f 3460
8015bb74
YL		 3461 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3462 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3463 vport[j].rss_indirection_tbl[i] =
3464 i % vport[j].alloc_rss_size;
3465 }
3466}
3467
3468static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3469{
3470 struct hclge_vport *vport = hdev->vport;
3471 int i;
3472
8015bb74
YL		 3473 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3474 vport[i].rss_tuple_sets.ipv4_tcp_en =
3475 HCLGE_RSS_INPUT_TUPLE_OTHER;
3476 vport[i].rss_tuple_sets.ipv4_udp_en =
3477 HCLGE_RSS_INPUT_TUPLE_OTHER;
3478 vport[i].rss_tuple_sets.ipv4_sctp_en =
3479 HCLGE_RSS_INPUT_TUPLE_SCTP;
3480 vport[i].rss_tuple_sets.ipv4_fragment_en =
3481 HCLGE_RSS_INPUT_TUPLE_OTHER;
3482 vport[i].rss_tuple_sets.ipv6_tcp_en =
3483 HCLGE_RSS_INPUT_TUPLE_OTHER;
3484 vport[i].rss_tuple_sets.ipv6_udp_en =
3485 HCLGE_RSS_INPUT_TUPLE_OTHER;
3486 vport[i].rss_tuple_sets.ipv6_sctp_en =
3487 HCLGE_RSS_INPUT_TUPLE_SCTP;
3488 vport[i].rss_tuple_sets.ipv6_fragment_en =
3489 HCLGE_RSS_INPUT_TUPLE_OTHER;
3490
3491 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
823fe868
FL		 3492
3493 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
8015bb74
YL		 3494 }
3495
3496 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3497}
3498
63d7e66f
SM		 3499int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3500 int vector_id, bool en,
3501 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3502{
3503 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3504 struct hnae3_ring_chain_node *node;
3505 struct hclge_desc desc;
63d7e66f
SM		 3506 struct hclge_ctrl_vector_chain_cmd *req
3507 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3508 enum hclge_cmd_status status;
3509 enum hclge_opcode_type op;
3510 u16 tqp_type_and_id;
46a3df9f
S		 3511 int i;
3512
63d7e66f
SM		 3513 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3514 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3515 req->int_vector_id = vector_id;
3516
3517 i = 0;
3518 for (node = ring_chain; node; node = node->next) {
63d7e66f 3519 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
928d369a 3520 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3521 HCLGE_INT_TYPE_S,
3522 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
3523 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3524 HCLGE_TQP_ID_S, node->tqp_index);
3525 hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3526 HCLGE_INT_GL_IDX_S,
3527 hnae_get_field(node->int_gl_idx,
3528 HNAE3_RING_GL_IDX_M,
3529 HNAE3_RING_GL_IDX_S));
63d7e66f 3530 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3531 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3532 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
63d7e66f 3533 req->vfid = vport->vport_id;
46a3df9f 3534
63d7e66f
SM		 3535 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3536 if (status) {
46a3df9f
S		 3537 dev_err(&hdev->pdev->dev,
3538 "Map TQP fail, status is %d.\n",
63d7e66f
SM		 3539 status);
3540 return -EIO;
46a3df9f
S		 3541 }
3542 i = 0;
3543
3544 hclge_cmd_setup_basic_desc(&desc,
63d7e66f 3545 op,
46a3df9f
S		 3546 false);
3547 req->int_vector_id = vector_id;
3548 }
3549 }
3550
3551 if (i > 0) {
3552 req->int_cause_num = i;
63d7e66f
SM		 3553 req->vfid = vport->vport_id;
3554 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3555 if (status) {
46a3df9f 3556 dev_err(&hdev->pdev->dev,
63d7e66f
SM		 3557 "Map TQP fail, status is %d.\n", status);
3558 return -EIO;
46a3df9f
S		 3559 }
3560 }
3561
3562 return 0;
3563}
3564
63d7e66f
SM		 3565static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3566 int vector,
3567 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3568{
3569 struct hclge_vport *vport = hclge_get_vport(handle);
3570 struct hclge_dev *hdev = vport->back;
3571 int vector_id;
3572
3573 vector_id = hclge_get_vector_index(hdev, vector);
3574 if (vector_id < 0) {
3575 dev_err(&hdev->pdev->dev,
63d7e66f 3576 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3577 return vector_id;
3578 }
3579
63d7e66f 3580 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3581}
3582
63d7e66f
SM		 3583static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3584 int vector,
3585 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3586{
3587 struct hclge_vport *vport = hclge_get_vport(handle);
3588 struct hclge_dev *hdev = vport->back;
63d7e66f 3589 int vector_id, ret;
46a3df9f 3590
f9637cc2
PL		 3591 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3592 return 0;
3593
46a3df9f
S		 3594 vector_id = hclge_get_vector_index(hdev, vector);
3595 if (vector_id < 0) {
3596 dev_err(&handle->pdev->dev,
3597 "Get vector index fail. ret =%d\n", vector_id);
3598 return vector_id;
3599 }
3600
63d7e66f 3601 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
7412200c 3602 if (ret)
63d7e66f
SM		 3603 dev_err(&handle->pdev->dev,
3604 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3605 vector_id,
3606 ret);
46a3df9f 3607
7412200c 3608 return ret;
46a3df9f
S		 3609}
3610
3611int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3612 struct hclge_promisc_param *param)
3613{
d44f9b63 3614 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3615 struct hclge_desc desc;
3616 int ret;
3617
3618 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3619
d44f9b63 3620 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3621 req->vf_id = param->vf_id;
4771e104
PL		 3622
3623 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3624 * pdev revision(0x20), new revision support them. The
3625 * value of this two fields will not return error when driver
3626 * send command to fireware in revision(0x20).
3627 */
3628 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3629 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3630
3631 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 3632 if (ret) {
46a3df9f
S		 3633 dev_err(&hdev->pdev->dev,
3634 "Set promisc mode fail, status is %d.\n", ret);
930ff2f6 3635 return ret;
3636 }
3637 return 0;
46a3df9f
S		 3638}
3639
3640void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3641 bool en_mc, bool en_bc, int vport_id)
3642{
3643 if (!param)
3644 return;
3645
3646 memset(param, 0, sizeof(struct hclge_promisc_param));
3647 if (en_uc)
3648 param->enable = HCLGE_PROMISC_EN_UC;
3649 if (en_mc)
3650 param->enable |= HCLGE_PROMISC_EN_MC;
3651 if (en_bc)
3652 param->enable |= HCLGE_PROMISC_EN_BC;
3653 param->vf_id = vport_id;
3654}
3655
e8600a3d
PL		 3656static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3657 bool en_mc_pmc)
46a3df9f
S		 3658{
3659 struct hclge_vport *vport = hclge_get_vport(handle);
3660 struct hclge_dev *hdev = vport->back;
3661 struct hclge_promisc_param param;
3662
e8600a3d
PL		 3663 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3664 vport->vport_id);
46a3df9f
S		 3665 hclge_cmd_set_promisc_mode(hdev, &param);
3666}
3667
3668static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3669{
3670 struct hclge_desc desc;
d44f9b63
YL		 3671 struct hclge_config_mac_mode_cmd *req =
3672 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3673 u32 loop_en = 0;
46a3df9f
S		 3674 int ret;
3675
3676 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
928d369a 3677 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3678 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3679 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3680 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3681 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3682 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3683 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3684 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3685 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3686 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3687 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3688 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3689 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3690 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 3691 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3692
3693 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3694 if (ret)
3695 dev_err(&hdev->pdev->dev,
3696 "mac enable fail, ret =%d.\n", ret);
3697}
3698
e67d9ce9 3699static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 3700{
c39c4d98 3701 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 3702 struct hclge_desc desc;
3703 u32 loop_en;
3704 int ret;
3705
e67d9ce9
YL		 3706 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3707 /* 1 Read out the MAC mode config at first */
3708 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3709 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3710 if (ret) {
3711 dev_err(&hdev->pdev->dev,
3712 "mac loopback get fail, ret =%d.\n", ret);
3713 return ret;
3714 }
c39c4d98 3715
e67d9ce9
YL		 3716 /* 2 Then setup the loopback flag */
3717 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
928d369a 3718 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
e67d9ce9
YL		 3719
3720 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 3721
e67d9ce9
YL		 3722 /* 3 Config mac work mode with loopback flag
3723 * and its original configure parameters
3724 */
3725 hclge_cmd_reuse_desc(&desc, false);
3726 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3727 if (ret)
3728 dev_err(&hdev->pdev->dev,
3729 "mac loopback set fail, ret =%d.\n", ret);
3730 return ret;
3731}
c39c4d98 3732
e67d9ce9
YL		 3733static int hclge_set_loopback(struct hnae3_handle *handle,
3734 enum hnae3_loop loop_mode, bool en)
3735{
3736 struct hclge_vport *vport = hclge_get_vport(handle);
3737 struct hclge_dev *hdev = vport->back;
3738 int ret;
3739
3740 switch (loop_mode) {
3741 case HNAE3_MAC_INTER_LOOP_MAC:
3742 ret = hclge_set_mac_loopback(hdev, en);
c39c4d98
YL		 3743 break;
3744 default:
3745 ret = -ENOTSUPP;
3746 dev_err(&hdev->pdev->dev,
3747 "loop_mode %d is not supported\n", loop_mode);
3748 break;
3749 }
3750
3751 return ret;
3752}
3753
46a3df9f
S		 3754static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3755 int stream_id, bool enable)
3756{
3757 struct hclge_desc desc;
d44f9b63
YL		 3758 struct hclge_cfg_com_tqp_queue_cmd *req =
3759 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3760 int ret;
3761
3762 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3763 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3764 req->stream_id = cpu_to_le16(stream_id);
3765 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3766
3767 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3768 if (ret)
3769 dev_err(&hdev->pdev->dev,
3770 "Tqp enable fail, status =%d.\n", ret);
3771 return ret;
3772}
3773
3774static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3775{
3776 struct hclge_vport *vport = hclge_get_vport(handle);
3777 struct hnae3_queue *queue;
3778 struct hclge_tqp *tqp;
3779 int i;
3780
3781 for (i = 0; i < vport->alloc_tqps; i++) {
3782 queue = handle->kinfo.tqp[i];
3783 tqp = container_of(queue, struct hclge_tqp, q);
3784 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3785 }
3786}
3787
3788static int hclge_ae_start(struct hnae3_handle *handle)
3789{
3790 struct hclge_vport *vport = hclge_get_vport(handle);
3791 struct hclge_dev *hdev = vport->back;
e5e89cda 3792 int i, ret;
46a3df9f 3793
e5e89cda
PL		 3794 for (i = 0; i < vport->alloc_tqps; i++)
3795 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3796
46a3df9f
S		 3797 /* mac enable */
3798 hclge_cfg_mac_mode(hdev, true);
3799 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3800 mod_timer(&hdev->service_timer, jiffies + HZ);
3ae84019 3801 hdev->hw.mac.link = 0;
46a3df9f 3802
f9637cc2
PL		 3803 /* reset tqp stats */
3804 hclge_reset_tqp_stats(handle);
3805
46a3df9f
S		 3806 ret = hclge_mac_start_phy(hdev);
3807 if (ret)
3808 return ret;
3809
46a3df9f
S		 3810 return 0;
3811}
3812
3813static void hclge_ae_stop(struct hnae3_handle *handle)
3814{
3815 struct hclge_vport *vport = hclge_get_vport(handle);
3816 struct hclge_dev *hdev = vport->back;
e5e89cda 3817 int i;
46a3df9f 3818
f9637cc2
PL		 3819 del_timer_sync(&hdev->service_timer);
3820 cancel_work_sync(&hdev->service_task);
42b11ab7 3821 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
f9637cc2 3822
4486f5c9
YL		 3823 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3824 hclge_mac_stop_phy(hdev);
f9637cc2 3825 return;
4486f5c9 3826 }
f9637cc2 3827
e5e89cda
PL		 3828 for (i = 0; i < vport->alloc_tqps; i++)
3829 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3830
46a3df9f
S		 3831 /* Mac disable */
3832 hclge_cfg_mac_mode(hdev, false);
3833
3834 hclge_mac_stop_phy(hdev);
3835
3836 /* reset tqp stats */
3837 hclge_reset_tqp_stats(handle);
b91fb71c
FL		 3838 del_timer_sync(&hdev->service_timer);
3839 cancel_work_sync(&hdev->service_task);
3840 hclge_update_link_status(hdev);
46a3df9f
S		 3841}
3842
3843static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3844 u16 cmdq_resp, u8 resp_code,
3845 enum hclge_mac_vlan_tbl_opcode op)
3846{
3847 struct hclge_dev *hdev = vport->back;
3848 int return_status = -EIO;
3849
3850 if (cmdq_resp) {
3851 dev_err(&hdev->pdev->dev,
3852 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3853 cmdq_resp);
3854 return -EIO;
3855 }
3856
3857 if (op == HCLGE_MAC_VLAN_ADD) {
3858 if ((!resp_code) || (resp_code == 1)) {
3859 return_status = 0;
3860 } else if (resp_code == 2) {
2f894c5b 3861 return_status = -ENOSPC;
46a3df9f
S		 3862 dev_err(&hdev->pdev->dev,
3863 "add mac addr failed for uc_overflow.\n");
3864 } else if (resp_code == 3) {
2f894c5b 3865 return_status = -ENOSPC;
46a3df9f
S		 3866 dev_err(&hdev->pdev->dev,
3867 "add mac addr failed for mc_overflow.\n");
3868 } else {
3869 dev_err(&hdev->pdev->dev,
3870 "add mac addr failed for undefined, code=%d.\n",
3871 resp_code);
3872 }
3873 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3874 if (!resp_code) {
3875 return_status = 0;
3876 } else if (resp_code == 1) {
2f894c5b 3877 return_status = -ENOENT;
46a3df9f
S		 3878 dev_dbg(&hdev->pdev->dev,
3879 "remove mac addr failed for miss.\n");
3880 } else {
3881 dev_err(&hdev->pdev->dev,
3882 "remove mac addr failed for undefined, code=%d.\n",
3883 resp_code);
3884 }
3885 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3886 if (!resp_code) {
3887 return_status = 0;
3888 } else if (resp_code == 1) {
2f894c5b 3889 return_status = -ENOENT;
46a3df9f
S		 3890 dev_dbg(&hdev->pdev->dev,
3891 "lookup mac addr failed for miss.\n");
3892 } else {
3893 dev_err(&hdev->pdev->dev,
3894 "lookup mac addr failed for undefined, code=%d.\n",
3895 resp_code);
3896 }
3897 } else {
2f894c5b 3898 return_status = -EINVAL;
46a3df9f
S		 3899 dev_err(&hdev->pdev->dev,
3900 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3901 op);
3902 }
3903
3904 return return_status;
3905}
3906
3907static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3908{
3909 int word_num;
3910 int bit_num;
3911
3912 if (vfid > 255 || vfid < 0)
3913 return -EIO;
3914
3915 if (vfid >= 0 && vfid <= 191) {
3916 word_num = vfid / 32;
3917 bit_num = vfid % 32;
3918 if (clr)
a90bb9a5 3919 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3920 else
a90bb9a5 3921 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3922 } else {
3923 word_num = (vfid - 192) / 32;
3924 bit_num = vfid % 32;
3925 if (clr)
a90bb9a5 3926 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3927 else
a90bb9a5 3928 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3929 }
3930
3931 return 0;
3932}
3933
3934static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3935{
3936#define HCLGE_DESC_NUMBER 3
3937#define HCLGE_FUNC_NUMBER_PER_DESC 6
3938 int i, j;
3939
3940 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3941 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3942 if (desc[i].data[j])
3943 return false;
3944
3945 return true;
3946}
3947
d44f9b63 3948static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3949 const u8 *addr)
3950{
3951 const unsigned char *mac_addr = addr;
3952 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3953 (mac_addr[0]) | (mac_addr[1] << 8);
3954 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3955
3956 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3957 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3958}
3959
1db9b1bf
YL		 3960static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3961 const u8 *addr)
46a3df9f
S		 3962{
3963 u16 high_val = addr[1] | (addr[0] << 8);
3964 struct hclge_dev *hdev = vport->back;
3965 u32 rsh = 4 - hdev->mta_mac_sel_type;
3966 u16 ret_val = (high_val >> rsh) & 0xfff;
3967
3968 return ret_val;
3969}
3970
3971static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3972 enum hclge_mta_dmac_sel_type mta_mac_sel,
3973 bool enable)
3974{
d44f9b63 3975 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3976 struct hclge_desc desc;
3977 int ret;
3978
d44f9b63 3979 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3980 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3981
928d369a 3982 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3983 enable);
3984 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3985 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
46a3df9f
S		 3986
3987 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 3988 if (ret) {
46a3df9f
S		 3989 dev_err(&hdev->pdev->dev,
3990 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3991 ret);
930ff2f6 3992 return ret;
3993 }
46a3df9f 3994
930ff2f6 3995 return 0;
46a3df9f
S		 3996}
3997
3998int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3999 u8 func_id,
4000 bool enable)
4001{
d44f9b63 4002 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 4003 struct hclge_desc desc;
4004 int ret;
4005
d44f9b63 4006 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 4007 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
4008
928d369a 4009 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
4010 enable);
46a3df9f
S		 4011 req->function_id = func_id;
4012
4013 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 4014 if (ret) {
46a3df9f
S		 4015 dev_err(&hdev->pdev->dev,
4016 "Config func_id enable failed for cmd_send, ret =%d.\n",
4017 ret);
930ff2f6 4018 return ret;
4019 }
46a3df9f 4020
930ff2f6 4021 return 0;
46a3df9f
S		 4022}
4023
4024static int hclge_set_mta_table_item(struct hclge_vport *vport,
4025 u16 idx,
4026 bool enable)
4027{
4028 struct hclge_dev *hdev = vport->back;
d44f9b63 4029 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 4030 struct hclge_desc desc;
a90bb9a5 4031 u16 item_idx = 0;
46a3df9f
S		 4032 int ret;
4033
d44f9b63 4034 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f 4035 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
928d369a 4036 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
46a3df9f 4037
928d369a 4038 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
4039 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 4040 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 4041
4042 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4043 if (ret) {
4044 dev_err(&hdev->pdev->dev,
4045 "Config mta table item failed for cmd_send, ret =%d.\n",
4046 ret);
4047 return ret;
4048 }
4049
a832d8b5
XW		 4050 if (enable)
4051 set_bit(idx, vport->mta_shadow);
4052 else
4053 clear_bit(idx, vport->mta_shadow);
4054
46a3df9f
S		 4055 return 0;
4056}
4057
a832d8b5
XW		 4058static int hclge_update_mta_status(struct hnae3_handle *handle)
4059{
4060 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
4061 struct hclge_vport *vport = hclge_get_vport(handle);
4062 struct net_device *netdev = handle->kinfo.netdev;
4063 struct netdev_hw_addr *ha;
4064 u16 tbl_idx;
4065
4066 memset(mta_status, 0, sizeof(mta_status));
4067
4068 /* update mta_status from mc addr list */
4069 netdev_for_each_mc_addr(ha, netdev) {
4070 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
4071 set_bit(tbl_idx, mta_status);
4072 }
4073
4074 return hclge_update_mta_status_common(vport, mta_status,
4075 0, HCLGE_MTA_TBL_SIZE, true);
4076}
4077
4078int hclge_update_mta_status_common(struct hclge_vport *vport,
4079 unsigned long *status,
4080 u16 idx,
4081 u16 count,
4082 bool update_filter)
4083{
4084 struct hclge_dev *hdev = vport->back;
4085 u16 update_max = idx + count;
4086 u16 check_max;
4087 int ret = 0;
4088 bool used;
4089 u16 i;
4090
4091 /* setup mta check range */
4092 if (update_filter) {
4093 i = 0;
4094 check_max = HCLGE_MTA_TBL_SIZE;
4095 } else {
4096 i = idx;
4097 check_max = update_max;
4098 }
4099
4100 used = false;
4101 /* check and update all mta item */
4102 for (; i < check_max; i++) {
4103 /* ignore unused item */
4104 if (!test_bit(i, vport->mta_shadow))
4105 continue;
4106
4107 /* if i in update range then update it */
4108 if (i >= idx && i < update_max)
4109 if (!test_bit(i - idx, status))
4110 hclge_set_mta_table_item(vport, i, false);
4111
4112 if (!used && test_bit(i, vport->mta_shadow))
4113 used = true;
4114 }
4115
4116 /* no longer use mta, disable it */
4117 if (vport->accept_mta_mc && update_filter && !used) {
4118 ret = hclge_cfg_func_mta_filter(hdev,
4119 vport->vport_id,
4120 false);
4121 if (ret)
4122 dev_err(&hdev->pdev->dev,
4123 "disable func mta filter fail ret=%d\n",
4124 ret);
4125 else
4126 vport->accept_mta_mc = false;
4127 }
4128
4129 return ret;
4130}
4131
46a3df9f 4132static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4133 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 4134{
4135 struct hclge_dev *hdev = vport->back;
4136 struct hclge_desc desc;
4137 u8 resp_code;
a90bb9a5 4138 u16 retval;
46a3df9f
S		 4139 int ret;
4140
4141 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4142
d44f9b63 4143 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4144
4145 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4146 if (ret) {
4147 dev_err(&hdev->pdev->dev,
4148 "del mac addr failed for cmd_send, ret =%d.\n",
4149 ret);
4150 return ret;
4151 }
a90bb9a5
YL		 4152 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4153 retval = le16_to_cpu(desc.retval);
46a3df9f 4154
a90bb9a5 4155 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4156 HCLGE_MAC_VLAN_REMOVE);
4157}
4158
4159static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4160 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4161 struct hclge_desc *desc,
4162 bool is_mc)
4163{
4164 struct hclge_dev *hdev = vport->back;
4165 u8 resp_code;
a90bb9a5 4166 u16 retval;
46a3df9f
S		 4167 int ret;
4168
4169 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4170 if (is_mc) {
4171 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4172 memcpy(desc[0].data,
4173 req,
d44f9b63 4174 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4175 hclge_cmd_setup_basic_desc(&desc[1],
4176 HCLGE_OPC_MAC_VLAN_ADD,
4177 true);
4178 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4179 hclge_cmd_setup_basic_desc(&desc[2],
4180 HCLGE_OPC_MAC_VLAN_ADD,
4181 true);
4182 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4183 } else {
4184 memcpy(desc[0].data,
4185 req,
d44f9b63 4186 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4187 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4188 }
4189 if (ret) {
4190 dev_err(&hdev->pdev->dev,
4191 "lookup mac addr failed for cmd_send, ret =%d.\n",
4192 ret);
4193 return ret;
4194 }
a90bb9a5
YL		 4195 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4196 retval = le16_to_cpu(desc[0].retval);
46a3df9f 4197
a90bb9a5 4198 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4199 HCLGE_MAC_VLAN_LKUP);
4200}
4201
4202static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4203 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4204 struct hclge_desc *mc_desc)
4205{
4206 struct hclge_dev *hdev = vport->back;
4207 int cfg_status;
4208 u8 resp_code;
a90bb9a5 4209 u16 retval;
46a3df9f
S		 4210 int ret;
4211
4212 if (!mc_desc) {
4213 struct hclge_desc desc;
4214
4215 hclge_cmd_setup_basic_desc(&desc,
4216 HCLGE_OPC_MAC_VLAN_ADD,
4217 false);
d44f9b63
YL		 4218 memcpy(desc.data, req,
4219 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4220 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 4221 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4222 retval = le16_to_cpu(desc.retval);
4223
4224 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4225 resp_code,
4226 HCLGE_MAC_VLAN_ADD);
4227 } else {
c3b6f755 4228 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 4229 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4230 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 4231 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4232 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 4233 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4234 memcpy(mc_desc[0].data, req,
d44f9b63 4235 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4236 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 4237 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4238 retval = le16_to_cpu(mc_desc[0].retval);
4239
4240 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4241 resp_code,
4242 HCLGE_MAC_VLAN_ADD);
4243 }
4244
4245 if (ret) {
4246 dev_err(&hdev->pdev->dev,
4247 "add mac addr failed for cmd_send, ret =%d.\n",
4248 ret);
4249 return ret;
4250 }
4251
4252 return cfg_status;
4253}
4254
4255static int hclge_add_uc_addr(struct hnae3_handle *handle,
4256 const unsigned char *addr)
4257{
4258 struct hclge_vport *vport = hclge_get_vport(handle);
4259
4260 return hclge_add_uc_addr_common(vport, addr);
4261}
4262
4263int hclge_add_uc_addr_common(struct hclge_vport *vport,
4264 const unsigned char *addr)
4265{
4266 struct hclge_dev *hdev = vport->back;
d44f9b63 4267 struct hclge_mac_vlan_tbl_entry_cmd req;
bf88f41f 4268 struct hclge_desc desc;
a90bb9a5 4269 u16 egress_port = 0;
04f0c72a 4270 int ret;
46a3df9f
S		 4271
4272 /* mac addr check */
4273 if (is_zero_ether_addr(addr) ||
4274 is_broadcast_ether_addr(addr) ||
4275 is_multicast_ether_addr(addr)) {
4276 dev_err(&hdev->pdev->dev,
4277 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4278 addr,
4279 is_zero_ether_addr(addr),
4280 is_broadcast_ether_addr(addr),
4281 is_multicast_ether_addr(addr));
4282 return -EINVAL;
4283 }
4284
4285 memset(&req, 0, sizeof(req));
928d369a 4286 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
98529d42 4287 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4288 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4289 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
a90bb9a5 4290
98529d42 4291 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4292 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
928d369a 4293 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4294 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
98529d42 4295 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
4296 HCLGE_MAC_EPORT_PFID_S, 0);
a90bb9a5
YL		 4297
4298 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4299
4300 hclge_prepare_mac_addr(&req, addr);
4301
bf88f41f
JS		 4302 /* Lookup the mac address in the mac_vlan table, and add
4303 * it if the entry is inexistent. Repeated unicast entry
4304 * is not allowed in the mac vlan table.
4305 */
4306 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4307 if (ret == -ENOENT)
4308 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4309
4310 /* check if we just hit the duplicate */
4311 if (!ret)
4312 ret = -EINVAL;
4313
4314 dev_err(&hdev->pdev->dev,
4315 "PF failed to add unicast entry(%pM) in the MAC table\n",
4316 addr);
46a3df9f 4317
04f0c72a 4318 return ret;
46a3df9f
S		 4319}
4320
4321static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4322 const unsigned char *addr)
4323{
4324 struct hclge_vport *vport = hclge_get_vport(handle);
4325
4326 return hclge_rm_uc_addr_common(vport, addr);
4327}
4328
4329int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4330 const unsigned char *addr)
4331{
4332 struct hclge_dev *hdev = vport->back;
d44f9b63 4333 struct hclge_mac_vlan_tbl_entry_cmd req;
04f0c72a 4334 int ret;
46a3df9f
S		 4335
4336 /* mac addr check */
4337 if (is_zero_ether_addr(addr) ||
4338 is_broadcast_ether_addr(addr) ||
4339 is_multicast_ether_addr(addr)) {
4340 dev_dbg(&hdev->pdev->dev,
4341 "Remove mac err! invalid mac:%pM.\n",
4342 addr);
4343 return -EINVAL;
4344 }
4345
4346 memset(&req, 0, sizeof(req));
928d369a 4347 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4348 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 4349 hclge_prepare_mac_addr(&req, addr);
04f0c72a 4350 ret = hclge_remove_mac_vlan_tbl(vport, &req);
46a3df9f 4351
04f0c72a 4352 return ret;
46a3df9f
S		 4353}
4354
4355static int hclge_add_mc_addr(struct hnae3_handle *handle,
4356 const unsigned char *addr)
4357{
4358 struct hclge_vport *vport = hclge_get_vport(handle);
4359
27e6804f 4360 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 4361}
4362
4363int hclge_add_mc_addr_common(struct hclge_vport *vport,
4364 const unsigned char *addr)
4365{
4366 struct hclge_dev *hdev = vport->back;
d44f9b63 4367 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4368 struct hclge_desc desc[3];
4369 u16 tbl_idx;
4370 int status;
4371
4372 /* mac addr check */
4373 if (!is_multicast_ether_addr(addr)) {
4374 dev_err(&hdev->pdev->dev,
4375 "Add mc mac err! invalid mac:%pM.\n",
4376 addr);
4377 return -EINVAL;
4378 }
4379 memset(&req, 0, sizeof(req));
928d369a 4380 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4381 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4382 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4383 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f
S		 4384 hclge_prepare_mac_addr(&req, addr);
4385 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4386 if (!status) {
4387 /* This mac addr exist, update VFID for it */
4388 hclge_update_desc_vfid(desc, vport->vport_id, false);
4389 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4390 } else {
4391 /* This mac addr do not exist, add new entry for it */
4392 memset(desc[0].data, 0, sizeof(desc[0].data));
4393 memset(desc[1].data, 0, sizeof(desc[0].data));
4394 memset(desc[2].data, 0, sizeof(desc[0].data));
4395 hclge_update_desc_vfid(desc, vport->vport_id, false);
4396 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4397 }
4398
a832d8b5
XW		 4399 /* If mc mac vlan table is full, use MTA table */
4400 if (status == -ENOSPC) {
4401 if (!vport->accept_mta_mc) {
4402 status = hclge_cfg_func_mta_filter(hdev,
4403 vport->vport_id,
4404 true);
4405 if (status) {
4406 dev_err(&hdev->pdev->dev,
4407 "set mta filter mode fail ret=%d\n",
4408 status);
4409 return status;
4410 }
4411 vport->accept_mta_mc = true;
4412 }
4413
4414 /* Set MTA table for this MAC address */
4415 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4416 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4417 }
46a3df9f
S		 4418
4419 return status;
4420}
4421
4422static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4423 const unsigned char *addr)
4424{
4425 struct hclge_vport *vport = hclge_get_vport(handle);
4426
4427 return hclge_rm_mc_addr_common(vport, addr);
4428}
4429
4430int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4431 const unsigned char *addr)
4432{
4433 struct hclge_dev *hdev = vport->back;
d44f9b63 4434 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4435 enum hclge_cmd_status status;
4436 struct hclge_desc desc[3];
46a3df9f
S		 4437
4438 /* mac addr check */
4439 if (!is_multicast_ether_addr(addr)) {
4440 dev_dbg(&hdev->pdev->dev,
4441 "Remove mc mac err! invalid mac:%pM.\n",
4442 addr);
4443 return -EINVAL;
4444 }
4445
4446 memset(&req, 0, sizeof(req));
928d369a 4447 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4448 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4449 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4450 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f
S		 4451 hclge_prepare_mac_addr(&req, addr);
4452 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4453 if (!status) {
4454 /* This mac addr exist, remove this handle's VFID for it */
4455 hclge_update_desc_vfid(desc, vport->vport_id, true);
4456
4457 if (hclge_is_all_function_id_zero(desc))
4458 /* All the vfid is zero, so need to delete this entry */
4459 status = hclge_remove_mac_vlan_tbl(vport, &req);
4460 else
4461 /* Not all the vfid is zero, update the vfid */
4462 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4463
4464 } else {
a832d8b5
XW		 4465 /* Maybe this mac address is in mta table, but it cannot be
4466 * deleted here because an entry of mta represents an address
4467 * range rather than a specific address. the delete action to
4468 * all entries will take effect in update_mta_status called by
4469 * hns3_nic_set_rx_mode.
4470 */
4471 status = 0;
46a3df9f
S		 4472 }
4473
46a3df9f
S		 4474 return status;
4475}
4476
635bfb58
FL		 4477static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4478 u16 cmdq_resp, u8 resp_code)
4479{
4480#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4481#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4482#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4483#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4484
4485 int return_status;
4486
4487 if (cmdq_resp) {
4488 dev_err(&hdev->pdev->dev,
4489 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4490 cmdq_resp);
4491 return -EIO;
4492 }
4493
4494 switch (resp_code) {
4495 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4496 case HCLGE_ETHERTYPE_ALREADY_ADD:
4497 return_status = 0;
4498 break;
4499 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4500 dev_err(&hdev->pdev->dev,
4501 "add mac ethertype failed for manager table overflow.\n");
4502 return_status = -EIO;
4503 break;
4504 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4505 dev_err(&hdev->pdev->dev,
4506 "add mac ethertype failed for key conflict.\n");
4507 return_status = -EIO;
4508 break;
4509 default:
4510 dev_err(&hdev->pdev->dev,
4511 "add mac ethertype failed for undefined, code=%d.\n",
4512 resp_code);
4513 return_status = -EIO;
4514 }
4515
4516 return return_status;
4517}
4518
4519static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4520 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4521{
4522 struct hclge_desc desc;
4523 u8 resp_code;
4524 u16 retval;
4525 int ret;
4526
4527 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4528 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4529
4530 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4531 if (ret) {
4532 dev_err(&hdev->pdev->dev,
4533 "add mac ethertype failed for cmd_send, ret =%d.\n",
4534 ret);
4535 return ret;
4536 }
4537
4538 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4539 retval = le16_to_cpu(desc.retval);
4540
4541 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4542}
4543
4544static int init_mgr_tbl(struct hclge_dev *hdev)
4545{
4546 int ret;
4547 int i;
4548
4549 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4550 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4551 if (ret) {
4552 dev_err(&hdev->pdev->dev,
4553 "add mac ethertype failed, ret =%d.\n",
4554 ret);
4555 return ret;
4556 }
4557 }
4558
4559 return 0;
4560}
4561
46a3df9f
S		 4562static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4563{
4564 struct hclge_vport *vport = hclge_get_vport(handle);
4565 struct hclge_dev *hdev = vport->back;
4566
4567 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4568}
4569
3cbf5e2d
FL		 4570static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4571 bool is_first)
46a3df9f
S		 4572{
4573 const unsigned char *new_addr = (const unsigned char *)p;
4574 struct hclge_vport *vport = hclge_get_vport(handle);
4575 struct hclge_dev *hdev = vport->back;
20a5c4c0 4576 int ret;
46a3df9f
S		 4577
4578 /* mac addr check */
4579 if (is_zero_ether_addr(new_addr) ||
4580 is_broadcast_ether_addr(new_addr) ||
4581 is_multicast_ether_addr(new_addr)) {
4582 dev_err(&hdev->pdev->dev,
4583 "Change uc mac err! invalid mac:%p.\n",
4584 new_addr);
4585 return -EINVAL;
4586 }
4587
3cbf5e2d 4588 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 4589 dev_warn(&hdev->pdev->dev,
3cbf5e2d 4590 "remove old uc mac address fail.\n");
46a3df9f 4591
20a5c4c0
FL		 4592 ret = hclge_add_uc_addr(handle, new_addr);
4593 if (ret) {
4594 dev_err(&hdev->pdev->dev,
4595 "add uc mac address fail, ret =%d.\n",
4596 ret);
4597
3cbf5e2d
FL		 4598 if (!is_first &&
4599 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 4600 dev_err(&hdev->pdev->dev,
3cbf5e2d 4601 "restore uc mac address fail.\n");
20a5c4c0
FL		 4602
4603 return -EIO;
46a3df9f
S		 4604 }
4605
532fdd5e 4606 ret = hclge_pause_addr_cfg(hdev, new_addr);
20a5c4c0
FL		 4607 if (ret) {
4608 dev_err(&hdev->pdev->dev,
4609 "configure mac pause address fail, ret =%d.\n",
4610 ret);
4611 return -EIO;
4612 }
4613
4614 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4615
4616 return 0;
46a3df9f
S		 4617}
4618
4619static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4620 bool filter_en)
4621{
d44f9b63 4622 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4623 struct hclge_desc desc;
4624 int ret;
4625
4626 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4627
d44f9b63 4628 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4629 req->vlan_type = vlan_type;
4630 req->vlan_fe = filter_en;
4631
4632 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 4633 if (ret) {
46a3df9f
S		 4634 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4635 ret);
930ff2f6 4636 return ret;
4637 }
46a3df9f 4638
930ff2f6 4639 return 0;
46a3df9f
S		 4640}
4641
d818396d
JS		 4642#define HCLGE_FILTER_TYPE_VF 0
4643#define HCLGE_FILTER_TYPE_PORT 1
4644
4645static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4646{
4647 struct hclge_vport *vport = hclge_get_vport(handle);
4648 struct hclge_dev *hdev = vport->back;
4649
4650 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4651}
4652
4e66632d
YL		 4653static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4654 bool is_kill, u16 vlan, u8 qos,
4655 __be16 proto)
46a3df9f
S		 4656{
4657#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4658 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4659 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4660 struct hclge_desc desc[2];
4661 u8 vf_byte_val;
4662 u8 vf_byte_off;
4663 int ret;
4664
4665 hclge_cmd_setup_basic_desc(&desc[0],
4666 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4667 hclge_cmd_setup_basic_desc(&desc[1],
4668 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4669
4670 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4671
4672 vf_byte_off = vfid / 8;
4673 vf_byte_val = 1 << (vfid % 8);
4674
d44f9b63
YL		 4675 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4676 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4677
a90bb9a5 4678 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4679 req0->vlan_cfg = is_kill;
4680
4681 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4682 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4683 else
4684 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4685
4686 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4687 if (ret) {
4688 dev_err(&hdev->pdev->dev,
4689 "Send vf vlan command fail, ret =%d.\n",
4690 ret);
4691 return ret;
4692 }
4693
4694 if (!is_kill) {
715d610d 4695#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 4696 if (!req0->resp_code || req0->resp_code == 1)
4697 return 0;
4698
715d610d
YL		 4699 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4700 dev_warn(&hdev->pdev->dev,
4701 "vf vlan table is full, vf vlan filter is disabled\n");
4702 return 0;
4703 }
4704
46a3df9f
S		 4705 dev_err(&hdev->pdev->dev,
4706 "Add vf vlan filter fail, ret =%d.\n",
4707 req0->resp_code);
4708 } else {
4709 if (!req0->resp_code)
4710 return 0;
4711
4712 dev_err(&hdev->pdev->dev,
4713 "Kill vf vlan filter fail, ret =%d.\n",
4714 req0->resp_code);
4715 }
4716
4717 return -EIO;
4718}
4719
4e66632d
YL		 4720static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4721 u16 vlan_id, bool is_kill)
46a3df9f 4722{
d44f9b63 4723 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4724 struct hclge_desc desc;
4725 u8 vlan_offset_byte_val;
4726 u8 vlan_offset_byte;
4727 u8 vlan_offset_160;
4728 int ret;
4729
4730 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4731
4732 vlan_offset_160 = vlan_id / 160;
4733 vlan_offset_byte = (vlan_id % 160) / 8;
4734 vlan_offset_byte_val = 1 << (vlan_id % 8);
4735
d44f9b63 4736 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4737 req->vlan_offset = vlan_offset_160;
4738 req->vlan_cfg = is_kill;
4739 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4740
4741 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4e66632d
YL		 4742 if (ret)
4743 dev_err(&hdev->pdev->dev,
4744 "port vlan command, send fail, ret =%d.\n", ret);
4745 return ret;
4746}
4747
4748static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4749 u16 vport_id, u16 vlan_id, u8 qos,
4750 bool is_kill)
4751{
4752 u16 vport_idx, vport_num = 0;
4753 int ret;
4754
4755 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4756 0, proto);
46a3df9f
S		 4757 if (ret) {
4758 dev_err(&hdev->pdev->dev,
4e66632d
YL		 4759 "Set %d vport vlan filter config fail, ret =%d.\n",
4760 vport_id, ret);
46a3df9f
S		 4761 return ret;
4762 }
4763
4e66632d
YL		 4764 /* vlan 0 may be added twice when 8021q module is enabled */
4765 if (!is_kill && !vlan_id &&
4766 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4767 return 0;
4768
4769 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 4770 dev_err(&hdev->pdev->dev,
4e66632d
YL		 4771 "Add port vlan failed, vport %d is already in vlan %d\n",
4772 vport_id, vlan_id);
4773 return -EINVAL;
46a3df9f
S		 4774 }
4775
4e66632d
YL		 4776 if (is_kill &&
4777 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4778 dev_err(&hdev->pdev->dev,
4779 "Delete port vlan failed, vport %d is not in vlan %d\n",
4780 vport_id, vlan_id);
4781 return -EINVAL;
4782 }
4783
4784 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID)
4785 vport_num++;
4786
4787 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4788 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4789 is_kill);
4790
4791 return ret;
4792}
4793
4794int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4795 u16 vlan_id, bool is_kill)
4796{
4797 struct hclge_vport *vport = hclge_get_vport(handle);
4798 struct hclge_dev *hdev = vport->back;
4799
4800 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4801 0, is_kill);
46a3df9f
S		 4802}
4803
4804static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4805 u16 vlan, u8 qos, __be16 proto)
4806{
4807 struct hclge_vport *vport = hclge_get_vport(handle);
4808 struct hclge_dev *hdev = vport->back;
4809
4810 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4811 return -EINVAL;
4812 if (proto != htons(ETH_P_8021Q))
4813 return -EPROTONOSUPPORT;
4814
4e66632d 4815 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 4816}
4817
e62f2a6b
PL		 4818static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4819{
4820 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4821 struct hclge_vport_vtag_tx_cfg_cmd *req;
4822 struct hclge_dev *hdev = vport->back;
4823 struct hclge_desc desc;
4824 int status;
4825
4826 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4827
4828 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4829 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4830 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
928d369a 4831 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
b75b1a56 4832 vcfg->accept_tag1 ? 1 : 0);
928d369a 4833 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
b75b1a56 4834 vcfg->accept_untag1 ? 1 : 0);
928d369a 4835 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
b75b1a56 4836 vcfg->accept_tag2 ? 1 : 0);
928d369a 4837 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
b75b1a56 4838 vcfg->accept_untag2 ? 1 : 0);
928d369a 4839 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
e62f2a6b 4840 vcfg->insert_tag1_en ? 1 : 0);
928d369a 4841 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
e62f2a6b 4842 vcfg->insert_tag2_en ? 1 : 0);
928d369a 4843 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
e62f2a6b
PL		 4844
4845 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4846 req->vf_bitmap[req->vf_offset] =
4847 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4848
4849 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4850 if (status)
4851 dev_err(&hdev->pdev->dev,
4852 "Send port txvlan cfg command fail, ret =%d\n",
4853 status);
4854
4855 return status;
4856}
4857
4858static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4859{
4860 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4861 struct hclge_vport_vtag_rx_cfg_cmd *req;
4862 struct hclge_dev *hdev = vport->back;
4863 struct hclge_desc desc;
4864 int status;
4865
4866 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4867
4868 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
928d369a 4869 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4870 vcfg->strip_tag1_en ? 1 : 0);
4871 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4872 vcfg->strip_tag2_en ? 1 : 0);
4873 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4874 vcfg->vlan1_vlan_prionly ? 1 : 0);
4875 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4876 vcfg->vlan2_vlan_prionly ? 1 : 0);
e62f2a6b
PL		 4877
4878 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4879 req->vf_bitmap[req->vf_offset] =
4880 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4881
4882 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4883 if (status)
4884 dev_err(&hdev->pdev->dev,
4885 "Send port rxvlan cfg command fail, ret =%d\n",
4886 status);
4887
4888 return status;
4889}
4890
4891static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4892{
4893 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4894 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4895 struct hclge_desc desc;
4896 int status;
4897
4898 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4899 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4900 rx_req->ot_fst_vlan_type =
4901 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4902 rx_req->ot_sec_vlan_type =
4903 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4904 rx_req->in_fst_vlan_type =
4905 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4906 rx_req->in_sec_vlan_type =
4907 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4908
4909 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4910 if (status) {
4911 dev_err(&hdev->pdev->dev,
4912 "Send rxvlan protocol type command fail, ret =%d\n",
4913 status);
4914 return status;
4915 }
4916
4917 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4918
4919 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4920 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4921 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4922
4923 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4924 if (status)
4925 dev_err(&hdev->pdev->dev,
4926 "Send txvlan protocol type command fail, ret =%d\n",
4927 status);
4928
4929 return status;
4930}
4931
46a3df9f
S		 4932static int hclge_init_vlan_config(struct hclge_dev *hdev)
4933{
e62f2a6b
PL		 4934#define HCLGE_DEF_VLAN_TYPE 0x8100
4935
5e43aef8 4936 struct hnae3_handle *handle;
e62f2a6b 4937 struct hclge_vport *vport;
46a3df9f 4938 int ret;
e62f2a6b
PL		 4939 int i;
4940
4941 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4942 if (ret)
4943 return ret;
46a3df9f 4944
e62f2a6b 4945 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4946 if (ret)
4947 return ret;
4948
e62f2a6b
PL		 4949 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4950 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4951 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4952 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4953 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4954 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4955
4956 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4957 if (ret)
4958 return ret;
46a3df9f 4959
e62f2a6b
PL		 4960 for (i = 0; i < hdev->num_alloc_vport; i++) {
4961 vport = &hdev->vport[i];
b75b1a56
PL		 4962 vport->txvlan_cfg.accept_tag1 = true;
4963 vport->txvlan_cfg.accept_untag1 = true;
4964
4965 /* accept_tag2 and accept_untag2 are not supported on
4966 * pdev revision(0x20), new revision support them. The
4967 * value of this two fields will not return error when driver
4968 * send command to fireware in revision(0x20).
4969 * This two fields can not configured by user.
4970 */
4971 vport->txvlan_cfg.accept_tag2 = true;
4972 vport->txvlan_cfg.accept_untag2 = true;
4973
e62f2a6b
PL		 4974 vport->txvlan_cfg.insert_tag1_en = false;
4975 vport->txvlan_cfg.insert_tag2_en = false;
4976 vport->txvlan_cfg.default_tag1 = 0;
4977 vport->txvlan_cfg.default_tag2 = 0;
4978
4979 ret = hclge_set_vlan_tx_offload_cfg(vport);
4980 if (ret)
4981 return ret;
4982
4983 vport->rxvlan_cfg.strip_tag1_en = false;
4984 vport->rxvlan_cfg.strip_tag2_en = true;
4985 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4986 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4987
4988 ret = hclge_set_vlan_rx_offload_cfg(vport);
4989 if (ret)
4990 return ret;
4991 }
4992
5e43aef8 4993 handle = &hdev->vport[0].nic;
4e66632d 4994 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4995}
4996
3849d494 4997int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
5f9a7732
PL		 4998{
4999 struct hclge_vport *vport = hclge_get_vport(handle);
5000
5001 vport->rxvlan_cfg.strip_tag1_en = false;
5002 vport->rxvlan_cfg.strip_tag2_en = enable;
5003 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
5004 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
5005
5006 return hclge_set_vlan_rx_offload_cfg(vport);
5007}
5008
12341881 5009static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 5010{
d44f9b63 5011 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 5012 struct hclge_desc desc;
7393ed39 5013 int max_frm_size;
46a3df9f
S		 5014 int ret;
5015
7393ed39
FL		 5016 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5017
5018 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
5019 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 5020 return -EINVAL;
5021
7393ed39
FL		 5022 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
5023
46a3df9f
S		 5024 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
5025
d44f9b63 5026 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
7393ed39 5027 req->max_frm_size = cpu_to_le16(max_frm_size);
46a3df9f
S		 5028
5029 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 5030 if (ret) {
46a3df9f 5031 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
930ff2f6 5032 return ret;
5033 }
7393ed39 5034
930ff2f6 5035 hdev->mps = max_frm_size;
5036
5037 return 0;
46a3df9f
S		 5038}
5039
12341881
FL		 5040static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
5041{
5042 struct hclge_vport *vport = hclge_get_vport(handle);
5043 struct hclge_dev *hdev = vport->back;
5044 int ret;
5045
5046 ret = hclge_set_mac_mtu(hdev, new_mtu);
5047 if (ret) {
5048 dev_err(&hdev->pdev->dev,
5049 "Change mtu fail, ret =%d\n", ret);
5050 return ret;
5051 }
5052
5053 ret = hclge_buffer_alloc(hdev);
5054 if (ret)
5055 dev_err(&hdev->pdev->dev,
5056 "Allocate buffer fail, ret =%d\n", ret);
5057
5058 return ret;
5059}
5060
46a3df9f
S		 5061static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
5062 bool enable)
5063{
d44f9b63 5064 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5065 struct hclge_desc desc;
5066 int ret;
5067
5068 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
5069
d44f9b63 5070 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 5071 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
928d369a 5072 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 5073
5074 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5075 if (ret) {
5076 dev_err(&hdev->pdev->dev,
5077 "Send tqp reset cmd error, status =%d\n", ret);
5078 return ret;
5079 }
5080
5081 return 0;
5082}
5083
5084static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
5085{
d44f9b63 5086 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5087 struct hclge_desc desc;
5088 int ret;
5089
5090 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
5091
d44f9b63 5092 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 5093 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5094
5095 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5096 if (ret) {
5097 dev_err(&hdev->pdev->dev,
5098 "Get reset status error, status =%d\n", ret);
5099 return ret;
5100 }
5101
928d369a 5102 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 5103}
5104
e5e89cda
PL		 5105static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
5106 u16 queue_id)
5107{
5108 struct hnae3_queue *queue;
5109 struct hclge_tqp *tqp;
5110
5111 queue = handle->kinfo.tqp[queue_id];
5112 tqp = container_of(queue, struct hclge_tqp, q);
5113
5114 return tqp->index;
5115}
5116
63d7e66f 5117void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 5118{
5119 struct hclge_vport *vport = hclge_get_vport(handle);
5120 struct hclge_dev *hdev = vport->back;
5121 int reset_try_times = 0;
5122 int reset_status;
e5e89cda 5123 u16 queue_gid;
46a3df9f
S		 5124 int ret;
5125
f9637cc2
PL		 5126 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5127 return;
5128
e5e89cda
PL		 5129 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
5130
46a3df9f
S		 5131 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
5132 if (ret) {
5133 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
5134 return;
5135 }
5136
e5e89cda 5137 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 5138 if (ret) {
5139 dev_warn(&hdev->pdev->dev,
5140 "Send reset tqp cmd fail, ret = %d\n", ret);
5141 return;
5142 }
5143
5144 reset_try_times = 0;
5145 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5146 /* Wait for tqp hw reset */
5147 msleep(20);
e5e89cda 5148 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 5149 if (reset_status)
5150 break;
5151 }
5152
5153 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5154 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5155 return;
5156 }
5157
e5e89cda 5158 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 5159 if (ret) {
5160 dev_warn(&hdev->pdev->dev,
5161 "Deassert the soft reset fail, ret = %d\n", ret);
5162 return;
5163 }
5164}
5165
d3ea7fc4
PL		 5166void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
5167{
5168 struct hclge_dev *hdev = vport->back;
5169 int reset_try_times = 0;
5170 int reset_status;
5171 u16 queue_gid;
5172 int ret;
5173
5174 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
5175
5176 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5177 if (ret) {
5178 dev_warn(&hdev->pdev->dev,
5179 "Send reset tqp cmd fail, ret = %d\n", ret);
5180 return;
5181 }
5182
5183 reset_try_times = 0;
5184 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5185 /* Wait for tqp hw reset */
5186 msleep(20);
5187 reset_status = hclge_get_reset_status(hdev, queue_gid);
5188 if (reset_status)
5189 break;
5190 }
5191
5192 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5193 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5194 return;
5195 }
5196
5197 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5198 if (ret)
5199 dev_warn(&hdev->pdev->dev,
5200 "Deassert the soft reset fail, ret = %d\n", ret);
5201}
5202
46a3df9f
S		 5203static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5204{
5205 struct hclge_vport *vport = hclge_get_vport(handle);
5206 struct hclge_dev *hdev = vport->back;
5207
5208 return hdev->fw_version;
5209}
5210
a2cfbadb
PL		 5211static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5212 u32 *flowctrl_adv)
5213{
5214 struct hclge_vport *vport = hclge_get_vport(handle);
5215 struct hclge_dev *hdev = vport->back;
5216 struct phy_device *phydev = hdev->hw.mac.phydev;
5217
5218 if (!phydev)
5219 return;
5220
5221 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5222 (phydev->advertising & ADVERTISED_Asym_Pause);
5223}
5224
09ea401e
PL		 5225static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5226{
5227 struct phy_device *phydev = hdev->hw.mac.phydev;
5228
5229 if (!phydev)
5230 return;
5231
5232 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
5233
5234 if (rx_en)
5235 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5236
5237 if (tx_en)
5238 phydev->advertising ^= ADVERTISED_Asym_Pause;
5239}
5240
5241static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5242{
09ea401e
PL		 5243 int ret;
5244
5245 if (rx_en && tx_en)
7a28a82a 5246 hdev->fc_mode_last_time = HCLGE_FC_FULL;
09ea401e 5247 else if (rx_en && !tx_en)
7a28a82a 5248 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
09ea401e 5249 else if (!rx_en && tx_en)
7a28a82a 5250 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
09ea401e 5251 else
7a28a82a 5252 hdev->fc_mode_last_time = HCLGE_FC_NONE;
09ea401e 5253
7a28a82a 5254 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
09ea401e 5255 return 0;
09ea401e
PL		 5256
5257 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
5258 if (ret) {
5259 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
5260 ret);
5261 return ret;
5262 }
5263
7a28a82a 5264 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
09ea401e
PL		 5265
5266 return 0;
5267}
5268
6282f2ea
PL		 5269int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5270{
5271 struct phy_device *phydev = hdev->hw.mac.phydev;
5272 u16 remote_advertising = 0;
5273 u16 local_advertising = 0;
5274 u32 rx_pause, tx_pause;
5275 u8 flowctl;
5276
5277 if (!phydev->link || !phydev->autoneg)
5278 return 0;
5279
5280 if (phydev->advertising & ADVERTISED_Pause)
5281 local_advertising = ADVERTISE_PAUSE_CAP;
5282
5283 if (phydev->advertising & ADVERTISED_Asym_Pause)
5284 local_advertising |= ADVERTISE_PAUSE_ASYM;
5285
5286 if (phydev->pause)
5287 remote_advertising = LPA_PAUSE_CAP;
5288
5289 if (phydev->asym_pause)
5290 remote_advertising |= LPA_PAUSE_ASYM;
5291
5292 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5293 remote_advertising);
5294 tx_pause = flowctl & FLOW_CTRL_TX;
5295 rx_pause = flowctl & FLOW_CTRL_RX;
5296
5297 if (phydev->duplex == HCLGE_MAC_HALF) {
5298 tx_pause = 0;
5299 rx_pause = 0;
5300 }
5301
5302 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5303}
5304
46a3df9f
S		 5305static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5306 u32 *rx_en, u32 *tx_en)
5307{
5308 struct hclge_vport *vport = hclge_get_vport(handle);
5309 struct hclge_dev *hdev = vport->back;
5310
5311 *auto_neg = hclge_get_autoneg(handle);
5312
5313 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5314 *rx_en = 0;
5315 *tx_en = 0;
5316 return;
5317 }
5318
5319 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5320 *rx_en = 1;
5321 *tx_en = 0;
5322 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5323 *tx_en = 1;
5324 *rx_en = 0;
5325 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5326 *rx_en = 1;
5327 *tx_en = 1;
5328 } else {
5329 *rx_en = 0;
5330 *tx_en = 0;
5331 }
5332}
5333
09ea401e
PL		 5334static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5335 u32 rx_en, u32 tx_en)
5336{
5337 struct hclge_vport *vport = hclge_get_vport(handle);
5338 struct hclge_dev *hdev = vport->back;
5339 struct phy_device *phydev = hdev->hw.mac.phydev;
5340 u32 fc_autoneg;
5341
09ea401e
PL		 5342 fc_autoneg = hclge_get_autoneg(handle);
5343 if (auto_neg != fc_autoneg) {
5344 dev_info(&hdev->pdev->dev,
5345 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5346 return -EOPNOTSUPP;
5347 }
5348
5349 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5350 dev_info(&hdev->pdev->dev,
5351 "Priority flow control enabled. Cannot set link flow control.\n");
5352 return -EOPNOTSUPP;
5353 }
5354
5355 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5356
5357 if (!fc_autoneg)
5358 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5359
bef24782
FL		 5360 /* Only support flow control negotiation for netdev with
5361 * phy attached for now.
5362 */
5363 if (!phydev)
5364 return -EOPNOTSUPP;
5365
09ea401e
PL		 5366 return phy_start_aneg(phydev);
5367}
5368
46a3df9f
S		 5369static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5370 u8 *auto_neg, u32 *speed, u8 *duplex)
5371{
5372 struct hclge_vport *vport = hclge_get_vport(handle);
5373 struct hclge_dev *hdev = vport->back;
5374
5375 if (speed)
5376 *speed = hdev->hw.mac.speed;
5377 if (duplex)
5378 *duplex = hdev->hw.mac.duplex;
5379 if (auto_neg)
5380 *auto_neg = hdev->hw.mac.autoneg;
5381}
5382
5383static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5384{
5385 struct hclge_vport *vport = hclge_get_vport(handle);
5386 struct hclge_dev *hdev = vport->back;
5387
5388 if (media_type)
5389 *media_type = hdev->hw.mac.media_type;
5390}
5391
5392static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5393 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5394{
5395 struct hclge_vport *vport = hclge_get_vport(handle);
5396 struct hclge_dev *hdev = vport->back;
5397 struct phy_device *phydev = hdev->hw.mac.phydev;
5398 int mdix_ctrl, mdix, retval, is_resolved;
5399
5400 if (!phydev) {
5401 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5402 *tp_mdix = ETH_TP_MDI_INVALID;
5403 return;
5404 }
5405
5406 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5407
5408 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
928d369a 5409 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5410 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 5411
5412 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
928d369a 5413 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5414 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 5415
5416 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5417
5418 switch (mdix_ctrl) {
5419 case 0x0:
5420 *tp_mdix_ctrl = ETH_TP_MDI;
5421 break;
5422 case 0x1:
5423 *tp_mdix_ctrl = ETH_TP_MDI_X;
5424 break;
5425 case 0x3:
5426 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5427 break;
5428 default:
5429 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5430 break;
5431 }
5432
5433 if (!is_resolved)
5434 *tp_mdix = ETH_TP_MDI_INVALID;
5435 else if (mdix)
5436 *tp_mdix = ETH_TP_MDI_X;
5437 else
5438 *tp_mdix = ETH_TP_MDI;
5439}
5440
5441static int hclge_init_client_instance(struct hnae3_client *client,
5442 struct hnae3_ae_dev *ae_dev)
5443{
5444 struct hclge_dev *hdev = ae_dev->priv;
5445 struct hclge_vport *vport;
5446 int i, ret;
5447
5448 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5449 vport = &hdev->vport[i];
5450
5451 switch (client->type) {
5452 case HNAE3_CLIENT_KNIC:
5453
5454 hdev->nic_client = client;
5455 vport->nic.client = client;
5456 ret = client->ops->init_instance(&vport->nic);
5457 if (ret)
6f636872 5458 return ret;
46a3df9f
S		 5459
5460 if (hdev->roce_client &&
e92a0843 5461 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5462 struct hnae3_client *rc = hdev->roce_client;
5463
5464 ret = hclge_init_roce_base_info(vport);
5465 if (ret)
6f636872 5466 return ret;
46a3df9f
S		 5467
5468 ret = rc->ops->init_instance(&vport->roce);
5469 if (ret)
6f636872 5470 return ret;
46a3df9f
S		 5471 }
5472
5473 break;
5474 case HNAE3_CLIENT_UNIC:
5475 hdev->nic_client = client;
5476 vport->nic.client = client;
5477
5478 ret = client->ops->init_instance(&vport->nic);
5479 if (ret)
6f636872 5480 return ret;
46a3df9f
S		 5481
5482 break;
5483 case HNAE3_CLIENT_ROCE:
e92a0843 5484 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5485 hdev->roce_client = client;
5486 vport->roce.client = client;
5487 }
5488
3a46f34d 5489 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5490 ret = hclge_init_roce_base_info(vport);
5491 if (ret)
6f636872 5492 return ret;
46a3df9f
S		 5493
5494 ret = client->ops->init_instance(&vport->roce);
5495 if (ret)
6f636872 5496 return ret;
46a3df9f
S		 5497 }
5498 }
5499 }
5500
5501 return 0;
46a3df9f
S		 5502}
5503
5504static void hclge_uninit_client_instance(struct hnae3_client *client,
5505 struct hnae3_ae_dev *ae_dev)
5506{
5507 struct hclge_dev *hdev = ae_dev->priv;
5508 struct hclge_vport *vport;
5509 int i;
5510
5511 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5512 vport = &hdev->vport[i];
a17dcf3f 5513 if (hdev->roce_client) {
46a3df9f
S		 5514 hdev->roce_client->ops->uninit_instance(&vport->roce,
5515 0);
a17dcf3f
L		 5516 hdev->roce_client = NULL;
5517 vport->roce.client = NULL;
5518 }
46a3df9f
S		 5519 if (client->type == HNAE3_CLIENT_ROCE)
5520 return;
a17dcf3f 5521 if (client->ops->uninit_instance) {
46a3df9f 5522 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5523 hdev->nic_client = NULL;
5524 vport->nic.client = NULL;
5525 }
46a3df9f
S		 5526 }
5527}
5528
5529static int hclge_pci_init(struct hclge_dev *hdev)
5530{
5531 struct pci_dev *pdev = hdev->pdev;
5532 struct hclge_hw *hw;
5533 int ret;
5534
5535 ret = pci_enable_device(pdev);
5536 if (ret) {
5537 dev_err(&pdev->dev, "failed to enable PCI device\n");
6c46284e 5538 return ret;
46a3df9f
S		 5539 }
5540
5541 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5542 if (ret) {
5543 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5544 if (ret) {
5545 dev_err(&pdev->dev,
5546 "can't set consistent PCI DMA");
5547 goto err_disable_device;
5548 }
5549 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5550 }
5551
5552 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5553 if (ret) {
5554 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5555 goto err_disable_device;
5556 }
5557
5558 pci_set_master(pdev);
5559 hw = &hdev->hw;
48fff6ef 5560 hw->back = hdev;
46a3df9f
S		 5561 hw->io_base = pcim_iomap(pdev, 2, 0);
5562 if (!hw->io_base) {
5563 dev_err(&pdev->dev, "Can't map configuration register space\n");
5564 ret = -ENOMEM;
5565 goto err_clr_master;
5566 }
5567
709eb41a
L		 5568 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5569
46a3df9f
S		 5570 return 0;
5571err_clr_master:
5572 pci_clear_master(pdev);
5573 pci_release_regions(pdev);
5574err_disable_device:
5575 pci_disable_device(pdev);
46a3df9f
S		 5576
5577 return ret;
5578}
5579
5580static void hclge_pci_uninit(struct hclge_dev *hdev)
5581{
5582 struct pci_dev *pdev = hdev->pdev;
5583
7d6d639b 5584 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 5585 pci_free_irq_vectors(pdev);
46a3df9f
S		 5586 pci_clear_master(pdev);
5587 pci_release_mem_regions(pdev);
5588 pci_disable_device(pdev);
5589}
5590
2ec3d9f0
PL		 5591static void hclge_state_init(struct hclge_dev *hdev)
5592{
5593 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5594 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5595 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5596 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5597 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5598 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5599}
5600
5601static void hclge_state_uninit(struct hclge_dev *hdev)
5602{
5603 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5604
5605 if (hdev->service_timer.function)
5606 del_timer_sync(&hdev->service_timer);
5607 if (hdev->service_task.func)
5608 cancel_work_sync(&hdev->service_task);
5609 if (hdev->rst_service_task.func)
5610 cancel_work_sync(&hdev->rst_service_task);
5611 if (hdev->mbx_service_task.func)
5612 cancel_work_sync(&hdev->mbx_service_task);
5613}
5614
46a3df9f
S		 5615static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5616{
5617 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5618 struct hclge_dev *hdev;
5619 int ret;
5620
5621 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5622 if (!hdev) {
5623 ret = -ENOMEM;
e0027501 5624 goto out;
46a3df9f
S		 5625 }
5626
46a3df9f
S		 5627 hdev->pdev = pdev;
5628 hdev->ae_dev = ae_dev;
4ed340ab 5629 hdev->reset_type = HNAE3_NONE_RESET;
8e888151 5630 hdev->reset_request = 0;
5631 hdev->reset_pending = 0;
46a3df9f
S		 5632 ae_dev->priv = hdev;
5633
46a3df9f
S		 5634 ret = hclge_pci_init(hdev);
5635 if (ret) {
5636 dev_err(&pdev->dev, "PCI init failed\n");
e0027501 5637 goto out;
46a3df9f
S		 5638 }
5639
3efb960f
L		 5640 /* Firmware command queue initialize */
5641 ret = hclge_cmd_queue_init(hdev);
5642 if (ret) {
5643 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
e0027501 5644 goto err_pci_uninit;
3efb960f
L		 5645 }
5646
5647 /* Firmware command initialize */
46a3df9f
S		 5648 ret = hclge_cmd_init(hdev);
5649 if (ret)
e0027501 5650 goto err_cmd_uninit;
46a3df9f
S		 5651
5652 ret = hclge_get_cap(hdev);
5653 if (ret) {
e00e2197
CIK		 5654 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5655 ret);
e0027501 5656 goto err_cmd_uninit;
46a3df9f
S		 5657 }
5658
5659 ret = hclge_configure(hdev);
5660 if (ret) {
5661 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
e0027501 5662 goto err_cmd_uninit;
46a3df9f
S		 5663 }
5664
887c3820 5665 ret = hclge_init_msi(hdev);
46a3df9f 5666 if (ret) {
887c3820 5667 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
e0027501 5668 goto err_cmd_uninit;
46a3df9f
S		 5669 }
5670
466b0c00
L		 5671 ret = hclge_misc_irq_init(hdev);
5672 if (ret) {
5673 dev_err(&pdev->dev,
5674 "Misc IRQ(vector0) init error, ret = %d.\n",
5675 ret);
e0027501 5676 goto err_msi_uninit;
466b0c00
L		 5677 }
5678
46a3df9f
S		 5679 ret = hclge_alloc_tqps(hdev);
5680 if (ret) {
5681 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
e0027501 5682 goto err_msi_irq_uninit;
46a3df9f
S		 5683 }
5684
5685 ret = hclge_alloc_vport(hdev);
5686 if (ret) {
5687 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
e0027501 5688 goto err_msi_irq_uninit;
46a3df9f
S		 5689 }
5690
7df7dad6
L		 5691 ret = hclge_map_tqp(hdev);
5692 if (ret) {
5693 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
bc59f827 5694 goto err_msi_irq_uninit;
7df7dad6
L		 5695 }
5696
dea9a821
HT		 5697 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5698 ret = hclge_mac_mdio_config(hdev);
5699 if (ret) {
5700 dev_err(&hdev->pdev->dev,
5701 "mdio config fail ret=%d\n", ret);
bc59f827 5702 goto err_msi_irq_uninit;
dea9a821 5703 }
cf9cca2d 5704 }
5705
46a3df9f
S		 5706 ret = hclge_mac_init(hdev);
5707 if (ret) {
5708 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
e0027501 5709 goto err_mdiobus_unreg;
46a3df9f 5710 }
46a3df9f
S		 5711
5712 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5713 if (ret) {
5714 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
e0027501 5715 goto err_mdiobus_unreg;
46a3df9f
S		 5716 }
5717
46a3df9f
S		 5718 ret = hclge_init_vlan_config(hdev);
5719 if (ret) {
5720 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
e0027501 5721 goto err_mdiobus_unreg;
46a3df9f
S		 5722 }
5723
5724 ret = hclge_tm_schd_init(hdev);
5725 if (ret) {
5726 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
e0027501 5727 goto err_mdiobus_unreg;
68ece54e
YL		 5728 }
5729
8015bb74 5730 hclge_rss_init_cfg(hdev);
68ece54e
YL		 5731 ret = hclge_rss_init_hw(hdev);
5732 if (ret) {
5733 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
e0027501 5734 goto err_mdiobus_unreg;
46a3df9f
S		 5735 }
5736
635bfb58
FL		 5737 ret = init_mgr_tbl(hdev);
5738 if (ret) {
5739 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
e0027501 5740 goto err_mdiobus_unreg;
635bfb58
FL		 5741 }
5742
cacde272
YL		 5743 hclge_dcb_ops_set(hdev);
5744
d039ef68 5745 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5746 INIT_WORK(&hdev->service_task, hclge_service_task);
ed4a1bb8 5747 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
22fd3468 5748 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5749
9ab4ad14
XW		 5750 hclge_clear_all_event_cause(hdev);
5751
466b0c00
L		 5752 /* Enable MISC vector(vector0) */
5753 hclge_enable_vector(&hdev->misc_vector, true);
5754
2ec3d9f0 5755 hclge_state_init(hdev);
46a3df9f
S		 5756
5757 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5758 return 0;
5759
e0027501
HT		 5760err_mdiobus_unreg:
5761 if (hdev->hw.mac.phydev)
5762 mdiobus_unregister(hdev->hw.mac.mdio_bus);
e0027501
HT		 5763err_msi_irq_uninit:
5764 hclge_misc_irq_uninit(hdev);
5765err_msi_uninit:
5766 pci_free_irq_vectors(pdev);
5767err_cmd_uninit:
5768 hclge_destroy_cmd_queue(&hdev->hw);
5769err_pci_uninit:
7d6d639b 5770 pcim_iounmap(pdev, hdev->hw.io_base);
e0027501 5771 pci_clear_master(pdev);
46a3df9f 5772 pci_release_regions(pdev);
e0027501 5773 pci_disable_device(pdev);
e0027501 5774out:
46a3df9f
S		 5775 return ret;
5776}
5777
c6dc5213 5778static void hclge_stats_clear(struct hclge_dev *hdev)
5779{
5780 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5781}
5782
4ed340ab
L		 5783static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5784{
5785 struct hclge_dev *hdev = ae_dev->priv;
5786 struct pci_dev *pdev = ae_dev->pdev;
5787 int ret;
5788
5789 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5790
c6dc5213 5791 hclge_stats_clear(hdev);
4e66632d 5792 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 5793
4ed340ab
L		 5794 ret = hclge_cmd_init(hdev);
5795 if (ret) {
5796 dev_err(&pdev->dev, "Cmd queue init failed\n");
5797 return ret;
5798 }
5799
5800 ret = hclge_get_cap(hdev);
5801 if (ret) {
5802 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5803 ret);
5804 return ret;
5805 }
5806
5807 ret = hclge_configure(hdev);
5808 if (ret) {
5809 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5810 return ret;
5811 }
5812
5813 ret = hclge_map_tqp(hdev);
5814 if (ret) {
5815 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5816 return ret;
5817 }
5818
5819 ret = hclge_mac_init(hdev);
5820 if (ret) {
5821 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5822 return ret;
5823 }
5824
4ed340ab
L		 5825 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5826 if (ret) {
5827 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5828 return ret;
5829 }
5830
5831 ret = hclge_init_vlan_config(hdev);
5832 if (ret) {
5833 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5834 return ret;
5835 }
5836
d85f1ab5 5837 ret = hclge_tm_init_hw(hdev);
4ed340ab 5838 if (ret) {
d85f1ab5 5839 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 5840 return ret;
5841 }
5842
5843 ret = hclge_rss_init_hw(hdev);
5844 if (ret) {
5845 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5846 return ret;
5847 }
5848
4ed340ab
L		 5849 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5850 HCLGE_DRIVER_NAME);
5851
5852 return 0;
5853}
5854
46a3df9f
S		 5855static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5856{
5857 struct hclge_dev *hdev = ae_dev->priv;
5858 struct hclge_mac *mac = &hdev->hw.mac;
5859
2ec3d9f0 5860 hclge_state_uninit(hdev);
46a3df9f
S		 5861
5862 if (mac->phydev)
5863 mdiobus_unregister(mac->mdio_bus);
5864
466b0c00
L		 5865 /* Disable MISC vector(vector0) */
5866 hclge_enable_vector(&hdev->misc_vector, false);
9ab4ad14
XW		 5867 synchronize_irq(hdev->misc_vector.vector_irq);
5868
46a3df9f 5869 hclge_destroy_cmd_queue(&hdev->hw);
202f2014 5870 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5871 hclge_pci_uninit(hdev);
5872 ae_dev->priv = NULL;
5873}
5874
4f645a90
PL		 5875static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5876{
5877 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5878 struct hclge_vport *vport = hclge_get_vport(handle);
5879 struct hclge_dev *hdev = vport->back;
5880
5881 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5882}
5883
5884static void hclge_get_channels(struct hnae3_handle *handle,
5885 struct ethtool_channels *ch)
5886{
5887 struct hclge_vport *vport = hclge_get_vport(handle);
5888
5889 ch->max_combined = hclge_get_max_channels(handle);
5890 ch->other_count = 1;
5891 ch->max_other = 1;
5892 ch->combined_count = vport->alloc_tqps;
5893}
5894
f1f779ce
PL		 5895static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5896 u16 *free_tqps, u16 *max_rss_size)
5897{
5898 struct hclge_vport *vport = hclge_get_vport(handle);
5899 struct hclge_dev *hdev = vport->back;
5900 u16 temp_tqps = 0;
5901 int i;
5902
5903 for (i = 0; i < hdev->num_tqps; i++) {
5904 if (!hdev->htqp[i].alloced)
5905 temp_tqps++;
5906 }
5907 *free_tqps = temp_tqps;
5908 *max_rss_size = hdev->rss_size_max;
5909}
5910
5911static void hclge_release_tqp(struct hclge_vport *vport)
5912{
5913 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5914 struct hclge_dev *hdev = vport->back;
5915 int i;
5916
5917 for (i = 0; i < kinfo->num_tqps; i++) {
5918 struct hclge_tqp *tqp =
5919 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5920
5921 tqp->q.handle = NULL;
5922 tqp->q.tqp_index = 0;
5923 tqp->alloced = false;
5924 }
5925
5926 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5927 kinfo->tqp = NULL;
5928}
5929
5930static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5931{
5932 struct hclge_vport *vport = hclge_get_vport(handle);
5933 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5934 struct hclge_dev *hdev = vport->back;
5935 int cur_rss_size = kinfo->rss_size;
5936 int cur_tqps = kinfo->num_tqps;
5937 u16 tc_offset[HCLGE_MAX_TC_NUM];
5938 u16 tc_valid[HCLGE_MAX_TC_NUM];
5939 u16 tc_size[HCLGE_MAX_TC_NUM];
5940 u16 roundup_size;
5941 u32 *rss_indir;
5942 int ret, i;
5943
5944 hclge_release_tqp(vport);
5945
5946 ret = hclge_knic_setup(vport, new_tqps_num);
5947 if (ret) {
5948 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5949 return ret;
5950 }
5951
5952 ret = hclge_map_tqp_to_vport(hdev, vport);
5953 if (ret) {
5954 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5955 return ret;
5956 }
5957
5958 ret = hclge_tm_schd_init(hdev);
5959 if (ret) {
5960 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5961 return ret;
5962 }
5963
5964 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5965 roundup_size = ilog2(roundup_size);
5966 /* Set the RSS TC mode according to the new RSS size */
5967 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5968 tc_valid[i] = 0;
5969
5970 if (!(hdev->hw_tc_map & BIT(i)))
5971 continue;
5972
5973 tc_valid[i] = 1;
5974 tc_size[i] = roundup_size;
5975 tc_offset[i] = kinfo->rss_size * i;
5976 }
5977 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5978 if (ret)
5979 return ret;
5980
5981 /* Reinitializes the rss indirect table according to the new RSS size */
5982 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5983 if (!rss_indir)
5984 return -ENOMEM;
5985
5986 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5987 rss_indir[i] = i % kinfo->rss_size;
5988
5989 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5990 if (ret)
5991 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5992 ret);
5993
5994 kfree(rss_indir);
5995
5996 if (!ret)
5997 dev_info(&hdev->pdev->dev,
5998 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5999 cur_rss_size, kinfo->rss_size,
6000 cur_tqps, kinfo->rss_size * kinfo->num_tc);
6001
6002 return ret;
6003}
6004
db2a3e43
FL		 6005static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
6006 u32 *regs_num_64_bit)
6007{
6008 struct hclge_desc desc;
6009 u32 total_num;
6010 int ret;
6011
6012 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
6013 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6014 if (ret) {
6015 dev_err(&hdev->pdev->dev,
6016 "Query register number cmd failed, ret = %d.\n", ret);
6017 return ret;
6018 }
6019
6020 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
6021 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
6022
6023 total_num = *regs_num_32_bit + *regs_num_64_bit;
6024 if (!total_num)
6025 return -EINVAL;
6026
6027 return 0;
6028}
6029
6030static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6031 void *data)
6032{
6033#define HCLGE_32_BIT_REG_RTN_DATANUM 8
6034
6035 struct hclge_desc *desc;
6036 u32 *reg_val = data;
6037 __le32 *desc_data;
6038 int cmd_num;
6039 int i, k, n;
6040 int ret;
6041
6042 if (regs_num == 0)
6043 return 0;
6044
6045 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
6046 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6047 if (!desc)
6048 return -ENOMEM;
6049
6050 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
6051 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6052 if (ret) {
6053 dev_err(&hdev->pdev->dev,
6054 "Query 32 bit register cmd failed, ret = %d.\n", ret);
6055 kfree(desc);
6056 return ret;
6057 }
6058
6059 for (i = 0; i < cmd_num; i++) {
6060 if (i == 0) {
6061 desc_data = (__le32 *)(&desc[i].data[0]);
6062 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
6063 } else {
6064 desc_data = (__le32 *)(&desc[i]);
6065 n = HCLGE_32_BIT_REG_RTN_DATANUM;
6066 }
6067 for (k = 0; k < n; k++) {
6068 *reg_val++ = le32_to_cpu(*desc_data++);
6069
6070 regs_num--;
6071 if (!regs_num)
6072 break;
6073 }
6074 }
6075
6076 kfree(desc);
6077 return 0;
6078}
6079
6080static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6081 void *data)
6082{
6083#define HCLGE_64_BIT_REG_RTN_DATANUM 4
6084
6085 struct hclge_desc *desc;
6086 u64 *reg_val = data;
6087 __le64 *desc_data;
6088 int cmd_num;
6089 int i, k, n;
6090 int ret;
6091
6092 if (regs_num == 0)
6093 return 0;
6094
6095 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
6096 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6097 if (!desc)
6098 return -ENOMEM;
6099
6100 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
6101 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6102 if (ret) {
6103 dev_err(&hdev->pdev->dev,
6104 "Query 64 bit register cmd failed, ret = %d.\n", ret);
6105 kfree(desc);
6106 return ret;
6107 }
6108
6109 for (i = 0; i < cmd_num; i++) {
6110 if (i == 0) {
6111 desc_data = (__le64 *)(&desc[i].data[0]);
6112 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
6113 } else {
6114 desc_data = (__le64 *)(&desc[i]);
6115 n = HCLGE_64_BIT_REG_RTN_DATANUM;
6116 }
6117 for (k = 0; k < n; k++) {
6118 *reg_val++ = le64_to_cpu(*desc_data++);
6119
6120 regs_num--;
6121 if (!regs_num)
6122 break;
6123 }
6124 }
6125
6126 kfree(desc);
6127 return 0;
6128}
6129
6130static int hclge_get_regs_len(struct hnae3_handle *handle)
6131{
6132 struct hclge_vport *vport = hclge_get_vport(handle);
6133 struct hclge_dev *hdev = vport->back;
6134 u32 regs_num_32_bit, regs_num_64_bit;
6135 int ret;
6136
6137 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6138 if (ret) {
6139 dev_err(&hdev->pdev->dev,
6140 "Get register number failed, ret = %d.\n", ret);
6141 return -EOPNOTSUPP;
6142 }
6143
6144 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
6145}
6146
6147static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
6148 void *data)
6149{
6150 struct hclge_vport *vport = hclge_get_vport(handle);
6151 struct hclge_dev *hdev = vport->back;
6152 u32 regs_num_32_bit, regs_num_64_bit;
6153 int ret;
6154
6155 *version = hdev->fw_version;
6156
6157 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6158 if (ret) {
6159 dev_err(&hdev->pdev->dev,
6160 "Get register number failed, ret = %d.\n", ret);
6161 return;
6162 }
6163
6164 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
6165 if (ret) {
6166 dev_err(&hdev->pdev->dev,
6167 "Get 32 bit register failed, ret = %d.\n", ret);
6168 return;
6169 }
6170
6171 data = (u32 *)data + regs_num_32_bit;
6172 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
6173 data);
6174 if (ret)
6175 dev_err(&hdev->pdev->dev,
6176 "Get 64 bit register failed, ret = %d.\n", ret);
6177}
6178
fe3a3e15 6179static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
d9a0884e
JS		 6180{
6181 struct hclge_set_led_state_cmd *req;
6182 struct hclge_desc desc;
6183 int ret;
6184
6185 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
6186
6187 req = (struct hclge_set_led_state_cmd *)desc.data;
928d369a 6188 hnae_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
d9a0884e
JS		 6189 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6190
6191 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6192 if (ret)
6193 dev_err(&hdev->pdev->dev,
6194 "Send set led state cmd error, ret =%d\n", ret);
6195
6196 return ret;
6197}
6198
6199enum hclge_led_status {
6200 HCLGE_LED_OFF,
6201 HCLGE_LED_ON,
6202 HCLGE_LED_NO_CHANGE = 0xFF,
6203};
6204
6205static int hclge_set_led_id(struct hnae3_handle *handle,
6206 enum ethtool_phys_id_state status)
6207{
d9a0884e
JS		 6208 struct hclge_vport *vport = hclge_get_vport(handle);
6209 struct hclge_dev *hdev = vport->back;
d9a0884e
JS		 6210
6211 switch (status) {
6212 case ETHTOOL_ID_ACTIVE:
fe3a3e15 6213 return hclge_set_led_status(hdev, HCLGE_LED_ON);
d9a0884e 6214 case ETHTOOL_ID_INACTIVE:
fe3a3e15 6215 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
d9a0884e 6216 default:
fe3a3e15 6217 return -EINVAL;
d9a0884e 6218 }
d9a0884e
JS		 6219}
6220
d92ceae9
FL		 6221static void hclge_get_link_mode(struct hnae3_handle *handle,
6222 unsigned long *supported,
6223 unsigned long *advertising)
6224{
6225 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
6226 struct hclge_vport *vport = hclge_get_vport(handle);
6227 struct hclge_dev *hdev = vport->back;
6228 unsigned int idx = 0;
6229
6230 for (; idx < size; idx++) {
6231 supported[idx] = hdev->hw.mac.supported[idx];
6232 advertising[idx] = hdev->hw.mac.advertising[idx];
6233 }
6234}
6235
6236static void hclge_get_port_type(struct hnae3_handle *handle,
6237 u8 *port_type)
6238{
6239 struct hclge_vport *vport = hclge_get_vport(handle);
6240 struct hclge_dev *hdev = vport->back;
6241 u8 media_type = hdev->hw.mac.media_type;
6242
6243 switch (media_type) {
6244 case HNAE3_MEDIA_TYPE_FIBER:
6245 *port_type = PORT_FIBRE;
6246 break;
6247 case HNAE3_MEDIA_TYPE_COPPER:
6248 *port_type = PORT_TP;
6249 break;
6250 case HNAE3_MEDIA_TYPE_UNKNOWN:
6251 default:
6252 *port_type = PORT_OTHER;
6253 break;
6254 }
6255}
6256
46a3df9f
S		 6257static const struct hnae3_ae_ops hclge_ops = {
6258 .init_ae_dev = hclge_init_ae_dev,
6259 .uninit_ae_dev = hclge_uninit_ae_dev,
6260 .init_client_instance = hclge_init_client_instance,
6261 .uninit_client_instance = hclge_uninit_client_instance,
63d7e66f
SM		 6262 .map_ring_to_vector = hclge_map_ring_to_vector,
6263 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 6264 .get_vector = hclge_get_vector,
7412200c 6265 .put_vector = hclge_put_vector,
46a3df9f 6266 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 6267 .set_loopback = hclge_set_loopback,
46a3df9f
S		 6268 .start = hclge_ae_start,
6269 .stop = hclge_ae_stop,
6270 .get_status = hclge_get_status,
6271 .get_ksettings_an_result = hclge_get_ksettings_an_result,
6272 .update_speed_duplex_h = hclge_update_speed_duplex_h,
6273 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6274 .get_media_type = hclge_get_media_type,
6275 .get_rss_key_size = hclge_get_rss_key_size,
6276 .get_rss_indir_size = hclge_get_rss_indir_size,
6277 .get_rss = hclge_get_rss,
6278 .set_rss = hclge_set_rss,
f7db940a 6279 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 6280 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 6281 .get_tc_size = hclge_get_tc_size,
6282 .get_mac_addr = hclge_get_mac_addr,
6283 .set_mac_addr = hclge_set_mac_addr,
6284 .add_uc_addr = hclge_add_uc_addr,
6285 .rm_uc_addr = hclge_rm_uc_addr,
6286 .add_mc_addr = hclge_add_mc_addr,
6287 .rm_mc_addr = hclge_rm_mc_addr,
a832d8b5 6288 .update_mta_status = hclge_update_mta_status,
46a3df9f
S		 6289 .set_autoneg = hclge_set_autoneg,
6290 .get_autoneg = hclge_get_autoneg,
6291 .get_pauseparam = hclge_get_pauseparam,
09ea401e 6292 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6293 .set_mtu = hclge_set_mtu,
6294 .reset_queue = hclge_reset_tqp,
6295 .get_stats = hclge_get_stats,
6296 .update_stats = hclge_update_stats,
6297 .get_strings = hclge_get_strings,
6298 .get_sset_count = hclge_get_sset_count,
6299 .get_fw_version = hclge_get_fw_version,
6300 .get_mdix_mode = hclge_get_mdix_mode,
d818396d 6301 .enable_vlan_filter = hclge_enable_vlan_filter,
4e66632d 6302 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 6303 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5f9a7732 6304 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6305 .reset_event = hclge_reset_event,
f1f779ce
PL		 6306 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6307 .set_channels = hclge_set_channels,
4f645a90 6308 .get_channels = hclge_get_channels,
a2cfbadb 6309 .get_flowctrl_adv = hclge_get_flowctrl_adv,
db2a3e43
FL		 6310 .get_regs_len = hclge_get_regs_len,
6311 .get_regs = hclge_get_regs,
d9a0884e 6312 .set_led_id = hclge_set_led_id,
d92ceae9
FL		 6313 .get_link_mode = hclge_get_link_mode,
6314 .get_port_type = hclge_get_port_type,
46a3df9f
S		 6315};
6316
6317static struct hnae3_ae_algo ae_algo = {
6318 .ops = &hclge_ops,
3519af01 6319 .name = HCLGE_NAME,
46a3df9f
S		 6320 .pdev_id_table = ae_algo_pci_tbl,
6321};
6322
6323static int hclge_init(void)
6324{
6325 pr_info("%s is initializing\n", HCLGE_NAME);
6326
a4d090cc
FL		 6327 hnae3_register_ae_algo(&ae_algo);
6328
6329 return 0;
46a3df9f
S		 6330}
6331
6332static void hclge_exit(void)
6333{
6334 hnae3_unregister_ae_algo(&ae_algo);
6335}
6336module_init(hclge_init);
6337module_exit(hclge_exit);
6338
6339MODULE_LICENSE("GPL");
6340MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6341MODULE_DESCRIPTION("HCLGE Driver");
6342MODULE_VERSION(HCLGE_MOD_VERSION);
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