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46a3df9f S |
1 | /* |
2 | * Copyright (c) 2016-2017 Hisilicon Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/acpi.h> | |
11 | #include <linux/device.h> | |
12 | #include <linux/etherdevice.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/netdevice.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/platform_device.h> | |
7393ed39 | 20 | #include <linux/if_vlan.h> |
d5752031 | 21 | #include <net/rtnetlink.h> |
46a3df9f | 22 | #include "hclge_cmd.h" |
cacde272 | 23 | #include "hclge_dcb.h" |
46a3df9f | 24 | #include "hclge_main.h" |
0cdbdd3e | 25 | #include "hclge_mbx.h" |
46a3df9f S |
26 | #include "hclge_mdio.h" |
27 | #include "hclge_tm.h" | |
28 | #include "hnae3.h" | |
29 | ||
30 | #define HCLGE_NAME "hclge" | |
31 | #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) | |
32 | #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) | |
33 | #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f)) | |
34 | #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f)) | |
35 | ||
46a3df9f S |
36 | static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, |
37 | enum hclge_mta_dmac_sel_type mta_mac_sel, | |
38 | bool enable); | |
59bc85ec | 39 | static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu); |
46a3df9f | 40 | static int hclge_init_vlan_config(struct hclge_dev *hdev); |
4ed340ab | 41 | static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); |
fe36292f | 42 | static int hclge_update_led_status(struct hclge_dev *hdev); |
46a3df9f S |
43 | |
44 | static struct hnae3_ae_algo ae_algo; | |
45 | ||
46 | static const struct pci_device_id ae_algo_pci_tbl[] = { | |
47 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, | |
48 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, | |
49 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, | |
50 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, | |
51 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, | |
52 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, | |
53 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, | |
e92a0843 | 54 | /* required last entry */ |
46a3df9f S |
55 | {0, } |
56 | }; | |
57 | ||
28d9cec8 YL |
58 | MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); |
59 | ||
46a3df9f S |
60 | static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { |
61 | "Mac Loopback test", | |
62 | "Serdes Loopback test", | |
63 | "Phy Loopback test" | |
64 | }; | |
65 | ||
66 | static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = { | |
67 | {"igu_rx_oversize_pkt", | |
68 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)}, | |
69 | {"igu_rx_undersize_pkt", | |
70 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)}, | |
71 | {"igu_rx_out_all_pkt", | |
72 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)}, | |
73 | {"igu_rx_uni_pkt", | |
74 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)}, | |
75 | {"igu_rx_multi_pkt", | |
76 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)}, | |
77 | {"igu_rx_broad_pkt", | |
78 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)}, | |
79 | {"egu_tx_out_all_pkt", | |
80 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)}, | |
81 | {"egu_tx_uni_pkt", | |
82 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)}, | |
83 | {"egu_tx_multi_pkt", | |
84 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)}, | |
85 | {"egu_tx_broad_pkt", | |
86 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)}, | |
87 | {"ssu_ppp_mac_key_num", | |
88 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)}, | |
89 | {"ssu_ppp_host_key_num", | |
90 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)}, | |
91 | {"ppp_ssu_mac_rlt_num", | |
92 | HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)}, | |
93 | {"ppp_ssu_host_rlt_num", | |
94 | HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)}, | |
95 | {"ssu_tx_in_num", | |
96 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)}, | |
97 | {"ssu_tx_out_num", | |
98 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)}, | |
99 | {"ssu_rx_in_num", | |
100 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)}, | |
101 | {"ssu_rx_out_num", | |
102 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)} | |
103 | }; | |
104 | ||
105 | static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = { | |
106 | {"igu_rx_err_pkt", | |
107 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)}, | |
108 | {"igu_rx_no_eof_pkt", | |
109 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)}, | |
110 | {"igu_rx_no_sof_pkt", | |
111 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)}, | |
112 | {"egu_tx_1588_pkt", | |
113 | HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)}, | |
114 | {"ssu_full_drop_num", | |
115 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)}, | |
116 | {"ssu_part_drop_num", | |
117 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)}, | |
118 | {"ppp_key_drop_num", | |
119 | HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)}, | |
120 | {"ppp_rlt_drop_num", | |
121 | HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)}, | |
122 | {"ssu_key_drop_num", | |
123 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)}, | |
124 | {"pkt_curr_buf_cnt", | |
125 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)}, | |
126 | {"qcn_fb_rcv_cnt", | |
127 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)}, | |
128 | {"qcn_fb_drop_cnt", | |
129 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)}, | |
130 | {"qcn_fb_invaild_cnt", | |
131 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)}, | |
132 | {"rx_packet_tc0_in_cnt", | |
133 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)}, | |
134 | {"rx_packet_tc1_in_cnt", | |
135 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)}, | |
136 | {"rx_packet_tc2_in_cnt", | |
137 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)}, | |
138 | {"rx_packet_tc3_in_cnt", | |
139 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)}, | |
140 | {"rx_packet_tc4_in_cnt", | |
141 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)}, | |
142 | {"rx_packet_tc5_in_cnt", | |
143 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)}, | |
144 | {"rx_packet_tc6_in_cnt", | |
145 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)}, | |
146 | {"rx_packet_tc7_in_cnt", | |
147 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)}, | |
148 | {"rx_packet_tc0_out_cnt", | |
149 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)}, | |
150 | {"rx_packet_tc1_out_cnt", | |
151 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)}, | |
152 | {"rx_packet_tc2_out_cnt", | |
153 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)}, | |
154 | {"rx_packet_tc3_out_cnt", | |
155 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)}, | |
156 | {"rx_packet_tc4_out_cnt", | |
157 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)}, | |
158 | {"rx_packet_tc5_out_cnt", | |
159 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)}, | |
160 | {"rx_packet_tc6_out_cnt", | |
161 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)}, | |
162 | {"rx_packet_tc7_out_cnt", | |
163 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)}, | |
164 | {"tx_packet_tc0_in_cnt", | |
165 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)}, | |
166 | {"tx_packet_tc1_in_cnt", | |
167 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)}, | |
168 | {"tx_packet_tc2_in_cnt", | |
169 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)}, | |
170 | {"tx_packet_tc3_in_cnt", | |
171 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)}, | |
172 | {"tx_packet_tc4_in_cnt", | |
173 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)}, | |
174 | {"tx_packet_tc5_in_cnt", | |
175 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)}, | |
176 | {"tx_packet_tc6_in_cnt", | |
177 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)}, | |
178 | {"tx_packet_tc7_in_cnt", | |
179 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)}, | |
180 | {"tx_packet_tc0_out_cnt", | |
181 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)}, | |
182 | {"tx_packet_tc1_out_cnt", | |
183 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)}, | |
184 | {"tx_packet_tc2_out_cnt", | |
185 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)}, | |
186 | {"tx_packet_tc3_out_cnt", | |
187 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)}, | |
188 | {"tx_packet_tc4_out_cnt", | |
189 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)}, | |
190 | {"tx_packet_tc5_out_cnt", | |
191 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)}, | |
192 | {"tx_packet_tc6_out_cnt", | |
193 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)}, | |
194 | {"tx_packet_tc7_out_cnt", | |
195 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)}, | |
196 | {"pkt_curr_buf_tc0_cnt", | |
197 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)}, | |
198 | {"pkt_curr_buf_tc1_cnt", | |
199 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)}, | |
200 | {"pkt_curr_buf_tc2_cnt", | |
201 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)}, | |
202 | {"pkt_curr_buf_tc3_cnt", | |
203 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)}, | |
204 | {"pkt_curr_buf_tc4_cnt", | |
205 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)}, | |
206 | {"pkt_curr_buf_tc5_cnt", | |
207 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)}, | |
208 | {"pkt_curr_buf_tc6_cnt", | |
209 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)}, | |
210 | {"pkt_curr_buf_tc7_cnt", | |
211 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)}, | |
212 | {"mb_uncopy_num", | |
213 | HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)}, | |
214 | {"lo_pri_unicast_rlt_drop_num", | |
215 | HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)}, | |
216 | {"hi_pri_multicast_rlt_drop_num", | |
217 | HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)}, | |
218 | {"lo_pri_multicast_rlt_drop_num", | |
219 | HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)}, | |
220 | {"rx_oq_drop_pkt_cnt", | |
221 | HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)}, | |
222 | {"tx_oq_drop_pkt_cnt", | |
223 | HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)}, | |
224 | {"nic_l2_err_drop_pkt_cnt", | |
225 | HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)}, | |
226 | {"roc_l2_err_drop_pkt_cnt", | |
227 | HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)} | |
228 | }; | |
229 | ||
230 | static const struct hclge_comm_stats_str g_mac_stats_string[] = { | |
231 | {"mac_tx_mac_pause_num", | |
232 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, | |
233 | {"mac_rx_mac_pause_num", | |
234 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, | |
235 | {"mac_tx_pfc_pri0_pkt_num", | |
236 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, | |
237 | {"mac_tx_pfc_pri1_pkt_num", | |
238 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, | |
239 | {"mac_tx_pfc_pri2_pkt_num", | |
240 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, | |
241 | {"mac_tx_pfc_pri3_pkt_num", | |
242 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, | |
243 | {"mac_tx_pfc_pri4_pkt_num", | |
244 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, | |
245 | {"mac_tx_pfc_pri5_pkt_num", | |
246 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, | |
247 | {"mac_tx_pfc_pri6_pkt_num", | |
248 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, | |
249 | {"mac_tx_pfc_pri7_pkt_num", | |
250 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, | |
251 | {"mac_rx_pfc_pri0_pkt_num", | |
252 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, | |
253 | {"mac_rx_pfc_pri1_pkt_num", | |
254 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, | |
255 | {"mac_rx_pfc_pri2_pkt_num", | |
256 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, | |
257 | {"mac_rx_pfc_pri3_pkt_num", | |
258 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, | |
259 | {"mac_rx_pfc_pri4_pkt_num", | |
260 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, | |
261 | {"mac_rx_pfc_pri5_pkt_num", | |
262 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, | |
263 | {"mac_rx_pfc_pri6_pkt_num", | |
264 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, | |
265 | {"mac_rx_pfc_pri7_pkt_num", | |
266 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, | |
267 | {"mac_tx_total_pkt_num", | |
268 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, | |
269 | {"mac_tx_total_oct_num", | |
270 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, | |
271 | {"mac_tx_good_pkt_num", | |
272 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, | |
273 | {"mac_tx_bad_pkt_num", | |
274 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, | |
275 | {"mac_tx_good_oct_num", | |
276 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, | |
277 | {"mac_tx_bad_oct_num", | |
278 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, | |
279 | {"mac_tx_uni_pkt_num", | |
280 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, | |
281 | {"mac_tx_multi_pkt_num", | |
282 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, | |
283 | {"mac_tx_broad_pkt_num", | |
284 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, | |
285 | {"mac_tx_undersize_pkt_num", | |
286 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, | |
f3426583 JS |
287 | {"mac_tx_oversize_pkt_num", |
288 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, | |
46a3df9f S |
289 | {"mac_tx_64_oct_pkt_num", |
290 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, | |
291 | {"mac_tx_65_127_oct_pkt_num", | |
292 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, | |
293 | {"mac_tx_128_255_oct_pkt_num", | |
294 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, | |
295 | {"mac_tx_256_511_oct_pkt_num", | |
296 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, | |
297 | {"mac_tx_512_1023_oct_pkt_num", | |
298 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, | |
299 | {"mac_tx_1024_1518_oct_pkt_num", | |
300 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, | |
b42874e4 JS |
301 | {"mac_tx_1519_2047_oct_pkt_num", |
302 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, | |
303 | {"mac_tx_2048_4095_oct_pkt_num", | |
304 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, | |
305 | {"mac_tx_4096_8191_oct_pkt_num", | |
306 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, | |
b42874e4 JS |
307 | {"mac_tx_8192_9216_oct_pkt_num", |
308 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, | |
309 | {"mac_tx_9217_12287_oct_pkt_num", | |
310 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, | |
311 | {"mac_tx_12288_16383_oct_pkt_num", | |
312 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, | |
313 | {"mac_tx_1519_max_good_pkt_num", | |
314 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, | |
315 | {"mac_tx_1519_max_bad_pkt_num", | |
316 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, | |
46a3df9f S |
317 | {"mac_rx_total_pkt_num", |
318 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, | |
319 | {"mac_rx_total_oct_num", | |
320 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, | |
321 | {"mac_rx_good_pkt_num", | |
322 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, | |
323 | {"mac_rx_bad_pkt_num", | |
324 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, | |
325 | {"mac_rx_good_oct_num", | |
326 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, | |
327 | {"mac_rx_bad_oct_num", | |
328 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, | |
329 | {"mac_rx_uni_pkt_num", | |
330 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, | |
331 | {"mac_rx_multi_pkt_num", | |
332 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, | |
333 | {"mac_rx_broad_pkt_num", | |
334 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, | |
335 | {"mac_rx_undersize_pkt_num", | |
336 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, | |
f3426583 JS |
337 | {"mac_rx_oversize_pkt_num", |
338 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, | |
46a3df9f S |
339 | {"mac_rx_64_oct_pkt_num", |
340 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, | |
341 | {"mac_rx_65_127_oct_pkt_num", | |
342 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, | |
343 | {"mac_rx_128_255_oct_pkt_num", | |
344 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, | |
345 | {"mac_rx_256_511_oct_pkt_num", | |
346 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, | |
347 | {"mac_rx_512_1023_oct_pkt_num", | |
348 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, | |
349 | {"mac_rx_1024_1518_oct_pkt_num", | |
350 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, | |
b42874e4 JS |
351 | {"mac_rx_1519_2047_oct_pkt_num", |
352 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, | |
353 | {"mac_rx_2048_4095_oct_pkt_num", | |
354 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, | |
355 | {"mac_rx_4096_8191_oct_pkt_num", | |
356 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, | |
b42874e4 JS |
357 | {"mac_rx_8192_9216_oct_pkt_num", |
358 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, | |
359 | {"mac_rx_9217_12287_oct_pkt_num", | |
360 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, | |
361 | {"mac_rx_12288_16383_oct_pkt_num", | |
362 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, | |
363 | {"mac_rx_1519_max_good_pkt_num", | |
364 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, | |
365 | {"mac_rx_1519_max_bad_pkt_num", | |
366 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, | |
46a3df9f | 367 | |
c36317be JS |
368 | {"mac_tx_fragment_pkt_num", |
369 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, | |
370 | {"mac_tx_undermin_pkt_num", | |
371 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, | |
372 | {"mac_tx_jabber_pkt_num", | |
373 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, | |
374 | {"mac_tx_err_all_pkt_num", | |
375 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, | |
376 | {"mac_tx_from_app_good_pkt_num", | |
377 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, | |
378 | {"mac_tx_from_app_bad_pkt_num", | |
379 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, | |
380 | {"mac_rx_fragment_pkt_num", | |
381 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, | |
382 | {"mac_rx_undermin_pkt_num", | |
383 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, | |
384 | {"mac_rx_jabber_pkt_num", | |
385 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, | |
386 | {"mac_rx_fcs_err_pkt_num", | |
387 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, | |
388 | {"mac_rx_send_app_good_pkt_num", | |
389 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, | |
390 | {"mac_rx_send_app_bad_pkt_num", | |
391 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} | |
46a3df9f S |
392 | }; |
393 | ||
635bfb58 FL |
394 | static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { |
395 | { | |
396 | .flags = HCLGE_MAC_MGR_MASK_VLAN_B, | |
397 | .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP), | |
398 | .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)), | |
399 | .mac_addr_lo16 = cpu_to_le16(htons(0x000E)), | |
400 | .i_port_bitmap = 0x1, | |
401 | }, | |
402 | }; | |
403 | ||
46a3df9f S |
404 | static int hclge_64_bit_update_stats(struct hclge_dev *hdev) |
405 | { | |
406 | #define HCLGE_64_BIT_CMD_NUM 5 | |
407 | #define HCLGE_64_BIT_RTN_DATANUM 4 | |
408 | u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats); | |
409 | struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM]; | |
a90bb9a5 | 410 | __le64 *desc_data; |
46a3df9f S |
411 | int i, k, n; |
412 | int ret; | |
413 | ||
414 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true); | |
415 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM); | |
416 | if (ret) { | |
417 | dev_err(&hdev->pdev->dev, | |
418 | "Get 64 bit pkt stats fail, status = %d.\n", ret); | |
419 | return ret; | |
420 | } | |
421 | ||
422 | for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) { | |
423 | if (unlikely(i == 0)) { | |
a90bb9a5 | 424 | desc_data = (__le64 *)(&desc[i].data[0]); |
46a3df9f S |
425 | n = HCLGE_64_BIT_RTN_DATANUM - 1; |
426 | } else { | |
a90bb9a5 | 427 | desc_data = (__le64 *)(&desc[i]); |
46a3df9f S |
428 | n = HCLGE_64_BIT_RTN_DATANUM; |
429 | } | |
430 | for (k = 0; k < n; k++) { | |
a90bb9a5 | 431 | *data++ += le64_to_cpu(*desc_data); |
46a3df9f S |
432 | desc_data++; |
433 | } | |
434 | } | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
439 | static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats) | |
440 | { | |
441 | stats->pkt_curr_buf_cnt = 0; | |
442 | stats->pkt_curr_buf_tc0_cnt = 0; | |
443 | stats->pkt_curr_buf_tc1_cnt = 0; | |
444 | stats->pkt_curr_buf_tc2_cnt = 0; | |
445 | stats->pkt_curr_buf_tc3_cnt = 0; | |
446 | stats->pkt_curr_buf_tc4_cnt = 0; | |
447 | stats->pkt_curr_buf_tc5_cnt = 0; | |
448 | stats->pkt_curr_buf_tc6_cnt = 0; | |
449 | stats->pkt_curr_buf_tc7_cnt = 0; | |
450 | } | |
451 | ||
452 | static int hclge_32_bit_update_stats(struct hclge_dev *hdev) | |
453 | { | |
454 | #define HCLGE_32_BIT_CMD_NUM 8 | |
455 | #define HCLGE_32_BIT_RTN_DATANUM 8 | |
456 | ||
457 | struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM]; | |
458 | struct hclge_32_bit_stats *all_32_bit_stats; | |
a90bb9a5 | 459 | __le32 *desc_data; |
46a3df9f S |
460 | int i, k, n; |
461 | u64 *data; | |
462 | int ret; | |
463 | ||
464 | all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats; | |
465 | data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt); | |
466 | ||
467 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true); | |
468 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM); | |
469 | if (ret) { | |
470 | dev_err(&hdev->pdev->dev, | |
471 | "Get 32 bit pkt stats fail, status = %d.\n", ret); | |
472 | ||
473 | return ret; | |
474 | } | |
475 | ||
476 | hclge_reset_partial_32bit_counter(all_32_bit_stats); | |
477 | for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) { | |
478 | if (unlikely(i == 0)) { | |
a90bb9a5 YL |
479 | __le16 *desc_data_16bit; |
480 | ||
46a3df9f | 481 | all_32_bit_stats->igu_rx_err_pkt += |
a90bb9a5 YL |
482 | le32_to_cpu(desc[i].data[0]); |
483 | ||
484 | desc_data_16bit = (__le16 *)&desc[i].data[1]; | |
46a3df9f | 485 | all_32_bit_stats->igu_rx_no_eof_pkt += |
a90bb9a5 YL |
486 | le16_to_cpu(*desc_data_16bit); |
487 | ||
488 | desc_data_16bit++; | |
46a3df9f | 489 | all_32_bit_stats->igu_rx_no_sof_pkt += |
a90bb9a5 | 490 | le16_to_cpu(*desc_data_16bit); |
46a3df9f | 491 | |
a90bb9a5 | 492 | desc_data = &desc[i].data[2]; |
46a3df9f S |
493 | n = HCLGE_32_BIT_RTN_DATANUM - 4; |
494 | } else { | |
a90bb9a5 | 495 | desc_data = (__le32 *)&desc[i]; |
46a3df9f S |
496 | n = HCLGE_32_BIT_RTN_DATANUM; |
497 | } | |
498 | for (k = 0; k < n; k++) { | |
a90bb9a5 | 499 | *data++ += le32_to_cpu(*desc_data); |
46a3df9f S |
500 | desc_data++; |
501 | } | |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
fe36292f JS |
507 | static int hclge_mac_get_traffic_stats(struct hclge_dev *hdev) |
508 | { | |
509 | struct hclge_mac_stats *mac_stats = &hdev->hw_stats.mac_stats; | |
510 | struct hclge_desc desc; | |
511 | __le64 *desc_data; | |
512 | int ret; | |
513 | ||
514 | /* for fiber port, need to query the total rx/tx packets statstics, | |
515 | * used for data transferring checking. | |
516 | */ | |
517 | if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) | |
518 | return 0; | |
519 | ||
520 | if (test_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) | |
521 | return 0; | |
522 | ||
523 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_STATS_MAC_TRAFFIC, true); | |
524 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
525 | if (ret) { | |
526 | dev_err(&hdev->pdev->dev, | |
527 | "Get MAC total pkt stats fail, ret = %d\n", ret); | |
528 | ||
529 | return ret; | |
530 | } | |
531 | ||
532 | desc_data = (__le64 *)(&desc.data[0]); | |
533 | mac_stats->mac_tx_total_pkt_num += le64_to_cpu(*desc_data++); | |
534 | mac_stats->mac_rx_total_pkt_num += le64_to_cpu(*desc_data); | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
46a3df9f S |
539 | static int hclge_mac_update_stats(struct hclge_dev *hdev) |
540 | { | |
b42874e4 | 541 | #define HCLGE_MAC_CMD_NUM 21 |
46a3df9f S |
542 | #define HCLGE_RTN_DATA_NUM 4 |
543 | ||
544 | u64 *data = (u64 *)(&hdev->hw_stats.mac_stats); | |
545 | struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; | |
a90bb9a5 | 546 | __le64 *desc_data; |
46a3df9f S |
547 | int i, k, n; |
548 | int ret; | |
549 | ||
550 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); | |
551 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); | |
552 | if (ret) { | |
553 | dev_err(&hdev->pdev->dev, | |
554 | "Get MAC pkt stats fail, status = %d.\n", ret); | |
555 | ||
556 | return ret; | |
557 | } | |
558 | ||
559 | for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) { | |
560 | if (unlikely(i == 0)) { | |
a90bb9a5 | 561 | desc_data = (__le64 *)(&desc[i].data[0]); |
46a3df9f S |
562 | n = HCLGE_RTN_DATA_NUM - 2; |
563 | } else { | |
a90bb9a5 | 564 | desc_data = (__le64 *)(&desc[i]); |
46a3df9f S |
565 | n = HCLGE_RTN_DATA_NUM; |
566 | } | |
567 | for (k = 0; k < n; k++) { | |
a90bb9a5 | 568 | *data++ += le64_to_cpu(*desc_data); |
46a3df9f S |
569 | desc_data++; |
570 | } | |
571 | } | |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
576 | static int hclge_tqps_update_stats(struct hnae3_handle *handle) | |
577 | { | |
578 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
579 | struct hclge_vport *vport = hclge_get_vport(handle); | |
580 | struct hclge_dev *hdev = vport->back; | |
581 | struct hnae3_queue *queue; | |
582 | struct hclge_desc desc[1]; | |
583 | struct hclge_tqp *tqp; | |
584 | int ret, i; | |
585 | ||
586 | for (i = 0; i < kinfo->num_tqps; i++) { | |
587 | queue = handle->kinfo.tqp[i]; | |
588 | tqp = container_of(queue, struct hclge_tqp, q); | |
589 | /* command : HCLGE_OPC_QUERY_IGU_STAT */ | |
590 | hclge_cmd_setup_basic_desc(&desc[0], | |
591 | HCLGE_OPC_QUERY_RX_STATUS, | |
592 | true); | |
593 | ||
a90bb9a5 | 594 | desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); |
46a3df9f S |
595 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
596 | if (ret) { | |
597 | dev_err(&hdev->pdev->dev, | |
598 | "Query tqp stat fail, status = %d,queue = %d\n", | |
599 | ret, i); | |
600 | return ret; | |
601 | } | |
602 | tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += | |
93991b65 | 603 | le32_to_cpu(desc[0].data[1]); |
46a3df9f S |
604 | } |
605 | ||
606 | for (i = 0; i < kinfo->num_tqps; i++) { | |
607 | queue = handle->kinfo.tqp[i]; | |
608 | tqp = container_of(queue, struct hclge_tqp, q); | |
609 | /* command : HCLGE_OPC_QUERY_IGU_STAT */ | |
610 | hclge_cmd_setup_basic_desc(&desc[0], | |
611 | HCLGE_OPC_QUERY_TX_STATUS, | |
612 | true); | |
613 | ||
a90bb9a5 | 614 | desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); |
46a3df9f S |
615 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
616 | if (ret) { | |
617 | dev_err(&hdev->pdev->dev, | |
618 | "Query tqp stat fail, status = %d,queue = %d\n", | |
619 | ret, i); | |
620 | return ret; | |
621 | } | |
622 | tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += | |
93991b65 | 623 | le32_to_cpu(desc[0].data[1]); |
46a3df9f S |
624 | } |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data) | |
630 | { | |
631 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
632 | struct hclge_tqp *tqp; | |
633 | u64 *buff = data; | |
634 | int i; | |
635 | ||
636 | for (i = 0; i < kinfo->num_tqps; i++) { | |
637 | tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
a90bb9a5 | 638 | *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; |
46a3df9f S |
639 | } |
640 | ||
641 | for (i = 0; i < kinfo->num_tqps; i++) { | |
642 | tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
a90bb9a5 | 643 | *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; |
46a3df9f S |
644 | } |
645 | ||
646 | return buff; | |
647 | } | |
648 | ||
649 | static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset) | |
650 | { | |
651 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
652 | ||
653 | return kinfo->num_tqps * (2); | |
654 | } | |
655 | ||
656 | static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data) | |
657 | { | |
658 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
659 | u8 *buff = data; | |
660 | int i = 0; | |
661 | ||
662 | for (i = 0; i < kinfo->num_tqps; i++) { | |
663 | struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i], | |
664 | struct hclge_tqp, q); | |
c36317be | 665 | snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", |
46a3df9f S |
666 | tqp->index); |
667 | buff = buff + ETH_GSTRING_LEN; | |
668 | } | |
669 | ||
670 | for (i = 0; i < kinfo->num_tqps; i++) { | |
671 | struct hclge_tqp *tqp = container_of(kinfo->tqp[i], | |
672 | struct hclge_tqp, q); | |
c36317be | 673 | snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", |
46a3df9f S |
674 | tqp->index); |
675 | buff = buff + ETH_GSTRING_LEN; | |
676 | } | |
677 | ||
678 | return buff; | |
679 | } | |
680 | ||
681 | static u64 *hclge_comm_get_stats(void *comm_stats, | |
682 | const struct hclge_comm_stats_str strs[], | |
683 | int size, u64 *data) | |
684 | { | |
685 | u64 *buf = data; | |
686 | u32 i; | |
687 | ||
688 | for (i = 0; i < size; i++) | |
689 | buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset); | |
690 | ||
691 | return buf + size; | |
692 | } | |
693 | ||
694 | static u8 *hclge_comm_get_strings(u32 stringset, | |
695 | const struct hclge_comm_stats_str strs[], | |
696 | int size, u8 *data) | |
697 | { | |
698 | char *buff = (char *)data; | |
699 | u32 i; | |
700 | ||
701 | if (stringset != ETH_SS_STATS) | |
702 | return buff; | |
703 | ||
704 | for (i = 0; i < size; i++) { | |
705 | snprintf(buff, ETH_GSTRING_LEN, | |
706 | strs[i].desc); | |
707 | buff = buff + ETH_GSTRING_LEN; | |
708 | } | |
709 | ||
710 | return (u8 *)buff; | |
711 | } | |
712 | ||
713 | static void hclge_update_netstat(struct hclge_hw_stats *hw_stats, | |
714 | struct net_device_stats *net_stats) | |
715 | { | |
716 | net_stats->tx_dropped = 0; | |
717 | net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num; | |
718 | net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num; | |
719 | net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num; | |
720 | ||
f3426583 | 721 | net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
46a3df9f | 722 | net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num; |
46a3df9f S |
723 | net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt; |
724 | net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt; | |
c36317be | 725 | net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; |
46a3df9f S |
726 | |
727 | net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num; | |
728 | net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num; | |
729 | ||
c36317be | 730 | net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; |
46a3df9f S |
731 | net_stats->rx_length_errors = |
732 | hw_stats->mac_stats.mac_rx_undersize_pkt_num; | |
733 | net_stats->rx_length_errors += | |
f3426583 | 734 | hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
46a3df9f | 735 | net_stats->rx_over_errors = |
f3426583 | 736 | hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
46a3df9f S |
737 | } |
738 | ||
739 | static void hclge_update_stats_for_all(struct hclge_dev *hdev) | |
740 | { | |
741 | struct hnae3_handle *handle; | |
742 | int status; | |
743 | ||
744 | handle = &hdev->vport[0].nic; | |
745 | if (handle->client) { | |
746 | status = hclge_tqps_update_stats(handle); | |
747 | if (status) { | |
748 | dev_err(&hdev->pdev->dev, | |
749 | "Update TQPS stats fail, status = %d.\n", | |
750 | status); | |
751 | } | |
752 | } | |
753 | ||
754 | status = hclge_mac_update_stats(hdev); | |
755 | if (status) | |
756 | dev_err(&hdev->pdev->dev, | |
757 | "Update MAC stats fail, status = %d.\n", status); | |
758 | ||
759 | status = hclge_32_bit_update_stats(hdev); | |
760 | if (status) | |
761 | dev_err(&hdev->pdev->dev, | |
762 | "Update 32 bit stats fail, status = %d.\n", | |
763 | status); | |
764 | ||
765 | hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats); | |
766 | } | |
767 | ||
768 | static void hclge_update_stats(struct hnae3_handle *handle, | |
769 | struct net_device_stats *net_stats) | |
770 | { | |
771 | struct hclge_vport *vport = hclge_get_vport(handle); | |
772 | struct hclge_dev *hdev = vport->back; | |
773 | struct hclge_hw_stats *hw_stats = &hdev->hw_stats; | |
774 | int status; | |
775 | ||
7a5d2a39 JS |
776 | if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) |
777 | return; | |
778 | ||
46a3df9f S |
779 | status = hclge_mac_update_stats(hdev); |
780 | if (status) | |
781 | dev_err(&hdev->pdev->dev, | |
782 | "Update MAC stats fail, status = %d.\n", | |
783 | status); | |
784 | ||
785 | status = hclge_32_bit_update_stats(hdev); | |
786 | if (status) | |
787 | dev_err(&hdev->pdev->dev, | |
788 | "Update 32 bit stats fail, status = %d.\n", | |
789 | status); | |
790 | ||
791 | status = hclge_64_bit_update_stats(hdev); | |
792 | if (status) | |
793 | dev_err(&hdev->pdev->dev, | |
794 | "Update 64 bit stats fail, status = %d.\n", | |
795 | status); | |
796 | ||
797 | status = hclge_tqps_update_stats(handle); | |
798 | if (status) | |
799 | dev_err(&hdev->pdev->dev, | |
800 | "Update TQPS stats fail, status = %d.\n", | |
801 | status); | |
802 | ||
803 | hclge_update_netstat(hw_stats, net_stats); | |
7a5d2a39 JS |
804 | |
805 | clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); | |
46a3df9f S |
806 | } |
807 | ||
808 | static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) | |
809 | { | |
810 | #define HCLGE_LOOPBACK_TEST_FLAGS 0x7 | |
811 | ||
812 | struct hclge_vport *vport = hclge_get_vport(handle); | |
813 | struct hclge_dev *hdev = vport->back; | |
814 | int count = 0; | |
815 | ||
816 | /* Loopback test support rules: | |
817 | * mac: only GE mode support | |
818 | * serdes: all mac mode will support include GE/XGE/LGE/CGE | |
819 | * phy: only support when phy device exist on board | |
820 | */ | |
821 | if (stringset == ETH_SS_TEST) { | |
822 | /* clear loopback bit flags at first */ | |
823 | handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); | |
824 | if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || | |
825 | hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || | |
826 | hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { | |
827 | count += 1; | |
828 | handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK; | |
829 | } else { | |
830 | count = -EOPNOTSUPP; | |
831 | } | |
832 | } else if (stringset == ETH_SS_STATS) { | |
833 | count = ARRAY_SIZE(g_mac_stats_string) + | |
834 | ARRAY_SIZE(g_all_32bit_stats_string) + | |
835 | ARRAY_SIZE(g_all_64bit_stats_string) + | |
836 | hclge_tqps_get_sset_count(handle, stringset); | |
837 | } | |
838 | ||
839 | return count; | |
840 | } | |
841 | ||
842 | static void hclge_get_strings(struct hnae3_handle *handle, | |
843 | u32 stringset, | |
844 | u8 *data) | |
845 | { | |
846 | u8 *p = (char *)data; | |
847 | int size; | |
848 | ||
849 | if (stringset == ETH_SS_STATS) { | |
850 | size = ARRAY_SIZE(g_mac_stats_string); | |
851 | p = hclge_comm_get_strings(stringset, | |
852 | g_mac_stats_string, | |
853 | size, | |
854 | p); | |
855 | size = ARRAY_SIZE(g_all_32bit_stats_string); | |
856 | p = hclge_comm_get_strings(stringset, | |
857 | g_all_32bit_stats_string, | |
858 | size, | |
859 | p); | |
860 | size = ARRAY_SIZE(g_all_64bit_stats_string); | |
861 | p = hclge_comm_get_strings(stringset, | |
862 | g_all_64bit_stats_string, | |
863 | size, | |
864 | p); | |
865 | p = hclge_tqps_get_strings(handle, p); | |
866 | } else if (stringset == ETH_SS_TEST) { | |
867 | if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) { | |
868 | memcpy(p, | |
869 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC], | |
870 | ETH_GSTRING_LEN); | |
871 | p += ETH_GSTRING_LEN; | |
872 | } | |
873 | if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) { | |
874 | memcpy(p, | |
875 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES], | |
876 | ETH_GSTRING_LEN); | |
877 | p += ETH_GSTRING_LEN; | |
878 | } | |
879 | if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { | |
880 | memcpy(p, | |
881 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY], | |
882 | ETH_GSTRING_LEN); | |
883 | p += ETH_GSTRING_LEN; | |
884 | } | |
885 | } | |
886 | } | |
887 | ||
888 | static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) | |
889 | { | |
890 | struct hclge_vport *vport = hclge_get_vport(handle); | |
891 | struct hclge_dev *hdev = vport->back; | |
892 | u64 *p; | |
893 | ||
894 | p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats, | |
895 | g_mac_stats_string, | |
896 | ARRAY_SIZE(g_mac_stats_string), | |
897 | data); | |
898 | p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats, | |
899 | g_all_32bit_stats_string, | |
900 | ARRAY_SIZE(g_all_32bit_stats_string), | |
901 | p); | |
902 | p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats, | |
903 | g_all_64bit_stats_string, | |
904 | ARRAY_SIZE(g_all_64bit_stats_string), | |
905 | p); | |
906 | p = hclge_tqps_get_stats(handle, p); | |
907 | } | |
908 | ||
909 | static int hclge_parse_func_status(struct hclge_dev *hdev, | |
d44f9b63 | 910 | struct hclge_func_status_cmd *status) |
46a3df9f S |
911 | { |
912 | if (!(status->pf_state & HCLGE_PF_STATE_DONE)) | |
913 | return -EINVAL; | |
914 | ||
915 | /* Set the pf to main pf */ | |
916 | if (status->pf_state & HCLGE_PF_STATE_MAIN) | |
917 | hdev->flag |= HCLGE_FLAG_MAIN; | |
918 | else | |
919 | hdev->flag &= ~HCLGE_FLAG_MAIN; | |
920 | ||
46a3df9f S |
921 | return 0; |
922 | } | |
923 | ||
924 | static int hclge_query_function_status(struct hclge_dev *hdev) | |
925 | { | |
d44f9b63 | 926 | struct hclge_func_status_cmd *req; |
46a3df9f S |
927 | struct hclge_desc desc; |
928 | int timeout = 0; | |
929 | int ret; | |
930 | ||
931 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); | |
d44f9b63 | 932 | req = (struct hclge_func_status_cmd *)desc.data; |
46a3df9f S |
933 | |
934 | do { | |
935 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
936 | if (ret) { | |
937 | dev_err(&hdev->pdev->dev, | |
938 | "query function status failed %d.\n", | |
939 | ret); | |
940 | ||
941 | return ret; | |
942 | } | |
943 | ||
944 | /* Check pf reset is done */ | |
945 | if (req->pf_state) | |
946 | break; | |
947 | usleep_range(1000, 2000); | |
948 | } while (timeout++ < 5); | |
949 | ||
950 | ret = hclge_parse_func_status(hdev, req); | |
951 | ||
952 | return ret; | |
953 | } | |
954 | ||
955 | static int hclge_query_pf_resource(struct hclge_dev *hdev) | |
956 | { | |
d44f9b63 | 957 | struct hclge_pf_res_cmd *req; |
46a3df9f S |
958 | struct hclge_desc desc; |
959 | int ret; | |
960 | ||
961 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); | |
962 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
963 | if (ret) { | |
964 | dev_err(&hdev->pdev->dev, | |
965 | "query pf resource failed %d.\n", ret); | |
966 | return ret; | |
967 | } | |
968 | ||
d44f9b63 | 969 | req = (struct hclge_pf_res_cmd *)desc.data; |
46a3df9f S |
970 | hdev->num_tqps = __le16_to_cpu(req->tqp_num); |
971 | hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; | |
972 | ||
e92a0843 | 973 | if (hnae3_dev_roce_supported(hdev)) { |
887c3820 | 974 | hdev->num_roce_msi = |
46a3df9f S |
975 | hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number), |
976 | HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); | |
977 | ||
978 | /* PF should have NIC vectors and Roce vectors, | |
979 | * NIC vectors are queued before Roce vectors. | |
980 | */ | |
887c3820 | 981 | hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET; |
46a3df9f S |
982 | } else { |
983 | hdev->num_msi = | |
984 | hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number), | |
985 | HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); | |
986 | } | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | static int hclge_parse_speed(int speed_cmd, int *speed) | |
992 | { | |
993 | switch (speed_cmd) { | |
994 | case 6: | |
995 | *speed = HCLGE_MAC_SPEED_10M; | |
996 | break; | |
997 | case 7: | |
998 | *speed = HCLGE_MAC_SPEED_100M; | |
999 | break; | |
1000 | case 0: | |
1001 | *speed = HCLGE_MAC_SPEED_1G; | |
1002 | break; | |
1003 | case 1: | |
1004 | *speed = HCLGE_MAC_SPEED_10G; | |
1005 | break; | |
1006 | case 2: | |
1007 | *speed = HCLGE_MAC_SPEED_25G; | |
1008 | break; | |
1009 | case 3: | |
1010 | *speed = HCLGE_MAC_SPEED_40G; | |
1011 | break; | |
1012 | case 4: | |
1013 | *speed = HCLGE_MAC_SPEED_50G; | |
1014 | break; | |
1015 | case 5: | |
1016 | *speed = HCLGE_MAC_SPEED_100G; | |
1017 | break; | |
1018 | default: | |
1019 | return -EINVAL; | |
1020 | } | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
d92ceae9 FL |
1025 | static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, |
1026 | u8 speed_ability) | |
1027 | { | |
1028 | unsigned long *supported = hdev->hw.mac.supported; | |
1029 | ||
1030 | if (speed_ability & HCLGE_SUPPORT_1G_BIT) | |
1031 | set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, | |
1032 | supported); | |
1033 | ||
1034 | if (speed_ability & HCLGE_SUPPORT_10G_BIT) | |
1035 | set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, | |
1036 | supported); | |
1037 | ||
1038 | if (speed_ability & HCLGE_SUPPORT_25G_BIT) | |
1039 | set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, | |
1040 | supported); | |
1041 | ||
1042 | if (speed_ability & HCLGE_SUPPORT_50G_BIT) | |
1043 | set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, | |
1044 | supported); | |
1045 | ||
1046 | if (speed_ability & HCLGE_SUPPORT_100G_BIT) | |
1047 | set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, | |
1048 | supported); | |
1049 | ||
1050 | set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); | |
1051 | set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); | |
1052 | } | |
1053 | ||
1054 | static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability) | |
1055 | { | |
1056 | u8 media_type = hdev->hw.mac.media_type; | |
1057 | ||
1058 | if (media_type != HNAE3_MEDIA_TYPE_FIBER) | |
1059 | return; | |
1060 | ||
1061 | hclge_parse_fiber_link_mode(hdev, speed_ability); | |
1062 | } | |
1063 | ||
46a3df9f S |
1064 | static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) |
1065 | { | |
d44f9b63 | 1066 | struct hclge_cfg_param_cmd *req; |
46a3df9f S |
1067 | u64 mac_addr_tmp_high; |
1068 | u64 mac_addr_tmp; | |
1069 | int i; | |
1070 | ||
d44f9b63 | 1071 | req = (struct hclge_cfg_param_cmd *)desc[0].data; |
46a3df9f S |
1072 | |
1073 | /* get the configuration */ | |
1074 | cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]), | |
1075 | HCLGE_CFG_VMDQ_M, | |
1076 | HCLGE_CFG_VMDQ_S); | |
1077 | cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]), | |
1078 | HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); | |
1079 | cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]), | |
1080 | HCLGE_CFG_TQP_DESC_N_M, | |
1081 | HCLGE_CFG_TQP_DESC_N_S); | |
1082 | ||
1083 | cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]), | |
1084 | HCLGE_CFG_PHY_ADDR_M, | |
1085 | HCLGE_CFG_PHY_ADDR_S); | |
1086 | cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]), | |
1087 | HCLGE_CFG_MEDIA_TP_M, | |
1088 | HCLGE_CFG_MEDIA_TP_S); | |
1089 | cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]), | |
1090 | HCLGE_CFG_RX_BUF_LEN_M, | |
1091 | HCLGE_CFG_RX_BUF_LEN_S); | |
1092 | /* get mac_address */ | |
1093 | mac_addr_tmp = __le32_to_cpu(req->param[2]); | |
1094 | mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]), | |
1095 | HCLGE_CFG_MAC_ADDR_H_M, | |
1096 | HCLGE_CFG_MAC_ADDR_H_S); | |
1097 | ||
1098 | mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; | |
1099 | ||
1100 | cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]), | |
1101 | HCLGE_CFG_DEFAULT_SPEED_M, | |
1102 | HCLGE_CFG_DEFAULT_SPEED_S); | |
c408e202 PL |
1103 | cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]), |
1104 | HCLGE_CFG_RSS_SIZE_M, | |
1105 | HCLGE_CFG_RSS_SIZE_S); | |
1106 | ||
46a3df9f S |
1107 | for (i = 0; i < ETH_ALEN; i++) |
1108 | cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; | |
1109 | ||
d44f9b63 | 1110 | req = (struct hclge_cfg_param_cmd *)desc[1].data; |
46a3df9f | 1111 | cfg->numa_node_map = __le32_to_cpu(req->param[0]); |
d92ceae9 FL |
1112 | |
1113 | cfg->speed_ability = hnae_get_field(__le32_to_cpu(req->param[1]), | |
1114 | HCLGE_CFG_SPEED_ABILITY_M, | |
1115 | HCLGE_CFG_SPEED_ABILITY_S); | |
46a3df9f S |
1116 | } |
1117 | ||
1118 | /* hclge_get_cfg: query the static parameter from flash | |
1119 | * @hdev: pointer to struct hclge_dev | |
1120 | * @hcfg: the config structure to be getted | |
1121 | */ | |
1122 | static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) | |
1123 | { | |
1124 | struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; | |
d44f9b63 | 1125 | struct hclge_cfg_param_cmd *req; |
46a3df9f S |
1126 | int i, ret; |
1127 | ||
1128 | for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { | |
a90bb9a5 YL |
1129 | u32 offset = 0; |
1130 | ||
d44f9b63 | 1131 | req = (struct hclge_cfg_param_cmd *)desc[i].data; |
46a3df9f S |
1132 | hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, |
1133 | true); | |
a90bb9a5 | 1134 | hnae_set_field(offset, HCLGE_CFG_OFFSET_M, |
46a3df9f S |
1135 | HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); |
1136 | /* Len should be united by 4 bytes when send to hardware */ | |
a90bb9a5 | 1137 | hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, |
46a3df9f | 1138 | HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); |
a90bb9a5 | 1139 | req->offset = cpu_to_le32(offset); |
46a3df9f S |
1140 | } |
1141 | ||
1142 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); | |
1143 | if (ret) { | |
1144 | dev_err(&hdev->pdev->dev, | |
1145 | "get config failed %d.\n", ret); | |
1146 | return ret; | |
1147 | } | |
1148 | ||
1149 | hclge_parse_cfg(hcfg, desc); | |
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | static int hclge_get_cap(struct hclge_dev *hdev) | |
1154 | { | |
1155 | int ret; | |
1156 | ||
1157 | ret = hclge_query_function_status(hdev); | |
1158 | if (ret) { | |
1159 | dev_err(&hdev->pdev->dev, | |
1160 | "query function status error %d.\n", ret); | |
1161 | return ret; | |
1162 | } | |
1163 | ||
1164 | /* get pf resource */ | |
1165 | ret = hclge_query_pf_resource(hdev); | |
1166 | if (ret) { | |
1167 | dev_err(&hdev->pdev->dev, | |
1168 | "query pf resource error %d.\n", ret); | |
1169 | return ret; | |
1170 | } | |
1171 | ||
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | static int hclge_configure(struct hclge_dev *hdev) | |
1176 | { | |
1177 | struct hclge_cfg cfg; | |
1178 | int ret, i; | |
1179 | ||
1180 | ret = hclge_get_cfg(hdev, &cfg); | |
1181 | if (ret) { | |
1182 | dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret); | |
1183 | return ret; | |
1184 | } | |
1185 | ||
1186 | hdev->num_vmdq_vport = cfg.vmdq_vport_num; | |
1187 | hdev->base_tqp_pid = 0; | |
c408e202 | 1188 | hdev->rss_size_max = cfg.rss_size_max; |
46a3df9f | 1189 | hdev->rx_buf_len = cfg.rx_buf_len; |
fbbb1536 | 1190 | ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); |
46a3df9f | 1191 | hdev->hw.mac.media_type = cfg.media_type; |
2a4776e1 | 1192 | hdev->hw.mac.phy_addr = cfg.phy_addr; |
46a3df9f S |
1193 | hdev->num_desc = cfg.tqp_desc_num; |
1194 | hdev->tm_info.num_pg = 1; | |
cacde272 | 1195 | hdev->tc_max = cfg.tc_num; |
46a3df9f S |
1196 | hdev->tm_info.hw_pfc_map = 0; |
1197 | ||
1198 | ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); | |
1199 | if (ret) { | |
1200 | dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret); | |
1201 | return ret; | |
1202 | } | |
1203 | ||
d92ceae9 FL |
1204 | hclge_parse_link_mode(hdev, cfg.speed_ability); |
1205 | ||
cacde272 YL |
1206 | if ((hdev->tc_max > HNAE3_MAX_TC) || |
1207 | (hdev->tc_max < 1)) { | |
46a3df9f | 1208 | dev_warn(&hdev->pdev->dev, "TC num = %d.\n", |
cacde272 YL |
1209 | hdev->tc_max); |
1210 | hdev->tc_max = 1; | |
46a3df9f S |
1211 | } |
1212 | ||
cacde272 YL |
1213 | /* Dev does not support DCB */ |
1214 | if (!hnae3_dev_dcb_supported(hdev)) { | |
1215 | hdev->tc_max = 1; | |
1216 | hdev->pfc_max = 0; | |
1217 | } else { | |
1218 | hdev->pfc_max = hdev->tc_max; | |
1219 | } | |
1220 | ||
1221 | hdev->tm_info.num_tc = hdev->tc_max; | |
1222 | ||
46a3df9f | 1223 | /* Currently not support uncontiuous tc */ |
cacde272 | 1224 | for (i = 0; i < hdev->tm_info.num_tc; i++) |
46a3df9f S |
1225 | hnae_set_bit(hdev->hw_tc_map, i, 1); |
1226 | ||
f8362fe1 | 1227 | hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; |
46a3df9f S |
1228 | |
1229 | return ret; | |
1230 | } | |
1231 | ||
1232 | static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, | |
1233 | int tso_mss_max) | |
1234 | { | |
d44f9b63 | 1235 | struct hclge_cfg_tso_status_cmd *req; |
46a3df9f | 1236 | struct hclge_desc desc; |
a90bb9a5 | 1237 | u16 tso_mss; |
46a3df9f S |
1238 | |
1239 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); | |
1240 | ||
d44f9b63 | 1241 | req = (struct hclge_cfg_tso_status_cmd *)desc.data; |
a90bb9a5 YL |
1242 | |
1243 | tso_mss = 0; | |
1244 | hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, | |
46a3df9f | 1245 | HCLGE_TSO_MSS_MIN_S, tso_mss_min); |
a90bb9a5 YL |
1246 | req->tso_mss_min = cpu_to_le16(tso_mss); |
1247 | ||
1248 | tso_mss = 0; | |
1249 | hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, | |
46a3df9f | 1250 | HCLGE_TSO_MSS_MIN_S, tso_mss_max); |
a90bb9a5 | 1251 | req->tso_mss_max = cpu_to_le16(tso_mss); |
46a3df9f S |
1252 | |
1253 | return hclge_cmd_send(&hdev->hw, &desc, 1); | |
1254 | } | |
1255 | ||
1256 | static int hclge_alloc_tqps(struct hclge_dev *hdev) | |
1257 | { | |
1258 | struct hclge_tqp *tqp; | |
1259 | int i; | |
1260 | ||
1261 | hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, | |
1262 | sizeof(struct hclge_tqp), GFP_KERNEL); | |
1263 | if (!hdev->htqp) | |
1264 | return -ENOMEM; | |
1265 | ||
1266 | tqp = hdev->htqp; | |
1267 | ||
1268 | for (i = 0; i < hdev->num_tqps; i++) { | |
1269 | tqp->dev = &hdev->pdev->dev; | |
1270 | tqp->index = i; | |
1271 | ||
1272 | tqp->q.ae_algo = &ae_algo; | |
1273 | tqp->q.buf_size = hdev->rx_buf_len; | |
1274 | tqp->q.desc_num = hdev->num_desc; | |
1275 | tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET + | |
1276 | i * HCLGE_TQP_REG_SIZE; | |
1277 | ||
1278 | tqp++; | |
1279 | } | |
1280 | ||
1281 | return 0; | |
1282 | } | |
1283 | ||
1284 | static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, | |
1285 | u16 tqp_pid, u16 tqp_vid, bool is_pf) | |
1286 | { | |
d44f9b63 | 1287 | struct hclge_tqp_map_cmd *req; |
46a3df9f S |
1288 | struct hclge_desc desc; |
1289 | int ret; | |
1290 | ||
1291 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); | |
1292 | ||
d44f9b63 | 1293 | req = (struct hclge_tqp_map_cmd *)desc.data; |
46a3df9f | 1294 | req->tqp_id = cpu_to_le16(tqp_pid); |
a90bb9a5 | 1295 | req->tqp_vf = func_id; |
46a3df9f S |
1296 | req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B | |
1297 | 1 << HCLGE_TQP_MAP_EN_B; | |
1298 | req->tqp_vid = cpu_to_le16(tqp_vid); | |
1299 | ||
1300 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
1301 | if (ret) { | |
1302 | dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", | |
1303 | ret); | |
1304 | return ret; | |
1305 | } | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
1310 | static int hclge_assign_tqp(struct hclge_vport *vport, | |
1311 | struct hnae3_queue **tqp, u16 num_tqps) | |
1312 | { | |
1313 | struct hclge_dev *hdev = vport->back; | |
7df7dad6 | 1314 | int i, alloced; |
46a3df9f S |
1315 | |
1316 | for (i = 0, alloced = 0; i < hdev->num_tqps && | |
1317 | alloced < num_tqps; i++) { | |
1318 | if (!hdev->htqp[i].alloced) { | |
1319 | hdev->htqp[i].q.handle = &vport->nic; | |
1320 | hdev->htqp[i].q.tqp_index = alloced; | |
1321 | tqp[alloced] = &hdev->htqp[i].q; | |
1322 | hdev->htqp[i].alloced = true; | |
46a3df9f S |
1323 | alloced++; |
1324 | } | |
1325 | } | |
1326 | vport->alloc_tqps = num_tqps; | |
1327 | ||
1328 | return 0; | |
1329 | } | |
1330 | ||
1331 | static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps) | |
1332 | { | |
1333 | struct hnae3_handle *nic = &vport->nic; | |
1334 | struct hnae3_knic_private_info *kinfo = &nic->kinfo; | |
1335 | struct hclge_dev *hdev = vport->back; | |
1336 | int i, ret; | |
1337 | ||
1338 | kinfo->num_desc = hdev->num_desc; | |
1339 | kinfo->rx_buf_len = hdev->rx_buf_len; | |
1340 | kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc); | |
1341 | kinfo->rss_size | |
1342 | = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc); | |
1343 | kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc; | |
1344 | ||
1345 | for (i = 0; i < HNAE3_MAX_TC; i++) { | |
1346 | if (hdev->hw_tc_map & BIT(i)) { | |
1347 | kinfo->tc_info[i].enable = true; | |
1348 | kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; | |
1349 | kinfo->tc_info[i].tqp_count = kinfo->rss_size; | |
1350 | kinfo->tc_info[i].tc = i; | |
1351 | } else { | |
1352 | /* Set to default queue if TC is disable */ | |
1353 | kinfo->tc_info[i].enable = false; | |
1354 | kinfo->tc_info[i].tqp_offset = 0; | |
1355 | kinfo->tc_info[i].tqp_count = 1; | |
1356 | kinfo->tc_info[i].tc = 0; | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, | |
1361 | sizeof(struct hnae3_queue *), GFP_KERNEL); | |
1362 | if (!kinfo->tqp) | |
1363 | return -ENOMEM; | |
1364 | ||
1365 | ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps); | |
1366 | if (ret) { | |
1367 | dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); | |
1368 | return -EINVAL; | |
1369 | } | |
1370 | ||
1371 | return 0; | |
1372 | } | |
1373 | ||
7df7dad6 L |
1374 | static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, |
1375 | struct hclge_vport *vport) | |
1376 | { | |
1377 | struct hnae3_handle *nic = &vport->nic; | |
1378 | struct hnae3_knic_private_info *kinfo; | |
1379 | u16 i; | |
1380 | ||
1381 | kinfo = &nic->kinfo; | |
1382 | for (i = 0; i < kinfo->num_tqps; i++) { | |
1383 | struct hclge_tqp *q = | |
1384 | container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
1385 | bool is_pf; | |
1386 | int ret; | |
1387 | ||
1388 | is_pf = !(vport->vport_id); | |
1389 | ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, | |
1390 | i, is_pf); | |
1391 | if (ret) | |
1392 | return ret; | |
1393 | } | |
1394 | ||
1395 | return 0; | |
1396 | } | |
1397 | ||
1398 | static int hclge_map_tqp(struct hclge_dev *hdev) | |
1399 | { | |
1400 | struct hclge_vport *vport = hdev->vport; | |
1401 | u16 i, num_vport; | |
1402 | ||
1403 | num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; | |
1404 | for (i = 0; i < num_vport; i++) { | |
1405 | int ret; | |
1406 | ||
1407 | ret = hclge_map_tqp_to_vport(hdev, vport); | |
1408 | if (ret) | |
1409 | return ret; | |
1410 | ||
1411 | vport++; | |
1412 | } | |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
46a3df9f S |
1417 | static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps) |
1418 | { | |
1419 | /* this would be initialized later */ | |
1420 | } | |
1421 | ||
1422 | static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) | |
1423 | { | |
1424 | struct hnae3_handle *nic = &vport->nic; | |
1425 | struct hclge_dev *hdev = vport->back; | |
1426 | int ret; | |
1427 | ||
1428 | nic->pdev = hdev->pdev; | |
1429 | nic->ae_algo = &ae_algo; | |
1430 | nic->numa_node_mask = hdev->numa_node_mask; | |
1431 | ||
1432 | if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) { | |
1433 | ret = hclge_knic_setup(vport, num_tqps); | |
1434 | if (ret) { | |
1435 | dev_err(&hdev->pdev->dev, "knic setup failed %d\n", | |
1436 | ret); | |
1437 | return ret; | |
1438 | } | |
1439 | } else { | |
1440 | hclge_unic_setup(vport, num_tqps); | |
1441 | } | |
1442 | ||
1443 | return 0; | |
1444 | } | |
1445 | ||
1446 | static int hclge_alloc_vport(struct hclge_dev *hdev) | |
1447 | { | |
1448 | struct pci_dev *pdev = hdev->pdev; | |
1449 | struct hclge_vport *vport; | |
1450 | u32 tqp_main_vport; | |
1451 | u32 tqp_per_vport; | |
1452 | int num_vport, i; | |
1453 | int ret; | |
1454 | ||
1455 | /* We need to alloc a vport for main NIC of PF */ | |
1456 | num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; | |
1457 | ||
b76edfb2 HT |
1458 | if (hdev->num_tqps < num_vport) { |
1459 | dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)", | |
1460 | hdev->num_tqps, num_vport); | |
1461 | return -EINVAL; | |
1462 | } | |
46a3df9f S |
1463 | |
1464 | /* Alloc the same number of TQPs for every vport */ | |
1465 | tqp_per_vport = hdev->num_tqps / num_vport; | |
1466 | tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; | |
1467 | ||
1468 | vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), | |
1469 | GFP_KERNEL); | |
1470 | if (!vport) | |
1471 | return -ENOMEM; | |
1472 | ||
1473 | hdev->vport = vport; | |
1474 | hdev->num_alloc_vport = num_vport; | |
1475 | ||
1476 | #ifdef CONFIG_PCI_IOV | |
1477 | /* Enable SRIOV */ | |
1478 | if (hdev->num_req_vfs) { | |
1479 | dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n", | |
1480 | hdev->num_req_vfs); | |
1481 | ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs); | |
1482 | if (ret) { | |
1483 | hdev->num_alloc_vfs = 0; | |
1484 | dev_err(&pdev->dev, "SRIOV enable failed %d\n", | |
1485 | ret); | |
1486 | return ret; | |
1487 | } | |
1488 | } | |
1489 | hdev->num_alloc_vfs = hdev->num_req_vfs; | |
1490 | #endif | |
1491 | ||
1492 | for (i = 0; i < num_vport; i++) { | |
1493 | vport->back = hdev; | |
1494 | vport->vport_id = i; | |
1495 | ||
1496 | if (i == 0) | |
1497 | ret = hclge_vport_setup(vport, tqp_main_vport); | |
1498 | else | |
1499 | ret = hclge_vport_setup(vport, tqp_per_vport); | |
1500 | if (ret) { | |
1501 | dev_err(&pdev->dev, | |
1502 | "vport setup failed for vport %d, %d\n", | |
1503 | i, ret); | |
1504 | return ret; | |
1505 | } | |
1506 | ||
1507 | vport++; | |
1508 | } | |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
acf61ecd YL |
1513 | static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, |
1514 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1515 | { |
1516 | /* TX buffer size is unit by 128 byte */ | |
1517 | #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 | |
1518 | #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) | |
d44f9b63 | 1519 | struct hclge_tx_buff_alloc_cmd *req; |
46a3df9f S |
1520 | struct hclge_desc desc; |
1521 | int ret; | |
1522 | u8 i; | |
1523 | ||
d44f9b63 | 1524 | req = (struct hclge_tx_buff_alloc_cmd *)desc.data; |
46a3df9f S |
1525 | |
1526 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); | |
9ffe79a9 | 1527 | for (i = 0; i < HCLGE_TC_NUM; i++) { |
acf61ecd | 1528 | u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; |
9ffe79a9 | 1529 | |
46a3df9f S |
1530 | req->tx_pkt_buff[i] = |
1531 | cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | | |
1532 | HCLGE_BUF_SIZE_UPDATE_EN_MSK); | |
9ffe79a9 | 1533 | } |
46a3df9f S |
1534 | |
1535 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
1536 | if (ret) { | |
1537 | dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", | |
1538 | ret); | |
1539 | return ret; | |
1540 | } | |
1541 | ||
1542 | return 0; | |
1543 | } | |
1544 | ||
acf61ecd YL |
1545 | static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, |
1546 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1547 | { |
acf61ecd | 1548 | int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); |
46a3df9f S |
1549 | |
1550 | if (ret) { | |
1551 | dev_err(&hdev->pdev->dev, | |
1552 | "tx buffer alloc failed %d\n", ret); | |
1553 | return ret; | |
1554 | } | |
1555 | ||
1556 | return 0; | |
1557 | } | |
1558 | ||
1559 | static int hclge_get_tc_num(struct hclge_dev *hdev) | |
1560 | { | |
1561 | int i, cnt = 0; | |
1562 | ||
1563 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) | |
1564 | if (hdev->hw_tc_map & BIT(i)) | |
1565 | cnt++; | |
1566 | return cnt; | |
1567 | } | |
1568 | ||
1569 | static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev) | |
1570 | { | |
1571 | int i, cnt = 0; | |
1572 | ||
1573 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) | |
1574 | if (hdev->hw_tc_map & BIT(i) && | |
1575 | hdev->tm_info.hw_pfc_map & BIT(i)) | |
1576 | cnt++; | |
1577 | return cnt; | |
1578 | } | |
1579 | ||
1580 | /* Get the number of pfc enabled TCs, which have private buffer */ | |
acf61ecd YL |
1581 | static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, |
1582 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1583 | { |
1584 | struct hclge_priv_buf *priv; | |
1585 | int i, cnt = 0; | |
1586 | ||
1587 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1588 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1589 | if ((hdev->tm_info.hw_pfc_map & BIT(i)) && |
1590 | priv->enable) | |
1591 | cnt++; | |
1592 | } | |
1593 | ||
1594 | return cnt; | |
1595 | } | |
1596 | ||
1597 | /* Get the number of pfc disabled TCs, which have private buffer */ | |
acf61ecd YL |
1598 | static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, |
1599 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1600 | { |
1601 | struct hclge_priv_buf *priv; | |
1602 | int i, cnt = 0; | |
1603 | ||
1604 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1605 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1606 | if (hdev->hw_tc_map & BIT(i) && |
1607 | !(hdev->tm_info.hw_pfc_map & BIT(i)) && | |
1608 | priv->enable) | |
1609 | cnt++; | |
1610 | } | |
1611 | ||
1612 | return cnt; | |
1613 | } | |
1614 | ||
acf61ecd | 1615 | static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) |
46a3df9f S |
1616 | { |
1617 | struct hclge_priv_buf *priv; | |
1618 | u32 rx_priv = 0; | |
1619 | int i; | |
1620 | ||
1621 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1622 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1623 | if (priv->enable) |
1624 | rx_priv += priv->buf_size; | |
1625 | } | |
1626 | return rx_priv; | |
1627 | } | |
1628 | ||
acf61ecd | 1629 | static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) |
9ffe79a9 YL |
1630 | { |
1631 | u32 i, total_tx_size = 0; | |
1632 | ||
1633 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) | |
acf61ecd | 1634 | total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; |
9ffe79a9 YL |
1635 | |
1636 | return total_tx_size; | |
1637 | } | |
1638 | ||
acf61ecd YL |
1639 | static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, |
1640 | struct hclge_pkt_buf_alloc *buf_alloc, | |
1641 | u32 rx_all) | |
46a3df9f S |
1642 | { |
1643 | u32 shared_buf_min, shared_buf_tc, shared_std; | |
1644 | int tc_num, pfc_enable_num; | |
1645 | u32 shared_buf; | |
1646 | u32 rx_priv; | |
1647 | int i; | |
1648 | ||
1649 | tc_num = hclge_get_tc_num(hdev); | |
1650 | pfc_enable_num = hclge_get_pfc_enalbe_num(hdev); | |
1651 | ||
d221df4e YL |
1652 | if (hnae3_dev_dcb_supported(hdev)) |
1653 | shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV; | |
1654 | else | |
1655 | shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV; | |
1656 | ||
46a3df9f S |
1657 | shared_buf_tc = pfc_enable_num * hdev->mps + |
1658 | (tc_num - pfc_enable_num) * hdev->mps / 2 + | |
1659 | hdev->mps; | |
1660 | shared_std = max_t(u32, shared_buf_min, shared_buf_tc); | |
1661 | ||
acf61ecd | 1662 | rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); |
46a3df9f S |
1663 | if (rx_all <= rx_priv + shared_std) |
1664 | return false; | |
1665 | ||
1666 | shared_buf = rx_all - rx_priv; | |
acf61ecd YL |
1667 | buf_alloc->s_buf.buf_size = shared_buf; |
1668 | buf_alloc->s_buf.self.high = shared_buf; | |
1669 | buf_alloc->s_buf.self.low = 2 * hdev->mps; | |
46a3df9f S |
1670 | |
1671 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
1672 | if ((hdev->hw_tc_map & BIT(i)) && | |
1673 | (hdev->tm_info.hw_pfc_map & BIT(i))) { | |
acf61ecd YL |
1674 | buf_alloc->s_buf.tc_thrd[i].low = hdev->mps; |
1675 | buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps; | |
46a3df9f | 1676 | } else { |
acf61ecd YL |
1677 | buf_alloc->s_buf.tc_thrd[i].low = 0; |
1678 | buf_alloc->s_buf.tc_thrd[i].high = hdev->mps; | |
46a3df9f S |
1679 | } |
1680 | } | |
1681 | ||
1682 | return true; | |
1683 | } | |
1684 | ||
acf61ecd YL |
1685 | static int hclge_tx_buffer_calc(struct hclge_dev *hdev, |
1686 | struct hclge_pkt_buf_alloc *buf_alloc) | |
9ffe79a9 YL |
1687 | { |
1688 | u32 i, total_size; | |
1689 | ||
1690 | total_size = hdev->pkt_buf_size; | |
1691 | ||
1692 | /* alloc tx buffer for all enabled tc */ | |
1693 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1694 | struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; |
9ffe79a9 YL |
1695 | |
1696 | if (total_size < HCLGE_DEFAULT_TX_BUF) | |
1697 | return -ENOMEM; | |
1698 | ||
1699 | if (hdev->hw_tc_map & BIT(i)) | |
1700 | priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF; | |
1701 | else | |
1702 | priv->tx_buf_size = 0; | |
1703 | ||
1704 | total_size -= priv->tx_buf_size; | |
1705 | } | |
1706 | ||
1707 | return 0; | |
1708 | } | |
1709 | ||
46a3df9f S |
1710 | /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs |
1711 | * @hdev: pointer to struct hclge_dev | |
acf61ecd | 1712 | * @buf_alloc: pointer to buffer calculation data |
46a3df9f S |
1713 | * @return: 0: calculate sucessful, negative: fail |
1714 | */ | |
1db9b1bf YL |
1715 | static int hclge_rx_buffer_calc(struct hclge_dev *hdev, |
1716 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1717 | { |
9ffe79a9 | 1718 | u32 rx_all = hdev->pkt_buf_size; |
46a3df9f S |
1719 | int no_pfc_priv_num, pfc_priv_num; |
1720 | struct hclge_priv_buf *priv; | |
1721 | int i; | |
1722 | ||
acf61ecd | 1723 | rx_all -= hclge_get_tx_buff_alloced(buf_alloc); |
9ffe79a9 | 1724 | |
d602a525 YL |
1725 | /* When DCB is not supported, rx private |
1726 | * buffer is not allocated. | |
1727 | */ | |
1728 | if (!hnae3_dev_dcb_supported(hdev)) { | |
acf61ecd | 1729 | if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
d602a525 YL |
1730 | return -ENOMEM; |
1731 | ||
1732 | return 0; | |
1733 | } | |
1734 | ||
46a3df9f S |
1735 | /* step 1, try to alloc private buffer for all enabled tc */ |
1736 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1737 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1738 | if (hdev->hw_tc_map & BIT(i)) { |
1739 | priv->enable = 1; | |
1740 | if (hdev->tm_info.hw_pfc_map & BIT(i)) { | |
1741 | priv->wl.low = hdev->mps; | |
1742 | priv->wl.high = priv->wl.low + hdev->mps; | |
1743 | priv->buf_size = priv->wl.high + | |
1744 | HCLGE_DEFAULT_DV; | |
1745 | } else { | |
1746 | priv->wl.low = 0; | |
1747 | priv->wl.high = 2 * hdev->mps; | |
1748 | priv->buf_size = priv->wl.high; | |
1749 | } | |
bb1fe9ea YL |
1750 | } else { |
1751 | priv->enable = 0; | |
1752 | priv->wl.low = 0; | |
1753 | priv->wl.high = 0; | |
1754 | priv->buf_size = 0; | |
46a3df9f S |
1755 | } |
1756 | } | |
1757 | ||
acf61ecd | 1758 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1759 | return 0; |
1760 | ||
1761 | /* step 2, try to decrease the buffer size of | |
1762 | * no pfc TC's private buffer | |
1763 | */ | |
1764 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1765 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f | 1766 | |
bb1fe9ea YL |
1767 | priv->enable = 0; |
1768 | priv->wl.low = 0; | |
1769 | priv->wl.high = 0; | |
1770 | priv->buf_size = 0; | |
1771 | ||
1772 | if (!(hdev->hw_tc_map & BIT(i))) | |
1773 | continue; | |
1774 | ||
1775 | priv->enable = 1; | |
46a3df9f S |
1776 | |
1777 | if (hdev->tm_info.hw_pfc_map & BIT(i)) { | |
1778 | priv->wl.low = 128; | |
1779 | priv->wl.high = priv->wl.low + hdev->mps; | |
1780 | priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV; | |
1781 | } else { | |
1782 | priv->wl.low = 0; | |
1783 | priv->wl.high = hdev->mps; | |
1784 | priv->buf_size = priv->wl.high; | |
1785 | } | |
1786 | } | |
1787 | ||
acf61ecd | 1788 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1789 | return 0; |
1790 | ||
1791 | /* step 3, try to reduce the number of pfc disabled TCs, | |
1792 | * which have private buffer | |
1793 | */ | |
1794 | /* get the total no pfc enable TC number, which have private buffer */ | |
acf61ecd | 1795 | no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); |
46a3df9f S |
1796 | |
1797 | /* let the last to be cleared first */ | |
1798 | for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { | |
acf61ecd | 1799 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1800 | |
1801 | if (hdev->hw_tc_map & BIT(i) && | |
1802 | !(hdev->tm_info.hw_pfc_map & BIT(i))) { | |
1803 | /* Clear the no pfc TC private buffer */ | |
1804 | priv->wl.low = 0; | |
1805 | priv->wl.high = 0; | |
1806 | priv->buf_size = 0; | |
1807 | priv->enable = 0; | |
1808 | no_pfc_priv_num--; | |
1809 | } | |
1810 | ||
acf61ecd | 1811 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || |
46a3df9f S |
1812 | no_pfc_priv_num == 0) |
1813 | break; | |
1814 | } | |
1815 | ||
acf61ecd | 1816 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1817 | return 0; |
1818 | ||
1819 | /* step 4, try to reduce the number of pfc enabled TCs | |
1820 | * which have private buffer. | |
1821 | */ | |
acf61ecd | 1822 | pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); |
46a3df9f S |
1823 | |
1824 | /* let the last to be cleared first */ | |
1825 | for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { | |
acf61ecd | 1826 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1827 | |
1828 | if (hdev->hw_tc_map & BIT(i) && | |
1829 | hdev->tm_info.hw_pfc_map & BIT(i)) { | |
1830 | /* Reduce the number of pfc TC with private buffer */ | |
1831 | priv->wl.low = 0; | |
1832 | priv->enable = 0; | |
1833 | priv->wl.high = 0; | |
1834 | priv->buf_size = 0; | |
1835 | pfc_priv_num--; | |
1836 | } | |
1837 | ||
acf61ecd | 1838 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || |
46a3df9f S |
1839 | pfc_priv_num == 0) |
1840 | break; | |
1841 | } | |
acf61ecd | 1842 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1843 | return 0; |
1844 | ||
1845 | return -ENOMEM; | |
1846 | } | |
1847 | ||
acf61ecd YL |
1848 | static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, |
1849 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1850 | { |
d44f9b63 | 1851 | struct hclge_rx_priv_buff_cmd *req; |
46a3df9f S |
1852 | struct hclge_desc desc; |
1853 | int ret; | |
1854 | int i; | |
1855 | ||
1856 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); | |
d44f9b63 | 1857 | req = (struct hclge_rx_priv_buff_cmd *)desc.data; |
46a3df9f S |
1858 | |
1859 | /* Alloc private buffer TCs */ | |
1860 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1861 | struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1862 | |
1863 | req->buf_num[i] = | |
1864 | cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); | |
1865 | req->buf_num[i] |= | |
5bca3b94 | 1866 | cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); |
46a3df9f S |
1867 | } |
1868 | ||
b8c8bf47 | 1869 | req->shared_buf = |
acf61ecd | 1870 | cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | |
b8c8bf47 YL |
1871 | (1 << HCLGE_TC0_PRI_BUF_EN_B)); |
1872 | ||
46a3df9f S |
1873 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
1874 | if (ret) { | |
1875 | dev_err(&hdev->pdev->dev, | |
1876 | "rx private buffer alloc cmd failed %d\n", ret); | |
1877 | return ret; | |
1878 | } | |
1879 | ||
1880 | return 0; | |
1881 | } | |
1882 | ||
1883 | #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0) | |
1884 | ||
acf61ecd YL |
1885 | static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, |
1886 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1887 | { |
1888 | struct hclge_rx_priv_wl_buf *req; | |
1889 | struct hclge_priv_buf *priv; | |
1890 | struct hclge_desc desc[2]; | |
1891 | int i, j; | |
1892 | int ret; | |
1893 | ||
1894 | for (i = 0; i < 2; i++) { | |
1895 | hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, | |
1896 | false); | |
1897 | req = (struct hclge_rx_priv_wl_buf *)desc[i].data; | |
1898 | ||
1899 | /* The first descriptor set the NEXT bit to 1 */ | |
1900 | if (i == 0) | |
1901 | desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1902 | else | |
1903 | desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1904 | ||
1905 | for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { | |
acf61ecd YL |
1906 | u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; |
1907 | ||
1908 | priv = &buf_alloc->priv_buf[idx]; | |
46a3df9f S |
1909 | req->tc_wl[j].high = |
1910 | cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); | |
1911 | req->tc_wl[j].high |= | |
1912 | cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) << | |
1913 | HCLGE_RX_PRIV_EN_B); | |
1914 | req->tc_wl[j].low = | |
1915 | cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); | |
1916 | req->tc_wl[j].low |= | |
1917 | cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) << | |
1918 | HCLGE_RX_PRIV_EN_B); | |
1919 | } | |
1920 | } | |
1921 | ||
1922 | /* Send 2 descriptor at one time */ | |
1923 | ret = hclge_cmd_send(&hdev->hw, desc, 2); | |
1924 | if (ret) { | |
1925 | dev_err(&hdev->pdev->dev, | |
1926 | "rx private waterline config cmd failed %d\n", | |
1927 | ret); | |
1928 | return ret; | |
1929 | } | |
1930 | return 0; | |
1931 | } | |
1932 | ||
acf61ecd YL |
1933 | static int hclge_common_thrd_config(struct hclge_dev *hdev, |
1934 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1935 | { |
acf61ecd | 1936 | struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; |
46a3df9f S |
1937 | struct hclge_rx_com_thrd *req; |
1938 | struct hclge_desc desc[2]; | |
1939 | struct hclge_tc_thrd *tc; | |
1940 | int i, j; | |
1941 | int ret; | |
1942 | ||
1943 | for (i = 0; i < 2; i++) { | |
1944 | hclge_cmd_setup_basic_desc(&desc[i], | |
1945 | HCLGE_OPC_RX_COM_THRD_ALLOC, false); | |
1946 | req = (struct hclge_rx_com_thrd *)&desc[i].data; | |
1947 | ||
1948 | /* The first descriptor set the NEXT bit to 1 */ | |
1949 | if (i == 0) | |
1950 | desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1951 | else | |
1952 | desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1953 | ||
1954 | for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { | |
1955 | tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; | |
1956 | ||
1957 | req->com_thrd[j].high = | |
1958 | cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); | |
1959 | req->com_thrd[j].high |= | |
1960 | cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) << | |
1961 | HCLGE_RX_PRIV_EN_B); | |
1962 | req->com_thrd[j].low = | |
1963 | cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); | |
1964 | req->com_thrd[j].low |= | |
1965 | cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) << | |
1966 | HCLGE_RX_PRIV_EN_B); | |
1967 | } | |
1968 | } | |
1969 | ||
1970 | /* Send 2 descriptors at one time */ | |
1971 | ret = hclge_cmd_send(&hdev->hw, desc, 2); | |
1972 | if (ret) { | |
1973 | dev_err(&hdev->pdev->dev, | |
1974 | "common threshold config cmd failed %d\n", ret); | |
1975 | return ret; | |
1976 | } | |
1977 | return 0; | |
1978 | } | |
1979 | ||
acf61ecd YL |
1980 | static int hclge_common_wl_config(struct hclge_dev *hdev, |
1981 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1982 | { |
acf61ecd | 1983 | struct hclge_shared_buf *buf = &buf_alloc->s_buf; |
46a3df9f S |
1984 | struct hclge_rx_com_wl *req; |
1985 | struct hclge_desc desc; | |
1986 | int ret; | |
1987 | ||
1988 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); | |
1989 | ||
1990 | req = (struct hclge_rx_com_wl *)desc.data; | |
1991 | req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); | |
1992 | req->com_wl.high |= | |
1993 | cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) << | |
1994 | HCLGE_RX_PRIV_EN_B); | |
1995 | ||
1996 | req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); | |
1997 | req->com_wl.low |= | |
1998 | cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) << | |
1999 | HCLGE_RX_PRIV_EN_B); | |
2000 | ||
2001 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2002 | if (ret) { | |
2003 | dev_err(&hdev->pdev->dev, | |
2004 | "common waterline config cmd failed %d\n", ret); | |
2005 | return ret; | |
2006 | } | |
2007 | ||
2008 | return 0; | |
2009 | } | |
2010 | ||
2011 | int hclge_buffer_alloc(struct hclge_dev *hdev) | |
2012 | { | |
acf61ecd | 2013 | struct hclge_pkt_buf_alloc *pkt_buf; |
46a3df9f S |
2014 | int ret; |
2015 | ||
acf61ecd YL |
2016 | pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); |
2017 | if (!pkt_buf) | |
46a3df9f S |
2018 | return -ENOMEM; |
2019 | ||
acf61ecd | 2020 | ret = hclge_tx_buffer_calc(hdev, pkt_buf); |
9ffe79a9 YL |
2021 | if (ret) { |
2022 | dev_err(&hdev->pdev->dev, | |
2023 | "could not calc tx buffer size for all TCs %d\n", ret); | |
acf61ecd | 2024 | goto out; |
9ffe79a9 YL |
2025 | } |
2026 | ||
acf61ecd | 2027 | ret = hclge_tx_buffer_alloc(hdev, pkt_buf); |
46a3df9f S |
2028 | if (ret) { |
2029 | dev_err(&hdev->pdev->dev, | |
2030 | "could not alloc tx buffers %d\n", ret); | |
acf61ecd | 2031 | goto out; |
46a3df9f S |
2032 | } |
2033 | ||
acf61ecd | 2034 | ret = hclge_rx_buffer_calc(hdev, pkt_buf); |
46a3df9f S |
2035 | if (ret) { |
2036 | dev_err(&hdev->pdev->dev, | |
2037 | "could not calc rx priv buffer size for all TCs %d\n", | |
2038 | ret); | |
acf61ecd | 2039 | goto out; |
46a3df9f S |
2040 | } |
2041 | ||
acf61ecd | 2042 | ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); |
46a3df9f S |
2043 | if (ret) { |
2044 | dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", | |
2045 | ret); | |
acf61ecd | 2046 | goto out; |
46a3df9f S |
2047 | } |
2048 | ||
2daf4a65 | 2049 | if (hnae3_dev_dcb_supported(hdev)) { |
acf61ecd | 2050 | ret = hclge_rx_priv_wl_config(hdev, pkt_buf); |
2daf4a65 YL |
2051 | if (ret) { |
2052 | dev_err(&hdev->pdev->dev, | |
2053 | "could not configure rx private waterline %d\n", | |
2054 | ret); | |
acf61ecd | 2055 | goto out; |
2daf4a65 | 2056 | } |
46a3df9f | 2057 | |
acf61ecd | 2058 | ret = hclge_common_thrd_config(hdev, pkt_buf); |
2daf4a65 YL |
2059 | if (ret) { |
2060 | dev_err(&hdev->pdev->dev, | |
2061 | "could not configure common threshold %d\n", | |
2062 | ret); | |
acf61ecd | 2063 | goto out; |
2daf4a65 | 2064 | } |
46a3df9f S |
2065 | } |
2066 | ||
acf61ecd YL |
2067 | ret = hclge_common_wl_config(hdev, pkt_buf); |
2068 | if (ret) | |
46a3df9f S |
2069 | dev_err(&hdev->pdev->dev, |
2070 | "could not configure common waterline %d\n", ret); | |
46a3df9f | 2071 | |
acf61ecd YL |
2072 | out: |
2073 | kfree(pkt_buf); | |
2074 | return ret; | |
46a3df9f S |
2075 | } |
2076 | ||
2077 | static int hclge_init_roce_base_info(struct hclge_vport *vport) | |
2078 | { | |
2079 | struct hnae3_handle *roce = &vport->roce; | |
2080 | struct hnae3_handle *nic = &vport->nic; | |
2081 | ||
887c3820 | 2082 | roce->rinfo.num_vectors = vport->back->num_roce_msi; |
46a3df9f S |
2083 | |
2084 | if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors || | |
2085 | vport->back->num_msi_left == 0) | |
2086 | return -EINVAL; | |
2087 | ||
2088 | roce->rinfo.base_vector = vport->back->roce_base_vector; | |
2089 | ||
2090 | roce->rinfo.netdev = nic->kinfo.netdev; | |
2091 | roce->rinfo.roce_io_base = vport->back->hw.io_base; | |
2092 | ||
2093 | roce->pdev = nic->pdev; | |
2094 | roce->ae_algo = nic->ae_algo; | |
2095 | roce->numa_node_mask = nic->numa_node_mask; | |
2096 | ||
2097 | return 0; | |
2098 | } | |
2099 | ||
887c3820 | 2100 | static int hclge_init_msi(struct hclge_dev *hdev) |
46a3df9f S |
2101 | { |
2102 | struct pci_dev *pdev = hdev->pdev; | |
887c3820 SM |
2103 | int vectors; |
2104 | int i; | |
46a3df9f | 2105 | |
887c3820 SM |
2106 | vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, |
2107 | PCI_IRQ_MSI | PCI_IRQ_MSIX); | |
2108 | if (vectors < 0) { | |
2109 | dev_err(&pdev->dev, | |
2110 | "failed(%d) to allocate MSI/MSI-X vectors\n", | |
2111 | vectors); | |
2112 | return vectors; | |
46a3df9f | 2113 | } |
887c3820 SM |
2114 | if (vectors < hdev->num_msi) |
2115 | dev_warn(&hdev->pdev->dev, | |
2116 | "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", | |
2117 | hdev->num_msi, vectors); | |
46a3df9f | 2118 | |
887c3820 SM |
2119 | hdev->num_msi = vectors; |
2120 | hdev->num_msi_left = vectors; | |
2121 | hdev->base_msi_vector = pdev->irq; | |
46a3df9f S |
2122 | hdev->roce_base_vector = hdev->base_msi_vector + |
2123 | HCLGE_ROCE_VECTOR_OFFSET; | |
2124 | ||
46a3df9f S |
2125 | hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, |
2126 | sizeof(u16), GFP_KERNEL); | |
887c3820 SM |
2127 | if (!hdev->vector_status) { |
2128 | pci_free_irq_vectors(pdev); | |
46a3df9f | 2129 | return -ENOMEM; |
887c3820 | 2130 | } |
46a3df9f S |
2131 | |
2132 | for (i = 0; i < hdev->num_msi; i++) | |
2133 | hdev->vector_status[i] = HCLGE_INVALID_VPORT; | |
2134 | ||
887c3820 SM |
2135 | hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, |
2136 | sizeof(int), GFP_KERNEL); | |
2137 | if (!hdev->vector_irq) { | |
2138 | pci_free_irq_vectors(pdev); | |
2139 | return -ENOMEM; | |
46a3df9f | 2140 | } |
46a3df9f S |
2141 | |
2142 | return 0; | |
2143 | } | |
2144 | ||
2145 | static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed) | |
2146 | { | |
2147 | struct hclge_mac *mac = &hdev->hw.mac; | |
2148 | ||
2149 | if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M)) | |
2150 | mac->duplex = (u8)duplex; | |
2151 | else | |
2152 | mac->duplex = HCLGE_MAC_FULL; | |
2153 | ||
2154 | mac->speed = speed; | |
2155 | } | |
2156 | ||
2157 | int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) | |
2158 | { | |
d44f9b63 | 2159 | struct hclge_config_mac_speed_dup_cmd *req; |
46a3df9f S |
2160 | struct hclge_desc desc; |
2161 | int ret; | |
2162 | ||
d44f9b63 | 2163 | req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; |
46a3df9f S |
2164 | |
2165 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); | |
2166 | ||
2167 | hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex); | |
2168 | ||
2169 | switch (speed) { | |
2170 | case HCLGE_MAC_SPEED_10M: | |
2171 | hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, | |
2172 | HCLGE_CFG_SPEED_S, 6); | |
2173 | break; | |
2174 | case HCLGE_MAC_SPEED_100M: | |
2175 | hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, | |
2176 | HCLGE_CFG_SPEED_S, 7); | |
2177 | break; | |
2178 | case HCLGE_MAC_SPEED_1G: | |
2179 | hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, | |
2180 | HCLGE_CFG_SPEED_S, 0); | |
2181 | break; | |
2182 | case HCLGE_MAC_SPEED_10G: | |
2183 | hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, | |
2184 | HCLGE_CFG_SPEED_S, 1); | |
2185 | break; | |
2186 | case HCLGE_MAC_SPEED_25G: | |
2187 | hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, | |
2188 | HCLGE_CFG_SPEED_S, 2); | |
2189 | break; | |
2190 | case HCLGE_MAC_SPEED_40G: | |
2191 | hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, | |
2192 | HCLGE_CFG_SPEED_S, 3); | |
2193 | break; | |
2194 | case HCLGE_MAC_SPEED_50G: | |
2195 | hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, | |
2196 | HCLGE_CFG_SPEED_S, 4); | |
2197 | break; | |
2198 | case HCLGE_MAC_SPEED_100G: | |
2199 | hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, | |
2200 | HCLGE_CFG_SPEED_S, 5); | |
2201 | break; | |
2202 | default: | |
d7629e74 | 2203 | dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); |
46a3df9f S |
2204 | return -EINVAL; |
2205 | } | |
2206 | ||
2207 | hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, | |
2208 | 1); | |
2209 | ||
2210 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2211 | if (ret) { | |
2212 | dev_err(&hdev->pdev->dev, | |
2213 | "mac speed/duplex config cmd failed %d.\n", ret); | |
2214 | return ret; | |
2215 | } | |
2216 | ||
2217 | hclge_check_speed_dup(hdev, duplex, speed); | |
2218 | ||
2219 | return 0; | |
2220 | } | |
2221 | ||
2222 | static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, | |
2223 | u8 duplex) | |
2224 | { | |
2225 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2226 | struct hclge_dev *hdev = vport->back; | |
2227 | ||
2228 | return hclge_cfg_mac_speed_dup(hdev, speed, duplex); | |
2229 | } | |
2230 | ||
2231 | static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed, | |
2232 | u8 *duplex) | |
2233 | { | |
d44f9b63 | 2234 | struct hclge_query_an_speed_dup_cmd *req; |
46a3df9f S |
2235 | struct hclge_desc desc; |
2236 | int speed_tmp; | |
2237 | int ret; | |
2238 | ||
d44f9b63 | 2239 | req = (struct hclge_query_an_speed_dup_cmd *)desc.data; |
46a3df9f S |
2240 | |
2241 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true); | |
2242 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2243 | if (ret) { | |
2244 | dev_err(&hdev->pdev->dev, | |
2245 | "mac speed/autoneg/duplex query cmd failed %d\n", | |
2246 | ret); | |
2247 | return ret; | |
2248 | } | |
2249 | ||
2250 | *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B); | |
2251 | speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M, | |
2252 | HCLGE_QUERY_SPEED_S); | |
2253 | ||
2254 | ret = hclge_parse_speed(speed_tmp, speed); | |
2255 | if (ret) { | |
2256 | dev_err(&hdev->pdev->dev, | |
2257 | "could not parse speed(=%d), %d\n", speed_tmp, ret); | |
2258 | return -EIO; | |
2259 | } | |
2260 | ||
2261 | return 0; | |
2262 | } | |
2263 | ||
46a3df9f S |
2264 | static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) |
2265 | { | |
d44f9b63 | 2266 | struct hclge_config_auto_neg_cmd *req; |
46a3df9f | 2267 | struct hclge_desc desc; |
a90bb9a5 | 2268 | u32 flag = 0; |
46a3df9f S |
2269 | int ret; |
2270 | ||
2271 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); | |
2272 | ||
d44f9b63 | 2273 | req = (struct hclge_config_auto_neg_cmd *)desc.data; |
a90bb9a5 YL |
2274 | hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable); |
2275 | req->cfg_an_cmd_flag = cpu_to_le32(flag); | |
46a3df9f S |
2276 | |
2277 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2278 | if (ret) { | |
2279 | dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", | |
2280 | ret); | |
2281 | return ret; | |
2282 | } | |
2283 | ||
2284 | return 0; | |
2285 | } | |
2286 | ||
2287 | static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) | |
2288 | { | |
2289 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2290 | struct hclge_dev *hdev = vport->back; | |
2291 | ||
2292 | return hclge_set_autoneg_en(hdev, enable); | |
2293 | } | |
2294 | ||
2295 | static int hclge_get_autoneg(struct hnae3_handle *handle) | |
2296 | { | |
2297 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2298 | struct hclge_dev *hdev = vport->back; | |
9ff804ee FL |
2299 | struct phy_device *phydev = hdev->hw.mac.phydev; |
2300 | ||
2301 | if (phydev) | |
2302 | return phydev->autoneg; | |
46a3df9f S |
2303 | |
2304 | return hdev->hw.mac.autoneg; | |
2305 | } | |
2306 | ||
6f712727 PL |
2307 | static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev, |
2308 | bool mask_vlan, | |
2309 | u8 *mac_mask) | |
2310 | { | |
2311 | struct hclge_mac_vlan_mask_entry_cmd *req; | |
2312 | struct hclge_desc desc; | |
2313 | int status; | |
2314 | ||
2315 | req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data; | |
2316 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false); | |
2317 | ||
2318 | hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B, | |
2319 | mask_vlan ? 1 : 0); | |
2320 | ether_addr_copy(req->mac_mask, mac_mask); | |
2321 | ||
2322 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2323 | if (status) | |
2324 | dev_err(&hdev->pdev->dev, | |
2325 | "Config mac_vlan_mask failed for cmd_send, ret =%d\n", | |
2326 | status); | |
2327 | ||
2328 | return status; | |
2329 | } | |
2330 | ||
46a3df9f S |
2331 | static int hclge_mac_init(struct hclge_dev *hdev) |
2332 | { | |
59bc85ec FL |
2333 | struct hnae3_handle *handle = &hdev->vport[0].nic; |
2334 | struct net_device *netdev = handle->kinfo.netdev; | |
46a3df9f | 2335 | struct hclge_mac *mac = &hdev->hw.mac; |
6f712727 | 2336 | u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; |
59bc85ec | 2337 | int mtu; |
46a3df9f S |
2338 | int ret; |
2339 | ||
2340 | ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL); | |
2341 | if (ret) { | |
2342 | dev_err(&hdev->pdev->dev, | |
2343 | "Config mac speed dup fail ret=%d\n", ret); | |
2344 | return ret; | |
2345 | } | |
2346 | ||
2347 | mac->link = 0; | |
2348 | ||
46a3df9f S |
2349 | /* Initialize the MTA table work mode */ |
2350 | hdev->accept_mta_mc = true; | |
2351 | hdev->enable_mta = true; | |
2352 | hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36; | |
2353 | ||
2354 | ret = hclge_set_mta_filter_mode(hdev, | |
2355 | hdev->mta_mac_sel_type, | |
2356 | hdev->enable_mta); | |
2357 | if (ret) { | |
2358 | dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n", | |
2359 | ret); | |
2360 | return ret; | |
2361 | } | |
2362 | ||
6f712727 PL |
2363 | ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc); |
2364 | if (ret) { | |
2365 | dev_err(&hdev->pdev->dev, | |
2366 | "set mta filter mode fail ret=%d\n", ret); | |
2367 | return ret; | |
2368 | } | |
2369 | ||
2370 | ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask); | |
59bc85ec | 2371 | if (ret) { |
6f712727 PL |
2372 | dev_err(&hdev->pdev->dev, |
2373 | "set default mac_vlan_mask fail ret=%d\n", ret); | |
59bc85ec FL |
2374 | return ret; |
2375 | } | |
6f712727 | 2376 | |
59bc85ec FL |
2377 | if (netdev) |
2378 | mtu = netdev->mtu; | |
2379 | else | |
2380 | mtu = ETH_DATA_LEN; | |
2381 | ||
2382 | ret = hclge_set_mtu(handle, mtu); | |
2383 | if (ret) { | |
2384 | dev_err(&hdev->pdev->dev, | |
2385 | "set mtu failed ret=%d\n", ret); | |
2386 | return ret; | |
2387 | } | |
2388 | ||
2389 | return 0; | |
46a3df9f S |
2390 | } |
2391 | ||
22fd3468 SM |
2392 | static void hclge_mbx_task_schedule(struct hclge_dev *hdev) |
2393 | { | |
2394 | if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) | |
2395 | schedule_work(&hdev->mbx_service_task); | |
2396 | } | |
2397 | ||
ed4a1bb8 SM |
2398 | static void hclge_reset_task_schedule(struct hclge_dev *hdev) |
2399 | { | |
2400 | if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) | |
2401 | schedule_work(&hdev->rst_service_task); | |
2402 | } | |
2403 | ||
46a3df9f S |
2404 | static void hclge_task_schedule(struct hclge_dev *hdev) |
2405 | { | |
2406 | if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) && | |
2407 | !test_bit(HCLGE_STATE_REMOVING, &hdev->state) && | |
2408 | !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)) | |
2409 | (void)schedule_work(&hdev->service_task); | |
2410 | } | |
2411 | ||
2412 | static int hclge_get_mac_link_status(struct hclge_dev *hdev) | |
2413 | { | |
d44f9b63 | 2414 | struct hclge_link_status_cmd *req; |
46a3df9f S |
2415 | struct hclge_desc desc; |
2416 | int link_status; | |
2417 | int ret; | |
2418 | ||
2419 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); | |
2420 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2421 | if (ret) { | |
2422 | dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", | |
2423 | ret); | |
2424 | return ret; | |
2425 | } | |
2426 | ||
d44f9b63 | 2427 | req = (struct hclge_link_status_cmd *)desc.data; |
46a3df9f S |
2428 | link_status = req->status & HCLGE_LINK_STATUS; |
2429 | ||
2430 | return !!link_status; | |
2431 | } | |
2432 | ||
2433 | static int hclge_get_mac_phy_link(struct hclge_dev *hdev) | |
2434 | { | |
2435 | int mac_state; | |
2436 | int link_stat; | |
2437 | ||
2438 | mac_state = hclge_get_mac_link_status(hdev); | |
2439 | ||
2440 | if (hdev->hw.mac.phydev) { | |
2441 | if (!genphy_read_status(hdev->hw.mac.phydev)) | |
2442 | link_stat = mac_state & | |
2443 | hdev->hw.mac.phydev->link; | |
2444 | else | |
2445 | link_stat = 0; | |
2446 | ||
2447 | } else { | |
2448 | link_stat = mac_state; | |
2449 | } | |
2450 | ||
2451 | return !!link_stat; | |
2452 | } | |
2453 | ||
2454 | static void hclge_update_link_status(struct hclge_dev *hdev) | |
2455 | { | |
2456 | struct hnae3_client *client = hdev->nic_client; | |
2457 | struct hnae3_handle *handle; | |
2458 | int state; | |
2459 | int i; | |
2460 | ||
2461 | if (!client) | |
2462 | return; | |
2463 | state = hclge_get_mac_phy_link(hdev); | |
2464 | if (state != hdev->hw.mac.link) { | |
2465 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
2466 | handle = &hdev->vport[i].nic; | |
2467 | client->ops->link_status_change(handle, state); | |
2468 | } | |
2469 | hdev->hw.mac.link = state; | |
2470 | } | |
2471 | } | |
2472 | ||
2473 | static int hclge_update_speed_duplex(struct hclge_dev *hdev) | |
2474 | { | |
2475 | struct hclge_mac mac = hdev->hw.mac; | |
2476 | u8 duplex; | |
2477 | int speed; | |
2478 | int ret; | |
2479 | ||
2480 | /* get the speed and duplex as autoneg'result from mac cmd when phy | |
2481 | * doesn't exit. | |
2482 | */ | |
c040366b | 2483 | if (mac.phydev || !mac.autoneg) |
46a3df9f S |
2484 | return 0; |
2485 | ||
2486 | ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex); | |
2487 | if (ret) { | |
2488 | dev_err(&hdev->pdev->dev, | |
2489 | "mac autoneg/speed/duplex query failed %d\n", ret); | |
2490 | return ret; | |
2491 | } | |
2492 | ||
2493 | if ((mac.speed != speed) || (mac.duplex != duplex)) { | |
2494 | ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); | |
2495 | if (ret) { | |
2496 | dev_err(&hdev->pdev->dev, | |
2497 | "mac speed/duplex config failed %d\n", ret); | |
2498 | return ret; | |
2499 | } | |
2500 | } | |
2501 | ||
2502 | return 0; | |
2503 | } | |
2504 | ||
2505 | static int hclge_update_speed_duplex_h(struct hnae3_handle *handle) | |
2506 | { | |
2507 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2508 | struct hclge_dev *hdev = vport->back; | |
2509 | ||
2510 | return hclge_update_speed_duplex(hdev); | |
2511 | } | |
2512 | ||
2513 | static int hclge_get_status(struct hnae3_handle *handle) | |
2514 | { | |
2515 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2516 | struct hclge_dev *hdev = vport->back; | |
2517 | ||
2518 | hclge_update_link_status(hdev); | |
2519 | ||
2520 | return hdev->hw.mac.link; | |
2521 | } | |
2522 | ||
d039ef68 | 2523 | static void hclge_service_timer(struct timer_list *t) |
46a3df9f | 2524 | { |
d039ef68 | 2525 | struct hclge_dev *hdev = from_timer(hdev, t, service_timer); |
46a3df9f | 2526 | |
d039ef68 | 2527 | mod_timer(&hdev->service_timer, jiffies + HZ); |
7a5d2a39 | 2528 | hdev->hw_stats.stats_timer++; |
46a3df9f S |
2529 | hclge_task_schedule(hdev); |
2530 | } | |
2531 | ||
2532 | static void hclge_service_complete(struct hclge_dev *hdev) | |
2533 | { | |
2534 | WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)); | |
2535 | ||
2536 | /* Flush memory before next watchdog */ | |
2537 | smp_mb__before_atomic(); | |
2538 | clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); | |
2539 | } | |
2540 | ||
202f2014 SM |
2541 | static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) |
2542 | { | |
2543 | u32 rst_src_reg; | |
22fd3468 | 2544 | u32 cmdq_src_reg; |
202f2014 SM |
2545 | |
2546 | /* fetch the events from their corresponding regs */ | |
2547 | rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG); | |
22fd3468 SM |
2548 | cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); |
2549 | ||
2550 | /* Assumption: If by any chance reset and mailbox events are reported | |
2551 | * together then we will only process reset event in this go and will | |
2552 | * defer the processing of the mailbox events. Since, we would have not | |
2553 | * cleared RX CMDQ event this time we would receive again another | |
2554 | * interrupt from H/W just for the mailbox. | |
2555 | */ | |
202f2014 SM |
2556 | |
2557 | /* check for vector0 reset event sources */ | |
2558 | if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { | |
2559 | set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); | |
2560 | *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); | |
2561 | return HCLGE_VECTOR0_EVENT_RST; | |
2562 | } | |
2563 | ||
2564 | if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) { | |
2565 | set_bit(HNAE3_CORE_RESET, &hdev->reset_pending); | |
2566 | *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); | |
2567 | return HCLGE_VECTOR0_EVENT_RST; | |
2568 | } | |
2569 | ||
2570 | if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) { | |
2571 | set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); | |
2572 | *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); | |
2573 | return HCLGE_VECTOR0_EVENT_RST; | |
2574 | } | |
2575 | ||
22fd3468 SM |
2576 | /* check for vector0 mailbox(=CMDQ RX) event source */ |
2577 | if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { | |
2578 | cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); | |
2579 | *clearval = cmdq_src_reg; | |
2580 | return HCLGE_VECTOR0_EVENT_MBX; | |
2581 | } | |
202f2014 SM |
2582 | |
2583 | return HCLGE_VECTOR0_EVENT_OTHER; | |
2584 | } | |
2585 | ||
2586 | static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, | |
2587 | u32 regclr) | |
2588 | { | |
22fd3468 SM |
2589 | switch (event_type) { |
2590 | case HCLGE_VECTOR0_EVENT_RST: | |
202f2014 | 2591 | hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); |
22fd3468 SM |
2592 | break; |
2593 | case HCLGE_VECTOR0_EVENT_MBX: | |
2594 | hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); | |
2595 | break; | |
2596 | } | |
202f2014 SM |
2597 | } |
2598 | ||
466b0c00 L |
2599 | static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) |
2600 | { | |
2601 | writel(enable ? 1 : 0, vector->addr); | |
2602 | } | |
2603 | ||
2604 | static irqreturn_t hclge_misc_irq_handle(int irq, void *data) | |
2605 | { | |
2606 | struct hclge_dev *hdev = data; | |
202f2014 SM |
2607 | u32 event_cause; |
2608 | u32 clearval; | |
466b0c00 L |
2609 | |
2610 | hclge_enable_vector(&hdev->misc_vector, false); | |
202f2014 SM |
2611 | event_cause = hclge_check_event_cause(hdev, &clearval); |
2612 | ||
22fd3468 | 2613 | /* vector 0 interrupt is shared with reset and mailbox source events.*/ |
202f2014 SM |
2614 | switch (event_cause) { |
2615 | case HCLGE_VECTOR0_EVENT_RST: | |
ed4a1bb8 | 2616 | hclge_reset_task_schedule(hdev); |
202f2014 | 2617 | break; |
22fd3468 SM |
2618 | case HCLGE_VECTOR0_EVENT_MBX: |
2619 | /* If we are here then, | |
2620 | * 1. Either we are not handling any mbx task and we are not | |
2621 | * scheduled as well | |
2622 | * OR | |
2623 | * 2. We could be handling a mbx task but nothing more is | |
2624 | * scheduled. | |
2625 | * In both cases, we should schedule mbx task as there are more | |
2626 | * mbx messages reported by this interrupt. | |
2627 | */ | |
2628 | hclge_mbx_task_schedule(hdev); | |
2629 | ||
202f2014 SM |
2630 | default: |
2631 | dev_dbg(&hdev->pdev->dev, | |
2632 | "received unknown or unhandled event of vector0\n"); | |
2633 | break; | |
2634 | } | |
2635 | ||
2636 | /* we should clear the source of interrupt */ | |
2637 | hclge_clear_event_cause(hdev, event_cause, clearval); | |
2638 | hclge_enable_vector(&hdev->misc_vector, true); | |
466b0c00 L |
2639 | |
2640 | return IRQ_HANDLED; | |
2641 | } | |
2642 | ||
2643 | static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) | |
2644 | { | |
2645 | hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; | |
2646 | hdev->num_msi_left += 1; | |
2647 | hdev->num_msi_used -= 1; | |
2648 | } | |
2649 | ||
2650 | static void hclge_get_misc_vector(struct hclge_dev *hdev) | |
2651 | { | |
2652 | struct hclge_misc_vector *vector = &hdev->misc_vector; | |
2653 | ||
2654 | vector->vector_irq = pci_irq_vector(hdev->pdev, 0); | |
2655 | ||
2656 | vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; | |
2657 | hdev->vector_status[0] = 0; | |
2658 | ||
2659 | hdev->num_msi_left -= 1; | |
2660 | hdev->num_msi_used += 1; | |
2661 | } | |
2662 | ||
2663 | static int hclge_misc_irq_init(struct hclge_dev *hdev) | |
2664 | { | |
2665 | int ret; | |
2666 | ||
2667 | hclge_get_misc_vector(hdev); | |
2668 | ||
202f2014 SM |
2669 | /* this would be explicitly freed in the end */ |
2670 | ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, | |
2671 | 0, "hclge_misc", hdev); | |
466b0c00 L |
2672 | if (ret) { |
2673 | hclge_free_vector(hdev, 0); | |
2674 | dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", | |
2675 | hdev->misc_vector.vector_irq); | |
2676 | } | |
2677 | ||
2678 | return ret; | |
2679 | } | |
2680 | ||
202f2014 SM |
2681 | static void hclge_misc_irq_uninit(struct hclge_dev *hdev) |
2682 | { | |
2683 | free_irq(hdev->misc_vector.vector_irq, hdev); | |
2684 | hclge_free_vector(hdev, 0); | |
2685 | } | |
2686 | ||
4ed340ab L |
2687 | static int hclge_notify_client(struct hclge_dev *hdev, |
2688 | enum hnae3_reset_notify_type type) | |
2689 | { | |
2690 | struct hnae3_client *client = hdev->nic_client; | |
2691 | u16 i; | |
2692 | ||
2693 | if (!client->ops->reset_notify) | |
2694 | return -EOPNOTSUPP; | |
2695 | ||
2696 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
2697 | struct hnae3_handle *handle = &hdev->vport[i].nic; | |
2698 | int ret; | |
2699 | ||
2700 | ret = client->ops->reset_notify(handle, type); | |
2701 | if (ret) | |
2702 | return ret; | |
2703 | } | |
2704 | ||
2705 | return 0; | |
2706 | } | |
2707 | ||
2708 | static int hclge_reset_wait(struct hclge_dev *hdev) | |
2709 | { | |
2710 | #define HCLGE_RESET_WATI_MS 100 | |
2711 | #define HCLGE_RESET_WAIT_CNT 5 | |
2712 | u32 val, reg, reg_bit; | |
2713 | u32 cnt = 0; | |
2714 | ||
2715 | switch (hdev->reset_type) { | |
2716 | case HNAE3_GLOBAL_RESET: | |
2717 | reg = HCLGE_GLOBAL_RESET_REG; | |
2718 | reg_bit = HCLGE_GLOBAL_RESET_BIT; | |
2719 | break; | |
2720 | case HNAE3_CORE_RESET: | |
2721 | reg = HCLGE_GLOBAL_RESET_REG; | |
2722 | reg_bit = HCLGE_CORE_RESET_BIT; | |
2723 | break; | |
2724 | case HNAE3_FUNC_RESET: | |
2725 | reg = HCLGE_FUN_RST_ING; | |
2726 | reg_bit = HCLGE_FUN_RST_ING_B; | |
2727 | break; | |
2728 | default: | |
2729 | dev_err(&hdev->pdev->dev, | |
2730 | "Wait for unsupported reset type: %d\n", | |
2731 | hdev->reset_type); | |
2732 | return -EINVAL; | |
2733 | } | |
2734 | ||
2735 | val = hclge_read_dev(&hdev->hw, reg); | |
2736 | while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { | |
2737 | msleep(HCLGE_RESET_WATI_MS); | |
2738 | val = hclge_read_dev(&hdev->hw, reg); | |
2739 | cnt++; | |
2740 | } | |
2741 | ||
4ed340ab L |
2742 | if (cnt >= HCLGE_RESET_WAIT_CNT) { |
2743 | dev_warn(&hdev->pdev->dev, | |
2744 | "Wait for reset timeout: %d\n", hdev->reset_type); | |
2745 | return -EBUSY; | |
2746 | } | |
2747 | ||
2748 | return 0; | |
2749 | } | |
2750 | ||
13a86fae | 2751 | int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) |
4ed340ab L |
2752 | { |
2753 | struct hclge_desc desc; | |
2754 | struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; | |
2755 | int ret; | |
2756 | ||
2757 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); | |
2758 | hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0); | |
2759 | hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); | |
2760 | req->fun_reset_vfid = func_id; | |
2761 | ||
2762 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2763 | if (ret) | |
2764 | dev_err(&hdev->pdev->dev, | |
2765 | "send function reset cmd fail, status =%d\n", ret); | |
2766 | ||
2767 | return ret; | |
2768 | } | |
2769 | ||
d5752031 | 2770 | static void hclge_do_reset(struct hclge_dev *hdev) |
4ed340ab L |
2771 | { |
2772 | struct pci_dev *pdev = hdev->pdev; | |
2773 | u32 val; | |
2774 | ||
d5752031 | 2775 | switch (hdev->reset_type) { |
4ed340ab L |
2776 | case HNAE3_GLOBAL_RESET: |
2777 | val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); | |
2778 | hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); | |
2779 | hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); | |
2780 | dev_info(&pdev->dev, "Global Reset requested\n"); | |
2781 | break; | |
2782 | case HNAE3_CORE_RESET: | |
2783 | val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); | |
2784 | hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1); | |
2785 | hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); | |
2786 | dev_info(&pdev->dev, "Core Reset requested\n"); | |
2787 | break; | |
2788 | case HNAE3_FUNC_RESET: | |
2789 | dev_info(&pdev->dev, "PF Reset requested\n"); | |
2790 | hclge_func_reset_cmd(hdev, 0); | |
ed4a1bb8 SM |
2791 | /* schedule again to check later */ |
2792 | set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); | |
2793 | hclge_reset_task_schedule(hdev); | |
4ed340ab L |
2794 | break; |
2795 | default: | |
2796 | dev_warn(&pdev->dev, | |
d5752031 | 2797 | "Unsupported reset type: %d\n", hdev->reset_type); |
4ed340ab L |
2798 | break; |
2799 | } | |
2800 | } | |
2801 | ||
d5752031 SM |
2802 | static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev, |
2803 | unsigned long *addr) | |
2804 | { | |
2805 | enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; | |
2806 | ||
2807 | /* return the highest priority reset level amongst all */ | |
2808 | if (test_bit(HNAE3_GLOBAL_RESET, addr)) | |
2809 | rst_level = HNAE3_GLOBAL_RESET; | |
2810 | else if (test_bit(HNAE3_CORE_RESET, addr)) | |
2811 | rst_level = HNAE3_CORE_RESET; | |
2812 | else if (test_bit(HNAE3_IMP_RESET, addr)) | |
2813 | rst_level = HNAE3_IMP_RESET; | |
2814 | else if (test_bit(HNAE3_FUNC_RESET, addr)) | |
2815 | rst_level = HNAE3_FUNC_RESET; | |
2816 | ||
2817 | /* now, clear all other resets */ | |
2818 | clear_bit(HNAE3_GLOBAL_RESET, addr); | |
2819 | clear_bit(HNAE3_CORE_RESET, addr); | |
2820 | clear_bit(HNAE3_IMP_RESET, addr); | |
2821 | clear_bit(HNAE3_FUNC_RESET, addr); | |
2822 | ||
2823 | return rst_level; | |
2824 | } | |
2825 | ||
2826 | static void hclge_reset(struct hclge_dev *hdev) | |
2827 | { | |
2828 | /* perform reset of the stack & ae device for a client */ | |
2829 | ||
2830 | hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); | |
2831 | ||
2832 | if (!hclge_reset_wait(hdev)) { | |
2833 | rtnl_lock(); | |
2834 | hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); | |
2835 | hclge_reset_ae_dev(hdev->ae_dev); | |
2836 | hclge_notify_client(hdev, HNAE3_INIT_CLIENT); | |
2837 | rtnl_unlock(); | |
2838 | } else { | |
2839 | /* schedule again to check pending resets later */ | |
2840 | set_bit(hdev->reset_type, &hdev->reset_pending); | |
2841 | hclge_reset_task_schedule(hdev); | |
2842 | } | |
2843 | ||
2844 | hclge_notify_client(hdev, HNAE3_UP_CLIENT); | |
2845 | } | |
2846 | ||
4aef908d | 2847 | static void hclge_reset_event(struct hnae3_handle *handle) |
4ed340ab L |
2848 | { |
2849 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2850 | struct hclge_dev *hdev = vport->back; | |
2851 | ||
4aef908d SM |
2852 | /* check if this is a new reset request and we are not here just because |
2853 | * last reset attempt did not succeed and watchdog hit us again. We will | |
2854 | * know this if last reset request did not occur very recently (watchdog | |
2855 | * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) | |
2856 | * In case of new request we reset the "reset level" to PF reset. | |
2857 | */ | |
2858 | if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ))) | |
2859 | handle->reset_level = HNAE3_FUNC_RESET; | |
4ed340ab | 2860 | |
4aef908d SM |
2861 | dev_info(&hdev->pdev->dev, "received reset event , reset type is %d", |
2862 | handle->reset_level); | |
2863 | ||
2864 | /* request reset & schedule reset task */ | |
2865 | set_bit(handle->reset_level, &hdev->reset_request); | |
2866 | hclge_reset_task_schedule(hdev); | |
2867 | ||
2868 | if (handle->reset_level < HNAE3_GLOBAL_RESET) | |
2869 | handle->reset_level++; | |
2870 | ||
2871 | handle->last_reset_time = jiffies; | |
4ed340ab L |
2872 | } |
2873 | ||
2874 | static void hclge_reset_subtask(struct hclge_dev *hdev) | |
2875 | { | |
d5752031 SM |
2876 | /* check if there is any ongoing reset in the hardware. This status can |
2877 | * be checked from reset_pending. If there is then, we need to wait for | |
2878 | * hardware to complete reset. | |
2879 | * a. If we are able to figure out in reasonable time that hardware | |
2880 | * has fully resetted then, we can proceed with driver, client | |
2881 | * reset. | |
2882 | * b. else, we can come back later to check this status so re-sched | |
2883 | * now. | |
2884 | */ | |
2885 | hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending); | |
2886 | if (hdev->reset_type != HNAE3_NONE_RESET) | |
2887 | hclge_reset(hdev); | |
4ed340ab | 2888 | |
d5752031 SM |
2889 | /* check if we got any *new* reset requests to be honored */ |
2890 | hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request); | |
2891 | if (hdev->reset_type != HNAE3_NONE_RESET) | |
2892 | hclge_do_reset(hdev); | |
4ed340ab | 2893 | |
4ed340ab L |
2894 | hdev->reset_type = HNAE3_NONE_RESET; |
2895 | } | |
2896 | ||
ed4a1bb8 | 2897 | static void hclge_reset_service_task(struct work_struct *work) |
466b0c00 | 2898 | { |
ed4a1bb8 SM |
2899 | struct hclge_dev *hdev = |
2900 | container_of(work, struct hclge_dev, rst_service_task); | |
2901 | ||
2902 | if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) | |
2903 | return; | |
2904 | ||
2905 | clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); | |
2906 | ||
4ed340ab | 2907 | hclge_reset_subtask(hdev); |
ed4a1bb8 SM |
2908 | |
2909 | clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); | |
466b0c00 L |
2910 | } |
2911 | ||
22fd3468 SM |
2912 | static void hclge_mailbox_service_task(struct work_struct *work) |
2913 | { | |
2914 | struct hclge_dev *hdev = | |
2915 | container_of(work, struct hclge_dev, mbx_service_task); | |
2916 | ||
2917 | if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) | |
2918 | return; | |
2919 | ||
2920 | clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); | |
2921 | ||
2922 | hclge_mbx_handler(hdev); | |
2923 | ||
2924 | clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); | |
2925 | } | |
2926 | ||
46a3df9f S |
2927 | static void hclge_service_task(struct work_struct *work) |
2928 | { | |
2929 | struct hclge_dev *hdev = | |
2930 | container_of(work, struct hclge_dev, service_task); | |
2931 | ||
fe36292f JS |
2932 | /* The total rx/tx packets statstics are wanted to be updated |
2933 | * per second. Both hclge_update_stats_for_all() and | |
2934 | * hclge_mac_get_traffic_stats() can do it. | |
2935 | */ | |
7a5d2a39 JS |
2936 | if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) { |
2937 | hclge_update_stats_for_all(hdev); | |
2938 | hdev->hw_stats.stats_timer = 0; | |
fe36292f JS |
2939 | } else { |
2940 | hclge_mac_get_traffic_stats(hdev); | |
7a5d2a39 JS |
2941 | } |
2942 | ||
46a3df9f S |
2943 | hclge_update_speed_duplex(hdev); |
2944 | hclge_update_link_status(hdev); | |
fe36292f | 2945 | hclge_update_led_status(hdev); |
46a3df9f S |
2946 | hclge_service_complete(hdev); |
2947 | } | |
2948 | ||
2949 | static void hclge_disable_sriov(struct hclge_dev *hdev) | |
2950 | { | |
2a32ca13 AB |
2951 | /* If our VFs are assigned we cannot shut down SR-IOV |
2952 | * without causing issues, so just leave the hardware | |
2953 | * available but disabled | |
2954 | */ | |
2955 | if (pci_vfs_assigned(hdev->pdev)) { | |
2956 | dev_warn(&hdev->pdev->dev, | |
2957 | "disabling driver while VFs are assigned\n"); | |
2958 | return; | |
2959 | } | |
46a3df9f | 2960 | |
2a32ca13 | 2961 | pci_disable_sriov(hdev->pdev); |
46a3df9f S |
2962 | } |
2963 | ||
2964 | struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) | |
2965 | { | |
2966 | /* VF handle has no client */ | |
2967 | if (!handle->client) | |
2968 | return container_of(handle, struct hclge_vport, nic); | |
2969 | else if (handle->client->type == HNAE3_CLIENT_ROCE) | |
2970 | return container_of(handle, struct hclge_vport, roce); | |
2971 | else | |
2972 | return container_of(handle, struct hclge_vport, nic); | |
2973 | } | |
2974 | ||
2975 | static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, | |
2976 | struct hnae3_vector_info *vector_info) | |
2977 | { | |
2978 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2979 | struct hnae3_vector_info *vector = vector_info; | |
2980 | struct hclge_dev *hdev = vport->back; | |
2981 | int alloc = 0; | |
2982 | int i, j; | |
2983 | ||
2984 | vector_num = min(hdev->num_msi_left, vector_num); | |
2985 | ||
2986 | for (j = 0; j < vector_num; j++) { | |
2987 | for (i = 1; i < hdev->num_msi; i++) { | |
2988 | if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { | |
2989 | vector->vector = pci_irq_vector(hdev->pdev, i); | |
2990 | vector->io_addr = hdev->hw.io_base + | |
2991 | HCLGE_VECTOR_REG_BASE + | |
2992 | (i - 1) * HCLGE_VECTOR_REG_OFFSET + | |
2993 | vport->vport_id * | |
2994 | HCLGE_VECTOR_VF_OFFSET; | |
2995 | hdev->vector_status[i] = vport->vport_id; | |
887c3820 | 2996 | hdev->vector_irq[i] = vector->vector; |
46a3df9f S |
2997 | |
2998 | vector++; | |
2999 | alloc++; | |
3000 | ||
3001 | break; | |
3002 | } | |
3003 | } | |
3004 | } | |
3005 | hdev->num_msi_left -= alloc; | |
3006 | hdev->num_msi_used += alloc; | |
3007 | ||
3008 | return alloc; | |
3009 | } | |
3010 | ||
3011 | static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) | |
3012 | { | |
3013 | int i; | |
3014 | ||
887c3820 SM |
3015 | for (i = 0; i < hdev->num_msi; i++) |
3016 | if (vector == hdev->vector_irq[i]) | |
3017 | return i; | |
3018 | ||
46a3df9f S |
3019 | return -EINVAL; |
3020 | } | |
3021 | ||
7412200c YL |
3022 | static int hclge_put_vector(struct hnae3_handle *handle, int vector) |
3023 | { | |
3024 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3025 | struct hclge_dev *hdev = vport->back; | |
3026 | int vector_id; | |
3027 | ||
3028 | vector_id = hclge_get_vector_index(hdev, vector); | |
3029 | if (vector_id < 0) { | |
3030 | dev_err(&hdev->pdev->dev, | |
3031 | "Get vector index fail. vector_id =%d\n", vector_id); | |
3032 | return vector_id; | |
3033 | } | |
3034 | ||
3035 | hclge_free_vector(hdev, vector_id); | |
3036 | ||
3037 | return 0; | |
3038 | } | |
3039 | ||
46a3df9f S |
3040 | static u32 hclge_get_rss_key_size(struct hnae3_handle *handle) |
3041 | { | |
3042 | return HCLGE_RSS_KEY_SIZE; | |
3043 | } | |
3044 | ||
3045 | static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle) | |
3046 | { | |
3047 | return HCLGE_RSS_IND_TBL_SIZE; | |
3048 | } | |
3049 | ||
46a3df9f S |
3050 | static int hclge_set_rss_algo_key(struct hclge_dev *hdev, |
3051 | const u8 hfunc, const u8 *key) | |
3052 | { | |
d44f9b63 | 3053 | struct hclge_rss_config_cmd *req; |
46a3df9f S |
3054 | struct hclge_desc desc; |
3055 | int key_offset; | |
3056 | int key_size; | |
3057 | int ret; | |
3058 | ||
d44f9b63 | 3059 | req = (struct hclge_rss_config_cmd *)desc.data; |
46a3df9f S |
3060 | |
3061 | for (key_offset = 0; key_offset < 3; key_offset++) { | |
3062 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, | |
3063 | false); | |
3064 | ||
3065 | req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK); | |
3066 | req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B); | |
3067 | ||
3068 | if (key_offset == 2) | |
3069 | key_size = | |
3070 | HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2; | |
3071 | else | |
3072 | key_size = HCLGE_RSS_HASH_KEY_NUM; | |
3073 | ||
3074 | memcpy(req->hash_key, | |
3075 | key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size); | |
3076 | ||
3077 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3078 | if (ret) { | |
3079 | dev_err(&hdev->pdev->dev, | |
3080 | "Configure RSS config fail, status = %d\n", | |
3081 | ret); | |
3082 | return ret; | |
3083 | } | |
3084 | } | |
3085 | return 0; | |
3086 | } | |
3087 | ||
dcd4ef5e | 3088 | static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir) |
46a3df9f | 3089 | { |
d44f9b63 | 3090 | struct hclge_rss_indirection_table_cmd *req; |
46a3df9f S |
3091 | struct hclge_desc desc; |
3092 | int i, j; | |
3093 | int ret; | |
3094 | ||
d44f9b63 | 3095 | req = (struct hclge_rss_indirection_table_cmd *)desc.data; |
46a3df9f S |
3096 | |
3097 | for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) { | |
3098 | hclge_cmd_setup_basic_desc | |
3099 | (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false); | |
3100 | ||
a90bb9a5 YL |
3101 | req->start_table_index = |
3102 | cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE); | |
3103 | req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK); | |
46a3df9f S |
3104 | |
3105 | for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++) | |
3106 | req->rss_result[j] = | |
3107 | indir[i * HCLGE_RSS_CFG_TBL_SIZE + j]; | |
3108 | ||
3109 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3110 | if (ret) { | |
3111 | dev_err(&hdev->pdev->dev, | |
3112 | "Configure rss indir table fail,status = %d\n", | |
3113 | ret); | |
3114 | return ret; | |
3115 | } | |
3116 | } | |
3117 | return 0; | |
3118 | } | |
3119 | ||
3120 | static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid, | |
3121 | u16 *tc_size, u16 *tc_offset) | |
3122 | { | |
d44f9b63 | 3123 | struct hclge_rss_tc_mode_cmd *req; |
46a3df9f S |
3124 | struct hclge_desc desc; |
3125 | int ret; | |
3126 | int i; | |
3127 | ||
3128 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false); | |
d44f9b63 | 3129 | req = (struct hclge_rss_tc_mode_cmd *)desc.data; |
46a3df9f S |
3130 | |
3131 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
a90bb9a5 YL |
3132 | u16 mode = 0; |
3133 | ||
3134 | hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); | |
3135 | hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M, | |
46a3df9f | 3136 | HCLGE_RSS_TC_SIZE_S, tc_size[i]); |
a90bb9a5 | 3137 | hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M, |
46a3df9f | 3138 | HCLGE_RSS_TC_OFFSET_S, tc_offset[i]); |
a90bb9a5 YL |
3139 | |
3140 | req->rss_tc_mode[i] = cpu_to_le16(mode); | |
46a3df9f S |
3141 | } |
3142 | ||
3143 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3144 | if (ret) { | |
3145 | dev_err(&hdev->pdev->dev, | |
3146 | "Configure rss tc mode fail, status = %d\n", ret); | |
3147 | return ret; | |
3148 | } | |
3149 | ||
3150 | return 0; | |
3151 | } | |
3152 | ||
3153 | static int hclge_set_rss_input_tuple(struct hclge_dev *hdev) | |
3154 | { | |
d44f9b63 | 3155 | struct hclge_rss_input_tuple_cmd *req; |
46a3df9f S |
3156 | struct hclge_desc desc; |
3157 | int ret; | |
3158 | ||
3159 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); | |
3160 | ||
d44f9b63 | 3161 | req = (struct hclge_rss_input_tuple_cmd *)desc.data; |
637053ef YL |
3162 | |
3163 | /* Get the tuple cfg from pf */ | |
3164 | req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en; | |
3165 | req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en; | |
3166 | req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en; | |
3167 | req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en; | |
3168 | req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en; | |
3169 | req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en; | |
3170 | req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en; | |
3171 | req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en; | |
46a3df9f S |
3172 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
3173 | if (ret) { | |
3174 | dev_err(&hdev->pdev->dev, | |
3175 | "Configure rss input fail, status = %d\n", ret); | |
3176 | return ret; | |
3177 | } | |
3178 | ||
3179 | return 0; | |
3180 | } | |
3181 | ||
3182 | static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, | |
3183 | u8 *key, u8 *hfunc) | |
3184 | { | |
3185 | struct hclge_vport *vport = hclge_get_vport(handle); | |
46a3df9f S |
3186 | int i; |
3187 | ||
3188 | /* Get hash algorithm */ | |
3189 | if (hfunc) | |
dcd4ef5e | 3190 | *hfunc = vport->rss_algo; |
46a3df9f S |
3191 | |
3192 | /* Get the RSS Key required by the user */ | |
3193 | if (key) | |
3194 | memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE); | |
3195 | ||
3196 | /* Get indirect table */ | |
3197 | if (indir) | |
3198 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
3199 | indir[i] = vport->rss_indirection_tbl[i]; | |
3200 | ||
3201 | return 0; | |
3202 | } | |
3203 | ||
3204 | static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, | |
3205 | const u8 *key, const u8 hfunc) | |
3206 | { | |
3207 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3208 | struct hclge_dev *hdev = vport->back; | |
3209 | u8 hash_algo; | |
3210 | int ret, i; | |
3211 | ||
3212 | /* Set the RSS Hash Key if specififed by the user */ | |
3213 | if (key) { | |
46a3df9f S |
3214 | |
3215 | if (hfunc == ETH_RSS_HASH_TOP || | |
3216 | hfunc == ETH_RSS_HASH_NO_CHANGE) | |
3217 | hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; | |
3218 | else | |
3219 | return -EINVAL; | |
3220 | ret = hclge_set_rss_algo_key(hdev, hash_algo, key); | |
3221 | if (ret) | |
3222 | return ret; | |
dcd4ef5e YL |
3223 | |
3224 | /* Update the shadow RSS key with user specified qids */ | |
3225 | memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE); | |
3226 | vport->rss_algo = hash_algo; | |
46a3df9f S |
3227 | } |
3228 | ||
3229 | /* Update the shadow RSS table with user specified qids */ | |
3230 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
3231 | vport->rss_indirection_tbl[i] = indir[i]; | |
3232 | ||
3233 | /* Update the hardware */ | |
dcd4ef5e | 3234 | return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl); |
46a3df9f S |
3235 | } |
3236 | ||
f7db940a L |
3237 | static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc) |
3238 | { | |
3239 | u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0; | |
3240 | ||
3241 | if (nfc->data & RXH_L4_B_2_3) | |
3242 | hash_sets |= HCLGE_D_PORT_BIT; | |
3243 | else | |
3244 | hash_sets &= ~HCLGE_D_PORT_BIT; | |
3245 | ||
3246 | if (nfc->data & RXH_IP_SRC) | |
3247 | hash_sets |= HCLGE_S_IP_BIT; | |
3248 | else | |
3249 | hash_sets &= ~HCLGE_S_IP_BIT; | |
3250 | ||
3251 | if (nfc->data & RXH_IP_DST) | |
3252 | hash_sets |= HCLGE_D_IP_BIT; | |
3253 | else | |
3254 | hash_sets &= ~HCLGE_D_IP_BIT; | |
3255 | ||
3256 | if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) | |
3257 | hash_sets |= HCLGE_V_TAG_BIT; | |
3258 | ||
3259 | return hash_sets; | |
3260 | } | |
3261 | ||
3262 | static int hclge_set_rss_tuple(struct hnae3_handle *handle, | |
3263 | struct ethtool_rxnfc *nfc) | |
3264 | { | |
3265 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3266 | struct hclge_dev *hdev = vport->back; | |
3267 | struct hclge_rss_input_tuple_cmd *req; | |
3268 | struct hclge_desc desc; | |
3269 | u8 tuple_sets; | |
3270 | int ret; | |
3271 | ||
3272 | if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | | |
3273 | RXH_L4_B_0_1 | RXH_L4_B_2_3)) | |
3274 | return -EINVAL; | |
3275 | ||
3276 | req = (struct hclge_rss_input_tuple_cmd *)desc.data; | |
637053ef | 3277 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); |
f7db940a | 3278 | |
637053ef YL |
3279 | req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en; |
3280 | req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en; | |
3281 | req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en; | |
3282 | req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en; | |
3283 | req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en; | |
3284 | req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en; | |
3285 | req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en; | |
3286 | req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en; | |
f7db940a L |
3287 | |
3288 | tuple_sets = hclge_get_rss_hash_bits(nfc); | |
3289 | switch (nfc->flow_type) { | |
3290 | case TCP_V4_FLOW: | |
3291 | req->ipv4_tcp_en = tuple_sets; | |
3292 | break; | |
3293 | case TCP_V6_FLOW: | |
3294 | req->ipv6_tcp_en = tuple_sets; | |
3295 | break; | |
3296 | case UDP_V4_FLOW: | |
3297 | req->ipv4_udp_en = tuple_sets; | |
3298 | break; | |
3299 | case UDP_V6_FLOW: | |
3300 | req->ipv6_udp_en = tuple_sets; | |
3301 | break; | |
3302 | case SCTP_V4_FLOW: | |
3303 | req->ipv4_sctp_en = tuple_sets; | |
3304 | break; | |
3305 | case SCTP_V6_FLOW: | |
3306 | if ((nfc->data & RXH_L4_B_0_1) || | |
3307 | (nfc->data & RXH_L4_B_2_3)) | |
3308 | return -EINVAL; | |
3309 | ||
3310 | req->ipv6_sctp_en = tuple_sets; | |
3311 | break; | |
3312 | case IPV4_FLOW: | |
3313 | req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3314 | break; | |
3315 | case IPV6_FLOW: | |
3316 | req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3317 | break; | |
3318 | default: | |
3319 | return -EINVAL; | |
3320 | } | |
3321 | ||
3322 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
637053ef | 3323 | if (ret) { |
f7db940a L |
3324 | dev_err(&hdev->pdev->dev, |
3325 | "Set rss tuple fail, status = %d\n", ret); | |
637053ef YL |
3326 | return ret; |
3327 | } | |
f7db940a | 3328 | |
637053ef YL |
3329 | vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; |
3330 | vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; | |
3331 | vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; | |
3332 | vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; | |
3333 | vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; | |
3334 | vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; | |
3335 | vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; | |
3336 | vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; | |
3337 | return 0; | |
f7db940a L |
3338 | } |
3339 | ||
07d29954 L |
3340 | static int hclge_get_rss_tuple(struct hnae3_handle *handle, |
3341 | struct ethtool_rxnfc *nfc) | |
3342 | { | |
3343 | struct hclge_vport *vport = hclge_get_vport(handle); | |
07d29954 | 3344 | u8 tuple_sets; |
07d29954 L |
3345 | |
3346 | nfc->data = 0; | |
3347 | ||
07d29954 L |
3348 | switch (nfc->flow_type) { |
3349 | case TCP_V4_FLOW: | |
637053ef | 3350 | tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en; |
07d29954 L |
3351 | break; |
3352 | case UDP_V4_FLOW: | |
637053ef | 3353 | tuple_sets = vport->rss_tuple_sets.ipv4_udp_en; |
07d29954 L |
3354 | break; |
3355 | case TCP_V6_FLOW: | |
637053ef | 3356 | tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en; |
07d29954 L |
3357 | break; |
3358 | case UDP_V6_FLOW: | |
637053ef | 3359 | tuple_sets = vport->rss_tuple_sets.ipv6_udp_en; |
07d29954 L |
3360 | break; |
3361 | case SCTP_V4_FLOW: | |
637053ef | 3362 | tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en; |
07d29954 L |
3363 | break; |
3364 | case SCTP_V6_FLOW: | |
637053ef | 3365 | tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en; |
07d29954 L |
3366 | break; |
3367 | case IPV4_FLOW: | |
3368 | case IPV6_FLOW: | |
3369 | tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT; | |
3370 | break; | |
3371 | default: | |
3372 | return -EINVAL; | |
3373 | } | |
3374 | ||
3375 | if (!tuple_sets) | |
3376 | return 0; | |
3377 | ||
3378 | if (tuple_sets & HCLGE_D_PORT_BIT) | |
3379 | nfc->data |= RXH_L4_B_2_3; | |
3380 | if (tuple_sets & HCLGE_S_PORT_BIT) | |
3381 | nfc->data |= RXH_L4_B_0_1; | |
3382 | if (tuple_sets & HCLGE_D_IP_BIT) | |
3383 | nfc->data |= RXH_IP_DST; | |
3384 | if (tuple_sets & HCLGE_S_IP_BIT) | |
3385 | nfc->data |= RXH_IP_SRC; | |
3386 | ||
3387 | return 0; | |
3388 | } | |
3389 | ||
46a3df9f S |
3390 | static int hclge_get_tc_size(struct hnae3_handle *handle) |
3391 | { | |
3392 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3393 | struct hclge_dev *hdev = vport->back; | |
3394 | ||
3395 | return hdev->rss_size_max; | |
3396 | } | |
3397 | ||
77f255c1 | 3398 | int hclge_rss_init_hw(struct hclge_dev *hdev) |
46a3df9f | 3399 | { |
46a3df9f | 3400 | struct hclge_vport *vport = hdev->vport; |
8015bb74 YL |
3401 | u8 *rss_indir = vport[0].rss_indirection_tbl; |
3402 | u16 rss_size = vport[0].alloc_rss_size; | |
3403 | u8 *key = vport[0].rss_hash_key; | |
3404 | u8 hfunc = vport[0].rss_algo; | |
46a3df9f | 3405 | u16 tc_offset[HCLGE_MAX_TC_NUM]; |
46a3df9f S |
3406 | u16 tc_valid[HCLGE_MAX_TC_NUM]; |
3407 | u16 tc_size[HCLGE_MAX_TC_NUM]; | |
8015bb74 YL |
3408 | u16 roundup_size; |
3409 | int i, ret; | |
68ece54e | 3410 | |
46a3df9f S |
3411 | ret = hclge_set_rss_indir_table(hdev, rss_indir); |
3412 | if (ret) | |
8015bb74 | 3413 | return ret; |
46a3df9f | 3414 | |
46a3df9f S |
3415 | ret = hclge_set_rss_algo_key(hdev, hfunc, key); |
3416 | if (ret) | |
8015bb74 | 3417 | return ret; |
46a3df9f S |
3418 | |
3419 | ret = hclge_set_rss_input_tuple(hdev); | |
3420 | if (ret) | |
8015bb74 | 3421 | return ret; |
46a3df9f | 3422 | |
68ece54e YL |
3423 | /* Each TC have the same queue size, and tc_size set to hardware is |
3424 | * the log2 of roundup power of two of rss_size, the acutal queue | |
3425 | * size is limited by indirection table. | |
3426 | */ | |
3427 | if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) { | |
3428 | dev_err(&hdev->pdev->dev, | |
3429 | "Configure rss tc size failed, invalid TC_SIZE = %d\n", | |
3430 | rss_size); | |
8015bb74 | 3431 | return -EINVAL; |
68ece54e YL |
3432 | } |
3433 | ||
3434 | roundup_size = roundup_pow_of_two(rss_size); | |
3435 | roundup_size = ilog2(roundup_size); | |
3436 | ||
46a3df9f | 3437 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
68ece54e | 3438 | tc_valid[i] = 0; |
46a3df9f | 3439 | |
68ece54e YL |
3440 | if (!(hdev->hw_tc_map & BIT(i))) |
3441 | continue; | |
3442 | ||
3443 | tc_valid[i] = 1; | |
3444 | tc_size[i] = roundup_size; | |
3445 | tc_offset[i] = rss_size * i; | |
46a3df9f | 3446 | } |
68ece54e | 3447 | |
8015bb74 YL |
3448 | return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); |
3449 | } | |
46a3df9f | 3450 | |
8015bb74 YL |
3451 | void hclge_rss_indir_init_cfg(struct hclge_dev *hdev) |
3452 | { | |
3453 | struct hclge_vport *vport = hdev->vport; | |
3454 | int i, j; | |
46a3df9f | 3455 | |
8015bb74 YL |
3456 | for (j = 0; j < hdev->num_vmdq_vport + 1; j++) { |
3457 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
3458 | vport[j].rss_indirection_tbl[i] = | |
3459 | i % vport[j].alloc_rss_size; | |
3460 | } | |
3461 | } | |
3462 | ||
3463 | static void hclge_rss_init_cfg(struct hclge_dev *hdev) | |
3464 | { | |
3465 | struct hclge_vport *vport = hdev->vport; | |
3466 | int i; | |
3467 | ||
8015bb74 YL |
3468 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { |
3469 | vport[i].rss_tuple_sets.ipv4_tcp_en = | |
3470 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3471 | vport[i].rss_tuple_sets.ipv4_udp_en = | |
3472 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3473 | vport[i].rss_tuple_sets.ipv4_sctp_en = | |
3474 | HCLGE_RSS_INPUT_TUPLE_SCTP; | |
3475 | vport[i].rss_tuple_sets.ipv4_fragment_en = | |
3476 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3477 | vport[i].rss_tuple_sets.ipv6_tcp_en = | |
3478 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3479 | vport[i].rss_tuple_sets.ipv6_udp_en = | |
3480 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3481 | vport[i].rss_tuple_sets.ipv6_sctp_en = | |
3482 | HCLGE_RSS_INPUT_TUPLE_SCTP; | |
3483 | vport[i].rss_tuple_sets.ipv6_fragment_en = | |
3484 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3485 | ||
3486 | vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; | |
823fe868 FL |
3487 | |
3488 | netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE); | |
8015bb74 YL |
3489 | } |
3490 | ||
3491 | hclge_rss_indir_init_cfg(hdev); | |
46a3df9f S |
3492 | } |
3493 | ||
63d7e66f SM |
3494 | int hclge_bind_ring_with_vector(struct hclge_vport *vport, |
3495 | int vector_id, bool en, | |
3496 | struct hnae3_ring_chain_node *ring_chain) | |
46a3df9f S |
3497 | { |
3498 | struct hclge_dev *hdev = vport->back; | |
46a3df9f S |
3499 | struct hnae3_ring_chain_node *node; |
3500 | struct hclge_desc desc; | |
63d7e66f SM |
3501 | struct hclge_ctrl_vector_chain_cmd *req |
3502 | = (struct hclge_ctrl_vector_chain_cmd *)desc.data; | |
3503 | enum hclge_cmd_status status; | |
3504 | enum hclge_opcode_type op; | |
3505 | u16 tqp_type_and_id; | |
46a3df9f S |
3506 | int i; |
3507 | ||
63d7e66f SM |
3508 | op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; |
3509 | hclge_cmd_setup_basic_desc(&desc, op, false); | |
46a3df9f S |
3510 | req->int_vector_id = vector_id; |
3511 | ||
3512 | i = 0; | |
3513 | for (node = ring_chain; node; node = node->next) { | |
63d7e66f SM |
3514 | tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); |
3515 | hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, | |
3516 | HCLGE_INT_TYPE_S, | |
46a3df9f | 3517 | hnae_get_bit(node->flag, HNAE3_RING_TYPE_B)); |
63d7e66f SM |
3518 | hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, |
3519 | HCLGE_TQP_ID_S, node->tqp_index); | |
f230c6c5 FL |
3520 | hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, |
3521 | HCLGE_INT_GL_IDX_S, | |
3522 | hnae_get_field(node->int_gl_idx, | |
3523 | HNAE3_RING_GL_IDX_M, | |
3524 | HNAE3_RING_GL_IDX_S)); | |
63d7e66f | 3525 | req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); |
46a3df9f S |
3526 | if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { |
3527 | req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; | |
63d7e66f | 3528 | req->vfid = vport->vport_id; |
46a3df9f | 3529 | |
63d7e66f SM |
3530 | status = hclge_cmd_send(&hdev->hw, &desc, 1); |
3531 | if (status) { | |
46a3df9f S |
3532 | dev_err(&hdev->pdev->dev, |
3533 | "Map TQP fail, status is %d.\n", | |
63d7e66f SM |
3534 | status); |
3535 | return -EIO; | |
46a3df9f S |
3536 | } |
3537 | i = 0; | |
3538 | ||
3539 | hclge_cmd_setup_basic_desc(&desc, | |
63d7e66f | 3540 | op, |
46a3df9f S |
3541 | false); |
3542 | req->int_vector_id = vector_id; | |
3543 | } | |
3544 | } | |
3545 | ||
3546 | if (i > 0) { | |
3547 | req->int_cause_num = i; | |
63d7e66f SM |
3548 | req->vfid = vport->vport_id; |
3549 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3550 | if (status) { | |
46a3df9f | 3551 | dev_err(&hdev->pdev->dev, |
63d7e66f SM |
3552 | "Map TQP fail, status is %d.\n", status); |
3553 | return -EIO; | |
46a3df9f S |
3554 | } |
3555 | } | |
3556 | ||
3557 | return 0; | |
3558 | } | |
3559 | ||
63d7e66f SM |
3560 | static int hclge_map_ring_to_vector(struct hnae3_handle *handle, |
3561 | int vector, | |
3562 | struct hnae3_ring_chain_node *ring_chain) | |
46a3df9f S |
3563 | { |
3564 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3565 | struct hclge_dev *hdev = vport->back; | |
3566 | int vector_id; | |
3567 | ||
3568 | vector_id = hclge_get_vector_index(hdev, vector); | |
3569 | if (vector_id < 0) { | |
3570 | dev_err(&hdev->pdev->dev, | |
63d7e66f | 3571 | "Get vector index fail. vector_id =%d\n", vector_id); |
46a3df9f S |
3572 | return vector_id; |
3573 | } | |
3574 | ||
63d7e66f | 3575 | return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); |
46a3df9f S |
3576 | } |
3577 | ||
63d7e66f SM |
3578 | static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, |
3579 | int vector, | |
3580 | struct hnae3_ring_chain_node *ring_chain) | |
46a3df9f S |
3581 | { |
3582 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3583 | struct hclge_dev *hdev = vport->back; | |
63d7e66f | 3584 | int vector_id, ret; |
46a3df9f | 3585 | |
f9637cc2 PL |
3586 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) |
3587 | return 0; | |
3588 | ||
46a3df9f S |
3589 | vector_id = hclge_get_vector_index(hdev, vector); |
3590 | if (vector_id < 0) { | |
3591 | dev_err(&handle->pdev->dev, | |
3592 | "Get vector index fail. ret =%d\n", vector_id); | |
3593 | return vector_id; | |
3594 | } | |
3595 | ||
63d7e66f | 3596 | ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); |
7412200c | 3597 | if (ret) |
63d7e66f SM |
3598 | dev_err(&handle->pdev->dev, |
3599 | "Unmap ring from vector fail. vectorid=%d, ret =%d\n", | |
3600 | vector_id, | |
3601 | ret); | |
46a3df9f | 3602 | |
7412200c | 3603 | return ret; |
46a3df9f S |
3604 | } |
3605 | ||
3606 | int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, | |
3607 | struct hclge_promisc_param *param) | |
3608 | { | |
d44f9b63 | 3609 | struct hclge_promisc_cfg_cmd *req; |
46a3df9f S |
3610 | struct hclge_desc desc; |
3611 | int ret; | |
3612 | ||
3613 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); | |
3614 | ||
d44f9b63 | 3615 | req = (struct hclge_promisc_cfg_cmd *)desc.data; |
46a3df9f S |
3616 | req->vf_id = param->vf_id; |
3617 | req->flag = (param->enable << HCLGE_PROMISC_EN_B); | |
3618 | ||
3619 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3620 | if (ret) { | |
3621 | dev_err(&hdev->pdev->dev, | |
3622 | "Set promisc mode fail, status is %d.\n", ret); | |
3623 | return ret; | |
3624 | } | |
3625 | return 0; | |
3626 | } | |
3627 | ||
3628 | void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, | |
3629 | bool en_mc, bool en_bc, int vport_id) | |
3630 | { | |
3631 | if (!param) | |
3632 | return; | |
3633 | ||
3634 | memset(param, 0, sizeof(struct hclge_promisc_param)); | |
3635 | if (en_uc) | |
3636 | param->enable = HCLGE_PROMISC_EN_UC; | |
3637 | if (en_mc) | |
3638 | param->enable |= HCLGE_PROMISC_EN_MC; | |
3639 | if (en_bc) | |
3640 | param->enable |= HCLGE_PROMISC_EN_BC; | |
3641 | param->vf_id = vport_id; | |
3642 | } | |
3643 | ||
3644 | static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en) | |
3645 | { | |
3646 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3647 | struct hclge_dev *hdev = vport->back; | |
3648 | struct hclge_promisc_param param; | |
3649 | ||
3650 | hclge_promisc_param_init(¶m, en, en, true, vport->vport_id); | |
3651 | hclge_cmd_set_promisc_mode(hdev, ¶m); | |
3652 | } | |
3653 | ||
3654 | static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) | |
3655 | { | |
3656 | struct hclge_desc desc; | |
d44f9b63 YL |
3657 | struct hclge_config_mac_mode_cmd *req = |
3658 | (struct hclge_config_mac_mode_cmd *)desc.data; | |
a90bb9a5 | 3659 | u32 loop_en = 0; |
46a3df9f S |
3660 | int ret; |
3661 | ||
3662 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); | |
a90bb9a5 YL |
3663 | hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable); |
3664 | hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable); | |
3665 | hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable); | |
3666 | hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable); | |
3667 | hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0); | |
3668 | hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0); | |
3669 | hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); | |
3670 | hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0); | |
3671 | hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable); | |
3672 | hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable); | |
3673 | hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable); | |
3674 | hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable); | |
3675 | hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable); | |
3676 | hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable); | |
3677 | req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); | |
46a3df9f S |
3678 | |
3679 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3680 | if (ret) | |
3681 | dev_err(&hdev->pdev->dev, | |
3682 | "mac enable fail, ret =%d.\n", ret); | |
3683 | } | |
3684 | ||
c39c4d98 YL |
3685 | static int hclge_set_loopback(struct hnae3_handle *handle, |
3686 | enum hnae3_loop loop_mode, bool en) | |
3687 | { | |
3688 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3689 | struct hclge_config_mac_mode_cmd *req; | |
3690 | struct hclge_dev *hdev = vport->back; | |
3691 | struct hclge_desc desc; | |
3692 | u32 loop_en; | |
3693 | int ret; | |
3694 | ||
3695 | switch (loop_mode) { | |
3696 | case HNAE3_MAC_INTER_LOOP_MAC: | |
3697 | req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; | |
3698 | /* 1 Read out the MAC mode config at first */ | |
3699 | hclge_cmd_setup_basic_desc(&desc, | |
3700 | HCLGE_OPC_CONFIG_MAC_MODE, | |
3701 | true); | |
3702 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3703 | if (ret) { | |
3704 | dev_err(&hdev->pdev->dev, | |
3705 | "mac loopback get fail, ret =%d.\n", | |
3706 | ret); | |
3707 | return ret; | |
3708 | } | |
3709 | ||
3710 | /* 2 Then setup the loopback flag */ | |
3711 | loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); | |
3712 | if (en) | |
3713 | hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1); | |
3714 | else | |
3715 | hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); | |
3716 | ||
3717 | req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); | |
3718 | ||
3719 | /* 3 Config mac work mode with loopback flag | |
3720 | * and its original configure parameters | |
3721 | */ | |
3722 | hclge_cmd_reuse_desc(&desc, false); | |
3723 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3724 | if (ret) | |
3725 | dev_err(&hdev->pdev->dev, | |
3726 | "mac loopback set fail, ret =%d.\n", ret); | |
3727 | break; | |
3728 | default: | |
3729 | ret = -ENOTSUPP; | |
3730 | dev_err(&hdev->pdev->dev, | |
3731 | "loop_mode %d is not supported\n", loop_mode); | |
3732 | break; | |
3733 | } | |
3734 | ||
3735 | return ret; | |
3736 | } | |
3737 | ||
46a3df9f S |
3738 | static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id, |
3739 | int stream_id, bool enable) | |
3740 | { | |
3741 | struct hclge_desc desc; | |
d44f9b63 YL |
3742 | struct hclge_cfg_com_tqp_queue_cmd *req = |
3743 | (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; | |
46a3df9f S |
3744 | int ret; |
3745 | ||
3746 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); | |
3747 | req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK); | |
3748 | req->stream_id = cpu_to_le16(stream_id); | |
3749 | req->enable |= enable << HCLGE_TQP_ENABLE_B; | |
3750 | ||
3751 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3752 | if (ret) | |
3753 | dev_err(&hdev->pdev->dev, | |
3754 | "Tqp enable fail, status =%d.\n", ret); | |
3755 | return ret; | |
3756 | } | |
3757 | ||
3758 | static void hclge_reset_tqp_stats(struct hnae3_handle *handle) | |
3759 | { | |
3760 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3761 | struct hnae3_queue *queue; | |
3762 | struct hclge_tqp *tqp; | |
3763 | int i; | |
3764 | ||
3765 | for (i = 0; i < vport->alloc_tqps; i++) { | |
3766 | queue = handle->kinfo.tqp[i]; | |
3767 | tqp = container_of(queue, struct hclge_tqp, q); | |
3768 | memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); | |
3769 | } | |
3770 | } | |
3771 | ||
3772 | static int hclge_ae_start(struct hnae3_handle *handle) | |
3773 | { | |
3774 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3775 | struct hclge_dev *hdev = vport->back; | |
e5e89cda | 3776 | int i, ret; |
46a3df9f | 3777 | |
e5e89cda PL |
3778 | for (i = 0; i < vport->alloc_tqps; i++) |
3779 | hclge_tqp_enable(hdev, i, 0, true); | |
46a3df9f | 3780 | |
46a3df9f S |
3781 | /* mac enable */ |
3782 | hclge_cfg_mac_mode(hdev, true); | |
3783 | clear_bit(HCLGE_STATE_DOWN, &hdev->state); | |
d039ef68 | 3784 | mod_timer(&hdev->service_timer, jiffies + HZ); |
46a3df9f | 3785 | |
f9637cc2 PL |
3786 | /* reset tqp stats */ |
3787 | hclge_reset_tqp_stats(handle); | |
3788 | ||
3789 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) | |
3790 | return 0; | |
3791 | ||
46a3df9f S |
3792 | ret = hclge_mac_start_phy(hdev); |
3793 | if (ret) | |
3794 | return ret; | |
3795 | ||
46a3df9f S |
3796 | return 0; |
3797 | } | |
3798 | ||
3799 | static void hclge_ae_stop(struct hnae3_handle *handle) | |
3800 | { | |
3801 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3802 | struct hclge_dev *hdev = vport->back; | |
e5e89cda | 3803 | int i; |
46a3df9f | 3804 | |
f9637cc2 PL |
3805 | del_timer_sync(&hdev->service_timer); |
3806 | cancel_work_sync(&hdev->service_task); | |
3807 | ||
3808 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) | |
3809 | return; | |
3810 | ||
e5e89cda PL |
3811 | for (i = 0; i < vport->alloc_tqps; i++) |
3812 | hclge_tqp_enable(hdev, i, 0, false); | |
46a3df9f | 3813 | |
46a3df9f S |
3814 | /* Mac disable */ |
3815 | hclge_cfg_mac_mode(hdev, false); | |
3816 | ||
3817 | hclge_mac_stop_phy(hdev); | |
3818 | ||
3819 | /* reset tqp stats */ | |
3820 | hclge_reset_tqp_stats(handle); | |
d14992df | 3821 | hclge_update_link_status(hdev); |
46a3df9f S |
3822 | } |
3823 | ||
3824 | static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, | |
3825 | u16 cmdq_resp, u8 resp_code, | |
3826 | enum hclge_mac_vlan_tbl_opcode op) | |
3827 | { | |
3828 | struct hclge_dev *hdev = vport->back; | |
3829 | int return_status = -EIO; | |
3830 | ||
3831 | if (cmdq_resp) { | |
3832 | dev_err(&hdev->pdev->dev, | |
3833 | "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n", | |
3834 | cmdq_resp); | |
3835 | return -EIO; | |
3836 | } | |
3837 | ||
3838 | if (op == HCLGE_MAC_VLAN_ADD) { | |
3839 | if ((!resp_code) || (resp_code == 1)) { | |
3840 | return_status = 0; | |
3841 | } else if (resp_code == 2) { | |
2f894c5b | 3842 | return_status = -ENOSPC; |
46a3df9f S |
3843 | dev_err(&hdev->pdev->dev, |
3844 | "add mac addr failed for uc_overflow.\n"); | |
3845 | } else if (resp_code == 3) { | |
2f894c5b | 3846 | return_status = -ENOSPC; |
46a3df9f S |
3847 | dev_err(&hdev->pdev->dev, |
3848 | "add mac addr failed for mc_overflow.\n"); | |
3849 | } else { | |
3850 | dev_err(&hdev->pdev->dev, | |
3851 | "add mac addr failed for undefined, code=%d.\n", | |
3852 | resp_code); | |
3853 | } | |
3854 | } else if (op == HCLGE_MAC_VLAN_REMOVE) { | |
3855 | if (!resp_code) { | |
3856 | return_status = 0; | |
3857 | } else if (resp_code == 1) { | |
2f894c5b | 3858 | return_status = -ENOENT; |
46a3df9f S |
3859 | dev_dbg(&hdev->pdev->dev, |
3860 | "remove mac addr failed for miss.\n"); | |
3861 | } else { | |
3862 | dev_err(&hdev->pdev->dev, | |
3863 | "remove mac addr failed for undefined, code=%d.\n", | |
3864 | resp_code); | |
3865 | } | |
3866 | } else if (op == HCLGE_MAC_VLAN_LKUP) { | |
3867 | if (!resp_code) { | |
3868 | return_status = 0; | |
3869 | } else if (resp_code == 1) { | |
2f894c5b | 3870 | return_status = -ENOENT; |
46a3df9f S |
3871 | dev_dbg(&hdev->pdev->dev, |
3872 | "lookup mac addr failed for miss.\n"); | |
3873 | } else { | |
3874 | dev_err(&hdev->pdev->dev, | |
3875 | "lookup mac addr failed for undefined, code=%d.\n", | |
3876 | resp_code); | |
3877 | } | |
3878 | } else { | |
2f894c5b | 3879 | return_status = -EINVAL; |
46a3df9f S |
3880 | dev_err(&hdev->pdev->dev, |
3881 | "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n", | |
3882 | op); | |
3883 | } | |
3884 | ||
3885 | return return_status; | |
3886 | } | |
3887 | ||
3888 | static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) | |
3889 | { | |
3890 | int word_num; | |
3891 | int bit_num; | |
3892 | ||
3893 | if (vfid > 255 || vfid < 0) | |
3894 | return -EIO; | |
3895 | ||
3896 | if (vfid >= 0 && vfid <= 191) { | |
3897 | word_num = vfid / 32; | |
3898 | bit_num = vfid % 32; | |
3899 | if (clr) | |
a90bb9a5 | 3900 | desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); |
46a3df9f | 3901 | else |
a90bb9a5 | 3902 | desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); |
46a3df9f S |
3903 | } else { |
3904 | word_num = (vfid - 192) / 32; | |
3905 | bit_num = vfid % 32; | |
3906 | if (clr) | |
a90bb9a5 | 3907 | desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); |
46a3df9f | 3908 | else |
a90bb9a5 | 3909 | desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); |
46a3df9f S |
3910 | } |
3911 | ||
3912 | return 0; | |
3913 | } | |
3914 | ||
3915 | static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) | |
3916 | { | |
3917 | #define HCLGE_DESC_NUMBER 3 | |
3918 | #define HCLGE_FUNC_NUMBER_PER_DESC 6 | |
3919 | int i, j; | |
3920 | ||
3921 | for (i = 0; i < HCLGE_DESC_NUMBER; i++) | |
3922 | for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) | |
3923 | if (desc[i].data[j]) | |
3924 | return false; | |
3925 | ||
3926 | return true; | |
3927 | } | |
3928 | ||
d44f9b63 | 3929 | static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, |
46a3df9f S |
3930 | const u8 *addr) |
3931 | { | |
3932 | const unsigned char *mac_addr = addr; | |
3933 | u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | | |
3934 | (mac_addr[0]) | (mac_addr[1] << 8); | |
3935 | u32 low_val = mac_addr[4] | (mac_addr[5] << 8); | |
3936 | ||
3937 | new_req->mac_addr_hi32 = cpu_to_le32(high_val); | |
3938 | new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); | |
3939 | } | |
3940 | ||
1db9b1bf YL |
3941 | static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport, |
3942 | const u8 *addr) | |
46a3df9f S |
3943 | { |
3944 | u16 high_val = addr[1] | (addr[0] << 8); | |
3945 | struct hclge_dev *hdev = vport->back; | |
3946 | u32 rsh = 4 - hdev->mta_mac_sel_type; | |
3947 | u16 ret_val = (high_val >> rsh) & 0xfff; | |
3948 | ||
3949 | return ret_val; | |
3950 | } | |
3951 | ||
3952 | static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, | |
3953 | enum hclge_mta_dmac_sel_type mta_mac_sel, | |
3954 | bool enable) | |
3955 | { | |
d44f9b63 | 3956 | struct hclge_mta_filter_mode_cmd *req; |
46a3df9f S |
3957 | struct hclge_desc desc; |
3958 | int ret; | |
3959 | ||
d44f9b63 | 3960 | req = (struct hclge_mta_filter_mode_cmd *)desc.data; |
46a3df9f S |
3961 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false); |
3962 | ||
3963 | hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B, | |
3964 | enable); | |
3965 | hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M, | |
3966 | HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel); | |
3967 | ||
3968 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3969 | if (ret) { | |
3970 | dev_err(&hdev->pdev->dev, | |
3971 | "Config mat filter mode failed for cmd_send, ret =%d.\n", | |
3972 | ret); | |
3973 | return ret; | |
3974 | } | |
3975 | ||
3976 | return 0; | |
3977 | } | |
3978 | ||
3979 | int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, | |
3980 | u8 func_id, | |
3981 | bool enable) | |
3982 | { | |
d44f9b63 | 3983 | struct hclge_cfg_func_mta_filter_cmd *req; |
46a3df9f S |
3984 | struct hclge_desc desc; |
3985 | int ret; | |
3986 | ||
d44f9b63 | 3987 | req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data; |
46a3df9f S |
3988 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false); |
3989 | ||
3990 | hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B, | |
3991 | enable); | |
3992 | req->function_id = func_id; | |
3993 | ||
3994 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3995 | if (ret) { | |
3996 | dev_err(&hdev->pdev->dev, | |
3997 | "Config func_id enable failed for cmd_send, ret =%d.\n", | |
3998 | ret); | |
3999 | return ret; | |
4000 | } | |
4001 | ||
4002 | return 0; | |
4003 | } | |
4004 | ||
4005 | static int hclge_set_mta_table_item(struct hclge_vport *vport, | |
4006 | u16 idx, | |
4007 | bool enable) | |
4008 | { | |
4009 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4010 | struct hclge_cfg_func_mta_item_cmd *req; |
46a3df9f | 4011 | struct hclge_desc desc; |
a90bb9a5 | 4012 | u16 item_idx = 0; |
46a3df9f S |
4013 | int ret; |
4014 | ||
d44f9b63 | 4015 | req = (struct hclge_cfg_func_mta_item_cmd *)desc.data; |
46a3df9f S |
4016 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false); |
4017 | hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable); | |
4018 | ||
a90bb9a5 | 4019 | hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M, |
46a3df9f | 4020 | HCLGE_CFG_MTA_ITEM_IDX_S, idx); |
a90bb9a5 | 4021 | req->item_idx = cpu_to_le16(item_idx); |
46a3df9f S |
4022 | |
4023 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4024 | if (ret) { | |
4025 | dev_err(&hdev->pdev->dev, | |
4026 | "Config mta table item failed for cmd_send, ret =%d.\n", | |
4027 | ret); | |
4028 | return ret; | |
4029 | } | |
4030 | ||
4031 | return 0; | |
4032 | } | |
4033 | ||
4034 | static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, | |
d44f9b63 | 4035 | struct hclge_mac_vlan_tbl_entry_cmd *req) |
46a3df9f S |
4036 | { |
4037 | struct hclge_dev *hdev = vport->back; | |
4038 | struct hclge_desc desc; | |
4039 | u8 resp_code; | |
a90bb9a5 | 4040 | u16 retval; |
46a3df9f S |
4041 | int ret; |
4042 | ||
4043 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); | |
4044 | ||
d44f9b63 | 4045 | memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f S |
4046 | |
4047 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4048 | if (ret) { | |
4049 | dev_err(&hdev->pdev->dev, | |
4050 | "del mac addr failed for cmd_send, ret =%d.\n", | |
4051 | ret); | |
4052 | return ret; | |
4053 | } | |
a90bb9a5 YL |
4054 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; |
4055 | retval = le16_to_cpu(desc.retval); | |
46a3df9f | 4056 | |
a90bb9a5 | 4057 | return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, |
46a3df9f S |
4058 | HCLGE_MAC_VLAN_REMOVE); |
4059 | } | |
4060 | ||
4061 | static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, | |
d44f9b63 | 4062 | struct hclge_mac_vlan_tbl_entry_cmd *req, |
46a3df9f S |
4063 | struct hclge_desc *desc, |
4064 | bool is_mc) | |
4065 | { | |
4066 | struct hclge_dev *hdev = vport->back; | |
4067 | u8 resp_code; | |
a90bb9a5 | 4068 | u16 retval; |
46a3df9f S |
4069 | int ret; |
4070 | ||
4071 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); | |
4072 | if (is_mc) { | |
4073 | desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
4074 | memcpy(desc[0].data, | |
4075 | req, | |
d44f9b63 | 4076 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f S |
4077 | hclge_cmd_setup_basic_desc(&desc[1], |
4078 | HCLGE_OPC_MAC_VLAN_ADD, | |
4079 | true); | |
4080 | desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
4081 | hclge_cmd_setup_basic_desc(&desc[2], | |
4082 | HCLGE_OPC_MAC_VLAN_ADD, | |
4083 | true); | |
4084 | ret = hclge_cmd_send(&hdev->hw, desc, 3); | |
4085 | } else { | |
4086 | memcpy(desc[0].data, | |
4087 | req, | |
d44f9b63 | 4088 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f S |
4089 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
4090 | } | |
4091 | if (ret) { | |
4092 | dev_err(&hdev->pdev->dev, | |
4093 | "lookup mac addr failed for cmd_send, ret =%d.\n", | |
4094 | ret); | |
4095 | return ret; | |
4096 | } | |
a90bb9a5 YL |
4097 | resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; |
4098 | retval = le16_to_cpu(desc[0].retval); | |
46a3df9f | 4099 | |
a90bb9a5 | 4100 | return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, |
46a3df9f S |
4101 | HCLGE_MAC_VLAN_LKUP); |
4102 | } | |
4103 | ||
4104 | static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, | |
d44f9b63 | 4105 | struct hclge_mac_vlan_tbl_entry_cmd *req, |
46a3df9f S |
4106 | struct hclge_desc *mc_desc) |
4107 | { | |
4108 | struct hclge_dev *hdev = vport->back; | |
4109 | int cfg_status; | |
4110 | u8 resp_code; | |
a90bb9a5 | 4111 | u16 retval; |
46a3df9f S |
4112 | int ret; |
4113 | ||
4114 | if (!mc_desc) { | |
4115 | struct hclge_desc desc; | |
4116 | ||
4117 | hclge_cmd_setup_basic_desc(&desc, | |
4118 | HCLGE_OPC_MAC_VLAN_ADD, | |
4119 | false); | |
d44f9b63 YL |
4120 | memcpy(desc.data, req, |
4121 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); | |
46a3df9f | 4122 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
a90bb9a5 YL |
4123 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; |
4124 | retval = le16_to_cpu(desc.retval); | |
4125 | ||
4126 | cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, | |
46a3df9f S |
4127 | resp_code, |
4128 | HCLGE_MAC_VLAN_ADD); | |
4129 | } else { | |
c3b6f755 | 4130 | hclge_cmd_reuse_desc(&mc_desc[0], false); |
46a3df9f | 4131 | mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
c3b6f755 | 4132 | hclge_cmd_reuse_desc(&mc_desc[1], false); |
46a3df9f | 4133 | mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
c3b6f755 | 4134 | hclge_cmd_reuse_desc(&mc_desc[2], false); |
46a3df9f S |
4135 | mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT); |
4136 | memcpy(mc_desc[0].data, req, | |
d44f9b63 | 4137 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f | 4138 | ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); |
a90bb9a5 YL |
4139 | resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; |
4140 | retval = le16_to_cpu(mc_desc[0].retval); | |
4141 | ||
4142 | cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, | |
46a3df9f S |
4143 | resp_code, |
4144 | HCLGE_MAC_VLAN_ADD); | |
4145 | } | |
4146 | ||
4147 | if (ret) { | |
4148 | dev_err(&hdev->pdev->dev, | |
4149 | "add mac addr failed for cmd_send, ret =%d.\n", | |
4150 | ret); | |
4151 | return ret; | |
4152 | } | |
4153 | ||
4154 | return cfg_status; | |
4155 | } | |
4156 | ||
4157 | static int hclge_add_uc_addr(struct hnae3_handle *handle, | |
4158 | const unsigned char *addr) | |
4159 | { | |
4160 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4161 | ||
4162 | return hclge_add_uc_addr_common(vport, addr); | |
4163 | } | |
4164 | ||
4165 | int hclge_add_uc_addr_common(struct hclge_vport *vport, | |
4166 | const unsigned char *addr) | |
4167 | { | |
4168 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4169 | struct hclge_mac_vlan_tbl_entry_cmd req; |
bf88f41f | 4170 | struct hclge_desc desc; |
a90bb9a5 | 4171 | u16 egress_port = 0; |
04f0c72a | 4172 | int ret; |
46a3df9f S |
4173 | |
4174 | /* mac addr check */ | |
4175 | if (is_zero_ether_addr(addr) || | |
4176 | is_broadcast_ether_addr(addr) || | |
4177 | is_multicast_ether_addr(addr)) { | |
4178 | dev_err(&hdev->pdev->dev, | |
4179 | "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n", | |
4180 | addr, | |
4181 | is_zero_ether_addr(addr), | |
4182 | is_broadcast_ether_addr(addr), | |
4183 | is_multicast_ether_addr(addr)); | |
4184 | return -EINVAL; | |
4185 | } | |
4186 | ||
4187 | memset(&req, 0, sizeof(req)); | |
4188 | hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); | |
4189 | hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
4190 | hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0); | |
4191 | hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
a90bb9a5 YL |
4192 | |
4193 | hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0); | |
4194 | hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0); | |
4195 | hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, | |
46a3df9f | 4196 | HCLGE_MAC_EPORT_VFID_S, vport->vport_id); |
a90bb9a5 | 4197 | hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M, |
46a3df9f | 4198 | HCLGE_MAC_EPORT_PFID_S, 0); |
a90bb9a5 YL |
4199 | |
4200 | req.egress_port = cpu_to_le16(egress_port); | |
46a3df9f S |
4201 | |
4202 | hclge_prepare_mac_addr(&req, addr); | |
4203 | ||
bf88f41f JS |
4204 | /* Lookup the mac address in the mac_vlan table, and add |
4205 | * it if the entry is inexistent. Repeated unicast entry | |
4206 | * is not allowed in the mac vlan table. | |
4207 | */ | |
4208 | ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); | |
4209 | if (ret == -ENOENT) | |
4210 | return hclge_add_mac_vlan_tbl(vport, &req, NULL); | |
4211 | ||
4212 | /* check if we just hit the duplicate */ | |
4213 | if (!ret) | |
4214 | ret = -EINVAL; | |
4215 | ||
4216 | dev_err(&hdev->pdev->dev, | |
4217 | "PF failed to add unicast entry(%pM) in the MAC table\n", | |
4218 | addr); | |
46a3df9f | 4219 | |
04f0c72a | 4220 | return ret; |
46a3df9f S |
4221 | } |
4222 | ||
4223 | static int hclge_rm_uc_addr(struct hnae3_handle *handle, | |
4224 | const unsigned char *addr) | |
4225 | { | |
4226 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4227 | ||
4228 | return hclge_rm_uc_addr_common(vport, addr); | |
4229 | } | |
4230 | ||
4231 | int hclge_rm_uc_addr_common(struct hclge_vport *vport, | |
4232 | const unsigned char *addr) | |
4233 | { | |
4234 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4235 | struct hclge_mac_vlan_tbl_entry_cmd req; |
04f0c72a | 4236 | int ret; |
46a3df9f S |
4237 | |
4238 | /* mac addr check */ | |
4239 | if (is_zero_ether_addr(addr) || | |
4240 | is_broadcast_ether_addr(addr) || | |
4241 | is_multicast_ether_addr(addr)) { | |
4242 | dev_dbg(&hdev->pdev->dev, | |
4243 | "Remove mac err! invalid mac:%pM.\n", | |
4244 | addr); | |
4245 | return -EINVAL; | |
4246 | } | |
4247 | ||
4248 | memset(&req, 0, sizeof(req)); | |
4249 | hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); | |
4250 | hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
4251 | hclge_prepare_mac_addr(&req, addr); | |
04f0c72a | 4252 | ret = hclge_remove_mac_vlan_tbl(vport, &req); |
46a3df9f | 4253 | |
04f0c72a | 4254 | return ret; |
46a3df9f S |
4255 | } |
4256 | ||
4257 | static int hclge_add_mc_addr(struct hnae3_handle *handle, | |
4258 | const unsigned char *addr) | |
4259 | { | |
4260 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4261 | ||
4262 | return hclge_add_mc_addr_common(vport, addr); | |
4263 | } | |
4264 | ||
4265 | int hclge_add_mc_addr_common(struct hclge_vport *vport, | |
4266 | const unsigned char *addr) | |
4267 | { | |
4268 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4269 | struct hclge_mac_vlan_tbl_entry_cmd req; |
46a3df9f S |
4270 | struct hclge_desc desc[3]; |
4271 | u16 tbl_idx; | |
4272 | int status; | |
4273 | ||
4274 | /* mac addr check */ | |
4275 | if (!is_multicast_ether_addr(addr)) { | |
4276 | dev_err(&hdev->pdev->dev, | |
4277 | "Add mc mac err! invalid mac:%pM.\n", | |
4278 | addr); | |
4279 | return -EINVAL; | |
4280 | } | |
4281 | memset(&req, 0, sizeof(req)); | |
4282 | hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); | |
4283 | hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
4284 | hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); | |
4285 | hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
4286 | hclge_prepare_mac_addr(&req, addr); | |
4287 | status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); | |
4288 | if (!status) { | |
4289 | /* This mac addr exist, update VFID for it */ | |
4290 | hclge_update_desc_vfid(desc, vport->vport_id, false); | |
4291 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); | |
4292 | } else { | |
4293 | /* This mac addr do not exist, add new entry for it */ | |
4294 | memset(desc[0].data, 0, sizeof(desc[0].data)); | |
4295 | memset(desc[1].data, 0, sizeof(desc[0].data)); | |
4296 | memset(desc[2].data, 0, sizeof(desc[0].data)); | |
4297 | hclge_update_desc_vfid(desc, vport->vport_id, false); | |
4298 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); | |
4299 | } | |
4300 | ||
4301 | /* Set MTA table for this MAC address */ | |
4302 | tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); | |
4303 | status = hclge_set_mta_table_item(vport, tbl_idx, true); | |
4304 | ||
4305 | return status; | |
4306 | } | |
4307 | ||
4308 | static int hclge_rm_mc_addr(struct hnae3_handle *handle, | |
4309 | const unsigned char *addr) | |
4310 | { | |
4311 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4312 | ||
4313 | return hclge_rm_mc_addr_common(vport, addr); | |
4314 | } | |
4315 | ||
4316 | int hclge_rm_mc_addr_common(struct hclge_vport *vport, | |
4317 | const unsigned char *addr) | |
4318 | { | |
4319 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4320 | struct hclge_mac_vlan_tbl_entry_cmd req; |
46a3df9f S |
4321 | enum hclge_cmd_status status; |
4322 | struct hclge_desc desc[3]; | |
4323 | u16 tbl_idx; | |
4324 | ||
4325 | /* mac addr check */ | |
4326 | if (!is_multicast_ether_addr(addr)) { | |
4327 | dev_dbg(&hdev->pdev->dev, | |
4328 | "Remove mc mac err! invalid mac:%pM.\n", | |
4329 | addr); | |
4330 | return -EINVAL; | |
4331 | } | |
4332 | ||
4333 | memset(&req, 0, sizeof(req)); | |
4334 | hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); | |
4335 | hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
4336 | hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); | |
4337 | hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
4338 | hclge_prepare_mac_addr(&req, addr); | |
4339 | status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); | |
4340 | if (!status) { | |
4341 | /* This mac addr exist, remove this handle's VFID for it */ | |
4342 | hclge_update_desc_vfid(desc, vport->vport_id, true); | |
4343 | ||
4344 | if (hclge_is_all_function_id_zero(desc)) | |
4345 | /* All the vfid is zero, so need to delete this entry */ | |
4346 | status = hclge_remove_mac_vlan_tbl(vport, &req); | |
4347 | else | |
4348 | /* Not all the vfid is zero, update the vfid */ | |
4349 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); | |
4350 | ||
4351 | } else { | |
4352 | /* This mac addr do not exist, can't delete it */ | |
4353 | dev_err(&hdev->pdev->dev, | |
d7629e74 | 4354 | "Rm multicast mac addr failed, ret = %d.\n", |
46a3df9f S |
4355 | status); |
4356 | return -EIO; | |
4357 | } | |
4358 | ||
4359 | /* Set MTB table for this MAC address */ | |
4360 | tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); | |
4361 | status = hclge_set_mta_table_item(vport, tbl_idx, false); | |
4362 | ||
4363 | return status; | |
4364 | } | |
4365 | ||
635bfb58 FL |
4366 | static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, |
4367 | u16 cmdq_resp, u8 resp_code) | |
4368 | { | |
4369 | #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 | |
4370 | #define HCLGE_ETHERTYPE_ALREADY_ADD 1 | |
4371 | #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 | |
4372 | #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 | |
4373 | ||
4374 | int return_status; | |
4375 | ||
4376 | if (cmdq_resp) { | |
4377 | dev_err(&hdev->pdev->dev, | |
4378 | "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", | |
4379 | cmdq_resp); | |
4380 | return -EIO; | |
4381 | } | |
4382 | ||
4383 | switch (resp_code) { | |
4384 | case HCLGE_ETHERTYPE_SUCCESS_ADD: | |
4385 | case HCLGE_ETHERTYPE_ALREADY_ADD: | |
4386 | return_status = 0; | |
4387 | break; | |
4388 | case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: | |
4389 | dev_err(&hdev->pdev->dev, | |
4390 | "add mac ethertype failed for manager table overflow.\n"); | |
4391 | return_status = -EIO; | |
4392 | break; | |
4393 | case HCLGE_ETHERTYPE_KEY_CONFLICT: | |
4394 | dev_err(&hdev->pdev->dev, | |
4395 | "add mac ethertype failed for key conflict.\n"); | |
4396 | return_status = -EIO; | |
4397 | break; | |
4398 | default: | |
4399 | dev_err(&hdev->pdev->dev, | |
4400 | "add mac ethertype failed for undefined, code=%d.\n", | |
4401 | resp_code); | |
4402 | return_status = -EIO; | |
4403 | } | |
4404 | ||
4405 | return return_status; | |
4406 | } | |
4407 | ||
4408 | static int hclge_add_mgr_tbl(struct hclge_dev *hdev, | |
4409 | const struct hclge_mac_mgr_tbl_entry_cmd *req) | |
4410 | { | |
4411 | struct hclge_desc desc; | |
4412 | u8 resp_code; | |
4413 | u16 retval; | |
4414 | int ret; | |
4415 | ||
4416 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); | |
4417 | memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); | |
4418 | ||
4419 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4420 | if (ret) { | |
4421 | dev_err(&hdev->pdev->dev, | |
4422 | "add mac ethertype failed for cmd_send, ret =%d.\n", | |
4423 | ret); | |
4424 | return ret; | |
4425 | } | |
4426 | ||
4427 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; | |
4428 | retval = le16_to_cpu(desc.retval); | |
4429 | ||
4430 | return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); | |
4431 | } | |
4432 | ||
4433 | static int init_mgr_tbl(struct hclge_dev *hdev) | |
4434 | { | |
4435 | int ret; | |
4436 | int i; | |
4437 | ||
4438 | for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { | |
4439 | ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); | |
4440 | if (ret) { | |
4441 | dev_err(&hdev->pdev->dev, | |
4442 | "add mac ethertype failed, ret =%d.\n", | |
4443 | ret); | |
4444 | return ret; | |
4445 | } | |
4446 | } | |
4447 | ||
4448 | return 0; | |
4449 | } | |
4450 | ||
46a3df9f S |
4451 | static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) |
4452 | { | |
4453 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4454 | struct hclge_dev *hdev = vport->back; | |
4455 | ||
4456 | ether_addr_copy(p, hdev->hw.mac.mac_addr); | |
4457 | } | |
4458 | ||
3cbf5e2d FL |
4459 | static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p, |
4460 | bool is_first) | |
46a3df9f S |
4461 | { |
4462 | const unsigned char *new_addr = (const unsigned char *)p; | |
4463 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4464 | struct hclge_dev *hdev = vport->back; | |
20a5c4c0 | 4465 | int ret; |
46a3df9f S |
4466 | |
4467 | /* mac addr check */ | |
4468 | if (is_zero_ether_addr(new_addr) || | |
4469 | is_broadcast_ether_addr(new_addr) || | |
4470 | is_multicast_ether_addr(new_addr)) { | |
4471 | dev_err(&hdev->pdev->dev, | |
4472 | "Change uc mac err! invalid mac:%p.\n", | |
4473 | new_addr); | |
4474 | return -EINVAL; | |
4475 | } | |
4476 | ||
3cbf5e2d | 4477 | if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr)) |
20a5c4c0 | 4478 | dev_warn(&hdev->pdev->dev, |
3cbf5e2d | 4479 | "remove old uc mac address fail.\n"); |
46a3df9f | 4480 | |
20a5c4c0 FL |
4481 | ret = hclge_add_uc_addr(handle, new_addr); |
4482 | if (ret) { | |
4483 | dev_err(&hdev->pdev->dev, | |
4484 | "add uc mac address fail, ret =%d.\n", | |
4485 | ret); | |
4486 | ||
3cbf5e2d FL |
4487 | if (!is_first && |
4488 | hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr)) | |
20a5c4c0 | 4489 | dev_err(&hdev->pdev->dev, |
3cbf5e2d | 4490 | "restore uc mac address fail.\n"); |
20a5c4c0 FL |
4491 | |
4492 | return -EIO; | |
46a3df9f S |
4493 | } |
4494 | ||
532fdd5e | 4495 | ret = hclge_pause_addr_cfg(hdev, new_addr); |
20a5c4c0 FL |
4496 | if (ret) { |
4497 | dev_err(&hdev->pdev->dev, | |
4498 | "configure mac pause address fail, ret =%d.\n", | |
4499 | ret); | |
4500 | return -EIO; | |
4501 | } | |
4502 | ||
4503 | ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); | |
4504 | ||
4505 | return 0; | |
46a3df9f S |
4506 | } |
4507 | ||
4508 | static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, | |
4509 | bool filter_en) | |
4510 | { | |
d44f9b63 | 4511 | struct hclge_vlan_filter_ctrl_cmd *req; |
46a3df9f S |
4512 | struct hclge_desc desc; |
4513 | int ret; | |
4514 | ||
4515 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false); | |
4516 | ||
d44f9b63 | 4517 | req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; |
46a3df9f S |
4518 | req->vlan_type = vlan_type; |
4519 | req->vlan_fe = filter_en; | |
4520 | ||
4521 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4522 | if (ret) { | |
4523 | dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n", | |
4524 | ret); | |
4525 | return ret; | |
4526 | } | |
4527 | ||
4528 | return 0; | |
4529 | } | |
4530 | ||
d818396d JS |
4531 | #define HCLGE_FILTER_TYPE_VF 0 |
4532 | #define HCLGE_FILTER_TYPE_PORT 1 | |
4533 | ||
4534 | static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) | |
4535 | { | |
4536 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4537 | struct hclge_dev *hdev = vport->back; | |
4538 | ||
4539 | hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable); | |
4540 | } | |
4541 | ||
4e66632d YL |
4542 | static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid, |
4543 | bool is_kill, u16 vlan, u8 qos, | |
4544 | __be16 proto) | |
46a3df9f S |
4545 | { |
4546 | #define HCLGE_MAX_VF_BYTES 16 | |
d44f9b63 YL |
4547 | struct hclge_vlan_filter_vf_cfg_cmd *req0; |
4548 | struct hclge_vlan_filter_vf_cfg_cmd *req1; | |
46a3df9f S |
4549 | struct hclge_desc desc[2]; |
4550 | u8 vf_byte_val; | |
4551 | u8 vf_byte_off; | |
4552 | int ret; | |
4553 | ||
4554 | hclge_cmd_setup_basic_desc(&desc[0], | |
4555 | HCLGE_OPC_VLAN_FILTER_VF_CFG, false); | |
4556 | hclge_cmd_setup_basic_desc(&desc[1], | |
4557 | HCLGE_OPC_VLAN_FILTER_VF_CFG, false); | |
4558 | ||
4559 | desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
4560 | ||
4561 | vf_byte_off = vfid / 8; | |
4562 | vf_byte_val = 1 << (vfid % 8); | |
4563 | ||
d44f9b63 YL |
4564 | req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; |
4565 | req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; | |
46a3df9f | 4566 | |
a90bb9a5 | 4567 | req0->vlan_id = cpu_to_le16(vlan); |
46a3df9f S |
4568 | req0->vlan_cfg = is_kill; |
4569 | ||
4570 | if (vf_byte_off < HCLGE_MAX_VF_BYTES) | |
4571 | req0->vf_bitmap[vf_byte_off] = vf_byte_val; | |
4572 | else | |
4573 | req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; | |
4574 | ||
4575 | ret = hclge_cmd_send(&hdev->hw, desc, 2); | |
4576 | if (ret) { | |
4577 | dev_err(&hdev->pdev->dev, | |
4578 | "Send vf vlan command fail, ret =%d.\n", | |
4579 | ret); | |
4580 | return ret; | |
4581 | } | |
4582 | ||
4583 | if (!is_kill) { | |
4584 | if (!req0->resp_code || req0->resp_code == 1) | |
4585 | return 0; | |
4586 | ||
4587 | dev_err(&hdev->pdev->dev, | |
4588 | "Add vf vlan filter fail, ret =%d.\n", | |
4589 | req0->resp_code); | |
4590 | } else { | |
4591 | if (!req0->resp_code) | |
4592 | return 0; | |
4593 | ||
4594 | dev_err(&hdev->pdev->dev, | |
4595 | "Kill vf vlan filter fail, ret =%d.\n", | |
4596 | req0->resp_code); | |
4597 | } | |
4598 | ||
4599 | return -EIO; | |
4600 | } | |
4601 | ||
4e66632d YL |
4602 | static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, |
4603 | u16 vlan_id, bool is_kill) | |
46a3df9f | 4604 | { |
d44f9b63 | 4605 | struct hclge_vlan_filter_pf_cfg_cmd *req; |
46a3df9f S |
4606 | struct hclge_desc desc; |
4607 | u8 vlan_offset_byte_val; | |
4608 | u8 vlan_offset_byte; | |
4609 | u8 vlan_offset_160; | |
4610 | int ret; | |
4611 | ||
4612 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); | |
4613 | ||
4614 | vlan_offset_160 = vlan_id / 160; | |
4615 | vlan_offset_byte = (vlan_id % 160) / 8; | |
4616 | vlan_offset_byte_val = 1 << (vlan_id % 8); | |
4617 | ||
d44f9b63 | 4618 | req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; |
46a3df9f S |
4619 | req->vlan_offset = vlan_offset_160; |
4620 | req->vlan_cfg = is_kill; | |
4621 | req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; | |
4622 | ||
4623 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4e66632d YL |
4624 | if (ret) |
4625 | dev_err(&hdev->pdev->dev, | |
4626 | "port vlan command, send fail, ret =%d.\n", ret); | |
4627 | return ret; | |
4628 | } | |
4629 | ||
4630 | static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, | |
4631 | u16 vport_id, u16 vlan_id, u8 qos, | |
4632 | bool is_kill) | |
4633 | { | |
4634 | u16 vport_idx, vport_num = 0; | |
4635 | int ret; | |
4636 | ||
4637 | ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id, | |
4638 | 0, proto); | |
46a3df9f S |
4639 | if (ret) { |
4640 | dev_err(&hdev->pdev->dev, | |
4e66632d YL |
4641 | "Set %d vport vlan filter config fail, ret =%d.\n", |
4642 | vport_id, ret); | |
46a3df9f S |
4643 | return ret; |
4644 | } | |
4645 | ||
4e66632d YL |
4646 | /* vlan 0 may be added twice when 8021q module is enabled */ |
4647 | if (!is_kill && !vlan_id && | |
4648 | test_bit(vport_id, hdev->vlan_table[vlan_id])) | |
4649 | return 0; | |
4650 | ||
4651 | if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { | |
46a3df9f | 4652 | dev_err(&hdev->pdev->dev, |
4e66632d YL |
4653 | "Add port vlan failed, vport %d is already in vlan %d\n", |
4654 | vport_id, vlan_id); | |
4655 | return -EINVAL; | |
46a3df9f S |
4656 | } |
4657 | ||
4e66632d YL |
4658 | if (is_kill && |
4659 | !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { | |
4660 | dev_err(&hdev->pdev->dev, | |
4661 | "Delete port vlan failed, vport %d is not in vlan %d\n", | |
4662 | vport_id, vlan_id); | |
4663 | return -EINVAL; | |
4664 | } | |
4665 | ||
4666 | for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID) | |
4667 | vport_num++; | |
4668 | ||
4669 | if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) | |
4670 | ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, | |
4671 | is_kill); | |
4672 | ||
4673 | return ret; | |
4674 | } | |
4675 | ||
4676 | int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, | |
4677 | u16 vlan_id, bool is_kill) | |
4678 | { | |
4679 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4680 | struct hclge_dev *hdev = vport->back; | |
4681 | ||
4682 | return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id, | |
4683 | 0, is_kill); | |
46a3df9f S |
4684 | } |
4685 | ||
4686 | static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, | |
4687 | u16 vlan, u8 qos, __be16 proto) | |
4688 | { | |
4689 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4690 | struct hclge_dev *hdev = vport->back; | |
4691 | ||
4692 | if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7)) | |
4693 | return -EINVAL; | |
4694 | if (proto != htons(ETH_P_8021Q)) | |
4695 | return -EPROTONOSUPPORT; | |
4696 | ||
4e66632d | 4697 | return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false); |
46a3df9f S |
4698 | } |
4699 | ||
e62f2a6b PL |
4700 | static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) |
4701 | { | |
4702 | struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; | |
4703 | struct hclge_vport_vtag_tx_cfg_cmd *req; | |
4704 | struct hclge_dev *hdev = vport->back; | |
4705 | struct hclge_desc desc; | |
4706 | int status; | |
4707 | ||
4708 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); | |
4709 | ||
4710 | req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; | |
4711 | req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); | |
4712 | req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); | |
4713 | hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B, | |
4714 | vcfg->accept_tag ? 1 : 0); | |
4715 | hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B, | |
4716 | vcfg->accept_untag ? 1 : 0); | |
4717 | hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, | |
4718 | vcfg->insert_tag1_en ? 1 : 0); | |
4719 | hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, | |
4720 | vcfg->insert_tag2_en ? 1 : 0); | |
4721 | hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); | |
4722 | ||
4723 | req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; | |
4724 | req->vf_bitmap[req->vf_offset] = | |
4725 | 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); | |
4726 | ||
4727 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4728 | if (status) | |
4729 | dev_err(&hdev->pdev->dev, | |
4730 | "Send port txvlan cfg command fail, ret =%d\n", | |
4731 | status); | |
4732 | ||
4733 | return status; | |
4734 | } | |
4735 | ||
4736 | static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) | |
4737 | { | |
4738 | struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; | |
4739 | struct hclge_vport_vtag_rx_cfg_cmd *req; | |
4740 | struct hclge_dev *hdev = vport->back; | |
4741 | struct hclge_desc desc; | |
4742 | int status; | |
4743 | ||
4744 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); | |
4745 | ||
4746 | req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; | |
4747 | hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, | |
4748 | vcfg->strip_tag1_en ? 1 : 0); | |
4749 | hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, | |
4750 | vcfg->strip_tag2_en ? 1 : 0); | |
4751 | hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, | |
4752 | vcfg->vlan1_vlan_prionly ? 1 : 0); | |
4753 | hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, | |
4754 | vcfg->vlan2_vlan_prionly ? 1 : 0); | |
4755 | ||
4756 | req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; | |
4757 | req->vf_bitmap[req->vf_offset] = | |
4758 | 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); | |
4759 | ||
4760 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4761 | if (status) | |
4762 | dev_err(&hdev->pdev->dev, | |
4763 | "Send port rxvlan cfg command fail, ret =%d\n", | |
4764 | status); | |
4765 | ||
4766 | return status; | |
4767 | } | |
4768 | ||
4769 | static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) | |
4770 | { | |
4771 | struct hclge_rx_vlan_type_cfg_cmd *rx_req; | |
4772 | struct hclge_tx_vlan_type_cfg_cmd *tx_req; | |
4773 | struct hclge_desc desc; | |
4774 | int status; | |
4775 | ||
4776 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); | |
4777 | rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; | |
4778 | rx_req->ot_fst_vlan_type = | |
4779 | cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); | |
4780 | rx_req->ot_sec_vlan_type = | |
4781 | cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); | |
4782 | rx_req->in_fst_vlan_type = | |
4783 | cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); | |
4784 | rx_req->in_sec_vlan_type = | |
4785 | cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); | |
4786 | ||
4787 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4788 | if (status) { | |
4789 | dev_err(&hdev->pdev->dev, | |
4790 | "Send rxvlan protocol type command fail, ret =%d\n", | |
4791 | status); | |
4792 | return status; | |
4793 | } | |
4794 | ||
4795 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); | |
4796 | ||
4797 | tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data; | |
4798 | tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); | |
4799 | tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); | |
4800 | ||
4801 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4802 | if (status) | |
4803 | dev_err(&hdev->pdev->dev, | |
4804 | "Send txvlan protocol type command fail, ret =%d\n", | |
4805 | status); | |
4806 | ||
4807 | return status; | |
4808 | } | |
4809 | ||
46a3df9f S |
4810 | static int hclge_init_vlan_config(struct hclge_dev *hdev) |
4811 | { | |
e62f2a6b PL |
4812 | #define HCLGE_DEF_VLAN_TYPE 0x8100 |
4813 | ||
5e43aef8 | 4814 | struct hnae3_handle *handle; |
e62f2a6b | 4815 | struct hclge_vport *vport; |
46a3df9f | 4816 | int ret; |
e62f2a6b PL |
4817 | int i; |
4818 | ||
4819 | ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true); | |
4820 | if (ret) | |
4821 | return ret; | |
46a3df9f | 4822 | |
e62f2a6b | 4823 | ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true); |
46a3df9f S |
4824 | if (ret) |
4825 | return ret; | |
4826 | ||
e62f2a6b PL |
4827 | hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; |
4828 | hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4829 | hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4830 | hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4831 | hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4832 | hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4833 | ||
4834 | ret = hclge_set_vlan_protocol_type(hdev); | |
5e43aef8 L |
4835 | if (ret) |
4836 | return ret; | |
46a3df9f | 4837 | |
e62f2a6b PL |
4838 | for (i = 0; i < hdev->num_alloc_vport; i++) { |
4839 | vport = &hdev->vport[i]; | |
4840 | vport->txvlan_cfg.accept_tag = true; | |
4841 | vport->txvlan_cfg.accept_untag = true; | |
4842 | vport->txvlan_cfg.insert_tag1_en = false; | |
4843 | vport->txvlan_cfg.insert_tag2_en = false; | |
4844 | vport->txvlan_cfg.default_tag1 = 0; | |
4845 | vport->txvlan_cfg.default_tag2 = 0; | |
4846 | ||
4847 | ret = hclge_set_vlan_tx_offload_cfg(vport); | |
4848 | if (ret) | |
4849 | return ret; | |
4850 | ||
4851 | vport->rxvlan_cfg.strip_tag1_en = false; | |
4852 | vport->rxvlan_cfg.strip_tag2_en = true; | |
4853 | vport->rxvlan_cfg.vlan1_vlan_prionly = false; | |
4854 | vport->rxvlan_cfg.vlan2_vlan_prionly = false; | |
4855 | ||
4856 | ret = hclge_set_vlan_rx_offload_cfg(vport); | |
4857 | if (ret) | |
4858 | return ret; | |
4859 | } | |
4860 | ||
5e43aef8 | 4861 | handle = &hdev->vport[0].nic; |
4e66632d | 4862 | return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); |
46a3df9f S |
4863 | } |
4864 | ||
3849d494 | 4865 | int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) |
5f9a7732 PL |
4866 | { |
4867 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4868 | ||
4869 | vport->rxvlan_cfg.strip_tag1_en = false; | |
4870 | vport->rxvlan_cfg.strip_tag2_en = enable; | |
4871 | vport->rxvlan_cfg.vlan1_vlan_prionly = false; | |
4872 | vport->rxvlan_cfg.vlan2_vlan_prionly = false; | |
4873 | ||
4874 | return hclge_set_vlan_rx_offload_cfg(vport); | |
4875 | } | |
4876 | ||
12341881 | 4877 | static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu) |
46a3df9f | 4878 | { |
d44f9b63 | 4879 | struct hclge_config_max_frm_size_cmd *req; |
46a3df9f | 4880 | struct hclge_desc desc; |
7393ed39 | 4881 | int max_frm_size; |
46a3df9f S |
4882 | int ret; |
4883 | ||
7393ed39 FL |
4884 | max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
4885 | ||
4886 | if (max_frm_size < HCLGE_MAC_MIN_FRAME || | |
4887 | max_frm_size > HCLGE_MAC_MAX_FRAME) | |
46a3df9f S |
4888 | return -EINVAL; |
4889 | ||
7393ed39 FL |
4890 | max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); |
4891 | ||
46a3df9f S |
4892 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); |
4893 | ||
d44f9b63 | 4894 | req = (struct hclge_config_max_frm_size_cmd *)desc.data; |
7393ed39 | 4895 | req->max_frm_size = cpu_to_le16(max_frm_size); |
46a3df9f S |
4896 | |
4897 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4898 | if (ret) { | |
4899 | dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret); | |
4900 | return ret; | |
4901 | } | |
4902 | ||
7393ed39 FL |
4903 | hdev->mps = max_frm_size; |
4904 | ||
46a3df9f S |
4905 | return 0; |
4906 | } | |
4907 | ||
12341881 FL |
4908 | static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) |
4909 | { | |
4910 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4911 | struct hclge_dev *hdev = vport->back; | |
4912 | int ret; | |
4913 | ||
4914 | ret = hclge_set_mac_mtu(hdev, new_mtu); | |
4915 | if (ret) { | |
4916 | dev_err(&hdev->pdev->dev, | |
4917 | "Change mtu fail, ret =%d\n", ret); | |
4918 | return ret; | |
4919 | } | |
4920 | ||
4921 | ret = hclge_buffer_alloc(hdev); | |
4922 | if (ret) | |
4923 | dev_err(&hdev->pdev->dev, | |
4924 | "Allocate buffer fail, ret =%d\n", ret); | |
4925 | ||
4926 | return ret; | |
4927 | } | |
4928 | ||
46a3df9f S |
4929 | static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id, |
4930 | bool enable) | |
4931 | { | |
d44f9b63 | 4932 | struct hclge_reset_tqp_queue_cmd *req; |
46a3df9f S |
4933 | struct hclge_desc desc; |
4934 | int ret; | |
4935 | ||
4936 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); | |
4937 | ||
d44f9b63 | 4938 | req = (struct hclge_reset_tqp_queue_cmd *)desc.data; |
46a3df9f S |
4939 | req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); |
4940 | hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable); | |
4941 | ||
4942 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4943 | if (ret) { | |
4944 | dev_err(&hdev->pdev->dev, | |
4945 | "Send tqp reset cmd error, status =%d\n", ret); | |
4946 | return ret; | |
4947 | } | |
4948 | ||
4949 | return 0; | |
4950 | } | |
4951 | ||
4952 | static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id) | |
4953 | { | |
d44f9b63 | 4954 | struct hclge_reset_tqp_queue_cmd *req; |
46a3df9f S |
4955 | struct hclge_desc desc; |
4956 | int ret; | |
4957 | ||
4958 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); | |
4959 | ||
d44f9b63 | 4960 | req = (struct hclge_reset_tqp_queue_cmd *)desc.data; |
46a3df9f S |
4961 | req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); |
4962 | ||
4963 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4964 | if (ret) { | |
4965 | dev_err(&hdev->pdev->dev, | |
4966 | "Get reset status error, status =%d\n", ret); | |
4967 | return ret; | |
4968 | } | |
4969 | ||
4970 | return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); | |
4971 | } | |
4972 | ||
e5e89cda PL |
4973 | static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, |
4974 | u16 queue_id) | |
4975 | { | |
4976 | struct hnae3_queue *queue; | |
4977 | struct hclge_tqp *tqp; | |
4978 | ||
4979 | queue = handle->kinfo.tqp[queue_id]; | |
4980 | tqp = container_of(queue, struct hclge_tqp, q); | |
4981 | ||
4982 | return tqp->index; | |
4983 | } | |
4984 | ||
63d7e66f | 4985 | void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id) |
46a3df9f S |
4986 | { |
4987 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4988 | struct hclge_dev *hdev = vport->back; | |
4989 | int reset_try_times = 0; | |
4990 | int reset_status; | |
e5e89cda | 4991 | u16 queue_gid; |
46a3df9f S |
4992 | int ret; |
4993 | ||
f9637cc2 PL |
4994 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) |
4995 | return; | |
4996 | ||
e5e89cda PL |
4997 | queue_gid = hclge_covert_handle_qid_global(handle, queue_id); |
4998 | ||
46a3df9f S |
4999 | ret = hclge_tqp_enable(hdev, queue_id, 0, false); |
5000 | if (ret) { | |
5001 | dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret); | |
5002 | return; | |
5003 | } | |
5004 | ||
e5e89cda | 5005 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); |
46a3df9f S |
5006 | if (ret) { |
5007 | dev_warn(&hdev->pdev->dev, | |
5008 | "Send reset tqp cmd fail, ret = %d\n", ret); | |
5009 | return; | |
5010 | } | |
5011 | ||
5012 | reset_try_times = 0; | |
5013 | while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { | |
5014 | /* Wait for tqp hw reset */ | |
5015 | msleep(20); | |
e5e89cda | 5016 | reset_status = hclge_get_reset_status(hdev, queue_gid); |
46a3df9f S |
5017 | if (reset_status) |
5018 | break; | |
5019 | } | |
5020 | ||
5021 | if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { | |
5022 | dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); | |
5023 | return; | |
5024 | } | |
5025 | ||
e5e89cda | 5026 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); |
46a3df9f S |
5027 | if (ret) { |
5028 | dev_warn(&hdev->pdev->dev, | |
5029 | "Deassert the soft reset fail, ret = %d\n", ret); | |
5030 | return; | |
5031 | } | |
5032 | } | |
5033 | ||
d3ea7fc4 PL |
5034 | void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id) |
5035 | { | |
5036 | struct hclge_dev *hdev = vport->back; | |
5037 | int reset_try_times = 0; | |
5038 | int reset_status; | |
5039 | u16 queue_gid; | |
5040 | int ret; | |
5041 | ||
5042 | queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id); | |
5043 | ||
5044 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); | |
5045 | if (ret) { | |
5046 | dev_warn(&hdev->pdev->dev, | |
5047 | "Send reset tqp cmd fail, ret = %d\n", ret); | |
5048 | return; | |
5049 | } | |
5050 | ||
5051 | reset_try_times = 0; | |
5052 | while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { | |
5053 | /* Wait for tqp hw reset */ | |
5054 | msleep(20); | |
5055 | reset_status = hclge_get_reset_status(hdev, queue_gid); | |
5056 | if (reset_status) | |
5057 | break; | |
5058 | } | |
5059 | ||
5060 | if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { | |
5061 | dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); | |
5062 | return; | |
5063 | } | |
5064 | ||
5065 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); | |
5066 | if (ret) | |
5067 | dev_warn(&hdev->pdev->dev, | |
5068 | "Deassert the soft reset fail, ret = %d\n", ret); | |
5069 | } | |
5070 | ||
46a3df9f S |
5071 | static u32 hclge_get_fw_version(struct hnae3_handle *handle) |
5072 | { | |
5073 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5074 | struct hclge_dev *hdev = vport->back; | |
5075 | ||
5076 | return hdev->fw_version; | |
5077 | } | |
5078 | ||
a2cfbadb PL |
5079 | static void hclge_get_flowctrl_adv(struct hnae3_handle *handle, |
5080 | u32 *flowctrl_adv) | |
5081 | { | |
5082 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5083 | struct hclge_dev *hdev = vport->back; | |
5084 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5085 | ||
5086 | if (!phydev) | |
5087 | return; | |
5088 | ||
5089 | *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) | | |
5090 | (phydev->advertising & ADVERTISED_Asym_Pause); | |
5091 | } | |
5092 | ||
09ea401e PL |
5093 | static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) |
5094 | { | |
5095 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5096 | ||
5097 | if (!phydev) | |
5098 | return; | |
5099 | ||
5100 | phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
5101 | ||
5102 | if (rx_en) | |
5103 | phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; | |
5104 | ||
5105 | if (tx_en) | |
5106 | phydev->advertising ^= ADVERTISED_Asym_Pause; | |
5107 | } | |
5108 | ||
5109 | static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) | |
5110 | { | |
09ea401e PL |
5111 | int ret; |
5112 | ||
5113 | if (rx_en && tx_en) | |
7a28a82a | 5114 | hdev->fc_mode_last_time = HCLGE_FC_FULL; |
09ea401e | 5115 | else if (rx_en && !tx_en) |
7a28a82a | 5116 | hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; |
09ea401e | 5117 | else if (!rx_en && tx_en) |
7a28a82a | 5118 | hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; |
09ea401e | 5119 | else |
7a28a82a | 5120 | hdev->fc_mode_last_time = HCLGE_FC_NONE; |
09ea401e | 5121 | |
7a28a82a | 5122 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) |
09ea401e | 5123 | return 0; |
09ea401e PL |
5124 | |
5125 | ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); | |
5126 | if (ret) { | |
5127 | dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n", | |
5128 | ret); | |
5129 | return ret; | |
5130 | } | |
5131 | ||
7a28a82a | 5132 | hdev->tm_info.fc_mode = hdev->fc_mode_last_time; |
09ea401e PL |
5133 | |
5134 | return 0; | |
5135 | } | |
5136 | ||
6282f2ea PL |
5137 | int hclge_cfg_flowctrl(struct hclge_dev *hdev) |
5138 | { | |
5139 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5140 | u16 remote_advertising = 0; | |
5141 | u16 local_advertising = 0; | |
5142 | u32 rx_pause, tx_pause; | |
5143 | u8 flowctl; | |
5144 | ||
5145 | if (!phydev->link || !phydev->autoneg) | |
5146 | return 0; | |
5147 | ||
5148 | if (phydev->advertising & ADVERTISED_Pause) | |
5149 | local_advertising = ADVERTISE_PAUSE_CAP; | |
5150 | ||
5151 | if (phydev->advertising & ADVERTISED_Asym_Pause) | |
5152 | local_advertising |= ADVERTISE_PAUSE_ASYM; | |
5153 | ||
5154 | if (phydev->pause) | |
5155 | remote_advertising = LPA_PAUSE_CAP; | |
5156 | ||
5157 | if (phydev->asym_pause) | |
5158 | remote_advertising |= LPA_PAUSE_ASYM; | |
5159 | ||
5160 | flowctl = mii_resolve_flowctrl_fdx(local_advertising, | |
5161 | remote_advertising); | |
5162 | tx_pause = flowctl & FLOW_CTRL_TX; | |
5163 | rx_pause = flowctl & FLOW_CTRL_RX; | |
5164 | ||
5165 | if (phydev->duplex == HCLGE_MAC_HALF) { | |
5166 | tx_pause = 0; | |
5167 | rx_pause = 0; | |
5168 | } | |
5169 | ||
5170 | return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); | |
5171 | } | |
5172 | ||
46a3df9f S |
5173 | static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, |
5174 | u32 *rx_en, u32 *tx_en) | |
5175 | { | |
5176 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5177 | struct hclge_dev *hdev = vport->back; | |
5178 | ||
5179 | *auto_neg = hclge_get_autoneg(handle); | |
5180 | ||
5181 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { | |
5182 | *rx_en = 0; | |
5183 | *tx_en = 0; | |
5184 | return; | |
5185 | } | |
5186 | ||
5187 | if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { | |
5188 | *rx_en = 1; | |
5189 | *tx_en = 0; | |
5190 | } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { | |
5191 | *tx_en = 1; | |
5192 | *rx_en = 0; | |
5193 | } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { | |
5194 | *rx_en = 1; | |
5195 | *tx_en = 1; | |
5196 | } else { | |
5197 | *rx_en = 0; | |
5198 | *tx_en = 0; | |
5199 | } | |
5200 | } | |
5201 | ||
09ea401e PL |
5202 | static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, |
5203 | u32 rx_en, u32 tx_en) | |
5204 | { | |
5205 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5206 | struct hclge_dev *hdev = vport->back; | |
5207 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5208 | u32 fc_autoneg; | |
5209 | ||
09ea401e PL |
5210 | fc_autoneg = hclge_get_autoneg(handle); |
5211 | if (auto_neg != fc_autoneg) { | |
5212 | dev_info(&hdev->pdev->dev, | |
5213 | "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); | |
5214 | return -EOPNOTSUPP; | |
5215 | } | |
5216 | ||
5217 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { | |
5218 | dev_info(&hdev->pdev->dev, | |
5219 | "Priority flow control enabled. Cannot set link flow control.\n"); | |
5220 | return -EOPNOTSUPP; | |
5221 | } | |
5222 | ||
5223 | hclge_set_flowctrl_adv(hdev, rx_en, tx_en); | |
5224 | ||
5225 | if (!fc_autoneg) | |
5226 | return hclge_cfg_pauseparam(hdev, rx_en, tx_en); | |
5227 | ||
bef24782 FL |
5228 | /* Only support flow control negotiation for netdev with |
5229 | * phy attached for now. | |
5230 | */ | |
5231 | if (!phydev) | |
5232 | return -EOPNOTSUPP; | |
5233 | ||
09ea401e PL |
5234 | return phy_start_aneg(phydev); |
5235 | } | |
5236 | ||
46a3df9f S |
5237 | static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, |
5238 | u8 *auto_neg, u32 *speed, u8 *duplex) | |
5239 | { | |
5240 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5241 | struct hclge_dev *hdev = vport->back; | |
5242 | ||
5243 | if (speed) | |
5244 | *speed = hdev->hw.mac.speed; | |
5245 | if (duplex) | |
5246 | *duplex = hdev->hw.mac.duplex; | |
5247 | if (auto_neg) | |
5248 | *auto_neg = hdev->hw.mac.autoneg; | |
5249 | } | |
5250 | ||
5251 | static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type) | |
5252 | { | |
5253 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5254 | struct hclge_dev *hdev = vport->back; | |
5255 | ||
5256 | if (media_type) | |
5257 | *media_type = hdev->hw.mac.media_type; | |
5258 | } | |
5259 | ||
5260 | static void hclge_get_mdix_mode(struct hnae3_handle *handle, | |
5261 | u8 *tp_mdix_ctrl, u8 *tp_mdix) | |
5262 | { | |
5263 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5264 | struct hclge_dev *hdev = vport->back; | |
5265 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5266 | int mdix_ctrl, mdix, retval, is_resolved; | |
5267 | ||
5268 | if (!phydev) { | |
5269 | *tp_mdix_ctrl = ETH_TP_MDI_INVALID; | |
5270 | *tp_mdix = ETH_TP_MDI_INVALID; | |
5271 | return; | |
5272 | } | |
5273 | ||
5274 | phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); | |
5275 | ||
5276 | retval = phy_read(phydev, HCLGE_PHY_CSC_REG); | |
5277 | mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, | |
5278 | HCLGE_PHY_MDIX_CTRL_S); | |
5279 | ||
5280 | retval = phy_read(phydev, HCLGE_PHY_CSS_REG); | |
5281 | mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); | |
5282 | is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); | |
5283 | ||
5284 | phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); | |
5285 | ||
5286 | switch (mdix_ctrl) { | |
5287 | case 0x0: | |
5288 | *tp_mdix_ctrl = ETH_TP_MDI; | |
5289 | break; | |
5290 | case 0x1: | |
5291 | *tp_mdix_ctrl = ETH_TP_MDI_X; | |
5292 | break; | |
5293 | case 0x3: | |
5294 | *tp_mdix_ctrl = ETH_TP_MDI_AUTO; | |
5295 | break; | |
5296 | default: | |
5297 | *tp_mdix_ctrl = ETH_TP_MDI_INVALID; | |
5298 | break; | |
5299 | } | |
5300 | ||
5301 | if (!is_resolved) | |
5302 | *tp_mdix = ETH_TP_MDI_INVALID; | |
5303 | else if (mdix) | |
5304 | *tp_mdix = ETH_TP_MDI_X; | |
5305 | else | |
5306 | *tp_mdix = ETH_TP_MDI; | |
5307 | } | |
5308 | ||
5309 | static int hclge_init_client_instance(struct hnae3_client *client, | |
5310 | struct hnae3_ae_dev *ae_dev) | |
5311 | { | |
5312 | struct hclge_dev *hdev = ae_dev->priv; | |
5313 | struct hclge_vport *vport; | |
5314 | int i, ret; | |
5315 | ||
5316 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
5317 | vport = &hdev->vport[i]; | |
5318 | ||
5319 | switch (client->type) { | |
5320 | case HNAE3_CLIENT_KNIC: | |
5321 | ||
5322 | hdev->nic_client = client; | |
5323 | vport->nic.client = client; | |
5324 | ret = client->ops->init_instance(&vport->nic); | |
5325 | if (ret) | |
5326 | goto err; | |
5327 | ||
5328 | if (hdev->roce_client && | |
e92a0843 | 5329 | hnae3_dev_roce_supported(hdev)) { |
46a3df9f S |
5330 | struct hnae3_client *rc = hdev->roce_client; |
5331 | ||
5332 | ret = hclge_init_roce_base_info(vport); | |
5333 | if (ret) | |
5334 | goto err; | |
5335 | ||
5336 | ret = rc->ops->init_instance(&vport->roce); | |
5337 | if (ret) | |
5338 | goto err; | |
5339 | } | |
5340 | ||
5341 | break; | |
5342 | case HNAE3_CLIENT_UNIC: | |
5343 | hdev->nic_client = client; | |
5344 | vport->nic.client = client; | |
5345 | ||
5346 | ret = client->ops->init_instance(&vport->nic); | |
5347 | if (ret) | |
5348 | goto err; | |
5349 | ||
5350 | break; | |
5351 | case HNAE3_CLIENT_ROCE: | |
e92a0843 | 5352 | if (hnae3_dev_roce_supported(hdev)) { |
46a3df9f S |
5353 | hdev->roce_client = client; |
5354 | vport->roce.client = client; | |
5355 | } | |
5356 | ||
3a46f34d | 5357 | if (hdev->roce_client && hdev->nic_client) { |
46a3df9f S |
5358 | ret = hclge_init_roce_base_info(vport); |
5359 | if (ret) | |
5360 | goto err; | |
5361 | ||
5362 | ret = client->ops->init_instance(&vport->roce); | |
5363 | if (ret) | |
5364 | goto err; | |
5365 | } | |
5366 | } | |
5367 | } | |
5368 | ||
5369 | return 0; | |
5370 | err: | |
5371 | return ret; | |
5372 | } | |
5373 | ||
5374 | static void hclge_uninit_client_instance(struct hnae3_client *client, | |
5375 | struct hnae3_ae_dev *ae_dev) | |
5376 | { | |
5377 | struct hclge_dev *hdev = ae_dev->priv; | |
5378 | struct hclge_vport *vport; | |
5379 | int i; | |
5380 | ||
5381 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
5382 | vport = &hdev->vport[i]; | |
a17dcf3f | 5383 | if (hdev->roce_client) { |
46a3df9f S |
5384 | hdev->roce_client->ops->uninit_instance(&vport->roce, |
5385 | 0); | |
a17dcf3f L |
5386 | hdev->roce_client = NULL; |
5387 | vport->roce.client = NULL; | |
5388 | } | |
46a3df9f S |
5389 | if (client->type == HNAE3_CLIENT_ROCE) |
5390 | return; | |
a17dcf3f | 5391 | if (client->ops->uninit_instance) { |
46a3df9f | 5392 | client->ops->uninit_instance(&vport->nic, 0); |
a17dcf3f L |
5393 | hdev->nic_client = NULL; |
5394 | vport->nic.client = NULL; | |
5395 | } | |
46a3df9f S |
5396 | } |
5397 | } | |
5398 | ||
5399 | static int hclge_pci_init(struct hclge_dev *hdev) | |
5400 | { | |
5401 | struct pci_dev *pdev = hdev->pdev; | |
5402 | struct hclge_hw *hw; | |
5403 | int ret; | |
5404 | ||
5405 | ret = pci_enable_device(pdev); | |
5406 | if (ret) { | |
5407 | dev_err(&pdev->dev, "failed to enable PCI device\n"); | |
5408 | goto err_no_drvdata; | |
5409 | } | |
5410 | ||
5411 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); | |
5412 | if (ret) { | |
5413 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); | |
5414 | if (ret) { | |
5415 | dev_err(&pdev->dev, | |
5416 | "can't set consistent PCI DMA"); | |
5417 | goto err_disable_device; | |
5418 | } | |
5419 | dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); | |
5420 | } | |
5421 | ||
5422 | ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); | |
5423 | if (ret) { | |
5424 | dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); | |
5425 | goto err_disable_device; | |
5426 | } | |
5427 | ||
5428 | pci_set_master(pdev); | |
5429 | hw = &hdev->hw; | |
5430 | hw->back = hdev; | |
5431 | hw->io_base = pcim_iomap(pdev, 2, 0); | |
5432 | if (!hw->io_base) { | |
5433 | dev_err(&pdev->dev, "Can't map configuration register space\n"); | |
5434 | ret = -ENOMEM; | |
5435 | goto err_clr_master; | |
5436 | } | |
5437 | ||
709eb41a L |
5438 | hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); |
5439 | ||
46a3df9f S |
5440 | return 0; |
5441 | err_clr_master: | |
5442 | pci_clear_master(pdev); | |
5443 | pci_release_regions(pdev); | |
5444 | err_disable_device: | |
5445 | pci_disable_device(pdev); | |
5446 | err_no_drvdata: | |
5447 | pci_set_drvdata(pdev, NULL); | |
5448 | ||
5449 | return ret; | |
5450 | } | |
5451 | ||
5452 | static void hclge_pci_uninit(struct hclge_dev *hdev) | |
5453 | { | |
5454 | struct pci_dev *pdev = hdev->pdev; | |
5455 | ||
887c3820 | 5456 | pci_free_irq_vectors(pdev); |
46a3df9f S |
5457 | pci_clear_master(pdev); |
5458 | pci_release_mem_regions(pdev); | |
5459 | pci_disable_device(pdev); | |
5460 | } | |
5461 | ||
5462 | static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) | |
5463 | { | |
5464 | struct pci_dev *pdev = ae_dev->pdev; | |
46a3df9f S |
5465 | struct hclge_dev *hdev; |
5466 | int ret; | |
5467 | ||
5468 | hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); | |
5469 | if (!hdev) { | |
5470 | ret = -ENOMEM; | |
e0027501 | 5471 | goto out; |
46a3df9f S |
5472 | } |
5473 | ||
46a3df9f S |
5474 | hdev->pdev = pdev; |
5475 | hdev->ae_dev = ae_dev; | |
4ed340ab | 5476 | hdev->reset_type = HNAE3_NONE_RESET; |
ed4a1bb8 | 5477 | hdev->reset_request = 0; |
202f2014 | 5478 | hdev->reset_pending = 0; |
46a3df9f S |
5479 | ae_dev->priv = hdev; |
5480 | ||
46a3df9f S |
5481 | ret = hclge_pci_init(hdev); |
5482 | if (ret) { | |
5483 | dev_err(&pdev->dev, "PCI init failed\n"); | |
e0027501 | 5484 | goto out; |
46a3df9f S |
5485 | } |
5486 | ||
3efb960f L |
5487 | /* Firmware command queue initialize */ |
5488 | ret = hclge_cmd_queue_init(hdev); | |
5489 | if (ret) { | |
5490 | dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret); | |
e0027501 | 5491 | goto err_pci_uninit; |
3efb960f L |
5492 | } |
5493 | ||
5494 | /* Firmware command initialize */ | |
46a3df9f S |
5495 | ret = hclge_cmd_init(hdev); |
5496 | if (ret) | |
e0027501 | 5497 | goto err_cmd_uninit; |
46a3df9f S |
5498 | |
5499 | ret = hclge_get_cap(hdev); | |
5500 | if (ret) { | |
e00e2197 CIK |
5501 | dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", |
5502 | ret); | |
e0027501 | 5503 | goto err_cmd_uninit; |
46a3df9f S |
5504 | } |
5505 | ||
5506 | ret = hclge_configure(hdev); | |
5507 | if (ret) { | |
5508 | dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); | |
e0027501 | 5509 | goto err_cmd_uninit; |
46a3df9f S |
5510 | } |
5511 | ||
887c3820 | 5512 | ret = hclge_init_msi(hdev); |
46a3df9f | 5513 | if (ret) { |
887c3820 | 5514 | dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); |
e0027501 | 5515 | goto err_cmd_uninit; |
46a3df9f S |
5516 | } |
5517 | ||
466b0c00 L |
5518 | ret = hclge_misc_irq_init(hdev); |
5519 | if (ret) { | |
5520 | dev_err(&pdev->dev, | |
5521 | "Misc IRQ(vector0) init error, ret = %d.\n", | |
5522 | ret); | |
e0027501 | 5523 | goto err_msi_uninit; |
466b0c00 L |
5524 | } |
5525 | ||
46a3df9f S |
5526 | ret = hclge_alloc_tqps(hdev); |
5527 | if (ret) { | |
5528 | dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); | |
e0027501 | 5529 | goto err_msi_irq_uninit; |
46a3df9f S |
5530 | } |
5531 | ||
5532 | ret = hclge_alloc_vport(hdev); | |
5533 | if (ret) { | |
5534 | dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret); | |
e0027501 | 5535 | goto err_msi_irq_uninit; |
46a3df9f S |
5536 | } |
5537 | ||
7df7dad6 L |
5538 | ret = hclge_map_tqp(hdev); |
5539 | if (ret) { | |
5540 | dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); | |
e0027501 | 5541 | goto err_sriov_disable; |
7df7dad6 L |
5542 | } |
5543 | ||
dea9a821 HT |
5544 | if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { |
5545 | ret = hclge_mac_mdio_config(hdev); | |
5546 | if (ret) { | |
5547 | dev_err(&hdev->pdev->dev, | |
5548 | "mdio config fail ret=%d\n", ret); | |
5549 | goto err_sriov_disable; | |
5550 | } | |
cf9cca2d | 5551 | } |
5552 | ||
46a3df9f S |
5553 | ret = hclge_mac_init(hdev); |
5554 | if (ret) { | |
5555 | dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); | |
e0027501 | 5556 | goto err_mdiobus_unreg; |
46a3df9f | 5557 | } |
46a3df9f S |
5558 | |
5559 | ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); | |
5560 | if (ret) { | |
5561 | dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); | |
e0027501 | 5562 | goto err_mdiobus_unreg; |
46a3df9f S |
5563 | } |
5564 | ||
46a3df9f S |
5565 | ret = hclge_init_vlan_config(hdev); |
5566 | if (ret) { | |
5567 | dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); | |
e0027501 | 5568 | goto err_mdiobus_unreg; |
46a3df9f S |
5569 | } |
5570 | ||
5571 | ret = hclge_tm_schd_init(hdev); | |
5572 | if (ret) { | |
5573 | dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); | |
e0027501 | 5574 | goto err_mdiobus_unreg; |
68ece54e YL |
5575 | } |
5576 | ||
8015bb74 | 5577 | hclge_rss_init_cfg(hdev); |
68ece54e YL |
5578 | ret = hclge_rss_init_hw(hdev); |
5579 | if (ret) { | |
5580 | dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); | |
e0027501 | 5581 | goto err_mdiobus_unreg; |
46a3df9f S |
5582 | } |
5583 | ||
635bfb58 FL |
5584 | ret = init_mgr_tbl(hdev); |
5585 | if (ret) { | |
5586 | dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); | |
e0027501 | 5587 | goto err_mdiobus_unreg; |
635bfb58 FL |
5588 | } |
5589 | ||
cacde272 YL |
5590 | hclge_dcb_ops_set(hdev); |
5591 | ||
d039ef68 | 5592 | timer_setup(&hdev->service_timer, hclge_service_timer, 0); |
46a3df9f | 5593 | INIT_WORK(&hdev->service_task, hclge_service_task); |
ed4a1bb8 | 5594 | INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); |
22fd3468 | 5595 | INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task); |
46a3df9f | 5596 | |
466b0c00 L |
5597 | /* Enable MISC vector(vector0) */ |
5598 | hclge_enable_vector(&hdev->misc_vector, true); | |
5599 | ||
46a3df9f S |
5600 | set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); |
5601 | set_bit(HCLGE_STATE_DOWN, &hdev->state); | |
ed4a1bb8 SM |
5602 | clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); |
5603 | clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); | |
22fd3468 SM |
5604 | clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); |
5605 | clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); | |
46a3df9f S |
5606 | |
5607 | pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); | |
5608 | return 0; | |
5609 | ||
e0027501 HT |
5610 | err_mdiobus_unreg: |
5611 | if (hdev->hw.mac.phydev) | |
5612 | mdiobus_unregister(hdev->hw.mac.mdio_bus); | |
5613 | err_sriov_disable: | |
5614 | if (IS_ENABLED(CONFIG_PCI_IOV)) | |
5615 | hclge_disable_sriov(hdev); | |
5616 | err_msi_irq_uninit: | |
5617 | hclge_misc_irq_uninit(hdev); | |
5618 | err_msi_uninit: | |
5619 | pci_free_irq_vectors(pdev); | |
5620 | err_cmd_uninit: | |
5621 | hclge_destroy_cmd_queue(&hdev->hw); | |
5622 | err_pci_uninit: | |
5623 | pci_clear_master(pdev); | |
46a3df9f | 5624 | pci_release_regions(pdev); |
e0027501 | 5625 | pci_disable_device(pdev); |
46a3df9f | 5626 | pci_set_drvdata(pdev, NULL); |
e0027501 | 5627 | out: |
46a3df9f S |
5628 | return ret; |
5629 | } | |
5630 | ||
c6dc5213 | 5631 | static void hclge_stats_clear(struct hclge_dev *hdev) |
5632 | { | |
5633 | memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats)); | |
5634 | } | |
5635 | ||
4ed340ab L |
5636 | static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) |
5637 | { | |
5638 | struct hclge_dev *hdev = ae_dev->priv; | |
5639 | struct pci_dev *pdev = ae_dev->pdev; | |
5640 | int ret; | |
5641 | ||
5642 | set_bit(HCLGE_STATE_DOWN, &hdev->state); | |
5643 | ||
c6dc5213 | 5644 | hclge_stats_clear(hdev); |
4e66632d | 5645 | memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); |
c6dc5213 | 5646 | |
4ed340ab L |
5647 | ret = hclge_cmd_init(hdev); |
5648 | if (ret) { | |
5649 | dev_err(&pdev->dev, "Cmd queue init failed\n"); | |
5650 | return ret; | |
5651 | } | |
5652 | ||
5653 | ret = hclge_get_cap(hdev); | |
5654 | if (ret) { | |
5655 | dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", | |
5656 | ret); | |
5657 | return ret; | |
5658 | } | |
5659 | ||
5660 | ret = hclge_configure(hdev); | |
5661 | if (ret) { | |
5662 | dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); | |
5663 | return ret; | |
5664 | } | |
5665 | ||
5666 | ret = hclge_map_tqp(hdev); | |
5667 | if (ret) { | |
5668 | dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); | |
5669 | return ret; | |
5670 | } | |
5671 | ||
5672 | ret = hclge_mac_init(hdev); | |
5673 | if (ret) { | |
5674 | dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); | |
5675 | return ret; | |
5676 | } | |
5677 | ||
4ed340ab L |
5678 | ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); |
5679 | if (ret) { | |
5680 | dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); | |
5681 | return ret; | |
5682 | } | |
5683 | ||
5684 | ret = hclge_init_vlan_config(hdev); | |
5685 | if (ret) { | |
5686 | dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); | |
5687 | return ret; | |
5688 | } | |
5689 | ||
d85f1ab5 | 5690 | ret = hclge_tm_init_hw(hdev); |
4ed340ab | 5691 | if (ret) { |
d85f1ab5 | 5692 | dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); |
4ed340ab L |
5693 | return ret; |
5694 | } | |
5695 | ||
5696 | ret = hclge_rss_init_hw(hdev); | |
5697 | if (ret) { | |
5698 | dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); | |
5699 | return ret; | |
5700 | } | |
5701 | ||
5702 | /* Enable MISC vector(vector0) */ | |
5703 | hclge_enable_vector(&hdev->misc_vector, true); | |
5704 | ||
5705 | dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", | |
5706 | HCLGE_DRIVER_NAME); | |
5707 | ||
5708 | return 0; | |
5709 | } | |
5710 | ||
46a3df9f S |
5711 | static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) |
5712 | { | |
5713 | struct hclge_dev *hdev = ae_dev->priv; | |
5714 | struct hclge_mac *mac = &hdev->hw.mac; | |
5715 | ||
5716 | set_bit(HCLGE_STATE_DOWN, &hdev->state); | |
5717 | ||
2a32ca13 AB |
5718 | if (IS_ENABLED(CONFIG_PCI_IOV)) |
5719 | hclge_disable_sriov(hdev); | |
46a3df9f | 5720 | |
d039ef68 | 5721 | if (hdev->service_timer.function) |
46a3df9f S |
5722 | del_timer_sync(&hdev->service_timer); |
5723 | if (hdev->service_task.func) | |
5724 | cancel_work_sync(&hdev->service_task); | |
ed4a1bb8 SM |
5725 | if (hdev->rst_service_task.func) |
5726 | cancel_work_sync(&hdev->rst_service_task); | |
22fd3468 SM |
5727 | if (hdev->mbx_service_task.func) |
5728 | cancel_work_sync(&hdev->mbx_service_task); | |
46a3df9f S |
5729 | |
5730 | if (mac->phydev) | |
5731 | mdiobus_unregister(mac->mdio_bus); | |
5732 | ||
466b0c00 L |
5733 | /* Disable MISC vector(vector0) */ |
5734 | hclge_enable_vector(&hdev->misc_vector, false); | |
46a3df9f | 5735 | hclge_destroy_cmd_queue(&hdev->hw); |
202f2014 | 5736 | hclge_misc_irq_uninit(hdev); |
46a3df9f S |
5737 | hclge_pci_uninit(hdev); |
5738 | ae_dev->priv = NULL; | |
5739 | } | |
5740 | ||
4f645a90 PL |
5741 | static u32 hclge_get_max_channels(struct hnae3_handle *handle) |
5742 | { | |
5743 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
5744 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5745 | struct hclge_dev *hdev = vport->back; | |
5746 | ||
5747 | return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); | |
5748 | } | |
5749 | ||
5750 | static void hclge_get_channels(struct hnae3_handle *handle, | |
5751 | struct ethtool_channels *ch) | |
5752 | { | |
5753 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5754 | ||
5755 | ch->max_combined = hclge_get_max_channels(handle); | |
5756 | ch->other_count = 1; | |
5757 | ch->max_other = 1; | |
5758 | ch->combined_count = vport->alloc_tqps; | |
5759 | } | |
5760 | ||
f1f779ce PL |
5761 | static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, |
5762 | u16 *free_tqps, u16 *max_rss_size) | |
5763 | { | |
5764 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5765 | struct hclge_dev *hdev = vport->back; | |
5766 | u16 temp_tqps = 0; | |
5767 | int i; | |
5768 | ||
5769 | for (i = 0; i < hdev->num_tqps; i++) { | |
5770 | if (!hdev->htqp[i].alloced) | |
5771 | temp_tqps++; | |
5772 | } | |
5773 | *free_tqps = temp_tqps; | |
5774 | *max_rss_size = hdev->rss_size_max; | |
5775 | } | |
5776 | ||
5777 | static void hclge_release_tqp(struct hclge_vport *vport) | |
5778 | { | |
5779 | struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; | |
5780 | struct hclge_dev *hdev = vport->back; | |
5781 | int i; | |
5782 | ||
5783 | for (i = 0; i < kinfo->num_tqps; i++) { | |
5784 | struct hclge_tqp *tqp = | |
5785 | container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
5786 | ||
5787 | tqp->q.handle = NULL; | |
5788 | tqp->q.tqp_index = 0; | |
5789 | tqp->alloced = false; | |
5790 | } | |
5791 | ||
5792 | devm_kfree(&hdev->pdev->dev, kinfo->tqp); | |
5793 | kinfo->tqp = NULL; | |
5794 | } | |
5795 | ||
5796 | static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num) | |
5797 | { | |
5798 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5799 | struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; | |
5800 | struct hclge_dev *hdev = vport->back; | |
5801 | int cur_rss_size = kinfo->rss_size; | |
5802 | int cur_tqps = kinfo->num_tqps; | |
5803 | u16 tc_offset[HCLGE_MAX_TC_NUM]; | |
5804 | u16 tc_valid[HCLGE_MAX_TC_NUM]; | |
5805 | u16 tc_size[HCLGE_MAX_TC_NUM]; | |
5806 | u16 roundup_size; | |
5807 | u32 *rss_indir; | |
5808 | int ret, i; | |
5809 | ||
5810 | hclge_release_tqp(vport); | |
5811 | ||
5812 | ret = hclge_knic_setup(vport, new_tqps_num); | |
5813 | if (ret) { | |
5814 | dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret); | |
5815 | return ret; | |
5816 | } | |
5817 | ||
5818 | ret = hclge_map_tqp_to_vport(hdev, vport); | |
5819 | if (ret) { | |
5820 | dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret); | |
5821 | return ret; | |
5822 | } | |
5823 | ||
5824 | ret = hclge_tm_schd_init(hdev); | |
5825 | if (ret) { | |
5826 | dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret); | |
5827 | return ret; | |
5828 | } | |
5829 | ||
5830 | roundup_size = roundup_pow_of_two(kinfo->rss_size); | |
5831 | roundup_size = ilog2(roundup_size); | |
5832 | /* Set the RSS TC mode according to the new RSS size */ | |
5833 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
5834 | tc_valid[i] = 0; | |
5835 | ||
5836 | if (!(hdev->hw_tc_map & BIT(i))) | |
5837 | continue; | |
5838 | ||
5839 | tc_valid[i] = 1; | |
5840 | tc_size[i] = roundup_size; | |
5841 | tc_offset[i] = kinfo->rss_size * i; | |
5842 | } | |
5843 | ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); | |
5844 | if (ret) | |
5845 | return ret; | |
5846 | ||
5847 | /* Reinitializes the rss indirect table according to the new RSS size */ | |
5848 | rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); | |
5849 | if (!rss_indir) | |
5850 | return -ENOMEM; | |
5851 | ||
5852 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
5853 | rss_indir[i] = i % kinfo->rss_size; | |
5854 | ||
5855 | ret = hclge_set_rss(handle, rss_indir, NULL, 0); | |
5856 | if (ret) | |
5857 | dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", | |
5858 | ret); | |
5859 | ||
5860 | kfree(rss_indir); | |
5861 | ||
5862 | if (!ret) | |
5863 | dev_info(&hdev->pdev->dev, | |
5864 | "Channels changed, rss_size from %d to %d, tqps from %d to %d", | |
5865 | cur_rss_size, kinfo->rss_size, | |
5866 | cur_tqps, kinfo->rss_size * kinfo->num_tc); | |
5867 | ||
5868 | return ret; | |
5869 | } | |
5870 | ||
db2a3e43 FL |
5871 | static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, |
5872 | u32 *regs_num_64_bit) | |
5873 | { | |
5874 | struct hclge_desc desc; | |
5875 | u32 total_num; | |
5876 | int ret; | |
5877 | ||
5878 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); | |
5879 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
5880 | if (ret) { | |
5881 | dev_err(&hdev->pdev->dev, | |
5882 | "Query register number cmd failed, ret = %d.\n", ret); | |
5883 | return ret; | |
5884 | } | |
5885 | ||
5886 | *regs_num_32_bit = le32_to_cpu(desc.data[0]); | |
5887 | *regs_num_64_bit = le32_to_cpu(desc.data[1]); | |
5888 | ||
5889 | total_num = *regs_num_32_bit + *regs_num_64_bit; | |
5890 | if (!total_num) | |
5891 | return -EINVAL; | |
5892 | ||
5893 | return 0; | |
5894 | } | |
5895 | ||
5896 | static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, | |
5897 | void *data) | |
5898 | { | |
5899 | #define HCLGE_32_BIT_REG_RTN_DATANUM 8 | |
5900 | ||
5901 | struct hclge_desc *desc; | |
5902 | u32 *reg_val = data; | |
5903 | __le32 *desc_data; | |
5904 | int cmd_num; | |
5905 | int i, k, n; | |
5906 | int ret; | |
5907 | ||
5908 | if (regs_num == 0) | |
5909 | return 0; | |
5910 | ||
5911 | cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM); | |
5912 | desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); | |
5913 | if (!desc) | |
5914 | return -ENOMEM; | |
5915 | ||
5916 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); | |
5917 | ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); | |
5918 | if (ret) { | |
5919 | dev_err(&hdev->pdev->dev, | |
5920 | "Query 32 bit register cmd failed, ret = %d.\n", ret); | |
5921 | kfree(desc); | |
5922 | return ret; | |
5923 | } | |
5924 | ||
5925 | for (i = 0; i < cmd_num; i++) { | |
5926 | if (i == 0) { | |
5927 | desc_data = (__le32 *)(&desc[i].data[0]); | |
5928 | n = HCLGE_32_BIT_REG_RTN_DATANUM - 2; | |
5929 | } else { | |
5930 | desc_data = (__le32 *)(&desc[i]); | |
5931 | n = HCLGE_32_BIT_REG_RTN_DATANUM; | |
5932 | } | |
5933 | for (k = 0; k < n; k++) { | |
5934 | *reg_val++ = le32_to_cpu(*desc_data++); | |
5935 | ||
5936 | regs_num--; | |
5937 | if (!regs_num) | |
5938 | break; | |
5939 | } | |
5940 | } | |
5941 | ||
5942 | kfree(desc); | |
5943 | return 0; | |
5944 | } | |
5945 | ||
5946 | static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, | |
5947 | void *data) | |
5948 | { | |
5949 | #define HCLGE_64_BIT_REG_RTN_DATANUM 4 | |
5950 | ||
5951 | struct hclge_desc *desc; | |
5952 | u64 *reg_val = data; | |
5953 | __le64 *desc_data; | |
5954 | int cmd_num; | |
5955 | int i, k, n; | |
5956 | int ret; | |
5957 | ||
5958 | if (regs_num == 0) | |
5959 | return 0; | |
5960 | ||
5961 | cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM); | |
5962 | desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); | |
5963 | if (!desc) | |
5964 | return -ENOMEM; | |
5965 | ||
5966 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); | |
5967 | ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); | |
5968 | if (ret) { | |
5969 | dev_err(&hdev->pdev->dev, | |
5970 | "Query 64 bit register cmd failed, ret = %d.\n", ret); | |
5971 | kfree(desc); | |
5972 | return ret; | |
5973 | } | |
5974 | ||
5975 | for (i = 0; i < cmd_num; i++) { | |
5976 | if (i == 0) { | |
5977 | desc_data = (__le64 *)(&desc[i].data[0]); | |
5978 | n = HCLGE_64_BIT_REG_RTN_DATANUM - 1; | |
5979 | } else { | |
5980 | desc_data = (__le64 *)(&desc[i]); | |
5981 | n = HCLGE_64_BIT_REG_RTN_DATANUM; | |
5982 | } | |
5983 | for (k = 0; k < n; k++) { | |
5984 | *reg_val++ = le64_to_cpu(*desc_data++); | |
5985 | ||
5986 | regs_num--; | |
5987 | if (!regs_num) | |
5988 | break; | |
5989 | } | |
5990 | } | |
5991 | ||
5992 | kfree(desc); | |
5993 | return 0; | |
5994 | } | |
5995 | ||
5996 | static int hclge_get_regs_len(struct hnae3_handle *handle) | |
5997 | { | |
5998 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5999 | struct hclge_dev *hdev = vport->back; | |
6000 | u32 regs_num_32_bit, regs_num_64_bit; | |
6001 | int ret; | |
6002 | ||
6003 | ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); | |
6004 | if (ret) { | |
6005 | dev_err(&hdev->pdev->dev, | |
6006 | "Get register number failed, ret = %d.\n", ret); | |
6007 | return -EOPNOTSUPP; | |
6008 | } | |
6009 | ||
6010 | return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64); | |
6011 | } | |
6012 | ||
6013 | static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, | |
6014 | void *data) | |
6015 | { | |
6016 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6017 | struct hclge_dev *hdev = vport->back; | |
6018 | u32 regs_num_32_bit, regs_num_64_bit; | |
6019 | int ret; | |
6020 | ||
6021 | *version = hdev->fw_version; | |
6022 | ||
6023 | ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); | |
6024 | if (ret) { | |
6025 | dev_err(&hdev->pdev->dev, | |
6026 | "Get register number failed, ret = %d.\n", ret); | |
6027 | return; | |
6028 | } | |
6029 | ||
6030 | ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data); | |
6031 | if (ret) { | |
6032 | dev_err(&hdev->pdev->dev, | |
6033 | "Get 32 bit register failed, ret = %d.\n", ret); | |
6034 | return; | |
6035 | } | |
6036 | ||
6037 | data = (u32 *)data + regs_num_32_bit; | |
6038 | ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, | |
6039 | data); | |
6040 | if (ret) | |
6041 | dev_err(&hdev->pdev->dev, | |
6042 | "Get 64 bit register failed, ret = %d.\n", ret); | |
6043 | } | |
6044 | ||
d9a0884e JS |
6045 | static int hclge_set_led_status_sfp(struct hclge_dev *hdev, u8 speed_led_status, |
6046 | u8 act_led_status, u8 link_led_status, | |
6047 | u8 locate_led_status) | |
6048 | { | |
6049 | struct hclge_set_led_state_cmd *req; | |
6050 | struct hclge_desc desc; | |
6051 | int ret; | |
6052 | ||
6053 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); | |
6054 | ||
6055 | req = (struct hclge_set_led_state_cmd *)desc.data; | |
6056 | hnae_set_field(req->port_speed_led_config, HCLGE_LED_PORT_SPEED_STATE_M, | |
6057 | HCLGE_LED_PORT_SPEED_STATE_S, speed_led_status); | |
6058 | hnae_set_field(req->link_led_config, HCLGE_LED_ACTIVITY_STATE_M, | |
6059 | HCLGE_LED_ACTIVITY_STATE_S, act_led_status); | |
6060 | hnae_set_field(req->activity_led_config, HCLGE_LED_LINK_STATE_M, | |
6061 | HCLGE_LED_LINK_STATE_S, link_led_status); | |
6062 | hnae_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, | |
6063 | HCLGE_LED_LOCATE_STATE_S, locate_led_status); | |
6064 | ||
6065 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
6066 | if (ret) | |
6067 | dev_err(&hdev->pdev->dev, | |
6068 | "Send set led state cmd error, ret =%d\n", ret); | |
6069 | ||
6070 | return ret; | |
6071 | } | |
6072 | ||
6073 | enum hclge_led_status { | |
6074 | HCLGE_LED_OFF, | |
6075 | HCLGE_LED_ON, | |
6076 | HCLGE_LED_NO_CHANGE = 0xFF, | |
6077 | }; | |
6078 | ||
6079 | static int hclge_set_led_id(struct hnae3_handle *handle, | |
6080 | enum ethtool_phys_id_state status) | |
6081 | { | |
6082 | #define BLINK_FREQUENCY 2 | |
6083 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6084 | struct hclge_dev *hdev = vport->back; | |
6085 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
6086 | int ret = 0; | |
6087 | ||
6088 | if (phydev || hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) | |
6089 | return -EOPNOTSUPP; | |
6090 | ||
6091 | switch (status) { | |
6092 | case ETHTOOL_ID_ACTIVE: | |
6093 | ret = hclge_set_led_status_sfp(hdev, | |
6094 | HCLGE_LED_NO_CHANGE, | |
6095 | HCLGE_LED_NO_CHANGE, | |
6096 | HCLGE_LED_NO_CHANGE, | |
6097 | HCLGE_LED_ON); | |
6098 | break; | |
6099 | case ETHTOOL_ID_INACTIVE: | |
6100 | ret = hclge_set_led_status_sfp(hdev, | |
6101 | HCLGE_LED_NO_CHANGE, | |
6102 | HCLGE_LED_NO_CHANGE, | |
6103 | HCLGE_LED_NO_CHANGE, | |
6104 | HCLGE_LED_OFF); | |
6105 | break; | |
6106 | default: | |
6107 | ret = -EINVAL; | |
6108 | break; | |
6109 | } | |
6110 | ||
6111 | return ret; | |
6112 | } | |
6113 | ||
fe36292f JS |
6114 | enum hclge_led_port_speed { |
6115 | HCLGE_SPEED_LED_FOR_1G, | |
6116 | HCLGE_SPEED_LED_FOR_10G, | |
6117 | HCLGE_SPEED_LED_FOR_25G, | |
6118 | HCLGE_SPEED_LED_FOR_40G, | |
6119 | HCLGE_SPEED_LED_FOR_50G, | |
6120 | HCLGE_SPEED_LED_FOR_100G, | |
6121 | }; | |
6122 | ||
6123 | static u8 hclge_led_get_speed_status(u32 speed) | |
6124 | { | |
6125 | u8 speed_led; | |
6126 | ||
6127 | switch (speed) { | |
6128 | case HCLGE_MAC_SPEED_1G: | |
6129 | speed_led = HCLGE_SPEED_LED_FOR_1G; | |
6130 | break; | |
6131 | case HCLGE_MAC_SPEED_10G: | |
6132 | speed_led = HCLGE_SPEED_LED_FOR_10G; | |
6133 | break; | |
6134 | case HCLGE_MAC_SPEED_25G: | |
6135 | speed_led = HCLGE_SPEED_LED_FOR_25G; | |
6136 | break; | |
6137 | case HCLGE_MAC_SPEED_40G: | |
6138 | speed_led = HCLGE_SPEED_LED_FOR_40G; | |
6139 | break; | |
6140 | case HCLGE_MAC_SPEED_50G: | |
6141 | speed_led = HCLGE_SPEED_LED_FOR_50G; | |
6142 | break; | |
6143 | case HCLGE_MAC_SPEED_100G: | |
6144 | speed_led = HCLGE_SPEED_LED_FOR_100G; | |
6145 | break; | |
6146 | default: | |
6147 | speed_led = HCLGE_LED_NO_CHANGE; | |
6148 | } | |
6149 | ||
6150 | return speed_led; | |
6151 | } | |
6152 | ||
6153 | static int hclge_update_led_status(struct hclge_dev *hdev) | |
6154 | { | |
6155 | u8 port_speed_status, link_status, activity_status; | |
6156 | u64 rx_pkts, tx_pkts; | |
6157 | ||
6158 | if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) | |
6159 | return 0; | |
6160 | ||
6161 | port_speed_status = hclge_led_get_speed_status(hdev->hw.mac.speed); | |
6162 | ||
6163 | rx_pkts = hdev->hw_stats.mac_stats.mac_rx_total_pkt_num; | |
6164 | tx_pkts = hdev->hw_stats.mac_stats.mac_tx_total_pkt_num; | |
6165 | if (rx_pkts != hdev->rx_pkts_for_led || | |
6166 | tx_pkts != hdev->tx_pkts_for_led) | |
6167 | activity_status = HCLGE_LED_ON; | |
6168 | else | |
6169 | activity_status = HCLGE_LED_OFF; | |
6170 | hdev->rx_pkts_for_led = rx_pkts; | |
6171 | hdev->tx_pkts_for_led = tx_pkts; | |
6172 | ||
6173 | if (hdev->hw.mac.link) | |
6174 | link_status = HCLGE_LED_ON; | |
6175 | else | |
6176 | link_status = HCLGE_LED_OFF; | |
6177 | ||
6178 | return hclge_set_led_status_sfp(hdev, port_speed_status, | |
6179 | activity_status, link_status, | |
6180 | HCLGE_LED_NO_CHANGE); | |
6181 | } | |
6182 | ||
d92ceae9 FL |
6183 | static void hclge_get_link_mode(struct hnae3_handle *handle, |
6184 | unsigned long *supported, | |
6185 | unsigned long *advertising) | |
6186 | { | |
6187 | unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); | |
6188 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6189 | struct hclge_dev *hdev = vport->back; | |
6190 | unsigned int idx = 0; | |
6191 | ||
6192 | for (; idx < size; idx++) { | |
6193 | supported[idx] = hdev->hw.mac.supported[idx]; | |
6194 | advertising[idx] = hdev->hw.mac.advertising[idx]; | |
6195 | } | |
6196 | } | |
6197 | ||
6198 | static void hclge_get_port_type(struct hnae3_handle *handle, | |
6199 | u8 *port_type) | |
6200 | { | |
6201 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6202 | struct hclge_dev *hdev = vport->back; | |
6203 | u8 media_type = hdev->hw.mac.media_type; | |
6204 | ||
6205 | switch (media_type) { | |
6206 | case HNAE3_MEDIA_TYPE_FIBER: | |
6207 | *port_type = PORT_FIBRE; | |
6208 | break; | |
6209 | case HNAE3_MEDIA_TYPE_COPPER: | |
6210 | *port_type = PORT_TP; | |
6211 | break; | |
6212 | case HNAE3_MEDIA_TYPE_UNKNOWN: | |
6213 | default: | |
6214 | *port_type = PORT_OTHER; | |
6215 | break; | |
6216 | } | |
6217 | } | |
6218 | ||
46a3df9f S |
6219 | static const struct hnae3_ae_ops hclge_ops = { |
6220 | .init_ae_dev = hclge_init_ae_dev, | |
6221 | .uninit_ae_dev = hclge_uninit_ae_dev, | |
6222 | .init_client_instance = hclge_init_client_instance, | |
6223 | .uninit_client_instance = hclge_uninit_client_instance, | |
63d7e66f SM |
6224 | .map_ring_to_vector = hclge_map_ring_to_vector, |
6225 | .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, | |
46a3df9f | 6226 | .get_vector = hclge_get_vector, |
7412200c | 6227 | .put_vector = hclge_put_vector, |
46a3df9f | 6228 | .set_promisc_mode = hclge_set_promisc_mode, |
c39c4d98 | 6229 | .set_loopback = hclge_set_loopback, |
46a3df9f S |
6230 | .start = hclge_ae_start, |
6231 | .stop = hclge_ae_stop, | |
6232 | .get_status = hclge_get_status, | |
6233 | .get_ksettings_an_result = hclge_get_ksettings_an_result, | |
6234 | .update_speed_duplex_h = hclge_update_speed_duplex_h, | |
6235 | .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, | |
6236 | .get_media_type = hclge_get_media_type, | |
6237 | .get_rss_key_size = hclge_get_rss_key_size, | |
6238 | .get_rss_indir_size = hclge_get_rss_indir_size, | |
6239 | .get_rss = hclge_get_rss, | |
6240 | .set_rss = hclge_set_rss, | |
f7db940a | 6241 | .set_rss_tuple = hclge_set_rss_tuple, |
07d29954 | 6242 | .get_rss_tuple = hclge_get_rss_tuple, |
46a3df9f S |
6243 | .get_tc_size = hclge_get_tc_size, |
6244 | .get_mac_addr = hclge_get_mac_addr, | |
6245 | .set_mac_addr = hclge_set_mac_addr, | |
6246 | .add_uc_addr = hclge_add_uc_addr, | |
6247 | .rm_uc_addr = hclge_rm_uc_addr, | |
6248 | .add_mc_addr = hclge_add_mc_addr, | |
6249 | .rm_mc_addr = hclge_rm_mc_addr, | |
6250 | .set_autoneg = hclge_set_autoneg, | |
6251 | .get_autoneg = hclge_get_autoneg, | |
6252 | .get_pauseparam = hclge_get_pauseparam, | |
09ea401e | 6253 | .set_pauseparam = hclge_set_pauseparam, |
46a3df9f S |
6254 | .set_mtu = hclge_set_mtu, |
6255 | .reset_queue = hclge_reset_tqp, | |
6256 | .get_stats = hclge_get_stats, | |
6257 | .update_stats = hclge_update_stats, | |
6258 | .get_strings = hclge_get_strings, | |
6259 | .get_sset_count = hclge_get_sset_count, | |
6260 | .get_fw_version = hclge_get_fw_version, | |
6261 | .get_mdix_mode = hclge_get_mdix_mode, | |
d818396d | 6262 | .enable_vlan_filter = hclge_enable_vlan_filter, |
4e66632d | 6263 | .set_vlan_filter = hclge_set_vlan_filter, |
46a3df9f | 6264 | .set_vf_vlan_filter = hclge_set_vf_vlan_filter, |
5f9a7732 | 6265 | .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, |
4ed340ab | 6266 | .reset_event = hclge_reset_event, |
f1f779ce PL |
6267 | .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, |
6268 | .set_channels = hclge_set_channels, | |
4f645a90 | 6269 | .get_channels = hclge_get_channels, |
a2cfbadb | 6270 | .get_flowctrl_adv = hclge_get_flowctrl_adv, |
db2a3e43 FL |
6271 | .get_regs_len = hclge_get_regs_len, |
6272 | .get_regs = hclge_get_regs, | |
d9a0884e | 6273 | .set_led_id = hclge_set_led_id, |
d92ceae9 FL |
6274 | .get_link_mode = hclge_get_link_mode, |
6275 | .get_port_type = hclge_get_port_type, | |
46a3df9f S |
6276 | }; |
6277 | ||
6278 | static struct hnae3_ae_algo ae_algo = { | |
6279 | .ops = &hclge_ops, | |
6280 | .name = HCLGE_NAME, | |
6281 | .pdev_id_table = ae_algo_pci_tbl, | |
6282 | }; | |
6283 | ||
6284 | static int hclge_init(void) | |
6285 | { | |
6286 | pr_info("%s is initializing\n", HCLGE_NAME); | |
6287 | ||
6288 | return hnae3_register_ae_algo(&ae_algo); | |
6289 | } | |
6290 | ||
6291 | static void hclge_exit(void) | |
6292 | { | |
6293 | hnae3_unregister_ae_algo(&ae_algo); | |
6294 | } | |
6295 | module_init(hclge_init); | |
6296 | module_exit(hclge_exit); | |
6297 | ||
6298 | MODULE_LICENSE("GPL"); | |
6299 | MODULE_AUTHOR("Huawei Tech. Co., Ltd."); | |
6300 | MODULE_DESCRIPTION("HCLGE Driver"); | |
6301 | MODULE_VERSION(HCLGE_MOD_VERSION); |