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Revert "UBUNTU: SAUCE: {topost} net: hns3: correct reset event status register"
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
4e2e261d
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
46a3df9f
S		 3
4#include <linux/acpi.h>
5#include <linux/device.h>
6#include <linux/etherdevice.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
7393ed39 14#include <linux/if_vlan.h>
d5752031 15#include <net/rtnetlink.h>
46a3df9f 16#include "hclge_cmd.h"
cacde272 17#include "hclge_dcb.h"
46a3df9f 18#include "hclge_main.h"
0cdbdd3e 19#include "hclge_mbx.h"
46a3df9f
S		 20#include "hclge_mdio.h"
21#include "hclge_tm.h"
22#include "hnae3.h"
23
24#define HCLGE_NAME "hclge"
25#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
26#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
27#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
28#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
29
46a3df9f
S		 30static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
31 enum hclge_mta_dmac_sel_type mta_mac_sel,
32 bool enable);
59bc85ec 33static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 34static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 35static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 36
37static struct hnae3_ae_algo ae_algo;
38
39static const struct pci_device_id ae_algo_pci_tbl[] = {
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 47 /* required last entry */
46a3df9f
S		 48 {0, }
49};
50
28d9cec8
YL		 51MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
52
46a3df9f
S		 53static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
54 "Mac Loopback test",
55 "Serdes Loopback test",
56 "Phy Loopback test"
57};
58
59static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
66 {"igu_rx_uni_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
68 {"igu_rx_multi_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
70 {"igu_rx_broad_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
74 {"egu_tx_uni_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
76 {"egu_tx_multi_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
78 {"egu_tx_broad_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
88 {"ssu_tx_in_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
90 {"ssu_tx_out_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
92 {"ssu_rx_in_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
94 {"ssu_rx_out_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
96};
97
98static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
99 {"igu_rx_err_pkt",
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
105 {"egu_tx_1588_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
111 {"ppp_key_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
113 {"ppp_rlt_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
115 {"ssu_key_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
117 {"pkt_curr_buf_cnt",
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
119 {"qcn_fb_rcv_cnt",
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
121 {"qcn_fb_drop_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
205 {"mb_uncopy_num",
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
221};
222
223static const struct hclge_comm_stats_str g_mac_stats_string[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
f3426583
JS		 280 {"mac_tx_oversize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
b42874e4
JS		 294 {"mac_tx_1519_2047_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
296 {"mac_tx_2048_4095_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
298 {"mac_tx_4096_8191_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
b42874e4
JS		 300 {"mac_tx_8192_9216_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
302 {"mac_tx_9217_12287_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
304 {"mac_tx_12288_16383_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
306 {"mac_tx_1519_max_good_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
308 {"mac_tx_1519_max_bad_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 310 {"mac_rx_total_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
312 {"mac_rx_total_oct_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
314 {"mac_rx_good_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
316 {"mac_rx_bad_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
318 {"mac_rx_good_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
320 {"mac_rx_bad_oct_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
322 {"mac_rx_uni_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
324 {"mac_rx_multi_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
326 {"mac_rx_broad_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
328 {"mac_rx_undersize_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
f3426583
JS		 330 {"mac_rx_oversize_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 332 {"mac_rx_64_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
334 {"mac_rx_65_127_oct_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
336 {"mac_rx_128_255_oct_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
338 {"mac_rx_256_511_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
340 {"mac_rx_512_1023_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
342 {"mac_rx_1024_1518_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
b42874e4
JS		 344 {"mac_rx_1519_2047_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
346 {"mac_rx_2048_4095_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
348 {"mac_rx_4096_8191_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
b42874e4
JS		 350 {"mac_rx_8192_9216_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
352 {"mac_rx_9217_12287_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
354 {"mac_rx_12288_16383_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
356 {"mac_rx_1519_max_good_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
358 {"mac_rx_1519_max_bad_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 360
c36317be
JS		 361 {"mac_tx_fragment_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
363 {"mac_tx_undermin_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
365 {"mac_tx_jabber_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
367 {"mac_tx_err_all_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
369 {"mac_tx_from_app_good_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
371 {"mac_tx_from_app_bad_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
373 {"mac_rx_fragment_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
375 {"mac_rx_undermin_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
377 {"mac_rx_jabber_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
379 {"mac_rx_fcs_err_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
381 {"mac_rx_send_app_good_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
383 {"mac_rx_send_app_bad_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 385};
386
635bfb58
FL		 387static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
388 {
389 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
390 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
391 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
392 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
393 .i_port_bitmap = 0x1,
394 },
395};
396
46a3df9f
S		 397static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
398{
399#define HCLGE_64_BIT_CMD_NUM 5
400#define HCLGE_64_BIT_RTN_DATANUM 4
401 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
402 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 403 __le64 *desc_data;
46a3df9f
S		 404 int i, k, n;
405 int ret;
406
407 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
408 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
409 if (ret) {
410 dev_err(&hdev->pdev->dev,
411 "Get 64 bit pkt stats fail, status = %d.\n", ret);
412 return ret;
413 }
414
415 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
416 if (unlikely(i == 0)) {
a90bb9a5 417 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 418 n = HCLGE_64_BIT_RTN_DATANUM - 1;
419 } else {
a90bb9a5 420 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 421 n = HCLGE_64_BIT_RTN_DATANUM;
422 }
423 for (k = 0; k < n; k++) {
a90bb9a5 424 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 425 desc_data++;
426 }
427 }
428
429 return 0;
430}
431
432static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
433{
434 stats->pkt_curr_buf_cnt = 0;
435 stats->pkt_curr_buf_tc0_cnt = 0;
436 stats->pkt_curr_buf_tc1_cnt = 0;
437 stats->pkt_curr_buf_tc2_cnt = 0;
438 stats->pkt_curr_buf_tc3_cnt = 0;
439 stats->pkt_curr_buf_tc4_cnt = 0;
440 stats->pkt_curr_buf_tc5_cnt = 0;
441 stats->pkt_curr_buf_tc6_cnt = 0;
442 stats->pkt_curr_buf_tc7_cnt = 0;
443}
444
445static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
446{
447#define HCLGE_32_BIT_CMD_NUM 8
448#define HCLGE_32_BIT_RTN_DATANUM 8
449
450 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
451 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 452 __le32 *desc_data;
46a3df9f
S		 453 int i, k, n;
454 u64 *data;
455 int ret;
456
457 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
458 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
459
460 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
461 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
462 if (ret) {
463 dev_err(&hdev->pdev->dev,
464 "Get 32 bit pkt stats fail, status = %d.\n", ret);
465
466 return ret;
467 }
468
469 hclge_reset_partial_32bit_counter(all_32_bit_stats);
470 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
471 if (unlikely(i == 0)) {
a90bb9a5
YL		 472 __le16 *desc_data_16bit;
473
46a3df9f 474 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 475 le32_to_cpu(desc[i].data[0]);
476
477 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 478 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 479 le16_to_cpu(*desc_data_16bit);
480
481 desc_data_16bit++;
46a3df9f 482 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 483 le16_to_cpu(*desc_data_16bit);
46a3df9f 484
a90bb9a5 485 desc_data = &desc[i].data[2];
46a3df9f
S		 486 n = HCLGE_32_BIT_RTN_DATANUM - 4;
487 } else {
a90bb9a5 488 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 489 n = HCLGE_32_BIT_RTN_DATANUM;
490 }
491 for (k = 0; k < n; k++) {
a90bb9a5 492 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 493 desc_data++;
494 }
495 }
496
497 return 0;
498}
499
500static int hclge_mac_update_stats(struct hclge_dev *hdev)
501{
b42874e4 502#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 503#define HCLGE_RTN_DATA_NUM 4
504
505 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
506 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 507 __le64 *desc_data;
46a3df9f
S		 508 int i, k, n;
509 int ret;
510
511 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
512 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
513 if (ret) {
514 dev_err(&hdev->pdev->dev,
515 "Get MAC pkt stats fail, status = %d.\n", ret);
516
517 return ret;
518 }
519
520 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
521 if (unlikely(i == 0)) {
a90bb9a5 522 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 523 n = HCLGE_RTN_DATA_NUM - 2;
524 } else {
a90bb9a5 525 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 526 n = HCLGE_RTN_DATA_NUM;
527 }
528 for (k = 0; k < n; k++) {
a90bb9a5 529 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 530 desc_data++;
531 }
532 }
533
534 return 0;
535}
536
537static int hclge_tqps_update_stats(struct hnae3_handle *handle)
538{
539 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
540 struct hclge_vport *vport = hclge_get_vport(handle);
541 struct hclge_dev *hdev = vport->back;
542 struct hnae3_queue *queue;
543 struct hclge_desc desc[1];
544 struct hclge_tqp *tqp;
545 int ret, i;
546
547 for (i = 0; i < kinfo->num_tqps; i++) {
548 queue = handle->kinfo.tqp[i];
549 tqp = container_of(queue, struct hclge_tqp, q);
550 /* command : HCLGE_OPC_QUERY_IGU_STAT */
551 hclge_cmd_setup_basic_desc(&desc[0],
552 HCLGE_OPC_QUERY_RX_STATUS,
553 true);
554
a90bb9a5 555 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 556 ret = hclge_cmd_send(&hdev->hw, desc, 1);
557 if (ret) {
558 dev_err(&hdev->pdev->dev,
559 "Query tqp stat fail, status = %d,queue = %d\n",
560 ret, i);
561 return ret;
562 }
563 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 564 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 565 }
566
567 for (i = 0; i < kinfo->num_tqps; i++) {
568 queue = handle->kinfo.tqp[i];
569 tqp = container_of(queue, struct hclge_tqp, q);
570 /* command : HCLGE_OPC_QUERY_IGU_STAT */
571 hclge_cmd_setup_basic_desc(&desc[0],
572 HCLGE_OPC_QUERY_TX_STATUS,
573 true);
574
a90bb9a5 575 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 576 ret = hclge_cmd_send(&hdev->hw, desc, 1);
577 if (ret) {
578 dev_err(&hdev->pdev->dev,
579 "Query tqp stat fail, status = %d,queue = %d\n",
580 ret, i);
581 return ret;
582 }
583 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 584 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 585 }
586
587 return 0;
588}
589
590static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
591{
592 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
593 struct hclge_tqp *tqp;
594 u64 *buff = data;
595 int i;
596
597 for (i = 0; i < kinfo->num_tqps; i++) {
598 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 599 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 600 }
601
602 for (i = 0; i < kinfo->num_tqps; i++) {
603 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 604 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 605 }
606
607 return buff;
608}
609
610static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
611{
612 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
613
614 return kinfo->num_tqps * (2);
615}
616
617static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
618{
619 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
620 u8 *buff = data;
621 int i = 0;
622
623 for (i = 0; i < kinfo->num_tqps; i++) {
624 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
625 struct hclge_tqp, q);
c36317be 626 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
46a3df9f
S		 627 tqp->index);
628 buff = buff + ETH_GSTRING_LEN;
629 }
630
631 for (i = 0; i < kinfo->num_tqps; i++) {
632 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
633 struct hclge_tqp, q);
c36317be 634 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
46a3df9f
S		 635 tqp->index);
636 buff = buff + ETH_GSTRING_LEN;
637 }
638
639 return buff;
640}
641
642static u64 *hclge_comm_get_stats(void *comm_stats,
643 const struct hclge_comm_stats_str strs[],
644 int size, u64 *data)
645{
646 u64 *buf = data;
647 u32 i;
648
649 for (i = 0; i < size; i++)
650 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
651
652 return buf + size;
653}
654
655static u8 *hclge_comm_get_strings(u32 stringset,
656 const struct hclge_comm_stats_str strs[],
657 int size, u8 *data)
658{
659 char *buff = (char *)data;
660 u32 i;
661
662 if (stringset != ETH_SS_STATS)
663 return buff;
664
665 for (i = 0; i < size; i++) {
666 snprintf(buff, ETH_GSTRING_LEN,
667 strs[i].desc);
668 buff = buff + ETH_GSTRING_LEN;
669 }
670
671 return (u8 *)buff;
672}
673
674static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
675 struct net_device_stats *net_stats)
676{
677 net_stats->tx_dropped = 0;
678 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
679 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
680 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
681
f3426583 682 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 683 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
46a3df9f
S		 684 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
685 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
c36317be 686 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 687
688 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
689 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
690
c36317be 691 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 692 net_stats->rx_length_errors =
693 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
694 net_stats->rx_length_errors +=
f3426583 695 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 696 net_stats->rx_over_errors =
f3426583 697 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 698}
699
700static void hclge_update_stats_for_all(struct hclge_dev *hdev)
701{
702 struct hnae3_handle *handle;
703 int status;
704
705 handle = &hdev->vport[0].nic;
706 if (handle->client) {
707 status = hclge_tqps_update_stats(handle);
708 if (status) {
709 dev_err(&hdev->pdev->dev,
710 "Update TQPS stats fail, status = %d.\n",
711 status);
712 }
713 }
714
715 status = hclge_mac_update_stats(hdev);
716 if (status)
717 dev_err(&hdev->pdev->dev,
718 "Update MAC stats fail, status = %d.\n", status);
719
720 status = hclge_32_bit_update_stats(hdev);
721 if (status)
722 dev_err(&hdev->pdev->dev,
723 "Update 32 bit stats fail, status = %d.\n",
724 status);
725
726 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
727}
728
729static void hclge_update_stats(struct hnae3_handle *handle,
730 struct net_device_stats *net_stats)
731{
732 struct hclge_vport *vport = hclge_get_vport(handle);
733 struct hclge_dev *hdev = vport->back;
734 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
735 int status;
736
7a5d2a39
JS		 737 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
738 return;
739
46a3df9f
S		 740 status = hclge_mac_update_stats(hdev);
741 if (status)
742 dev_err(&hdev->pdev->dev,
743 "Update MAC stats fail, status = %d.\n",
744 status);
745
746 status = hclge_32_bit_update_stats(hdev);
747 if (status)
748 dev_err(&hdev->pdev->dev,
749 "Update 32 bit stats fail, status = %d.\n",
750 status);
751
752 status = hclge_64_bit_update_stats(hdev);
753 if (status)
754 dev_err(&hdev->pdev->dev,
755 "Update 64 bit stats fail, status = %d.\n",
756 status);
757
758 status = hclge_tqps_update_stats(handle);
759 if (status)
760 dev_err(&hdev->pdev->dev,
761 "Update TQPS stats fail, status = %d.\n",
762 status);
763
764 hclge_update_netstat(hw_stats, net_stats);
7a5d2a39
JS		 765
766 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 767}
768
769static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
770{
771#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
772
773 struct hclge_vport *vport = hclge_get_vport(handle);
774 struct hclge_dev *hdev = vport->back;
775 int count = 0;
776
777 /* Loopback test support rules:
778 * mac: only GE mode support
779 * serdes: all mac mode will support include GE/XGE/LGE/CGE
780 * phy: only support when phy device exist on board
781 */
782 if (stringset == ETH_SS_TEST) {
783 /* clear loopback bit flags at first */
784 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
785 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
786 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
787 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
788 count += 1;
789 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
46a3df9f 790 }
2fd5416a
YL		 791
792 count ++;
793 handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK;
46a3df9f
S		 794 } else if (stringset == ETH_SS_STATS) {
795 count = ARRAY_SIZE(g_mac_stats_string) +
796 ARRAY_SIZE(g_all_32bit_stats_string) +
797 ARRAY_SIZE(g_all_64bit_stats_string) +
798 hclge_tqps_get_sset_count(handle, stringset);
799 }
800
801 return count;
802}
803
804static void hclge_get_strings(struct hnae3_handle *handle,
805 u32 stringset,
806 u8 *data)
807{
808 u8 *p = (char *)data;
809 int size;
810
811 if (stringset == ETH_SS_STATS) {
812 size = ARRAY_SIZE(g_mac_stats_string);
813 p = hclge_comm_get_strings(stringset,
814 g_mac_stats_string,
815 size,
816 p);
817 size = ARRAY_SIZE(g_all_32bit_stats_string);
818 p = hclge_comm_get_strings(stringset,
819 g_all_32bit_stats_string,
820 size,
821 p);
822 size = ARRAY_SIZE(g_all_64bit_stats_string);
823 p = hclge_comm_get_strings(stringset,
824 g_all_64bit_stats_string,
825 size,
826 p);
827 p = hclge_tqps_get_strings(handle, p);
828 } else if (stringset == ETH_SS_TEST) {
829 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
830 memcpy(p,
831 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
832 ETH_GSTRING_LEN);
833 p += ETH_GSTRING_LEN;
834 }
835 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
836 memcpy(p,
837 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
838 ETH_GSTRING_LEN);
839 p += ETH_GSTRING_LEN;
840 }
841 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
842 memcpy(p,
843 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
844 ETH_GSTRING_LEN);
845 p += ETH_GSTRING_LEN;
846 }
847 }
848}
849
850static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
851{
852 struct hclge_vport *vport = hclge_get_vport(handle);
853 struct hclge_dev *hdev = vport->back;
854 u64 *p;
855
856 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
857 g_mac_stats_string,
858 ARRAY_SIZE(g_mac_stats_string),
859 data);
860 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
861 g_all_32bit_stats_string,
862 ARRAY_SIZE(g_all_32bit_stats_string),
863 p);
864 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
865 g_all_64bit_stats_string,
866 ARRAY_SIZE(g_all_64bit_stats_string),
867 p);
868 p = hclge_tqps_get_stats(handle, p);
869}
870
871static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 872 struct hclge_func_status_cmd *status)
46a3df9f
S		 873{
874 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
875 return -EINVAL;
876
877 /* Set the pf to main pf */
878 if (status->pf_state & HCLGE_PF_STATE_MAIN)
879 hdev->flag |= HCLGE_FLAG_MAIN;
880 else
881 hdev->flag &= ~HCLGE_FLAG_MAIN;
882
46a3df9f
S		 883 return 0;
884}
885
886static int hclge_query_function_status(struct hclge_dev *hdev)
887{
d44f9b63 888 struct hclge_func_status_cmd *req;
46a3df9f
S		 889 struct hclge_desc desc;
890 int timeout = 0;
891 int ret;
892
893 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 894 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 895
896 do {
897 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
898 if (ret) {
899 dev_err(&hdev->pdev->dev,
900 "query function status failed %d.\n",
901 ret);
902
903 return ret;
904 }
905
906 /* Check pf reset is done */
907 if (req->pf_state)
908 break;
909 usleep_range(1000, 2000);
910 } while (timeout++ < 5);
911
912 ret = hclge_parse_func_status(hdev, req);
913
914 return ret;
915}
916
917static int hclge_query_pf_resource(struct hclge_dev *hdev)
918{
d44f9b63 919 struct hclge_pf_res_cmd *req;
46a3df9f
S		 920 struct hclge_desc desc;
921 int ret;
922
923 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
924 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
925 if (ret) {
926 dev_err(&hdev->pdev->dev,
927 "query pf resource failed %d.\n", ret);
928 return ret;
929 }
930
d44f9b63 931 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 932 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
933 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
934
e92a0843 935 if (hnae3_dev_roce_supported(hdev)) {
887c3820 936 hdev->num_roce_msi =
e22b531b
HT		 937 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
938 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 939
940 /* PF should have NIC vectors and Roce vectors,
941 * NIC vectors are queued before Roce vectors.
942 */
887c3820 943 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 944 } else {
945 hdev->num_msi =
e22b531b
HT		 946 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
947 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 948 }
949
950 return 0;
951}
952
953static int hclge_parse_speed(int speed_cmd, int *speed)
954{
955 switch (speed_cmd) {
956 case 6:
957 *speed = HCLGE_MAC_SPEED_10M;
958 break;
959 case 7:
960 *speed = HCLGE_MAC_SPEED_100M;
961 break;
962 case 0:
963 *speed = HCLGE_MAC_SPEED_1G;
964 break;
965 case 1:
966 *speed = HCLGE_MAC_SPEED_10G;
967 break;
968 case 2:
969 *speed = HCLGE_MAC_SPEED_25G;
970 break;
971 case 3:
972 *speed = HCLGE_MAC_SPEED_40G;
973 break;
974 case 4:
975 *speed = HCLGE_MAC_SPEED_50G;
976 break;
977 case 5:
978 *speed = HCLGE_MAC_SPEED_100G;
979 break;
980 default:
981 return -EINVAL;
982 }
983
984 return 0;
985}
986
d92ceae9
FL		 987static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
988 u8 speed_ability)
989{
990 unsigned long *supported = hdev->hw.mac.supported;
991
992 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
993 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
994 supported);
995
996 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
997 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
998 supported);
999
1000 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1001 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1002 supported);
1003
1004 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1005 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1006 supported);
1007
1008 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1009 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1010 supported);
1011
1012 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
1013 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1014}
1015
1016static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
1017{
1018 u8 media_type = hdev->hw.mac.media_type;
1019
1020 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
1021 return;
1022
1023 hclge_parse_fiber_link_mode(hdev, speed_ability);
1024}
1025
46a3df9f
S		 1026static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1027{
d44f9b63 1028 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1029 u64 mac_addr_tmp_high;
1030 u64 mac_addr_tmp;
1031 int i;
1032
d44f9b63 1033 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 1034
1035 /* get the configuration */
e22b531b
HT		 1036 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1037 HCLGE_CFG_VMDQ_M,
1038 HCLGE_CFG_VMDQ_S);
1039 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1040 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1041 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1042 HCLGE_CFG_TQP_DESC_N_M,
1043 HCLGE_CFG_TQP_DESC_N_S);
1044
1045 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1046 HCLGE_CFG_PHY_ADDR_M,
1047 HCLGE_CFG_PHY_ADDR_S);
1048 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1049 HCLGE_CFG_MEDIA_TP_M,
1050 HCLGE_CFG_MEDIA_TP_S);
1051 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1052 HCLGE_CFG_RX_BUF_LEN_M,
1053 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 1054 /* get mac_address */
1055 mac_addr_tmp = __le32_to_cpu(req->param[2]);
e22b531b
HT		 1056 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1057 HCLGE_CFG_MAC_ADDR_H_M,
1058 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 1059
1060 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1061
e22b531b
HT		 1062 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1063 HCLGE_CFG_DEFAULT_SPEED_M,
1064 HCLGE_CFG_DEFAULT_SPEED_S);
1065 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1066 HCLGE_CFG_RSS_SIZE_M,
1067 HCLGE_CFG_RSS_SIZE_S);
c408e202 1068
46a3df9f
S		 1069 for (i = 0; i < ETH_ALEN; i++)
1070 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1071
d44f9b63 1072 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 1073 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
d92ceae9 1074
e22b531b
HT		 1075 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1076 HCLGE_CFG_SPEED_ABILITY_M,
1077 HCLGE_CFG_SPEED_ABILITY_S);
46a3df9f
S		 1078}
1079
1080/* hclge_get_cfg: query the static parameter from flash
1081 * @hdev: pointer to struct hclge_dev
1082 * @hcfg: the config structure to be getted
1083 */
1084static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1085{
1086 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 1087 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1088 int i, ret;
1089
1090 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1091 u32 offset = 0;
1092
d44f9b63 1093 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1094 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1095 true);
e22b531b
HT		 1096 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1097 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 1098 /* Len should be united by 4 bytes when send to hardware */
e22b531b
HT		 1099 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1100 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1101 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1102 }
1103
1104 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1105 if (ret) {
e125295a 1106 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
46a3df9f
S		 1107 return ret;
1108 }
1109
1110 hclge_parse_cfg(hcfg, desc);
e125295a 1111
46a3df9f
S		 1112 return 0;
1113}
1114
1115static int hclge_get_cap(struct hclge_dev *hdev)
1116{
1117 int ret;
1118
1119 ret = hclge_query_function_status(hdev);
1120 if (ret) {
1121 dev_err(&hdev->pdev->dev,
1122 "query function status error %d.\n", ret);
1123 return ret;
1124 }
1125
1126 /* get pf resource */
1127 ret = hclge_query_pf_resource(hdev);
e125295a
JS		 1128 if (ret)
1129 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
46a3df9f 1130
e125295a 1131 return ret;
46a3df9f
S		 1132}
1133
1134static int hclge_configure(struct hclge_dev *hdev)
1135{
1136 struct hclge_cfg cfg;
1137 int ret, i;
1138
1139 ret = hclge_get_cfg(hdev, &cfg);
1140 if (ret) {
1141 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1142 return ret;
1143 }
1144
1145 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1146 hdev->base_tqp_pid = 0;
c408e202 1147 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 1148 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1149 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1150 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1151 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1152 hdev->num_desc = cfg.tqp_desc_num;
1153 hdev->tm_info.num_pg = 1;
cacde272 1154 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1155 hdev->tm_info.hw_pfc_map = 0;
1156
1157 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1158 if (ret) {
1159 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1160 return ret;
1161 }
1162
d92ceae9
FL		 1163 hclge_parse_link_mode(hdev, cfg.speed_ability);
1164
cacde272
YL		 1165 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1166 (hdev->tc_max < 1)) {
46a3df9f 1167 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1168 hdev->tc_max);
1169 hdev->tc_max = 1;
46a3df9f
S		 1170 }
1171
cacde272
YL		 1172 /* Dev does not support DCB */
1173 if (!hnae3_dev_dcb_supported(hdev)) {
1174 hdev->tc_max = 1;
1175 hdev->pfc_max = 0;
1176 } else {
1177 hdev->pfc_max = hdev->tc_max;
1178 }
1179
1180 hdev->tm_info.num_tc = hdev->tc_max;
1181
46a3df9f 1182 /* Currently not support uncontiuous tc */
cacde272 1183 for (i = 0; i < hdev->tm_info.num_tc; i++)
e22b531b 1184 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 1185
f8362fe1 1186 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 1187
1188 return ret;
1189}
1190
1191static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1192 int tso_mss_max)
1193{
d44f9b63 1194 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1195 struct hclge_desc desc;
a90bb9a5 1196 u16 tso_mss;
46a3df9f
S		 1197
1198 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1199
d44f9b63 1200 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1201
1202 tso_mss = 0;
e22b531b
HT		 1203 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1204 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1205 req->tso_mss_min = cpu_to_le16(tso_mss);
1206
1207 tso_mss = 0;
e22b531b
HT		 1208 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1209 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1210 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1211
1212 return hclge_cmd_send(&hdev->hw, &desc, 1);
1213}
1214
1215static int hclge_alloc_tqps(struct hclge_dev *hdev)
1216{
1217 struct hclge_tqp *tqp;
1218 int i;
1219
1220 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1221 sizeof(struct hclge_tqp), GFP_KERNEL);
1222 if (!hdev->htqp)
1223 return -ENOMEM;
1224
1225 tqp = hdev->htqp;
1226
1227 for (i = 0; i < hdev->num_tqps; i++) {
1228 tqp->dev = &hdev->pdev->dev;
1229 tqp->index = i;
1230
1231 tqp->q.ae_algo = &ae_algo;
1232 tqp->q.buf_size = hdev->rx_buf_len;
1233 tqp->q.desc_num = hdev->num_desc;
1234 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1235 i * HCLGE_TQP_REG_SIZE;
1236
1237 tqp++;
1238 }
1239
1240 return 0;
1241}
1242
1243static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1244 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1245{
d44f9b63 1246 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1247 struct hclge_desc desc;
1248 int ret;
1249
1250 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1251
d44f9b63 1252 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1253 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1254 req->tqp_vf = func_id;
46a3df9f
S		 1255 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1256 1 << HCLGE_TQP_MAP_EN_B;
1257 req->tqp_vid = cpu_to_le16(tqp_vid);
1258
1259 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a
JS		 1260 if (ret)
1261 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
46a3df9f 1262
e125295a 1263 return ret;
46a3df9f
S		 1264}
1265
1266static int hclge_assign_tqp(struct hclge_vport *vport,
1267 struct hnae3_queue **tqp, u16 num_tqps)
1268{
1269 struct hclge_dev *hdev = vport->back;
7df7dad6 1270 int i, alloced;
46a3df9f
S		 1271
1272 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1273 alloced < num_tqps; i++) {
1274 if (!hdev->htqp[i].alloced) {
1275 hdev->htqp[i].q.handle = &vport->nic;
1276 hdev->htqp[i].q.tqp_index = alloced;
1277 tqp[alloced] = &hdev->htqp[i].q;
1278 hdev->htqp[i].alloced = true;
46a3df9f
S		 1279 alloced++;
1280 }
1281 }
1282 vport->alloc_tqps = num_tqps;
1283
1284 return 0;
1285}
1286
1287static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1288{
1289 struct hnae3_handle *nic = &vport->nic;
1290 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1291 struct hclge_dev *hdev = vport->back;
1292 int i, ret;
1293
1294 kinfo->num_desc = hdev->num_desc;
1295 kinfo->rx_buf_len = hdev->rx_buf_len;
1296 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1297 kinfo->rss_size
1298 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1299 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1300
1301 for (i = 0; i < HNAE3_MAX_TC; i++) {
1302 if (hdev->hw_tc_map & BIT(i)) {
1303 kinfo->tc_info[i].enable = true;
1304 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1305 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1306 kinfo->tc_info[i].tc = i;
1307 } else {
1308 /* Set to default queue if TC is disable */
1309 kinfo->tc_info[i].enable = false;
1310 kinfo->tc_info[i].tqp_offset = 0;
1311 kinfo->tc_info[i].tqp_count = 1;
1312 kinfo->tc_info[i].tc = 0;
1313 }
1314 }
1315
1316 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1317 sizeof(struct hnae3_queue *), GFP_KERNEL);
1318 if (!kinfo->tqp)
1319 return -ENOMEM;
1320
1321 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
e125295a 1322 if (ret)
46a3df9f 1323 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
46a3df9f 1324
e125295a 1325 return ret;
46a3df9f
S		 1326}
1327
7df7dad6
L		 1328static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1329 struct hclge_vport *vport)
1330{
1331 struct hnae3_handle *nic = &vport->nic;
1332 struct hnae3_knic_private_info *kinfo;
1333 u16 i;
1334
1335 kinfo = &nic->kinfo;
1336 for (i = 0; i < kinfo->num_tqps; i++) {
1337 struct hclge_tqp *q =
1338 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1339 bool is_pf;
1340 int ret;
1341
1342 is_pf = !(vport->vport_id);
1343 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1344 i, is_pf);
1345 if (ret)
1346 return ret;
1347 }
1348
1349 return 0;
1350}
1351
1352static int hclge_map_tqp(struct hclge_dev *hdev)
1353{
1354 struct hclge_vport *vport = hdev->vport;
1355 u16 i, num_vport;
1356
1357 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1358 for (i = 0; i < num_vport; i++) {
1359 int ret;
1360
1361 ret = hclge_map_tqp_to_vport(hdev, vport);
1362 if (ret)
1363 return ret;
1364
1365 vport++;
1366 }
1367
1368 return 0;
1369}
1370
46a3df9f
S		 1371static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1372{
1373 /* this would be initialized later */
1374}
1375
1376static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1377{
1378 struct hnae3_handle *nic = &vport->nic;
1379 struct hclge_dev *hdev = vport->back;
1380 int ret;
1381
1382 nic->pdev = hdev->pdev;
1383 nic->ae_algo = &ae_algo;
1384 nic->numa_node_mask = hdev->numa_node_mask;
1385
1386 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1387 ret = hclge_knic_setup(vport, num_tqps);
1388 if (ret) {
1389 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1390 ret);
1391 return ret;
1392 }
1393 } else {
1394 hclge_unic_setup(vport, num_tqps);
1395 }
1396
1397 return 0;
1398}
1399
1400static int hclge_alloc_vport(struct hclge_dev *hdev)
1401{
1402 struct pci_dev *pdev = hdev->pdev;
1403 struct hclge_vport *vport;
1404 u32 tqp_main_vport;
1405 u32 tqp_per_vport;
1406 int num_vport, i;
1407 int ret;
1408
1409 /* We need to alloc a vport for main NIC of PF */
1410 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1411
b76edfb2
HT		 1412 if (hdev->num_tqps < num_vport) {
1413 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1414 hdev->num_tqps, num_vport);
1415 return -EINVAL;
1416 }
46a3df9f
S		 1417
1418 /* Alloc the same number of TQPs for every vport */
1419 tqp_per_vport = hdev->num_tqps / num_vport;
1420 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1421
1422 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1423 GFP_KERNEL);
1424 if (!vport)
1425 return -ENOMEM;
1426
1427 hdev->vport = vport;
1428 hdev->num_alloc_vport = num_vport;
1429
bc59f827
FL		 1430 if (IS_ENABLED(CONFIG_PCI_IOV))
1431 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1432
1433 for (i = 0; i < num_vport; i++) {
1434 vport->back = hdev;
1435 vport->vport_id = i;
1436
1437 if (i == 0)
1438 ret = hclge_vport_setup(vport, tqp_main_vport);
1439 else
1440 ret = hclge_vport_setup(vport, tqp_per_vport);
1441 if (ret) {
1442 dev_err(&pdev->dev,
1443 "vport setup failed for vport %d, %d\n",
1444 i, ret);
1445 return ret;
1446 }
1447
1448 vport++;
1449 }
1450
1451 return 0;
1452}
1453
acf61ecd
YL		 1454static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1455 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1456{
1457/* TX buffer size is unit by 128 byte */
1458#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1459#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1460 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1461 struct hclge_desc desc;
1462 int ret;
1463 u8 i;
1464
d44f9b63 1465 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1466
1467 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1468 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1469 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1470
46a3df9f
S		 1471 req->tx_pkt_buff[i] =
1472 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1473 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1474 }
46a3df9f
S		 1475
1476 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 1477 if (ret)
46a3df9f
S		 1478 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1479 ret);
46a3df9f 1480
e125295a 1481 return ret;
46a3df9f
S		 1482}
1483
acf61ecd
YL		 1484static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1485 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1486{
acf61ecd 1487 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1488
e125295a
JS		 1489 if (ret)
1490 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
46a3df9f 1491
e125295a 1492 return ret;
46a3df9f
S		 1493}
1494
1495static int hclge_get_tc_num(struct hclge_dev *hdev)
1496{
1497 int i, cnt = 0;
1498
1499 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1500 if (hdev->hw_tc_map & BIT(i))
1501 cnt++;
1502 return cnt;
1503}
1504
1505static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1506{
1507 int i, cnt = 0;
1508
1509 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1510 if (hdev->hw_tc_map & BIT(i) &&
1511 hdev->tm_info.hw_pfc_map & BIT(i))
1512 cnt++;
1513 return cnt;
1514}
1515
1516/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1517static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1518 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1519{
1520 struct hclge_priv_buf *priv;
1521 int i, cnt = 0;
1522
1523 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1524 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1525 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1526 priv->enable)
1527 cnt++;
1528 }
1529
1530 return cnt;
1531}
1532
1533/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1534static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1535 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1536{
1537 struct hclge_priv_buf *priv;
1538 int i, cnt = 0;
1539
1540 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1541 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1542 if (hdev->hw_tc_map & BIT(i) &&
1543 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1544 priv->enable)
1545 cnt++;
1546 }
1547
1548 return cnt;
1549}
1550
acf61ecd 1551static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1552{
1553 struct hclge_priv_buf *priv;
1554 u32 rx_priv = 0;
1555 int i;
1556
1557 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1558 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1559 if (priv->enable)
1560 rx_priv += priv->buf_size;
1561 }
1562 return rx_priv;
1563}
1564
acf61ecd 1565static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1566{
1567 u32 i, total_tx_size = 0;
1568
1569 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1570 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1571
1572 return total_tx_size;
1573}
1574
acf61ecd
YL		 1575static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1576 struct hclge_pkt_buf_alloc *buf_alloc,
1577 u32 rx_all)
46a3df9f
S		 1578{
1579 u32 shared_buf_min, shared_buf_tc, shared_std;
1580 int tc_num, pfc_enable_num;
1581 u32 shared_buf;
1582 u32 rx_priv;
1583 int i;
1584
1585 tc_num = hclge_get_tc_num(hdev);
1586 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1587
d221df4e
YL		 1588 if (hnae3_dev_dcb_supported(hdev))
1589 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1590 else
1591 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1592
46a3df9f
S		 1593 shared_buf_tc = pfc_enable_num * hdev->mps +
1594 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1595 hdev->mps;
1596 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1597
acf61ecd 1598 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1599 if (rx_all <= rx_priv + shared_std)
1600 return false;
1601
1602 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1603 buf_alloc->s_buf.buf_size = shared_buf;
1604 buf_alloc->s_buf.self.high = shared_buf;
1605 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1606
1607 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1608 if ((hdev->hw_tc_map & BIT(i)) &&
1609 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1610 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1611 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1612 } else {
acf61ecd
YL		 1613 buf_alloc->s_buf.tc_thrd[i].low = 0;
1614 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1615 }
1616 }
1617
1618 return true;
1619}
1620
acf61ecd
YL		 1621static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1622 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1623{
1624 u32 i, total_size;
1625
1626 total_size = hdev->pkt_buf_size;
1627
1628 /* alloc tx buffer for all enabled tc */
1629 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1630 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1631
1632 if (total_size < HCLGE_DEFAULT_TX_BUF)
1633 return -ENOMEM;
1634
1635 if (hdev->hw_tc_map & BIT(i))
1636 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1637 else
1638 priv->tx_buf_size = 0;
1639
1640 total_size -= priv->tx_buf_size;
1641 }
1642
1643 return 0;
1644}
1645
46a3df9f
S		 1646/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1647 * @hdev: pointer to struct hclge_dev
acf61ecd 1648 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1649 * @return: 0: calculate sucessful, negative: fail
1650 */
1db9b1bf
YL		 1651static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1652 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1653{
9ffe79a9 1654 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1655 int no_pfc_priv_num, pfc_priv_num;
1656 struct hclge_priv_buf *priv;
1657 int i;
1658
acf61ecd 1659 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1660
d602a525
YL		 1661 /* When DCB is not supported, rx private
1662 * buffer is not allocated.
1663 */
1664 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1665 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1666 return -ENOMEM;
1667
1668 return 0;
1669 }
1670
46a3df9f
S		 1671 /* step 1, try to alloc private buffer for all enabled tc */
1672 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1673 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1674 if (hdev->hw_tc_map & BIT(i)) {
1675 priv->enable = 1;
1676 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1677 priv->wl.low = hdev->mps;
1678 priv->wl.high = priv->wl.low + hdev->mps;
1679 priv->buf_size = priv->wl.high +
1680 HCLGE_DEFAULT_DV;
1681 } else {
1682 priv->wl.low = 0;
1683 priv->wl.high = 2 * hdev->mps;
1684 priv->buf_size = priv->wl.high;
1685 }
bb1fe9ea
YL		 1686 } else {
1687 priv->enable = 0;
1688 priv->wl.low = 0;
1689 priv->wl.high = 0;
1690 priv->buf_size = 0;
46a3df9f
S		 1691 }
1692 }
1693
acf61ecd 1694 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1695 return 0;
1696
1697 /* step 2, try to decrease the buffer size of
1698 * no pfc TC's private buffer
1699 */
1700 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1701 priv = &buf_alloc->priv_buf[i];
46a3df9f 1702
bb1fe9ea
YL		 1703 priv->enable = 0;
1704 priv->wl.low = 0;
1705 priv->wl.high = 0;
1706 priv->buf_size = 0;
1707
1708 if (!(hdev->hw_tc_map & BIT(i)))
1709 continue;
1710
1711 priv->enable = 1;
46a3df9f
S		 1712
1713 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1714 priv->wl.low = 128;
1715 priv->wl.high = priv->wl.low + hdev->mps;
1716 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1717 } else {
1718 priv->wl.low = 0;
1719 priv->wl.high = hdev->mps;
1720 priv->buf_size = priv->wl.high;
1721 }
1722 }
1723
acf61ecd 1724 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1725 return 0;
1726
1727 /* step 3, try to reduce the number of pfc disabled TCs,
1728 * which have private buffer
1729 */
1730 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1731 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1732
1733 /* let the last to be cleared first */
1734 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1735 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1736
1737 if (hdev->hw_tc_map & BIT(i) &&
1738 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1739 /* Clear the no pfc TC private buffer */
1740 priv->wl.low = 0;
1741 priv->wl.high = 0;
1742 priv->buf_size = 0;
1743 priv->enable = 0;
1744 no_pfc_priv_num--;
1745 }
1746
acf61ecd 1747 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1748 no_pfc_priv_num == 0)
1749 break;
1750 }
1751
acf61ecd 1752 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1753 return 0;
1754
1755 /* step 4, try to reduce the number of pfc enabled TCs
1756 * which have private buffer.
1757 */
acf61ecd 1758 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1759
1760 /* let the last to be cleared first */
1761 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1762 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1763
1764 if (hdev->hw_tc_map & BIT(i) &&
1765 hdev->tm_info.hw_pfc_map & BIT(i)) {
1766 /* Reduce the number of pfc TC with private buffer */
1767 priv->wl.low = 0;
1768 priv->enable = 0;
1769 priv->wl.high = 0;
1770 priv->buf_size = 0;
1771 pfc_priv_num--;
1772 }
1773
acf61ecd 1774 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1775 pfc_priv_num == 0)
1776 break;
1777 }
acf61ecd 1778 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1779 return 0;
1780
1781 return -ENOMEM;
1782}
1783
acf61ecd
YL		 1784static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1785 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1786{
d44f9b63 1787 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1788 struct hclge_desc desc;
1789 int ret;
1790 int i;
1791
1792 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1793 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1794
1795 /* Alloc private buffer TCs */
1796 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1797 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1798
1799 req->buf_num[i] =
1800 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1801 req->buf_num[i] |=
5bca3b94 1802 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1803 }
1804
b8c8bf47 1805 req->shared_buf =
acf61ecd 1806 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1807 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1808
46a3df9f 1809 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 1810 if (ret)
46a3df9f
S		 1811 dev_err(&hdev->pdev->dev,
1812 "rx private buffer alloc cmd failed %d\n", ret);
46a3df9f 1813
e125295a 1814 return ret;
46a3df9f
S		 1815}
1816
acf61ecd
YL		 1817static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1818 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1819{
1820 struct hclge_rx_priv_wl_buf *req;
1821 struct hclge_priv_buf *priv;
1822 struct hclge_desc desc[2];
1823 int i, j;
1824 int ret;
1825
1826 for (i = 0; i < 2; i++) {
1827 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1828 false);
1829 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1830
1831 /* The first descriptor set the NEXT bit to 1 */
1832 if (i == 0)
1833 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1834 else
1835 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1836
1837 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1838 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1839
1840 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1841 req->tc_wl[j].high =
1842 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1843 req->tc_wl[j].high |=
1b9980c7 1844 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1845 req->tc_wl[j].low =
1846 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1847 req->tc_wl[j].low |=
1b9980c7 1848 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1849 }
1850 }
1851
1852 /* Send 2 descriptor at one time */
1853 ret = hclge_cmd_send(&hdev->hw, desc, 2);
e125295a 1854 if (ret)
46a3df9f
S		 1855 dev_err(&hdev->pdev->dev,
1856 "rx private waterline config cmd failed %d\n",
1857 ret);
e125295a 1858 return ret;
46a3df9f
S		 1859}
1860
acf61ecd
YL		 1861static int hclge_common_thrd_config(struct hclge_dev *hdev,
1862 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1863{
acf61ecd 1864 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1865 struct hclge_rx_com_thrd *req;
1866 struct hclge_desc desc[2];
1867 struct hclge_tc_thrd *tc;
1868 int i, j;
1869 int ret;
1870
1871 for (i = 0; i < 2; i++) {
1872 hclge_cmd_setup_basic_desc(&desc[i],
1873 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1874 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1875
1876 /* The first descriptor set the NEXT bit to 1 */
1877 if (i == 0)
1878 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1879 else
1880 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1881
1882 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1883 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1884
1885 req->com_thrd[j].high =
1886 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1887 req->com_thrd[j].high |=
1b9980c7 1888 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1889 req->com_thrd[j].low =
1890 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1891 req->com_thrd[j].low |=
1b9980c7 1892 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1893 }
1894 }
1895
1896 /* Send 2 descriptors at one time */
1897 ret = hclge_cmd_send(&hdev->hw, desc, 2);
e125295a 1898 if (ret)
46a3df9f
S		 1899 dev_err(&hdev->pdev->dev,
1900 "common threshold config cmd failed %d\n", ret);
e125295a 1901 return ret;
46a3df9f
S		 1902}
1903
acf61ecd
YL		 1904static int hclge_common_wl_config(struct hclge_dev *hdev,
1905 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1906{
acf61ecd 1907 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1908 struct hclge_rx_com_wl *req;
1909 struct hclge_desc desc;
1910 int ret;
1911
1912 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1913
1914 req = (struct hclge_rx_com_wl *)desc.data;
1915 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1b9980c7 1916 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1917
1918 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1b9980c7 1919 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1920
1921 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 1922 if (ret)
46a3df9f
S		 1923 dev_err(&hdev->pdev->dev,
1924 "common waterline config cmd failed %d\n", ret);
e125295a 1925 return ret;
46a3df9f
S		 1926}
1927
1928int hclge_buffer_alloc(struct hclge_dev *hdev)
1929{
acf61ecd 1930 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1931 int ret;
1932
acf61ecd
YL		 1933 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1934 if (!pkt_buf)
46a3df9f
S		 1935 return -ENOMEM;
1936
acf61ecd 1937 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1938 if (ret) {
1939 dev_err(&hdev->pdev->dev,
1940 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1941 goto out;
9ffe79a9
YL		 1942 }
1943
acf61ecd 1944 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1945 if (ret) {
1946 dev_err(&hdev->pdev->dev,
1947 "could not alloc tx buffers %d\n", ret);
acf61ecd 1948 goto out;
46a3df9f
S		 1949 }
1950
acf61ecd 1951 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1952 if (ret) {
1953 dev_err(&hdev->pdev->dev,
1954 "could not calc rx priv buffer size for all TCs %d\n",
1955 ret);
acf61ecd 1956 goto out;
46a3df9f
S		 1957 }
1958
acf61ecd 1959 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1960 if (ret) {
1961 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1962 ret);
acf61ecd 1963 goto out;
46a3df9f
S		 1964 }
1965
2daf4a65 1966 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1967 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1968 if (ret) {
1969 dev_err(&hdev->pdev->dev,
1970 "could not configure rx private waterline %d\n",
1971 ret);
acf61ecd 1972 goto out;
2daf4a65 1973 }
46a3df9f 1974
acf61ecd 1975 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1976 if (ret) {
1977 dev_err(&hdev->pdev->dev,
1978 "could not configure common threshold %d\n",
1979 ret);
acf61ecd 1980 goto out;
2daf4a65 1981 }
46a3df9f
S		 1982 }
1983
acf61ecd
YL		 1984 ret = hclge_common_wl_config(hdev, pkt_buf);
1985 if (ret)
46a3df9f
S		 1986 dev_err(&hdev->pdev->dev,
1987 "could not configure common waterline %d\n", ret);
46a3df9f 1988
acf61ecd
YL		 1989out:
1990 kfree(pkt_buf);
1991 return ret;
46a3df9f
S		 1992}
1993
1994static int hclge_init_roce_base_info(struct hclge_vport *vport)
1995{
1996 struct hnae3_handle *roce = &vport->roce;
1997 struct hnae3_handle *nic = &vport->nic;
1998
887c3820 1999 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 2000
2001 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2002 vport->back->num_msi_left == 0)
2003 return -EINVAL;
2004
2005 roce->rinfo.base_vector = vport->back->roce_base_vector;
2006
2007 roce->rinfo.netdev = nic->kinfo.netdev;
2008 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2009
2010 roce->pdev = nic->pdev;
2011 roce->ae_algo = nic->ae_algo;
2012 roce->numa_node_mask = nic->numa_node_mask;
2013
2014 return 0;
2015}
2016
887c3820 2017static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 2018{
2019 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 2020 int vectors;
2021 int i;
46a3df9f 2022
887c3820
SM		 2023 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2024 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2025 if (vectors < 0) {
2026 dev_err(&pdev->dev,
2027 "failed(%d) to allocate MSI/MSI-X vectors\n",
2028 vectors);
2029 return vectors;
46a3df9f 2030 }
887c3820
SM		 2031 if (vectors < hdev->num_msi)
2032 dev_warn(&hdev->pdev->dev,
2033 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2034 hdev->num_msi, vectors);
46a3df9f 2035
887c3820
SM		 2036 hdev->num_msi = vectors;
2037 hdev->num_msi_left = vectors;
2038 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 2039 hdev->roce_base_vector = hdev->base_msi_vector +
2040 HCLGE_ROCE_VECTOR_OFFSET;
2041
46a3df9f
S		 2042 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2043 sizeof(u16), GFP_KERNEL);
887c3820
SM		 2044 if (!hdev->vector_status) {
2045 pci_free_irq_vectors(pdev);
46a3df9f 2046 return -ENOMEM;
887c3820 2047 }
46a3df9f
S		 2048
2049 for (i = 0; i < hdev->num_msi; i++)
2050 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2051
887c3820
SM		 2052 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2053 sizeof(int), GFP_KERNEL);
2054 if (!hdev->vector_irq) {
2055 pci_free_irq_vectors(pdev);
2056 return -ENOMEM;
46a3df9f 2057 }
46a3df9f
S		 2058
2059 return 0;
2060}
2061
2062static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2063{
2064 struct hclge_mac *mac = &hdev->hw.mac;
2065
2066 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2067 mac->duplex = (u8)duplex;
2068 else
2069 mac->duplex = HCLGE_MAC_FULL;
2070
2071 mac->speed = speed;
2072}
2073
2074int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2075{
d44f9b63 2076 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2077 struct hclge_desc desc;
2078 int ret;
2079
d44f9b63 2080 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2081
2082 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2083
e22b531b 2084 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 2085
2086 switch (speed) {
2087 case HCLGE_MAC_SPEED_10M:
e22b531b
HT		 2088 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2089 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 2090 break;
2091 case HCLGE_MAC_SPEED_100M:
e22b531b
HT		 2092 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2093 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 2094 break;
2095 case HCLGE_MAC_SPEED_1G:
e22b531b
HT		 2096 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2097 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 2098 break;
2099 case HCLGE_MAC_SPEED_10G:
e22b531b
HT		 2100 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2101 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 2102 break;
2103 case HCLGE_MAC_SPEED_25G:
e22b531b
HT		 2104 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2105 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 2106 break;
2107 case HCLGE_MAC_SPEED_40G:
e22b531b
HT		 2108 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2109 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 2110 break;
2111 case HCLGE_MAC_SPEED_50G:
e22b531b
HT		 2112 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2113 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 2114 break;
2115 case HCLGE_MAC_SPEED_100G:
e22b531b
HT		 2116 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2117 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 2118 break;
2119 default:
d7629e74 2120 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2121 return -EINVAL;
2122 }
2123
e22b531b
HT		 2124 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2125 1);
46a3df9f
S		 2126
2127 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2128 if (ret) {
2129 dev_err(&hdev->pdev->dev,
2130 "mac speed/duplex config cmd failed %d.\n", ret);
2131 return ret;
2132 }
2133
2134 hclge_check_speed_dup(hdev, duplex, speed);
2135
2136 return 0;
2137}
2138
2139static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2140 u8 duplex)
2141{
2142 struct hclge_vport *vport = hclge_get_vport(handle);
2143 struct hclge_dev *hdev = vport->back;
2144
2145 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2146}
2147
2148static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2149 u8 *duplex)
2150{
d44f9b63 2151 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2152 struct hclge_desc desc;
2153 int speed_tmp;
2154 int ret;
2155
d44f9b63 2156 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2157
2158 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2159 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2160 if (ret) {
2161 dev_err(&hdev->pdev->dev,
2162 "mac speed/autoneg/duplex query cmd failed %d\n",
2163 ret);
2164 return ret;
2165 }
2166
e22b531b
HT		 2167 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2168 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2169 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 2170
2171 ret = hclge_parse_speed(speed_tmp, speed);
e125295a 2172 if (ret)
46a3df9f
S		 2173 dev_err(&hdev->pdev->dev,
2174 "could not parse speed(=%d), %d\n", speed_tmp, ret);
46a3df9f 2175
e125295a 2176 return ret;
46a3df9f
S		 2177}
2178
46a3df9f
S		 2179static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2180{
d44f9b63 2181 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2182 struct hclge_desc desc;
a90bb9a5 2183 u32 flag = 0;
46a3df9f
S		 2184 int ret;
2185
2186 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2187
d44f9b63 2188 req = (struct hclge_config_auto_neg_cmd *)desc.data;
e22b531b 2189 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 2190 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2191
2192 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 2193 if (ret)
46a3df9f
S		 2194 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2195 ret);
46a3df9f 2196
e125295a 2197 return ret;
46a3df9f
S		 2198}
2199
2200static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2201{
2202 struct hclge_vport *vport = hclge_get_vport(handle);
2203 struct hclge_dev *hdev = vport->back;
2204
2205 return hclge_set_autoneg_en(hdev, enable);
2206}
2207
2208static int hclge_get_autoneg(struct hnae3_handle *handle)
2209{
2210 struct hclge_vport *vport = hclge_get_vport(handle);
2211 struct hclge_dev *hdev = vport->back;
9ff804ee
FL		 2212 struct phy_device *phydev = hdev->hw.mac.phydev;
2213
2214 if (phydev)
2215 return phydev->autoneg;
46a3df9f
S		 2216
2217 return hdev->hw.mac.autoneg;
2218}
2219
6f712727
PL		 2220static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2221 bool mask_vlan,
2222 u8 *mac_mask)
2223{
2224 struct hclge_mac_vlan_mask_entry_cmd *req;
2225 struct hclge_desc desc;
2226 int status;
2227
2228 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2229 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2230
e22b531b
HT		 2231 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2232 mask_vlan ? 1 : 0);
6f712727
PL		 2233 ether_addr_copy(req->mac_mask, mac_mask);
2234
2235 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2236 if (status)
2237 dev_err(&hdev->pdev->dev,
2238 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2239 status);
2240
2241 return status;
2242}
2243
46a3df9f
S		 2244static int hclge_mac_init(struct hclge_dev *hdev)
2245{
59bc85ec
FL		 2246 struct hnae3_handle *handle = &hdev->vport[0].nic;
2247 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 2248 struct hclge_mac *mac = &hdev->hw.mac;
6f712727 2249 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
a832d8b5 2250 struct hclge_vport *vport;
59bc85ec 2251 int mtu;
46a3df9f 2252 int ret;
a832d8b5 2253 int i;
46a3df9f
S		 2254
2255 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2256 if (ret) {
2257 dev_err(&hdev->pdev->dev,
2258 "Config mac speed dup fail ret=%d\n", ret);
2259 return ret;
2260 }
2261
2262 mac->link = 0;
2263
46a3df9f 2264 /* Initialize the MTA table work mode */
46a3df9f
S		 2265 hdev->enable_mta = true;
2266 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2267
2268 ret = hclge_set_mta_filter_mode(hdev,
2269 hdev->mta_mac_sel_type,
2270 hdev->enable_mta);
2271 if (ret) {
2272 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2273 ret);
2274 return ret;
2275 }
2276
a832d8b5
XW		 2277 for (i = 0; i < hdev->num_alloc_vport; i++) {
2278 vport = &hdev->vport[i];
2279 vport->accept_mta_mc = false;
2280
2281 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2282 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2283 if (ret) {
2284 dev_err(&hdev->pdev->dev,
2285 "set mta filter mode fail ret=%d\n", ret);
2286 return ret;
2287 }
6f712727
PL		 2288 }
2289
2290 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
59bc85ec 2291 if (ret) {
6f712727
PL		 2292 dev_err(&hdev->pdev->dev,
2293 "set default mac_vlan_mask fail ret=%d\n", ret);
59bc85ec
FL		 2294 return ret;
2295 }
6f712727 2296
59bc85ec
FL		 2297 if (netdev)
2298 mtu = netdev->mtu;
2299 else
2300 mtu = ETH_DATA_LEN;
2301
2302 ret = hclge_set_mtu(handle, mtu);
e125295a 2303 if (ret)
59bc85ec
FL		 2304 dev_err(&hdev->pdev->dev,
2305 "set mtu failed ret=%d\n", ret);
59bc85ec 2306
e125295a 2307 return ret;
46a3df9f
S		 2308}
2309
22fd3468
SM		 2310static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2311{
2312 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2313 schedule_work(&hdev->mbx_service_task);
2314}
2315
ed4a1bb8
SM		 2316static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2317{
2318 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2319 schedule_work(&hdev->rst_service_task);
2320}
2321
46a3df9f
S		 2322static void hclge_task_schedule(struct hclge_dev *hdev)
2323{
2324 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2325 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2326 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2327 (void)schedule_work(&hdev->service_task);
2328}
2329
2330static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2331{
d44f9b63 2332 struct hclge_link_status_cmd *req;
46a3df9f
S		 2333 struct hclge_desc desc;
2334 int link_status;
2335 int ret;
2336
2337 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2338 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2339 if (ret) {
2340 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2341 ret);
2342 return ret;
2343 }
2344
d44f9b63 2345 req = (struct hclge_link_status_cmd *)desc.data;
b28556c9 2346 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
46a3df9f
S		 2347
2348 return !!link_status;
2349}
2350
2351static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2352{
2353 int mac_state;
2354 int link_stat;
2355
2356 mac_state = hclge_get_mac_link_status(hdev);
2357
2358 if (hdev->hw.mac.phydev) {
2359 if (!genphy_read_status(hdev->hw.mac.phydev))
2360 link_stat = mac_state &
2361 hdev->hw.mac.phydev->link;
2362 else
2363 link_stat = 0;
2364
2365 } else {
2366 link_stat = mac_state;
2367 }
2368
2369 return !!link_stat;
2370}
2371
2372static void hclge_update_link_status(struct hclge_dev *hdev)
2373{
15a50665 2374 struct hnae3_client *rclient = hdev->roce_client;
46a3df9f 2375 struct hnae3_client *client = hdev->nic_client;
bc0b7416 2376 struct hnae3_handle *rhandle;
46a3df9f
S		 2377 struct hnae3_handle *handle;
2378 int state;
2379 int i;
2380
2381 if (!client)
2382 return;
2383 state = hclge_get_mac_phy_link(hdev);
2384 if (state != hdev->hw.mac.link) {
2385 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2386 handle = &hdev->vport[i].nic;
2387 client->ops->link_status_change(handle, state);
bc0b7416 2388 rhandle = &hdev->vport[i].roce;
15a50665 2389 if (rclient && rclient->ops->link_status_change)
bc0b7416
WHX		 2390 rclient->ops->link_status_change(rhandle,
2391 state);
46a3df9f
S		 2392 }
2393 hdev->hw.mac.link = state;
2394 }
2395}
2396
2397static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2398{
2399 struct hclge_mac mac = hdev->hw.mac;
2400 u8 duplex;
2401 int speed;
2402 int ret;
2403
2404 /* get the speed and duplex as autoneg'result from mac cmd when phy
2405 * doesn't exit.
2406 */
c040366b 2407 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2408 return 0;
2409
2410 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2411 if (ret) {
2412 dev_err(&hdev->pdev->dev,
2413 "mac autoneg/speed/duplex query failed %d\n", ret);
2414 return ret;
2415 }
2416
2417 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2418 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2419 if (ret) {
2420 dev_err(&hdev->pdev->dev,
2421 "mac speed/duplex config failed %d\n", ret);
2422 return ret;
2423 }
2424 }
2425
2426 return 0;
2427}
2428
2429static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2430{
2431 struct hclge_vport *vport = hclge_get_vport(handle);
2432 struct hclge_dev *hdev = vport->back;
2433
2434 return hclge_update_speed_duplex(hdev);
2435}
2436
2437static int hclge_get_status(struct hnae3_handle *handle)
2438{
2439 struct hclge_vport *vport = hclge_get_vport(handle);
2440 struct hclge_dev *hdev = vport->back;
2441
2442 hclge_update_link_status(hdev);
2443
2444 return hdev->hw.mac.link;
2445}
2446
d039ef68 2447static void hclge_service_timer(struct timer_list *t)
46a3df9f 2448{
d039ef68 2449 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2450
d039ef68 2451 mod_timer(&hdev->service_timer, jiffies + HZ);
7a5d2a39 2452 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2453 hclge_task_schedule(hdev);
2454}
2455
2456static void hclge_service_complete(struct hclge_dev *hdev)
2457{
2458 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2459
2460 /* Flush memory before next watchdog */
2461 smp_mb__before_atomic();
2462 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2463}
2464
202f2014
SM		 2465static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2466{
2467 u32 rst_src_reg;
22fd3468 2468 u32 cmdq_src_reg;
202f2014
SM		 2469
2470 /* fetch the events from their corresponding regs */
82bd1bef 2471 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
22fd3468
SM		 2472 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2473
2474 /* Assumption: If by any chance reset and mailbox events are reported
2475 * together then we will only process reset event in this go and will
2476 * defer the processing of the mailbox events. Since, we would have not
2477 * cleared RX CMDQ event this time we would receive again another
2478 * interrupt from H/W just for the mailbox.
2479 */
202f2014
SM		 2480
2481 /* check for vector0 reset event sources */
2482 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
79d505d3 2483 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
202f2014
SM		 2484 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2485 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2486 return HCLGE_VECTOR0_EVENT_RST;
2487 }
2488
2489 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
79d505d3 2490 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
202f2014
SM		 2491 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2492 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2493 return HCLGE_VECTOR0_EVENT_RST;
2494 }
2495
2496 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2497 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2498 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2499 return HCLGE_VECTOR0_EVENT_RST;
2500 }
2501
22fd3468
SM		 2502 /* check for vector0 mailbox(=CMDQ RX) event source */
2503 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2504 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2505 *clearval = cmdq_src_reg;
2506 return HCLGE_VECTOR0_EVENT_MBX;
2507 }
202f2014
SM		 2508
2509 return HCLGE_VECTOR0_EVENT_OTHER;
2510}
2511
2512static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2513 u32 regclr)
2514{
22fd3468
SM		 2515 switch (event_type) {
2516 case HCLGE_VECTOR0_EVENT_RST:
202f2014 2517 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
22fd3468
SM		 2518 break;
2519 case HCLGE_VECTOR0_EVENT_MBX:
2520 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2521 break;
2522 }
202f2014
SM		 2523}
2524
466b0c00
L		 2525static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2526{
2527 writel(enable ? 1 : 0, vector->addr);
2528}
2529
2530static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2531{
2532 struct hclge_dev *hdev = data;
202f2014
SM		 2533 u32 event_cause;
2534 u32 clearval;
466b0c00
L		 2535
2536 hclge_enable_vector(&hdev->misc_vector, false);
202f2014
SM		 2537 event_cause = hclge_check_event_cause(hdev, &clearval);
2538
22fd3468 2539 /* vector 0 interrupt is shared with reset and mailbox source events.*/
202f2014
SM		 2540 switch (event_cause) {
2541 case HCLGE_VECTOR0_EVENT_RST:
ed4a1bb8 2542 hclge_reset_task_schedule(hdev);
202f2014 2543 break;
22fd3468
SM		 2544 case HCLGE_VECTOR0_EVENT_MBX:
2545 /* If we are here then,
2546 * 1. Either we are not handling any mbx task and we are not
2547 * scheduled as well
2548 * OR
2549 * 2. We could be handling a mbx task but nothing more is
2550 * scheduled.
2551 * In both cases, we should schedule mbx task as there are more
2552 * mbx messages reported by this interrupt.
2553 */
2554 hclge_mbx_task_schedule(hdev);
40ee4b71 2555 break;
202f2014 2556 default:
40ee4b71
YL		 2557 dev_warn(&hdev->pdev->dev,
2558 "received unknown or unhandled event of vector0\n");
202f2014
SM		 2559 break;
2560 }
2561
e9a50d09
YL		 2562 /* clear the source of interrupt if it is not cause by reset */
2563 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2564 hclge_clear_event_cause(hdev, event_cause, clearval);
2565 hclge_enable_vector(&hdev->misc_vector, true);
2566 }
466b0c00
L		 2567
2568 return IRQ_HANDLED;
2569}
2570
2571static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2572{
617cb5a2
PL		 2573 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2574 dev_warn(&hdev->pdev->dev,
2575 "vector(vector_id %d) has been freed.\n", vector_id);
2576 return;
2577 }
2578
466b0c00
L		 2579 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2580 hdev->num_msi_left += 1;
2581 hdev->num_msi_used -= 1;
2582}
2583
2584static void hclge_get_misc_vector(struct hclge_dev *hdev)
2585{
2586 struct hclge_misc_vector *vector = &hdev->misc_vector;
2587
2588 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2589
2590 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2591 hdev->vector_status[0] = 0;
2592
2593 hdev->num_msi_left -= 1;
2594 hdev->num_msi_used += 1;
2595}
2596
2597static int hclge_misc_irq_init(struct hclge_dev *hdev)
2598{
2599 int ret;
2600
2601 hclge_get_misc_vector(hdev);
2602
202f2014
SM		 2603 /* this would be explicitly freed in the end */
2604 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2605 0, "hclge_misc", hdev);
466b0c00
L		 2606 if (ret) {
2607 hclge_free_vector(hdev, 0);
2608 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2609 hdev->misc_vector.vector_irq);
2610 }
2611
2612 return ret;
2613}
2614
202f2014
SM		 2615static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2616{
2617 free_irq(hdev->misc_vector.vector_irq, hdev);
2618 hclge_free_vector(hdev, 0);
2619}
2620
4ed340ab
L		 2621static int hclge_notify_client(struct hclge_dev *hdev,
2622 enum hnae3_reset_notify_type type)
2623{
3628abd0 2624 struct hnae3_client *rclient = hdev->roce_client;
4ed340ab 2625 struct hnae3_client *client = hdev->nic_client;
d3f5c892
LO		 2626 struct hnae3_handle *handle;
2627 int ret;
4ed340ab
L		 2628 u16 i;
2629
2630 if (!client->ops->reset_notify)
2631 return -EOPNOTSUPP;
2632
2633 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
d3f5c892 2634 handle = &hdev->vport[i].nic;
4ed340ab 2635 ret = client->ops->reset_notify(handle, type);
2e5ed0d2
WHX		 2636 if (ret) {
2637 dev_err(&hdev->pdev->dev,
2638 "notify nic client failed %d", ret);
4ed340ab 2639 return ret;
2e5ed0d2 2640 }
0520c2e5 2641
3628abd0 2642 if (rclient && rclient->ops->reset_notify) {
2643 handle = &hdev->vport[i].roce;
2644 ret = rclient->ops->reset_notify(handle, type);
2645 if (ret) {
2646 dev_err(&hdev->pdev->dev,
2647 "notify roce client failed %d", ret);
2648 return ret;
2649 }
d3f5c892 2650 }
4ed340ab
L		 2651 }
2652
3628abd0 2653 return 0;
4ed340ab
L		 2654}
2655
2656static int hclge_reset_wait(struct hclge_dev *hdev)
2657{
2658#define HCLGE_RESET_WATI_MS 100
2659#define HCLGE_RESET_WAIT_CNT 5
2660 u32 val, reg, reg_bit;
2661 u32 cnt = 0;
2662
2663 switch (hdev->reset_type) {
2664 case HNAE3_GLOBAL_RESET:
2665 reg = HCLGE_GLOBAL_RESET_REG;
2666 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2667 break;
2668 case HNAE3_CORE_RESET:
2669 reg = HCLGE_GLOBAL_RESET_REG;
2670 reg_bit = HCLGE_CORE_RESET_BIT;
2671 break;
2672 case HNAE3_FUNC_RESET:
2673 reg = HCLGE_FUN_RST_ING;
2674 reg_bit = HCLGE_FUN_RST_ING_B;
2675 break;
2676 default:
2677 dev_err(&hdev->pdev->dev,
2678 "Wait for unsupported reset type: %d\n",
2679 hdev->reset_type);
2680 return -EINVAL;
2681 }
2682
2683 val = hclge_read_dev(&hdev->hw, reg);
e22b531b
HT		 2684 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT &&
2685 test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
4ed340ab
L		 2686 msleep(HCLGE_RESET_WATI_MS);
2687 val = hclge_read_dev(&hdev->hw, reg);
2688 cnt++;
2689 }
2690
4ed340ab
L		 2691 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2692 dev_warn(&hdev->pdev->dev,
2693 "Wait for reset timeout: %d\n", hdev->reset_type);
2694 return -EBUSY;
2695 }
2696
2697 return 0;
2698}
2699
13a86fae 2700int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2701{
2702 struct hclge_desc desc;
2703 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2704 int ret;
2705
2706 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
e22b531b 2707 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2708 req->fun_reset_vfid = func_id;
2709
2710 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2711 if (ret)
2712 dev_err(&hdev->pdev->dev,
2713 "send function reset cmd fail, status =%d\n", ret);
2714
2715 return ret;
2716}
2717
d5752031 2718static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2719{
2720 struct pci_dev *pdev = hdev->pdev;
2721 u32 val;
2722
d5752031 2723 switch (hdev->reset_type) {
4ed340ab
L		 2724 case HNAE3_GLOBAL_RESET:
2725 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e22b531b 2726 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2727 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2728 dev_info(&pdev->dev, "Global Reset requested\n");
2729 break;
2730 case HNAE3_CORE_RESET:
2731 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e22b531b 2732 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2733 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2734 dev_info(&pdev->dev, "Core Reset requested\n");
2735 break;
2736 case HNAE3_FUNC_RESET:
2737 dev_info(&pdev->dev, "PF Reset requested\n");
2738 hclge_func_reset_cmd(hdev, 0);
ed4a1bb8
SM		 2739 /* schedule again to check later */
2740 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2741 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2742 break;
2743 default:
2744 dev_warn(&pdev->dev,
d5752031 2745 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2746 break;
2747 }
2748}
2749
d5752031
SM		 2750static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2751 unsigned long *addr)
2752{
2753 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2754
2755 /* return the highest priority reset level amongst all */
2756 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2757 rst_level = HNAE3_GLOBAL_RESET;
2758 else if (test_bit(HNAE3_CORE_RESET, addr))
2759 rst_level = HNAE3_CORE_RESET;
2760 else if (test_bit(HNAE3_IMP_RESET, addr))
2761 rst_level = HNAE3_IMP_RESET;
2762 else if (test_bit(HNAE3_FUNC_RESET, addr))
2763 rst_level = HNAE3_FUNC_RESET;
2764
2765 /* now, clear all other resets */
2766 clear_bit(HNAE3_GLOBAL_RESET, addr);
2767 clear_bit(HNAE3_CORE_RESET, addr);
2768 clear_bit(HNAE3_IMP_RESET, addr);
2769 clear_bit(HNAE3_FUNC_RESET, addr);
2770
2771 return rst_level;
2772}
2773
e9a50d09
YL		 2774static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2775{
2776 u32 clearval = 0;
2777
2778 switch (hdev->reset_type) {
2779 case HNAE3_IMP_RESET:
2780 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2781 break;
2782 case HNAE3_GLOBAL_RESET:
2783 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2784 break;
2785 case HNAE3_CORE_RESET:
2786 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2787 break;
2788 default:
e9a50d09
YL		 2789 break;
2790 }
2791
2792 if (!clearval)
2793 return;
2794
2795 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2796 hclge_enable_vector(&hdev->misc_vector, true);
2797}
2798
d5752031
SM		 2799static void hclge_reset(struct hclge_dev *hdev)
2800{
c7ddaa37
HT		 2801 struct hnae3_handle *handle;
2802
d5752031 2803 /* perform reset of the stack & ae device for a client */
c7ddaa37 2804 handle = &hdev->vport[0].nic;
778daa11 2805 rtnl_lock();
d5752031
SM		 2806 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2807
2808 if (!hclge_reset_wait(hdev)) {
d5752031
SM		 2809 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2810 hclge_reset_ae_dev(hdev->ae_dev);
2811 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
e9a50d09
YL		 2812
2813 hclge_clear_reset_cause(hdev);
d5752031
SM		 2814 } else {
2815 /* schedule again to check pending resets later */
2816 set_bit(hdev->reset_type, &hdev->reset_pending);
2817 hclge_reset_task_schedule(hdev);
2818 }
2819
2820 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
c7ddaa37 2821 handle->last_reset_time = jiffies;
778daa11 2822 rtnl_unlock();
d5752031
SM		 2823}
2824
4aef908d 2825static void hclge_reset_event(struct hnae3_handle *handle)
4ed340ab
L		 2826{
2827 struct hclge_vport *vport = hclge_get_vport(handle);
2828 struct hclge_dev *hdev = vport->back;
2829
4aef908d
SM		 2830 /* check if this is a new reset request and we are not here just because
2831 * last reset attempt did not succeed and watchdog hit us again. We will
2832 * know this if last reset request did not occur very recently (watchdog
2833 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2834 * In case of new request we reset the "reset level" to PF reset.
c7ddaa37
HT		 2835 * And if it is a repeat reset request of the most recent one then we
2836 * want to make sure we throttle the reset request. Therefore, we will
2837 * not allow it again before 3*HZ times.
4aef908d 2838 */
c7ddaa37
HT		 2839 if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2840 return;
2841 else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
4aef908d 2842 handle->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2843
4aef908d
SM		 2844 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2845 handle->reset_level);
2846
2847 /* request reset & schedule reset task */
2848 set_bit(handle->reset_level, &hdev->reset_request);
2849 hclge_reset_task_schedule(hdev);
2850
2851 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2852 handle->reset_level++;
4ed340ab
L		 2853}
2854
2855static void hclge_reset_subtask(struct hclge_dev *hdev)
2856{
d5752031
SM		 2857 /* check if there is any ongoing reset in the hardware. This status can
2858 * be checked from reset_pending. If there is then, we need to wait for
2859 * hardware to complete reset.
2860 * a. If we are able to figure out in reasonable time that hardware
2861 * has fully resetted then, we can proceed with driver, client
2862 * reset.
2863 * b. else, we can come back later to check this status so re-sched
2864 * now.
2865 */
2866 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2867 if (hdev->reset_type != HNAE3_NONE_RESET)
2868 hclge_reset(hdev);
4ed340ab 2869
d5752031
SM		 2870 /* check if we got any *new* reset requests to be honored */
2871 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2872 if (hdev->reset_type != HNAE3_NONE_RESET)
2873 hclge_do_reset(hdev);
4ed340ab 2874
4ed340ab
L		 2875 hdev->reset_type = HNAE3_NONE_RESET;
2876}
2877
ed4a1bb8 2878static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2879{
ed4a1bb8
SM		 2880 struct hclge_dev *hdev =
2881 container_of(work, struct hclge_dev, rst_service_task);
2882
2883 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2884 return;
2885
2886 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2887
4ed340ab 2888 hclge_reset_subtask(hdev);
ed4a1bb8
SM		 2889
2890 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2891}
2892
22fd3468
SM		 2893static void hclge_mailbox_service_task(struct work_struct *work)
2894{
2895 struct hclge_dev *hdev =
2896 container_of(work, struct hclge_dev, mbx_service_task);
2897
2898 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2899 return;
2900
2901 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2902
2903 hclge_mbx_handler(hdev);
2904
2905 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2906}
2907
46a3df9f
S		 2908static void hclge_service_task(struct work_struct *work)
2909{
2910 struct hclge_dev *hdev =
2911 container_of(work, struct hclge_dev, service_task);
2912
7a5d2a39
JS		 2913 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2914 hclge_update_stats_for_all(hdev);
2915 hdev->hw_stats.stats_timer = 0;
2916 }
2917
46a3df9f
S		 2918 hclge_update_speed_duplex(hdev);
2919 hclge_update_link_status(hdev);
46a3df9f
S		 2920 hclge_service_complete(hdev);
2921}
2922
46a3df9f
S		 2923struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2924{
2925 /* VF handle has no client */
2926 if (!handle->client)
2927 return container_of(handle, struct hclge_vport, nic);
2928 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2929 return container_of(handle, struct hclge_vport, roce);
2930 else
2931 return container_of(handle, struct hclge_vport, nic);
2932}
2933
2934static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2935 struct hnae3_vector_info *vector_info)
2936{
2937 struct hclge_vport *vport = hclge_get_vport(handle);
2938 struct hnae3_vector_info *vector = vector_info;
2939 struct hclge_dev *hdev = vport->back;
2940 int alloc = 0;
2941 int i, j;
2942
2943 vector_num = min(hdev->num_msi_left, vector_num);
2944
2945 for (j = 0; j < vector_num; j++) {
2946 for (i = 1; i < hdev->num_msi; i++) {
2947 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2948 vector->vector = pci_irq_vector(hdev->pdev, i);
2949 vector->io_addr = hdev->hw.io_base +
2950 HCLGE_VECTOR_REG_BASE +
2951 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2952 vport->vport_id *
2953 HCLGE_VECTOR_VF_OFFSET;
2954 hdev->vector_status[i] = vport->vport_id;
887c3820 2955 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2956
2957 vector++;
2958 alloc++;
2959
2960 break;
2961 }
2962 }
2963 }
2964 hdev->num_msi_left -= alloc;
2965 hdev->num_msi_used += alloc;
2966
2967 return alloc;
2968}
2969
2970static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2971{
2972 int i;
2973
887c3820
SM		 2974 for (i = 0; i < hdev->num_msi; i++)
2975 if (vector == hdev->vector_irq[i])
2976 return i;
2977
46a3df9f
S		 2978 return -EINVAL;
2979}
2980
7412200c
YL		 2981static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2982{
2983 struct hclge_vport *vport = hclge_get_vport(handle);
2984 struct hclge_dev *hdev = vport->back;
2985 int vector_id;
2986
2987 vector_id = hclge_get_vector_index(hdev, vector);
2988 if (vector_id < 0) {
2989 dev_err(&hdev->pdev->dev,
2990 "Get vector index fail. vector_id =%d\n", vector_id);
2991 return vector_id;
2992 }
2993
2994 hclge_free_vector(hdev, vector_id);
2995
2996 return 0;
2997}
2998
46a3df9f
S		 2999static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
3000{
3001 return HCLGE_RSS_KEY_SIZE;
3002}
3003
3004static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3005{
3006 return HCLGE_RSS_IND_TBL_SIZE;
3007}
3008
46a3df9f
S		 3009static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3010 const u8 hfunc, const u8 *key)
3011{
d44f9b63 3012 struct hclge_rss_config_cmd *req;
46a3df9f
S		 3013 struct hclge_desc desc;
3014 int key_offset;
3015 int key_size;
3016 int ret;
3017
d44f9b63 3018 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 3019
3020 for (key_offset = 0; key_offset < 3; key_offset++) {
3021 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3022 false);
3023
3024 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3025 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3026
3027 if (key_offset == 2)
3028 key_size =
3029 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3030 else
3031 key_size = HCLGE_RSS_HASH_KEY_NUM;
3032
3033 memcpy(req->hash_key,
3034 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3035
3036 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3037 if (ret) {
3038 dev_err(&hdev->pdev->dev,
3039 "Configure RSS config fail, status = %d\n",
3040 ret);
3041 return ret;
3042 }
3043 }
3044 return 0;
3045}
3046
dcd4ef5e 3047static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3048{
d44f9b63 3049 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3050 struct hclge_desc desc;
3051 int i, j;
3052 int ret;
3053
d44f9b63 3054 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3055
3056 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3057 hclge_cmd_setup_basic_desc
3058 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3059
a90bb9a5
YL		 3060 req->start_table_index =
3061 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3062 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3063
3064 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3065 req->rss_result[j] =
3066 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3067
3068 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3069 if (ret) {
3070 dev_err(&hdev->pdev->dev,
3071 "Configure rss indir table fail,status = %d\n",
3072 ret);
3073 return ret;
3074 }
3075 }
3076 return 0;
3077}
3078
3079static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3080 u16 *tc_size, u16 *tc_offset)
3081{
d44f9b63 3082 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3083 struct hclge_desc desc;
3084 int ret;
3085 int i;
3086
3087 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3088 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3089
3090 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3091 u16 mode = 0;
3092
e22b531b
HT		 3093 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3094 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3095 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3096 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3097 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3098
3099 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3100 }
3101
3102 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3103 if (ret)
46a3df9f
S		 3104 dev_err(&hdev->pdev->dev,
3105 "Configure rss tc mode fail, status = %d\n", ret);
46a3df9f 3106
e125295a 3107 return ret;
46a3df9f
S		 3108}
3109
3110static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3111{
d44f9b63 3112 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3113 struct hclge_desc desc;
3114 int ret;
3115
3116 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3117
d44f9b63 3118 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef
YL		 3119
3120 /* Get the tuple cfg from pf */
3121 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3122 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3123 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3124 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3125 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3126 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3127 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3128 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
46a3df9f 3129 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3130 if (ret)
46a3df9f
S		 3131 dev_err(&hdev->pdev->dev,
3132 "Configure rss input fail, status = %d\n", ret);
e125295a 3133 return ret;
46a3df9f
S		 3134}
3135
3136static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3137 u8 *key, u8 *hfunc)
3138{
3139 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3140 int i;
3141
3142 /* Get hash algorithm */
3143 if (hfunc)
dcd4ef5e 3144 *hfunc = vport->rss_algo;
46a3df9f
S		 3145
3146 /* Get the RSS Key required by the user */
3147 if (key)
3148 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3149
3150 /* Get indirect table */
3151 if (indir)
3152 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3153 indir[i] = vport->rss_indirection_tbl[i];
3154
3155 return 0;
3156}
3157
3158static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3159 const u8 *key, const u8 hfunc)
3160{
3161 struct hclge_vport *vport = hclge_get_vport(handle);
3162 struct hclge_dev *hdev = vport->back;
3163 u8 hash_algo;
3164 int ret, i;
3165
3166 /* Set the RSS Hash Key if specififed by the user */
3167 if (key) {
46a3df9f
S		 3168
3169 if (hfunc == ETH_RSS_HASH_TOP ||
3170 hfunc == ETH_RSS_HASH_NO_CHANGE)
3171 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3172 else
3173 return -EINVAL;
3174 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3175 if (ret)
3176 return ret;
dcd4ef5e
YL		 3177
3178 /* Update the shadow RSS key with user specified qids */
3179 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3180 vport->rss_algo = hash_algo;
46a3df9f
S		 3181 }
3182
3183 /* Update the shadow RSS table with user specified qids */
3184 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3185 vport->rss_indirection_tbl[i] = indir[i];
3186
3187 /* Update the hardware */
dcd4ef5e 3188 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3189}
3190
f7db940a
L		 3191static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3192{
3193 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3194
3195 if (nfc->data & RXH_L4_B_2_3)
3196 hash_sets |= HCLGE_D_PORT_BIT;
3197 else
3198 hash_sets &= ~HCLGE_D_PORT_BIT;
3199
3200 if (nfc->data & RXH_IP_SRC)
3201 hash_sets |= HCLGE_S_IP_BIT;
3202 else
3203 hash_sets &= ~HCLGE_S_IP_BIT;
3204
3205 if (nfc->data & RXH_IP_DST)
3206 hash_sets |= HCLGE_D_IP_BIT;
3207 else
3208 hash_sets &= ~HCLGE_D_IP_BIT;
3209
3210 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3211 hash_sets |= HCLGE_V_TAG_BIT;
3212
3213 return hash_sets;
3214}
3215
3216static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3217 struct ethtool_rxnfc *nfc)
3218{
3219 struct hclge_vport *vport = hclge_get_vport(handle);
3220 struct hclge_dev *hdev = vport->back;
3221 struct hclge_rss_input_tuple_cmd *req;
3222 struct hclge_desc desc;
3223 u8 tuple_sets;
3224 int ret;
3225
3226 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3227 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3228 return -EINVAL;
3229
3230 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef 3231 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 3232
637053ef
YL		 3233 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3234 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3235 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3236 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3237 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3238 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3239 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3240 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 3241
3242 tuple_sets = hclge_get_rss_hash_bits(nfc);
3243 switch (nfc->flow_type) {
3244 case TCP_V4_FLOW:
3245 req->ipv4_tcp_en = tuple_sets;
3246 break;
3247 case TCP_V6_FLOW:
3248 req->ipv6_tcp_en = tuple_sets;
3249 break;
3250 case UDP_V4_FLOW:
3251 req->ipv4_udp_en = tuple_sets;
3252 break;
3253 case UDP_V6_FLOW:
3254 req->ipv6_udp_en = tuple_sets;
3255 break;
3256 case SCTP_V4_FLOW:
3257 req->ipv4_sctp_en = tuple_sets;
3258 break;
3259 case SCTP_V6_FLOW:
3260 if ((nfc->data & RXH_L4_B_0_1) ||
3261 (nfc->data & RXH_L4_B_2_3))
3262 return -EINVAL;
3263
3264 req->ipv6_sctp_en = tuple_sets;
3265 break;
3266 case IPV4_FLOW:
3267 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3268 break;
3269 case IPV6_FLOW:
3270 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3271 break;
3272 default:
3273 return -EINVAL;
3274 }
3275
3276 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
637053ef 3277 if (ret) {
f7db940a
L		 3278 dev_err(&hdev->pdev->dev,
3279 "Set rss tuple fail, status = %d\n", ret);
637053ef
YL		 3280 return ret;
3281 }
f7db940a 3282
637053ef
YL		 3283 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3284 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3285 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3286 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3287 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3288 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3289 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3290 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3291 return 0;
f7db940a
L		 3292}
3293
07d29954
L		 3294static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3295 struct ethtool_rxnfc *nfc)
3296{
3297 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3298 u8 tuple_sets;
07d29954
L		 3299
3300 nfc->data = 0;
3301
07d29954
L		 3302 switch (nfc->flow_type) {
3303 case TCP_V4_FLOW:
637053ef 3304 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3305 break;
3306 case UDP_V4_FLOW:
637053ef 3307 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3308 break;
3309 case TCP_V6_FLOW:
637053ef 3310 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3311 break;
3312 case UDP_V6_FLOW:
637053ef 3313 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3314 break;
3315 case SCTP_V4_FLOW:
637053ef 3316 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3317 break;
3318 case SCTP_V6_FLOW:
637053ef 3319 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3320 break;
3321 case IPV4_FLOW:
3322 case IPV6_FLOW:
3323 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3324 break;
3325 default:
3326 return -EINVAL;
3327 }
3328
3329 if (!tuple_sets)
3330 return 0;
3331
3332 if (tuple_sets & HCLGE_D_PORT_BIT)
3333 nfc->data |= RXH_L4_B_2_3;
3334 if (tuple_sets & HCLGE_S_PORT_BIT)
3335 nfc->data |= RXH_L4_B_0_1;
3336 if (tuple_sets & HCLGE_D_IP_BIT)
3337 nfc->data |= RXH_IP_DST;
3338 if (tuple_sets & HCLGE_S_IP_BIT)
3339 nfc->data |= RXH_IP_SRC;
3340
3341 return 0;
3342}
3343
46a3df9f
S		 3344static int hclge_get_tc_size(struct hnae3_handle *handle)
3345{
3346 struct hclge_vport *vport = hclge_get_vport(handle);
3347 struct hclge_dev *hdev = vport->back;
3348
3349 return hdev->rss_size_max;
3350}
3351
77f255c1 3352int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3353{
46a3df9f 3354 struct hclge_vport *vport = hdev->vport;
8015bb74
YL		 3355 u8 *rss_indir = vport[0].rss_indirection_tbl;
3356 u16 rss_size = vport[0].alloc_rss_size;
3357 u8 *key = vport[0].rss_hash_key;
3358 u8 hfunc = vport[0].rss_algo;
46a3df9f 3359 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3360 u16 tc_valid[HCLGE_MAX_TC_NUM];
3361 u16 tc_size[HCLGE_MAX_TC_NUM];
8015bb74
YL		 3362 u16 roundup_size;
3363 int i, ret;
68ece54e 3364
46a3df9f
S		 3365 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3366 if (ret)
8015bb74 3367 return ret;
46a3df9f 3368
46a3df9f
S		 3369 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3370 if (ret)
8015bb74 3371 return ret;
46a3df9f
S		 3372
3373 ret = hclge_set_rss_input_tuple(hdev);
3374 if (ret)
8015bb74 3375 return ret;
46a3df9f 3376
68ece54e
YL		 3377 /* Each TC have the same queue size, and tc_size set to hardware is
3378 * the log2 of roundup power of two of rss_size, the acutal queue
3379 * size is limited by indirection table.
3380 */
3381 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3382 dev_err(&hdev->pdev->dev,
3383 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3384 rss_size);
8015bb74 3385 return -EINVAL;
68ece54e
YL		 3386 }
3387
3388 roundup_size = roundup_pow_of_two(rss_size);
3389 roundup_size = ilog2(roundup_size);
3390
46a3df9f 3391 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3392 tc_valid[i] = 0;
46a3df9f 3393
68ece54e
YL		 3394 if (!(hdev->hw_tc_map & BIT(i)))
3395 continue;
3396
3397 tc_valid[i] = 1;
3398 tc_size[i] = roundup_size;
3399 tc_offset[i] = rss_size * i;
46a3df9f 3400 }
68ece54e 3401
8015bb74
YL		 3402 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3403}
46a3df9f 3404
8015bb74
YL		 3405void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3406{
3407 struct hclge_vport *vport = hdev->vport;
3408 int i, j;
46a3df9f 3409
8015bb74
YL		 3410 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3411 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3412 vport[j].rss_indirection_tbl[i] =
3413 i % vport[j].alloc_rss_size;
3414 }
3415}
3416
3417static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3418{
3419 struct hclge_vport *vport = hdev->vport;
3420 int i;
3421
8015bb74
YL		 3422 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3423 vport[i].rss_tuple_sets.ipv4_tcp_en =
3424 HCLGE_RSS_INPUT_TUPLE_OTHER;
3425 vport[i].rss_tuple_sets.ipv4_udp_en =
3426 HCLGE_RSS_INPUT_TUPLE_OTHER;
3427 vport[i].rss_tuple_sets.ipv4_sctp_en =
3428 HCLGE_RSS_INPUT_TUPLE_SCTP;
3429 vport[i].rss_tuple_sets.ipv4_fragment_en =
3430 HCLGE_RSS_INPUT_TUPLE_OTHER;
3431 vport[i].rss_tuple_sets.ipv6_tcp_en =
3432 HCLGE_RSS_INPUT_TUPLE_OTHER;
3433 vport[i].rss_tuple_sets.ipv6_udp_en =
3434 HCLGE_RSS_INPUT_TUPLE_OTHER;
3435 vport[i].rss_tuple_sets.ipv6_sctp_en =
3436 HCLGE_RSS_INPUT_TUPLE_SCTP;
3437 vport[i].rss_tuple_sets.ipv6_fragment_en =
3438 HCLGE_RSS_INPUT_TUPLE_OTHER;
3439
3440 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
823fe868
FL		 3441
3442 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
8015bb74
YL		 3443 }
3444
3445 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3446}
3447
63d7e66f
SM		 3448int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3449 int vector_id, bool en,
3450 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3451{
3452 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3453 struct hnae3_ring_chain_node *node;
3454 struct hclge_desc desc;
63d7e66f
SM		 3455 struct hclge_ctrl_vector_chain_cmd *req
3456 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3457 enum hclge_cmd_status status;
3458 enum hclge_opcode_type op;
3459 u16 tqp_type_and_id;
46a3df9f
S		 3460 int i;
3461
63d7e66f
SM		 3462 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3463 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3464 req->int_vector_id = vector_id;
3465
3466 i = 0;
3467 for (node = ring_chain; node; node = node->next) {
63d7e66f 3468 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
e22b531b
HT		 3469 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3470 HCLGE_INT_TYPE_S,
3471 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3472 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3473 HCLGE_TQP_ID_S, node->tqp_index);
3474 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3475 HCLGE_INT_GL_IDX_S,
3476 hnae3_get_field(node->int_gl_idx,
3477 HNAE3_RING_GL_IDX_M,
3478 HNAE3_RING_GL_IDX_S));
63d7e66f 3479 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3480 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3481 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
63d7e66f 3482 req->vfid = vport->vport_id;
46a3df9f 3483
63d7e66f
SM		 3484 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3485 if (status) {
46a3df9f
S		 3486 dev_err(&hdev->pdev->dev,
3487 "Map TQP fail, status is %d.\n",
63d7e66f
SM		 3488 status);
3489 return -EIO;
46a3df9f
S		 3490 }
3491 i = 0;
3492
3493 hclge_cmd_setup_basic_desc(&desc,
63d7e66f 3494 op,
46a3df9f
S		 3495 false);
3496 req->int_vector_id = vector_id;
3497 }
3498 }
3499
3500 if (i > 0) {
3501 req->int_cause_num = i;
63d7e66f
SM		 3502 req->vfid = vport->vport_id;
3503 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3504 if (status) {
46a3df9f 3505 dev_err(&hdev->pdev->dev,
63d7e66f
SM		 3506 "Map TQP fail, status is %d.\n", status);
3507 return -EIO;
46a3df9f
S		 3508 }
3509 }
3510
3511 return 0;
3512}
3513
63d7e66f
SM		 3514static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3515 int vector,
3516 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3517{
3518 struct hclge_vport *vport = hclge_get_vport(handle);
3519 struct hclge_dev *hdev = vport->back;
3520 int vector_id;
3521
3522 vector_id = hclge_get_vector_index(hdev, vector);
3523 if (vector_id < 0) {
3524 dev_err(&hdev->pdev->dev,
63d7e66f 3525 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3526 return vector_id;
3527 }
3528
63d7e66f 3529 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3530}
3531
63d7e66f
SM		 3532static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3533 int vector,
3534 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3535{
3536 struct hclge_vport *vport = hclge_get_vport(handle);
3537 struct hclge_dev *hdev = vport->back;
63d7e66f 3538 int vector_id, ret;
46a3df9f 3539
f9637cc2
PL		 3540 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3541 return 0;
3542
46a3df9f
S		 3543 vector_id = hclge_get_vector_index(hdev, vector);
3544 if (vector_id < 0) {
3545 dev_err(&handle->pdev->dev,
3546 "Get vector index fail. ret =%d\n", vector_id);
3547 return vector_id;
3548 }
3549
63d7e66f 3550 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
7412200c 3551 if (ret)
63d7e66f
SM		 3552 dev_err(&handle->pdev->dev,
3553 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3554 vector_id,
3555 ret);
46a3df9f 3556
7412200c 3557 return ret;
46a3df9f
S		 3558}
3559
3560int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3561 struct hclge_promisc_param *param)
3562{
d44f9b63 3563 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3564 struct hclge_desc desc;
3565 int ret;
3566
3567 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3568
d44f9b63 3569 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3570 req->vf_id = param->vf_id;
4771e104
PL		 3571
3572 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3573 * pdev revision(0x20), new revision support them. The
3574 * value of this two fields will not return error when driver
3575 * send command to fireware in revision(0x20).
3576 */
3577 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3578 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3579
3580 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3581 if (ret)
46a3df9f
S		 3582 dev_err(&hdev->pdev->dev,
3583 "Set promisc mode fail, status is %d.\n", ret);
e125295a
JS		 3584
3585 return ret;
46a3df9f
S		 3586}
3587
3588void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3589 bool en_mc, bool en_bc, int vport_id)
3590{
3591 if (!param)
3592 return;
3593
3594 memset(param, 0, sizeof(struct hclge_promisc_param));
3595 if (en_uc)
3596 param->enable = HCLGE_PROMISC_EN_UC;
3597 if (en_mc)
3598 param->enable |= HCLGE_PROMISC_EN_MC;
3599 if (en_bc)
3600 param->enable |= HCLGE_PROMISC_EN_BC;
3601 param->vf_id = vport_id;
3602}
3603
e8600a3d
PL		 3604static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3605 bool en_mc_pmc)
46a3df9f
S		 3606{
3607 struct hclge_vport *vport = hclge_get_vport(handle);
3608 struct hclge_dev *hdev = vport->back;
3609 struct hclge_promisc_param param;
3610
e8600a3d
PL		 3611 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3612 vport->vport_id);
46a3df9f
S		 3613 hclge_cmd_set_promisc_mode(hdev, &param);
3614}
3615
3616static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3617{
3618 struct hclge_desc desc;
d44f9b63
YL		 3619 struct hclge_config_mac_mode_cmd *req =
3620 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3621 u32 loop_en = 0;
46a3df9f
S		 3622 int ret;
3623
3624 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
e22b531b
HT		 3625 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3626 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3627 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3628 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3629 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3630 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3631 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3632 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3633 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3634 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3635 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3636 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3637 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3638 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 3639 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3640
3641 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3642 if (ret)
3643 dev_err(&hdev->pdev->dev,
3644 "mac enable fail, ret =%d.\n", ret);
3645}
3646
e67d9ce9 3647static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 3648{
c39c4d98 3649 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 3650 struct hclge_desc desc;
3651 u32 loop_en;
3652 int ret;
3653
e67d9ce9
YL		 3654 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3655 /* 1 Read out the MAC mode config at first */
3656 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3657 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3658 if (ret) {
3659 dev_err(&hdev->pdev->dev,
3660 "mac loopback get fail, ret =%d.\n", ret);
3661 return ret;
3662 }
c39c4d98 3663
e67d9ce9
YL		 3664 /* 2 Then setup the loopback flag */
3665 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
e22b531b 3666 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
e67d9ce9
YL		 3667
3668 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 3669
e67d9ce9
YL		 3670 /* 3 Config mac work mode with loopback flag
3671 * and its original configure parameters
3672 */
3673 hclge_cmd_reuse_desc(&desc, false);
3674 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3675 if (ret)
3676 dev_err(&hdev->pdev->dev,
3677 "mac loopback set fail, ret =%d.\n", ret);
3678 return ret;
3679}
c39c4d98 3680
2fd5416a
YL		 3681static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en)
3682{
3683#define HCLGE_SERDES_RETRY_MS 10
3684#define HCLGE_SERDES_RETRY_NUM 100
3685 struct hclge_serdes_lb_cmd *req;
3686 struct hclge_desc desc;
3687 int ret, i = 0;
3688
3689 req = (struct hclge_serdes_lb_cmd *)&desc.data[0];
3690 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
3691
3692 if (en) {
3693 req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3694 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3695 } else {
3696 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3697 }
3698
3699 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3700 if (ret) {
3701 dev_err(&hdev->pdev->dev,
3702 "serdes loopback set fail, ret = %d\n", ret);
3703 return ret;
3704 }
3705
3706 do {
3707 msleep(HCLGE_SERDES_RETRY_MS);
3708 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3709 true);
3710 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3711 if (ret) {
3712 dev_err(&hdev->pdev->dev,
3713 "serdes loopback get, ret = %d\n", ret);
3714 return ret;
3715 }
3716 } while (++i < HCLGE_SERDES_RETRY_NUM &&
3717 !(req->result & HCLGE_CMD_SERDES_DONE_B));
3718
3719 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3720 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3721 return -EBUSY;
3722 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3723 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3724 return -EIO;
3725 }
3726
3727 return 0;
3728}
3729
e67d9ce9
YL		 3730static int hclge_set_loopback(struct hnae3_handle *handle,
3731 enum hnae3_loop loop_mode, bool en)
3732{
3733 struct hclge_vport *vport = hclge_get_vport(handle);
3734 struct hclge_dev *hdev = vport->back;
3735 int ret;
3736
3737 switch (loop_mode) {
3738 case HNAE3_MAC_INTER_LOOP_MAC:
3739 ret = hclge_set_mac_loopback(hdev, en);
c39c4d98 3740 break;
2fd5416a
YL		 3741 case HNAE3_MAC_INTER_LOOP_SERDES:
3742 ret = hclge_set_serdes_loopback(hdev, en);
3743 break;
c39c4d98
YL		 3744 default:
3745 ret = -ENOTSUPP;
3746 dev_err(&hdev->pdev->dev,
3747 "loop_mode %d is not supported\n", loop_mode);
3748 break;
3749 }
3750
3751 return ret;
3752}
3753
46a3df9f
S		 3754static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3755 int stream_id, bool enable)
3756{
3757 struct hclge_desc desc;
d44f9b63
YL		 3758 struct hclge_cfg_com_tqp_queue_cmd *req =
3759 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3760 int ret;
3761
3762 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3763 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3764 req->stream_id = cpu_to_le16(stream_id);
3765 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3766
3767 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3768 if (ret)
3769 dev_err(&hdev->pdev->dev,
3770 "Tqp enable fail, status =%d.\n", ret);
3771 return ret;
3772}
3773
3774static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3775{
3776 struct hclge_vport *vport = hclge_get_vport(handle);
3777 struct hnae3_queue *queue;
3778 struct hclge_tqp *tqp;
3779 int i;
3780
3781 for (i = 0; i < vport->alloc_tqps; i++) {
3782 queue = handle->kinfo.tqp[i];
3783 tqp = container_of(queue, struct hclge_tqp, q);
3784 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3785 }
3786}
3787
3788static int hclge_ae_start(struct hnae3_handle *handle)
3789{
3790 struct hclge_vport *vport = hclge_get_vport(handle);
3791 struct hclge_dev *hdev = vport->back;
e5e89cda 3792 int i, ret;
46a3df9f 3793
e5e89cda
PL		 3794 for (i = 0; i < vport->alloc_tqps; i++)
3795 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3796
46a3df9f
S		 3797 /* mac enable */
3798 hclge_cfg_mac_mode(hdev, true);
3799 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3800 mod_timer(&hdev->service_timer, jiffies + HZ);
3ae84019 3801 hdev->hw.mac.link = 0;
46a3df9f 3802
f9637cc2
PL		 3803 /* reset tqp stats */
3804 hclge_reset_tqp_stats(handle);
3805
46a3df9f
S		 3806 ret = hclge_mac_start_phy(hdev);
3807 if (ret)
3808 return ret;
3809
46a3df9f
S		 3810 return 0;
3811}
3812
3813static void hclge_ae_stop(struct hnae3_handle *handle)
3814{
3815 struct hclge_vport *vport = hclge_get_vport(handle);
3816 struct hclge_dev *hdev = vport->back;
e5e89cda 3817 int i;
46a3df9f 3818
f9637cc2
PL		 3819 del_timer_sync(&hdev->service_timer);
3820 cancel_work_sync(&hdev->service_task);
42b11ab7 3821 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
f9637cc2 3822
4486f5c9
YL		 3823 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3824 hclge_mac_stop_phy(hdev);
f9637cc2 3825 return;
4486f5c9 3826 }
f9637cc2 3827
e5e89cda
PL		 3828 for (i = 0; i < vport->alloc_tqps; i++)
3829 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3830
46a3df9f
S		 3831 /* Mac disable */
3832 hclge_cfg_mac_mode(hdev, false);
3833
3834 hclge_mac_stop_phy(hdev);
3835
3836 /* reset tqp stats */
3837 hclge_reset_tqp_stats(handle);
b91fb71c
FL		 3838 del_timer_sync(&hdev->service_timer);
3839 cancel_work_sync(&hdev->service_task);
3840 hclge_update_link_status(hdev);
46a3df9f
S		 3841}
3842
3843static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3844 u16 cmdq_resp, u8 resp_code,
3845 enum hclge_mac_vlan_tbl_opcode op)
3846{
3847 struct hclge_dev *hdev = vport->back;
3848 int return_status = -EIO;
3849
3850 if (cmdq_resp) {
3851 dev_err(&hdev->pdev->dev,
3852 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3853 cmdq_resp);
3854 return -EIO;
3855 }
3856
3857 if (op == HCLGE_MAC_VLAN_ADD) {
3858 if ((!resp_code) || (resp_code == 1)) {
3859 return_status = 0;
3860 } else if (resp_code == 2) {
2f894c5b 3861 return_status = -ENOSPC;
46a3df9f
S		 3862 dev_err(&hdev->pdev->dev,
3863 "add mac addr failed for uc_overflow.\n");
3864 } else if (resp_code == 3) {
2f894c5b 3865 return_status = -ENOSPC;
46a3df9f
S		 3866 dev_err(&hdev->pdev->dev,
3867 "add mac addr failed for mc_overflow.\n");
3868 } else {
3869 dev_err(&hdev->pdev->dev,
3870 "add mac addr failed for undefined, code=%d.\n",
3871 resp_code);
3872 }
3873 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3874 if (!resp_code) {
3875 return_status = 0;
3876 } else if (resp_code == 1) {
2f894c5b 3877 return_status = -ENOENT;
46a3df9f
S		 3878 dev_dbg(&hdev->pdev->dev,
3879 "remove mac addr failed for miss.\n");
3880 } else {
3881 dev_err(&hdev->pdev->dev,
3882 "remove mac addr failed for undefined, code=%d.\n",
3883 resp_code);
3884 }
3885 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3886 if (!resp_code) {
3887 return_status = 0;
3888 } else if (resp_code == 1) {
2f894c5b 3889 return_status = -ENOENT;
46a3df9f
S		 3890 dev_dbg(&hdev->pdev->dev,
3891 "lookup mac addr failed for miss.\n");
3892 } else {
3893 dev_err(&hdev->pdev->dev,
3894 "lookup mac addr failed for undefined, code=%d.\n",
3895 resp_code);
3896 }
3897 } else {
2f894c5b 3898 return_status = -EINVAL;
46a3df9f
S		 3899 dev_err(&hdev->pdev->dev,
3900 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3901 op);
3902 }
3903
3904 return return_status;
3905}
3906
3907static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3908{
3909 int word_num;
3910 int bit_num;
3911
3912 if (vfid > 255 || vfid < 0)
3913 return -EIO;
3914
3915 if (vfid >= 0 && vfid <= 191) {
3916 word_num = vfid / 32;
3917 bit_num = vfid % 32;
3918 if (clr)
a90bb9a5 3919 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3920 else
a90bb9a5 3921 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3922 } else {
3923 word_num = (vfid - 192) / 32;
3924 bit_num = vfid % 32;
3925 if (clr)
a90bb9a5 3926 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3927 else
a90bb9a5 3928 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3929 }
3930
3931 return 0;
3932}
3933
3934static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3935{
3936#define HCLGE_DESC_NUMBER 3
3937#define HCLGE_FUNC_NUMBER_PER_DESC 6
3938 int i, j;
3939
3940 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3941 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3942 if (desc[i].data[j])
3943 return false;
3944
3945 return true;
3946}
3947
d44f9b63 3948static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3949 const u8 *addr)
3950{
3951 const unsigned char *mac_addr = addr;
3952 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3953 (mac_addr[0]) | (mac_addr[1] << 8);
3954 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3955
3956 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3957 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3958}
3959
1db9b1bf
YL		 3960static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3961 const u8 *addr)
46a3df9f
S		 3962{
3963 u16 high_val = addr[1] | (addr[0] << 8);
3964 struct hclge_dev *hdev = vport->back;
3965 u32 rsh = 4 - hdev->mta_mac_sel_type;
3966 u16 ret_val = (high_val >> rsh) & 0xfff;
3967
3968 return ret_val;
3969}
3970
3971static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3972 enum hclge_mta_dmac_sel_type mta_mac_sel,
3973 bool enable)
3974{
d44f9b63 3975 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3976 struct hclge_desc desc;
3977 int ret;
3978
d44f9b63 3979 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3980 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3981
e22b531b
HT		 3982 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3983 enable);
3984 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3985 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
46a3df9f
S		 3986
3987 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3988 if (ret)
46a3df9f
S		 3989 dev_err(&hdev->pdev->dev,
3990 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3991 ret);
46a3df9f 3992
e125295a 3993 return ret;
46a3df9f
S		 3994}
3995
3996int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3997 u8 func_id,
3998 bool enable)
3999{
d44f9b63 4000 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 4001 struct hclge_desc desc;
4002 int ret;
4003
d44f9b63 4004 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 4005 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
4006
e22b531b
HT		 4007 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
4008 enable);
46a3df9f
S		 4009 req->function_id = func_id;
4010
4011 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 4012 if (ret)
46a3df9f
S		 4013 dev_err(&hdev->pdev->dev,
4014 "Config func_id enable failed for cmd_send, ret =%d.\n",
4015 ret);
46a3df9f 4016
e125295a 4017 return ret;
46a3df9f
S		 4018}
4019
4020static int hclge_set_mta_table_item(struct hclge_vport *vport,
4021 u16 idx,
4022 bool enable)
4023{
4024 struct hclge_dev *hdev = vport->back;
d44f9b63 4025 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 4026 struct hclge_desc desc;
a90bb9a5 4027 u16 item_idx = 0;
46a3df9f
S		 4028 int ret;
4029
d44f9b63 4030 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f 4031 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
e22b531b 4032 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
46a3df9f 4033
e22b531b
HT		 4034 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
4035 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 4036 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 4037
4038 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4039 if (ret) {
4040 dev_err(&hdev->pdev->dev,
4041 "Config mta table item failed for cmd_send, ret =%d.\n",
4042 ret);
4043 return ret;
4044 }
4045
a832d8b5
XW		 4046 if (enable)
4047 set_bit(idx, vport->mta_shadow);
4048 else
4049 clear_bit(idx, vport->mta_shadow);
4050
46a3df9f
S		 4051 return 0;
4052}
4053
a832d8b5
XW		 4054static int hclge_update_mta_status(struct hnae3_handle *handle)
4055{
4056 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
4057 struct hclge_vport *vport = hclge_get_vport(handle);
4058 struct net_device *netdev = handle->kinfo.netdev;
4059 struct netdev_hw_addr *ha;
4060 u16 tbl_idx;
4061
4062 memset(mta_status, 0, sizeof(mta_status));
4063
4064 /* update mta_status from mc addr list */
4065 netdev_for_each_mc_addr(ha, netdev) {
4066 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
4067 set_bit(tbl_idx, mta_status);
4068 }
4069
4070 return hclge_update_mta_status_common(vport, mta_status,
4071 0, HCLGE_MTA_TBL_SIZE, true);
4072}
4073
4074int hclge_update_mta_status_common(struct hclge_vport *vport,
4075 unsigned long *status,
4076 u16 idx,
4077 u16 count,
4078 bool update_filter)
4079{
4080 struct hclge_dev *hdev = vport->back;
4081 u16 update_max = idx + count;
4082 u16 check_max;
4083 int ret = 0;
4084 bool used;
4085 u16 i;
4086
4087 /* setup mta check range */
4088 if (update_filter) {
4089 i = 0;
4090 check_max = HCLGE_MTA_TBL_SIZE;
4091 } else {
4092 i = idx;
4093 check_max = update_max;
4094 }
4095
4096 used = false;
4097 /* check and update all mta item */
4098 for (; i < check_max; i++) {
4099 /* ignore unused item */
4100 if (!test_bit(i, vport->mta_shadow))
4101 continue;
4102
4103 /* if i in update range then update it */
4104 if (i >= idx && i < update_max)
4105 if (!test_bit(i - idx, status))
4106 hclge_set_mta_table_item(vport, i, false);
4107
4108 if (!used && test_bit(i, vport->mta_shadow))
4109 used = true;
4110 }
4111
4112 /* no longer use mta, disable it */
4113 if (vport->accept_mta_mc && update_filter && !used) {
4114 ret = hclge_cfg_func_mta_filter(hdev,
4115 vport->vport_id,
4116 false);
4117 if (ret)
4118 dev_err(&hdev->pdev->dev,
4119 "disable func mta filter fail ret=%d\n",
4120 ret);
4121 else
4122 vport->accept_mta_mc = false;
4123 }
4124
4125 return ret;
4126}
4127
46a3df9f 4128static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4129 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 4130{
4131 struct hclge_dev *hdev = vport->back;
4132 struct hclge_desc desc;
4133 u8 resp_code;
a90bb9a5 4134 u16 retval;
46a3df9f
S		 4135 int ret;
4136
4137 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4138
d44f9b63 4139 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4140
4141 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4142 if (ret) {
4143 dev_err(&hdev->pdev->dev,
4144 "del mac addr failed for cmd_send, ret =%d.\n",
4145 ret);
4146 return ret;
4147 }
a90bb9a5
YL		 4148 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4149 retval = le16_to_cpu(desc.retval);
46a3df9f 4150
a90bb9a5 4151 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4152 HCLGE_MAC_VLAN_REMOVE);
4153}
4154
4155static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4156 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4157 struct hclge_desc *desc,
4158 bool is_mc)
4159{
4160 struct hclge_dev *hdev = vport->back;
4161 u8 resp_code;
a90bb9a5 4162 u16 retval;
46a3df9f
S		 4163 int ret;
4164
4165 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4166 if (is_mc) {
4167 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4168 memcpy(desc[0].data,
4169 req,
d44f9b63 4170 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4171 hclge_cmd_setup_basic_desc(&desc[1],
4172 HCLGE_OPC_MAC_VLAN_ADD,
4173 true);
4174 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4175 hclge_cmd_setup_basic_desc(&desc[2],
4176 HCLGE_OPC_MAC_VLAN_ADD,
4177 true);
4178 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4179 } else {
4180 memcpy(desc[0].data,
4181 req,
d44f9b63 4182 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4183 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4184 }
4185 if (ret) {
4186 dev_err(&hdev->pdev->dev,
4187 "lookup mac addr failed for cmd_send, ret =%d.\n",
4188 ret);
4189 return ret;
4190 }
a90bb9a5
YL		 4191 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4192 retval = le16_to_cpu(desc[0].retval);
46a3df9f 4193
a90bb9a5 4194 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4195 HCLGE_MAC_VLAN_LKUP);
4196}
4197
4198static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4199 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4200 struct hclge_desc *mc_desc)
4201{
4202 struct hclge_dev *hdev = vport->back;
4203 int cfg_status;
4204 u8 resp_code;
a90bb9a5 4205 u16 retval;
46a3df9f
S		 4206 int ret;
4207
4208 if (!mc_desc) {
4209 struct hclge_desc desc;
4210
4211 hclge_cmd_setup_basic_desc(&desc,
4212 HCLGE_OPC_MAC_VLAN_ADD,
4213 false);
d44f9b63
YL		 4214 memcpy(desc.data, req,
4215 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4216 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 4217 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4218 retval = le16_to_cpu(desc.retval);
4219
4220 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4221 resp_code,
4222 HCLGE_MAC_VLAN_ADD);
4223 } else {
c3b6f755 4224 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 4225 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4226 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 4227 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4228 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 4229 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4230 memcpy(mc_desc[0].data, req,
d44f9b63 4231 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4232 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 4233 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4234 retval = le16_to_cpu(mc_desc[0].retval);
4235
4236 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4237 resp_code,
4238 HCLGE_MAC_VLAN_ADD);
4239 }
4240
4241 if (ret) {
4242 dev_err(&hdev->pdev->dev,
4243 "add mac addr failed for cmd_send, ret =%d.\n",
4244 ret);
4245 return ret;
4246 }
4247
4248 return cfg_status;
4249}
4250
4251static int hclge_add_uc_addr(struct hnae3_handle *handle,
4252 const unsigned char *addr)
4253{
4254 struct hclge_vport *vport = hclge_get_vport(handle);
4255
4256 return hclge_add_uc_addr_common(vport, addr);
4257}
4258
4259int hclge_add_uc_addr_common(struct hclge_vport *vport,
4260 const unsigned char *addr)
4261{
4262 struct hclge_dev *hdev = vport->back;
d44f9b63 4263 struct hclge_mac_vlan_tbl_entry_cmd req;
bf88f41f 4264 struct hclge_desc desc;
a90bb9a5 4265 u16 egress_port = 0;
04f0c72a 4266 int ret;
46a3df9f
S		 4267
4268 /* mac addr check */
4269 if (is_zero_ether_addr(addr) ||
4270 is_broadcast_ether_addr(addr) ||
4271 is_multicast_ether_addr(addr)) {
4272 dev_err(&hdev->pdev->dev,
4273 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4274 addr,
4275 is_zero_ether_addr(addr),
4276 is_broadcast_ether_addr(addr),
4277 is_multicast_ether_addr(addr));
4278 return -EINVAL;
4279 }
4280
4281 memset(&req, 0, sizeof(req));
e22b531b 4282 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 4283
e22b531b
HT		 4284 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4285 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 4286
4287 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4288
4289 hclge_prepare_mac_addr(&req, addr);
4290
bf88f41f
JS		 4291 /* Lookup the mac address in the mac_vlan table, and add
4292 * it if the entry is inexistent. Repeated unicast entry
4293 * is not allowed in the mac vlan table.
4294 */
4295 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4296 if (ret == -ENOENT)
4297 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4298
4299 /* check if we just hit the duplicate */
4300 if (!ret)
4301 ret = -EINVAL;
4302
4303 dev_err(&hdev->pdev->dev,
4304 "PF failed to add unicast entry(%pM) in the MAC table\n",
4305 addr);
46a3df9f 4306
04f0c72a 4307 return ret;
46a3df9f
S		 4308}
4309
4310static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4311 const unsigned char *addr)
4312{
4313 struct hclge_vport *vport = hclge_get_vport(handle);
4314
4315 return hclge_rm_uc_addr_common(vport, addr);
4316}
4317
4318int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4319 const unsigned char *addr)
4320{
4321 struct hclge_dev *hdev = vport->back;
d44f9b63 4322 struct hclge_mac_vlan_tbl_entry_cmd req;
04f0c72a 4323 int ret;
46a3df9f
S		 4324
4325 /* mac addr check */
4326 if (is_zero_ether_addr(addr) ||
4327 is_broadcast_ether_addr(addr) ||
4328 is_multicast_ether_addr(addr)) {
4329 dev_dbg(&hdev->pdev->dev,
4330 "Remove mac err! invalid mac:%pM.\n",
4331 addr);
4332 return -EINVAL;
4333 }
4334
4335 memset(&req, 0, sizeof(req));
e22b531b
HT		 4336 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4337 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 4338 hclge_prepare_mac_addr(&req, addr);
04f0c72a 4339 ret = hclge_remove_mac_vlan_tbl(vport, &req);
46a3df9f 4340
04f0c72a 4341 return ret;
46a3df9f
S		 4342}
4343
4344static int hclge_add_mc_addr(struct hnae3_handle *handle,
4345 const unsigned char *addr)
4346{
4347 struct hclge_vport *vport = hclge_get_vport(handle);
4348
de4116e0 4349 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 4350}
4351
4352int hclge_add_mc_addr_common(struct hclge_vport *vport,
4353 const unsigned char *addr)
4354{
4355 struct hclge_dev *hdev = vport->back;
d44f9b63 4356 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4357 struct hclge_desc desc[3];
4358 u16 tbl_idx;
4359 int status;
4360
4361 /* mac addr check */
4362 if (!is_multicast_ether_addr(addr)) {
4363 dev_err(&hdev->pdev->dev,
4364 "Add mc mac err! invalid mac:%pM.\n",
4365 addr);
4366 return -EINVAL;
4367 }
4368 memset(&req, 0, sizeof(req));
e22b531b
HT		 4369 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4370 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4371 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4372 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f
S		 4373 hclge_prepare_mac_addr(&req, addr);
4374 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4375 if (!status) {
4376 /* This mac addr exist, update VFID for it */
4377 hclge_update_desc_vfid(desc, vport->vport_id, false);
4378 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4379 } else {
4380 /* This mac addr do not exist, add new entry for it */
4381 memset(desc[0].data, 0, sizeof(desc[0].data));
4382 memset(desc[1].data, 0, sizeof(desc[0].data));
4383 memset(desc[2].data, 0, sizeof(desc[0].data));
4384 hclge_update_desc_vfid(desc, vport->vport_id, false);
4385 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4386 }
4387
a832d8b5
XW		 4388 /* If mc mac vlan table is full, use MTA table */
4389 if (status == -ENOSPC) {
4390 if (!vport->accept_mta_mc) {
4391 status = hclge_cfg_func_mta_filter(hdev,
4392 vport->vport_id,
4393 true);
4394 if (status) {
4395 dev_err(&hdev->pdev->dev,
4396 "set mta filter mode fail ret=%d\n",
4397 status);
4398 return status;
4399 }
4400 vport->accept_mta_mc = true;
4401 }
4402
4403 /* Set MTA table for this MAC address */
4404 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4405 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4406 }
46a3df9f
S		 4407
4408 return status;
4409}
4410
4411static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4412 const unsigned char *addr)
4413{
4414 struct hclge_vport *vport = hclge_get_vport(handle);
4415
4416 return hclge_rm_mc_addr_common(vport, addr);
4417}
4418
4419int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4420 const unsigned char *addr)
4421{
4422 struct hclge_dev *hdev = vport->back;
d44f9b63 4423 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4424 enum hclge_cmd_status status;
4425 struct hclge_desc desc[3];
46a3df9f
S		 4426
4427 /* mac addr check */
4428 if (!is_multicast_ether_addr(addr)) {
4429 dev_dbg(&hdev->pdev->dev,
4430 "Remove mc mac err! invalid mac:%pM.\n",
4431 addr);
4432 return -EINVAL;
4433 }
4434
4435 memset(&req, 0, sizeof(req));
e22b531b
HT		 4436 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4437 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4438 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4439 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f
S		 4440 hclge_prepare_mac_addr(&req, addr);
4441 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4442 if (!status) {
4443 /* This mac addr exist, remove this handle's VFID for it */
4444 hclge_update_desc_vfid(desc, vport->vport_id, true);
4445
4446 if (hclge_is_all_function_id_zero(desc))
4447 /* All the vfid is zero, so need to delete this entry */
4448 status = hclge_remove_mac_vlan_tbl(vport, &req);
4449 else
4450 /* Not all the vfid is zero, update the vfid */
4451 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4452
4453 } else {
a832d8b5
XW		 4454 /* Maybe this mac address is in mta table, but it cannot be
4455 * deleted here because an entry of mta represents an address
4456 * range rather than a specific address. the delete action to
4457 * all entries will take effect in update_mta_status called by
4458 * hns3_nic_set_rx_mode.
4459 */
4460 status = 0;
46a3df9f
S		 4461 }
4462
46a3df9f
S		 4463 return status;
4464}
4465
635bfb58
FL		 4466static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4467 u16 cmdq_resp, u8 resp_code)
4468{
4469#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4470#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4471#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4472#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4473
4474 int return_status;
4475
4476 if (cmdq_resp) {
4477 dev_err(&hdev->pdev->dev,
4478 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4479 cmdq_resp);
4480 return -EIO;
4481 }
4482
4483 switch (resp_code) {
4484 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4485 case HCLGE_ETHERTYPE_ALREADY_ADD:
4486 return_status = 0;
4487 break;
4488 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4489 dev_err(&hdev->pdev->dev,
4490 "add mac ethertype failed for manager table overflow.\n");
4491 return_status = -EIO;
4492 break;
4493 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4494 dev_err(&hdev->pdev->dev,
4495 "add mac ethertype failed for key conflict.\n");
4496 return_status = -EIO;
4497 break;
4498 default:
4499 dev_err(&hdev->pdev->dev,
4500 "add mac ethertype failed for undefined, code=%d.\n",
4501 resp_code);
4502 return_status = -EIO;
4503 }
4504
4505 return return_status;
4506}
4507
4508static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4509 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4510{
4511 struct hclge_desc desc;
4512 u8 resp_code;
4513 u16 retval;
4514 int ret;
4515
4516 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4517 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4518
4519 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4520 if (ret) {
4521 dev_err(&hdev->pdev->dev,
4522 "add mac ethertype failed for cmd_send, ret =%d.\n",
4523 ret);
4524 return ret;
4525 }
4526
4527 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4528 retval = le16_to_cpu(desc.retval);
4529
4530 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4531}
4532
4533static int init_mgr_tbl(struct hclge_dev *hdev)
4534{
4535 int ret;
4536 int i;
4537
4538 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4539 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4540 if (ret) {
4541 dev_err(&hdev->pdev->dev,
4542 "add mac ethertype failed, ret =%d.\n",
4543 ret);
4544 return ret;
4545 }
4546 }
4547
4548 return 0;
4549}
4550
46a3df9f
S		 4551static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4552{
4553 struct hclge_vport *vport = hclge_get_vport(handle);
4554 struct hclge_dev *hdev = vport->back;
4555
4556 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4557}
4558
3cbf5e2d
FL		 4559static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4560 bool is_first)
46a3df9f
S		 4561{
4562 const unsigned char *new_addr = (const unsigned char *)p;
4563 struct hclge_vport *vport = hclge_get_vport(handle);
4564 struct hclge_dev *hdev = vport->back;
20a5c4c0 4565 int ret;
46a3df9f
S		 4566
4567 /* mac addr check */
4568 if (is_zero_ether_addr(new_addr) ||
4569 is_broadcast_ether_addr(new_addr) ||
4570 is_multicast_ether_addr(new_addr)) {
4571 dev_err(&hdev->pdev->dev,
4572 "Change uc mac err! invalid mac:%p.\n",
4573 new_addr);
4574 return -EINVAL;
4575 }
4576
3cbf5e2d 4577 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 4578 dev_warn(&hdev->pdev->dev,
3cbf5e2d 4579 "remove old uc mac address fail.\n");
46a3df9f 4580
20a5c4c0
FL		 4581 ret = hclge_add_uc_addr(handle, new_addr);
4582 if (ret) {
4583 dev_err(&hdev->pdev->dev,
4584 "add uc mac address fail, ret =%d.\n",
4585 ret);
4586
3cbf5e2d
FL		 4587 if (!is_first &&
4588 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 4589 dev_err(&hdev->pdev->dev,
3cbf5e2d 4590 "restore uc mac address fail.\n");
20a5c4c0
FL		 4591
4592 return -EIO;
46a3df9f
S		 4593 }
4594
532fdd5e 4595 ret = hclge_pause_addr_cfg(hdev, new_addr);
20a5c4c0
FL		 4596 if (ret) {
4597 dev_err(&hdev->pdev->dev,
4598 "configure mac pause address fail, ret =%d.\n",
4599 ret);
4600 return -EIO;
4601 }
4602
4603 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4604
4605 return 0;
46a3df9f
S		 4606}
4607
4608static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4609 bool filter_en)
4610{
d44f9b63 4611 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4612 struct hclge_desc desc;
4613 int ret;
4614
4615 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4616
d44f9b63 4617 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4618 req->vlan_type = vlan_type;
4619 req->vlan_fe = filter_en;
4620
4621 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 4622 if (ret)
46a3df9f
S		 4623 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4624 ret);
46a3df9f 4625
e125295a 4626 return ret;
46a3df9f
S		 4627}
4628
d818396d
JS		 4629#define HCLGE_FILTER_TYPE_VF 0
4630#define HCLGE_FILTER_TYPE_PORT 1
4631
4632static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4633{
4634 struct hclge_vport *vport = hclge_get_vport(handle);
4635 struct hclge_dev *hdev = vport->back;
4636
4637 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4638}
4639
4e66632d
YL		 4640static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4641 bool is_kill, u16 vlan, u8 qos,
4642 __be16 proto)
46a3df9f
S		 4643{
4644#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4645 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4646 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4647 struct hclge_desc desc[2];
4648 u8 vf_byte_val;
4649 u8 vf_byte_off;
4650 int ret;
4651
4652 hclge_cmd_setup_basic_desc(&desc[0],
4653 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4654 hclge_cmd_setup_basic_desc(&desc[1],
4655 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4656
4657 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4658
4659 vf_byte_off = vfid / 8;
4660 vf_byte_val = 1 << (vfid % 8);
4661
d44f9b63
YL		 4662 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4663 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4664
a90bb9a5 4665 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4666 req0->vlan_cfg = is_kill;
4667
4668 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4669 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4670 else
4671 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4672
4673 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4674 if (ret) {
4675 dev_err(&hdev->pdev->dev,
4676 "Send vf vlan command fail, ret =%d.\n",
4677 ret);
4678 return ret;
4679 }
4680
4681 if (!is_kill) {
715d610d 4682#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 4683 if (!req0->resp_code || req0->resp_code == 1)
4684 return 0;
4685
715d610d
YL		 4686 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4687 dev_warn(&hdev->pdev->dev,
4688 "vf vlan table is full, vf vlan filter is disabled\n");
4689 return 0;
4690 }
4691
46a3df9f
S		 4692 dev_err(&hdev->pdev->dev,
4693 "Add vf vlan filter fail, ret =%d.\n",
4694 req0->resp_code);
4695 } else {
4696 if (!req0->resp_code)
4697 return 0;
4698
4699 dev_err(&hdev->pdev->dev,
4700 "Kill vf vlan filter fail, ret =%d.\n",
4701 req0->resp_code);
4702 }
4703
4704 return -EIO;
4705}
4706
4e66632d
YL		 4707static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4708 u16 vlan_id, bool is_kill)
46a3df9f 4709{
d44f9b63 4710 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4711 struct hclge_desc desc;
4712 u8 vlan_offset_byte_val;
4713 u8 vlan_offset_byte;
4714 u8 vlan_offset_160;
4715 int ret;
4716
4717 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4718
4719 vlan_offset_160 = vlan_id / 160;
4720 vlan_offset_byte = (vlan_id % 160) / 8;
4721 vlan_offset_byte_val = 1 << (vlan_id % 8);
4722
d44f9b63 4723 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4724 req->vlan_offset = vlan_offset_160;
4725 req->vlan_cfg = is_kill;
4726 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4727
4728 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4e66632d
YL		 4729 if (ret)
4730 dev_err(&hdev->pdev->dev,
4731 "port vlan command, send fail, ret =%d.\n", ret);
4732 return ret;
4733}
4734
4735static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4736 u16 vport_id, u16 vlan_id, u8 qos,
4737 bool is_kill)
4738{
4739 u16 vport_idx, vport_num = 0;
4740 int ret;
4741
4742 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4743 0, proto);
46a3df9f
S		 4744 if (ret) {
4745 dev_err(&hdev->pdev->dev,
4e66632d
YL		 4746 "Set %d vport vlan filter config fail, ret =%d.\n",
4747 vport_id, ret);
46a3df9f
S		 4748 return ret;
4749 }
4750
4e66632d
YL		 4751 /* vlan 0 may be added twice when 8021q module is enabled */
4752 if (!is_kill && !vlan_id &&
4753 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4754 return 0;
4755
4756 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 4757 dev_err(&hdev->pdev->dev,
4e66632d
YL		 4758 "Add port vlan failed, vport %d is already in vlan %d\n",
4759 vport_id, vlan_id);
4760 return -EINVAL;
46a3df9f
S		 4761 }
4762
4e66632d
YL		 4763 if (is_kill &&
4764 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4765 dev_err(&hdev->pdev->dev,
4766 "Delete port vlan failed, vport %d is not in vlan %d\n",
4767 vport_id, vlan_id);
4768 return -EINVAL;
4769 }
4770
4771 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID)
4772 vport_num++;
4773
4774 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4775 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4776 is_kill);
4777
4778 return ret;
4779}
4780
4781int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4782 u16 vlan_id, bool is_kill)
4783{
4784 struct hclge_vport *vport = hclge_get_vport(handle);
4785 struct hclge_dev *hdev = vport->back;
4786
4787 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4788 0, is_kill);
46a3df9f
S		 4789}
4790
4791static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4792 u16 vlan, u8 qos, __be16 proto)
4793{
4794 struct hclge_vport *vport = hclge_get_vport(handle);
4795 struct hclge_dev *hdev = vport->back;
4796
4797 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4798 return -EINVAL;
4799 if (proto != htons(ETH_P_8021Q))
4800 return -EPROTONOSUPPORT;
4801
4e66632d 4802 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 4803}
4804
e62f2a6b
PL		 4805static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4806{
4807 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4808 struct hclge_vport_vtag_tx_cfg_cmd *req;
4809 struct hclge_dev *hdev = vport->back;
4810 struct hclge_desc desc;
4811 int status;
4812
4813 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4814
4815 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4816 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4817 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
e22b531b 4818 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
b75b1a56 4819 vcfg->accept_tag1 ? 1 : 0);
e22b531b 4820 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
b75b1a56 4821 vcfg->accept_untag1 ? 1 : 0);
e22b531b 4822 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
b75b1a56 4823 vcfg->accept_tag2 ? 1 : 0);
e22b531b 4824 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
b75b1a56 4825 vcfg->accept_untag2 ? 1 : 0);
e22b531b 4826 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
e62f2a6b 4827 vcfg->insert_tag1_en ? 1 : 0);
e22b531b 4828 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
e62f2a6b 4829 vcfg->insert_tag2_en ? 1 : 0);
e22b531b 4830 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
e62f2a6b
PL		 4831
4832 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4833 req->vf_bitmap[req->vf_offset] =
4834 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4835
4836 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4837 if (status)
4838 dev_err(&hdev->pdev->dev,
4839 "Send port txvlan cfg command fail, ret =%d\n",
4840 status);
4841
4842 return status;
4843}
4844
4845static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4846{
4847 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4848 struct hclge_vport_vtag_rx_cfg_cmd *req;
4849 struct hclge_dev *hdev = vport->back;
4850 struct hclge_desc desc;
4851 int status;
4852
4853 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4854
4855 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
e22b531b
HT		 4856 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4857 vcfg->strip_tag1_en ? 1 : 0);
4858 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4859 vcfg->strip_tag2_en ? 1 : 0);
4860 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4861 vcfg->vlan1_vlan_prionly ? 1 : 0);
4862 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4863 vcfg->vlan2_vlan_prionly ? 1 : 0);
e62f2a6b
PL		 4864
4865 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4866 req->vf_bitmap[req->vf_offset] =
4867 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4868
4869 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4870 if (status)
4871 dev_err(&hdev->pdev->dev,
4872 "Send port rxvlan cfg command fail, ret =%d\n",
4873 status);
4874
4875 return status;
4876}
4877
4878static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4879{
4880 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4881 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4882 struct hclge_desc desc;
4883 int status;
4884
4885 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4886 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4887 rx_req->ot_fst_vlan_type =
4888 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4889 rx_req->ot_sec_vlan_type =
4890 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4891 rx_req->in_fst_vlan_type =
4892 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4893 rx_req->in_sec_vlan_type =
4894 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4895
4896 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4897 if (status) {
4898 dev_err(&hdev->pdev->dev,
4899 "Send rxvlan protocol type command fail, ret =%d\n",
4900 status);
4901 return status;
4902 }
4903
4904 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4905
4906 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4907 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4908 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4909
4910 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4911 if (status)
4912 dev_err(&hdev->pdev->dev,
4913 "Send txvlan protocol type command fail, ret =%d\n",
4914 status);
4915
4916 return status;
4917}
4918
46a3df9f
S		 4919static int hclge_init_vlan_config(struct hclge_dev *hdev)
4920{
e62f2a6b
PL		 4921#define HCLGE_DEF_VLAN_TYPE 0x8100
4922
5e43aef8 4923 struct hnae3_handle *handle;
e62f2a6b 4924 struct hclge_vport *vport;
46a3df9f 4925 int ret;
e62f2a6b
PL		 4926 int i;
4927
4928 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4929 if (ret)
4930 return ret;
46a3df9f 4931
e62f2a6b 4932 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4933 if (ret)
4934 return ret;
4935
e62f2a6b
PL		 4936 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4937 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4938 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4939 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4940 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4941 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4942
4943 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4944 if (ret)
4945 return ret;
46a3df9f 4946
e62f2a6b
PL		 4947 for (i = 0; i < hdev->num_alloc_vport; i++) {
4948 vport = &hdev->vport[i];
b75b1a56
PL		 4949 vport->txvlan_cfg.accept_tag1 = true;
4950 vport->txvlan_cfg.accept_untag1 = true;
4951
4952 /* accept_tag2 and accept_untag2 are not supported on
4953 * pdev revision(0x20), new revision support them. The
4954 * value of this two fields will not return error when driver
4955 * send command to fireware in revision(0x20).
4956 * This two fields can not configured by user.
4957 */
4958 vport->txvlan_cfg.accept_tag2 = true;
4959 vport->txvlan_cfg.accept_untag2 = true;
4960
e62f2a6b
PL		 4961 vport->txvlan_cfg.insert_tag1_en = false;
4962 vport->txvlan_cfg.insert_tag2_en = false;
4963 vport->txvlan_cfg.default_tag1 = 0;
4964 vport->txvlan_cfg.default_tag2 = 0;
4965
4966 ret = hclge_set_vlan_tx_offload_cfg(vport);
4967 if (ret)
4968 return ret;
4969
4970 vport->rxvlan_cfg.strip_tag1_en = false;
4971 vport->rxvlan_cfg.strip_tag2_en = true;
4972 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4973 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4974
4975 ret = hclge_set_vlan_rx_offload_cfg(vport);
4976 if (ret)
4977 return ret;
4978 }
4979
5e43aef8 4980 handle = &hdev->vport[0].nic;
4e66632d 4981 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4982}
4983
3849d494 4984int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
5f9a7732
PL		 4985{
4986 struct hclge_vport *vport = hclge_get_vport(handle);
4987
4988 vport->rxvlan_cfg.strip_tag1_en = false;
4989 vport->rxvlan_cfg.strip_tag2_en = enable;
4990 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4991 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4992
4993 return hclge_set_vlan_rx_offload_cfg(vport);
4994}
4995
12341881 4996static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 4997{
d44f9b63 4998 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 4999 struct hclge_desc desc;
7393ed39 5000 int max_frm_size;
46a3df9f
S		 5001 int ret;
5002
7393ed39
FL		 5003 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5004
5005 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
5006 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 5007 return -EINVAL;
5008
7393ed39
FL		 5009 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
5010
46a3df9f
S		 5011 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
5012
d44f9b63 5013 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
7393ed39 5014 req->max_frm_size = cpu_to_le16(max_frm_size);
51d43446 5015 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
46a3df9f
S		 5016
5017 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 5018 if (ret)
46a3df9f 5019 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
e125295a
JS		 5020 else
5021 hdev->mps = max_frm_size;
7393ed39 5022
e125295a 5023 return ret;
46a3df9f
S		 5024}
5025
12341881
FL		 5026static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
5027{
5028 struct hclge_vport *vport = hclge_get_vport(handle);
5029 struct hclge_dev *hdev = vport->back;
5030 int ret;
5031
5032 ret = hclge_set_mac_mtu(hdev, new_mtu);
5033 if (ret) {
5034 dev_err(&hdev->pdev->dev,
5035 "Change mtu fail, ret =%d\n", ret);
5036 return ret;
5037 }
5038
5039 ret = hclge_buffer_alloc(hdev);
5040 if (ret)
5041 dev_err(&hdev->pdev->dev,
5042 "Allocate buffer fail, ret =%d\n", ret);
5043
5044 return ret;
5045}
5046
46a3df9f
S		 5047static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
5048 bool enable)
5049{
d44f9b63 5050 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5051 struct hclge_desc desc;
5052 int ret;
5053
5054 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
5055
d44f9b63 5056 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 5057 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
e22b531b 5058 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 5059
5060 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5061 if (ret) {
5062 dev_err(&hdev->pdev->dev,
5063 "Send tqp reset cmd error, status =%d\n", ret);
5064 return ret;
5065 }
5066
5067 return 0;
5068}
5069
5070static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
5071{
d44f9b63 5072 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5073 struct hclge_desc desc;
5074 int ret;
5075
5076 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
5077
d44f9b63 5078 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 5079 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5080
5081 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5082 if (ret) {
5083 dev_err(&hdev->pdev->dev,
5084 "Get reset status error, status =%d\n", ret);
5085 return ret;
5086 }
5087
e22b531b 5088 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 5089}
5090
e5e89cda
PL		 5091static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
5092 u16 queue_id)
5093{
5094 struct hnae3_queue *queue;
5095 struct hclge_tqp *tqp;
5096
5097 queue = handle->kinfo.tqp[queue_id];
5098 tqp = container_of(queue, struct hclge_tqp, q);
5099
5100 return tqp->index;
5101}
5102
63d7e66f 5103void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 5104{
5105 struct hclge_vport *vport = hclge_get_vport(handle);
5106 struct hclge_dev *hdev = vport->back;
5107 int reset_try_times = 0;
5108 int reset_status;
e5e89cda 5109 u16 queue_gid;
46a3df9f
S		 5110 int ret;
5111
f9637cc2
PL		 5112 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5113 return;
5114
e5e89cda
PL		 5115 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
5116
46a3df9f
S		 5117 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
5118 if (ret) {
5119 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
5120 return;
5121 }
5122
e5e89cda 5123 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 5124 if (ret) {
5125 dev_warn(&hdev->pdev->dev,
5126 "Send reset tqp cmd fail, ret = %d\n", ret);
5127 return;
5128 }
5129
5130 reset_try_times = 0;
5131 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5132 /* Wait for tqp hw reset */
5133 msleep(20);
e5e89cda 5134 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 5135 if (reset_status)
5136 break;
5137 }
5138
5139 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5140 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5141 return;
5142 }
5143
e5e89cda 5144 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 5145 if (ret) {
5146 dev_warn(&hdev->pdev->dev,
5147 "Deassert the soft reset fail, ret = %d\n", ret);
5148 return;
5149 }
5150}
5151
d3ea7fc4
PL		 5152void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
5153{
5154 struct hclge_dev *hdev = vport->back;
5155 int reset_try_times = 0;
5156 int reset_status;
5157 u16 queue_gid;
5158 int ret;
5159
5160 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
5161
5162 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5163 if (ret) {
5164 dev_warn(&hdev->pdev->dev,
5165 "Send reset tqp cmd fail, ret = %d\n", ret);
5166 return;
5167 }
5168
5169 reset_try_times = 0;
5170 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5171 /* Wait for tqp hw reset */
5172 msleep(20);
5173 reset_status = hclge_get_reset_status(hdev, queue_gid);
5174 if (reset_status)
5175 break;
5176 }
5177
5178 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5179 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5180 return;
5181 }
5182
5183 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5184 if (ret)
5185 dev_warn(&hdev->pdev->dev,
5186 "Deassert the soft reset fail, ret = %d\n", ret);
5187}
5188
46a3df9f
S		 5189static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5190{
5191 struct hclge_vport *vport = hclge_get_vport(handle);
5192 struct hclge_dev *hdev = vport->back;
5193
5194 return hdev->fw_version;
5195}
5196
a2cfbadb
PL		 5197static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5198 u32 *flowctrl_adv)
5199{
5200 struct hclge_vport *vport = hclge_get_vport(handle);
5201 struct hclge_dev *hdev = vport->back;
5202 struct phy_device *phydev = hdev->hw.mac.phydev;
5203
5204 if (!phydev)
5205 return;
5206
5207 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5208 (phydev->advertising & ADVERTISED_Asym_Pause);
5209}
5210
09ea401e
PL		 5211static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5212{
5213 struct phy_device *phydev = hdev->hw.mac.phydev;
5214
5215 if (!phydev)
5216 return;
5217
5218 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
5219
5220 if (rx_en)
5221 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5222
5223 if (tx_en)
5224 phydev->advertising ^= ADVERTISED_Asym_Pause;
5225}
5226
5227static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5228{
09ea401e
PL		 5229 int ret;
5230
5231 if (rx_en && tx_en)
7a28a82a 5232 hdev->fc_mode_last_time = HCLGE_FC_FULL;
09ea401e 5233 else if (rx_en && !tx_en)
7a28a82a 5234 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
09ea401e 5235 else if (!rx_en && tx_en)
7a28a82a 5236 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
09ea401e 5237 else
7a28a82a 5238 hdev->fc_mode_last_time = HCLGE_FC_NONE;
09ea401e 5239
7a28a82a 5240 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
09ea401e 5241 return 0;
09ea401e
PL		 5242
5243 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
5244 if (ret) {
5245 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
5246 ret);
5247 return ret;
5248 }
5249
7a28a82a 5250 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
09ea401e
PL		 5251
5252 return 0;
5253}
5254
6282f2ea
PL		 5255int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5256{
5257 struct phy_device *phydev = hdev->hw.mac.phydev;
5258 u16 remote_advertising = 0;
5259 u16 local_advertising = 0;
5260 u32 rx_pause, tx_pause;
5261 u8 flowctl;
5262
5263 if (!phydev->link || !phydev->autoneg)
5264 return 0;
5265
5266 if (phydev->advertising & ADVERTISED_Pause)
5267 local_advertising = ADVERTISE_PAUSE_CAP;
5268
5269 if (phydev->advertising & ADVERTISED_Asym_Pause)
5270 local_advertising |= ADVERTISE_PAUSE_ASYM;
5271
5272 if (phydev->pause)
5273 remote_advertising = LPA_PAUSE_CAP;
5274
5275 if (phydev->asym_pause)
5276 remote_advertising |= LPA_PAUSE_ASYM;
5277
5278 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5279 remote_advertising);
5280 tx_pause = flowctl & FLOW_CTRL_TX;
5281 rx_pause = flowctl & FLOW_CTRL_RX;
5282
5283 if (phydev->duplex == HCLGE_MAC_HALF) {
5284 tx_pause = 0;
5285 rx_pause = 0;
5286 }
5287
5288 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5289}
5290
46a3df9f
S		 5291static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5292 u32 *rx_en, u32 *tx_en)
5293{
5294 struct hclge_vport *vport = hclge_get_vport(handle);
5295 struct hclge_dev *hdev = vport->back;
5296
5297 *auto_neg = hclge_get_autoneg(handle);
5298
5299 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5300 *rx_en = 0;
5301 *tx_en = 0;
5302 return;
5303 }
5304
5305 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5306 *rx_en = 1;
5307 *tx_en = 0;
5308 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5309 *tx_en = 1;
5310 *rx_en = 0;
5311 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5312 *rx_en = 1;
5313 *tx_en = 1;
5314 } else {
5315 *rx_en = 0;
5316 *tx_en = 0;
5317 }
5318}
5319
09ea401e
PL		 5320static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5321 u32 rx_en, u32 tx_en)
5322{
5323 struct hclge_vport *vport = hclge_get_vport(handle);
5324 struct hclge_dev *hdev = vport->back;
5325 struct phy_device *phydev = hdev->hw.mac.phydev;
5326 u32 fc_autoneg;
5327
09ea401e
PL		 5328 fc_autoneg = hclge_get_autoneg(handle);
5329 if (auto_neg != fc_autoneg) {
5330 dev_info(&hdev->pdev->dev,
5331 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5332 return -EOPNOTSUPP;
5333 }
5334
5335 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5336 dev_info(&hdev->pdev->dev,
5337 "Priority flow control enabled. Cannot set link flow control.\n");
5338 return -EOPNOTSUPP;
5339 }
5340
5341 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5342
5343 if (!fc_autoneg)
5344 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5345
bef24782
FL		 5346 /* Only support flow control negotiation for netdev with
5347 * phy attached for now.
5348 */
5349 if (!phydev)
5350 return -EOPNOTSUPP;
5351
09ea401e
PL		 5352 return phy_start_aneg(phydev);
5353}
5354
46a3df9f
S		 5355static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5356 u8 *auto_neg, u32 *speed, u8 *duplex)
5357{
5358 struct hclge_vport *vport = hclge_get_vport(handle);
5359 struct hclge_dev *hdev = vport->back;
5360
5361 if (speed)
5362 *speed = hdev->hw.mac.speed;
5363 if (duplex)
5364 *duplex = hdev->hw.mac.duplex;
5365 if (auto_neg)
5366 *auto_neg = hdev->hw.mac.autoneg;
5367}
5368
5369static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5370{
5371 struct hclge_vport *vport = hclge_get_vport(handle);
5372 struct hclge_dev *hdev = vport->back;
5373
5374 if (media_type)
5375 *media_type = hdev->hw.mac.media_type;
5376}
5377
5378static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5379 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5380{
5381 struct hclge_vport *vport = hclge_get_vport(handle);
5382 struct hclge_dev *hdev = vport->back;
5383 struct phy_device *phydev = hdev->hw.mac.phydev;
5384 int mdix_ctrl, mdix, retval, is_resolved;
5385
5386 if (!phydev) {
5387 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5388 *tp_mdix = ETH_TP_MDI_INVALID;
5389 return;
5390 }
5391
5392 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5393
5394 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
e22b531b
HT		 5395 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5396 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 5397
5398 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
e22b531b
HT		 5399 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5400 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 5401
5402 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5403
5404 switch (mdix_ctrl) {
5405 case 0x0:
5406 *tp_mdix_ctrl = ETH_TP_MDI;
5407 break;
5408 case 0x1:
5409 *tp_mdix_ctrl = ETH_TP_MDI_X;
5410 break;
5411 case 0x3:
5412 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5413 break;
5414 default:
5415 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5416 break;
5417 }
5418
5419 if (!is_resolved)
5420 *tp_mdix = ETH_TP_MDI_INVALID;
5421 else if (mdix)
5422 *tp_mdix = ETH_TP_MDI_X;
5423 else
5424 *tp_mdix = ETH_TP_MDI;
5425}
5426
5427static int hclge_init_client_instance(struct hnae3_client *client,
5428 struct hnae3_ae_dev *ae_dev)
5429{
5430 struct hclge_dev *hdev = ae_dev->priv;
5431 struct hclge_vport *vport;
5432 int i, ret;
5433
5434 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5435 vport = &hdev->vport[i];
5436
5437 switch (client->type) {
5438 case HNAE3_CLIENT_KNIC:
5439
5440 hdev->nic_client = client;
5441 vport->nic.client = client;
5442 ret = client->ops->init_instance(&vport->nic);
5443 if (ret)
6f636872 5444 return ret;
46a3df9f
S		 5445
5446 if (hdev->roce_client &&
e92a0843 5447 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5448 struct hnae3_client *rc = hdev->roce_client;
5449
5450 ret = hclge_init_roce_base_info(vport);
5451 if (ret)
6f636872 5452 return ret;
46a3df9f
S		 5453
5454 ret = rc->ops->init_instance(&vport->roce);
5455 if (ret)
6f636872 5456 return ret;
46a3df9f
S		 5457 }
5458
5459 break;
5460 case HNAE3_CLIENT_UNIC:
5461 hdev->nic_client = client;
5462 vport->nic.client = client;
5463
5464 ret = client->ops->init_instance(&vport->nic);
5465 if (ret)
6f636872 5466 return ret;
46a3df9f
S		 5467
5468 break;
5469 case HNAE3_CLIENT_ROCE:
e92a0843 5470 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5471 hdev->roce_client = client;
5472 vport->roce.client = client;
5473 }
5474
3a46f34d 5475 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5476 ret = hclge_init_roce_base_info(vport);
5477 if (ret)
6f636872 5478 return ret;
46a3df9f
S		 5479
5480 ret = client->ops->init_instance(&vport->roce);
5481 if (ret)
6f636872 5482 return ret;
46a3df9f
S		 5483 }
5484 }
5485 }
5486
5487 return 0;
46a3df9f
S		 5488}
5489
5490static void hclge_uninit_client_instance(struct hnae3_client *client,
5491 struct hnae3_ae_dev *ae_dev)
5492{
5493 struct hclge_dev *hdev = ae_dev->priv;
5494 struct hclge_vport *vport;
5495 int i;
5496
5497 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5498 vport = &hdev->vport[i];
a17dcf3f 5499 if (hdev->roce_client) {
46a3df9f
S		 5500 hdev->roce_client->ops->uninit_instance(&vport->roce,
5501 0);
a17dcf3f
L		 5502 hdev->roce_client = NULL;
5503 vport->roce.client = NULL;
5504 }
46a3df9f
S		 5505 if (client->type == HNAE3_CLIENT_ROCE)
5506 return;
a17dcf3f 5507 if (client->ops->uninit_instance) {
46a3df9f 5508 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5509 hdev->nic_client = NULL;
5510 vport->nic.client = NULL;
5511 }
46a3df9f
S		 5512 }
5513}
5514
5515static int hclge_pci_init(struct hclge_dev *hdev)
5516{
5517 struct pci_dev *pdev = hdev->pdev;
5518 struct hclge_hw *hw;
5519 int ret;
5520
5521 ret = pci_enable_device(pdev);
5522 if (ret) {
5523 dev_err(&pdev->dev, "failed to enable PCI device\n");
6c46284e 5524 return ret;
46a3df9f
S		 5525 }
5526
5527 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5528 if (ret) {
5529 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5530 if (ret) {
5531 dev_err(&pdev->dev,
5532 "can't set consistent PCI DMA");
5533 goto err_disable_device;
5534 }
5535 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5536 }
5537
5538 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5539 if (ret) {
5540 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5541 goto err_disable_device;
5542 }
5543
5544 pci_set_master(pdev);
5545 hw = &hdev->hw;
46a3df9f
S		 5546 hw->io_base = pcim_iomap(pdev, 2, 0);
5547 if (!hw->io_base) {
5548 dev_err(&pdev->dev, "Can't map configuration register space\n");
5549 ret = -ENOMEM;
5550 goto err_clr_master;
5551 }
5552
709eb41a
L		 5553 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5554
46a3df9f
S		 5555 return 0;
5556err_clr_master:
5557 pci_clear_master(pdev);
5558 pci_release_regions(pdev);
5559err_disable_device:
5560 pci_disable_device(pdev);
46a3df9f
S		 5561
5562 return ret;
5563}
5564
5565static void hclge_pci_uninit(struct hclge_dev *hdev)
5566{
5567 struct pci_dev *pdev = hdev->pdev;
5568
7d6d639b 5569 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 5570 pci_free_irq_vectors(pdev);
46a3df9f
S		 5571 pci_clear_master(pdev);
5572 pci_release_mem_regions(pdev);
5573 pci_disable_device(pdev);
5574}
5575
71d7e8ea
PL		 5576static void hclge_state_init(struct hclge_dev *hdev)
5577{
5578 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5579 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5580 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5581 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5582 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5583 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5584}
5585
5586static void hclge_state_uninit(struct hclge_dev *hdev)
5587{
5588 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5589
5590 if (hdev->service_timer.function)
5591 del_timer_sync(&hdev->service_timer);
5592 if (hdev->service_task.func)
5593 cancel_work_sync(&hdev->service_task);
5594 if (hdev->rst_service_task.func)
5595 cancel_work_sync(&hdev->rst_service_task);
5596 if (hdev->mbx_service_task.func)
5597 cancel_work_sync(&hdev->mbx_service_task);
5598}
5599
46a3df9f
S		 5600static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5601{
5602 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5603 struct hclge_dev *hdev;
5604 int ret;
5605
5606 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5607 if (!hdev) {
5608 ret = -ENOMEM;
e0027501 5609 goto out;
46a3df9f
S		 5610 }
5611
46a3df9f
S		 5612 hdev->pdev = pdev;
5613 hdev->ae_dev = ae_dev;
4ed340ab 5614 hdev->reset_type = HNAE3_NONE_RESET;
46a3df9f
S		 5615 ae_dev->priv = hdev;
5616
46a3df9f
S		 5617 ret = hclge_pci_init(hdev);
5618 if (ret) {
5619 dev_err(&pdev->dev, "PCI init failed\n");
e0027501 5620 goto out;
46a3df9f
S		 5621 }
5622
3efb960f
L		 5623 /* Firmware command queue initialize */
5624 ret = hclge_cmd_queue_init(hdev);
5625 if (ret) {
5626 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
e0027501 5627 goto err_pci_uninit;
3efb960f
L		 5628 }
5629
5630 /* Firmware command initialize */
46a3df9f
S		 5631 ret = hclge_cmd_init(hdev);
5632 if (ret)
e0027501 5633 goto err_cmd_uninit;
46a3df9f
S		 5634
5635 ret = hclge_get_cap(hdev);
5636 if (ret) {
e00e2197
CIK		 5637 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5638 ret);
e0027501 5639 goto err_cmd_uninit;
46a3df9f
S		 5640 }
5641
5642 ret = hclge_configure(hdev);
5643 if (ret) {
5644 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
e0027501 5645 goto err_cmd_uninit;
46a3df9f
S		 5646 }
5647
887c3820 5648 ret = hclge_init_msi(hdev);
46a3df9f 5649 if (ret) {
887c3820 5650 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
e0027501 5651 goto err_cmd_uninit;
46a3df9f
S		 5652 }
5653
466b0c00
L		 5654 ret = hclge_misc_irq_init(hdev);
5655 if (ret) {
5656 dev_err(&pdev->dev,
5657 "Misc IRQ(vector0) init error, ret = %d.\n",
5658 ret);
e0027501 5659 goto err_msi_uninit;
466b0c00
L		 5660 }
5661
46a3df9f
S		 5662 ret = hclge_alloc_tqps(hdev);
5663 if (ret) {
5664 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
e0027501 5665 goto err_msi_irq_uninit;
46a3df9f
S		 5666 }
5667
5668 ret = hclge_alloc_vport(hdev);
5669 if (ret) {
5670 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
e0027501 5671 goto err_msi_irq_uninit;
46a3df9f
S		 5672 }
5673
7df7dad6
L		 5674 ret = hclge_map_tqp(hdev);
5675 if (ret) {
5676 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
bc59f827 5677 goto err_msi_irq_uninit;
7df7dad6
L		 5678 }
5679
dea9a821
HT		 5680 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5681 ret = hclge_mac_mdio_config(hdev);
5682 if (ret) {
5683 dev_err(&hdev->pdev->dev,
5684 "mdio config fail ret=%d\n", ret);
bc59f827 5685 goto err_msi_irq_uninit;
dea9a821 5686 }
cf9cca2d 5687 }
5688
46a3df9f
S		 5689 ret = hclge_mac_init(hdev);
5690 if (ret) {
5691 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
e0027501 5692 goto err_mdiobus_unreg;
46a3df9f 5693 }
46a3df9f
S		 5694
5695 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5696 if (ret) {
5697 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
e0027501 5698 goto err_mdiobus_unreg;
46a3df9f
S		 5699 }
5700
46a3df9f
S		 5701 ret = hclge_init_vlan_config(hdev);
5702 if (ret) {
5703 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
e0027501 5704 goto err_mdiobus_unreg;
46a3df9f
S		 5705 }
5706
5707 ret = hclge_tm_schd_init(hdev);
5708 if (ret) {
5709 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
e0027501 5710 goto err_mdiobus_unreg;
68ece54e
YL		 5711 }
5712
8015bb74 5713 hclge_rss_init_cfg(hdev);
68ece54e
YL		 5714 ret = hclge_rss_init_hw(hdev);
5715 if (ret) {
5716 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
e0027501 5717 goto err_mdiobus_unreg;
46a3df9f
S		 5718 }
5719
635bfb58
FL		 5720 ret = init_mgr_tbl(hdev);
5721 if (ret) {
5722 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
e0027501 5723 goto err_mdiobus_unreg;
635bfb58
FL		 5724 }
5725
cacde272
YL		 5726 hclge_dcb_ops_set(hdev);
5727
d039ef68 5728 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5729 INIT_WORK(&hdev->service_task, hclge_service_task);
ed4a1bb8 5730 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
22fd3468 5731 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5732
466b0c00
L		 5733 /* Enable MISC vector(vector0) */
5734 hclge_enable_vector(&hdev->misc_vector, true);
5735
71d7e8ea 5736 hclge_state_init(hdev);
46a3df9f
S		 5737
5738 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5739 return 0;
5740
e0027501
HT		 5741err_mdiobus_unreg:
5742 if (hdev->hw.mac.phydev)
5743 mdiobus_unregister(hdev->hw.mac.mdio_bus);
e0027501
HT		 5744err_msi_irq_uninit:
5745 hclge_misc_irq_uninit(hdev);
5746err_msi_uninit:
5747 pci_free_irq_vectors(pdev);
5748err_cmd_uninit:
5749 hclge_destroy_cmd_queue(&hdev->hw);
5750err_pci_uninit:
7d6d639b 5751 pcim_iounmap(pdev, hdev->hw.io_base);
e0027501 5752 pci_clear_master(pdev);
46a3df9f 5753 pci_release_regions(pdev);
e0027501 5754 pci_disable_device(pdev);
e0027501 5755out:
46a3df9f
S		 5756 return ret;
5757}
5758
c6dc5213 5759static void hclge_stats_clear(struct hclge_dev *hdev)
5760{
5761 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5762}
5763
4ed340ab
L		 5764static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5765{
5766 struct hclge_dev *hdev = ae_dev->priv;
5767 struct pci_dev *pdev = ae_dev->pdev;
5768 int ret;
5769
5770 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5771
c6dc5213 5772 hclge_stats_clear(hdev);
4e66632d 5773 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 5774
4ed340ab
L		 5775 ret = hclge_cmd_init(hdev);
5776 if (ret) {
5777 dev_err(&pdev->dev, "Cmd queue init failed\n");
5778 return ret;
5779 }
5780
5781 ret = hclge_get_cap(hdev);
5782 if (ret) {
5783 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5784 ret);
5785 return ret;
5786 }
5787
5788 ret = hclge_configure(hdev);
5789 if (ret) {
5790 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5791 return ret;
5792 }
5793
5794 ret = hclge_map_tqp(hdev);
5795 if (ret) {
5796 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5797 return ret;
5798 }
5799
5800 ret = hclge_mac_init(hdev);
5801 if (ret) {
5802 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5803 return ret;
5804 }
5805
4ed340ab
L		 5806 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5807 if (ret) {
5808 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5809 return ret;
5810 }
5811
5812 ret = hclge_init_vlan_config(hdev);
5813 if (ret) {
5814 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5815 return ret;
5816 }
5817
d85f1ab5 5818 ret = hclge_tm_init_hw(hdev);
4ed340ab 5819 if (ret) {
d85f1ab5 5820 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 5821 return ret;
5822 }
5823
5824 ret = hclge_rss_init_hw(hdev);
5825 if (ret) {
5826 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5827 return ret;
5828 }
5829
4ed340ab
L		 5830 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5831 HCLGE_DRIVER_NAME);
5832
5833 return 0;
5834}
5835
46a3df9f
S		 5836static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5837{
5838 struct hclge_dev *hdev = ae_dev->priv;
5839 struct hclge_mac *mac = &hdev->hw.mac;
5840
71d7e8ea 5841 hclge_state_uninit(hdev);
46a3df9f
S		 5842
5843 if (mac->phydev)
5844 mdiobus_unregister(mac->mdio_bus);
5845
466b0c00
L		 5846 /* Disable MISC vector(vector0) */
5847 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 5848 hclge_destroy_cmd_queue(&hdev->hw);
202f2014 5849 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5850 hclge_pci_uninit(hdev);
5851 ae_dev->priv = NULL;
5852}
5853
4f645a90
PL		 5854static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5855{
5856 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5857 struct hclge_vport *vport = hclge_get_vport(handle);
5858 struct hclge_dev *hdev = vport->back;
5859
5860 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5861}
5862
5863static void hclge_get_channels(struct hnae3_handle *handle,
5864 struct ethtool_channels *ch)
5865{
5866 struct hclge_vport *vport = hclge_get_vport(handle);
5867
5868 ch->max_combined = hclge_get_max_channels(handle);
5869 ch->other_count = 1;
5870 ch->max_other = 1;
5871 ch->combined_count = vport->alloc_tqps;
5872}
5873
f1f779ce
PL		 5874static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5875 u16 *free_tqps, u16 *max_rss_size)
5876{
5877 struct hclge_vport *vport = hclge_get_vport(handle);
5878 struct hclge_dev *hdev = vport->back;
5879 u16 temp_tqps = 0;
5880 int i;
5881
5882 for (i = 0; i < hdev->num_tqps; i++) {
5883 if (!hdev->htqp[i].alloced)
5884 temp_tqps++;
5885 }
5886 *free_tqps = temp_tqps;
5887 *max_rss_size = hdev->rss_size_max;
5888}
5889
5890static void hclge_release_tqp(struct hclge_vport *vport)
5891{
5892 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5893 struct hclge_dev *hdev = vport->back;
5894 int i;
5895
5896 for (i = 0; i < kinfo->num_tqps; i++) {
5897 struct hclge_tqp *tqp =
5898 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5899
5900 tqp->q.handle = NULL;
5901 tqp->q.tqp_index = 0;
5902 tqp->alloced = false;
5903 }
5904
5905 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5906 kinfo->tqp = NULL;
5907}
5908
5909static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5910{
5911 struct hclge_vport *vport = hclge_get_vport(handle);
5912 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5913 struct hclge_dev *hdev = vport->back;
5914 int cur_rss_size = kinfo->rss_size;
5915 int cur_tqps = kinfo->num_tqps;
5916 u16 tc_offset[HCLGE_MAX_TC_NUM];
5917 u16 tc_valid[HCLGE_MAX_TC_NUM];
5918 u16 tc_size[HCLGE_MAX_TC_NUM];
5919 u16 roundup_size;
5920 u32 *rss_indir;
5921 int ret, i;
5922
ec7a62b9 5923 /* Free old tqps, and reallocate with new tqp number when nic setup */
f1f779ce
PL		 5924 hclge_release_tqp(vport);
5925
5926 ret = hclge_knic_setup(vport, new_tqps_num);
5927 if (ret) {
5928 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5929 return ret;
5930 }
5931
5932 ret = hclge_map_tqp_to_vport(hdev, vport);
5933 if (ret) {
5934 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5935 return ret;
5936 }
5937
5938 ret = hclge_tm_schd_init(hdev);
5939 if (ret) {
5940 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5941 return ret;
5942 }
5943
5944 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5945 roundup_size = ilog2(roundup_size);
5946 /* Set the RSS TC mode according to the new RSS size */
5947 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5948 tc_valid[i] = 0;
5949
5950 if (!(hdev->hw_tc_map & BIT(i)))
5951 continue;
5952
5953 tc_valid[i] = 1;
5954 tc_size[i] = roundup_size;
5955 tc_offset[i] = kinfo->rss_size * i;
5956 }
5957 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5958 if (ret)
5959 return ret;
5960
5961 /* Reinitializes the rss indirect table according to the new RSS size */
5962 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5963 if (!rss_indir)
5964 return -ENOMEM;
5965
5966 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5967 rss_indir[i] = i % kinfo->rss_size;
5968
5969 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5970 if (ret)
5971 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5972 ret);
5973
5974 kfree(rss_indir);
5975
5976 if (!ret)
5977 dev_info(&hdev->pdev->dev,
5978 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5979 cur_rss_size, kinfo->rss_size,
5980 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5981
5982 return ret;
5983}
5984
db2a3e43
FL		 5985static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5986 u32 *regs_num_64_bit)
5987{
5988 struct hclge_desc desc;
5989 u32 total_num;
5990 int ret;
5991
5992 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5993 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5994 if (ret) {
5995 dev_err(&hdev->pdev->dev,
5996 "Query register number cmd failed, ret = %d.\n", ret);
5997 return ret;
5998 }
5999
6000 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
6001 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
6002
6003 total_num = *regs_num_32_bit + *regs_num_64_bit;
6004 if (!total_num)
6005 return -EINVAL;
6006
6007 return 0;
6008}
6009
6010static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6011 void *data)
6012{
6013#define HCLGE_32_BIT_REG_RTN_DATANUM 8
6014
6015 struct hclge_desc *desc;
6016 u32 *reg_val = data;
6017 __le32 *desc_data;
6018 int cmd_num;
6019 int i, k, n;
6020 int ret;
6021
6022 if (regs_num == 0)
6023 return 0;
6024
6025 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
6026 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6027 if (!desc)
6028 return -ENOMEM;
6029
6030 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
6031 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6032 if (ret) {
6033 dev_err(&hdev->pdev->dev,
6034 "Query 32 bit register cmd failed, ret = %d.\n", ret);
6035 kfree(desc);
6036 return ret;
6037 }
6038
6039 for (i = 0; i < cmd_num; i++) {
6040 if (i == 0) {
6041 desc_data = (__le32 *)(&desc[i].data[0]);
6042 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
6043 } else {
6044 desc_data = (__le32 *)(&desc[i]);
6045 n = HCLGE_32_BIT_REG_RTN_DATANUM;
6046 }
6047 for (k = 0; k < n; k++) {
6048 *reg_val++ = le32_to_cpu(*desc_data++);
6049
6050 regs_num--;
6051 if (!regs_num)
6052 break;
6053 }
6054 }
6055
6056 kfree(desc);
6057 return 0;
6058}
6059
6060static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6061 void *data)
6062{
6063#define HCLGE_64_BIT_REG_RTN_DATANUM 4
6064
6065 struct hclge_desc *desc;
6066 u64 *reg_val = data;
6067 __le64 *desc_data;
6068 int cmd_num;
6069 int i, k, n;
6070 int ret;
6071
6072 if (regs_num == 0)
6073 return 0;
6074
6075 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
6076 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6077 if (!desc)
6078 return -ENOMEM;
6079
6080 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
6081 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6082 if (ret) {
6083 dev_err(&hdev->pdev->dev,
6084 "Query 64 bit register cmd failed, ret = %d.\n", ret);
6085 kfree(desc);
6086 return ret;
6087 }
6088
6089 for (i = 0; i < cmd_num; i++) {
6090 if (i == 0) {
6091 desc_data = (__le64 *)(&desc[i].data[0]);
6092 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
6093 } else {
6094 desc_data = (__le64 *)(&desc[i]);
6095 n = HCLGE_64_BIT_REG_RTN_DATANUM;
6096 }
6097 for (k = 0; k < n; k++) {
6098 *reg_val++ = le64_to_cpu(*desc_data++);
6099
6100 regs_num--;
6101 if (!regs_num)
6102 break;
6103 }
6104 }
6105
6106 kfree(desc);
6107 return 0;
6108}
6109
6110static int hclge_get_regs_len(struct hnae3_handle *handle)
6111{
6112 struct hclge_vport *vport = hclge_get_vport(handle);
6113 struct hclge_dev *hdev = vport->back;
6114 u32 regs_num_32_bit, regs_num_64_bit;
6115 int ret;
6116
6117 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6118 if (ret) {
6119 dev_err(&hdev->pdev->dev,
6120 "Get register number failed, ret = %d.\n", ret);
6121 return -EOPNOTSUPP;
6122 }
6123
6124 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
6125}
6126
6127static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
6128 void *data)
6129{
6130 struct hclge_vport *vport = hclge_get_vport(handle);
6131 struct hclge_dev *hdev = vport->back;
6132 u32 regs_num_32_bit, regs_num_64_bit;
6133 int ret;
6134
6135 *version = hdev->fw_version;
6136
6137 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6138 if (ret) {
6139 dev_err(&hdev->pdev->dev,
6140 "Get register number failed, ret = %d.\n", ret);
6141 return;
6142 }
6143
6144 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
6145 if (ret) {
6146 dev_err(&hdev->pdev->dev,
6147 "Get 32 bit register failed, ret = %d.\n", ret);
6148 return;
6149 }
6150
6151 data = (u32 *)data + regs_num_32_bit;
6152 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
6153 data);
6154 if (ret)
6155 dev_err(&hdev->pdev->dev,
6156 "Get 64 bit register failed, ret = %d.\n", ret);
6157}
6158
fe3a3e15 6159static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
d9a0884e
JS		 6160{
6161 struct hclge_set_led_state_cmd *req;
6162 struct hclge_desc desc;
6163 int ret;
6164
6165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
6166
6167 req = (struct hclge_set_led_state_cmd *)desc.data;
e22b531b 6168 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
d9a0884e
JS		 6169 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6170
6171 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6172 if (ret)
6173 dev_err(&hdev->pdev->dev,
6174 "Send set led state cmd error, ret =%d\n", ret);
6175
6176 return ret;
6177}
6178
6179enum hclge_led_status {
6180 HCLGE_LED_OFF,
6181 HCLGE_LED_ON,
6182 HCLGE_LED_NO_CHANGE = 0xFF,
6183};
6184
6185static int hclge_set_led_id(struct hnae3_handle *handle,
6186 enum ethtool_phys_id_state status)
6187{
d9a0884e
JS		 6188 struct hclge_vport *vport = hclge_get_vport(handle);
6189 struct hclge_dev *hdev = vport->back;
d9a0884e
JS		 6190
6191 switch (status) {
6192 case ETHTOOL_ID_ACTIVE:
fe3a3e15 6193 return hclge_set_led_status(hdev, HCLGE_LED_ON);
d9a0884e 6194 case ETHTOOL_ID_INACTIVE:
fe3a3e15 6195 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
d9a0884e 6196 default:
fe3a3e15 6197 return -EINVAL;
d9a0884e 6198 }
d9a0884e
JS		 6199}
6200
d92ceae9
FL		 6201static void hclge_get_link_mode(struct hnae3_handle *handle,
6202 unsigned long *supported,
6203 unsigned long *advertising)
6204{
6205 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
6206 struct hclge_vport *vport = hclge_get_vport(handle);
6207 struct hclge_dev *hdev = vport->back;
6208 unsigned int idx = 0;
6209
6210 for (; idx < size; idx++) {
6211 supported[idx] = hdev->hw.mac.supported[idx];
6212 advertising[idx] = hdev->hw.mac.advertising[idx];
6213 }
6214}
6215
6216static void hclge_get_port_type(struct hnae3_handle *handle,
6217 u8 *port_type)
6218{
6219 struct hclge_vport *vport = hclge_get_vport(handle);
6220 struct hclge_dev *hdev = vport->back;
6221 u8 media_type = hdev->hw.mac.media_type;
6222
6223 switch (media_type) {
6224 case HNAE3_MEDIA_TYPE_FIBER:
6225 *port_type = PORT_FIBRE;
6226 break;
6227 case HNAE3_MEDIA_TYPE_COPPER:
6228 *port_type = PORT_TP;
6229 break;
6230 case HNAE3_MEDIA_TYPE_UNKNOWN:
6231 default:
6232 *port_type = PORT_OTHER;
6233 break;
6234 }
6235}
6236
46a3df9f
S		 6237static const struct hnae3_ae_ops hclge_ops = {
6238 .init_ae_dev = hclge_init_ae_dev,
6239 .uninit_ae_dev = hclge_uninit_ae_dev,
6240 .init_client_instance = hclge_init_client_instance,
6241 .uninit_client_instance = hclge_uninit_client_instance,
63d7e66f
SM		 6242 .map_ring_to_vector = hclge_map_ring_to_vector,
6243 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 6244 .get_vector = hclge_get_vector,
7412200c 6245 .put_vector = hclge_put_vector,
46a3df9f 6246 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 6247 .set_loopback = hclge_set_loopback,
46a3df9f
S		 6248 .start = hclge_ae_start,
6249 .stop = hclge_ae_stop,
6250 .get_status = hclge_get_status,
6251 .get_ksettings_an_result = hclge_get_ksettings_an_result,
6252 .update_speed_duplex_h = hclge_update_speed_duplex_h,
6253 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6254 .get_media_type = hclge_get_media_type,
6255 .get_rss_key_size = hclge_get_rss_key_size,
6256 .get_rss_indir_size = hclge_get_rss_indir_size,
6257 .get_rss = hclge_get_rss,
6258 .set_rss = hclge_set_rss,
f7db940a 6259 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 6260 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 6261 .get_tc_size = hclge_get_tc_size,
6262 .get_mac_addr = hclge_get_mac_addr,
6263 .set_mac_addr = hclge_set_mac_addr,
6264 .add_uc_addr = hclge_add_uc_addr,
6265 .rm_uc_addr = hclge_rm_uc_addr,
6266 .add_mc_addr = hclge_add_mc_addr,
6267 .rm_mc_addr = hclge_rm_mc_addr,
a832d8b5 6268 .update_mta_status = hclge_update_mta_status,
46a3df9f
S		 6269 .set_autoneg = hclge_set_autoneg,
6270 .get_autoneg = hclge_get_autoneg,
6271 .get_pauseparam = hclge_get_pauseparam,
09ea401e 6272 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6273 .set_mtu = hclge_set_mtu,
6274 .reset_queue = hclge_reset_tqp,
6275 .get_stats = hclge_get_stats,
6276 .update_stats = hclge_update_stats,
6277 .get_strings = hclge_get_strings,
6278 .get_sset_count = hclge_get_sset_count,
6279 .get_fw_version = hclge_get_fw_version,
6280 .get_mdix_mode = hclge_get_mdix_mode,
d818396d 6281 .enable_vlan_filter = hclge_enable_vlan_filter,
4e66632d 6282 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 6283 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5f9a7732 6284 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6285 .reset_event = hclge_reset_event,
f1f779ce
PL		 6286 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6287 .set_channels = hclge_set_channels,
4f645a90 6288 .get_channels = hclge_get_channels,
a2cfbadb 6289 .get_flowctrl_adv = hclge_get_flowctrl_adv,
db2a3e43
FL		 6290 .get_regs_len = hclge_get_regs_len,
6291 .get_regs = hclge_get_regs,
d9a0884e 6292 .set_led_id = hclge_set_led_id,
d92ceae9
FL		 6293 .get_link_mode = hclge_get_link_mode,
6294 .get_port_type = hclge_get_port_type,
46a3df9f
S		 6295};
6296
6297static struct hnae3_ae_algo ae_algo = {
6298 .ops = &hclge_ops,
46a3df9f
S		 6299 .pdev_id_table = ae_algo_pci_tbl,
6300};
6301
6302static int hclge_init(void)
6303{
6304 pr_info("%s is initializing\n", HCLGE_NAME);
6305
a4d090cc
FL		 6306 hnae3_register_ae_algo(&ae_algo);
6307
6308 return 0;
46a3df9f
S		 6309}
6310
6311static void hclge_exit(void)
6312{
6313 hnae3_unregister_ae_algo(&ae_algo);
6314}
6315module_init(hclge_init);
6316module_exit(hclge_exit);
6317
6318MODULE_LICENSE("GPL");
6319MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6320MODULE_DESCRIPTION("HCLGE Driver");
6321MODULE_VERSION(HCLGE_MOD_VERSION);
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