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Revert "UBUNTU: SAUCE: {topost} net: hns3: standardize the handle of return value"
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
f2b4a171 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
46a3df9f
S		 9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
7393ed39 20#include <linux/if_vlan.h>
d5752031 21#include <net/rtnetlink.h>
46a3df9f 22#include "hclge_cmd.h"
cacde272 23#include "hclge_dcb.h"
46a3df9f 24#include "hclge_main.h"
0cdbdd3e 25#include "hclge_mbx.h"
46a3df9f
S		 26#include "hclge_mdio.h"
27#include "hclge_tm.h"
28#include "hnae3.h"
29
30#define HCLGE_NAME "hclge"
31#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35
46a3df9f
S		 36static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
37 enum hclge_mta_dmac_sel_type mta_mac_sel,
38 bool enable);
59bc85ec 39static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 40static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 41static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 42
43static struct hnae3_ae_algo ae_algo;
44
45static const struct pci_device_id ae_algo_pci_tbl[] = {
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 53 /* required last entry */
46a3df9f
S		 54 {0, }
55};
56
28d9cec8
YL		 57MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
58
46a3df9f
S		 59static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
60 "Mac Loopback test",
61 "Serdes Loopback test",
62 "Phy Loopback test"
63};
64
65static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
66 {"igu_rx_oversize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
68 {"igu_rx_undersize_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
70 {"igu_rx_out_all_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
72 {"igu_rx_uni_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
74 {"igu_rx_multi_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
76 {"igu_rx_broad_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
78 {"egu_tx_out_all_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
80 {"egu_tx_uni_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
82 {"egu_tx_multi_pkt",
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
84 {"egu_tx_broad_pkt",
85 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
86 {"ssu_ppp_mac_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
88 {"ssu_ppp_host_key_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
90 {"ppp_ssu_mac_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
92 {"ppp_ssu_host_rlt_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
94 {"ssu_tx_in_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
96 {"ssu_tx_out_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
98 {"ssu_rx_in_num",
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
100 {"ssu_rx_out_num",
101 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
102};
103
104static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
105 {"igu_rx_err_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
107 {"igu_rx_no_eof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
109 {"igu_rx_no_sof_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
111 {"egu_tx_1588_pkt",
112 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
113 {"ssu_full_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
115 {"ssu_part_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
117 {"ppp_key_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
119 {"ppp_rlt_drop_num",
120 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
121 {"ssu_key_drop_num",
122 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
123 {"pkt_curr_buf_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
125 {"qcn_fb_rcv_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
127 {"qcn_fb_drop_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
129 {"qcn_fb_invaild_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
131 {"rx_packet_tc0_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
133 {"rx_packet_tc1_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
135 {"rx_packet_tc2_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
137 {"rx_packet_tc3_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
139 {"rx_packet_tc4_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
141 {"rx_packet_tc5_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
143 {"rx_packet_tc6_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
145 {"rx_packet_tc7_in_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
147 {"rx_packet_tc0_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
149 {"rx_packet_tc1_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
151 {"rx_packet_tc2_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
153 {"rx_packet_tc3_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
155 {"rx_packet_tc4_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
157 {"rx_packet_tc5_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
159 {"rx_packet_tc6_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
161 {"rx_packet_tc7_out_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
163 {"tx_packet_tc0_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
165 {"tx_packet_tc1_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
167 {"tx_packet_tc2_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
169 {"tx_packet_tc3_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
171 {"tx_packet_tc4_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
173 {"tx_packet_tc5_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
175 {"tx_packet_tc6_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
177 {"tx_packet_tc7_in_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
179 {"tx_packet_tc0_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
181 {"tx_packet_tc1_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
183 {"tx_packet_tc2_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
185 {"tx_packet_tc3_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
187 {"tx_packet_tc4_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
189 {"tx_packet_tc5_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
191 {"tx_packet_tc6_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
193 {"tx_packet_tc7_out_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
195 {"pkt_curr_buf_tc0_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
197 {"pkt_curr_buf_tc1_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
199 {"pkt_curr_buf_tc2_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
201 {"pkt_curr_buf_tc3_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
203 {"pkt_curr_buf_tc4_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
205 {"pkt_curr_buf_tc5_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
207 {"pkt_curr_buf_tc6_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
209 {"pkt_curr_buf_tc7_cnt",
210 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
211 {"mb_uncopy_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
213 {"lo_pri_unicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
215 {"hi_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
217 {"lo_pri_multicast_rlt_drop_num",
218 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
219 {"rx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
221 {"tx_oq_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
223 {"nic_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
225 {"roc_l2_err_drop_pkt_cnt",
226 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
227};
228
229static const struct hclge_comm_stats_str g_mac_stats_string[] = {
230 {"mac_tx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
232 {"mac_rx_mac_pause_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
234 {"mac_tx_pfc_pri0_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
236 {"mac_tx_pfc_pri1_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
238 {"mac_tx_pfc_pri2_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
240 {"mac_tx_pfc_pri3_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
242 {"mac_tx_pfc_pri4_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
244 {"mac_tx_pfc_pri5_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
246 {"mac_tx_pfc_pri6_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
248 {"mac_tx_pfc_pri7_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
250 {"mac_rx_pfc_pri0_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
252 {"mac_rx_pfc_pri1_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
254 {"mac_rx_pfc_pri2_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
256 {"mac_rx_pfc_pri3_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
258 {"mac_rx_pfc_pri4_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
260 {"mac_rx_pfc_pri5_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
262 {"mac_rx_pfc_pri6_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
264 {"mac_rx_pfc_pri7_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
266 {"mac_tx_total_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
268 {"mac_tx_total_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
270 {"mac_tx_good_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
272 {"mac_tx_bad_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
274 {"mac_tx_good_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
276 {"mac_tx_bad_oct_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
278 {"mac_tx_uni_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
280 {"mac_tx_multi_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
282 {"mac_tx_broad_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
284 {"mac_tx_undersize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
f3426583
JS		 286 {"mac_tx_oversize_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 288 {"mac_tx_64_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
290 {"mac_tx_65_127_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
292 {"mac_tx_128_255_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
294 {"mac_tx_256_511_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
296 {"mac_tx_512_1023_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
298 {"mac_tx_1024_1518_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
b42874e4
JS		 300 {"mac_tx_1519_2047_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
302 {"mac_tx_2048_4095_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
304 {"mac_tx_4096_8191_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
b42874e4
JS		 306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
f3426583
JS		 336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
b42874e4
JS		 350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
b42874e4
JS		 356 {"mac_rx_8192_9216_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
358 {"mac_rx_9217_12287_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
360 {"mac_rx_12288_16383_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
362 {"mac_rx_1519_max_good_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
364 {"mac_rx_1519_max_bad_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 366
c36317be
JS		 367 {"mac_tx_fragment_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
369 {"mac_tx_undermin_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
371 {"mac_tx_jabber_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
373 {"mac_tx_err_all_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
375 {"mac_tx_from_app_good_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
377 {"mac_tx_from_app_bad_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
379 {"mac_rx_fragment_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
381 {"mac_rx_undermin_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
383 {"mac_rx_jabber_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
385 {"mac_rx_fcs_err_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
387 {"mac_rx_send_app_good_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
389 {"mac_rx_send_app_bad_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 391};
392
635bfb58
FL		 393static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
394 {
395 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
396 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
397 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
398 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
399 .i_port_bitmap = 0x1,
400 },
401};
402
46a3df9f
S		 403static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
404{
405#define HCLGE_64_BIT_CMD_NUM 5
406#define HCLGE_64_BIT_RTN_DATANUM 4
407 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
408 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 409 __le64 *desc_data;
46a3df9f
S		 410 int i, k, n;
411 int ret;
412
413 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
414 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
415 if (ret) {
416 dev_err(&hdev->pdev->dev,
417 "Get 64 bit pkt stats fail, status = %d.\n", ret);
418 return ret;
419 }
420
421 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
422 if (unlikely(i == 0)) {
a90bb9a5 423 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 424 n = HCLGE_64_BIT_RTN_DATANUM - 1;
425 } else {
a90bb9a5 426 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 427 n = HCLGE_64_BIT_RTN_DATANUM;
428 }
429 for (k = 0; k < n; k++) {
a90bb9a5 430 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 431 desc_data++;
432 }
433 }
434
435 return 0;
436}
437
438static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
439{
440 stats->pkt_curr_buf_cnt = 0;
441 stats->pkt_curr_buf_tc0_cnt = 0;
442 stats->pkt_curr_buf_tc1_cnt = 0;
443 stats->pkt_curr_buf_tc2_cnt = 0;
444 stats->pkt_curr_buf_tc3_cnt = 0;
445 stats->pkt_curr_buf_tc4_cnt = 0;
446 stats->pkt_curr_buf_tc5_cnt = 0;
447 stats->pkt_curr_buf_tc6_cnt = 0;
448 stats->pkt_curr_buf_tc7_cnt = 0;
449}
450
451static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
452{
453#define HCLGE_32_BIT_CMD_NUM 8
454#define HCLGE_32_BIT_RTN_DATANUM 8
455
456 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
457 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 458 __le32 *desc_data;
46a3df9f
S		 459 int i, k, n;
460 u64 *data;
461 int ret;
462
463 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
464 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
465
466 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
467 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
468 if (ret) {
469 dev_err(&hdev->pdev->dev,
470 "Get 32 bit pkt stats fail, status = %d.\n", ret);
471
472 return ret;
473 }
474
475 hclge_reset_partial_32bit_counter(all_32_bit_stats);
476 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
477 if (unlikely(i == 0)) {
a90bb9a5
YL		 478 __le16 *desc_data_16bit;
479
46a3df9f 480 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 481 le32_to_cpu(desc[i].data[0]);
482
483 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 484 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 485 le16_to_cpu(*desc_data_16bit);
486
487 desc_data_16bit++;
46a3df9f 488 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 489 le16_to_cpu(*desc_data_16bit);
46a3df9f 490
a90bb9a5 491 desc_data = &desc[i].data[2];
46a3df9f
S		 492 n = HCLGE_32_BIT_RTN_DATANUM - 4;
493 } else {
a90bb9a5 494 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 495 n = HCLGE_32_BIT_RTN_DATANUM;
496 }
497 for (k = 0; k < n; k++) {
a90bb9a5 498 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 499 desc_data++;
500 }
501 }
502
503 return 0;
504}
505
506static int hclge_mac_update_stats(struct hclge_dev *hdev)
507{
b42874e4 508#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 509#define HCLGE_RTN_DATA_NUM 4
510
511 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
512 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 513 __le64 *desc_data;
46a3df9f
S		 514 int i, k, n;
515 int ret;
516
517 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
518 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
519 if (ret) {
520 dev_err(&hdev->pdev->dev,
521 "Get MAC pkt stats fail, status = %d.\n", ret);
522
523 return ret;
524 }
525
526 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
527 if (unlikely(i == 0)) {
a90bb9a5 528 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 529 n = HCLGE_RTN_DATA_NUM - 2;
530 } else {
a90bb9a5 531 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 532 n = HCLGE_RTN_DATA_NUM;
533 }
534 for (k = 0; k < n; k++) {
a90bb9a5 535 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 536 desc_data++;
537 }
538 }
539
540 return 0;
541}
542
543static int hclge_tqps_update_stats(struct hnae3_handle *handle)
544{
545 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
546 struct hclge_vport *vport = hclge_get_vport(handle);
547 struct hclge_dev *hdev = vport->back;
548 struct hnae3_queue *queue;
549 struct hclge_desc desc[1];
550 struct hclge_tqp *tqp;
551 int ret, i;
552
553 for (i = 0; i < kinfo->num_tqps; i++) {
554 queue = handle->kinfo.tqp[i];
555 tqp = container_of(queue, struct hclge_tqp, q);
556 /* command : HCLGE_OPC_QUERY_IGU_STAT */
557 hclge_cmd_setup_basic_desc(&desc[0],
558 HCLGE_OPC_QUERY_RX_STATUS,
559 true);
560
a90bb9a5 561 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 562 ret = hclge_cmd_send(&hdev->hw, desc, 1);
563 if (ret) {
564 dev_err(&hdev->pdev->dev,
565 "Query tqp stat fail, status = %d,queue = %d\n",
566 ret, i);
567 return ret;
568 }
569 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 570 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 571 }
572
573 for (i = 0; i < kinfo->num_tqps; i++) {
574 queue = handle->kinfo.tqp[i];
575 tqp = container_of(queue, struct hclge_tqp, q);
576 /* command : HCLGE_OPC_QUERY_IGU_STAT */
577 hclge_cmd_setup_basic_desc(&desc[0],
578 HCLGE_OPC_QUERY_TX_STATUS,
579 true);
580
a90bb9a5 581 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 582 ret = hclge_cmd_send(&hdev->hw, desc, 1);
583 if (ret) {
584 dev_err(&hdev->pdev->dev,
585 "Query tqp stat fail, status = %d,queue = %d\n",
586 ret, i);
587 return ret;
588 }
589 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 590 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 591 }
592
593 return 0;
594}
595
596static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
597{
598 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
599 struct hclge_tqp *tqp;
600 u64 *buff = data;
601 int i;
602
603 for (i = 0; i < kinfo->num_tqps; i++) {
604 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 605 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 606 }
607
608 for (i = 0; i < kinfo->num_tqps; i++) {
609 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 610 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 611 }
612
613 return buff;
614}
615
616static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
617{
618 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
619
620 return kinfo->num_tqps * (2);
621}
622
623static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
624{
625 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
626 u8 *buff = data;
627 int i = 0;
628
629 for (i = 0; i < kinfo->num_tqps; i++) {
630 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
631 struct hclge_tqp, q);
c36317be 632 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
46a3df9f
S		 633 tqp->index);
634 buff = buff + ETH_GSTRING_LEN;
635 }
636
637 for (i = 0; i < kinfo->num_tqps; i++) {
638 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
639 struct hclge_tqp, q);
c36317be 640 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
46a3df9f
S		 641 tqp->index);
642 buff = buff + ETH_GSTRING_LEN;
643 }
644
645 return buff;
646}
647
648static u64 *hclge_comm_get_stats(void *comm_stats,
649 const struct hclge_comm_stats_str strs[],
650 int size, u64 *data)
651{
652 u64 *buf = data;
653 u32 i;
654
655 for (i = 0; i < size; i++)
656 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
657
658 return buf + size;
659}
660
661static u8 *hclge_comm_get_strings(u32 stringset,
662 const struct hclge_comm_stats_str strs[],
663 int size, u8 *data)
664{
665 char *buff = (char *)data;
666 u32 i;
667
668 if (stringset != ETH_SS_STATS)
669 return buff;
670
671 for (i = 0; i < size; i++) {
672 snprintf(buff, ETH_GSTRING_LEN,
673 strs[i].desc);
674 buff = buff + ETH_GSTRING_LEN;
675 }
676
677 return (u8 *)buff;
678}
679
680static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
681 struct net_device_stats *net_stats)
682{
683 net_stats->tx_dropped = 0;
684 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
685 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
686 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
687
f3426583 688 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 689 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
46a3df9f
S		 690 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
691 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
c36317be 692 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 693
694 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
695 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
696
c36317be 697 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 698 net_stats->rx_length_errors =
699 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
700 net_stats->rx_length_errors +=
f3426583 701 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 702 net_stats->rx_over_errors =
f3426583 703 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 704}
705
706static void hclge_update_stats_for_all(struct hclge_dev *hdev)
707{
708 struct hnae3_handle *handle;
709 int status;
710
711 handle = &hdev->vport[0].nic;
712 if (handle->client) {
713 status = hclge_tqps_update_stats(handle);
714 if (status) {
715 dev_err(&hdev->pdev->dev,
716 "Update TQPS stats fail, status = %d.\n",
717 status);
718 }
719 }
720
721 status = hclge_mac_update_stats(hdev);
722 if (status)
723 dev_err(&hdev->pdev->dev,
724 "Update MAC stats fail, status = %d.\n", status);
725
726 status = hclge_32_bit_update_stats(hdev);
727 if (status)
728 dev_err(&hdev->pdev->dev,
729 "Update 32 bit stats fail, status = %d.\n",
730 status);
731
732 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
733}
734
735static void hclge_update_stats(struct hnae3_handle *handle,
736 struct net_device_stats *net_stats)
737{
738 struct hclge_vport *vport = hclge_get_vport(handle);
739 struct hclge_dev *hdev = vport->back;
740 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
741 int status;
742
7a5d2a39
JS		 743 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
744 return;
745
46a3df9f
S		 746 status = hclge_mac_update_stats(hdev);
747 if (status)
748 dev_err(&hdev->pdev->dev,
749 "Update MAC stats fail, status = %d.\n",
750 status);
751
752 status = hclge_32_bit_update_stats(hdev);
753 if (status)
754 dev_err(&hdev->pdev->dev,
755 "Update 32 bit stats fail, status = %d.\n",
756 status);
757
758 status = hclge_64_bit_update_stats(hdev);
759 if (status)
760 dev_err(&hdev->pdev->dev,
761 "Update 64 bit stats fail, status = %d.\n",
762 status);
763
764 status = hclge_tqps_update_stats(handle);
765 if (status)
766 dev_err(&hdev->pdev->dev,
767 "Update TQPS stats fail, status = %d.\n",
768 status);
769
770 hclge_update_netstat(hw_stats, net_stats);
7a5d2a39
JS		 771
772 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 773}
774
775static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
776{
777#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
778
779 struct hclge_vport *vport = hclge_get_vport(handle);
780 struct hclge_dev *hdev = vport->back;
781 int count = 0;
782
783 /* Loopback test support rules:
784 * mac: only GE mode support
785 * serdes: all mac mode will support include GE/XGE/LGE/CGE
786 * phy: only support when phy device exist on board
787 */
788 if (stringset == ETH_SS_TEST) {
789 /* clear loopback bit flags at first */
790 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
791 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
792 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
793 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
794 count += 1;
795 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
46a3df9f 796 }
2fd5416a
YL		 797
798 count ++;
799 handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK;
46a3df9f
S		 800 } else if (stringset == ETH_SS_STATS) {
801 count = ARRAY_SIZE(g_mac_stats_string) +
802 ARRAY_SIZE(g_all_32bit_stats_string) +
803 ARRAY_SIZE(g_all_64bit_stats_string) +
804 hclge_tqps_get_sset_count(handle, stringset);
805 }
806
807 return count;
808}
809
810static void hclge_get_strings(struct hnae3_handle *handle,
811 u32 stringset,
812 u8 *data)
813{
814 u8 *p = (char *)data;
815 int size;
816
817 if (stringset == ETH_SS_STATS) {
818 size = ARRAY_SIZE(g_mac_stats_string);
819 p = hclge_comm_get_strings(stringset,
820 g_mac_stats_string,
821 size,
822 p);
823 size = ARRAY_SIZE(g_all_32bit_stats_string);
824 p = hclge_comm_get_strings(stringset,
825 g_all_32bit_stats_string,
826 size,
827 p);
828 size = ARRAY_SIZE(g_all_64bit_stats_string);
829 p = hclge_comm_get_strings(stringset,
830 g_all_64bit_stats_string,
831 size,
832 p);
833 p = hclge_tqps_get_strings(handle, p);
834 } else if (stringset == ETH_SS_TEST) {
835 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
836 memcpy(p,
837 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
838 ETH_GSTRING_LEN);
839 p += ETH_GSTRING_LEN;
840 }
841 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
842 memcpy(p,
843 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
844 ETH_GSTRING_LEN);
845 p += ETH_GSTRING_LEN;
846 }
847 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
848 memcpy(p,
849 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
850 ETH_GSTRING_LEN);
851 p += ETH_GSTRING_LEN;
852 }
853 }
854}
855
856static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
857{
858 struct hclge_vport *vport = hclge_get_vport(handle);
859 struct hclge_dev *hdev = vport->back;
860 u64 *p;
861
862 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
863 g_mac_stats_string,
864 ARRAY_SIZE(g_mac_stats_string),
865 data);
866 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
867 g_all_32bit_stats_string,
868 ARRAY_SIZE(g_all_32bit_stats_string),
869 p);
870 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
871 g_all_64bit_stats_string,
872 ARRAY_SIZE(g_all_64bit_stats_string),
873 p);
874 p = hclge_tqps_get_stats(handle, p);
875}
876
877static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 878 struct hclge_func_status_cmd *status)
46a3df9f
S		 879{
880 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
881 return -EINVAL;
882
883 /* Set the pf to main pf */
884 if (status->pf_state & HCLGE_PF_STATE_MAIN)
885 hdev->flag |= HCLGE_FLAG_MAIN;
886 else
887 hdev->flag &= ~HCLGE_FLAG_MAIN;
888
46a3df9f
S		 889 return 0;
890}
891
892static int hclge_query_function_status(struct hclge_dev *hdev)
893{
d44f9b63 894 struct hclge_func_status_cmd *req;
46a3df9f
S		 895 struct hclge_desc desc;
896 int timeout = 0;
897 int ret;
898
899 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 900 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 901
902 do {
903 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
904 if (ret) {
905 dev_err(&hdev->pdev->dev,
906 "query function status failed %d.\n",
907 ret);
908
909 return ret;
910 }
911
912 /* Check pf reset is done */
913 if (req->pf_state)
914 break;
915 usleep_range(1000, 2000);
916 } while (timeout++ < 5);
917
918 ret = hclge_parse_func_status(hdev, req);
919
920 return ret;
921}
922
923static int hclge_query_pf_resource(struct hclge_dev *hdev)
924{
d44f9b63 925 struct hclge_pf_res_cmd *req;
46a3df9f
S		 926 struct hclge_desc desc;
927 int ret;
928
929 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
930 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
931 if (ret) {
932 dev_err(&hdev->pdev->dev,
933 "query pf resource failed %d.\n", ret);
934 return ret;
935 }
936
d44f9b63 937 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 938 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
939 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
940
e92a0843 941 if (hnae3_dev_roce_supported(hdev)) {
887c3820 942 hdev->num_roce_msi =
e22b531b
HT		 943 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
944 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 945
946 /* PF should have NIC vectors and Roce vectors,
947 * NIC vectors are queued before Roce vectors.
948 */
887c3820 949 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 950 } else {
951 hdev->num_msi =
e22b531b
HT		 952 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
953 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 954 }
955
956 return 0;
957}
958
959static int hclge_parse_speed(int speed_cmd, int *speed)
960{
961 switch (speed_cmd) {
962 case 6:
963 *speed = HCLGE_MAC_SPEED_10M;
964 break;
965 case 7:
966 *speed = HCLGE_MAC_SPEED_100M;
967 break;
968 case 0:
969 *speed = HCLGE_MAC_SPEED_1G;
970 break;
971 case 1:
972 *speed = HCLGE_MAC_SPEED_10G;
973 break;
974 case 2:
975 *speed = HCLGE_MAC_SPEED_25G;
976 break;
977 case 3:
978 *speed = HCLGE_MAC_SPEED_40G;
979 break;
980 case 4:
981 *speed = HCLGE_MAC_SPEED_50G;
982 break;
983 case 5:
984 *speed = HCLGE_MAC_SPEED_100G;
985 break;
986 default:
987 return -EINVAL;
988 }
989
990 return 0;
991}
992
d92ceae9
FL		 993static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
994 u8 speed_ability)
995{
996 unsigned long *supported = hdev->hw.mac.supported;
997
998 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
999 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1000 supported);
1001
1002 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1003 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1004 supported);
1005
1006 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1007 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1008 supported);
1009
1010 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1011 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1012 supported);
1013
1014 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1015 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1016 supported);
1017
1018 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
1019 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1020}
1021
1022static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
1023{
1024 u8 media_type = hdev->hw.mac.media_type;
1025
1026 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
1027 return;
1028
1029 hclge_parse_fiber_link_mode(hdev, speed_ability);
1030}
1031
46a3df9f
S		 1032static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1033{
d44f9b63 1034 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1035 u64 mac_addr_tmp_high;
1036 u64 mac_addr_tmp;
1037 int i;
1038
d44f9b63 1039 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 1040
1041 /* get the configuration */
e22b531b
HT		 1042 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1043 HCLGE_CFG_VMDQ_M,
1044 HCLGE_CFG_VMDQ_S);
1045 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1046 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1047 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1048 HCLGE_CFG_TQP_DESC_N_M,
1049 HCLGE_CFG_TQP_DESC_N_S);
1050
1051 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1052 HCLGE_CFG_PHY_ADDR_M,
1053 HCLGE_CFG_PHY_ADDR_S);
1054 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1055 HCLGE_CFG_MEDIA_TP_M,
1056 HCLGE_CFG_MEDIA_TP_S);
1057 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1058 HCLGE_CFG_RX_BUF_LEN_M,
1059 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 1060 /* get mac_address */
1061 mac_addr_tmp = __le32_to_cpu(req->param[2]);
e22b531b
HT		 1062 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1063 HCLGE_CFG_MAC_ADDR_H_M,
1064 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 1065
1066 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1067
e22b531b
HT		 1068 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1069 HCLGE_CFG_DEFAULT_SPEED_M,
1070 HCLGE_CFG_DEFAULT_SPEED_S);
1071 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1072 HCLGE_CFG_RSS_SIZE_M,
1073 HCLGE_CFG_RSS_SIZE_S);
c408e202 1074
46a3df9f
S		 1075 for (i = 0; i < ETH_ALEN; i++)
1076 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1077
d44f9b63 1078 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 1079 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
d92ceae9 1080
e22b531b
HT		 1081 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1082 HCLGE_CFG_SPEED_ABILITY_M,
1083 HCLGE_CFG_SPEED_ABILITY_S);
46a3df9f
S		 1084}
1085
1086/* hclge_get_cfg: query the static parameter from flash
1087 * @hdev: pointer to struct hclge_dev
1088 * @hcfg: the config structure to be getted
1089 */
1090static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1091{
1092 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 1093 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1094 int i, ret;
1095
1096 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1097 u32 offset = 0;
1098
d44f9b63 1099 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1100 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1101 true);
e22b531b
HT		 1102 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1103 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 1104 /* Len should be united by 4 bytes when send to hardware */
e22b531b
HT		 1105 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1106 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1107 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1108 }
1109
1110 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1111 if (ret) {
930ff2f6 1112 dev_err(&hdev->pdev->dev,
1113 "get config failed %d.\n", ret);
46a3df9f
S		 1114 return ret;
1115 }
1116
1117 hclge_parse_cfg(hcfg, desc);
1118 return 0;
1119}
1120
1121static int hclge_get_cap(struct hclge_dev *hdev)
1122{
1123 int ret;
1124
1125 ret = hclge_query_function_status(hdev);
1126 if (ret) {
1127 dev_err(&hdev->pdev->dev,
1128 "query function status error %d.\n", ret);
1129 return ret;
1130 }
1131
1132 /* get pf resource */
1133 ret = hclge_query_pf_resource(hdev);
930ff2f6 1134 if (ret) {
1135 dev_err(&hdev->pdev->dev,
1136 "query pf resource error %d.\n", ret);
1137 return ret;
1138 }
46a3df9f 1139
930ff2f6 1140 return 0;
46a3df9f
S		 1141}
1142
1143static int hclge_configure(struct hclge_dev *hdev)
1144{
1145 struct hclge_cfg cfg;
1146 int ret, i;
1147
1148 ret = hclge_get_cfg(hdev, &cfg);
1149 if (ret) {
1150 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1151 return ret;
1152 }
1153
1154 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1155 hdev->base_tqp_pid = 0;
c408e202 1156 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 1157 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1158 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1159 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1160 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1161 hdev->num_desc = cfg.tqp_desc_num;
1162 hdev->tm_info.num_pg = 1;
cacde272 1163 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1164 hdev->tm_info.hw_pfc_map = 0;
1165
1166 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1167 if (ret) {
1168 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1169 return ret;
1170 }
1171
d92ceae9
FL		 1172 hclge_parse_link_mode(hdev, cfg.speed_ability);
1173
cacde272
YL		 1174 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1175 (hdev->tc_max < 1)) {
46a3df9f 1176 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1177 hdev->tc_max);
1178 hdev->tc_max = 1;
46a3df9f
S		 1179 }
1180
cacde272
YL		 1181 /* Dev does not support DCB */
1182 if (!hnae3_dev_dcb_supported(hdev)) {
1183 hdev->tc_max = 1;
1184 hdev->pfc_max = 0;
1185 } else {
1186 hdev->pfc_max = hdev->tc_max;
1187 }
1188
1189 hdev->tm_info.num_tc = hdev->tc_max;
1190
46a3df9f 1191 /* Currently not support uncontiuous tc */
cacde272 1192 for (i = 0; i < hdev->tm_info.num_tc; i++)
e22b531b 1193 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 1194
f8362fe1 1195 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 1196
1197 return ret;
1198}
1199
1200static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1201 int tso_mss_max)
1202{
d44f9b63 1203 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1204 struct hclge_desc desc;
a90bb9a5 1205 u16 tso_mss;
46a3df9f
S		 1206
1207 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1208
d44f9b63 1209 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1210
1211 tso_mss = 0;
e22b531b
HT		 1212 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1213 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1214 req->tso_mss_min = cpu_to_le16(tso_mss);
1215
1216 tso_mss = 0;
e22b531b
HT		 1217 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1218 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1219 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1220
1221 return hclge_cmd_send(&hdev->hw, &desc, 1);
1222}
1223
1224static int hclge_alloc_tqps(struct hclge_dev *hdev)
1225{
1226 struct hclge_tqp *tqp;
1227 int i;
1228
1229 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1230 sizeof(struct hclge_tqp), GFP_KERNEL);
1231 if (!hdev->htqp)
1232 return -ENOMEM;
1233
1234 tqp = hdev->htqp;
1235
1236 for (i = 0; i < hdev->num_tqps; i++) {
1237 tqp->dev = &hdev->pdev->dev;
1238 tqp->index = i;
1239
1240 tqp->q.ae_algo = &ae_algo;
1241 tqp->q.buf_size = hdev->rx_buf_len;
1242 tqp->q.desc_num = hdev->num_desc;
1243 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1244 i * HCLGE_TQP_REG_SIZE;
1245
1246 tqp++;
1247 }
1248
1249 return 0;
1250}
1251
1252static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1253 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1254{
d44f9b63 1255 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1256 struct hclge_desc desc;
1257 int ret;
1258
1259 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1260
d44f9b63 1261 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1262 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1263 req->tqp_vf = func_id;
46a3df9f
S		 1264 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1265 1 << HCLGE_TQP_MAP_EN_B;
1266 req->tqp_vid = cpu_to_le16(tqp_vid);
1267
1268 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 1269 if (ret) {
1270 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1271 ret);
1272 return ret;
1273 }
46a3df9f 1274
930ff2f6 1275 return 0;
46a3df9f
S		 1276}
1277
1278static int hclge_assign_tqp(struct hclge_vport *vport,
1279 struct hnae3_queue **tqp, u16 num_tqps)
1280{
1281 struct hclge_dev *hdev = vport->back;
7df7dad6 1282 int i, alloced;
46a3df9f
S		 1283
1284 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1285 alloced < num_tqps; i++) {
1286 if (!hdev->htqp[i].alloced) {
1287 hdev->htqp[i].q.handle = &vport->nic;
1288 hdev->htqp[i].q.tqp_index = alloced;
1289 tqp[alloced] = &hdev->htqp[i].q;
1290 hdev->htqp[i].alloced = true;
46a3df9f
S		 1291 alloced++;
1292 }
1293 }
1294 vport->alloc_tqps = num_tqps;
1295
1296 return 0;
1297}
1298
1299static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1300{
1301 struct hnae3_handle *nic = &vport->nic;
1302 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1303 struct hclge_dev *hdev = vport->back;
1304 int i, ret;
1305
1306 kinfo->num_desc = hdev->num_desc;
1307 kinfo->rx_buf_len = hdev->rx_buf_len;
1308 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1309 kinfo->rss_size
1310 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1311 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1312
1313 for (i = 0; i < HNAE3_MAX_TC; i++) {
1314 if (hdev->hw_tc_map & BIT(i)) {
1315 kinfo->tc_info[i].enable = true;
1316 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1317 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1318 kinfo->tc_info[i].tc = i;
1319 } else {
1320 /* Set to default queue if TC is disable */
1321 kinfo->tc_info[i].enable = false;
1322 kinfo->tc_info[i].tqp_offset = 0;
1323 kinfo->tc_info[i].tqp_count = 1;
1324 kinfo->tc_info[i].tc = 0;
1325 }
1326 }
1327
1328 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1329 sizeof(struct hnae3_queue *), GFP_KERNEL);
1330 if (!kinfo->tqp)
1331 return -ENOMEM;
1332
1333 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
930ff2f6 1334 if (ret) {
46a3df9f 1335 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
930ff2f6 1336 return -EINVAL;
1337 }
46a3df9f 1338
930ff2f6 1339 return 0;
46a3df9f
S		 1340}
1341
7df7dad6
L		 1342static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1343 struct hclge_vport *vport)
1344{
1345 struct hnae3_handle *nic = &vport->nic;
1346 struct hnae3_knic_private_info *kinfo;
1347 u16 i;
1348
1349 kinfo = &nic->kinfo;
1350 for (i = 0; i < kinfo->num_tqps; i++) {
1351 struct hclge_tqp *q =
1352 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1353 bool is_pf;
1354 int ret;
1355
1356 is_pf = !(vport->vport_id);
1357 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1358 i, is_pf);
1359 if (ret)
1360 return ret;
1361 }
1362
1363 return 0;
1364}
1365
1366static int hclge_map_tqp(struct hclge_dev *hdev)
1367{
1368 struct hclge_vport *vport = hdev->vport;
1369 u16 i, num_vport;
1370
1371 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1372 for (i = 0; i < num_vport; i++) {
1373 int ret;
1374
1375 ret = hclge_map_tqp_to_vport(hdev, vport);
1376 if (ret)
1377 return ret;
1378
1379 vport++;
1380 }
1381
1382 return 0;
1383}
1384
46a3df9f
S		 1385static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1386{
1387 /* this would be initialized later */
1388}
1389
1390static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1391{
1392 struct hnae3_handle *nic = &vport->nic;
1393 struct hclge_dev *hdev = vport->back;
1394 int ret;
1395
1396 nic->pdev = hdev->pdev;
1397 nic->ae_algo = &ae_algo;
1398 nic->numa_node_mask = hdev->numa_node_mask;
1399
1400 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1401 ret = hclge_knic_setup(vport, num_tqps);
1402 if (ret) {
1403 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1404 ret);
1405 return ret;
1406 }
1407 } else {
1408 hclge_unic_setup(vport, num_tqps);
1409 }
1410
1411 return 0;
1412}
1413
1414static int hclge_alloc_vport(struct hclge_dev *hdev)
1415{
1416 struct pci_dev *pdev = hdev->pdev;
1417 struct hclge_vport *vport;
1418 u32 tqp_main_vport;
1419 u32 tqp_per_vport;
1420 int num_vport, i;
1421 int ret;
1422
1423 /* We need to alloc a vport for main NIC of PF */
1424 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1425
b76edfb2
HT		 1426 if (hdev->num_tqps < num_vport) {
1427 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1428 hdev->num_tqps, num_vport);
1429 return -EINVAL;
1430 }
46a3df9f
S		 1431
1432 /* Alloc the same number of TQPs for every vport */
1433 tqp_per_vport = hdev->num_tqps / num_vport;
1434 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1435
1436 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1437 GFP_KERNEL);
1438 if (!vport)
1439 return -ENOMEM;
1440
1441 hdev->vport = vport;
1442 hdev->num_alloc_vport = num_vport;
1443
bc59f827
FL		 1444 if (IS_ENABLED(CONFIG_PCI_IOV))
1445 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1446
1447 for (i = 0; i < num_vport; i++) {
1448 vport->back = hdev;
1449 vport->vport_id = i;
1450
1451 if (i == 0)
1452 ret = hclge_vport_setup(vport, tqp_main_vport);
1453 else
1454 ret = hclge_vport_setup(vport, tqp_per_vport);
1455 if (ret) {
1456 dev_err(&pdev->dev,
1457 "vport setup failed for vport %d, %d\n",
1458 i, ret);
1459 return ret;
1460 }
1461
1462 vport++;
1463 }
1464
1465 return 0;
1466}
1467
acf61ecd
YL		 1468static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1469 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1470{
1471/* TX buffer size is unit by 128 byte */
1472#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1473#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1474 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1475 struct hclge_desc desc;
1476 int ret;
1477 u8 i;
1478
d44f9b63 1479 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1480
1481 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1482 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1483 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1484
46a3df9f
S		 1485 req->tx_pkt_buff[i] =
1486 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1487 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1488 }
46a3df9f
S		 1489
1490 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 1491 if (ret) {
46a3df9f
S		 1492 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1493 ret);
930ff2f6 1494 return ret;
1495 }
46a3df9f 1496
930ff2f6 1497 return 0;
46a3df9f
S		 1498}
1499
acf61ecd
YL		 1500static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1501 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1502{
acf61ecd 1503 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1504
930ff2f6 1505 if (ret) {
1506 dev_err(&hdev->pdev->dev,
1507 "tx buffer alloc failed %d\n", ret);
1508 return ret;
1509 }
46a3df9f 1510
930ff2f6 1511 return 0;
46a3df9f
S		 1512}
1513
1514static int hclge_get_tc_num(struct hclge_dev *hdev)
1515{
1516 int i, cnt = 0;
1517
1518 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1519 if (hdev->hw_tc_map & BIT(i))
1520 cnt++;
1521 return cnt;
1522}
1523
1524static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1525{
1526 int i, cnt = 0;
1527
1528 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1529 if (hdev->hw_tc_map & BIT(i) &&
1530 hdev->tm_info.hw_pfc_map & BIT(i))
1531 cnt++;
1532 return cnt;
1533}
1534
1535/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1536static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1537 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1538{
1539 struct hclge_priv_buf *priv;
1540 int i, cnt = 0;
1541
1542 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1543 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1544 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1545 priv->enable)
1546 cnt++;
1547 }
1548
1549 return cnt;
1550}
1551
1552/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1553static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1554 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1555{
1556 struct hclge_priv_buf *priv;
1557 int i, cnt = 0;
1558
1559 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1560 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1561 if (hdev->hw_tc_map & BIT(i) &&
1562 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1563 priv->enable)
1564 cnt++;
1565 }
1566
1567 return cnt;
1568}
1569
acf61ecd 1570static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1571{
1572 struct hclge_priv_buf *priv;
1573 u32 rx_priv = 0;
1574 int i;
1575
1576 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1577 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1578 if (priv->enable)
1579 rx_priv += priv->buf_size;
1580 }
1581 return rx_priv;
1582}
1583
acf61ecd 1584static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1585{
1586 u32 i, total_tx_size = 0;
1587
1588 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1589 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1590
1591 return total_tx_size;
1592}
1593
acf61ecd
YL		 1594static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1595 struct hclge_pkt_buf_alloc *buf_alloc,
1596 u32 rx_all)
46a3df9f
S		 1597{
1598 u32 shared_buf_min, shared_buf_tc, shared_std;
1599 int tc_num, pfc_enable_num;
1600 u32 shared_buf;
1601 u32 rx_priv;
1602 int i;
1603
1604 tc_num = hclge_get_tc_num(hdev);
1605 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1606
d221df4e
YL		 1607 if (hnae3_dev_dcb_supported(hdev))
1608 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1609 else
1610 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1611
46a3df9f
S		 1612 shared_buf_tc = pfc_enable_num * hdev->mps +
1613 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1614 hdev->mps;
1615 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1616
acf61ecd 1617 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1618 if (rx_all <= rx_priv + shared_std)
1619 return false;
1620
1621 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1622 buf_alloc->s_buf.buf_size = shared_buf;
1623 buf_alloc->s_buf.self.high = shared_buf;
1624 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1625
1626 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1627 if ((hdev->hw_tc_map & BIT(i)) &&
1628 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1629 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1630 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1631 } else {
acf61ecd
YL		 1632 buf_alloc->s_buf.tc_thrd[i].low = 0;
1633 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1634 }
1635 }
1636
1637 return true;
1638}
1639
acf61ecd
YL		 1640static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1641 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1642{
1643 u32 i, total_size;
1644
1645 total_size = hdev->pkt_buf_size;
1646
1647 /* alloc tx buffer for all enabled tc */
1648 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1649 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1650
1651 if (total_size < HCLGE_DEFAULT_TX_BUF)
1652 return -ENOMEM;
1653
1654 if (hdev->hw_tc_map & BIT(i))
1655 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1656 else
1657 priv->tx_buf_size = 0;
1658
1659 total_size -= priv->tx_buf_size;
1660 }
1661
1662 return 0;
1663}
1664
46a3df9f
S		 1665/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1666 * @hdev: pointer to struct hclge_dev
acf61ecd 1667 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1668 * @return: 0: calculate sucessful, negative: fail
1669 */
1db9b1bf
YL		 1670static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1671 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1672{
9ffe79a9 1673 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1674 int no_pfc_priv_num, pfc_priv_num;
1675 struct hclge_priv_buf *priv;
1676 int i;
1677
acf61ecd 1678 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1679
d602a525
YL		 1680 /* When DCB is not supported, rx private
1681 * buffer is not allocated.
1682 */
1683 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1684 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1685 return -ENOMEM;
1686
1687 return 0;
1688 }
1689
46a3df9f
S		 1690 /* step 1, try to alloc private buffer for all enabled tc */
1691 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1692 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1693 if (hdev->hw_tc_map & BIT(i)) {
1694 priv->enable = 1;
1695 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1696 priv->wl.low = hdev->mps;
1697 priv->wl.high = priv->wl.low + hdev->mps;
1698 priv->buf_size = priv->wl.high +
1699 HCLGE_DEFAULT_DV;
1700 } else {
1701 priv->wl.low = 0;
1702 priv->wl.high = 2 * hdev->mps;
1703 priv->buf_size = priv->wl.high;
1704 }
bb1fe9ea
YL		 1705 } else {
1706 priv->enable = 0;
1707 priv->wl.low = 0;
1708 priv->wl.high = 0;
1709 priv->buf_size = 0;
46a3df9f
S		 1710 }
1711 }
1712
acf61ecd 1713 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1714 return 0;
1715
1716 /* step 2, try to decrease the buffer size of
1717 * no pfc TC's private buffer
1718 */
1719 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1720 priv = &buf_alloc->priv_buf[i];
46a3df9f 1721
bb1fe9ea
YL		 1722 priv->enable = 0;
1723 priv->wl.low = 0;
1724 priv->wl.high = 0;
1725 priv->buf_size = 0;
1726
1727 if (!(hdev->hw_tc_map & BIT(i)))
1728 continue;
1729
1730 priv->enable = 1;
46a3df9f
S		 1731
1732 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1733 priv->wl.low = 128;
1734 priv->wl.high = priv->wl.low + hdev->mps;
1735 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1736 } else {
1737 priv->wl.low = 0;
1738 priv->wl.high = hdev->mps;
1739 priv->buf_size = priv->wl.high;
1740 }
1741 }
1742
acf61ecd 1743 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1744 return 0;
1745
1746 /* step 3, try to reduce the number of pfc disabled TCs,
1747 * which have private buffer
1748 */
1749 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1750 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1751
1752 /* let the last to be cleared first */
1753 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1754 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1755
1756 if (hdev->hw_tc_map & BIT(i) &&
1757 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1758 /* Clear the no pfc TC private buffer */
1759 priv->wl.low = 0;
1760 priv->wl.high = 0;
1761 priv->buf_size = 0;
1762 priv->enable = 0;
1763 no_pfc_priv_num--;
1764 }
1765
acf61ecd 1766 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1767 no_pfc_priv_num == 0)
1768 break;
1769 }
1770
acf61ecd 1771 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1772 return 0;
1773
1774 /* step 4, try to reduce the number of pfc enabled TCs
1775 * which have private buffer.
1776 */
acf61ecd 1777 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1778
1779 /* let the last to be cleared first */
1780 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1781 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1782
1783 if (hdev->hw_tc_map & BIT(i) &&
1784 hdev->tm_info.hw_pfc_map & BIT(i)) {
1785 /* Reduce the number of pfc TC with private buffer */
1786 priv->wl.low = 0;
1787 priv->enable = 0;
1788 priv->wl.high = 0;
1789 priv->buf_size = 0;
1790 pfc_priv_num--;
1791 }
1792
acf61ecd 1793 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1794 pfc_priv_num == 0)
1795 break;
1796 }
acf61ecd 1797 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1798 return 0;
1799
1800 return -ENOMEM;
1801}
1802
acf61ecd
YL		 1803static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1804 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1805{
d44f9b63 1806 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1807 struct hclge_desc desc;
1808 int ret;
1809 int i;
1810
1811 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1812 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1813
1814 /* Alloc private buffer TCs */
1815 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1816 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1817
1818 req->buf_num[i] =
1819 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1820 req->buf_num[i] |=
5bca3b94 1821 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1822 }
1823
b8c8bf47 1824 req->shared_buf =
acf61ecd 1825 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1826 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1827
46a3df9f 1828 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 1829 if (ret) {
46a3df9f
S		 1830 dev_err(&hdev->pdev->dev,
1831 "rx private buffer alloc cmd failed %d\n", ret);
930ff2f6 1832 return ret;
1833 }
46a3df9f 1834
930ff2f6 1835 return 0;
46a3df9f
S		 1836}
1837
8cc87583 1838#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1839
acf61ecd
YL		 1840static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1841 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1842{
1843 struct hclge_rx_priv_wl_buf *req;
1844 struct hclge_priv_buf *priv;
1845 struct hclge_desc desc[2];
1846 int i, j;
1847 int ret;
1848
1849 for (i = 0; i < 2; i++) {
1850 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1851 false);
1852 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1853
1854 /* The first descriptor set the NEXT bit to 1 */
1855 if (i == 0)
1856 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1857 else
1858 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1859
1860 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1861 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1862
1863 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1864 req->tc_wl[j].high =
1865 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1866 req->tc_wl[j].high |=
8cc87583 1867 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1868 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1869 req->tc_wl[j].low =
1870 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1871 req->tc_wl[j].low |=
8cc87583 1872 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1873 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1874 }
1875 }
1876
1877 /* Send 2 descriptor at one time */
1878 ret = hclge_cmd_send(&hdev->hw, desc, 2);
930ff2f6 1879 if (ret) {
46a3df9f
S		 1880 dev_err(&hdev->pdev->dev,
1881 "rx private waterline config cmd failed %d\n",
1882 ret);
930ff2f6 1883 return ret;
1884 }
1885 return 0;
46a3df9f
S		 1886}
1887
acf61ecd
YL		 1888static int hclge_common_thrd_config(struct hclge_dev *hdev,
1889 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1890{
acf61ecd 1891 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1892 struct hclge_rx_com_thrd *req;
1893 struct hclge_desc desc[2];
1894 struct hclge_tc_thrd *tc;
1895 int i, j;
1896 int ret;
1897
1898 for (i = 0; i < 2; i++) {
1899 hclge_cmd_setup_basic_desc(&desc[i],
1900 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1901 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1902
1903 /* The first descriptor set the NEXT bit to 1 */
1904 if (i == 0)
1905 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1906 else
1907 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1908
1909 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1910 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1911
1912 req->com_thrd[j].high =
1913 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1914 req->com_thrd[j].high |=
8cc87583 1915 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1916 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1917 req->com_thrd[j].low =
1918 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1919 req->com_thrd[j].low |=
8cc87583 1920 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1921 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1922 }
1923 }
1924
1925 /* Send 2 descriptors at one time */
1926 ret = hclge_cmd_send(&hdev->hw, desc, 2);
930ff2f6 1927 if (ret) {
46a3df9f
S		 1928 dev_err(&hdev->pdev->dev,
1929 "common threshold config cmd failed %d\n", ret);
930ff2f6 1930 return ret;
1931 }
1932 return 0;
46a3df9f
S		 1933}
1934
acf61ecd
YL		 1935static int hclge_common_wl_config(struct hclge_dev *hdev,
1936 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1937{
acf61ecd 1938 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1939 struct hclge_rx_com_wl *req;
1940 struct hclge_desc desc;
1941 int ret;
1942
1943 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1944
1945 req = (struct hclge_rx_com_wl *)desc.data;
1946 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
8cc87583 1947 req->com_wl.high |=
1948 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1949 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1950
1951 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
8cc87583 1952 req->com_wl.low |=
1953 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1954 HCLGE_RX_PRIV_EN_B);
46a3df9f
S		 1955
1956 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 1957 if (ret) {
46a3df9f
S		 1958 dev_err(&hdev->pdev->dev,
1959 "common waterline config cmd failed %d\n", ret);
930ff2f6 1960 return ret;
1961 }
1962
1963 return 0;
46a3df9f
S		 1964}
1965
1966int hclge_buffer_alloc(struct hclge_dev *hdev)
1967{
acf61ecd 1968 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1969 int ret;
1970
acf61ecd
YL		 1971 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1972 if (!pkt_buf)
46a3df9f
S		 1973 return -ENOMEM;
1974
acf61ecd 1975 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1976 if (ret) {
1977 dev_err(&hdev->pdev->dev,
1978 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1979 goto out;
9ffe79a9
YL		 1980 }
1981
acf61ecd 1982 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1983 if (ret) {
1984 dev_err(&hdev->pdev->dev,
1985 "could not alloc tx buffers %d\n", ret);
acf61ecd 1986 goto out;
46a3df9f
S		 1987 }
1988
acf61ecd 1989 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1990 if (ret) {
1991 dev_err(&hdev->pdev->dev,
1992 "could not calc rx priv buffer size for all TCs %d\n",
1993 ret);
acf61ecd 1994 goto out;
46a3df9f
S		 1995 }
1996
acf61ecd 1997 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1998 if (ret) {
1999 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
2000 ret);
acf61ecd 2001 goto out;
46a3df9f
S		 2002 }
2003
2daf4a65 2004 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 2005 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 2006 if (ret) {
2007 dev_err(&hdev->pdev->dev,
2008 "could not configure rx private waterline %d\n",
2009 ret);
acf61ecd 2010 goto out;
2daf4a65 2011 }
46a3df9f 2012
acf61ecd 2013 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 2014 if (ret) {
2015 dev_err(&hdev->pdev->dev,
2016 "could not configure common threshold %d\n",
2017 ret);
acf61ecd 2018 goto out;
2daf4a65 2019 }
46a3df9f
S		 2020 }
2021
acf61ecd
YL		 2022 ret = hclge_common_wl_config(hdev, pkt_buf);
2023 if (ret)
46a3df9f
S		 2024 dev_err(&hdev->pdev->dev,
2025 "could not configure common waterline %d\n", ret);
46a3df9f 2026
acf61ecd
YL		 2027out:
2028 kfree(pkt_buf);
2029 return ret;
46a3df9f
S		 2030}
2031
2032static int hclge_init_roce_base_info(struct hclge_vport *vport)
2033{
2034 struct hnae3_handle *roce = &vport->roce;
2035 struct hnae3_handle *nic = &vport->nic;
2036
887c3820 2037 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 2038
2039 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2040 vport->back->num_msi_left == 0)
2041 return -EINVAL;
2042
2043 roce->rinfo.base_vector = vport->back->roce_base_vector;
2044
2045 roce->rinfo.netdev = nic->kinfo.netdev;
2046 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2047
2048 roce->pdev = nic->pdev;
2049 roce->ae_algo = nic->ae_algo;
2050 roce->numa_node_mask = nic->numa_node_mask;
2051
2052 return 0;
2053}
2054
887c3820 2055static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 2056{
2057 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 2058 int vectors;
2059 int i;
46a3df9f 2060
887c3820
SM		 2061 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2062 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2063 if (vectors < 0) {
2064 dev_err(&pdev->dev,
2065 "failed(%d) to allocate MSI/MSI-X vectors\n",
2066 vectors);
2067 return vectors;
46a3df9f 2068 }
887c3820
SM		 2069 if (vectors < hdev->num_msi)
2070 dev_warn(&hdev->pdev->dev,
2071 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2072 hdev->num_msi, vectors);
46a3df9f 2073
887c3820
SM		 2074 hdev->num_msi = vectors;
2075 hdev->num_msi_left = vectors;
2076 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 2077 hdev->roce_base_vector = hdev->base_msi_vector +
2078 HCLGE_ROCE_VECTOR_OFFSET;
2079
46a3df9f
S		 2080 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2081 sizeof(u16), GFP_KERNEL);
887c3820
SM		 2082 if (!hdev->vector_status) {
2083 pci_free_irq_vectors(pdev);
46a3df9f 2084 return -ENOMEM;
887c3820 2085 }
46a3df9f
S		 2086
2087 for (i = 0; i < hdev->num_msi; i++)
2088 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2089
887c3820
SM		 2090 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2091 sizeof(int), GFP_KERNEL);
2092 if (!hdev->vector_irq) {
2093 pci_free_irq_vectors(pdev);
2094 return -ENOMEM;
46a3df9f 2095 }
46a3df9f
S		 2096
2097 return 0;
2098}
2099
2100static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2101{
2102 struct hclge_mac *mac = &hdev->hw.mac;
2103
2104 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2105 mac->duplex = (u8)duplex;
2106 else
2107 mac->duplex = HCLGE_MAC_FULL;
2108
2109 mac->speed = speed;
2110}
2111
2112int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2113{
d44f9b63 2114 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2115 struct hclge_desc desc;
2116 int ret;
2117
d44f9b63 2118 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2119
2120 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2121
e22b531b 2122 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 2123
2124 switch (speed) {
2125 case HCLGE_MAC_SPEED_10M:
e22b531b
HT		 2126 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2127 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 2128 break;
2129 case HCLGE_MAC_SPEED_100M:
e22b531b
HT		 2130 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2131 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 2132 break;
2133 case HCLGE_MAC_SPEED_1G:
e22b531b
HT		 2134 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2135 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 2136 break;
2137 case HCLGE_MAC_SPEED_10G:
e22b531b
HT		 2138 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2139 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 2140 break;
2141 case HCLGE_MAC_SPEED_25G:
e22b531b
HT		 2142 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2143 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 2144 break;
2145 case HCLGE_MAC_SPEED_40G:
e22b531b
HT		 2146 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2147 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 2148 break;
2149 case HCLGE_MAC_SPEED_50G:
e22b531b
HT		 2150 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2151 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 2152 break;
2153 case HCLGE_MAC_SPEED_100G:
e22b531b
HT		 2154 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2155 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 2156 break;
2157 default:
d7629e74 2158 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2159 return -EINVAL;
2160 }
2161
e22b531b
HT		 2162 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2163 1);
46a3df9f
S		 2164
2165 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2166 if (ret) {
2167 dev_err(&hdev->pdev->dev,
2168 "mac speed/duplex config cmd failed %d.\n", ret);
2169 return ret;
2170 }
2171
2172 hclge_check_speed_dup(hdev, duplex, speed);
2173
2174 return 0;
2175}
2176
2177static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2178 u8 duplex)
2179{
2180 struct hclge_vport *vport = hclge_get_vport(handle);
2181 struct hclge_dev *hdev = vport->back;
2182
2183 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2184}
2185
2186static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2187 u8 *duplex)
2188{
d44f9b63 2189 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2190 struct hclge_desc desc;
2191 int speed_tmp;
2192 int ret;
2193
d44f9b63 2194 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2195
2196 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2197 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2198 if (ret) {
2199 dev_err(&hdev->pdev->dev,
2200 "mac speed/autoneg/duplex query cmd failed %d\n",
2201 ret);
2202 return ret;
2203 }
2204
e22b531b
HT		 2205 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2206 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2207 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 2208
2209 ret = hclge_parse_speed(speed_tmp, speed);
930ff2f6 2210 if (ret) {
46a3df9f
S		 2211 dev_err(&hdev->pdev->dev,
2212 "could not parse speed(=%d), %d\n", speed_tmp, ret);
930ff2f6 2213 return -EIO;
2214 }
46a3df9f 2215
930ff2f6 2216 return 0;
46a3df9f
S		 2217}
2218
46a3df9f
S		 2219static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2220{
d44f9b63 2221 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2222 struct hclge_desc desc;
a90bb9a5 2223 u32 flag = 0;
46a3df9f
S		 2224 int ret;
2225
2226 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2227
d44f9b63 2228 req = (struct hclge_config_auto_neg_cmd *)desc.data;
e22b531b 2229 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 2230 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2231
2232 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 2233 if (ret) {
46a3df9f
S		 2234 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2235 ret);
930ff2f6 2236 return ret;
2237 }
46a3df9f 2238
930ff2f6 2239 return 0;
46a3df9f
S		 2240}
2241
2242static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2243{
2244 struct hclge_vport *vport = hclge_get_vport(handle);
2245 struct hclge_dev *hdev = vport->back;
2246
2247 return hclge_set_autoneg_en(hdev, enable);
2248}
2249
2250static int hclge_get_autoneg(struct hnae3_handle *handle)
2251{
2252 struct hclge_vport *vport = hclge_get_vport(handle);
2253 struct hclge_dev *hdev = vport->back;
9ff804ee
FL		 2254 struct phy_device *phydev = hdev->hw.mac.phydev;
2255
2256 if (phydev)
2257 return phydev->autoneg;
46a3df9f
S		 2258
2259 return hdev->hw.mac.autoneg;
2260}
2261
6f712727
PL		 2262static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2263 bool mask_vlan,
2264 u8 *mac_mask)
2265{
2266 struct hclge_mac_vlan_mask_entry_cmd *req;
2267 struct hclge_desc desc;
2268 int status;
2269
2270 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2271 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2272
e22b531b
HT		 2273 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2274 mask_vlan ? 1 : 0);
6f712727
PL		 2275 ether_addr_copy(req->mac_mask, mac_mask);
2276
2277 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2278 if (status)
2279 dev_err(&hdev->pdev->dev,
2280 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2281 status);
2282
2283 return status;
2284}
2285
46a3df9f
S		 2286static int hclge_mac_init(struct hclge_dev *hdev)
2287{
59bc85ec
FL		 2288 struct hnae3_handle *handle = &hdev->vport[0].nic;
2289 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 2290 struct hclge_mac *mac = &hdev->hw.mac;
6f712727 2291 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
a832d8b5 2292 struct hclge_vport *vport;
59bc85ec 2293 int mtu;
46a3df9f 2294 int ret;
a832d8b5 2295 int i;
46a3df9f
S		 2296
2297 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2298 if (ret) {
2299 dev_err(&hdev->pdev->dev,
2300 "Config mac speed dup fail ret=%d\n", ret);
2301 return ret;
2302 }
2303
2304 mac->link = 0;
2305
46a3df9f 2306 /* Initialize the MTA table work mode */
46a3df9f
S		 2307 hdev->enable_mta = true;
2308 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2309
2310 ret = hclge_set_mta_filter_mode(hdev,
2311 hdev->mta_mac_sel_type,
2312 hdev->enable_mta);
2313 if (ret) {
2314 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2315 ret);
2316 return ret;
2317 }
2318
a832d8b5
XW		 2319 for (i = 0; i < hdev->num_alloc_vport; i++) {
2320 vport = &hdev->vport[i];
2321 vport->accept_mta_mc = false;
2322
2323 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2324 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2325 if (ret) {
2326 dev_err(&hdev->pdev->dev,
2327 "set mta filter mode fail ret=%d\n", ret);
2328 return ret;
2329 }
6f712727
PL		 2330 }
2331
2332 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
59bc85ec 2333 if (ret) {
6f712727
PL		 2334 dev_err(&hdev->pdev->dev,
2335 "set default mac_vlan_mask fail ret=%d\n", ret);
59bc85ec
FL		 2336 return ret;
2337 }
6f712727 2338
59bc85ec
FL		 2339 if (netdev)
2340 mtu = netdev->mtu;
2341 else
2342 mtu = ETH_DATA_LEN;
2343
2344 ret = hclge_set_mtu(handle, mtu);
930ff2f6 2345 if (ret) {
59bc85ec
FL		 2346 dev_err(&hdev->pdev->dev,
2347 "set mtu failed ret=%d\n", ret);
930ff2f6 2348 return ret;
2349 }
59bc85ec 2350
930ff2f6 2351 return 0;
46a3df9f
S		 2352}
2353
22fd3468
SM		 2354static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2355{
2356 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2357 schedule_work(&hdev->mbx_service_task);
2358}
2359
ed4a1bb8
SM		 2360static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2361{
2362 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2363 schedule_work(&hdev->rst_service_task);
2364}
2365
46a3df9f
S		 2366static void hclge_task_schedule(struct hclge_dev *hdev)
2367{
2368 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2369 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2370 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2371 (void)schedule_work(&hdev->service_task);
2372}
2373
2374static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2375{
d44f9b63 2376 struct hclge_link_status_cmd *req;
46a3df9f
S		 2377 struct hclge_desc desc;
2378 int link_status;
2379 int ret;
2380
2381 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2382 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2383 if (ret) {
2384 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2385 ret);
2386 return ret;
2387 }
2388
d44f9b63 2389 req = (struct hclge_link_status_cmd *)desc.data;
717523d0 2390 link_status = req->status & HCLGE_LINK_STATUS;
46a3df9f
S		 2391
2392 return !!link_status;
2393}
2394
2395static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2396{
2397 int mac_state;
2398 int link_stat;
2399
2400 mac_state = hclge_get_mac_link_status(hdev);
2401
2402 if (hdev->hw.mac.phydev) {
2403 if (!genphy_read_status(hdev->hw.mac.phydev))
2404 link_stat = mac_state &
2405 hdev->hw.mac.phydev->link;
2406 else
2407 link_stat = 0;
2408
2409 } else {
2410 link_stat = mac_state;
2411 }
2412
2413 return !!link_stat;
2414}
2415
2416static void hclge_update_link_status(struct hclge_dev *hdev)
2417{
15a50665 2418 struct hnae3_client *rclient = hdev->roce_client;
46a3df9f 2419 struct hnae3_client *client = hdev->nic_client;
bc0b7416 2420 struct hnae3_handle *rhandle;
46a3df9f
S		 2421 struct hnae3_handle *handle;
2422 int state;
2423 int i;
2424
2425 if (!client)
2426 return;
2427 state = hclge_get_mac_phy_link(hdev);
2428 if (state != hdev->hw.mac.link) {
2429 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2430 handle = &hdev->vport[i].nic;
2431 client->ops->link_status_change(handle, state);
bc0b7416 2432 rhandle = &hdev->vport[i].roce;
15a50665 2433 if (rclient && rclient->ops->link_status_change)
bc0b7416
WHX		 2434 rclient->ops->link_status_change(rhandle,
2435 state);
46a3df9f
S		 2436 }
2437 hdev->hw.mac.link = state;
2438 }
2439}
2440
2441static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2442{
2443 struct hclge_mac mac = hdev->hw.mac;
2444 u8 duplex;
2445 int speed;
2446 int ret;
2447
2448 /* get the speed and duplex as autoneg'result from mac cmd when phy
2449 * doesn't exit.
2450 */
c040366b 2451 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2452 return 0;
2453
2454 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2455 if (ret) {
2456 dev_err(&hdev->pdev->dev,
2457 "mac autoneg/speed/duplex query failed %d\n", ret);
2458 return ret;
2459 }
2460
2461 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2462 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2463 if (ret) {
2464 dev_err(&hdev->pdev->dev,
2465 "mac speed/duplex config failed %d\n", ret);
2466 return ret;
2467 }
2468 }
2469
2470 return 0;
2471}
2472
2473static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2474{
2475 struct hclge_vport *vport = hclge_get_vport(handle);
2476 struct hclge_dev *hdev = vport->back;
2477
2478 return hclge_update_speed_duplex(hdev);
2479}
2480
2481static int hclge_get_status(struct hnae3_handle *handle)
2482{
2483 struct hclge_vport *vport = hclge_get_vport(handle);
2484 struct hclge_dev *hdev = vport->back;
2485
2486 hclge_update_link_status(hdev);
2487
2488 return hdev->hw.mac.link;
2489}
2490
d039ef68 2491static void hclge_service_timer(struct timer_list *t)
46a3df9f 2492{
d039ef68 2493 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2494
d039ef68 2495 mod_timer(&hdev->service_timer, jiffies + HZ);
7a5d2a39 2496 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2497 hclge_task_schedule(hdev);
2498}
2499
2500static void hclge_service_complete(struct hclge_dev *hdev)
2501{
2502 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2503
2504 /* Flush memory before next watchdog */
2505 smp_mb__before_atomic();
2506 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2507}
2508
202f2014
SM		 2509static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2510{
2511 u32 rst_src_reg;
22fd3468 2512 u32 cmdq_src_reg;
202f2014
SM		 2513
2514 /* fetch the events from their corresponding regs */
82bd1bef 2515 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
22fd3468
SM		 2516 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2517
2518 /* Assumption: If by any chance reset and mailbox events are reported
2519 * together then we will only process reset event in this go and will
2520 * defer the processing of the mailbox events. Since, we would have not
2521 * cleared RX CMDQ event this time we would receive again another
2522 * interrupt from H/W just for the mailbox.
2523 */
202f2014
SM		 2524
2525 /* check for vector0 reset event sources */
2526 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2527 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2528 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2529 return HCLGE_VECTOR0_EVENT_RST;
2530 }
2531
2532 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2533 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2534 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2535 return HCLGE_VECTOR0_EVENT_RST;
2536 }
2537
2538 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2539 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2540 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2541 return HCLGE_VECTOR0_EVENT_RST;
2542 }
2543
22fd3468
SM		 2544 /* check for vector0 mailbox(=CMDQ RX) event source */
2545 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2546 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2547 *clearval = cmdq_src_reg;
2548 return HCLGE_VECTOR0_EVENT_MBX;
2549 }
202f2014
SM		 2550
2551 return HCLGE_VECTOR0_EVENT_OTHER;
2552}
2553
2554static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2555 u32 regclr)
2556{
22fd3468
SM		 2557 switch (event_type) {
2558 case HCLGE_VECTOR0_EVENT_RST:
202f2014 2559 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
22fd3468
SM		 2560 break;
2561 case HCLGE_VECTOR0_EVENT_MBX:
2562 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2563 break;
2564 }
202f2014
SM		 2565}
2566
466b0c00
L		 2567static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2568{
2569 writel(enable ? 1 : 0, vector->addr);
2570}
2571
2572static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2573{
2574 struct hclge_dev *hdev = data;
202f2014
SM		 2575 u32 event_cause;
2576 u32 clearval;
466b0c00
L		 2577
2578 hclge_enable_vector(&hdev->misc_vector, false);
202f2014
SM		 2579 event_cause = hclge_check_event_cause(hdev, &clearval);
2580
22fd3468 2581 /* vector 0 interrupt is shared with reset and mailbox source events.*/
202f2014
SM		 2582 switch (event_cause) {
2583 case HCLGE_VECTOR0_EVENT_RST:
ed4a1bb8 2584 hclge_reset_task_schedule(hdev);
202f2014 2585 break;
22fd3468
SM		 2586 case HCLGE_VECTOR0_EVENT_MBX:
2587 /* If we are here then,
2588 * 1. Either we are not handling any mbx task and we are not
2589 * scheduled as well
2590 * OR
2591 * 2. We could be handling a mbx task but nothing more is
2592 * scheduled.
2593 * In both cases, we should schedule mbx task as there are more
2594 * mbx messages reported by this interrupt.
2595 */
2596 hclge_mbx_task_schedule(hdev);
40ee4b71 2597 break;
202f2014 2598 default:
40ee4b71
YL		 2599 dev_warn(&hdev->pdev->dev,
2600 "received unknown or unhandled event of vector0\n");
202f2014
SM		 2601 break;
2602 }
2603
e9a50d09
YL		 2604 /* clear the source of interrupt if it is not cause by reset */
2605 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2606 hclge_clear_event_cause(hdev, event_cause, clearval);
2607 hclge_enable_vector(&hdev->misc_vector, true);
2608 }
466b0c00
L		 2609
2610 return IRQ_HANDLED;
2611}
2612
2613static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2614{
617cb5a2
PL		 2615 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2616 dev_warn(&hdev->pdev->dev,
2617 "vector(vector_id %d) has been freed.\n", vector_id);
2618 return;
2619 }
2620
466b0c00
L		 2621 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2622 hdev->num_msi_left += 1;
2623 hdev->num_msi_used -= 1;
2624}
2625
2626static void hclge_get_misc_vector(struct hclge_dev *hdev)
2627{
2628 struct hclge_misc_vector *vector = &hdev->misc_vector;
2629
2630 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2631
2632 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2633 hdev->vector_status[0] = 0;
2634
2635 hdev->num_msi_left -= 1;
2636 hdev->num_msi_used += 1;
2637}
2638
2639static int hclge_misc_irq_init(struct hclge_dev *hdev)
2640{
2641 int ret;
2642
2643 hclge_get_misc_vector(hdev);
2644
202f2014
SM		 2645 /* this would be explicitly freed in the end */
2646 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2647 0, "hclge_misc", hdev);
466b0c00
L		 2648 if (ret) {
2649 hclge_free_vector(hdev, 0);
2650 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2651 hdev->misc_vector.vector_irq);
2652 }
2653
2654 return ret;
2655}
2656
202f2014
SM		 2657static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2658{
2659 free_irq(hdev->misc_vector.vector_irq, hdev);
2660 hclge_free_vector(hdev, 0);
2661}
2662
4ed340ab
L		 2663static int hclge_notify_client(struct hclge_dev *hdev,
2664 enum hnae3_reset_notify_type type)
2665{
3628abd0 2666 struct hnae3_client *rclient = hdev->roce_client;
4ed340ab 2667 struct hnae3_client *client = hdev->nic_client;
d3f5c892
LO		 2668 struct hnae3_handle *handle;
2669 int ret;
4ed340ab
L		 2670 u16 i;
2671
2672 if (!client->ops->reset_notify)
2673 return -EOPNOTSUPP;
2674
2675 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
d3f5c892 2676 handle = &hdev->vport[i].nic;
4ed340ab 2677 ret = client->ops->reset_notify(handle, type);
2e5ed0d2
WHX		 2678 if (ret) {
2679 dev_err(&hdev->pdev->dev,
2680 "notify nic client failed %d", ret);
4ed340ab 2681 return ret;
2e5ed0d2 2682 }
0520c2e5 2683
3628abd0 2684 if (rclient && rclient->ops->reset_notify) {
2685 handle = &hdev->vport[i].roce;
2686 ret = rclient->ops->reset_notify(handle, type);
2687 if (ret) {
2688 dev_err(&hdev->pdev->dev,
2689 "notify roce client failed %d", ret);
2690 return ret;
2691 }
d3f5c892 2692 }
4ed340ab
L		 2693 }
2694
3628abd0 2695 return 0;
4ed340ab
L		 2696}
2697
2698static int hclge_reset_wait(struct hclge_dev *hdev)
2699{
2700#define HCLGE_RESET_WATI_MS 100
2701#define HCLGE_RESET_WAIT_CNT 5
2702 u32 val, reg, reg_bit;
2703 u32 cnt = 0;
2704
2705 switch (hdev->reset_type) {
2706 case HNAE3_GLOBAL_RESET:
2707 reg = HCLGE_GLOBAL_RESET_REG;
2708 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2709 break;
2710 case HNAE3_CORE_RESET:
2711 reg = HCLGE_GLOBAL_RESET_REG;
2712 reg_bit = HCLGE_CORE_RESET_BIT;
2713 break;
2714 case HNAE3_FUNC_RESET:
2715 reg = HCLGE_FUN_RST_ING;
2716 reg_bit = HCLGE_FUN_RST_ING_B;
2717 break;
2718 default:
2719 dev_err(&hdev->pdev->dev,
2720 "Wait for unsupported reset type: %d\n",
2721 hdev->reset_type);
2722 return -EINVAL;
2723 }
2724
2725 val = hclge_read_dev(&hdev->hw, reg);
e22b531b
HT		 2726 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT &&
2727 test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
4ed340ab
L		 2728 msleep(HCLGE_RESET_WATI_MS);
2729 val = hclge_read_dev(&hdev->hw, reg);
2730 cnt++;
2731 }
2732
4ed340ab
L		 2733 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2734 dev_warn(&hdev->pdev->dev,
2735 "Wait for reset timeout: %d\n", hdev->reset_type);
2736 return -EBUSY;
2737 }
2738
2739 return 0;
2740}
2741
13a86fae 2742int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2743{
2744 struct hclge_desc desc;
2745 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2746 int ret;
2747
2748 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
e22b531b 2749 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2750 req->fun_reset_vfid = func_id;
2751
2752 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2753 if (ret)
2754 dev_err(&hdev->pdev->dev,
2755 "send function reset cmd fail, status =%d\n", ret);
2756
2757 return ret;
2758}
2759
d5752031 2760static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2761{
2762 struct pci_dev *pdev = hdev->pdev;
2763 u32 val;
2764
d5752031 2765 switch (hdev->reset_type) {
4ed340ab
L		 2766 case HNAE3_GLOBAL_RESET:
2767 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e22b531b 2768 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2769 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2770 dev_info(&pdev->dev, "Global Reset requested\n");
2771 break;
2772 case HNAE3_CORE_RESET:
2773 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e22b531b 2774 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2775 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2776 dev_info(&pdev->dev, "Core Reset requested\n");
2777 break;
2778 case HNAE3_FUNC_RESET:
2779 dev_info(&pdev->dev, "PF Reset requested\n");
2780 hclge_func_reset_cmd(hdev, 0);
ed4a1bb8
SM		 2781 /* schedule again to check later */
2782 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2783 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2784 break;
2785 default:
2786 dev_warn(&pdev->dev,
d5752031 2787 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2788 break;
2789 }
2790}
2791
d5752031
SM		 2792static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2793 unsigned long *addr)
2794{
2795 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2796
2797 /* return the highest priority reset level amongst all */
2798 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2799 rst_level = HNAE3_GLOBAL_RESET;
2800 else if (test_bit(HNAE3_CORE_RESET, addr))
2801 rst_level = HNAE3_CORE_RESET;
2802 else if (test_bit(HNAE3_IMP_RESET, addr))
2803 rst_level = HNAE3_IMP_RESET;
2804 else if (test_bit(HNAE3_FUNC_RESET, addr))
2805 rst_level = HNAE3_FUNC_RESET;
2806
2807 /* now, clear all other resets */
2808 clear_bit(HNAE3_GLOBAL_RESET, addr);
2809 clear_bit(HNAE3_CORE_RESET, addr);
2810 clear_bit(HNAE3_IMP_RESET, addr);
2811 clear_bit(HNAE3_FUNC_RESET, addr);
2812
2813 return rst_level;
2814}
2815
e9a50d09
YL		 2816static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2817{
2818 u32 clearval = 0;
2819
2820 switch (hdev->reset_type) {
2821 case HNAE3_IMP_RESET:
2822 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2823 break;
2824 case HNAE3_GLOBAL_RESET:
2825 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2826 break;
2827 case HNAE3_CORE_RESET:
2828 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2829 break;
2830 default:
abcbcae3 2831 dev_warn(&hdev->pdev->dev, "Unsupported reset event to clear:%d",
2832 hdev->reset_type);
e9a50d09
YL		 2833 break;
2834 }
2835
2836 if (!clearval)
2837 return;
2838
2839 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2840 hclge_enable_vector(&hdev->misc_vector, true);
2841}
2842
d5752031
SM		 2843static void hclge_reset(struct hclge_dev *hdev)
2844{
2845 /* perform reset of the stack & ae device for a client */
c07b029f 2846
d5752031
SM		 2847 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2848
2849 if (!hclge_reset_wait(hdev)) {
c07b029f 2850 rtnl_lock();
d5752031
SM		 2851 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2852 hclge_reset_ae_dev(hdev->ae_dev);
2853 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
c07b029f 2854 rtnl_unlock();
e9a50d09
YL		 2855
2856 hclge_clear_reset_cause(hdev);
d5752031
SM		 2857 } else {
2858 /* schedule again to check pending resets later */
2859 set_bit(hdev->reset_type, &hdev->reset_pending);
2860 hclge_reset_task_schedule(hdev);
2861 }
2862
2863 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2864}
2865
4aef908d 2866static void hclge_reset_event(struct hnae3_handle *handle)
4ed340ab
L		 2867{
2868 struct hclge_vport *vport = hclge_get_vport(handle);
2869 struct hclge_dev *hdev = vport->back;
2870
4aef908d
SM		 2871 /* check if this is a new reset request and we are not here just because
2872 * last reset attempt did not succeed and watchdog hit us again. We will
2873 * know this if last reset request did not occur very recently (watchdog
2874 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2875 * In case of new request we reset the "reset level" to PF reset.
2876 */
0324e7bd 2877 if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
4aef908d 2878 handle->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2879
4aef908d
SM		 2880 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2881 handle->reset_level);
2882
2883 /* request reset & schedule reset task */
2884 set_bit(handle->reset_level, &hdev->reset_request);
2885 hclge_reset_task_schedule(hdev);
2886
2887 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2888 handle->reset_level++;
0324e7bd 2889
2890 handle->last_reset_time = jiffies;
4ed340ab
L		 2891}
2892
2893static void hclge_reset_subtask(struct hclge_dev *hdev)
2894{
d5752031
SM		 2895 /* check if there is any ongoing reset in the hardware. This status can
2896 * be checked from reset_pending. If there is then, we need to wait for
2897 * hardware to complete reset.
2898 * a. If we are able to figure out in reasonable time that hardware
2899 * has fully resetted then, we can proceed with driver, client
2900 * reset.
2901 * b. else, we can come back later to check this status so re-sched
2902 * now.
2903 */
2904 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2905 if (hdev->reset_type != HNAE3_NONE_RESET)
2906 hclge_reset(hdev);
4ed340ab 2907
d5752031
SM		 2908 /* check if we got any *new* reset requests to be honored */
2909 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2910 if (hdev->reset_type != HNAE3_NONE_RESET)
2911 hclge_do_reset(hdev);
4ed340ab 2912
4ed340ab
L		 2913 hdev->reset_type = HNAE3_NONE_RESET;
2914}
2915
ed4a1bb8 2916static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2917{
ed4a1bb8
SM		 2918 struct hclge_dev *hdev =
2919 container_of(work, struct hclge_dev, rst_service_task);
2920
2921 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2922 return;
2923
2924 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2925
4ed340ab 2926 hclge_reset_subtask(hdev);
ed4a1bb8
SM		 2927
2928 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2929}
2930
22fd3468
SM		 2931static void hclge_mailbox_service_task(struct work_struct *work)
2932{
2933 struct hclge_dev *hdev =
2934 container_of(work, struct hclge_dev, mbx_service_task);
2935
2936 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2937 return;
2938
2939 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2940
2941 hclge_mbx_handler(hdev);
2942
2943 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2944}
2945
46a3df9f
S		 2946static void hclge_service_task(struct work_struct *work)
2947{
2948 struct hclge_dev *hdev =
2949 container_of(work, struct hclge_dev, service_task);
2950
7a5d2a39
JS		 2951 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2952 hclge_update_stats_for_all(hdev);
2953 hdev->hw_stats.stats_timer = 0;
2954 }
2955
46a3df9f
S		 2956 hclge_update_speed_duplex(hdev);
2957 hclge_update_link_status(hdev);
46a3df9f
S		 2958 hclge_service_complete(hdev);
2959}
2960
46a3df9f
S		 2961struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2962{
2963 /* VF handle has no client */
2964 if (!handle->client)
2965 return container_of(handle, struct hclge_vport, nic);
2966 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2967 return container_of(handle, struct hclge_vport, roce);
2968 else
2969 return container_of(handle, struct hclge_vport, nic);
2970}
2971
2972static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2973 struct hnae3_vector_info *vector_info)
2974{
2975 struct hclge_vport *vport = hclge_get_vport(handle);
2976 struct hnae3_vector_info *vector = vector_info;
2977 struct hclge_dev *hdev = vport->back;
2978 int alloc = 0;
2979 int i, j;
2980
2981 vector_num = min(hdev->num_msi_left, vector_num);
2982
2983 for (j = 0; j < vector_num; j++) {
2984 for (i = 1; i < hdev->num_msi; i++) {
2985 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2986 vector->vector = pci_irq_vector(hdev->pdev, i);
2987 vector->io_addr = hdev->hw.io_base +
2988 HCLGE_VECTOR_REG_BASE +
2989 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2990 vport->vport_id *
2991 HCLGE_VECTOR_VF_OFFSET;
2992 hdev->vector_status[i] = vport->vport_id;
887c3820 2993 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2994
2995 vector++;
2996 alloc++;
2997
2998 break;
2999 }
3000 }
3001 }
3002 hdev->num_msi_left -= alloc;
3003 hdev->num_msi_used += alloc;
3004
3005 return alloc;
3006}
3007
3008static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
3009{
3010 int i;
3011
887c3820
SM		 3012 for (i = 0; i < hdev->num_msi; i++)
3013 if (vector == hdev->vector_irq[i])
3014 return i;
3015
46a3df9f
S		 3016 return -EINVAL;
3017}
3018
7412200c
YL		 3019static int hclge_put_vector(struct hnae3_handle *handle, int vector)
3020{
3021 struct hclge_vport *vport = hclge_get_vport(handle);
3022 struct hclge_dev *hdev = vport->back;
3023 int vector_id;
3024
3025 vector_id = hclge_get_vector_index(hdev, vector);
3026 if (vector_id < 0) {
3027 dev_err(&hdev->pdev->dev,
3028 "Get vector index fail. vector_id =%d\n", vector_id);
3029 return vector_id;
3030 }
3031
3032 hclge_free_vector(hdev, vector_id);
3033
3034 return 0;
3035}
3036
46a3df9f
S		 3037static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
3038{
3039 return HCLGE_RSS_KEY_SIZE;
3040}
3041
3042static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3043{
3044 return HCLGE_RSS_IND_TBL_SIZE;
3045}
3046
46a3df9f
S		 3047static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3048 const u8 hfunc, const u8 *key)
3049{
d44f9b63 3050 struct hclge_rss_config_cmd *req;
46a3df9f
S		 3051 struct hclge_desc desc;
3052 int key_offset;
3053 int key_size;
3054 int ret;
3055
d44f9b63 3056 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 3057
3058 for (key_offset = 0; key_offset < 3; key_offset++) {
3059 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3060 false);
3061
3062 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3063 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3064
3065 if (key_offset == 2)
3066 key_size =
3067 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3068 else
3069 key_size = HCLGE_RSS_HASH_KEY_NUM;
3070
3071 memcpy(req->hash_key,
3072 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3073
3074 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3075 if (ret) {
3076 dev_err(&hdev->pdev->dev,
3077 "Configure RSS config fail, status = %d\n",
3078 ret);
3079 return ret;
3080 }
3081 }
3082 return 0;
3083}
3084
dcd4ef5e 3085static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3086{
d44f9b63 3087 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3088 struct hclge_desc desc;
3089 int i, j;
3090 int ret;
3091
d44f9b63 3092 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3093
3094 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3095 hclge_cmd_setup_basic_desc
3096 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3097
a90bb9a5
YL		 3098 req->start_table_index =
3099 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3100 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3101
3102 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3103 req->rss_result[j] =
3104 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3105
3106 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3107 if (ret) {
3108 dev_err(&hdev->pdev->dev,
3109 "Configure rss indir table fail,status = %d\n",
3110 ret);
3111 return ret;
3112 }
3113 }
3114 return 0;
3115}
3116
3117static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3118 u16 *tc_size, u16 *tc_offset)
3119{
d44f9b63 3120 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3121 struct hclge_desc desc;
3122 int ret;
3123 int i;
3124
3125 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3126 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3127
3128 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3129 u16 mode = 0;
3130
e22b531b
HT		 3131 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3132 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3133 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3134 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3135 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3136
3137 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3138 }
3139
3140 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 3141 if (ret) {
46a3df9f
S		 3142 dev_err(&hdev->pdev->dev,
3143 "Configure rss tc mode fail, status = %d\n", ret);
930ff2f6 3144 return ret;
3145 }
46a3df9f 3146
930ff2f6 3147 return 0;
46a3df9f
S		 3148}
3149
3150static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3151{
d44f9b63 3152 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3153 struct hclge_desc desc;
3154 int ret;
3155
3156 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3157
d44f9b63 3158 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef
YL		 3159
3160 /* Get the tuple cfg from pf */
3161 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3162 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3163 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3164 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3165 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3166 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3167 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3168 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
46a3df9f 3169 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 3170 if (ret) {
46a3df9f
S		 3171 dev_err(&hdev->pdev->dev,
3172 "Configure rss input fail, status = %d\n", ret);
930ff2f6 3173 return ret;
3174 }
3175
3176 return 0;
46a3df9f
S		 3177}
3178
3179static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3180 u8 *key, u8 *hfunc)
3181{
3182 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3183 int i;
3184
3185 /* Get hash algorithm */
3186 if (hfunc)
dcd4ef5e 3187 *hfunc = vport->rss_algo;
46a3df9f
S		 3188
3189 /* Get the RSS Key required by the user */
3190 if (key)
3191 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3192
3193 /* Get indirect table */
3194 if (indir)
3195 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3196 indir[i] = vport->rss_indirection_tbl[i];
3197
3198 return 0;
3199}
3200
3201static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3202 const u8 *key, const u8 hfunc)
3203{
3204 struct hclge_vport *vport = hclge_get_vport(handle);
3205 struct hclge_dev *hdev = vport->back;
3206 u8 hash_algo;
3207 int ret, i;
3208
3209 /* Set the RSS Hash Key if specififed by the user */
3210 if (key) {
46a3df9f
S		 3211
3212 if (hfunc == ETH_RSS_HASH_TOP ||
3213 hfunc == ETH_RSS_HASH_NO_CHANGE)
3214 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3215 else
3216 return -EINVAL;
3217 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3218 if (ret)
3219 return ret;
dcd4ef5e
YL		 3220
3221 /* Update the shadow RSS key with user specified qids */
3222 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3223 vport->rss_algo = hash_algo;
46a3df9f
S		 3224 }
3225
3226 /* Update the shadow RSS table with user specified qids */
3227 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3228 vport->rss_indirection_tbl[i] = indir[i];
3229
3230 /* Update the hardware */
dcd4ef5e 3231 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3232}
3233
f7db940a
L		 3234static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3235{
3236 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3237
3238 if (nfc->data & RXH_L4_B_2_3)
3239 hash_sets |= HCLGE_D_PORT_BIT;
3240 else
3241 hash_sets &= ~HCLGE_D_PORT_BIT;
3242
3243 if (nfc->data & RXH_IP_SRC)
3244 hash_sets |= HCLGE_S_IP_BIT;
3245 else
3246 hash_sets &= ~HCLGE_S_IP_BIT;
3247
3248 if (nfc->data & RXH_IP_DST)
3249 hash_sets |= HCLGE_D_IP_BIT;
3250 else
3251 hash_sets &= ~HCLGE_D_IP_BIT;
3252
3253 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3254 hash_sets |= HCLGE_V_TAG_BIT;
3255
3256 return hash_sets;
3257}
3258
3259static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3260 struct ethtool_rxnfc *nfc)
3261{
3262 struct hclge_vport *vport = hclge_get_vport(handle);
3263 struct hclge_dev *hdev = vport->back;
3264 struct hclge_rss_input_tuple_cmd *req;
3265 struct hclge_desc desc;
3266 u8 tuple_sets;
3267 int ret;
3268
3269 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3270 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3271 return -EINVAL;
3272
3273 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef 3274 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 3275
637053ef
YL		 3276 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3277 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3278 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3279 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3280 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3281 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3282 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3283 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 3284
3285 tuple_sets = hclge_get_rss_hash_bits(nfc);
3286 switch (nfc->flow_type) {
3287 case TCP_V4_FLOW:
3288 req->ipv4_tcp_en = tuple_sets;
3289 break;
3290 case TCP_V6_FLOW:
3291 req->ipv6_tcp_en = tuple_sets;
3292 break;
3293 case UDP_V4_FLOW:
3294 req->ipv4_udp_en = tuple_sets;
3295 break;
3296 case UDP_V6_FLOW:
3297 req->ipv6_udp_en = tuple_sets;
3298 break;
3299 case SCTP_V4_FLOW:
3300 req->ipv4_sctp_en = tuple_sets;
3301 break;
3302 case SCTP_V6_FLOW:
3303 if ((nfc->data & RXH_L4_B_0_1) ||
3304 (nfc->data & RXH_L4_B_2_3))
3305 return -EINVAL;
3306
3307 req->ipv6_sctp_en = tuple_sets;
3308 break;
3309 case IPV4_FLOW:
3310 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3311 break;
3312 case IPV6_FLOW:
3313 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3314 break;
3315 default:
3316 return -EINVAL;
3317 }
3318
3319 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
637053ef 3320 if (ret) {
f7db940a
L		 3321 dev_err(&hdev->pdev->dev,
3322 "Set rss tuple fail, status = %d\n", ret);
637053ef
YL		 3323 return ret;
3324 }
f7db940a 3325
637053ef
YL		 3326 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3327 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3328 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3329 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3330 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3331 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3332 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3333 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3334 return 0;
f7db940a
L		 3335}
3336
07d29954
L		 3337static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3338 struct ethtool_rxnfc *nfc)
3339{
3340 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3341 u8 tuple_sets;
07d29954
L		 3342
3343 nfc->data = 0;
3344
07d29954
L		 3345 switch (nfc->flow_type) {
3346 case TCP_V4_FLOW:
637053ef 3347 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3348 break;
3349 case UDP_V4_FLOW:
637053ef 3350 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3351 break;
3352 case TCP_V6_FLOW:
637053ef 3353 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3354 break;
3355 case UDP_V6_FLOW:
637053ef 3356 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3357 break;
3358 case SCTP_V4_FLOW:
637053ef 3359 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3360 break;
3361 case SCTP_V6_FLOW:
637053ef 3362 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3363 break;
3364 case IPV4_FLOW:
3365 case IPV6_FLOW:
3366 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3367 break;
3368 default:
3369 return -EINVAL;
3370 }
3371
3372 if (!tuple_sets)
3373 return 0;
3374
3375 if (tuple_sets & HCLGE_D_PORT_BIT)
3376 nfc->data |= RXH_L4_B_2_3;
3377 if (tuple_sets & HCLGE_S_PORT_BIT)
3378 nfc->data |= RXH_L4_B_0_1;
3379 if (tuple_sets & HCLGE_D_IP_BIT)
3380 nfc->data |= RXH_IP_DST;
3381 if (tuple_sets & HCLGE_S_IP_BIT)
3382 nfc->data |= RXH_IP_SRC;
3383
3384 return 0;
3385}
3386
46a3df9f
S		 3387static int hclge_get_tc_size(struct hnae3_handle *handle)
3388{
3389 struct hclge_vport *vport = hclge_get_vport(handle);
3390 struct hclge_dev *hdev = vport->back;
3391
3392 return hdev->rss_size_max;
3393}
3394
77f255c1 3395int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3396{
46a3df9f 3397 struct hclge_vport *vport = hdev->vport;
8015bb74
YL		 3398 u8 *rss_indir = vport[0].rss_indirection_tbl;
3399 u16 rss_size = vport[0].alloc_rss_size;
3400 u8 *key = vport[0].rss_hash_key;
3401 u8 hfunc = vport[0].rss_algo;
46a3df9f 3402 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3403 u16 tc_valid[HCLGE_MAX_TC_NUM];
3404 u16 tc_size[HCLGE_MAX_TC_NUM];
8015bb74
YL		 3405 u16 roundup_size;
3406 int i, ret;
68ece54e 3407
46a3df9f
S		 3408 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3409 if (ret)
8015bb74 3410 return ret;
46a3df9f 3411
46a3df9f
S		 3412 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3413 if (ret)
8015bb74 3414 return ret;
46a3df9f
S		 3415
3416 ret = hclge_set_rss_input_tuple(hdev);
3417 if (ret)
8015bb74 3418 return ret;
46a3df9f 3419
68ece54e
YL		 3420 /* Each TC have the same queue size, and tc_size set to hardware is
3421 * the log2 of roundup power of two of rss_size, the acutal queue
3422 * size is limited by indirection table.
3423 */
3424 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3425 dev_err(&hdev->pdev->dev,
3426 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3427 rss_size);
8015bb74 3428 return -EINVAL;
68ece54e
YL		 3429 }
3430
3431 roundup_size = roundup_pow_of_two(rss_size);
3432 roundup_size = ilog2(roundup_size);
3433
46a3df9f 3434 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3435 tc_valid[i] = 0;
46a3df9f 3436
68ece54e
YL		 3437 if (!(hdev->hw_tc_map & BIT(i)))
3438 continue;
3439
3440 tc_valid[i] = 1;
3441 tc_size[i] = roundup_size;
3442 tc_offset[i] = rss_size * i;
46a3df9f 3443 }
68ece54e 3444
8015bb74
YL		 3445 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3446}
46a3df9f 3447
8015bb74
YL		 3448void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3449{
3450 struct hclge_vport *vport = hdev->vport;
3451 int i, j;
46a3df9f 3452
8015bb74
YL		 3453 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3454 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3455 vport[j].rss_indirection_tbl[i] =
3456 i % vport[j].alloc_rss_size;
3457 }
3458}
3459
3460static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3461{
3462 struct hclge_vport *vport = hdev->vport;
3463 int i;
3464
8015bb74
YL		 3465 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3466 vport[i].rss_tuple_sets.ipv4_tcp_en =
3467 HCLGE_RSS_INPUT_TUPLE_OTHER;
3468 vport[i].rss_tuple_sets.ipv4_udp_en =
3469 HCLGE_RSS_INPUT_TUPLE_OTHER;
3470 vport[i].rss_tuple_sets.ipv4_sctp_en =
3471 HCLGE_RSS_INPUT_TUPLE_SCTP;
3472 vport[i].rss_tuple_sets.ipv4_fragment_en =
3473 HCLGE_RSS_INPUT_TUPLE_OTHER;
3474 vport[i].rss_tuple_sets.ipv6_tcp_en =
3475 HCLGE_RSS_INPUT_TUPLE_OTHER;
3476 vport[i].rss_tuple_sets.ipv6_udp_en =
3477 HCLGE_RSS_INPUT_TUPLE_OTHER;
3478 vport[i].rss_tuple_sets.ipv6_sctp_en =
3479 HCLGE_RSS_INPUT_TUPLE_SCTP;
3480 vport[i].rss_tuple_sets.ipv6_fragment_en =
3481 HCLGE_RSS_INPUT_TUPLE_OTHER;
3482
3483 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
823fe868
FL		 3484
3485 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
8015bb74
YL		 3486 }
3487
3488 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3489}
3490
63d7e66f
SM		 3491int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3492 int vector_id, bool en,
3493 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3494{
3495 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3496 struct hnae3_ring_chain_node *node;
3497 struct hclge_desc desc;
63d7e66f
SM		 3498 struct hclge_ctrl_vector_chain_cmd *req
3499 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3500 enum hclge_cmd_status status;
3501 enum hclge_opcode_type op;
3502 u16 tqp_type_and_id;
46a3df9f
S		 3503 int i;
3504
63d7e66f
SM		 3505 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3506 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3507 req->int_vector_id = vector_id;
3508
3509 i = 0;
3510 for (node = ring_chain; node; node = node->next) {
63d7e66f 3511 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
e22b531b
HT		 3512 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3513 HCLGE_INT_TYPE_S,
3514 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3515 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3516 HCLGE_TQP_ID_S, node->tqp_index);
3517 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3518 HCLGE_INT_GL_IDX_S,
3519 hnae3_get_field(node->int_gl_idx,
3520 HNAE3_RING_GL_IDX_M,
3521 HNAE3_RING_GL_IDX_S));
63d7e66f 3522 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3523 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3524 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
63d7e66f 3525 req->vfid = vport->vport_id;
46a3df9f 3526
63d7e66f
SM		 3527 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3528 if (status) {
46a3df9f
S		 3529 dev_err(&hdev->pdev->dev,
3530 "Map TQP fail, status is %d.\n",
63d7e66f
SM		 3531 status);
3532 return -EIO;
46a3df9f
S		 3533 }
3534 i = 0;
3535
3536 hclge_cmd_setup_basic_desc(&desc,
63d7e66f 3537 op,
46a3df9f
S		 3538 false);
3539 req->int_vector_id = vector_id;
3540 }
3541 }
3542
3543 if (i > 0) {
3544 req->int_cause_num = i;
63d7e66f
SM		 3545 req->vfid = vport->vport_id;
3546 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3547 if (status) {
46a3df9f 3548 dev_err(&hdev->pdev->dev,
63d7e66f
SM		 3549 "Map TQP fail, status is %d.\n", status);
3550 return -EIO;
46a3df9f
S		 3551 }
3552 }
3553
3554 return 0;
3555}
3556
63d7e66f
SM		 3557static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3558 int vector,
3559 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3560{
3561 struct hclge_vport *vport = hclge_get_vport(handle);
3562 struct hclge_dev *hdev = vport->back;
3563 int vector_id;
3564
3565 vector_id = hclge_get_vector_index(hdev, vector);
3566 if (vector_id < 0) {
3567 dev_err(&hdev->pdev->dev,
63d7e66f 3568 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3569 return vector_id;
3570 }
3571
63d7e66f 3572 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3573}
3574
63d7e66f
SM		 3575static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3576 int vector,
3577 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3578{
3579 struct hclge_vport *vport = hclge_get_vport(handle);
3580 struct hclge_dev *hdev = vport->back;
63d7e66f 3581 int vector_id, ret;
46a3df9f 3582
f9637cc2
PL		 3583 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3584 return 0;
3585
46a3df9f
S		 3586 vector_id = hclge_get_vector_index(hdev, vector);
3587 if (vector_id < 0) {
3588 dev_err(&handle->pdev->dev,
3589 "Get vector index fail. ret =%d\n", vector_id);
3590 return vector_id;
3591 }
3592
63d7e66f 3593 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
7412200c 3594 if (ret)
63d7e66f
SM		 3595 dev_err(&handle->pdev->dev,
3596 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3597 vector_id,
3598 ret);
46a3df9f 3599
7412200c 3600 return ret;
46a3df9f
S		 3601}
3602
3603int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3604 struct hclge_promisc_param *param)
3605{
d44f9b63 3606 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3607 struct hclge_desc desc;
3608 int ret;
3609
3610 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3611
d44f9b63 3612 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3613 req->vf_id = param->vf_id;
4771e104
PL		 3614
3615 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3616 * pdev revision(0x20), new revision support them. The
3617 * value of this two fields will not return error when driver
3618 * send command to fireware in revision(0x20).
3619 */
3620 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3621 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3622
3623 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 3624 if (ret) {
46a3df9f
S		 3625 dev_err(&hdev->pdev->dev,
3626 "Set promisc mode fail, status is %d.\n", ret);
930ff2f6 3627 return ret;
3628 }
3629 return 0;
46a3df9f
S		 3630}
3631
3632void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3633 bool en_mc, bool en_bc, int vport_id)
3634{
3635 if (!param)
3636 return;
3637
3638 memset(param, 0, sizeof(struct hclge_promisc_param));
3639 if (en_uc)
3640 param->enable = HCLGE_PROMISC_EN_UC;
3641 if (en_mc)
3642 param->enable |= HCLGE_PROMISC_EN_MC;
3643 if (en_bc)
3644 param->enable |= HCLGE_PROMISC_EN_BC;
3645 param->vf_id = vport_id;
3646}
3647
e8600a3d
PL		 3648static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3649 bool en_mc_pmc)
46a3df9f
S		 3650{
3651 struct hclge_vport *vport = hclge_get_vport(handle);
3652 struct hclge_dev *hdev = vport->back;
3653 struct hclge_promisc_param param;
3654
e8600a3d
PL		 3655 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3656 vport->vport_id);
46a3df9f
S		 3657 hclge_cmd_set_promisc_mode(hdev, &param);
3658}
3659
3660static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3661{
3662 struct hclge_desc desc;
d44f9b63
YL		 3663 struct hclge_config_mac_mode_cmd *req =
3664 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3665 u32 loop_en = 0;
46a3df9f
S		 3666 int ret;
3667
3668 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
e22b531b
HT		 3669 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3670 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3671 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3672 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3673 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3674 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3675 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3676 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3677 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3678 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3679 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3680 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3681 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3682 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 3683 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3684
3685 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3686 if (ret)
3687 dev_err(&hdev->pdev->dev,
3688 "mac enable fail, ret =%d.\n", ret);
3689}
3690
e67d9ce9 3691static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 3692{
c39c4d98 3693 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 3694 struct hclge_desc desc;
3695 u32 loop_en;
3696 int ret;
3697
e67d9ce9
YL		 3698 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3699 /* 1 Read out the MAC mode config at first */
3700 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3701 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3702 if (ret) {
3703 dev_err(&hdev->pdev->dev,
3704 "mac loopback get fail, ret =%d.\n", ret);
3705 return ret;
3706 }
c39c4d98 3707
e67d9ce9
YL		 3708 /* 2 Then setup the loopback flag */
3709 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
e22b531b 3710 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
e67d9ce9
YL		 3711
3712 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 3713
e67d9ce9
YL		 3714 /* 3 Config mac work mode with loopback flag
3715 * and its original configure parameters
3716 */
3717 hclge_cmd_reuse_desc(&desc, false);
3718 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3719 if (ret)
3720 dev_err(&hdev->pdev->dev,
3721 "mac loopback set fail, ret =%d.\n", ret);
3722 return ret;
3723}
c39c4d98 3724
2fd5416a
YL		 3725static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en)
3726{
3727#define HCLGE_SERDES_RETRY_MS 10
3728#define HCLGE_SERDES_RETRY_NUM 100
3729 struct hclge_serdes_lb_cmd *req;
3730 struct hclge_desc desc;
3731 int ret, i = 0;
3732
3733 req = (struct hclge_serdes_lb_cmd *)&desc.data[0];
3734 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
3735
3736 if (en) {
3737 req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3738 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3739 } else {
3740 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3741 }
3742
3743 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3744 if (ret) {
3745 dev_err(&hdev->pdev->dev,
3746 "serdes loopback set fail, ret = %d\n", ret);
3747 return ret;
3748 }
3749
3750 do {
3751 msleep(HCLGE_SERDES_RETRY_MS);
3752 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3753 true);
3754 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3755 if (ret) {
3756 dev_err(&hdev->pdev->dev,
3757 "serdes loopback get, ret = %d\n", ret);
3758 return ret;
3759 }
3760 } while (++i < HCLGE_SERDES_RETRY_NUM &&
3761 !(req->result & HCLGE_CMD_SERDES_DONE_B));
3762
3763 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3764 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3765 return -EBUSY;
3766 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3767 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3768 return -EIO;
3769 }
3770
3771 return 0;
3772}
3773
e67d9ce9
YL		 3774static int hclge_set_loopback(struct hnae3_handle *handle,
3775 enum hnae3_loop loop_mode, bool en)
3776{
3777 struct hclge_vport *vport = hclge_get_vport(handle);
3778 struct hclge_dev *hdev = vport->back;
3779 int ret;
3780
3781 switch (loop_mode) {
3782 case HNAE3_MAC_INTER_LOOP_MAC:
3783 ret = hclge_set_mac_loopback(hdev, en);
c39c4d98 3784 break;
2fd5416a
YL		 3785 case HNAE3_MAC_INTER_LOOP_SERDES:
3786 ret = hclge_set_serdes_loopback(hdev, en);
3787 break;
c39c4d98
YL		 3788 default:
3789 ret = -ENOTSUPP;
3790 dev_err(&hdev->pdev->dev,
3791 "loop_mode %d is not supported\n", loop_mode);
3792 break;
3793 }
3794
3795 return ret;
3796}
3797
46a3df9f
S		 3798static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3799 int stream_id, bool enable)
3800{
3801 struct hclge_desc desc;
d44f9b63
YL		 3802 struct hclge_cfg_com_tqp_queue_cmd *req =
3803 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3804 int ret;
3805
3806 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3807 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3808 req->stream_id = cpu_to_le16(stream_id);
3809 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3810
3811 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3812 if (ret)
3813 dev_err(&hdev->pdev->dev,
3814 "Tqp enable fail, status =%d.\n", ret);
3815 return ret;
3816}
3817
3818static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3819{
3820 struct hclge_vport *vport = hclge_get_vport(handle);
3821 struct hnae3_queue *queue;
3822 struct hclge_tqp *tqp;
3823 int i;
3824
3825 for (i = 0; i < vport->alloc_tqps; i++) {
3826 queue = handle->kinfo.tqp[i];
3827 tqp = container_of(queue, struct hclge_tqp, q);
3828 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3829 }
3830}
3831
3832static int hclge_ae_start(struct hnae3_handle *handle)
3833{
3834 struct hclge_vport *vport = hclge_get_vport(handle);
3835 struct hclge_dev *hdev = vport->back;
e5e89cda 3836 int i, ret;
46a3df9f 3837
e5e89cda
PL		 3838 for (i = 0; i < vport->alloc_tqps; i++)
3839 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3840
46a3df9f
S		 3841 /* mac enable */
3842 hclge_cfg_mac_mode(hdev, true);
3843 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3844 mod_timer(&hdev->service_timer, jiffies + HZ);
3ae84019 3845 hdev->hw.mac.link = 0;
46a3df9f 3846
f9637cc2
PL		 3847 /* reset tqp stats */
3848 hclge_reset_tqp_stats(handle);
3849
46a3df9f
S		 3850 ret = hclge_mac_start_phy(hdev);
3851 if (ret)
3852 return ret;
3853
46a3df9f
S		 3854 return 0;
3855}
3856
3857static void hclge_ae_stop(struct hnae3_handle *handle)
3858{
3859 struct hclge_vport *vport = hclge_get_vport(handle);
3860 struct hclge_dev *hdev = vport->back;
e5e89cda 3861 int i;
46a3df9f 3862
f9637cc2
PL		 3863 del_timer_sync(&hdev->service_timer);
3864 cancel_work_sync(&hdev->service_task);
42b11ab7 3865 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
f9637cc2 3866
4486f5c9
YL		 3867 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3868 hclge_mac_stop_phy(hdev);
f9637cc2 3869 return;
4486f5c9 3870 }
f9637cc2 3871
e5e89cda
PL		 3872 for (i = 0; i < vport->alloc_tqps; i++)
3873 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3874
46a3df9f
S		 3875 /* Mac disable */
3876 hclge_cfg_mac_mode(hdev, false);
3877
3878 hclge_mac_stop_phy(hdev);
3879
3880 /* reset tqp stats */
3881 hclge_reset_tqp_stats(handle);
b91fb71c
FL		 3882 del_timer_sync(&hdev->service_timer);
3883 cancel_work_sync(&hdev->service_task);
3884 hclge_update_link_status(hdev);
46a3df9f
S		 3885}
3886
3887static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3888 u16 cmdq_resp, u8 resp_code,
3889 enum hclge_mac_vlan_tbl_opcode op)
3890{
3891 struct hclge_dev *hdev = vport->back;
3892 int return_status = -EIO;
3893
3894 if (cmdq_resp) {
3895 dev_err(&hdev->pdev->dev,
3896 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3897 cmdq_resp);
3898 return -EIO;
3899 }
3900
3901 if (op == HCLGE_MAC_VLAN_ADD) {
3902 if ((!resp_code) || (resp_code == 1)) {
3903 return_status = 0;
3904 } else if (resp_code == 2) {
2f894c5b 3905 return_status = -ENOSPC;
46a3df9f
S		 3906 dev_err(&hdev->pdev->dev,
3907 "add mac addr failed for uc_overflow.\n");
3908 } else if (resp_code == 3) {
2f894c5b 3909 return_status = -ENOSPC;
46a3df9f
S		 3910 dev_err(&hdev->pdev->dev,
3911 "add mac addr failed for mc_overflow.\n");
3912 } else {
3913 dev_err(&hdev->pdev->dev,
3914 "add mac addr failed for undefined, code=%d.\n",
3915 resp_code);
3916 }
3917 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3918 if (!resp_code) {
3919 return_status = 0;
3920 } else if (resp_code == 1) {
2f894c5b 3921 return_status = -ENOENT;
46a3df9f
S		 3922 dev_dbg(&hdev->pdev->dev,
3923 "remove mac addr failed for miss.\n");
3924 } else {
3925 dev_err(&hdev->pdev->dev,
3926 "remove mac addr failed for undefined, code=%d.\n",
3927 resp_code);
3928 }
3929 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3930 if (!resp_code) {
3931 return_status = 0;
3932 } else if (resp_code == 1) {
2f894c5b 3933 return_status = -ENOENT;
46a3df9f
S		 3934 dev_dbg(&hdev->pdev->dev,
3935 "lookup mac addr failed for miss.\n");
3936 } else {
3937 dev_err(&hdev->pdev->dev,
3938 "lookup mac addr failed for undefined, code=%d.\n",
3939 resp_code);
3940 }
3941 } else {
2f894c5b 3942 return_status = -EINVAL;
46a3df9f
S		 3943 dev_err(&hdev->pdev->dev,
3944 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3945 op);
3946 }
3947
3948 return return_status;
3949}
3950
3951static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3952{
3953 int word_num;
3954 int bit_num;
3955
3956 if (vfid > 255 || vfid < 0)
3957 return -EIO;
3958
3959 if (vfid >= 0 && vfid <= 191) {
3960 word_num = vfid / 32;
3961 bit_num = vfid % 32;
3962 if (clr)
a90bb9a5 3963 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3964 else
a90bb9a5 3965 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3966 } else {
3967 word_num = (vfid - 192) / 32;
3968 bit_num = vfid % 32;
3969 if (clr)
a90bb9a5 3970 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3971 else
a90bb9a5 3972 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3973 }
3974
3975 return 0;
3976}
3977
3978static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3979{
3980#define HCLGE_DESC_NUMBER 3
3981#define HCLGE_FUNC_NUMBER_PER_DESC 6
3982 int i, j;
3983
3984 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3985 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3986 if (desc[i].data[j])
3987 return false;
3988
3989 return true;
3990}
3991
d44f9b63 3992static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3993 const u8 *addr)
3994{
3995 const unsigned char *mac_addr = addr;
3996 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3997 (mac_addr[0]) | (mac_addr[1] << 8);
3998 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3999
4000 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
4001 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
4002}
4003
1db9b1bf
YL		 4004static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
4005 const u8 *addr)
46a3df9f
S		 4006{
4007 u16 high_val = addr[1] | (addr[0] << 8);
4008 struct hclge_dev *hdev = vport->back;
4009 u32 rsh = 4 - hdev->mta_mac_sel_type;
4010 u16 ret_val = (high_val >> rsh) & 0xfff;
4011
4012 return ret_val;
4013}
4014
4015static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
4016 enum hclge_mta_dmac_sel_type mta_mac_sel,
4017 bool enable)
4018{
d44f9b63 4019 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 4020 struct hclge_desc desc;
4021 int ret;
4022
d44f9b63 4023 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 4024 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
4025
e22b531b
HT		 4026 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
4027 enable);
4028 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
4029 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
46a3df9f
S		 4030
4031 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 4032 if (ret) {
46a3df9f
S		 4033 dev_err(&hdev->pdev->dev,
4034 "Config mat filter mode failed for cmd_send, ret =%d.\n",
4035 ret);
930ff2f6 4036 return ret;
4037 }
46a3df9f 4038
930ff2f6 4039 return 0;
46a3df9f
S		 4040}
4041
4042int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
4043 u8 func_id,
4044 bool enable)
4045{
d44f9b63 4046 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 4047 struct hclge_desc desc;
4048 int ret;
4049
d44f9b63 4050 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 4051 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
4052
e22b531b
HT		 4053 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
4054 enable);
46a3df9f
S		 4055 req->function_id = func_id;
4056
4057 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 4058 if (ret) {
46a3df9f
S		 4059 dev_err(&hdev->pdev->dev,
4060 "Config func_id enable failed for cmd_send, ret =%d.\n",
4061 ret);
930ff2f6 4062 return ret;
4063 }
46a3df9f 4064
930ff2f6 4065 return 0;
46a3df9f
S		 4066}
4067
4068static int hclge_set_mta_table_item(struct hclge_vport *vport,
4069 u16 idx,
4070 bool enable)
4071{
4072 struct hclge_dev *hdev = vport->back;
d44f9b63 4073 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 4074 struct hclge_desc desc;
a90bb9a5 4075 u16 item_idx = 0;
46a3df9f
S		 4076 int ret;
4077
d44f9b63 4078 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f 4079 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
e22b531b 4080 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
46a3df9f 4081
e22b531b
HT		 4082 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
4083 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 4084 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 4085
4086 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4087 if (ret) {
4088 dev_err(&hdev->pdev->dev,
4089 "Config mta table item failed for cmd_send, ret =%d.\n",
4090 ret);
4091 return ret;
4092 }
4093
a832d8b5
XW		 4094 if (enable)
4095 set_bit(idx, vport->mta_shadow);
4096 else
4097 clear_bit(idx, vport->mta_shadow);
4098
46a3df9f
S		 4099 return 0;
4100}
4101
a832d8b5
XW		 4102static int hclge_update_mta_status(struct hnae3_handle *handle)
4103{
4104 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
4105 struct hclge_vport *vport = hclge_get_vport(handle);
4106 struct net_device *netdev = handle->kinfo.netdev;
4107 struct netdev_hw_addr *ha;
4108 u16 tbl_idx;
4109
4110 memset(mta_status, 0, sizeof(mta_status));
4111
4112 /* update mta_status from mc addr list */
4113 netdev_for_each_mc_addr(ha, netdev) {
4114 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
4115 set_bit(tbl_idx, mta_status);
4116 }
4117
4118 return hclge_update_mta_status_common(vport, mta_status,
4119 0, HCLGE_MTA_TBL_SIZE, true);
4120}
4121
4122int hclge_update_mta_status_common(struct hclge_vport *vport,
4123 unsigned long *status,
4124 u16 idx,
4125 u16 count,
4126 bool update_filter)
4127{
4128 struct hclge_dev *hdev = vport->back;
4129 u16 update_max = idx + count;
4130 u16 check_max;
4131 int ret = 0;
4132 bool used;
4133 u16 i;
4134
4135 /* setup mta check range */
4136 if (update_filter) {
4137 i = 0;
4138 check_max = HCLGE_MTA_TBL_SIZE;
4139 } else {
4140 i = idx;
4141 check_max = update_max;
4142 }
4143
4144 used = false;
4145 /* check and update all mta item */
4146 for (; i < check_max; i++) {
4147 /* ignore unused item */
4148 if (!test_bit(i, vport->mta_shadow))
4149 continue;
4150
4151 /* if i in update range then update it */
4152 if (i >= idx && i < update_max)
4153 if (!test_bit(i - idx, status))
4154 hclge_set_mta_table_item(vport, i, false);
4155
4156 if (!used && test_bit(i, vport->mta_shadow))
4157 used = true;
4158 }
4159
4160 /* no longer use mta, disable it */
4161 if (vport->accept_mta_mc && update_filter && !used) {
4162 ret = hclge_cfg_func_mta_filter(hdev,
4163 vport->vport_id,
4164 false);
4165 if (ret)
4166 dev_err(&hdev->pdev->dev,
4167 "disable func mta filter fail ret=%d\n",
4168 ret);
4169 else
4170 vport->accept_mta_mc = false;
4171 }
4172
4173 return ret;
4174}
4175
46a3df9f 4176static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4177 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 4178{
4179 struct hclge_dev *hdev = vport->back;
4180 struct hclge_desc desc;
4181 u8 resp_code;
a90bb9a5 4182 u16 retval;
46a3df9f
S		 4183 int ret;
4184
4185 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4186
d44f9b63 4187 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4188
4189 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4190 if (ret) {
4191 dev_err(&hdev->pdev->dev,
4192 "del mac addr failed for cmd_send, ret =%d.\n",
4193 ret);
4194 return ret;
4195 }
a90bb9a5
YL		 4196 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4197 retval = le16_to_cpu(desc.retval);
46a3df9f 4198
a90bb9a5 4199 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4200 HCLGE_MAC_VLAN_REMOVE);
4201}
4202
4203static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4204 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4205 struct hclge_desc *desc,
4206 bool is_mc)
4207{
4208 struct hclge_dev *hdev = vport->back;
4209 u8 resp_code;
a90bb9a5 4210 u16 retval;
46a3df9f
S		 4211 int ret;
4212
4213 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4214 if (is_mc) {
4215 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4216 memcpy(desc[0].data,
4217 req,
d44f9b63 4218 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4219 hclge_cmd_setup_basic_desc(&desc[1],
4220 HCLGE_OPC_MAC_VLAN_ADD,
4221 true);
4222 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4223 hclge_cmd_setup_basic_desc(&desc[2],
4224 HCLGE_OPC_MAC_VLAN_ADD,
4225 true);
4226 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4227 } else {
4228 memcpy(desc[0].data,
4229 req,
d44f9b63 4230 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4231 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4232 }
4233 if (ret) {
4234 dev_err(&hdev->pdev->dev,
4235 "lookup mac addr failed for cmd_send, ret =%d.\n",
4236 ret);
4237 return ret;
4238 }
a90bb9a5
YL		 4239 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4240 retval = le16_to_cpu(desc[0].retval);
46a3df9f 4241
a90bb9a5 4242 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4243 HCLGE_MAC_VLAN_LKUP);
4244}
4245
4246static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4247 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4248 struct hclge_desc *mc_desc)
4249{
4250 struct hclge_dev *hdev = vport->back;
4251 int cfg_status;
4252 u8 resp_code;
a90bb9a5 4253 u16 retval;
46a3df9f
S		 4254 int ret;
4255
4256 if (!mc_desc) {
4257 struct hclge_desc desc;
4258
4259 hclge_cmd_setup_basic_desc(&desc,
4260 HCLGE_OPC_MAC_VLAN_ADD,
4261 false);
d44f9b63
YL		 4262 memcpy(desc.data, req,
4263 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4264 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 4265 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4266 retval = le16_to_cpu(desc.retval);
4267
4268 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4269 resp_code,
4270 HCLGE_MAC_VLAN_ADD);
4271 } else {
c3b6f755 4272 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 4273 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4274 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 4275 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4276 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 4277 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4278 memcpy(mc_desc[0].data, req,
d44f9b63 4279 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4280 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 4281 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4282 retval = le16_to_cpu(mc_desc[0].retval);
4283
4284 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4285 resp_code,
4286 HCLGE_MAC_VLAN_ADD);
4287 }
4288
4289 if (ret) {
4290 dev_err(&hdev->pdev->dev,
4291 "add mac addr failed for cmd_send, ret =%d.\n",
4292 ret);
4293 return ret;
4294 }
4295
4296 return cfg_status;
4297}
4298
4299static int hclge_add_uc_addr(struct hnae3_handle *handle,
4300 const unsigned char *addr)
4301{
4302 struct hclge_vport *vport = hclge_get_vport(handle);
4303
4304 return hclge_add_uc_addr_common(vport, addr);
4305}
4306
4307int hclge_add_uc_addr_common(struct hclge_vport *vport,
4308 const unsigned char *addr)
4309{
4310 struct hclge_dev *hdev = vport->back;
d44f9b63 4311 struct hclge_mac_vlan_tbl_entry_cmd req;
bf88f41f 4312 struct hclge_desc desc;
a90bb9a5 4313 u16 egress_port = 0;
04f0c72a 4314 int ret;
46a3df9f
S		 4315
4316 /* mac addr check */
4317 if (is_zero_ether_addr(addr) ||
4318 is_broadcast_ether_addr(addr) ||
4319 is_multicast_ether_addr(addr)) {
4320 dev_err(&hdev->pdev->dev,
4321 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4322 addr,
4323 is_zero_ether_addr(addr),
4324 is_broadcast_ether_addr(addr),
4325 is_multicast_ether_addr(addr));
4326 return -EINVAL;
4327 }
4328
4329 memset(&req, 0, sizeof(req));
e22b531b 4330 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 4331
e22b531b
HT		 4332 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4333 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 4334
4335 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4336
4337 hclge_prepare_mac_addr(&req, addr);
4338
bf88f41f
JS		 4339 /* Lookup the mac address in the mac_vlan table, and add
4340 * it if the entry is inexistent. Repeated unicast entry
4341 * is not allowed in the mac vlan table.
4342 */
4343 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4344 if (ret == -ENOENT)
4345 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4346
4347 /* check if we just hit the duplicate */
4348 if (!ret)
4349 ret = -EINVAL;
4350
4351 dev_err(&hdev->pdev->dev,
4352 "PF failed to add unicast entry(%pM) in the MAC table\n",
4353 addr);
46a3df9f 4354
04f0c72a 4355 return ret;
46a3df9f
S		 4356}
4357
4358static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4359 const unsigned char *addr)
4360{
4361 struct hclge_vport *vport = hclge_get_vport(handle);
4362
4363 return hclge_rm_uc_addr_common(vport, addr);
4364}
4365
4366int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4367 const unsigned char *addr)
4368{
4369 struct hclge_dev *hdev = vport->back;
d44f9b63 4370 struct hclge_mac_vlan_tbl_entry_cmd req;
04f0c72a 4371 int ret;
46a3df9f
S		 4372
4373 /* mac addr check */
4374 if (is_zero_ether_addr(addr) ||
4375 is_broadcast_ether_addr(addr) ||
4376 is_multicast_ether_addr(addr)) {
4377 dev_dbg(&hdev->pdev->dev,
4378 "Remove mac err! invalid mac:%pM.\n",
4379 addr);
4380 return -EINVAL;
4381 }
4382
4383 memset(&req, 0, sizeof(req));
e22b531b
HT		 4384 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4385 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 4386 hclge_prepare_mac_addr(&req, addr);
04f0c72a 4387 ret = hclge_remove_mac_vlan_tbl(vport, &req);
46a3df9f 4388
04f0c72a 4389 return ret;
46a3df9f
S		 4390}
4391
4392static int hclge_add_mc_addr(struct hnae3_handle *handle,
4393 const unsigned char *addr)
4394{
4395 struct hclge_vport *vport = hclge_get_vport(handle);
4396
27e6804f 4397 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 4398}
4399
4400int hclge_add_mc_addr_common(struct hclge_vport *vport,
4401 const unsigned char *addr)
4402{
4403 struct hclge_dev *hdev = vport->back;
d44f9b63 4404 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4405 struct hclge_desc desc[3];
4406 u16 tbl_idx;
4407 int status;
4408
4409 /* mac addr check */
4410 if (!is_multicast_ether_addr(addr)) {
4411 dev_err(&hdev->pdev->dev,
4412 "Add mc mac err! invalid mac:%pM.\n",
4413 addr);
4414 return -EINVAL;
4415 }
4416 memset(&req, 0, sizeof(req));
e22b531b
HT		 4417 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4418 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4419 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4420 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f
S		 4421 hclge_prepare_mac_addr(&req, addr);
4422 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4423 if (!status) {
4424 /* This mac addr exist, update VFID for it */
4425 hclge_update_desc_vfid(desc, vport->vport_id, false);
4426 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4427 } else {
4428 /* This mac addr do not exist, add new entry for it */
4429 memset(desc[0].data, 0, sizeof(desc[0].data));
4430 memset(desc[1].data, 0, sizeof(desc[0].data));
4431 memset(desc[2].data, 0, sizeof(desc[0].data));
4432 hclge_update_desc_vfid(desc, vport->vport_id, false);
4433 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4434 }
4435
a832d8b5
XW		 4436 /* If mc mac vlan table is full, use MTA table */
4437 if (status == -ENOSPC) {
4438 if (!vport->accept_mta_mc) {
4439 status = hclge_cfg_func_mta_filter(hdev,
4440 vport->vport_id,
4441 true);
4442 if (status) {
4443 dev_err(&hdev->pdev->dev,
4444 "set mta filter mode fail ret=%d\n",
4445 status);
4446 return status;
4447 }
4448 vport->accept_mta_mc = true;
4449 }
4450
4451 /* Set MTA table for this MAC address */
4452 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4453 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4454 }
46a3df9f
S		 4455
4456 return status;
4457}
4458
4459static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4460 const unsigned char *addr)
4461{
4462 struct hclge_vport *vport = hclge_get_vport(handle);
4463
4464 return hclge_rm_mc_addr_common(vport, addr);
4465}
4466
4467int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4468 const unsigned char *addr)
4469{
4470 struct hclge_dev *hdev = vport->back;
d44f9b63 4471 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4472 enum hclge_cmd_status status;
4473 struct hclge_desc desc[3];
46a3df9f
S		 4474
4475 /* mac addr check */
4476 if (!is_multicast_ether_addr(addr)) {
4477 dev_dbg(&hdev->pdev->dev,
4478 "Remove mc mac err! invalid mac:%pM.\n",
4479 addr);
4480 return -EINVAL;
4481 }
4482
4483 memset(&req, 0, sizeof(req));
e22b531b
HT		 4484 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4485 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4486 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4487 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f
S		 4488 hclge_prepare_mac_addr(&req, addr);
4489 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4490 if (!status) {
4491 /* This mac addr exist, remove this handle's VFID for it */
4492 hclge_update_desc_vfid(desc, vport->vport_id, true);
4493
4494 if (hclge_is_all_function_id_zero(desc))
4495 /* All the vfid is zero, so need to delete this entry */
4496 status = hclge_remove_mac_vlan_tbl(vport, &req);
4497 else
4498 /* Not all the vfid is zero, update the vfid */
4499 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4500
4501 } else {
a832d8b5
XW		 4502 /* Maybe this mac address is in mta table, but it cannot be
4503 * deleted here because an entry of mta represents an address
4504 * range rather than a specific address. the delete action to
4505 * all entries will take effect in update_mta_status called by
4506 * hns3_nic_set_rx_mode.
4507 */
4508 status = 0;
46a3df9f
S		 4509 }
4510
46a3df9f
S		 4511 return status;
4512}
4513
635bfb58
FL		 4514static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4515 u16 cmdq_resp, u8 resp_code)
4516{
4517#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4518#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4519#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4520#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4521
4522 int return_status;
4523
4524 if (cmdq_resp) {
4525 dev_err(&hdev->pdev->dev,
4526 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4527 cmdq_resp);
4528 return -EIO;
4529 }
4530
4531 switch (resp_code) {
4532 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4533 case HCLGE_ETHERTYPE_ALREADY_ADD:
4534 return_status = 0;
4535 break;
4536 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4537 dev_err(&hdev->pdev->dev,
4538 "add mac ethertype failed for manager table overflow.\n");
4539 return_status = -EIO;
4540 break;
4541 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4542 dev_err(&hdev->pdev->dev,
4543 "add mac ethertype failed for key conflict.\n");
4544 return_status = -EIO;
4545 break;
4546 default:
4547 dev_err(&hdev->pdev->dev,
4548 "add mac ethertype failed for undefined, code=%d.\n",
4549 resp_code);
4550 return_status = -EIO;
4551 }
4552
4553 return return_status;
4554}
4555
4556static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4557 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4558{
4559 struct hclge_desc desc;
4560 u8 resp_code;
4561 u16 retval;
4562 int ret;
4563
4564 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4565 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4566
4567 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4568 if (ret) {
4569 dev_err(&hdev->pdev->dev,
4570 "add mac ethertype failed for cmd_send, ret =%d.\n",
4571 ret);
4572 return ret;
4573 }
4574
4575 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4576 retval = le16_to_cpu(desc.retval);
4577
4578 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4579}
4580
4581static int init_mgr_tbl(struct hclge_dev *hdev)
4582{
4583 int ret;
4584 int i;
4585
4586 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4587 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4588 if (ret) {
4589 dev_err(&hdev->pdev->dev,
4590 "add mac ethertype failed, ret =%d.\n",
4591 ret);
4592 return ret;
4593 }
4594 }
4595
4596 return 0;
4597}
4598
46a3df9f
S		 4599static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4600{
4601 struct hclge_vport *vport = hclge_get_vport(handle);
4602 struct hclge_dev *hdev = vport->back;
4603
4604 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4605}
4606
3cbf5e2d
FL		 4607static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4608 bool is_first)
46a3df9f
S		 4609{
4610 const unsigned char *new_addr = (const unsigned char *)p;
4611 struct hclge_vport *vport = hclge_get_vport(handle);
4612 struct hclge_dev *hdev = vport->back;
20a5c4c0 4613 int ret;
46a3df9f
S		 4614
4615 /* mac addr check */
4616 if (is_zero_ether_addr(new_addr) ||
4617 is_broadcast_ether_addr(new_addr) ||
4618 is_multicast_ether_addr(new_addr)) {
4619 dev_err(&hdev->pdev->dev,
4620 "Change uc mac err! invalid mac:%p.\n",
4621 new_addr);
4622 return -EINVAL;
4623 }
4624
3cbf5e2d 4625 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 4626 dev_warn(&hdev->pdev->dev,
3cbf5e2d 4627 "remove old uc mac address fail.\n");
46a3df9f 4628
20a5c4c0
FL		 4629 ret = hclge_add_uc_addr(handle, new_addr);
4630 if (ret) {
4631 dev_err(&hdev->pdev->dev,
4632 "add uc mac address fail, ret =%d.\n",
4633 ret);
4634
3cbf5e2d
FL		 4635 if (!is_first &&
4636 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 4637 dev_err(&hdev->pdev->dev,
3cbf5e2d 4638 "restore uc mac address fail.\n");
20a5c4c0
FL		 4639
4640 return -EIO;
46a3df9f
S		 4641 }
4642
532fdd5e 4643 ret = hclge_pause_addr_cfg(hdev, new_addr);
20a5c4c0
FL		 4644 if (ret) {
4645 dev_err(&hdev->pdev->dev,
4646 "configure mac pause address fail, ret =%d.\n",
4647 ret);
4648 return -EIO;
4649 }
4650
4651 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4652
4653 return 0;
46a3df9f
S		 4654}
4655
4656static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4657 bool filter_en)
4658{
d44f9b63 4659 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4660 struct hclge_desc desc;
4661 int ret;
4662
4663 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4664
d44f9b63 4665 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4666 req->vlan_type = vlan_type;
4667 req->vlan_fe = filter_en;
4668
4669 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 4670 if (ret) {
46a3df9f
S		 4671 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4672 ret);
930ff2f6 4673 return ret;
4674 }
46a3df9f 4675
930ff2f6 4676 return 0;
46a3df9f
S		 4677}
4678
d818396d
JS		 4679#define HCLGE_FILTER_TYPE_VF 0
4680#define HCLGE_FILTER_TYPE_PORT 1
4681
4682static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4683{
4684 struct hclge_vport *vport = hclge_get_vport(handle);
4685 struct hclge_dev *hdev = vport->back;
4686
4687 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4688}
4689
4e66632d
YL		 4690static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4691 bool is_kill, u16 vlan, u8 qos,
4692 __be16 proto)
46a3df9f
S		 4693{
4694#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4695 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4696 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4697 struct hclge_desc desc[2];
4698 u8 vf_byte_val;
4699 u8 vf_byte_off;
4700 int ret;
4701
4702 hclge_cmd_setup_basic_desc(&desc[0],
4703 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4704 hclge_cmd_setup_basic_desc(&desc[1],
4705 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4706
4707 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4708
4709 vf_byte_off = vfid / 8;
4710 vf_byte_val = 1 << (vfid % 8);
4711
d44f9b63
YL		 4712 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4713 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4714
a90bb9a5 4715 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4716 req0->vlan_cfg = is_kill;
4717
4718 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4719 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4720 else
4721 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4722
4723 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4724 if (ret) {
4725 dev_err(&hdev->pdev->dev,
4726 "Send vf vlan command fail, ret =%d.\n",
4727 ret);
4728 return ret;
4729 }
4730
4731 if (!is_kill) {
715d610d 4732#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 4733 if (!req0->resp_code || req0->resp_code == 1)
4734 return 0;
4735
715d610d
YL		 4736 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4737 dev_warn(&hdev->pdev->dev,
4738 "vf vlan table is full, vf vlan filter is disabled\n");
4739 return 0;
4740 }
4741
46a3df9f
S		 4742 dev_err(&hdev->pdev->dev,
4743 "Add vf vlan filter fail, ret =%d.\n",
4744 req0->resp_code);
4745 } else {
4746 if (!req0->resp_code)
4747 return 0;
4748
4749 dev_err(&hdev->pdev->dev,
4750 "Kill vf vlan filter fail, ret =%d.\n",
4751 req0->resp_code);
4752 }
4753
4754 return -EIO;
4755}
4756
4e66632d
YL		 4757static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4758 u16 vlan_id, bool is_kill)
46a3df9f 4759{
d44f9b63 4760 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4761 struct hclge_desc desc;
4762 u8 vlan_offset_byte_val;
4763 u8 vlan_offset_byte;
4764 u8 vlan_offset_160;
4765 int ret;
4766
4767 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4768
4769 vlan_offset_160 = vlan_id / 160;
4770 vlan_offset_byte = (vlan_id % 160) / 8;
4771 vlan_offset_byte_val = 1 << (vlan_id % 8);
4772
d44f9b63 4773 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4774 req->vlan_offset = vlan_offset_160;
4775 req->vlan_cfg = is_kill;
4776 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4777
4778 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4e66632d
YL		 4779 if (ret)
4780 dev_err(&hdev->pdev->dev,
4781 "port vlan command, send fail, ret =%d.\n", ret);
4782 return ret;
4783}
4784
4785static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4786 u16 vport_id, u16 vlan_id, u8 qos,
4787 bool is_kill)
4788{
4789 u16 vport_idx, vport_num = 0;
4790 int ret;
4791
4792 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4793 0, proto);
46a3df9f
S		 4794 if (ret) {
4795 dev_err(&hdev->pdev->dev,
4e66632d
YL		 4796 "Set %d vport vlan filter config fail, ret =%d.\n",
4797 vport_id, ret);
46a3df9f
S		 4798 return ret;
4799 }
4800
4e66632d
YL		 4801 /* vlan 0 may be added twice when 8021q module is enabled */
4802 if (!is_kill && !vlan_id &&
4803 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4804 return 0;
4805
4806 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 4807 dev_err(&hdev->pdev->dev,
4e66632d
YL		 4808 "Add port vlan failed, vport %d is already in vlan %d\n",
4809 vport_id, vlan_id);
4810 return -EINVAL;
46a3df9f
S		 4811 }
4812
4e66632d
YL		 4813 if (is_kill &&
4814 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4815 dev_err(&hdev->pdev->dev,
4816 "Delete port vlan failed, vport %d is not in vlan %d\n",
4817 vport_id, vlan_id);
4818 return -EINVAL;
4819 }
4820
4821 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID)
4822 vport_num++;
4823
4824 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4825 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4826 is_kill);
4827
4828 return ret;
4829}
4830
4831int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4832 u16 vlan_id, bool is_kill)
4833{
4834 struct hclge_vport *vport = hclge_get_vport(handle);
4835 struct hclge_dev *hdev = vport->back;
4836
4837 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4838 0, is_kill);
46a3df9f
S		 4839}
4840
4841static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4842 u16 vlan, u8 qos, __be16 proto)
4843{
4844 struct hclge_vport *vport = hclge_get_vport(handle);
4845 struct hclge_dev *hdev = vport->back;
4846
4847 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4848 return -EINVAL;
4849 if (proto != htons(ETH_P_8021Q))
4850 return -EPROTONOSUPPORT;
4851
4e66632d 4852 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 4853}
4854
e62f2a6b
PL		 4855static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4856{
4857 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4858 struct hclge_vport_vtag_tx_cfg_cmd *req;
4859 struct hclge_dev *hdev = vport->back;
4860 struct hclge_desc desc;
4861 int status;
4862
4863 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4864
4865 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4866 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4867 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
e22b531b 4868 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
b75b1a56 4869 vcfg->accept_tag1 ? 1 : 0);
e22b531b 4870 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
b75b1a56 4871 vcfg->accept_untag1 ? 1 : 0);
e22b531b 4872 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
b75b1a56 4873 vcfg->accept_tag2 ? 1 : 0);
e22b531b 4874 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
b75b1a56 4875 vcfg->accept_untag2 ? 1 : 0);
e22b531b 4876 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
e62f2a6b 4877 vcfg->insert_tag1_en ? 1 : 0);
e22b531b 4878 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
e62f2a6b 4879 vcfg->insert_tag2_en ? 1 : 0);
e22b531b 4880 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
e62f2a6b
PL		 4881
4882 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4883 req->vf_bitmap[req->vf_offset] =
4884 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4885
4886 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4887 if (status)
4888 dev_err(&hdev->pdev->dev,
4889 "Send port txvlan cfg command fail, ret =%d\n",
4890 status);
4891
4892 return status;
4893}
4894
4895static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4896{
4897 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4898 struct hclge_vport_vtag_rx_cfg_cmd *req;
4899 struct hclge_dev *hdev = vport->back;
4900 struct hclge_desc desc;
4901 int status;
4902
4903 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4904
4905 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
e22b531b
HT		 4906 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4907 vcfg->strip_tag1_en ? 1 : 0);
4908 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4909 vcfg->strip_tag2_en ? 1 : 0);
4910 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4911 vcfg->vlan1_vlan_prionly ? 1 : 0);
4912 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4913 vcfg->vlan2_vlan_prionly ? 1 : 0);
e62f2a6b
PL		 4914
4915 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4916 req->vf_bitmap[req->vf_offset] =
4917 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4918
4919 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4920 if (status)
4921 dev_err(&hdev->pdev->dev,
4922 "Send port rxvlan cfg command fail, ret =%d\n",
4923 status);
4924
4925 return status;
4926}
4927
4928static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4929{
4930 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4931 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4932 struct hclge_desc desc;
4933 int status;
4934
4935 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4936 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4937 rx_req->ot_fst_vlan_type =
4938 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4939 rx_req->ot_sec_vlan_type =
4940 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4941 rx_req->in_fst_vlan_type =
4942 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4943 rx_req->in_sec_vlan_type =
4944 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4945
4946 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4947 if (status) {
4948 dev_err(&hdev->pdev->dev,
4949 "Send rxvlan protocol type command fail, ret =%d\n",
4950 status);
4951 return status;
4952 }
4953
4954 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4955
4956 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4957 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4958 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4959
4960 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4961 if (status)
4962 dev_err(&hdev->pdev->dev,
4963 "Send txvlan protocol type command fail, ret =%d\n",
4964 status);
4965
4966 return status;
4967}
4968
46a3df9f
S		 4969static int hclge_init_vlan_config(struct hclge_dev *hdev)
4970{
e62f2a6b
PL		 4971#define HCLGE_DEF_VLAN_TYPE 0x8100
4972
5e43aef8 4973 struct hnae3_handle *handle;
e62f2a6b 4974 struct hclge_vport *vport;
46a3df9f 4975 int ret;
e62f2a6b
PL		 4976 int i;
4977
4978 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4979 if (ret)
4980 return ret;
46a3df9f 4981
e62f2a6b 4982 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4983 if (ret)
4984 return ret;
4985
e62f2a6b
PL		 4986 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4987 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4988 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4989 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4990 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4991 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4992
4993 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4994 if (ret)
4995 return ret;
46a3df9f 4996
e62f2a6b
PL		 4997 for (i = 0; i < hdev->num_alloc_vport; i++) {
4998 vport = &hdev->vport[i];
b75b1a56
PL		 4999 vport->txvlan_cfg.accept_tag1 = true;
5000 vport->txvlan_cfg.accept_untag1 = true;
5001
5002 /* accept_tag2 and accept_untag2 are not supported on
5003 * pdev revision(0x20), new revision support them. The
5004 * value of this two fields will not return error when driver
5005 * send command to fireware in revision(0x20).
5006 * This two fields can not configured by user.
5007 */
5008 vport->txvlan_cfg.accept_tag2 = true;
5009 vport->txvlan_cfg.accept_untag2 = true;
5010
e62f2a6b
PL		 5011 vport->txvlan_cfg.insert_tag1_en = false;
5012 vport->txvlan_cfg.insert_tag2_en = false;
5013 vport->txvlan_cfg.default_tag1 = 0;
5014 vport->txvlan_cfg.default_tag2 = 0;
5015
5016 ret = hclge_set_vlan_tx_offload_cfg(vport);
5017 if (ret)
5018 return ret;
5019
5020 vport->rxvlan_cfg.strip_tag1_en = false;
5021 vport->rxvlan_cfg.strip_tag2_en = true;
5022 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
5023 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
5024
5025 ret = hclge_set_vlan_rx_offload_cfg(vport);
5026 if (ret)
5027 return ret;
5028 }
5029
5e43aef8 5030 handle = &hdev->vport[0].nic;
4e66632d 5031 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 5032}
5033
3849d494 5034int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
5f9a7732
PL		 5035{
5036 struct hclge_vport *vport = hclge_get_vport(handle);
5037
5038 vport->rxvlan_cfg.strip_tag1_en = false;
5039 vport->rxvlan_cfg.strip_tag2_en = enable;
5040 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
5041 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
5042
5043 return hclge_set_vlan_rx_offload_cfg(vport);
5044}
5045
12341881 5046static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 5047{
d44f9b63 5048 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 5049 struct hclge_desc desc;
7393ed39 5050 int max_frm_size;
46a3df9f
S		 5051 int ret;
5052
7393ed39
FL		 5053 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5054
5055 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
5056 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 5057 return -EINVAL;
5058
7393ed39
FL		 5059 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
5060
46a3df9f
S		 5061 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
5062
d44f9b63 5063 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
7393ed39 5064 req->max_frm_size = cpu_to_le16(max_frm_size);
46a3df9f
S		 5065
5066 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
930ff2f6 5067 if (ret) {
46a3df9f 5068 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
930ff2f6 5069 return ret;
5070 }
7393ed39 5071
930ff2f6 5072 hdev->mps = max_frm_size;
5073
5074 return 0;
46a3df9f
S		 5075}
5076
12341881
FL		 5077static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
5078{
5079 struct hclge_vport *vport = hclge_get_vport(handle);
5080 struct hclge_dev *hdev = vport->back;
5081 int ret;
5082
5083 ret = hclge_set_mac_mtu(hdev, new_mtu);
5084 if (ret) {
5085 dev_err(&hdev->pdev->dev,
5086 "Change mtu fail, ret =%d\n", ret);
5087 return ret;
5088 }
5089
5090 ret = hclge_buffer_alloc(hdev);
5091 if (ret)
5092 dev_err(&hdev->pdev->dev,
5093 "Allocate buffer fail, ret =%d\n", ret);
5094
5095 return ret;
5096}
5097
46a3df9f
S		 5098static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
5099 bool enable)
5100{
d44f9b63 5101 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5102 struct hclge_desc desc;
5103 int ret;
5104
5105 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
5106
d44f9b63 5107 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 5108 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
e22b531b 5109 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 5110
5111 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5112 if (ret) {
5113 dev_err(&hdev->pdev->dev,
5114 "Send tqp reset cmd error, status =%d\n", ret);
5115 return ret;
5116 }
5117
5118 return 0;
5119}
5120
5121static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
5122{
d44f9b63 5123 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5124 struct hclge_desc desc;
5125 int ret;
5126
5127 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
5128
d44f9b63 5129 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 5130 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5131
5132 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5133 if (ret) {
5134 dev_err(&hdev->pdev->dev,
5135 "Get reset status error, status =%d\n", ret);
5136 return ret;
5137 }
5138
e22b531b 5139 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 5140}
5141
e5e89cda
PL		 5142static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
5143 u16 queue_id)
5144{
5145 struct hnae3_queue *queue;
5146 struct hclge_tqp *tqp;
5147
5148 queue = handle->kinfo.tqp[queue_id];
5149 tqp = container_of(queue, struct hclge_tqp, q);
5150
5151 return tqp->index;
5152}
5153
63d7e66f 5154void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 5155{
5156 struct hclge_vport *vport = hclge_get_vport(handle);
5157 struct hclge_dev *hdev = vport->back;
5158 int reset_try_times = 0;
5159 int reset_status;
e5e89cda 5160 u16 queue_gid;
46a3df9f
S		 5161 int ret;
5162
f9637cc2
PL		 5163 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5164 return;
5165
e5e89cda
PL		 5166 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
5167
46a3df9f
S		 5168 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
5169 if (ret) {
5170 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
5171 return;
5172 }
5173
e5e89cda 5174 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 5175 if (ret) {
5176 dev_warn(&hdev->pdev->dev,
5177 "Send reset tqp cmd fail, ret = %d\n", ret);
5178 return;
5179 }
5180
5181 reset_try_times = 0;
5182 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5183 /* Wait for tqp hw reset */
5184 msleep(20);
e5e89cda 5185 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 5186 if (reset_status)
5187 break;
5188 }
5189
5190 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5191 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5192 return;
5193 }
5194
e5e89cda 5195 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 5196 if (ret) {
5197 dev_warn(&hdev->pdev->dev,
5198 "Deassert the soft reset fail, ret = %d\n", ret);
5199 return;
5200 }
5201}
5202
d3ea7fc4
PL		 5203void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
5204{
5205 struct hclge_dev *hdev = vport->back;
5206 int reset_try_times = 0;
5207 int reset_status;
5208 u16 queue_gid;
5209 int ret;
5210
5211 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
5212
5213 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5214 if (ret) {
5215 dev_warn(&hdev->pdev->dev,
5216 "Send reset tqp cmd fail, ret = %d\n", ret);
5217 return;
5218 }
5219
5220 reset_try_times = 0;
5221 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5222 /* Wait for tqp hw reset */
5223 msleep(20);
5224 reset_status = hclge_get_reset_status(hdev, queue_gid);
5225 if (reset_status)
5226 break;
5227 }
5228
5229 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5230 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5231 return;
5232 }
5233
5234 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5235 if (ret)
5236 dev_warn(&hdev->pdev->dev,
5237 "Deassert the soft reset fail, ret = %d\n", ret);
5238}
5239
46a3df9f
S		 5240static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5241{
5242 struct hclge_vport *vport = hclge_get_vport(handle);
5243 struct hclge_dev *hdev = vport->back;
5244
5245 return hdev->fw_version;
5246}
5247
a2cfbadb
PL		 5248static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5249 u32 *flowctrl_adv)
5250{
5251 struct hclge_vport *vport = hclge_get_vport(handle);
5252 struct hclge_dev *hdev = vport->back;
5253 struct phy_device *phydev = hdev->hw.mac.phydev;
5254
5255 if (!phydev)
5256 return;
5257
5258 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5259 (phydev->advertising & ADVERTISED_Asym_Pause);
5260}
5261
09ea401e
PL		 5262static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5263{
5264 struct phy_device *phydev = hdev->hw.mac.phydev;
5265
5266 if (!phydev)
5267 return;
5268
5269 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
5270
5271 if (rx_en)
5272 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5273
5274 if (tx_en)
5275 phydev->advertising ^= ADVERTISED_Asym_Pause;
5276}
5277
5278static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5279{
09ea401e
PL		 5280 int ret;
5281
5282 if (rx_en && tx_en)
7a28a82a 5283 hdev->fc_mode_last_time = HCLGE_FC_FULL;
09ea401e 5284 else if (rx_en && !tx_en)
7a28a82a 5285 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
09ea401e 5286 else if (!rx_en && tx_en)
7a28a82a 5287 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
09ea401e 5288 else
7a28a82a 5289 hdev->fc_mode_last_time = HCLGE_FC_NONE;
09ea401e 5290
7a28a82a 5291 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
09ea401e 5292 return 0;
09ea401e
PL		 5293
5294 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
5295 if (ret) {
5296 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
5297 ret);
5298 return ret;
5299 }
5300
7a28a82a 5301 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
09ea401e
PL		 5302
5303 return 0;
5304}
5305
6282f2ea
PL		 5306int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5307{
5308 struct phy_device *phydev = hdev->hw.mac.phydev;
5309 u16 remote_advertising = 0;
5310 u16 local_advertising = 0;
5311 u32 rx_pause, tx_pause;
5312 u8 flowctl;
5313
5314 if (!phydev->link || !phydev->autoneg)
5315 return 0;
5316
5317 if (phydev->advertising & ADVERTISED_Pause)
5318 local_advertising = ADVERTISE_PAUSE_CAP;
5319
5320 if (phydev->advertising & ADVERTISED_Asym_Pause)
5321 local_advertising |= ADVERTISE_PAUSE_ASYM;
5322
5323 if (phydev->pause)
5324 remote_advertising = LPA_PAUSE_CAP;
5325
5326 if (phydev->asym_pause)
5327 remote_advertising |= LPA_PAUSE_ASYM;
5328
5329 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5330 remote_advertising);
5331 tx_pause = flowctl & FLOW_CTRL_TX;
5332 rx_pause = flowctl & FLOW_CTRL_RX;
5333
5334 if (phydev->duplex == HCLGE_MAC_HALF) {
5335 tx_pause = 0;
5336 rx_pause = 0;
5337 }
5338
5339 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5340}
5341
46a3df9f
S		 5342static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5343 u32 *rx_en, u32 *tx_en)
5344{
5345 struct hclge_vport *vport = hclge_get_vport(handle);
5346 struct hclge_dev *hdev = vport->back;
5347
5348 *auto_neg = hclge_get_autoneg(handle);
5349
5350 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5351 *rx_en = 0;
5352 *tx_en = 0;
5353 return;
5354 }
5355
5356 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5357 *rx_en = 1;
5358 *tx_en = 0;
5359 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5360 *tx_en = 1;
5361 *rx_en = 0;
5362 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5363 *rx_en = 1;
5364 *tx_en = 1;
5365 } else {
5366 *rx_en = 0;
5367 *tx_en = 0;
5368 }
5369}
5370
09ea401e
PL		 5371static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5372 u32 rx_en, u32 tx_en)
5373{
5374 struct hclge_vport *vport = hclge_get_vport(handle);
5375 struct hclge_dev *hdev = vport->back;
5376 struct phy_device *phydev = hdev->hw.mac.phydev;
5377 u32 fc_autoneg;
5378
09ea401e
PL		 5379 fc_autoneg = hclge_get_autoneg(handle);
5380 if (auto_neg != fc_autoneg) {
5381 dev_info(&hdev->pdev->dev,
5382 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5383 return -EOPNOTSUPP;
5384 }
5385
5386 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5387 dev_info(&hdev->pdev->dev,
5388 "Priority flow control enabled. Cannot set link flow control.\n");
5389 return -EOPNOTSUPP;
5390 }
5391
5392 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5393
5394 if (!fc_autoneg)
5395 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5396
bef24782
FL		 5397 /* Only support flow control negotiation for netdev with
5398 * phy attached for now.
5399 */
5400 if (!phydev)
5401 return -EOPNOTSUPP;
5402
09ea401e
PL		 5403 return phy_start_aneg(phydev);
5404}
5405
46a3df9f
S		 5406static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5407 u8 *auto_neg, u32 *speed, u8 *duplex)
5408{
5409 struct hclge_vport *vport = hclge_get_vport(handle);
5410 struct hclge_dev *hdev = vport->back;
5411
5412 if (speed)
5413 *speed = hdev->hw.mac.speed;
5414 if (duplex)
5415 *duplex = hdev->hw.mac.duplex;
5416 if (auto_neg)
5417 *auto_neg = hdev->hw.mac.autoneg;
5418}
5419
5420static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5421{
5422 struct hclge_vport *vport = hclge_get_vport(handle);
5423 struct hclge_dev *hdev = vport->back;
5424
5425 if (media_type)
5426 *media_type = hdev->hw.mac.media_type;
5427}
5428
5429static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5430 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5431{
5432 struct hclge_vport *vport = hclge_get_vport(handle);
5433 struct hclge_dev *hdev = vport->back;
5434 struct phy_device *phydev = hdev->hw.mac.phydev;
5435 int mdix_ctrl, mdix, retval, is_resolved;
5436
5437 if (!phydev) {
5438 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5439 *tp_mdix = ETH_TP_MDI_INVALID;
5440 return;
5441 }
5442
5443 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5444
5445 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
e22b531b
HT		 5446 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5447 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 5448
5449 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
e22b531b
HT		 5450 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5451 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 5452
5453 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5454
5455 switch (mdix_ctrl) {
5456 case 0x0:
5457 *tp_mdix_ctrl = ETH_TP_MDI;
5458 break;
5459 case 0x1:
5460 *tp_mdix_ctrl = ETH_TP_MDI_X;
5461 break;
5462 case 0x3:
5463 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5464 break;
5465 default:
5466 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5467 break;
5468 }
5469
5470 if (!is_resolved)
5471 *tp_mdix = ETH_TP_MDI_INVALID;
5472 else if (mdix)
5473 *tp_mdix = ETH_TP_MDI_X;
5474 else
5475 *tp_mdix = ETH_TP_MDI;
5476}
5477
5478static int hclge_init_client_instance(struct hnae3_client *client,
5479 struct hnae3_ae_dev *ae_dev)
5480{
5481 struct hclge_dev *hdev = ae_dev->priv;
5482 struct hclge_vport *vport;
5483 int i, ret;
5484
5485 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5486 vport = &hdev->vport[i];
5487
5488 switch (client->type) {
5489 case HNAE3_CLIENT_KNIC:
5490
5491 hdev->nic_client = client;
5492 vport->nic.client = client;
5493 ret = client->ops->init_instance(&vport->nic);
5494 if (ret)
6f636872 5495 return ret;
46a3df9f
S		 5496
5497 if (hdev->roce_client &&
e92a0843 5498 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5499 struct hnae3_client *rc = hdev->roce_client;
5500
5501 ret = hclge_init_roce_base_info(vport);
5502 if (ret)
6f636872 5503 return ret;
46a3df9f
S		 5504
5505 ret = rc->ops->init_instance(&vport->roce);
5506 if (ret)
6f636872 5507 return ret;
46a3df9f
S		 5508 }
5509
5510 break;
5511 case HNAE3_CLIENT_UNIC:
5512 hdev->nic_client = client;
5513 vport->nic.client = client;
5514
5515 ret = client->ops->init_instance(&vport->nic);
5516 if (ret)
6f636872 5517 return ret;
46a3df9f
S		 5518
5519 break;
5520 case HNAE3_CLIENT_ROCE:
e92a0843 5521 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5522 hdev->roce_client = client;
5523 vport->roce.client = client;
5524 }
5525
3a46f34d 5526 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5527 ret = hclge_init_roce_base_info(vport);
5528 if (ret)
6f636872 5529 return ret;
46a3df9f
S		 5530
5531 ret = client->ops->init_instance(&vport->roce);
5532 if (ret)
6f636872 5533 return ret;
46a3df9f
S		 5534 }
5535 }
5536 }
5537
5538 return 0;
46a3df9f
S		 5539}
5540
5541static void hclge_uninit_client_instance(struct hnae3_client *client,
5542 struct hnae3_ae_dev *ae_dev)
5543{
5544 struct hclge_dev *hdev = ae_dev->priv;
5545 struct hclge_vport *vport;
5546 int i;
5547
5548 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5549 vport = &hdev->vport[i];
a17dcf3f 5550 if (hdev->roce_client) {
46a3df9f
S		 5551 hdev->roce_client->ops->uninit_instance(&vport->roce,
5552 0);
a17dcf3f
L		 5553 hdev->roce_client = NULL;
5554 vport->roce.client = NULL;
5555 }
46a3df9f
S		 5556 if (client->type == HNAE3_CLIENT_ROCE)
5557 return;
a17dcf3f 5558 if (client->ops->uninit_instance) {
46a3df9f 5559 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5560 hdev->nic_client = NULL;
5561 vport->nic.client = NULL;
5562 }
46a3df9f
S		 5563 }
5564}
5565
5566static int hclge_pci_init(struct hclge_dev *hdev)
5567{
5568 struct pci_dev *pdev = hdev->pdev;
5569 struct hclge_hw *hw;
5570 int ret;
5571
5572 ret = pci_enable_device(pdev);
5573 if (ret) {
5574 dev_err(&pdev->dev, "failed to enable PCI device\n");
6c46284e 5575 return ret;
46a3df9f
S		 5576 }
5577
5578 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5579 if (ret) {
5580 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5581 if (ret) {
5582 dev_err(&pdev->dev,
5583 "can't set consistent PCI DMA");
5584 goto err_disable_device;
5585 }
5586 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5587 }
5588
5589 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5590 if (ret) {
5591 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5592 goto err_disable_device;
5593 }
5594
5595 pci_set_master(pdev);
5596 hw = &hdev->hw;
46a3df9f
S		 5597 hw->io_base = pcim_iomap(pdev, 2, 0);
5598 if (!hw->io_base) {
5599 dev_err(&pdev->dev, "Can't map configuration register space\n");
5600 ret = -ENOMEM;
5601 goto err_clr_master;
5602 }
5603
709eb41a
L		 5604 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5605
46a3df9f
S		 5606 return 0;
5607err_clr_master:
5608 pci_clear_master(pdev);
5609 pci_release_regions(pdev);
5610err_disable_device:
5611 pci_disable_device(pdev);
46a3df9f
S		 5612
5613 return ret;
5614}
5615
5616static void hclge_pci_uninit(struct hclge_dev *hdev)
5617{
5618 struct pci_dev *pdev = hdev->pdev;
5619
7d6d639b 5620 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 5621 pci_free_irq_vectors(pdev);
46a3df9f
S		 5622 pci_clear_master(pdev);
5623 pci_release_mem_regions(pdev);
5624 pci_disable_device(pdev);
5625}
5626
71d7e8ea
PL		 5627static void hclge_state_init(struct hclge_dev *hdev)
5628{
5629 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5630 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5631 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5632 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5633 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5634 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5635}
5636
5637static void hclge_state_uninit(struct hclge_dev *hdev)
5638{
5639 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5640
5641 if (hdev->service_timer.function)
5642 del_timer_sync(&hdev->service_timer);
5643 if (hdev->service_task.func)
5644 cancel_work_sync(&hdev->service_task);
5645 if (hdev->rst_service_task.func)
5646 cancel_work_sync(&hdev->rst_service_task);
5647 if (hdev->mbx_service_task.func)
5648 cancel_work_sync(&hdev->mbx_service_task);
5649}
5650
46a3df9f
S		 5651static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5652{
5653 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5654 struct hclge_dev *hdev;
5655 int ret;
5656
5657 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5658 if (!hdev) {
5659 ret = -ENOMEM;
e0027501 5660 goto out;
46a3df9f
S		 5661 }
5662
46a3df9f
S		 5663 hdev->pdev = pdev;
5664 hdev->ae_dev = ae_dev;
4ed340ab 5665 hdev->reset_type = HNAE3_NONE_RESET;
46a3df9f
S		 5666 ae_dev->priv = hdev;
5667
46a3df9f
S		 5668 ret = hclge_pci_init(hdev);
5669 if (ret) {
5670 dev_err(&pdev->dev, "PCI init failed\n");
e0027501 5671 goto out;
46a3df9f
S		 5672 }
5673
3efb960f
L		 5674 /* Firmware command queue initialize */
5675 ret = hclge_cmd_queue_init(hdev);
5676 if (ret) {
5677 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
e0027501 5678 goto err_pci_uninit;
3efb960f
L		 5679 }
5680
5681 /* Firmware command initialize */
46a3df9f
S		 5682 ret = hclge_cmd_init(hdev);
5683 if (ret)
e0027501 5684 goto err_cmd_uninit;
46a3df9f
S		 5685
5686 ret = hclge_get_cap(hdev);
5687 if (ret) {
e00e2197
CIK		 5688 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5689 ret);
e0027501 5690 goto err_cmd_uninit;
46a3df9f
S		 5691 }
5692
5693 ret = hclge_configure(hdev);
5694 if (ret) {
5695 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
e0027501 5696 goto err_cmd_uninit;
46a3df9f
S		 5697 }
5698
887c3820 5699 ret = hclge_init_msi(hdev);
46a3df9f 5700 if (ret) {
887c3820 5701 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
e0027501 5702 goto err_cmd_uninit;
46a3df9f
S		 5703 }
5704
466b0c00
L		 5705 ret = hclge_misc_irq_init(hdev);
5706 if (ret) {
5707 dev_err(&pdev->dev,
5708 "Misc IRQ(vector0) init error, ret = %d.\n",
5709 ret);
e0027501 5710 goto err_msi_uninit;
466b0c00
L		 5711 }
5712
46a3df9f
S		 5713 ret = hclge_alloc_tqps(hdev);
5714 if (ret) {
5715 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
e0027501 5716 goto err_msi_irq_uninit;
46a3df9f
S		 5717 }
5718
5719 ret = hclge_alloc_vport(hdev);
5720 if (ret) {
5721 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
e0027501 5722 goto err_msi_irq_uninit;
46a3df9f
S		 5723 }
5724
7df7dad6
L		 5725 ret = hclge_map_tqp(hdev);
5726 if (ret) {
5727 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
bc59f827 5728 goto err_msi_irq_uninit;
7df7dad6
L		 5729 }
5730
dea9a821
HT		 5731 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5732 ret = hclge_mac_mdio_config(hdev);
5733 if (ret) {
5734 dev_err(&hdev->pdev->dev,
5735 "mdio config fail ret=%d\n", ret);
bc59f827 5736 goto err_msi_irq_uninit;
dea9a821 5737 }
cf9cca2d 5738 }
5739
46a3df9f
S		 5740 ret = hclge_mac_init(hdev);
5741 if (ret) {
5742 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
e0027501 5743 goto err_mdiobus_unreg;
46a3df9f 5744 }
46a3df9f
S		 5745
5746 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5747 if (ret) {
5748 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
e0027501 5749 goto err_mdiobus_unreg;
46a3df9f
S		 5750 }
5751
46a3df9f
S		 5752 ret = hclge_init_vlan_config(hdev);
5753 if (ret) {
5754 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
e0027501 5755 goto err_mdiobus_unreg;
46a3df9f
S		 5756 }
5757
5758 ret = hclge_tm_schd_init(hdev);
5759 if (ret) {
5760 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
e0027501 5761 goto err_mdiobus_unreg;
68ece54e
YL		 5762 }
5763
8015bb74 5764 hclge_rss_init_cfg(hdev);
68ece54e
YL		 5765 ret = hclge_rss_init_hw(hdev);
5766 if (ret) {
5767 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
e0027501 5768 goto err_mdiobus_unreg;
46a3df9f
S		 5769 }
5770
635bfb58
FL		 5771 ret = init_mgr_tbl(hdev);
5772 if (ret) {
5773 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
e0027501 5774 goto err_mdiobus_unreg;
635bfb58
FL		 5775 }
5776
cacde272
YL		 5777 hclge_dcb_ops_set(hdev);
5778
d039ef68 5779 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5780 INIT_WORK(&hdev->service_task, hclge_service_task);
ed4a1bb8 5781 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
22fd3468 5782 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5783
466b0c00
L		 5784 /* Enable MISC vector(vector0) */
5785 hclge_enable_vector(&hdev->misc_vector, true);
5786
71d7e8ea 5787 hclge_state_init(hdev);
46a3df9f
S		 5788
5789 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5790 return 0;
5791
e0027501
HT		 5792err_mdiobus_unreg:
5793 if (hdev->hw.mac.phydev)
5794 mdiobus_unregister(hdev->hw.mac.mdio_bus);
e0027501
HT		 5795err_msi_irq_uninit:
5796 hclge_misc_irq_uninit(hdev);
5797err_msi_uninit:
5798 pci_free_irq_vectors(pdev);
5799err_cmd_uninit:
5800 hclge_destroy_cmd_queue(&hdev->hw);
5801err_pci_uninit:
7d6d639b 5802 pcim_iounmap(pdev, hdev->hw.io_base);
e0027501 5803 pci_clear_master(pdev);
46a3df9f 5804 pci_release_regions(pdev);
e0027501 5805 pci_disable_device(pdev);
e0027501 5806out:
46a3df9f
S		 5807 return ret;
5808}
5809
c6dc5213 5810static void hclge_stats_clear(struct hclge_dev *hdev)
5811{
5812 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5813}
5814
4ed340ab
L		 5815static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5816{
5817 struct hclge_dev *hdev = ae_dev->priv;
5818 struct pci_dev *pdev = ae_dev->pdev;
5819 int ret;
5820
5821 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5822
c6dc5213 5823 hclge_stats_clear(hdev);
4e66632d 5824 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 5825
4ed340ab
L		 5826 ret = hclge_cmd_init(hdev);
5827 if (ret) {
5828 dev_err(&pdev->dev, "Cmd queue init failed\n");
5829 return ret;
5830 }
5831
5832 ret = hclge_get_cap(hdev);
5833 if (ret) {
5834 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5835 ret);
5836 return ret;
5837 }
5838
5839 ret = hclge_configure(hdev);
5840 if (ret) {
5841 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5842 return ret;
5843 }
5844
5845 ret = hclge_map_tqp(hdev);
5846 if (ret) {
5847 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5848 return ret;
5849 }
5850
5851 ret = hclge_mac_init(hdev);
5852 if (ret) {
5853 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5854 return ret;
5855 }
5856
4ed340ab
L		 5857 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5858 if (ret) {
5859 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5860 return ret;
5861 }
5862
5863 ret = hclge_init_vlan_config(hdev);
5864 if (ret) {
5865 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5866 return ret;
5867 }
5868
d85f1ab5 5869 ret = hclge_tm_init_hw(hdev);
4ed340ab 5870 if (ret) {
d85f1ab5 5871 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 5872 return ret;
5873 }
5874
5875 ret = hclge_rss_init_hw(hdev);
5876 if (ret) {
5877 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5878 return ret;
5879 }
5880
4ed340ab
L		 5881 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5882 HCLGE_DRIVER_NAME);
5883
5884 return 0;
5885}
5886
46a3df9f
S		 5887static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5888{
5889 struct hclge_dev *hdev = ae_dev->priv;
5890 struct hclge_mac *mac = &hdev->hw.mac;
5891
71d7e8ea 5892 hclge_state_uninit(hdev);
46a3df9f
S		 5893
5894 if (mac->phydev)
5895 mdiobus_unregister(mac->mdio_bus);
5896
466b0c00
L		 5897 /* Disable MISC vector(vector0) */
5898 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 5899 hclge_destroy_cmd_queue(&hdev->hw);
202f2014 5900 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5901 hclge_pci_uninit(hdev);
5902 ae_dev->priv = NULL;
5903}
5904
4f645a90
PL		 5905static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5906{
5907 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5908 struct hclge_vport *vport = hclge_get_vport(handle);
5909 struct hclge_dev *hdev = vport->back;
5910
5911 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5912}
5913
5914static void hclge_get_channels(struct hnae3_handle *handle,
5915 struct ethtool_channels *ch)
5916{
5917 struct hclge_vport *vport = hclge_get_vport(handle);
5918
5919 ch->max_combined = hclge_get_max_channels(handle);
5920 ch->other_count = 1;
5921 ch->max_other = 1;
5922 ch->combined_count = vport->alloc_tqps;
5923}
5924
f1f779ce
PL		 5925static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5926 u16 *free_tqps, u16 *max_rss_size)
5927{
5928 struct hclge_vport *vport = hclge_get_vport(handle);
5929 struct hclge_dev *hdev = vport->back;
5930 u16 temp_tqps = 0;
5931 int i;
5932
5933 for (i = 0; i < hdev->num_tqps; i++) {
5934 if (!hdev->htqp[i].alloced)
5935 temp_tqps++;
5936 }
5937 *free_tqps = temp_tqps;
5938 *max_rss_size = hdev->rss_size_max;
5939}
5940
5941static void hclge_release_tqp(struct hclge_vport *vport)
5942{
5943 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5944 struct hclge_dev *hdev = vport->back;
5945 int i;
5946
5947 for (i = 0; i < kinfo->num_tqps; i++) {
5948 struct hclge_tqp *tqp =
5949 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5950
5951 tqp->q.handle = NULL;
5952 tqp->q.tqp_index = 0;
5953 tqp->alloced = false;
5954 }
5955
5956 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5957 kinfo->tqp = NULL;
5958}
5959
5960static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5961{
5962 struct hclge_vport *vport = hclge_get_vport(handle);
5963 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5964 struct hclge_dev *hdev = vport->back;
5965 int cur_rss_size = kinfo->rss_size;
5966 int cur_tqps = kinfo->num_tqps;
5967 u16 tc_offset[HCLGE_MAX_TC_NUM];
5968 u16 tc_valid[HCLGE_MAX_TC_NUM];
5969 u16 tc_size[HCLGE_MAX_TC_NUM];
5970 u16 roundup_size;
5971 u32 *rss_indir;
5972 int ret, i;
5973
5974 hclge_release_tqp(vport);
5975
5976 ret = hclge_knic_setup(vport, new_tqps_num);
5977 if (ret) {
5978 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5979 return ret;
5980 }
5981
5982 ret = hclge_map_tqp_to_vport(hdev, vport);
5983 if (ret) {
5984 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5985 return ret;
5986 }
5987
5988 ret = hclge_tm_schd_init(hdev);
5989 if (ret) {
5990 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5991 return ret;
5992 }
5993
5994 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5995 roundup_size = ilog2(roundup_size);
5996 /* Set the RSS TC mode according to the new RSS size */
5997 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5998 tc_valid[i] = 0;
5999
6000 if (!(hdev->hw_tc_map & BIT(i)))
6001 continue;
6002
6003 tc_valid[i] = 1;
6004 tc_size[i] = roundup_size;
6005 tc_offset[i] = kinfo->rss_size * i;
6006 }
6007 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
6008 if (ret)
6009 return ret;
6010
6011 /* Reinitializes the rss indirect table according to the new RSS size */
6012 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
6013 if (!rss_indir)
6014 return -ENOMEM;
6015
6016 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
6017 rss_indir[i] = i % kinfo->rss_size;
6018
6019 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
6020 if (ret)
6021 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
6022 ret);
6023
6024 kfree(rss_indir);
6025
6026 if (!ret)
6027 dev_info(&hdev->pdev->dev,
6028 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
6029 cur_rss_size, kinfo->rss_size,
6030 cur_tqps, kinfo->rss_size * kinfo->num_tc);
6031
6032 return ret;
6033}
6034
db2a3e43
FL		 6035static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
6036 u32 *regs_num_64_bit)
6037{
6038 struct hclge_desc desc;
6039 u32 total_num;
6040 int ret;
6041
6042 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
6043 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6044 if (ret) {
6045 dev_err(&hdev->pdev->dev,
6046 "Query register number cmd failed, ret = %d.\n", ret);
6047 return ret;
6048 }
6049
6050 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
6051 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
6052
6053 total_num = *regs_num_32_bit + *regs_num_64_bit;
6054 if (!total_num)
6055 return -EINVAL;
6056
6057 return 0;
6058}
6059
6060static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6061 void *data)
6062{
6063#define HCLGE_32_BIT_REG_RTN_DATANUM 8
6064
6065 struct hclge_desc *desc;
6066 u32 *reg_val = data;
6067 __le32 *desc_data;
6068 int cmd_num;
6069 int i, k, n;
6070 int ret;
6071
6072 if (regs_num == 0)
6073 return 0;
6074
6075 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
6076 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6077 if (!desc)
6078 return -ENOMEM;
6079
6080 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
6081 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6082 if (ret) {
6083 dev_err(&hdev->pdev->dev,
6084 "Query 32 bit register cmd failed, ret = %d.\n", ret);
6085 kfree(desc);
6086 return ret;
6087 }
6088
6089 for (i = 0; i < cmd_num; i++) {
6090 if (i == 0) {
6091 desc_data = (__le32 *)(&desc[i].data[0]);
6092 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
6093 } else {
6094 desc_data = (__le32 *)(&desc[i]);
6095 n = HCLGE_32_BIT_REG_RTN_DATANUM;
6096 }
6097 for (k = 0; k < n; k++) {
6098 *reg_val++ = le32_to_cpu(*desc_data++);
6099
6100 regs_num--;
6101 if (!regs_num)
6102 break;
6103 }
6104 }
6105
6106 kfree(desc);
6107 return 0;
6108}
6109
6110static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6111 void *data)
6112{
6113#define HCLGE_64_BIT_REG_RTN_DATANUM 4
6114
6115 struct hclge_desc *desc;
6116 u64 *reg_val = data;
6117 __le64 *desc_data;
6118 int cmd_num;
6119 int i, k, n;
6120 int ret;
6121
6122 if (regs_num == 0)
6123 return 0;
6124
6125 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
6126 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6127 if (!desc)
6128 return -ENOMEM;
6129
6130 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
6131 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6132 if (ret) {
6133 dev_err(&hdev->pdev->dev,
6134 "Query 64 bit register cmd failed, ret = %d.\n", ret);
6135 kfree(desc);
6136 return ret;
6137 }
6138
6139 for (i = 0; i < cmd_num; i++) {
6140 if (i == 0) {
6141 desc_data = (__le64 *)(&desc[i].data[0]);
6142 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
6143 } else {
6144 desc_data = (__le64 *)(&desc[i]);
6145 n = HCLGE_64_BIT_REG_RTN_DATANUM;
6146 }
6147 for (k = 0; k < n; k++) {
6148 *reg_val++ = le64_to_cpu(*desc_data++);
6149
6150 regs_num--;
6151 if (!regs_num)
6152 break;
6153 }
6154 }
6155
6156 kfree(desc);
6157 return 0;
6158}
6159
6160static int hclge_get_regs_len(struct hnae3_handle *handle)
6161{
6162 struct hclge_vport *vport = hclge_get_vport(handle);
6163 struct hclge_dev *hdev = vport->back;
6164 u32 regs_num_32_bit, regs_num_64_bit;
6165 int ret;
6166
6167 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6168 if (ret) {
6169 dev_err(&hdev->pdev->dev,
6170 "Get register number failed, ret = %d.\n", ret);
6171 return -EOPNOTSUPP;
6172 }
6173
6174 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
6175}
6176
6177static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
6178 void *data)
6179{
6180 struct hclge_vport *vport = hclge_get_vport(handle);
6181 struct hclge_dev *hdev = vport->back;
6182 u32 regs_num_32_bit, regs_num_64_bit;
6183 int ret;
6184
6185 *version = hdev->fw_version;
6186
6187 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6188 if (ret) {
6189 dev_err(&hdev->pdev->dev,
6190 "Get register number failed, ret = %d.\n", ret);
6191 return;
6192 }
6193
6194 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
6195 if (ret) {
6196 dev_err(&hdev->pdev->dev,
6197 "Get 32 bit register failed, ret = %d.\n", ret);
6198 return;
6199 }
6200
6201 data = (u32 *)data + regs_num_32_bit;
6202 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
6203 data);
6204 if (ret)
6205 dev_err(&hdev->pdev->dev,
6206 "Get 64 bit register failed, ret = %d.\n", ret);
6207}
6208
fe3a3e15 6209static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
d9a0884e
JS		 6210{
6211 struct hclge_set_led_state_cmd *req;
6212 struct hclge_desc desc;
6213 int ret;
6214
6215 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
6216
6217 req = (struct hclge_set_led_state_cmd *)desc.data;
e22b531b 6218 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
d9a0884e
JS		 6219 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6220
6221 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6222 if (ret)
6223 dev_err(&hdev->pdev->dev,
6224 "Send set led state cmd error, ret =%d\n", ret);
6225
6226 return ret;
6227}
6228
6229enum hclge_led_status {
6230 HCLGE_LED_OFF,
6231 HCLGE_LED_ON,
6232 HCLGE_LED_NO_CHANGE = 0xFF,
6233};
6234
6235static int hclge_set_led_id(struct hnae3_handle *handle,
6236 enum ethtool_phys_id_state status)
6237{
d9a0884e
JS		 6238 struct hclge_vport *vport = hclge_get_vport(handle);
6239 struct hclge_dev *hdev = vport->back;
d9a0884e
JS		 6240
6241 switch (status) {
6242 case ETHTOOL_ID_ACTIVE:
fe3a3e15 6243 return hclge_set_led_status(hdev, HCLGE_LED_ON);
d9a0884e 6244 case ETHTOOL_ID_INACTIVE:
fe3a3e15 6245 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
d9a0884e 6246 default:
fe3a3e15 6247 return -EINVAL;
d9a0884e 6248 }
d9a0884e
JS		 6249}
6250
d92ceae9
FL		 6251static void hclge_get_link_mode(struct hnae3_handle *handle,
6252 unsigned long *supported,
6253 unsigned long *advertising)
6254{
6255 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
6256 struct hclge_vport *vport = hclge_get_vport(handle);
6257 struct hclge_dev *hdev = vport->back;
6258 unsigned int idx = 0;
6259
6260 for (; idx < size; idx++) {
6261 supported[idx] = hdev->hw.mac.supported[idx];
6262 advertising[idx] = hdev->hw.mac.advertising[idx];
6263 }
6264}
6265
6266static void hclge_get_port_type(struct hnae3_handle *handle,
6267 u8 *port_type)
6268{
6269 struct hclge_vport *vport = hclge_get_vport(handle);
6270 struct hclge_dev *hdev = vport->back;
6271 u8 media_type = hdev->hw.mac.media_type;
6272
6273 switch (media_type) {
6274 case HNAE3_MEDIA_TYPE_FIBER:
6275 *port_type = PORT_FIBRE;
6276 break;
6277 case HNAE3_MEDIA_TYPE_COPPER:
6278 *port_type = PORT_TP;
6279 break;
6280 case HNAE3_MEDIA_TYPE_UNKNOWN:
6281 default:
6282 *port_type = PORT_OTHER;
6283 break;
6284 }
6285}
6286
46a3df9f
S		 6287static const struct hnae3_ae_ops hclge_ops = {
6288 .init_ae_dev = hclge_init_ae_dev,
6289 .uninit_ae_dev = hclge_uninit_ae_dev,
6290 .init_client_instance = hclge_init_client_instance,
6291 .uninit_client_instance = hclge_uninit_client_instance,
63d7e66f
SM		 6292 .map_ring_to_vector = hclge_map_ring_to_vector,
6293 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 6294 .get_vector = hclge_get_vector,
7412200c 6295 .put_vector = hclge_put_vector,
46a3df9f 6296 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 6297 .set_loopback = hclge_set_loopback,
46a3df9f
S		 6298 .start = hclge_ae_start,
6299 .stop = hclge_ae_stop,
6300 .get_status = hclge_get_status,
6301 .get_ksettings_an_result = hclge_get_ksettings_an_result,
6302 .update_speed_duplex_h = hclge_update_speed_duplex_h,
6303 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6304 .get_media_type = hclge_get_media_type,
6305 .get_rss_key_size = hclge_get_rss_key_size,
6306 .get_rss_indir_size = hclge_get_rss_indir_size,
6307 .get_rss = hclge_get_rss,
6308 .set_rss = hclge_set_rss,
f7db940a 6309 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 6310 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 6311 .get_tc_size = hclge_get_tc_size,
6312 .get_mac_addr = hclge_get_mac_addr,
6313 .set_mac_addr = hclge_set_mac_addr,
6314 .add_uc_addr = hclge_add_uc_addr,
6315 .rm_uc_addr = hclge_rm_uc_addr,
6316 .add_mc_addr = hclge_add_mc_addr,
6317 .rm_mc_addr = hclge_rm_mc_addr,
a832d8b5 6318 .update_mta_status = hclge_update_mta_status,
46a3df9f
S		 6319 .set_autoneg = hclge_set_autoneg,
6320 .get_autoneg = hclge_get_autoneg,
6321 .get_pauseparam = hclge_get_pauseparam,
09ea401e 6322 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6323 .set_mtu = hclge_set_mtu,
6324 .reset_queue = hclge_reset_tqp,
6325 .get_stats = hclge_get_stats,
6326 .update_stats = hclge_update_stats,
6327 .get_strings = hclge_get_strings,
6328 .get_sset_count = hclge_get_sset_count,
6329 .get_fw_version = hclge_get_fw_version,
6330 .get_mdix_mode = hclge_get_mdix_mode,
d818396d 6331 .enable_vlan_filter = hclge_enable_vlan_filter,
4e66632d 6332 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 6333 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5f9a7732 6334 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6335 .reset_event = hclge_reset_event,
f1f779ce
PL		 6336 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6337 .set_channels = hclge_set_channels,
4f645a90 6338 .get_channels = hclge_get_channels,
a2cfbadb 6339 .get_flowctrl_adv = hclge_get_flowctrl_adv,
db2a3e43
FL		 6340 .get_regs_len = hclge_get_regs_len,
6341 .get_regs = hclge_get_regs,
d9a0884e 6342 .set_led_id = hclge_set_led_id,
d92ceae9
FL		 6343 .get_link_mode = hclge_get_link_mode,
6344 .get_port_type = hclge_get_port_type,
46a3df9f
S		 6345};
6346
6347static struct hnae3_ae_algo ae_algo = {
6348 .ops = &hclge_ops,
46a3df9f
S		 6349 .pdev_id_table = ae_algo_pci_tbl,
6350};
6351
6352static int hclge_init(void)
6353{
6354 pr_info("%s is initializing\n", HCLGE_NAME);
6355
a4d090cc
FL		 6356 hnae3_register_ae_algo(&ae_algo);
6357
6358 return 0;
46a3df9f
S		 6359}
6360
6361static void hclge_exit(void)
6362{
6363 hnae3_unregister_ae_algo(&ae_algo);
6364}
6365module_init(hclge_init);
6366module_exit(hclge_exit);
6367
6368MODULE_LICENSE("GPL");
6369MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6370MODULE_DESCRIPTION("HCLGE Driver");
6371MODULE_VERSION(HCLGE_MOD_VERSION);
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