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[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
20
21#include "hclge_cmd.h"
22#include "hclge_main.h"
23#include "hclge_mdio.h"
24#include "hclge_tm.h"
25#include "hnae3.h"
26
27#define HCLGE_NAME "hclge"
28#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
29#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
30#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
31#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
32
33static int hclge_rss_init_hw(struct hclge_dev *hdev);
34static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
35 enum hclge_mta_dmac_sel_type mta_mac_sel,
36 bool enable);
37static int hclge_init_vlan_config(struct hclge_dev *hdev);
38
39static struct hnae3_ae_algo ae_algo;
40
41static const struct pci_device_id ae_algo_pci_tbl[] = {
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 49 /* required last entry */
46a3df9f
S		 50 {0, }
51};
52
53static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
54 "Mac Loopback test",
55 "Serdes Loopback test",
56 "Phy Loopback test"
57};
58
59static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
66 {"igu_rx_uni_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
68 {"igu_rx_multi_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
70 {"igu_rx_broad_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
74 {"egu_tx_uni_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
76 {"egu_tx_multi_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
78 {"egu_tx_broad_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
88 {"ssu_tx_in_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
90 {"ssu_tx_out_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
92 {"ssu_rx_in_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
94 {"ssu_rx_out_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
96};
97
98static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
99 {"igu_rx_err_pkt",
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
105 {"egu_tx_1588_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
111 {"ppp_key_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
113 {"ppp_rlt_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
115 {"ssu_key_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
117 {"pkt_curr_buf_cnt",
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
119 {"qcn_fb_rcv_cnt",
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
121 {"qcn_fb_drop_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
205 {"mb_uncopy_num",
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
221};
222
223static const struct hclge_comm_stats_str g_mac_stats_string[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
280 {"mac_tx_overrsize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
294 {"mac_tx_1519_max_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
296 {"mac_rx_total_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
298 {"mac_rx_total_oct_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
300 {"mac_rx_good_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
302 {"mac_rx_bad_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
304 {"mac_rx_good_oct_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
306 {"mac_rx_bad_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
308 {"mac_rx_uni_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
310 {"mac_rx_multi_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
312 {"mac_rx_broad_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
314 {"mac_rx_undersize_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
316 {"mac_rx_overrsize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
318 {"mac_rx_64_oct_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
320 {"mac_rx_65_127_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
322 {"mac_rx_128_255_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
324 {"mac_rx_256_511_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
326 {"mac_rx_512_1023_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
328 {"mac_rx_1024_1518_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
330 {"mac_rx_1519_max_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
332
333 {"mac_trans_fragment_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
335 {"mac_trans_undermin_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
337 {"mac_trans_jabber_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
339 {"mac_trans_err_all_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
341 {"mac_trans_from_app_good_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
343 {"mac_trans_from_app_bad_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
345 {"mac_rcv_fragment_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
347 {"mac_rcv_undermin_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
349 {"mac_rcv_jabber_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
351 {"mac_rcv_fcs_err_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
353 {"mac_rcv_send_app_good_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
355 {"mac_rcv_send_app_bad_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
357};
358
359static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
360{
361#define HCLGE_64_BIT_CMD_NUM 5
362#define HCLGE_64_BIT_RTN_DATANUM 4
363 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
364 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
365 u64 *desc_data;
366 int i, k, n;
367 int ret;
368
369 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
370 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
371 if (ret) {
372 dev_err(&hdev->pdev->dev,
373 "Get 64 bit pkt stats fail, status = %d.\n", ret);
374 return ret;
375 }
376
377 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
378 if (unlikely(i == 0)) {
379 desc_data = (u64 *)(&desc[i].data[0]);
380 n = HCLGE_64_BIT_RTN_DATANUM - 1;
381 } else {
382 desc_data = (u64 *)(&desc[i]);
383 n = HCLGE_64_BIT_RTN_DATANUM;
384 }
385 for (k = 0; k < n; k++) {
386 *data++ += cpu_to_le64(*desc_data);
387 desc_data++;
388 }
389 }
390
391 return 0;
392}
393
394static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
395{
396 stats->pkt_curr_buf_cnt = 0;
397 stats->pkt_curr_buf_tc0_cnt = 0;
398 stats->pkt_curr_buf_tc1_cnt = 0;
399 stats->pkt_curr_buf_tc2_cnt = 0;
400 stats->pkt_curr_buf_tc3_cnt = 0;
401 stats->pkt_curr_buf_tc4_cnt = 0;
402 stats->pkt_curr_buf_tc5_cnt = 0;
403 stats->pkt_curr_buf_tc6_cnt = 0;
404 stats->pkt_curr_buf_tc7_cnt = 0;
405}
406
407static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
408{
409#define HCLGE_32_BIT_CMD_NUM 8
410#define HCLGE_32_BIT_RTN_DATANUM 8
411
412 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
413 struct hclge_32_bit_stats *all_32_bit_stats;
414 u32 *desc_data;
415 int i, k, n;
416 u64 *data;
417 int ret;
418
419 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
420 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
421
422 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
423 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
424 if (ret) {
425 dev_err(&hdev->pdev->dev,
426 "Get 32 bit pkt stats fail, status = %d.\n", ret);
427
428 return ret;
429 }
430
431 hclge_reset_partial_32bit_counter(all_32_bit_stats);
432 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
433 if (unlikely(i == 0)) {
434 all_32_bit_stats->igu_rx_err_pkt +=
435 cpu_to_le32(desc[i].data[0]);
436 all_32_bit_stats->igu_rx_no_eof_pkt +=
437 cpu_to_le32(desc[i].data[1] & 0xffff);
438 all_32_bit_stats->igu_rx_no_sof_pkt +=
439 cpu_to_le32((desc[i].data[1] >> 16) & 0xffff);
440
441 desc_data = (u32 *)(&desc[i].data[2]);
442 n = HCLGE_32_BIT_RTN_DATANUM - 4;
443 } else {
444 desc_data = (u32 *)(&desc[i]);
445 n = HCLGE_32_BIT_RTN_DATANUM;
446 }
447 for (k = 0; k < n; k++) {
448 *data++ += cpu_to_le32(*desc_data);
449 desc_data++;
450 }
451 }
452
453 return 0;
454}
455
456static int hclge_mac_update_stats(struct hclge_dev *hdev)
457{
458#define HCLGE_MAC_CMD_NUM 17
459#define HCLGE_RTN_DATA_NUM 4
460
461 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
462 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
463 u64 *desc_data;
464 int i, k, n;
465 int ret;
466
467 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
468 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
469 if (ret) {
470 dev_err(&hdev->pdev->dev,
471 "Get MAC pkt stats fail, status = %d.\n", ret);
472
473 return ret;
474 }
475
476 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
477 if (unlikely(i == 0)) {
478 desc_data = (u64 *)(&desc[i].data[0]);
479 n = HCLGE_RTN_DATA_NUM - 2;
480 } else {
481 desc_data = (u64 *)(&desc[i]);
482 n = HCLGE_RTN_DATA_NUM;
483 }
484 for (k = 0; k < n; k++) {
485 *data++ += cpu_to_le64(*desc_data);
486 desc_data++;
487 }
488 }
489
490 return 0;
491}
492
493static int hclge_tqps_update_stats(struct hnae3_handle *handle)
494{
495 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
496 struct hclge_vport *vport = hclge_get_vport(handle);
497 struct hclge_dev *hdev = vport->back;
498 struct hnae3_queue *queue;
499 struct hclge_desc desc[1];
500 struct hclge_tqp *tqp;
501 int ret, i;
502
503 for (i = 0; i < kinfo->num_tqps; i++) {
504 queue = handle->kinfo.tqp[i];
505 tqp = container_of(queue, struct hclge_tqp, q);
506 /* command : HCLGE_OPC_QUERY_IGU_STAT */
507 hclge_cmd_setup_basic_desc(&desc[0],
508 HCLGE_OPC_QUERY_RX_STATUS,
509 true);
510
511 desc[0].data[0] = (tqp->index & 0x1ff);
512 ret = hclge_cmd_send(&hdev->hw, desc, 1);
513 if (ret) {
514 dev_err(&hdev->pdev->dev,
515 "Query tqp stat fail, status = %d,queue = %d\n",
516 ret, i);
517 return ret;
518 }
519 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
520 cpu_to_le32(desc[0].data[4]);
521 }
522
523 for (i = 0; i < kinfo->num_tqps; i++) {
524 queue = handle->kinfo.tqp[i];
525 tqp = container_of(queue, struct hclge_tqp, q);
526 /* command : HCLGE_OPC_QUERY_IGU_STAT */
527 hclge_cmd_setup_basic_desc(&desc[0],
528 HCLGE_OPC_QUERY_TX_STATUS,
529 true);
530
531 desc[0].data[0] = (tqp->index & 0x1ff);
532 ret = hclge_cmd_send(&hdev->hw, desc, 1);
533 if (ret) {
534 dev_err(&hdev->pdev->dev,
535 "Query tqp stat fail, status = %d,queue = %d\n",
536 ret, i);
537 return ret;
538 }
539 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
540 cpu_to_le32(desc[0].data[4]);
541 }
542
543 return 0;
544}
545
546static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
547{
548 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
549 struct hclge_tqp *tqp;
550 u64 *buff = data;
551 int i;
552
553 for (i = 0; i < kinfo->num_tqps; i++) {
554 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
555 *buff++ = cpu_to_le64(tqp->tqp_stats.rcb_tx_ring_pktnum_rcd);
556 }
557
558 for (i = 0; i < kinfo->num_tqps; i++) {
559 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
560 *buff++ = cpu_to_le64(tqp->tqp_stats.rcb_rx_ring_pktnum_rcd);
561 }
562
563 return buff;
564}
565
566static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
567{
568 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
569
570 return kinfo->num_tqps * (2);
571}
572
573static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
574{
575 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
576 u8 *buff = data;
577 int i = 0;
578
579 for (i = 0; i < kinfo->num_tqps; i++) {
580 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
581 struct hclge_tqp, q);
582 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
583 tqp->index);
584 buff = buff + ETH_GSTRING_LEN;
585 }
586
587 for (i = 0; i < kinfo->num_tqps; i++) {
588 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
589 struct hclge_tqp, q);
590 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
591 tqp->index);
592 buff = buff + ETH_GSTRING_LEN;
593 }
594
595 return buff;
596}
597
598static u64 *hclge_comm_get_stats(void *comm_stats,
599 const struct hclge_comm_stats_str strs[],
600 int size, u64 *data)
601{
602 u64 *buf = data;
603 u32 i;
604
605 for (i = 0; i < size; i++)
606 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
607
608 return buf + size;
609}
610
611static u8 *hclge_comm_get_strings(u32 stringset,
612 const struct hclge_comm_stats_str strs[],
613 int size, u8 *data)
614{
615 char *buff = (char *)data;
616 u32 i;
617
618 if (stringset != ETH_SS_STATS)
619 return buff;
620
621 for (i = 0; i < size; i++) {
622 snprintf(buff, ETH_GSTRING_LEN,
623 strs[i].desc);
624 buff = buff + ETH_GSTRING_LEN;
625 }
626
627 return (u8 *)buff;
628}
629
630static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
631 struct net_device_stats *net_stats)
632{
633 net_stats->tx_dropped = 0;
634 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
635 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
636 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
637
638 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
639 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
640 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
641 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
642 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
643 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
644
645 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
646 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
647
648 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
649 net_stats->rx_length_errors =
650 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
651 net_stats->rx_length_errors +=
652 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
653 net_stats->rx_over_errors =
654 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
655}
656
657static void hclge_update_stats_for_all(struct hclge_dev *hdev)
658{
659 struct hnae3_handle *handle;
660 int status;
661
662 handle = &hdev->vport[0].nic;
663 if (handle->client) {
664 status = hclge_tqps_update_stats(handle);
665 if (status) {
666 dev_err(&hdev->pdev->dev,
667 "Update TQPS stats fail, status = %d.\n",
668 status);
669 }
670 }
671
672 status = hclge_mac_update_stats(hdev);
673 if (status)
674 dev_err(&hdev->pdev->dev,
675 "Update MAC stats fail, status = %d.\n", status);
676
677 status = hclge_32_bit_update_stats(hdev);
678 if (status)
679 dev_err(&hdev->pdev->dev,
680 "Update 32 bit stats fail, status = %d.\n",
681 status);
682
683 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
684}
685
686static void hclge_update_stats(struct hnae3_handle *handle,
687 struct net_device_stats *net_stats)
688{
689 struct hclge_vport *vport = hclge_get_vport(handle);
690 struct hclge_dev *hdev = vport->back;
691 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
692 int status;
693
694 status = hclge_mac_update_stats(hdev);
695 if (status)
696 dev_err(&hdev->pdev->dev,
697 "Update MAC stats fail, status = %d.\n",
698 status);
699
700 status = hclge_32_bit_update_stats(hdev);
701 if (status)
702 dev_err(&hdev->pdev->dev,
703 "Update 32 bit stats fail, status = %d.\n",
704 status);
705
706 status = hclge_64_bit_update_stats(hdev);
707 if (status)
708 dev_err(&hdev->pdev->dev,
709 "Update 64 bit stats fail, status = %d.\n",
710 status);
711
712 status = hclge_tqps_update_stats(handle);
713 if (status)
714 dev_err(&hdev->pdev->dev,
715 "Update TQPS stats fail, status = %d.\n",
716 status);
717
718 hclge_update_netstat(hw_stats, net_stats);
719}
720
721static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
722{
723#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
724
725 struct hclge_vport *vport = hclge_get_vport(handle);
726 struct hclge_dev *hdev = vport->back;
727 int count = 0;
728
729 /* Loopback test support rules:
730 * mac: only GE mode support
731 * serdes: all mac mode will support include GE/XGE/LGE/CGE
732 * phy: only support when phy device exist on board
733 */
734 if (stringset == ETH_SS_TEST) {
735 /* clear loopback bit flags at first */
736 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
737 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
738 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
739 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
740 count += 1;
741 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
742 } else {
743 count = -EOPNOTSUPP;
744 }
745 } else if (stringset == ETH_SS_STATS) {
746 count = ARRAY_SIZE(g_mac_stats_string) +
747 ARRAY_SIZE(g_all_32bit_stats_string) +
748 ARRAY_SIZE(g_all_64bit_stats_string) +
749 hclge_tqps_get_sset_count(handle, stringset);
750 }
751
752 return count;
753}
754
755static void hclge_get_strings(struct hnae3_handle *handle,
756 u32 stringset,
757 u8 *data)
758{
759 u8 *p = (char *)data;
760 int size;
761
762 if (stringset == ETH_SS_STATS) {
763 size = ARRAY_SIZE(g_mac_stats_string);
764 p = hclge_comm_get_strings(stringset,
765 g_mac_stats_string,
766 size,
767 p);
768 size = ARRAY_SIZE(g_all_32bit_stats_string);
769 p = hclge_comm_get_strings(stringset,
770 g_all_32bit_stats_string,
771 size,
772 p);
773 size = ARRAY_SIZE(g_all_64bit_stats_string);
774 p = hclge_comm_get_strings(stringset,
775 g_all_64bit_stats_string,
776 size,
777 p);
778 p = hclge_tqps_get_strings(handle, p);
779 } else if (stringset == ETH_SS_TEST) {
780 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
781 memcpy(p,
782 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
783 ETH_GSTRING_LEN);
784 p += ETH_GSTRING_LEN;
785 }
786 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
787 memcpy(p,
788 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
789 ETH_GSTRING_LEN);
790 p += ETH_GSTRING_LEN;
791 }
792 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
793 memcpy(p,
794 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
795 ETH_GSTRING_LEN);
796 p += ETH_GSTRING_LEN;
797 }
798 }
799}
800
801static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
802{
803 struct hclge_vport *vport = hclge_get_vport(handle);
804 struct hclge_dev *hdev = vport->back;
805 u64 *p;
806
807 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
808 g_mac_stats_string,
809 ARRAY_SIZE(g_mac_stats_string),
810 data);
811 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
812 g_all_32bit_stats_string,
813 ARRAY_SIZE(g_all_32bit_stats_string),
814 p);
815 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
816 g_all_64bit_stats_string,
817 ARRAY_SIZE(g_all_64bit_stats_string),
818 p);
819 p = hclge_tqps_get_stats(handle, p);
820}
821
822static int hclge_parse_func_status(struct hclge_dev *hdev,
823 struct hclge_func_status *status)
824{
825 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
826 return -EINVAL;
827
828 /* Set the pf to main pf */
829 if (status->pf_state & HCLGE_PF_STATE_MAIN)
830 hdev->flag |= HCLGE_FLAG_MAIN;
831 else
832 hdev->flag &= ~HCLGE_FLAG_MAIN;
833
834 hdev->num_req_vfs = status->vf_num / status->pf_num;
835 return 0;
836}
837
838static int hclge_query_function_status(struct hclge_dev *hdev)
839{
840 struct hclge_func_status *req;
841 struct hclge_desc desc;
842 int timeout = 0;
843 int ret;
844
845 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
846 req = (struct hclge_func_status *)desc.data;
847
848 do {
849 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
850 if (ret) {
851 dev_err(&hdev->pdev->dev,
852 "query function status failed %d.\n",
853 ret);
854
855 return ret;
856 }
857
858 /* Check pf reset is done */
859 if (req->pf_state)
860 break;
861 usleep_range(1000, 2000);
862 } while (timeout++ < 5);
863
864 ret = hclge_parse_func_status(hdev, req);
865
866 return ret;
867}
868
869static int hclge_query_pf_resource(struct hclge_dev *hdev)
870{
871 struct hclge_pf_res *req;
872 struct hclge_desc desc;
873 int ret;
874
875 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
876 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
877 if (ret) {
878 dev_err(&hdev->pdev->dev,
879 "query pf resource failed %d.\n", ret);
880 return ret;
881 }
882
883 req = (struct hclge_pf_res *)desc.data;
884 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
885 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
886
e92a0843 887 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 888 hdev->num_roce_msix =
889 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
890 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
891
892 /* PF should have NIC vectors and Roce vectors,
893 * NIC vectors are queued before Roce vectors.
894 */
895 hdev->num_msi = hdev->num_roce_msix + HCLGE_ROCE_VECTOR_OFFSET;
896 } else {
897 hdev->num_msi =
898 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
899 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
900 }
901
902 return 0;
903}
904
905static int hclge_parse_speed(int speed_cmd, int *speed)
906{
907 switch (speed_cmd) {
908 case 6:
909 *speed = HCLGE_MAC_SPEED_10M;
910 break;
911 case 7:
912 *speed = HCLGE_MAC_SPEED_100M;
913 break;
914 case 0:
915 *speed = HCLGE_MAC_SPEED_1G;
916 break;
917 case 1:
918 *speed = HCLGE_MAC_SPEED_10G;
919 break;
920 case 2:
921 *speed = HCLGE_MAC_SPEED_25G;
922 break;
923 case 3:
924 *speed = HCLGE_MAC_SPEED_40G;
925 break;
926 case 4:
927 *speed = HCLGE_MAC_SPEED_50G;
928 break;
929 case 5:
930 *speed = HCLGE_MAC_SPEED_100G;
931 break;
932 default:
933 return -EINVAL;
934 }
935
936 return 0;
937}
938
939static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
940{
941 struct hclge_cfg_param *req;
942 u64 mac_addr_tmp_high;
943 u64 mac_addr_tmp;
944 int i;
945
946 req = (struct hclge_cfg_param *)desc[0].data;
947
948 /* get the configuration */
949 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
950 HCLGE_CFG_VMDQ_M,
951 HCLGE_CFG_VMDQ_S);
952 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
953 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
954 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
955 HCLGE_CFG_TQP_DESC_N_M,
956 HCLGE_CFG_TQP_DESC_N_S);
957
958 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
959 HCLGE_CFG_PHY_ADDR_M,
960 HCLGE_CFG_PHY_ADDR_S);
961 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
962 HCLGE_CFG_MEDIA_TP_M,
963 HCLGE_CFG_MEDIA_TP_S);
964 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
965 HCLGE_CFG_RX_BUF_LEN_M,
966 HCLGE_CFG_RX_BUF_LEN_S);
967 /* get mac_address */
968 mac_addr_tmp = __le32_to_cpu(req->param[2]);
969 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
970 HCLGE_CFG_MAC_ADDR_H_M,
971 HCLGE_CFG_MAC_ADDR_H_S);
972
973 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
974
975 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
976 HCLGE_CFG_DEFAULT_SPEED_M,
977 HCLGE_CFG_DEFAULT_SPEED_S);
978 for (i = 0; i < ETH_ALEN; i++)
979 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
980
981 req = (struct hclge_cfg_param *)desc[1].data;
982 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
983}
984
985/* hclge_get_cfg: query the static parameter from flash
986 * @hdev: pointer to struct hclge_dev
987 * @hcfg: the config structure to be getted
988 */
989static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
990{
991 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
992 struct hclge_cfg_param *req;
993 int i, ret;
994
995 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
996 req = (struct hclge_cfg_param *)desc[i].data;
997 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
998 true);
999 hnae_set_field(req->offset, HCLGE_CFG_OFFSET_M,
1000 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1001 /* Len should be united by 4 bytes when send to hardware */
1002 hnae_set_field(req->offset, HCLGE_CFG_RD_LEN_M,
1003 HCLGE_CFG_RD_LEN_S,
1004 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1005 req->offset = cpu_to_le32(req->offset);
1006 }
1007
1008 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1009 if (ret) {
1010 dev_err(&hdev->pdev->dev,
1011 "get config failed %d.\n", ret);
1012 return ret;
1013 }
1014
1015 hclge_parse_cfg(hcfg, desc);
1016 return 0;
1017}
1018
1019static int hclge_get_cap(struct hclge_dev *hdev)
1020{
1021 int ret;
1022
1023 ret = hclge_query_function_status(hdev);
1024 if (ret) {
1025 dev_err(&hdev->pdev->dev,
1026 "query function status error %d.\n", ret);
1027 return ret;
1028 }
1029
1030 /* get pf resource */
1031 ret = hclge_query_pf_resource(hdev);
1032 if (ret) {
1033 dev_err(&hdev->pdev->dev,
1034 "query pf resource error %d.\n", ret);
1035 return ret;
1036 }
1037
1038 return 0;
1039}
1040
1041static int hclge_configure(struct hclge_dev *hdev)
1042{
1043 struct hclge_cfg cfg;
1044 int ret, i;
1045
1046 ret = hclge_get_cfg(hdev, &cfg);
1047 if (ret) {
1048 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1049 return ret;
1050 }
1051
1052 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1053 hdev->base_tqp_pid = 0;
1054 hdev->rss_size_max = 1;
1055 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1056 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1057 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1058 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1059 hdev->num_desc = cfg.tqp_desc_num;
1060 hdev->tm_info.num_pg = 1;
1061 hdev->tm_info.num_tc = cfg.tc_num;
1062 hdev->tm_info.hw_pfc_map = 0;
1063
1064 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1065 if (ret) {
1066 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1067 return ret;
1068 }
1069
1070 if ((hdev->tm_info.num_tc > HNAE3_MAX_TC) ||
1071 (hdev->tm_info.num_tc < 1)) {
1072 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1073 hdev->tm_info.num_tc);
1074 hdev->tm_info.num_tc = 1;
1075 }
1076
1077 /* Currently not support uncontiuous tc */
1078 for (i = 0; i < cfg.tc_num; i++)
1079 hnae_set_bit(hdev->hw_tc_map, i, 1);
1080
1081 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1082 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1083 else
1084 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1085
1086 return ret;
1087}
1088
1089static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1090 int tso_mss_max)
1091{
1092 struct hclge_cfg_tso_status *req;
1093 struct hclge_desc desc;
1094
1095 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1096
1097 req = (struct hclge_cfg_tso_status *)desc.data;
1098 hnae_set_field(req->tso_mss_min, HCLGE_TSO_MSS_MIN_M,
1099 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1100 hnae_set_field(req->tso_mss_max, HCLGE_TSO_MSS_MIN_M,
1101 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1102
1103 return hclge_cmd_send(&hdev->hw, &desc, 1);
1104}
1105
1106static int hclge_alloc_tqps(struct hclge_dev *hdev)
1107{
1108 struct hclge_tqp *tqp;
1109 int i;
1110
1111 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1112 sizeof(struct hclge_tqp), GFP_KERNEL);
1113 if (!hdev->htqp)
1114 return -ENOMEM;
1115
1116 tqp = hdev->htqp;
1117
1118 for (i = 0; i < hdev->num_tqps; i++) {
1119 tqp->dev = &hdev->pdev->dev;
1120 tqp->index = i;
1121
1122 tqp->q.ae_algo = &ae_algo;
1123 tqp->q.buf_size = hdev->rx_buf_len;
1124 tqp->q.desc_num = hdev->num_desc;
1125 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1126 i * HCLGE_TQP_REG_SIZE;
1127
1128 tqp++;
1129 }
1130
1131 return 0;
1132}
1133
1134static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1135 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1136{
1137 struct hclge_tqp_map *req;
1138 struct hclge_desc desc;
1139 int ret;
1140
1141 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1142
1143 req = (struct hclge_tqp_map *)desc.data;
1144 req->tqp_id = cpu_to_le16(tqp_pid);
1145 req->tqp_vf = cpu_to_le16(func_id);
1146 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1147 1 << HCLGE_TQP_MAP_EN_B;
1148 req->tqp_vid = cpu_to_le16(tqp_vid);
1149
1150 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1151 if (ret) {
1152 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1153 ret);
1154 return ret;
1155 }
1156
1157 return 0;
1158}
1159
1160static int hclge_assign_tqp(struct hclge_vport *vport,
1161 struct hnae3_queue **tqp, u16 num_tqps)
1162{
1163 struct hclge_dev *hdev = vport->back;
1164 int i, alloced, func_id, ret;
1165 bool is_pf;
1166
1167 func_id = vport->vport_id;
1168 is_pf = (vport->vport_id == 0) ? true : false;
1169
1170 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1171 alloced < num_tqps; i++) {
1172 if (!hdev->htqp[i].alloced) {
1173 hdev->htqp[i].q.handle = &vport->nic;
1174 hdev->htqp[i].q.tqp_index = alloced;
1175 tqp[alloced] = &hdev->htqp[i].q;
1176 hdev->htqp[i].alloced = true;
1177 ret = hclge_map_tqps_to_func(hdev, func_id,
1178 hdev->htqp[i].index,
1179 alloced, is_pf);
1180 if (ret)
1181 return ret;
1182
1183 alloced++;
1184 }
1185 }
1186 vport->alloc_tqps = num_tqps;
1187
1188 return 0;
1189}
1190
1191static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1192{
1193 struct hnae3_handle *nic = &vport->nic;
1194 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1195 struct hclge_dev *hdev = vport->back;
1196 int i, ret;
1197
1198 kinfo->num_desc = hdev->num_desc;
1199 kinfo->rx_buf_len = hdev->rx_buf_len;
1200 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1201 kinfo->rss_size
1202 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1203 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1204
1205 for (i = 0; i < HNAE3_MAX_TC; i++) {
1206 if (hdev->hw_tc_map & BIT(i)) {
1207 kinfo->tc_info[i].enable = true;
1208 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1209 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1210 kinfo->tc_info[i].tc = i;
1211 } else {
1212 /* Set to default queue if TC is disable */
1213 kinfo->tc_info[i].enable = false;
1214 kinfo->tc_info[i].tqp_offset = 0;
1215 kinfo->tc_info[i].tqp_count = 1;
1216 kinfo->tc_info[i].tc = 0;
1217 }
1218 }
1219
1220 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1221 sizeof(struct hnae3_queue *), GFP_KERNEL);
1222 if (!kinfo->tqp)
1223 return -ENOMEM;
1224
1225 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1226 if (ret) {
1227 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1228 return -EINVAL;
1229 }
1230
1231 return 0;
1232}
1233
1234static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1235{
1236 /* this would be initialized later */
1237}
1238
1239static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1240{
1241 struct hnae3_handle *nic = &vport->nic;
1242 struct hclge_dev *hdev = vport->back;
1243 int ret;
1244
1245 nic->pdev = hdev->pdev;
1246 nic->ae_algo = &ae_algo;
1247 nic->numa_node_mask = hdev->numa_node_mask;
1248
1249 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1250 ret = hclge_knic_setup(vport, num_tqps);
1251 if (ret) {
1252 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1253 ret);
1254 return ret;
1255 }
1256 } else {
1257 hclge_unic_setup(vport, num_tqps);
1258 }
1259
1260 return 0;
1261}
1262
1263static int hclge_alloc_vport(struct hclge_dev *hdev)
1264{
1265 struct pci_dev *pdev = hdev->pdev;
1266 struct hclge_vport *vport;
1267 u32 tqp_main_vport;
1268 u32 tqp_per_vport;
1269 int num_vport, i;
1270 int ret;
1271
1272 /* We need to alloc a vport for main NIC of PF */
1273 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1274
1275 if (hdev->num_tqps < num_vport)
1276 num_vport = hdev->num_tqps;
1277
1278 /* Alloc the same number of TQPs for every vport */
1279 tqp_per_vport = hdev->num_tqps / num_vport;
1280 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1281
1282 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1283 GFP_KERNEL);
1284 if (!vport)
1285 return -ENOMEM;
1286
1287 hdev->vport = vport;
1288 hdev->num_alloc_vport = num_vport;
1289
1290#ifdef CONFIG_PCI_IOV
1291 /* Enable SRIOV */
1292 if (hdev->num_req_vfs) {
1293 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1294 hdev->num_req_vfs);
1295 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1296 if (ret) {
1297 hdev->num_alloc_vfs = 0;
1298 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1299 ret);
1300 return ret;
1301 }
1302 }
1303 hdev->num_alloc_vfs = hdev->num_req_vfs;
1304#endif
1305
1306 for (i = 0; i < num_vport; i++) {
1307 vport->back = hdev;
1308 vport->vport_id = i;
1309
1310 if (i == 0)
1311 ret = hclge_vport_setup(vport, tqp_main_vport);
1312 else
1313 ret = hclge_vport_setup(vport, tqp_per_vport);
1314 if (ret) {
1315 dev_err(&pdev->dev,
1316 "vport setup failed for vport %d, %d\n",
1317 i, ret);
1318 return ret;
1319 }
1320
1321 vport++;
1322 }
1323
1324 return 0;
1325}
1326
acf61ecd
YL		 1327static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1328 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1329{
1330/* TX buffer size is unit by 128 byte */
1331#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1332#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1333 struct hclge_tx_buff_alloc *req;
1334 struct hclge_desc desc;
1335 int ret;
1336 u8 i;
1337
1338 req = (struct hclge_tx_buff_alloc *)desc.data;
1339
1340 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1341 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1342 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1343
46a3df9f
S		 1344 req->tx_pkt_buff[i] =
1345 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1346 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1347 }
46a3df9f
S		 1348
1349 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1350 if (ret) {
1351 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1352 ret);
1353 return ret;
1354 }
1355
1356 return 0;
1357}
1358
acf61ecd
YL		 1359static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1360 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1361{
acf61ecd 1362 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1363
1364 if (ret) {
1365 dev_err(&hdev->pdev->dev,
1366 "tx buffer alloc failed %d\n", ret);
1367 return ret;
1368 }
1369
1370 return 0;
1371}
1372
1373static int hclge_get_tc_num(struct hclge_dev *hdev)
1374{
1375 int i, cnt = 0;
1376
1377 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1378 if (hdev->hw_tc_map & BIT(i))
1379 cnt++;
1380 return cnt;
1381}
1382
1383static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1384{
1385 int i, cnt = 0;
1386
1387 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1388 if (hdev->hw_tc_map & BIT(i) &&
1389 hdev->tm_info.hw_pfc_map & BIT(i))
1390 cnt++;
1391 return cnt;
1392}
1393
1394/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1395static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1396 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1397{
1398 struct hclge_priv_buf *priv;
1399 int i, cnt = 0;
1400
1401 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1402 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1403 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1404 priv->enable)
1405 cnt++;
1406 }
1407
1408 return cnt;
1409}
1410
1411/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1412static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1413 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1414{
1415 struct hclge_priv_buf *priv;
1416 int i, cnt = 0;
1417
1418 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1419 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1420 if (hdev->hw_tc_map & BIT(i) &&
1421 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1422 priv->enable)
1423 cnt++;
1424 }
1425
1426 return cnt;
1427}
1428
acf61ecd 1429static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1430{
1431 struct hclge_priv_buf *priv;
1432 u32 rx_priv = 0;
1433 int i;
1434
1435 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1436 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1437 if (priv->enable)
1438 rx_priv += priv->buf_size;
1439 }
1440 return rx_priv;
1441}
1442
acf61ecd 1443static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1444{
1445 u32 i, total_tx_size = 0;
1446
1447 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1448 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1449
1450 return total_tx_size;
1451}
1452
acf61ecd
YL		 1453static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1454 struct hclge_pkt_buf_alloc *buf_alloc,
1455 u32 rx_all)
46a3df9f
S		 1456{
1457 u32 shared_buf_min, shared_buf_tc, shared_std;
1458 int tc_num, pfc_enable_num;
1459 u32 shared_buf;
1460 u32 rx_priv;
1461 int i;
1462
1463 tc_num = hclge_get_tc_num(hdev);
1464 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1465
d221df4e
YL		 1466 if (hnae3_dev_dcb_supported(hdev))
1467 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1468 else
1469 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1470
46a3df9f
S		 1471 shared_buf_tc = pfc_enable_num * hdev->mps +
1472 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1473 hdev->mps;
1474 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1475
acf61ecd 1476 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1477 if (rx_all <= rx_priv + shared_std)
1478 return false;
1479
1480 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1481 buf_alloc->s_buf.buf_size = shared_buf;
1482 buf_alloc->s_buf.self.high = shared_buf;
1483 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1484
1485 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1486 if ((hdev->hw_tc_map & BIT(i)) &&
1487 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1488 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1489 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1490 } else {
acf61ecd
YL		 1491 buf_alloc->s_buf.tc_thrd[i].low = 0;
1492 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1493 }
1494 }
1495
1496 return true;
1497}
1498
acf61ecd
YL		 1499static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1500 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1501{
1502 u32 i, total_size;
1503
1504 total_size = hdev->pkt_buf_size;
1505
1506 /* alloc tx buffer for all enabled tc */
1507 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1508 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1509
1510 if (total_size < HCLGE_DEFAULT_TX_BUF)
1511 return -ENOMEM;
1512
1513 if (hdev->hw_tc_map & BIT(i))
1514 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1515 else
1516 priv->tx_buf_size = 0;
1517
1518 total_size -= priv->tx_buf_size;
1519 }
1520
1521 return 0;
1522}
1523
46a3df9f
S		 1524/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1525 * @hdev: pointer to struct hclge_dev
acf61ecd 1526 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1527 * @return: 0: calculate sucessful, negative: fail
1528 */
acf61ecd
YL		 1529int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1530 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1531{
9ffe79a9 1532 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1533 int no_pfc_priv_num, pfc_priv_num;
1534 struct hclge_priv_buf *priv;
1535 int i;
1536
acf61ecd 1537 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1538
d602a525
YL		 1539 /* When DCB is not supported, rx private
1540 * buffer is not allocated.
1541 */
1542 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1543 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1544 return -ENOMEM;
1545
1546 return 0;
1547 }
1548
46a3df9f
S		 1549 /* step 1, try to alloc private buffer for all enabled tc */
1550 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1551 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1552 if (hdev->hw_tc_map & BIT(i)) {
1553 priv->enable = 1;
1554 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1555 priv->wl.low = hdev->mps;
1556 priv->wl.high = priv->wl.low + hdev->mps;
1557 priv->buf_size = priv->wl.high +
1558 HCLGE_DEFAULT_DV;
1559 } else {
1560 priv->wl.low = 0;
1561 priv->wl.high = 2 * hdev->mps;
1562 priv->buf_size = priv->wl.high;
1563 }
bb1fe9ea
YL		 1564 } else {
1565 priv->enable = 0;
1566 priv->wl.low = 0;
1567 priv->wl.high = 0;
1568 priv->buf_size = 0;
46a3df9f
S		 1569 }
1570 }
1571
acf61ecd 1572 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1573 return 0;
1574
1575 /* step 2, try to decrease the buffer size of
1576 * no pfc TC's private buffer
1577 */
1578 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1579 priv = &buf_alloc->priv_buf[i];
46a3df9f 1580
bb1fe9ea
YL		 1581 priv->enable = 0;
1582 priv->wl.low = 0;
1583 priv->wl.high = 0;
1584 priv->buf_size = 0;
1585
1586 if (!(hdev->hw_tc_map & BIT(i)))
1587 continue;
1588
1589 priv->enable = 1;
46a3df9f
S		 1590
1591 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1592 priv->wl.low = 128;
1593 priv->wl.high = priv->wl.low + hdev->mps;
1594 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1595 } else {
1596 priv->wl.low = 0;
1597 priv->wl.high = hdev->mps;
1598 priv->buf_size = priv->wl.high;
1599 }
1600 }
1601
acf61ecd 1602 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1603 return 0;
1604
1605 /* step 3, try to reduce the number of pfc disabled TCs,
1606 * which have private buffer
1607 */
1608 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1609 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1610
1611 /* let the last to be cleared first */
1612 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1613 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1614
1615 if (hdev->hw_tc_map & BIT(i) &&
1616 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1617 /* Clear the no pfc TC private buffer */
1618 priv->wl.low = 0;
1619 priv->wl.high = 0;
1620 priv->buf_size = 0;
1621 priv->enable = 0;
1622 no_pfc_priv_num--;
1623 }
1624
acf61ecd 1625 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1626 no_pfc_priv_num == 0)
1627 break;
1628 }
1629
acf61ecd 1630 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1631 return 0;
1632
1633 /* step 4, try to reduce the number of pfc enabled TCs
1634 * which have private buffer.
1635 */
acf61ecd 1636 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1637
1638 /* let the last to be cleared first */
1639 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1640 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1641
1642 if (hdev->hw_tc_map & BIT(i) &&
1643 hdev->tm_info.hw_pfc_map & BIT(i)) {
1644 /* Reduce the number of pfc TC with private buffer */
1645 priv->wl.low = 0;
1646 priv->enable = 0;
1647 priv->wl.high = 0;
1648 priv->buf_size = 0;
1649 pfc_priv_num--;
1650 }
1651
acf61ecd 1652 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1653 pfc_priv_num == 0)
1654 break;
1655 }
acf61ecd 1656 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1657 return 0;
1658
1659 return -ENOMEM;
1660}
1661
acf61ecd
YL		 1662static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1663 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1664{
1665 struct hclge_rx_priv_buff *req;
1666 struct hclge_desc desc;
1667 int ret;
1668 int i;
1669
1670 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1671 req = (struct hclge_rx_priv_buff *)desc.data;
1672
1673 /* Alloc private buffer TCs */
1674 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1675 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1676
1677 req->buf_num[i] =
1678 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1679 req->buf_num[i] |=
1680 cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B);
1681 }
1682
b8c8bf47 1683 req->shared_buf =
acf61ecd 1684 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1685 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1686
46a3df9f
S		 1687 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1688 if (ret) {
1689 dev_err(&hdev->pdev->dev,
1690 "rx private buffer alloc cmd failed %d\n", ret);
1691 return ret;
1692 }
1693
1694 return 0;
1695}
1696
1697#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1698
acf61ecd
YL		 1699static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1700 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1701{
1702 struct hclge_rx_priv_wl_buf *req;
1703 struct hclge_priv_buf *priv;
1704 struct hclge_desc desc[2];
1705 int i, j;
1706 int ret;
1707
1708 for (i = 0; i < 2; i++) {
1709 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1710 false);
1711 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1712
1713 /* The first descriptor set the NEXT bit to 1 */
1714 if (i == 0)
1715 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1716 else
1717 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1718
1719 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1720 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1721
1722 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1723 req->tc_wl[j].high =
1724 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1725 req->tc_wl[j].high |=
1726 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1727 HCLGE_RX_PRIV_EN_B);
1728 req->tc_wl[j].low =
1729 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1730 req->tc_wl[j].low |=
1731 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1732 HCLGE_RX_PRIV_EN_B);
1733 }
1734 }
1735
1736 /* Send 2 descriptor at one time */
1737 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1738 if (ret) {
1739 dev_err(&hdev->pdev->dev,
1740 "rx private waterline config cmd failed %d\n",
1741 ret);
1742 return ret;
1743 }
1744 return 0;
1745}
1746
acf61ecd
YL		 1747static int hclge_common_thrd_config(struct hclge_dev *hdev,
1748 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1749{
acf61ecd 1750 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1751 struct hclge_rx_com_thrd *req;
1752 struct hclge_desc desc[2];
1753 struct hclge_tc_thrd *tc;
1754 int i, j;
1755 int ret;
1756
1757 for (i = 0; i < 2; i++) {
1758 hclge_cmd_setup_basic_desc(&desc[i],
1759 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1760 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1761
1762 /* The first descriptor set the NEXT bit to 1 */
1763 if (i == 0)
1764 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1765 else
1766 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1767
1768 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1769 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1770
1771 req->com_thrd[j].high =
1772 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1773 req->com_thrd[j].high |=
1774 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1775 HCLGE_RX_PRIV_EN_B);
1776 req->com_thrd[j].low =
1777 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1778 req->com_thrd[j].low |=
1779 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1780 HCLGE_RX_PRIV_EN_B);
1781 }
1782 }
1783
1784 /* Send 2 descriptors at one time */
1785 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1786 if (ret) {
1787 dev_err(&hdev->pdev->dev,
1788 "common threshold config cmd failed %d\n", ret);
1789 return ret;
1790 }
1791 return 0;
1792}
1793
acf61ecd
YL		 1794static int hclge_common_wl_config(struct hclge_dev *hdev,
1795 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1796{
acf61ecd 1797 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1798 struct hclge_rx_com_wl *req;
1799 struct hclge_desc desc;
1800 int ret;
1801
1802 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1803
1804 req = (struct hclge_rx_com_wl *)desc.data;
1805 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1806 req->com_wl.high |=
1807 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1808 HCLGE_RX_PRIV_EN_B);
1809
1810 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1811 req->com_wl.low |=
1812 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1813 HCLGE_RX_PRIV_EN_B);
1814
1815 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1816 if (ret) {
1817 dev_err(&hdev->pdev->dev,
1818 "common waterline config cmd failed %d\n", ret);
1819 return ret;
1820 }
1821
1822 return 0;
1823}
1824
1825int hclge_buffer_alloc(struct hclge_dev *hdev)
1826{
acf61ecd 1827 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1828 int ret;
1829
acf61ecd
YL		 1830 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1831 if (!pkt_buf)
46a3df9f
S		 1832 return -ENOMEM;
1833
acf61ecd 1834 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1835 if (ret) {
1836 dev_err(&hdev->pdev->dev,
1837 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1838 goto out;
9ffe79a9
YL		 1839 }
1840
acf61ecd 1841 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1842 if (ret) {
1843 dev_err(&hdev->pdev->dev,
1844 "could not alloc tx buffers %d\n", ret);
acf61ecd 1845 goto out;
46a3df9f
S		 1846 }
1847
acf61ecd 1848 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1849 if (ret) {
1850 dev_err(&hdev->pdev->dev,
1851 "could not calc rx priv buffer size for all TCs %d\n",
1852 ret);
acf61ecd 1853 goto out;
46a3df9f
S		 1854 }
1855
acf61ecd 1856 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1857 if (ret) {
1858 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1859 ret);
acf61ecd 1860 goto out;
46a3df9f
S		 1861 }
1862
2daf4a65 1863 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1864 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1865 if (ret) {
1866 dev_err(&hdev->pdev->dev,
1867 "could not configure rx private waterline %d\n",
1868 ret);
acf61ecd 1869 goto out;
2daf4a65 1870 }
46a3df9f 1871
acf61ecd 1872 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1873 if (ret) {
1874 dev_err(&hdev->pdev->dev,
1875 "could not configure common threshold %d\n",
1876 ret);
acf61ecd 1877 goto out;
2daf4a65 1878 }
46a3df9f
S		 1879 }
1880
acf61ecd
YL		 1881 ret = hclge_common_wl_config(hdev, pkt_buf);
1882 if (ret)
46a3df9f
S		 1883 dev_err(&hdev->pdev->dev,
1884 "could not configure common waterline %d\n", ret);
46a3df9f 1885
acf61ecd
YL		 1886out:
1887 kfree(pkt_buf);
1888 return ret;
46a3df9f
S		 1889}
1890
1891static int hclge_init_roce_base_info(struct hclge_vport *vport)
1892{
1893 struct hnae3_handle *roce = &vport->roce;
1894 struct hnae3_handle *nic = &vport->nic;
1895
1896 roce->rinfo.num_vectors = vport->back->num_roce_msix;
1897
1898 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1899 vport->back->num_msi_left == 0)
1900 return -EINVAL;
1901
1902 roce->rinfo.base_vector = vport->back->roce_base_vector;
1903
1904 roce->rinfo.netdev = nic->kinfo.netdev;
1905 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1906
1907 roce->pdev = nic->pdev;
1908 roce->ae_algo = nic->ae_algo;
1909 roce->numa_node_mask = nic->numa_node_mask;
1910
1911 return 0;
1912}
1913
1914static int hclge_init_msix(struct hclge_dev *hdev)
1915{
1916 struct pci_dev *pdev = hdev->pdev;
1917 int ret, i;
1918
1919 hdev->msix_entries = devm_kcalloc(&pdev->dev, hdev->num_msi,
1920 sizeof(struct msix_entry),
1921 GFP_KERNEL);
1922 if (!hdev->msix_entries)
1923 return -ENOMEM;
1924
1925 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1926 sizeof(u16), GFP_KERNEL);
1927 if (!hdev->vector_status)
1928 return -ENOMEM;
1929
1930 for (i = 0; i < hdev->num_msi; i++) {
1931 hdev->msix_entries[i].entry = i;
1932 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1933 }
1934
1935 hdev->num_msi_left = hdev->num_msi;
1936 hdev->base_msi_vector = hdev->pdev->irq;
1937 hdev->roce_base_vector = hdev->base_msi_vector +
1938 HCLGE_ROCE_VECTOR_OFFSET;
1939
1940 ret = pci_enable_msix_range(hdev->pdev, hdev->msix_entries,
1941 hdev->num_msi, hdev->num_msi);
1942 if (ret < 0) {
1943 dev_info(&hdev->pdev->dev,
1944 "MSI-X vector alloc failed: %d\n", ret);
1945 return ret;
1946 }
1947
1948 return 0;
1949}
1950
1951static int hclge_init_msi(struct hclge_dev *hdev)
1952{
1953 struct pci_dev *pdev = hdev->pdev;
1954 int vectors;
1955 int i;
1956
1957 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1958 sizeof(u16), GFP_KERNEL);
1959 if (!hdev->vector_status)
1960 return -ENOMEM;
1961
1962 for (i = 0; i < hdev->num_msi; i++)
1963 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1964
1965 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, PCI_IRQ_MSI);
1966 if (vectors < 0) {
1967 dev_err(&pdev->dev, "MSI vectors enable failed %d\n", vectors);
1968 return -EINVAL;
1969 }
1970 hdev->num_msi = vectors;
1971 hdev->num_msi_left = vectors;
1972 hdev->base_msi_vector = pdev->irq;
1973 hdev->roce_base_vector = hdev->base_msi_vector +
1974 HCLGE_ROCE_VECTOR_OFFSET;
1975
1976 return 0;
1977}
1978
1979static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
1980{
1981 struct hclge_mac *mac = &hdev->hw.mac;
1982
1983 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
1984 mac->duplex = (u8)duplex;
1985 else
1986 mac->duplex = HCLGE_MAC_FULL;
1987
1988 mac->speed = speed;
1989}
1990
1991int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1992{
1993 struct hclge_config_mac_speed_dup *req;
1994 struct hclge_desc desc;
1995 int ret;
1996
1997 req = (struct hclge_config_mac_speed_dup *)desc.data;
1998
1999 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2000
2001 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2002
2003 switch (speed) {
2004 case HCLGE_MAC_SPEED_10M:
2005 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2006 HCLGE_CFG_SPEED_S, 6);
2007 break;
2008 case HCLGE_MAC_SPEED_100M:
2009 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2010 HCLGE_CFG_SPEED_S, 7);
2011 break;
2012 case HCLGE_MAC_SPEED_1G:
2013 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2014 HCLGE_CFG_SPEED_S, 0);
2015 break;
2016 case HCLGE_MAC_SPEED_10G:
2017 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2018 HCLGE_CFG_SPEED_S, 1);
2019 break;
2020 case HCLGE_MAC_SPEED_25G:
2021 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2022 HCLGE_CFG_SPEED_S, 2);
2023 break;
2024 case HCLGE_MAC_SPEED_40G:
2025 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2026 HCLGE_CFG_SPEED_S, 3);
2027 break;
2028 case HCLGE_MAC_SPEED_50G:
2029 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2030 HCLGE_CFG_SPEED_S, 4);
2031 break;
2032 case HCLGE_MAC_SPEED_100G:
2033 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2034 HCLGE_CFG_SPEED_S, 5);
2035 break;
2036 default:
d7629e74 2037 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2038 return -EINVAL;
2039 }
2040
2041 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2042 1);
2043
2044 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2045 if (ret) {
2046 dev_err(&hdev->pdev->dev,
2047 "mac speed/duplex config cmd failed %d.\n", ret);
2048 return ret;
2049 }
2050
2051 hclge_check_speed_dup(hdev, duplex, speed);
2052
2053 return 0;
2054}
2055
2056static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2057 u8 duplex)
2058{
2059 struct hclge_vport *vport = hclge_get_vport(handle);
2060 struct hclge_dev *hdev = vport->back;
2061
2062 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2063}
2064
2065static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2066 u8 *duplex)
2067{
2068 struct hclge_query_an_speed_dup *req;
2069 struct hclge_desc desc;
2070 int speed_tmp;
2071 int ret;
2072
2073 req = (struct hclge_query_an_speed_dup *)desc.data;
2074
2075 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2076 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2077 if (ret) {
2078 dev_err(&hdev->pdev->dev,
2079 "mac speed/autoneg/duplex query cmd failed %d\n",
2080 ret);
2081 return ret;
2082 }
2083
2084 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2085 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2086 HCLGE_QUERY_SPEED_S);
2087
2088 ret = hclge_parse_speed(speed_tmp, speed);
2089 if (ret) {
2090 dev_err(&hdev->pdev->dev,
2091 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2092 return -EIO;
2093 }
2094
2095 return 0;
2096}
2097
2098static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2099{
2100 struct hclge_mac *mac = &hdev->hw.mac;
2101 struct hclge_query_an_speed_dup *req;
2102 struct hclge_desc desc;
2103 int ret;
2104
2105 req = (struct hclge_query_an_speed_dup *)desc.data;
2106
2107 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2108 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2109 if (ret) {
2110 dev_err(&hdev->pdev->dev,
2111 "autoneg result query cmd failed %d.\n", ret);
2112 return ret;
2113 }
2114
2115 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2116
2117 return 0;
2118}
2119
2120static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2121{
2122 struct hclge_config_auto_neg *req;
2123 struct hclge_desc desc;
2124 int ret;
2125
2126 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2127
2128 req = (struct hclge_config_auto_neg *)desc.data;
2129 hnae_set_bit(req->cfg_an_cmd_flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2130
2131 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2132 if (ret) {
2133 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2134 ret);
2135 return ret;
2136 }
2137
2138 return 0;
2139}
2140
2141static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2142{
2143 struct hclge_vport *vport = hclge_get_vport(handle);
2144 struct hclge_dev *hdev = vport->back;
2145
2146 return hclge_set_autoneg_en(hdev, enable);
2147}
2148
2149static int hclge_get_autoneg(struct hnae3_handle *handle)
2150{
2151 struct hclge_vport *vport = hclge_get_vport(handle);
2152 struct hclge_dev *hdev = vport->back;
2153
2154 hclge_query_autoneg_result(hdev);
2155
2156 return hdev->hw.mac.autoneg;
2157}
2158
2159static int hclge_mac_init(struct hclge_dev *hdev)
2160{
2161 struct hclge_mac *mac = &hdev->hw.mac;
2162 int ret;
2163
2164 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2165 if (ret) {
2166 dev_err(&hdev->pdev->dev,
2167 "Config mac speed dup fail ret=%d\n", ret);
2168 return ret;
2169 }
2170
2171 mac->link = 0;
2172
2173 ret = hclge_mac_mdio_config(hdev);
2174 if (ret) {
2175 dev_warn(&hdev->pdev->dev,
2176 "mdio config fail ret=%d\n", ret);
2177 return ret;
2178 }
2179
2180 /* Initialize the MTA table work mode */
2181 hdev->accept_mta_mc = true;
2182 hdev->enable_mta = true;
2183 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2184
2185 ret = hclge_set_mta_filter_mode(hdev,
2186 hdev->mta_mac_sel_type,
2187 hdev->enable_mta);
2188 if (ret) {
2189 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2190 ret);
2191 return ret;
2192 }
2193
2194 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2195}
2196
2197static void hclge_task_schedule(struct hclge_dev *hdev)
2198{
2199 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2200 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2201 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2202 (void)schedule_work(&hdev->service_task);
2203}
2204
2205static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2206{
2207 struct hclge_link_status *req;
2208 struct hclge_desc desc;
2209 int link_status;
2210 int ret;
2211
2212 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2213 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2214 if (ret) {
2215 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2216 ret);
2217 return ret;
2218 }
2219
2220 req = (struct hclge_link_status *)desc.data;
2221 link_status = req->status & HCLGE_LINK_STATUS;
2222
2223 return !!link_status;
2224}
2225
2226static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2227{
2228 int mac_state;
2229 int link_stat;
2230
2231 mac_state = hclge_get_mac_link_status(hdev);
2232
2233 if (hdev->hw.mac.phydev) {
2234 if (!genphy_read_status(hdev->hw.mac.phydev))
2235 link_stat = mac_state &
2236 hdev->hw.mac.phydev->link;
2237 else
2238 link_stat = 0;
2239
2240 } else {
2241 link_stat = mac_state;
2242 }
2243
2244 return !!link_stat;
2245}
2246
2247static void hclge_update_link_status(struct hclge_dev *hdev)
2248{
2249 struct hnae3_client *client = hdev->nic_client;
2250 struct hnae3_handle *handle;
2251 int state;
2252 int i;
2253
2254 if (!client)
2255 return;
2256 state = hclge_get_mac_phy_link(hdev);
2257 if (state != hdev->hw.mac.link) {
2258 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2259 handle = &hdev->vport[i].nic;
2260 client->ops->link_status_change(handle, state);
2261 }
2262 hdev->hw.mac.link = state;
2263 }
2264}
2265
2266static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2267{
2268 struct hclge_mac mac = hdev->hw.mac;
2269 u8 duplex;
2270 int speed;
2271 int ret;
2272
2273 /* get the speed and duplex as autoneg'result from mac cmd when phy
2274 * doesn't exit.
2275 */
2276 if (mac.phydev)
2277 return 0;
2278
2279 /* update mac->antoneg. */
2280 ret = hclge_query_autoneg_result(hdev);
2281 if (ret) {
2282 dev_err(&hdev->pdev->dev,
2283 "autoneg result query failed %d\n", ret);
2284 return ret;
2285 }
2286
2287 if (!mac.autoneg)
2288 return 0;
2289
2290 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2291 if (ret) {
2292 dev_err(&hdev->pdev->dev,
2293 "mac autoneg/speed/duplex query failed %d\n", ret);
2294 return ret;
2295 }
2296
2297 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2298 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2299 if (ret) {
2300 dev_err(&hdev->pdev->dev,
2301 "mac speed/duplex config failed %d\n", ret);
2302 return ret;
2303 }
2304 }
2305
2306 return 0;
2307}
2308
2309static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2310{
2311 struct hclge_vport *vport = hclge_get_vport(handle);
2312 struct hclge_dev *hdev = vport->back;
2313
2314 return hclge_update_speed_duplex(hdev);
2315}
2316
2317static int hclge_get_status(struct hnae3_handle *handle)
2318{
2319 struct hclge_vport *vport = hclge_get_vport(handle);
2320 struct hclge_dev *hdev = vport->back;
2321
2322 hclge_update_link_status(hdev);
2323
2324 return hdev->hw.mac.link;
2325}
2326
2327static void hclge_service_timer(unsigned long data)
2328{
2329 struct hclge_dev *hdev = (struct hclge_dev *)data;
2330 (void)mod_timer(&hdev->service_timer, jiffies + HZ);
2331
2332 hclge_task_schedule(hdev);
2333}
2334
2335static void hclge_service_complete(struct hclge_dev *hdev)
2336{
2337 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2338
2339 /* Flush memory before next watchdog */
2340 smp_mb__before_atomic();
2341 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2342}
2343
2344static void hclge_service_task(struct work_struct *work)
2345{
2346 struct hclge_dev *hdev =
2347 container_of(work, struct hclge_dev, service_task);
2348
2349 hclge_update_speed_duplex(hdev);
2350 hclge_update_link_status(hdev);
2351 hclge_update_stats_for_all(hdev);
2352 hclge_service_complete(hdev);
2353}
2354
2355static void hclge_disable_sriov(struct hclge_dev *hdev)
2356{
2a32ca13
AB		 2357 /* If our VFs are assigned we cannot shut down SR-IOV
2358 * without causing issues, so just leave the hardware
2359 * available but disabled
2360 */
2361 if (pci_vfs_assigned(hdev->pdev)) {
2362 dev_warn(&hdev->pdev->dev,
2363 "disabling driver while VFs are assigned\n");
2364 return;
2365 }
46a3df9f 2366
2a32ca13 2367 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2368}
2369
2370struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2371{
2372 /* VF handle has no client */
2373 if (!handle->client)
2374 return container_of(handle, struct hclge_vport, nic);
2375 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2376 return container_of(handle, struct hclge_vport, roce);
2377 else
2378 return container_of(handle, struct hclge_vport, nic);
2379}
2380
2381static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2382 struct hnae3_vector_info *vector_info)
2383{
2384 struct hclge_vport *vport = hclge_get_vport(handle);
2385 struct hnae3_vector_info *vector = vector_info;
2386 struct hclge_dev *hdev = vport->back;
2387 int alloc = 0;
2388 int i, j;
2389
2390 vector_num = min(hdev->num_msi_left, vector_num);
2391
2392 for (j = 0; j < vector_num; j++) {
2393 for (i = 1; i < hdev->num_msi; i++) {
2394 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2395 vector->vector = pci_irq_vector(hdev->pdev, i);
2396 vector->io_addr = hdev->hw.io_base +
2397 HCLGE_VECTOR_REG_BASE +
2398 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2399 vport->vport_id *
2400 HCLGE_VECTOR_VF_OFFSET;
2401 hdev->vector_status[i] = vport->vport_id;
2402
2403 vector++;
2404 alloc++;
2405
2406 break;
2407 }
2408 }
2409 }
2410 hdev->num_msi_left -= alloc;
2411 hdev->num_msi_used += alloc;
2412
2413 return alloc;
2414}
2415
2416static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2417{
2418 int i;
2419
2420 for (i = 0; i < hdev->num_msi; i++) {
2421 if (hdev->msix_entries) {
2422 if (vector == hdev->msix_entries[i].vector)
2423 return i;
2424 } else {
2425 if (vector == (hdev->base_msi_vector + i))
2426 return i;
2427 }
2428 }
2429 return -EINVAL;
2430}
2431
2432static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2433{
2434 return HCLGE_RSS_KEY_SIZE;
2435}
2436
2437static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2438{
2439 return HCLGE_RSS_IND_TBL_SIZE;
2440}
2441
2442static int hclge_get_rss_algo(struct hclge_dev *hdev)
2443{
2444 struct hclge_rss_config *req;
2445 struct hclge_desc desc;
2446 int rss_hash_algo;
2447 int ret;
2448
2449 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2450
2451 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2452 if (ret) {
2453 dev_err(&hdev->pdev->dev,
2454 "Get link status error, status =%d\n", ret);
2455 return ret;
2456 }
2457
2458 req = (struct hclge_rss_config *)desc.data;
2459 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2460
2461 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2462 return ETH_RSS_HASH_TOP;
2463
2464 return -EINVAL;
2465}
2466
2467static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2468 const u8 hfunc, const u8 *key)
2469{
2470 struct hclge_rss_config *req;
2471 struct hclge_desc desc;
2472 int key_offset;
2473 int key_size;
2474 int ret;
2475
2476 req = (struct hclge_rss_config *)desc.data;
2477
2478 for (key_offset = 0; key_offset < 3; key_offset++) {
2479 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2480 false);
2481
2482 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2483 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2484
2485 if (key_offset == 2)
2486 key_size =
2487 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2488 else
2489 key_size = HCLGE_RSS_HASH_KEY_NUM;
2490
2491 memcpy(req->hash_key,
2492 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2493
2494 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2495 if (ret) {
2496 dev_err(&hdev->pdev->dev,
2497 "Configure RSS config fail, status = %d\n",
2498 ret);
2499 return ret;
2500 }
2501 }
2502 return 0;
2503}
2504
2505static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2506{
2507 struct hclge_rss_indirection_table *req;
2508 struct hclge_desc desc;
2509 int i, j;
2510 int ret;
2511
2512 req = (struct hclge_rss_indirection_table *)desc.data;
2513
2514 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2515 hclge_cmd_setup_basic_desc
2516 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2517
2518 req->start_table_index = i * HCLGE_RSS_CFG_TBL_SIZE;
2519 req->rss_set_bitmap = HCLGE_RSS_SET_BITMAP_MSK;
2520
2521 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2522 req->rss_result[j] =
2523 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2524
2525 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2526 if (ret) {
2527 dev_err(&hdev->pdev->dev,
2528 "Configure rss indir table fail,status = %d\n",
2529 ret);
2530 return ret;
2531 }
2532 }
2533 return 0;
2534}
2535
2536static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2537 u16 *tc_size, u16 *tc_offset)
2538{
2539 struct hclge_rss_tc_mode *req;
2540 struct hclge_desc desc;
2541 int ret;
2542 int i;
2543
2544 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
2545 req = (struct hclge_rss_tc_mode *)desc.data;
2546
2547 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2548 hnae_set_bit(req->rss_tc_mode[i], HCLGE_RSS_TC_VALID_B,
2549 (tc_valid[i] & 0x1));
2550 hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_SIZE_M,
2551 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2552 hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_OFFSET_M,
2553 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
2554 }
2555
2556 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2557 if (ret) {
2558 dev_err(&hdev->pdev->dev,
2559 "Configure rss tc mode fail, status = %d\n", ret);
2560 return ret;
2561 }
2562
2563 return 0;
2564}
2565
2566static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2567{
2568#define HCLGE_RSS_INPUT_TUPLE_OTHER 0xf
2569#define HCLGE_RSS_INPUT_TUPLE_SCTP 0x1f
2570 struct hclge_rss_input_tuple *req;
2571 struct hclge_desc desc;
2572 int ret;
2573
2574 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2575
2576 req = (struct hclge_rss_input_tuple *)desc.data;
2577 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2578 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2579 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2580 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2581 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2582 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2583 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2584 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2585 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2586 if (ret) {
2587 dev_err(&hdev->pdev->dev,
2588 "Configure rss input fail, status = %d\n", ret);
2589 return ret;
2590 }
2591
2592 return 0;
2593}
2594
2595static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2596 u8 *key, u8 *hfunc)
2597{
2598 struct hclge_vport *vport = hclge_get_vport(handle);
2599 struct hclge_dev *hdev = vport->back;
2600 int i;
2601
2602 /* Get hash algorithm */
2603 if (hfunc)
2604 *hfunc = hclge_get_rss_algo(hdev);
2605
2606 /* Get the RSS Key required by the user */
2607 if (key)
2608 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2609
2610 /* Get indirect table */
2611 if (indir)
2612 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2613 indir[i] = vport->rss_indirection_tbl[i];
2614
2615 return 0;
2616}
2617
2618static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2619 const u8 *key, const u8 hfunc)
2620{
2621 struct hclge_vport *vport = hclge_get_vport(handle);
2622 struct hclge_dev *hdev = vport->back;
2623 u8 hash_algo;
2624 int ret, i;
2625
2626 /* Set the RSS Hash Key if specififed by the user */
2627 if (key) {
2628 /* Update the shadow RSS key with user specified qids */
2629 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2630
2631 if (hfunc == ETH_RSS_HASH_TOP ||
2632 hfunc == ETH_RSS_HASH_NO_CHANGE)
2633 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2634 else
2635 return -EINVAL;
2636 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2637 if (ret)
2638 return ret;
2639 }
2640
2641 /* Update the shadow RSS table with user specified qids */
2642 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2643 vport->rss_indirection_tbl[i] = indir[i];
2644
2645 /* Update the hardware */
2646 ret = hclge_set_rss_indir_table(hdev, indir);
2647 return ret;
2648}
2649
2650static int hclge_get_tc_size(struct hnae3_handle *handle)
2651{
2652 struct hclge_vport *vport = hclge_get_vport(handle);
2653 struct hclge_dev *hdev = vport->back;
2654
2655 return hdev->rss_size_max;
2656}
2657
2658static int hclge_rss_init_hw(struct hclge_dev *hdev)
2659{
2660 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2661 struct hclge_vport *vport = hdev->vport;
2662 u16 tc_offset[HCLGE_MAX_TC_NUM];
2663 u8 rss_key[HCLGE_RSS_KEY_SIZE];
2664 u16 tc_valid[HCLGE_MAX_TC_NUM];
2665 u16 tc_size[HCLGE_MAX_TC_NUM];
2666 u32 *rss_indir = NULL;
68ece54e 2667 u16 rss_size = 0, roundup_size;
46a3df9f
S		 2668 const u8 *key;
2669 int i, ret, j;
2670
2671 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
2672 if (!rss_indir)
2673 return -ENOMEM;
2674
2675 /* Get default RSS key */
2676 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
2677
2678 /* Initialize RSS indirect table for each vport */
2679 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
2680 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
2681 vport[j].rss_indirection_tbl[i] =
68ece54e
YL		 2682 i % vport[j].alloc_rss_size;
2683
2684 /* vport 0 is for PF */
2685 if (j != 0)
2686 continue;
2687
2688 rss_size = vport[j].alloc_rss_size;
46a3df9f
S		 2689 rss_indir[i] = vport[j].rss_indirection_tbl[i];
2690 }
2691 }
2692 ret = hclge_set_rss_indir_table(hdev, rss_indir);
2693 if (ret)
2694 goto err;
2695
2696 key = rss_key;
2697 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
2698 if (ret)
2699 goto err;
2700
2701 ret = hclge_set_rss_input_tuple(hdev);
2702 if (ret)
2703 goto err;
2704
68ece54e
YL		 2705 /* Each TC have the same queue size, and tc_size set to hardware is
2706 * the log2 of roundup power of two of rss_size, the acutal queue
2707 * size is limited by indirection table.
2708 */
2709 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
2710 dev_err(&hdev->pdev->dev,
2711 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
2712 rss_size);
2713 return -EINVAL;
2714 }
2715
2716 roundup_size = roundup_pow_of_two(rss_size);
2717 roundup_size = ilog2(roundup_size);
2718
46a3df9f 2719 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 2720 tc_valid[i] = 0;
46a3df9f 2721
68ece54e
YL		 2722 if (!(hdev->hw_tc_map & BIT(i)))
2723 continue;
2724
2725 tc_valid[i] = 1;
2726 tc_size[i] = roundup_size;
2727 tc_offset[i] = rss_size * i;
46a3df9f 2728 }
68ece54e 2729
46a3df9f
S		 2730 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
2731
2732err:
2733 kfree(rss_indir);
2734
2735 return ret;
2736}
2737
2738int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
2739 struct hnae3_ring_chain_node *ring_chain)
2740{
2741 struct hclge_dev *hdev = vport->back;
2742 struct hclge_ctrl_vector_chain *req;
2743 struct hnae3_ring_chain_node *node;
2744 struct hclge_desc desc;
2745 int ret;
2746 int i;
2747
2748 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
2749
2750 req = (struct hclge_ctrl_vector_chain *)desc.data;
2751 req->int_vector_id = vector_id;
2752
2753 i = 0;
2754 for (node = ring_chain; node; node = node->next) {
2755 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,
2756 HCLGE_INT_TYPE_S,
2757 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2758 hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2759 HCLGE_TQP_ID_S, node->tqp_index);
0305b443
L		 2760 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
2761 HCLGE_INT_GL_IDX_S,
2762 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f 2763 req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
0305b443 2764 req->vfid = vport->vport_id;
46a3df9f
S		 2765
2766 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2767 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
2768
2769 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2770 if (ret) {
2771 dev_err(&hdev->pdev->dev,
2772 "Map TQP fail, status is %d.\n",
2773 ret);
2774 return ret;
2775 }
2776 i = 0;
2777
2778 hclge_cmd_setup_basic_desc(&desc,
2779 HCLGE_OPC_ADD_RING_TO_VECTOR,
2780 false);
2781 req->int_vector_id = vector_id;
2782 }
2783 }
2784
2785 if (i > 0) {
2786 req->int_cause_num = i;
2787
2788 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2789 if (ret) {
2790 dev_err(&hdev->pdev->dev,
2791 "Map TQP fail, status is %d.\n", ret);
2792 return ret;
2793 }
2794 }
2795
2796 return 0;
2797}
2798
2799int hclge_map_handle_ring_to_vector(struct hnae3_handle *handle,
2800 int vector,
2801 struct hnae3_ring_chain_node *ring_chain)
2802{
2803 struct hclge_vport *vport = hclge_get_vport(handle);
2804 struct hclge_dev *hdev = vport->back;
2805 int vector_id;
2806
2807 vector_id = hclge_get_vector_index(hdev, vector);
2808 if (vector_id < 0) {
2809 dev_err(&hdev->pdev->dev,
2810 "Get vector index fail. ret =%d\n", vector_id);
2811 return vector_id;
2812 }
2813
2814 return hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);
2815}
2816
2817static int hclge_unmap_ring_from_vector(
2818 struct hnae3_handle *handle, int vector,
2819 struct hnae3_ring_chain_node *ring_chain)
2820{
2821 struct hclge_vport *vport = hclge_get_vport(handle);
2822 struct hclge_dev *hdev = vport->back;
2823 struct hclge_ctrl_vector_chain *req;
2824 struct hnae3_ring_chain_node *node;
2825 struct hclge_desc desc;
2826 int i, vector_id;
2827 int ret;
2828
2829 vector_id = hclge_get_vector_index(hdev, vector);
2830 if (vector_id < 0) {
2831 dev_err(&handle->pdev->dev,
2832 "Get vector index fail. ret =%d\n", vector_id);
2833 return vector_id;
2834 }
2835
2836 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);
2837
2838 req = (struct hclge_ctrl_vector_chain *)desc.data;
2839 req->int_vector_id = vector_id;
2840
2841 i = 0;
2842 for (node = ring_chain; node; node = node->next) {
2843 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,
2844 HCLGE_INT_TYPE_S,
2845 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2846 hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2847 HCLGE_TQP_ID_S, node->tqp_index);
0305b443
L		 2848 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
2849 HCLGE_INT_GL_IDX_S,
2850 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f
S		 2851
2852 req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
0305b443 2853 req->vfid = vport->vport_id;
46a3df9f
S		 2854
2855 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2856 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
2857
2858 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2859 if (ret) {
2860 dev_err(&hdev->pdev->dev,
2861 "Unmap TQP fail, status is %d.\n",
2862 ret);
2863 return ret;
2864 }
2865 i = 0;
2866 hclge_cmd_setup_basic_desc(&desc,
c5b1b975 2867 HCLGE_OPC_DEL_RING_TO_VECTOR,
46a3df9f
S		 2868 false);
2869 req->int_vector_id = vector_id;
2870 }
2871 }
2872
2873 if (i > 0) {
2874 req->int_cause_num = i;
2875
2876 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2877 if (ret) {
2878 dev_err(&hdev->pdev->dev,
2879 "Unmap TQP fail, status is %d.\n", ret);
2880 return ret;
2881 }
2882 }
2883
2884 return 0;
2885}
2886
2887int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
2888 struct hclge_promisc_param *param)
2889{
2890 struct hclge_promisc_cfg *req;
2891 struct hclge_desc desc;
2892 int ret;
2893
2894 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
2895
2896 req = (struct hclge_promisc_cfg *)desc.data;
2897 req->vf_id = param->vf_id;
2898 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
2899
2900 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2901 if (ret) {
2902 dev_err(&hdev->pdev->dev,
2903 "Set promisc mode fail, status is %d.\n", ret);
2904 return ret;
2905 }
2906 return 0;
2907}
2908
2909void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
2910 bool en_mc, bool en_bc, int vport_id)
2911{
2912 if (!param)
2913 return;
2914
2915 memset(param, 0, sizeof(struct hclge_promisc_param));
2916 if (en_uc)
2917 param->enable = HCLGE_PROMISC_EN_UC;
2918 if (en_mc)
2919 param->enable |= HCLGE_PROMISC_EN_MC;
2920 if (en_bc)
2921 param->enable |= HCLGE_PROMISC_EN_BC;
2922 param->vf_id = vport_id;
2923}
2924
2925static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
2926{
2927 struct hclge_vport *vport = hclge_get_vport(handle);
2928 struct hclge_dev *hdev = vport->back;
2929 struct hclge_promisc_param param;
2930
2931 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
2932 hclge_cmd_set_promisc_mode(hdev, &param);
2933}
2934
2935static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
2936{
2937 struct hclge_desc desc;
2938 struct hclge_config_mac_mode *req =
2939 (struct hclge_config_mac_mode *)desc.data;
2940 int ret;
2941
2942 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
2943 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_TX_EN_B, enable);
2944 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_RX_EN_B, enable);
2945 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_PAD_TX_B, enable);
2946 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_PAD_RX_B, enable);
2947 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_1588_TX_B, 0);
2948 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_1588_RX_B, 0);
2949 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_APP_LP_B, 0);
2950 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_LINE_LP_B, 0);
2951 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_FCS_TX_B, enable);
2952 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_RX_FCS_B, enable);
2953 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2954 HCLGE_MAC_RX_FCS_STRIP_B, enable);
2955 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2956 HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
2957 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2958 HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
2959 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2960 HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
2961
2962 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2963 if (ret)
2964 dev_err(&hdev->pdev->dev,
2965 "mac enable fail, ret =%d.\n", ret);
2966}
2967
2968static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
2969 int stream_id, bool enable)
2970{
2971 struct hclge_desc desc;
2972 struct hclge_cfg_com_tqp_queue *req =
2973 (struct hclge_cfg_com_tqp_queue *)desc.data;
2974 int ret;
2975
2976 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
2977 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
2978 req->stream_id = cpu_to_le16(stream_id);
2979 req->enable |= enable << HCLGE_TQP_ENABLE_B;
2980
2981 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2982 if (ret)
2983 dev_err(&hdev->pdev->dev,
2984 "Tqp enable fail, status =%d.\n", ret);
2985 return ret;
2986}
2987
2988static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
2989{
2990 struct hclge_vport *vport = hclge_get_vport(handle);
2991 struct hnae3_queue *queue;
2992 struct hclge_tqp *tqp;
2993 int i;
2994
2995 for (i = 0; i < vport->alloc_tqps; i++) {
2996 queue = handle->kinfo.tqp[i];
2997 tqp = container_of(queue, struct hclge_tqp, q);
2998 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
2999 }
3000}
3001
3002static int hclge_ae_start(struct hnae3_handle *handle)
3003{
3004 struct hclge_vport *vport = hclge_get_vport(handle);
3005 struct hclge_dev *hdev = vport->back;
3006 int i, queue_id, ret;
3007
3008 for (i = 0; i < vport->alloc_tqps; i++) {
3009 /* todo clear interrupt */
3010 /* ring enable */
3011 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3012 if (queue_id < 0) {
3013 dev_warn(&hdev->pdev->dev,
3014 "Get invalid queue id, ignore it\n");
3015 continue;
3016 }
3017
3018 hclge_tqp_enable(hdev, queue_id, 0, true);
3019 }
3020 /* mac enable */
3021 hclge_cfg_mac_mode(hdev, true);
3022 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3023 (void)mod_timer(&hdev->service_timer, jiffies + HZ);
3024
3025 ret = hclge_mac_start_phy(hdev);
3026 if (ret)
3027 return ret;
3028
3029 /* reset tqp stats */
3030 hclge_reset_tqp_stats(handle);
3031
3032 return 0;
3033}
3034
3035static void hclge_ae_stop(struct hnae3_handle *handle)
3036{
3037 struct hclge_vport *vport = hclge_get_vport(handle);
3038 struct hclge_dev *hdev = vport->back;
3039 int i, queue_id;
3040
3041 for (i = 0; i < vport->alloc_tqps; i++) {
3042 /* Ring disable */
3043 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3044 if (queue_id < 0) {
3045 dev_warn(&hdev->pdev->dev,
3046 "Get invalid queue id, ignore it\n");
3047 continue;
3048 }
3049
3050 hclge_tqp_enable(hdev, queue_id, 0, false);
3051 }
3052 /* Mac disable */
3053 hclge_cfg_mac_mode(hdev, false);
3054
3055 hclge_mac_stop_phy(hdev);
3056
3057 /* reset tqp stats */
3058 hclge_reset_tqp_stats(handle);
3059}
3060
3061static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3062 u16 cmdq_resp, u8 resp_code,
3063 enum hclge_mac_vlan_tbl_opcode op)
3064{
3065 struct hclge_dev *hdev = vport->back;
3066 int return_status = -EIO;
3067
3068 if (cmdq_resp) {
3069 dev_err(&hdev->pdev->dev,
3070 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3071 cmdq_resp);
3072 return -EIO;
3073 }
3074
3075 if (op == HCLGE_MAC_VLAN_ADD) {
3076 if ((!resp_code) || (resp_code == 1)) {
3077 return_status = 0;
3078 } else if (resp_code == 2) {
3079 return_status = -EIO;
3080 dev_err(&hdev->pdev->dev,
3081 "add mac addr failed for uc_overflow.\n");
3082 } else if (resp_code == 3) {
3083 return_status = -EIO;
3084 dev_err(&hdev->pdev->dev,
3085 "add mac addr failed for mc_overflow.\n");
3086 } else {
3087 dev_err(&hdev->pdev->dev,
3088 "add mac addr failed for undefined, code=%d.\n",
3089 resp_code);
3090 }
3091 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3092 if (!resp_code) {
3093 return_status = 0;
3094 } else if (resp_code == 1) {
3095 return_status = -EIO;
3096 dev_dbg(&hdev->pdev->dev,
3097 "remove mac addr failed for miss.\n");
3098 } else {
3099 dev_err(&hdev->pdev->dev,
3100 "remove mac addr failed for undefined, code=%d.\n",
3101 resp_code);
3102 }
3103 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3104 if (!resp_code) {
3105 return_status = 0;
3106 } else if (resp_code == 1) {
3107 return_status = -EIO;
3108 dev_dbg(&hdev->pdev->dev,
3109 "lookup mac addr failed for miss.\n");
3110 } else {
3111 dev_err(&hdev->pdev->dev,
3112 "lookup mac addr failed for undefined, code=%d.\n",
3113 resp_code);
3114 }
3115 } else {
3116 return_status = -EIO;
3117 dev_err(&hdev->pdev->dev,
3118 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3119 op);
3120 }
3121
3122 return return_status;
3123}
3124
3125static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3126{
3127 int word_num;
3128 int bit_num;
3129
3130 if (vfid > 255 || vfid < 0)
3131 return -EIO;
3132
3133 if (vfid >= 0 && vfid <= 191) {
3134 word_num = vfid / 32;
3135 bit_num = vfid % 32;
3136 if (clr)
3137 desc[1].data[word_num] &= ~(1 << bit_num);
3138 else
3139 desc[1].data[word_num] |= (1 << bit_num);
3140 } else {
3141 word_num = (vfid - 192) / 32;
3142 bit_num = vfid % 32;
3143 if (clr)
3144 desc[2].data[word_num] &= ~(1 << bit_num);
3145 else
3146 desc[2].data[word_num] |= (1 << bit_num);
3147 }
3148
3149 return 0;
3150}
3151
3152static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3153{
3154#define HCLGE_DESC_NUMBER 3
3155#define HCLGE_FUNC_NUMBER_PER_DESC 6
3156 int i, j;
3157
3158 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3159 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3160 if (desc[i].data[j])
3161 return false;
3162
3163 return true;
3164}
3165
3166static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry *new_req,
3167 const u8 *addr)
3168{
3169 const unsigned char *mac_addr = addr;
3170 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3171 (mac_addr[0]) | (mac_addr[1] << 8);
3172 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3173
3174 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3175 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3176}
3177
3178u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3179 const u8 *addr)
3180{
3181 u16 high_val = addr[1] | (addr[0] << 8);
3182 struct hclge_dev *hdev = vport->back;
3183 u32 rsh = 4 - hdev->mta_mac_sel_type;
3184 u16 ret_val = (high_val >> rsh) & 0xfff;
3185
3186 return ret_val;
3187}
3188
3189static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3190 enum hclge_mta_dmac_sel_type mta_mac_sel,
3191 bool enable)
3192{
3193 struct hclge_mta_filter_mode *req;
3194 struct hclge_desc desc;
3195 int ret;
3196
3197 req = (struct hclge_mta_filter_mode *)desc.data;
3198 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3199
3200 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3201 enable);
3202 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3203 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3204
3205 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3206 if (ret) {
3207 dev_err(&hdev->pdev->dev,
3208 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3209 ret);
3210 return ret;
3211 }
3212
3213 return 0;
3214}
3215
3216int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3217 u8 func_id,
3218 bool enable)
3219{
3220 struct hclge_cfg_func_mta_filter *req;
3221 struct hclge_desc desc;
3222 int ret;
3223
3224 req = (struct hclge_cfg_func_mta_filter *)desc.data;
3225 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3226
3227 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3228 enable);
3229 req->function_id = func_id;
3230
3231 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3232 if (ret) {
3233 dev_err(&hdev->pdev->dev,
3234 "Config func_id enable failed for cmd_send, ret =%d.\n",
3235 ret);
3236 return ret;
3237 }
3238
3239 return 0;
3240}
3241
3242static int hclge_set_mta_table_item(struct hclge_vport *vport,
3243 u16 idx,
3244 bool enable)
3245{
3246 struct hclge_dev *hdev = vport->back;
3247 struct hclge_cfg_func_mta_item *req;
3248 struct hclge_desc desc;
3249 int ret;
3250
3251 req = (struct hclge_cfg_func_mta_item *)desc.data;
3252 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3253 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3254
3255 hnae_set_field(req->item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3256 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
3257 req->item_idx = cpu_to_le16(req->item_idx);
3258
3259 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3260 if (ret) {
3261 dev_err(&hdev->pdev->dev,
3262 "Config mta table item failed for cmd_send, ret =%d.\n",
3263 ret);
3264 return ret;
3265 }
3266
3267 return 0;
3268}
3269
3270static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
3271 struct hclge_mac_vlan_tbl_entry *req)
3272{
3273 struct hclge_dev *hdev = vport->back;
3274 struct hclge_desc desc;
3275 u8 resp_code;
3276 int ret;
3277
3278 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3279
3280 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry));
3281
3282 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3283 if (ret) {
3284 dev_err(&hdev->pdev->dev,
3285 "del mac addr failed for cmd_send, ret =%d.\n",
3286 ret);
3287 return ret;
3288 }
3289 resp_code = (desc.data[0] >> 8) & 0xff;
3290
3291 return hclge_get_mac_vlan_cmd_status(vport, desc.retval, resp_code,
3292 HCLGE_MAC_VLAN_REMOVE);
3293}
3294
3295static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
3296 struct hclge_mac_vlan_tbl_entry *req,
3297 struct hclge_desc *desc,
3298 bool is_mc)
3299{
3300 struct hclge_dev *hdev = vport->back;
3301 u8 resp_code;
3302 int ret;
3303
3304 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3305 if (is_mc) {
3306 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3307 memcpy(desc[0].data,
3308 req,
3309 sizeof(struct hclge_mac_vlan_tbl_entry));
3310 hclge_cmd_setup_basic_desc(&desc[1],
3311 HCLGE_OPC_MAC_VLAN_ADD,
3312 true);
3313 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3314 hclge_cmd_setup_basic_desc(&desc[2],
3315 HCLGE_OPC_MAC_VLAN_ADD,
3316 true);
3317 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3318 } else {
3319 memcpy(desc[0].data,
3320 req,
3321 sizeof(struct hclge_mac_vlan_tbl_entry));
3322 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3323 }
3324 if (ret) {
3325 dev_err(&hdev->pdev->dev,
3326 "lookup mac addr failed for cmd_send, ret =%d.\n",
3327 ret);
3328 return ret;
3329 }
3330 resp_code = (desc[0].data[0] >> 8) & 0xff;
3331
3332 return hclge_get_mac_vlan_cmd_status(vport, desc[0].retval, resp_code,
3333 HCLGE_MAC_VLAN_LKUP);
3334}
3335
3336static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
3337 struct hclge_mac_vlan_tbl_entry *req,
3338 struct hclge_desc *mc_desc)
3339{
3340 struct hclge_dev *hdev = vport->back;
3341 int cfg_status;
3342 u8 resp_code;
3343 int ret;
3344
3345 if (!mc_desc) {
3346 struct hclge_desc desc;
3347
3348 hclge_cmd_setup_basic_desc(&desc,
3349 HCLGE_OPC_MAC_VLAN_ADD,
3350 false);
3351 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry));
3352 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3353 resp_code = (desc.data[0] >> 8) & 0xff;
3354 cfg_status = hclge_get_mac_vlan_cmd_status(vport, desc.retval,
3355 resp_code,
3356 HCLGE_MAC_VLAN_ADD);
3357 } else {
3358 mc_desc[0].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3359 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3360 mc_desc[1].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3361 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3362 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3363 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3364 memcpy(mc_desc[0].data, req,
3365 sizeof(struct hclge_mac_vlan_tbl_entry));
3366 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
3367 resp_code = (mc_desc[0].data[0] >> 8) & 0xff;
3368 cfg_status = hclge_get_mac_vlan_cmd_status(vport,
3369 mc_desc[0].retval,
3370 resp_code,
3371 HCLGE_MAC_VLAN_ADD);
3372 }
3373
3374 if (ret) {
3375 dev_err(&hdev->pdev->dev,
3376 "add mac addr failed for cmd_send, ret =%d.\n",
3377 ret);
3378 return ret;
3379 }
3380
3381 return cfg_status;
3382}
3383
3384static int hclge_add_uc_addr(struct hnae3_handle *handle,
3385 const unsigned char *addr)
3386{
3387 struct hclge_vport *vport = hclge_get_vport(handle);
3388
3389 return hclge_add_uc_addr_common(vport, addr);
3390}
3391
3392int hclge_add_uc_addr_common(struct hclge_vport *vport,
3393 const unsigned char *addr)
3394{
3395 struct hclge_dev *hdev = vport->back;
3396 struct hclge_mac_vlan_tbl_entry req;
3397 enum hclge_cmd_status status;
3398
3399 /* mac addr check */
3400 if (is_zero_ether_addr(addr) ||
3401 is_broadcast_ether_addr(addr) ||
3402 is_multicast_ether_addr(addr)) {
3403 dev_err(&hdev->pdev->dev,
3404 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3405 addr,
3406 is_zero_ether_addr(addr),
3407 is_broadcast_ether_addr(addr),
3408 is_multicast_ether_addr(addr));
3409 return -EINVAL;
3410 }
3411
3412 memset(&req, 0, sizeof(req));
3413 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3414 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3415 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
3416 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3417 hnae_set_bit(req.egress_port,
3418 HCLGE_MAC_EPORT_SW_EN_B, 0);
3419 hnae_set_bit(req.egress_port,
3420 HCLGE_MAC_EPORT_TYPE_B, 0);
3421 hnae_set_field(req.egress_port, HCLGE_MAC_EPORT_VFID_M,
3422 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
3423 hnae_set_field(req.egress_port, HCLGE_MAC_EPORT_PFID_M,
3424 HCLGE_MAC_EPORT_PFID_S, 0);
3425 req.egress_port = cpu_to_le16(req.egress_port);
3426
3427 hclge_prepare_mac_addr(&req, addr);
3428
3429 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
3430
3431 return status;
3432}
3433
3434static int hclge_rm_uc_addr(struct hnae3_handle *handle,
3435 const unsigned char *addr)
3436{
3437 struct hclge_vport *vport = hclge_get_vport(handle);
3438
3439 return hclge_rm_uc_addr_common(vport, addr);
3440}
3441
3442int hclge_rm_uc_addr_common(struct hclge_vport *vport,
3443 const unsigned char *addr)
3444{
3445 struct hclge_dev *hdev = vport->back;
3446 struct hclge_mac_vlan_tbl_entry req;
3447 enum hclge_cmd_status status;
3448
3449 /* mac addr check */
3450 if (is_zero_ether_addr(addr) ||
3451 is_broadcast_ether_addr(addr) ||
3452 is_multicast_ether_addr(addr)) {
3453 dev_dbg(&hdev->pdev->dev,
3454 "Remove mac err! invalid mac:%pM.\n",
3455 addr);
3456 return -EINVAL;
3457 }
3458
3459 memset(&req, 0, sizeof(req));
3460 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3461 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3462 hclge_prepare_mac_addr(&req, addr);
3463 status = hclge_remove_mac_vlan_tbl(vport, &req);
3464
3465 return status;
3466}
3467
3468static int hclge_add_mc_addr(struct hnae3_handle *handle,
3469 const unsigned char *addr)
3470{
3471 struct hclge_vport *vport = hclge_get_vport(handle);
3472
3473 return hclge_add_mc_addr_common(vport, addr);
3474}
3475
3476int hclge_add_mc_addr_common(struct hclge_vport *vport,
3477 const unsigned char *addr)
3478{
3479 struct hclge_dev *hdev = vport->back;
3480 struct hclge_mac_vlan_tbl_entry req;
3481 struct hclge_desc desc[3];
3482 u16 tbl_idx;
3483 int status;
3484
3485 /* mac addr check */
3486 if (!is_multicast_ether_addr(addr)) {
3487 dev_err(&hdev->pdev->dev,
3488 "Add mc mac err! invalid mac:%pM.\n",
3489 addr);
3490 return -EINVAL;
3491 }
3492 memset(&req, 0, sizeof(req));
3493 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3494 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3495 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
3496 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3497 hclge_prepare_mac_addr(&req, addr);
3498 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
3499 if (!status) {
3500 /* This mac addr exist, update VFID for it */
3501 hclge_update_desc_vfid(desc, vport->vport_id, false);
3502 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3503 } else {
3504 /* This mac addr do not exist, add new entry for it */
3505 memset(desc[0].data, 0, sizeof(desc[0].data));
3506 memset(desc[1].data, 0, sizeof(desc[0].data));
3507 memset(desc[2].data, 0, sizeof(desc[0].data));
3508 hclge_update_desc_vfid(desc, vport->vport_id, false);
3509 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3510 }
3511
3512 /* Set MTA table for this MAC address */
3513 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
3514 status = hclge_set_mta_table_item(vport, tbl_idx, true);
3515
3516 return status;
3517}
3518
3519static int hclge_rm_mc_addr(struct hnae3_handle *handle,
3520 const unsigned char *addr)
3521{
3522 struct hclge_vport *vport = hclge_get_vport(handle);
3523
3524 return hclge_rm_mc_addr_common(vport, addr);
3525}
3526
3527int hclge_rm_mc_addr_common(struct hclge_vport *vport,
3528 const unsigned char *addr)
3529{
3530 struct hclge_dev *hdev = vport->back;
3531 struct hclge_mac_vlan_tbl_entry req;
3532 enum hclge_cmd_status status;
3533 struct hclge_desc desc[3];
3534 u16 tbl_idx;
3535
3536 /* mac addr check */
3537 if (!is_multicast_ether_addr(addr)) {
3538 dev_dbg(&hdev->pdev->dev,
3539 "Remove mc mac err! invalid mac:%pM.\n",
3540 addr);
3541 return -EINVAL;
3542 }
3543
3544 memset(&req, 0, sizeof(req));
3545 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3546 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3547 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
3548 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3549 hclge_prepare_mac_addr(&req, addr);
3550 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
3551 if (!status) {
3552 /* This mac addr exist, remove this handle's VFID for it */
3553 hclge_update_desc_vfid(desc, vport->vport_id, true);
3554
3555 if (hclge_is_all_function_id_zero(desc))
3556 /* All the vfid is zero, so need to delete this entry */
3557 status = hclge_remove_mac_vlan_tbl(vport, &req);
3558 else
3559 /* Not all the vfid is zero, update the vfid */
3560 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3561
3562 } else {
3563 /* This mac addr do not exist, can't delete it */
3564 dev_err(&hdev->pdev->dev,
d7629e74 3565 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 3566 status);
3567 return -EIO;
3568 }
3569
3570 /* Set MTB table for this MAC address */
3571 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
3572 status = hclge_set_mta_table_item(vport, tbl_idx, false);
3573
3574 return status;
3575}
3576
3577static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
3578{
3579 struct hclge_vport *vport = hclge_get_vport(handle);
3580 struct hclge_dev *hdev = vport->back;
3581
3582 ether_addr_copy(p, hdev->hw.mac.mac_addr);
3583}
3584
3585static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
3586{
3587 const unsigned char *new_addr = (const unsigned char *)p;
3588 struct hclge_vport *vport = hclge_get_vport(handle);
3589 struct hclge_dev *hdev = vport->back;
3590
3591 /* mac addr check */
3592 if (is_zero_ether_addr(new_addr) ||
3593 is_broadcast_ether_addr(new_addr) ||
3594 is_multicast_ether_addr(new_addr)) {
3595 dev_err(&hdev->pdev->dev,
3596 "Change uc mac err! invalid mac:%p.\n",
3597 new_addr);
3598 return -EINVAL;
3599 }
3600
3601 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
3602
3603 if (!hclge_add_uc_addr(handle, new_addr)) {
3604 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
3605 return 0;
3606 }
3607
3608 return -EIO;
3609}
3610
3611static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
3612 bool filter_en)
3613{
3614 struct hclge_vlan_filter_ctrl *req;
3615 struct hclge_desc desc;
3616 int ret;
3617
3618 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
3619
3620 req = (struct hclge_vlan_filter_ctrl *)desc.data;
3621 req->vlan_type = vlan_type;
3622 req->vlan_fe = filter_en;
3623
3624 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3625 if (ret) {
3626 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
3627 ret);
3628 return ret;
3629 }
3630
3631 return 0;
3632}
3633
3634int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
3635 bool is_kill, u16 vlan, u8 qos, __be16 proto)
3636{
3637#define HCLGE_MAX_VF_BYTES 16
3638 struct hclge_vlan_filter_vf_cfg *req0;
3639 struct hclge_vlan_filter_vf_cfg *req1;
3640 struct hclge_desc desc[2];
3641 u8 vf_byte_val;
3642 u8 vf_byte_off;
3643 int ret;
3644
3645 hclge_cmd_setup_basic_desc(&desc[0],
3646 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
3647 hclge_cmd_setup_basic_desc(&desc[1],
3648 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
3649
3650 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3651
3652 vf_byte_off = vfid / 8;
3653 vf_byte_val = 1 << (vfid % 8);
3654
3655 req0 = (struct hclge_vlan_filter_vf_cfg *)desc[0].data;
3656 req1 = (struct hclge_vlan_filter_vf_cfg *)desc[1].data;
3657
3658 req0->vlan_id = vlan;
3659 req0->vlan_cfg = is_kill;
3660
3661 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
3662 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
3663 else
3664 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
3665
3666 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3667 if (ret) {
3668 dev_err(&hdev->pdev->dev,
3669 "Send vf vlan command fail, ret =%d.\n",
3670 ret);
3671 return ret;
3672 }
3673
3674 if (!is_kill) {
3675 if (!req0->resp_code || req0->resp_code == 1)
3676 return 0;
3677
3678 dev_err(&hdev->pdev->dev,
3679 "Add vf vlan filter fail, ret =%d.\n",
3680 req0->resp_code);
3681 } else {
3682 if (!req0->resp_code)
3683 return 0;
3684
3685 dev_err(&hdev->pdev->dev,
3686 "Kill vf vlan filter fail, ret =%d.\n",
3687 req0->resp_code);
3688 }
3689
3690 return -EIO;
3691}
3692
3693static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
3694 __be16 proto, u16 vlan_id,
3695 bool is_kill)
3696{
3697 struct hclge_vport *vport = hclge_get_vport(handle);
3698 struct hclge_dev *hdev = vport->back;
3699 struct hclge_vlan_filter_pf_cfg *req;
3700 struct hclge_desc desc;
3701 u8 vlan_offset_byte_val;
3702 u8 vlan_offset_byte;
3703 u8 vlan_offset_160;
3704 int ret;
3705
3706 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
3707
3708 vlan_offset_160 = vlan_id / 160;
3709 vlan_offset_byte = (vlan_id % 160) / 8;
3710 vlan_offset_byte_val = 1 << (vlan_id % 8);
3711
3712 req = (struct hclge_vlan_filter_pf_cfg *)desc.data;
3713 req->vlan_offset = vlan_offset_160;
3714 req->vlan_cfg = is_kill;
3715 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
3716
3717 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3718 if (ret) {
3719 dev_err(&hdev->pdev->dev,
3720 "port vlan command, send fail, ret =%d.\n",
3721 ret);
3722 return ret;
3723 }
3724
3725 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
3726 if (ret) {
3727 dev_err(&hdev->pdev->dev,
3728 "Set pf vlan filter config fail, ret =%d.\n",
3729 ret);
3730 return -EIO;
3731 }
3732
3733 return 0;
3734}
3735
3736static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
3737 u16 vlan, u8 qos, __be16 proto)
3738{
3739 struct hclge_vport *vport = hclge_get_vport(handle);
3740 struct hclge_dev *hdev = vport->back;
3741
3742 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
3743 return -EINVAL;
3744 if (proto != htons(ETH_P_8021Q))
3745 return -EPROTONOSUPPORT;
3746
3747 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
3748}
3749
3750static int hclge_init_vlan_config(struct hclge_dev *hdev)
3751{
3752#define HCLGE_VLAN_TYPE_VF_TABLE 0
3753#define HCLGE_VLAN_TYPE_PORT_TABLE 1
5e43aef8 3754 struct hnae3_handle *handle;
46a3df9f
S		 3755 int ret;
3756
3757 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
3758 true);
3759 if (ret)
3760 return ret;
3761
3762 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
3763 true);
5e43aef8
L		 3764 if (ret)
3765 return ret;
46a3df9f 3766
5e43aef8
L		 3767 handle = &hdev->vport[0].nic;
3768 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 3769}
3770
3771static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
3772{
3773 struct hclge_vport *vport = hclge_get_vport(handle);
3774 struct hclge_config_max_frm_size *req;
3775 struct hclge_dev *hdev = vport->back;
3776 struct hclge_desc desc;
3777 int ret;
3778
3779 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
3780 return -EINVAL;
3781
3782 hdev->mps = new_mtu;
3783 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
3784
3785 req = (struct hclge_config_max_frm_size *)desc.data;
3786 req->max_frm_size = cpu_to_le16(new_mtu);
3787
3788 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3789 if (ret) {
3790 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
3791 return ret;
3792 }
3793
3794 return 0;
3795}
3796
3797static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
3798 bool enable)
3799{
3800 struct hclge_reset_tqp_queue *req;
3801 struct hclge_desc desc;
3802 int ret;
3803
3804 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
3805
3806 req = (struct hclge_reset_tqp_queue *)desc.data;
3807 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
3808 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
3809
3810 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3811 if (ret) {
3812 dev_err(&hdev->pdev->dev,
3813 "Send tqp reset cmd error, status =%d\n", ret);
3814 return ret;
3815 }
3816
3817 return 0;
3818}
3819
3820static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
3821{
3822 struct hclge_reset_tqp_queue *req;
3823 struct hclge_desc desc;
3824 int ret;
3825
3826 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
3827
3828 req = (struct hclge_reset_tqp_queue *)desc.data;
3829 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
3830
3831 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3832 if (ret) {
3833 dev_err(&hdev->pdev->dev,
3834 "Get reset status error, status =%d\n", ret);
3835 return ret;
3836 }
3837
3838 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
3839}
3840
3841static void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
3842{
3843 struct hclge_vport *vport = hclge_get_vport(handle);
3844 struct hclge_dev *hdev = vport->back;
3845 int reset_try_times = 0;
3846 int reset_status;
3847 int ret;
3848
3849 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
3850 if (ret) {
3851 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
3852 return;
3853 }
3854
3855 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
3856 if (ret) {
3857 dev_warn(&hdev->pdev->dev,
3858 "Send reset tqp cmd fail, ret = %d\n", ret);
3859 return;
3860 }
3861
3862 reset_try_times = 0;
3863 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
3864 /* Wait for tqp hw reset */
3865 msleep(20);
3866 reset_status = hclge_get_reset_status(hdev, queue_id);
3867 if (reset_status)
3868 break;
3869 }
3870
3871 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
3872 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
3873 return;
3874 }
3875
3876 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
3877 if (ret) {
3878 dev_warn(&hdev->pdev->dev,
3879 "Deassert the soft reset fail, ret = %d\n", ret);
3880 return;
3881 }
3882}
3883
3884static u32 hclge_get_fw_version(struct hnae3_handle *handle)
3885{
3886 struct hclge_vport *vport = hclge_get_vport(handle);
3887 struct hclge_dev *hdev = vport->back;
3888
3889 return hdev->fw_version;
3890}
3891
3892static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
3893 u32 *rx_en, u32 *tx_en)
3894{
3895 struct hclge_vport *vport = hclge_get_vport(handle);
3896 struct hclge_dev *hdev = vport->back;
3897
3898 *auto_neg = hclge_get_autoneg(handle);
3899
3900 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
3901 *rx_en = 0;
3902 *tx_en = 0;
3903 return;
3904 }
3905
3906 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
3907 *rx_en = 1;
3908 *tx_en = 0;
3909 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
3910 *tx_en = 1;
3911 *rx_en = 0;
3912 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
3913 *rx_en = 1;
3914 *tx_en = 1;
3915 } else {
3916 *rx_en = 0;
3917 *tx_en = 0;
3918 }
3919}
3920
3921static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
3922 u8 *auto_neg, u32 *speed, u8 *duplex)
3923{
3924 struct hclge_vport *vport = hclge_get_vport(handle);
3925 struct hclge_dev *hdev = vport->back;
3926
3927 if (speed)
3928 *speed = hdev->hw.mac.speed;
3929 if (duplex)
3930 *duplex = hdev->hw.mac.duplex;
3931 if (auto_neg)
3932 *auto_neg = hdev->hw.mac.autoneg;
3933}
3934
3935static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
3936{
3937 struct hclge_vport *vport = hclge_get_vport(handle);
3938 struct hclge_dev *hdev = vport->back;
3939
3940 if (media_type)
3941 *media_type = hdev->hw.mac.media_type;
3942}
3943
3944static void hclge_get_mdix_mode(struct hnae3_handle *handle,
3945 u8 *tp_mdix_ctrl, u8 *tp_mdix)
3946{
3947 struct hclge_vport *vport = hclge_get_vport(handle);
3948 struct hclge_dev *hdev = vport->back;
3949 struct phy_device *phydev = hdev->hw.mac.phydev;
3950 int mdix_ctrl, mdix, retval, is_resolved;
3951
3952 if (!phydev) {
3953 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
3954 *tp_mdix = ETH_TP_MDI_INVALID;
3955 return;
3956 }
3957
3958 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
3959
3960 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
3961 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
3962 HCLGE_PHY_MDIX_CTRL_S);
3963
3964 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
3965 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
3966 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
3967
3968 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
3969
3970 switch (mdix_ctrl) {
3971 case 0x0:
3972 *tp_mdix_ctrl = ETH_TP_MDI;
3973 break;
3974 case 0x1:
3975 *tp_mdix_ctrl = ETH_TP_MDI_X;
3976 break;
3977 case 0x3:
3978 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
3979 break;
3980 default:
3981 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
3982 break;
3983 }
3984
3985 if (!is_resolved)
3986 *tp_mdix = ETH_TP_MDI_INVALID;
3987 else if (mdix)
3988 *tp_mdix = ETH_TP_MDI_X;
3989 else
3990 *tp_mdix = ETH_TP_MDI;
3991}
3992
3993static int hclge_init_client_instance(struct hnae3_client *client,
3994 struct hnae3_ae_dev *ae_dev)
3995{
3996 struct hclge_dev *hdev = ae_dev->priv;
3997 struct hclge_vport *vport;
3998 int i, ret;
3999
4000 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4001 vport = &hdev->vport[i];
4002
4003 switch (client->type) {
4004 case HNAE3_CLIENT_KNIC:
4005
4006 hdev->nic_client = client;
4007 vport->nic.client = client;
4008 ret = client->ops->init_instance(&vport->nic);
4009 if (ret)
4010 goto err;
4011
4012 if (hdev->roce_client &&
e92a0843 4013 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4014 struct hnae3_client *rc = hdev->roce_client;
4015
4016 ret = hclge_init_roce_base_info(vport);
4017 if (ret)
4018 goto err;
4019
4020 ret = rc->ops->init_instance(&vport->roce);
4021 if (ret)
4022 goto err;
4023 }
4024
4025 break;
4026 case HNAE3_CLIENT_UNIC:
4027 hdev->nic_client = client;
4028 vport->nic.client = client;
4029
4030 ret = client->ops->init_instance(&vport->nic);
4031 if (ret)
4032 goto err;
4033
4034 break;
4035 case HNAE3_CLIENT_ROCE:
e92a0843 4036 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4037 hdev->roce_client = client;
4038 vport->roce.client = client;
4039 }
4040
4041 if (hdev->roce_client) {
4042 ret = hclge_init_roce_base_info(vport);
4043 if (ret)
4044 goto err;
4045
4046 ret = client->ops->init_instance(&vport->roce);
4047 if (ret)
4048 goto err;
4049 }
4050 }
4051 }
4052
4053 return 0;
4054err:
4055 return ret;
4056}
4057
4058static void hclge_uninit_client_instance(struct hnae3_client *client,
4059 struct hnae3_ae_dev *ae_dev)
4060{
4061 struct hclge_dev *hdev = ae_dev->priv;
4062 struct hclge_vport *vport;
4063 int i;
4064
4065 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4066 vport = &hdev->vport[i];
4067 if (hdev->roce_client)
4068 hdev->roce_client->ops->uninit_instance(&vport->roce,
4069 0);
4070 if (client->type == HNAE3_CLIENT_ROCE)
4071 return;
4072 if (client->ops->uninit_instance)
4073 client->ops->uninit_instance(&vport->nic, 0);
4074 }
4075}
4076
4077static int hclge_pci_init(struct hclge_dev *hdev)
4078{
4079 struct pci_dev *pdev = hdev->pdev;
4080 struct hclge_hw *hw;
4081 int ret;
4082
4083 ret = pci_enable_device(pdev);
4084 if (ret) {
4085 dev_err(&pdev->dev, "failed to enable PCI device\n");
4086 goto err_no_drvdata;
4087 }
4088
4089 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4090 if (ret) {
4091 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4092 if (ret) {
4093 dev_err(&pdev->dev,
4094 "can't set consistent PCI DMA");
4095 goto err_disable_device;
4096 }
4097 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4098 }
4099
4100 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4101 if (ret) {
4102 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4103 goto err_disable_device;
4104 }
4105
4106 pci_set_master(pdev);
4107 hw = &hdev->hw;
4108 hw->back = hdev;
4109 hw->io_base = pcim_iomap(pdev, 2, 0);
4110 if (!hw->io_base) {
4111 dev_err(&pdev->dev, "Can't map configuration register space\n");
4112 ret = -ENOMEM;
4113 goto err_clr_master;
4114 }
4115
4116 return 0;
4117err_clr_master:
4118 pci_clear_master(pdev);
4119 pci_release_regions(pdev);
4120err_disable_device:
4121 pci_disable_device(pdev);
4122err_no_drvdata:
4123 pci_set_drvdata(pdev, NULL);
4124
4125 return ret;
4126}
4127
4128static void hclge_pci_uninit(struct hclge_dev *hdev)
4129{
4130 struct pci_dev *pdev = hdev->pdev;
4131
4132 if (hdev->flag & HCLGE_FLAG_USE_MSIX) {
4133 pci_disable_msix(pdev);
4134 devm_kfree(&pdev->dev, hdev->msix_entries);
4135 hdev->msix_entries = NULL;
4136 } else {
4137 pci_disable_msi(pdev);
4138 }
4139
4140 pci_clear_master(pdev);
4141 pci_release_mem_regions(pdev);
4142 pci_disable_device(pdev);
4143}
4144
4145static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4146{
4147 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 4148 struct hclge_dev *hdev;
4149 int ret;
4150
4151 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4152 if (!hdev) {
4153 ret = -ENOMEM;
4154 goto err_hclge_dev;
4155 }
4156
4157 hdev->flag |= HCLGE_FLAG_USE_MSIX;
4158 hdev->pdev = pdev;
4159 hdev->ae_dev = ae_dev;
4160 ae_dev->priv = hdev;
4161
46a3df9f
S		 4162 ret = hclge_pci_init(hdev);
4163 if (ret) {
4164 dev_err(&pdev->dev, "PCI init failed\n");
4165 goto err_pci_init;
4166 }
4167
4168 /* Command queue initialize */
4169 ret = hclge_cmd_init(hdev);
4170 if (ret)
4171 goto err_cmd_init;
4172
4173 ret = hclge_get_cap(hdev);
4174 if (ret) {
e00e2197
CIK		 4175 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4176 ret);
46a3df9f
S		 4177 return ret;
4178 }
4179
4180 ret = hclge_configure(hdev);
4181 if (ret) {
4182 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4183 return ret;
4184 }
4185
4186 if (hdev->flag & HCLGE_FLAG_USE_MSIX)
4187 ret = hclge_init_msix(hdev);
4188 else
4189 ret = hclge_init_msi(hdev);
4190 if (ret) {
4191 dev_err(&pdev->dev, "Init msix/msi error, ret = %d.\n", ret);
4192 return ret;
4193 }
4194
4195 ret = hclge_alloc_tqps(hdev);
4196 if (ret) {
4197 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4198 return ret;
4199 }
4200
4201 ret = hclge_alloc_vport(hdev);
4202 if (ret) {
4203 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4204 return ret;
4205 }
4206
4207 ret = hclge_mac_init(hdev);
4208 if (ret) {
4209 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4210 return ret;
4211 }
4212 ret = hclge_buffer_alloc(hdev);
4213 if (ret) {
4214 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4215 return ret;
4216 }
4217
4218 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4219 if (ret) {
4220 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4221 return ret;
4222 }
4223
46a3df9f
S		 4224 ret = hclge_init_vlan_config(hdev);
4225 if (ret) {
4226 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4227 return ret;
4228 }
4229
4230 ret = hclge_tm_schd_init(hdev);
4231 if (ret) {
4232 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4233 return ret;
68ece54e
YL		 4234 }
4235
4236 ret = hclge_rss_init_hw(hdev);
4237 if (ret) {
4238 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4239 return ret;
46a3df9f
S		 4240 }
4241
4242 setup_timer(&hdev->service_timer, hclge_service_timer,
4243 (unsigned long)hdev);
4244 INIT_WORK(&hdev->service_task, hclge_service_task);
4245
4246 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4247 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4248
4249 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4250 return 0;
4251
4252err_cmd_init:
4253 pci_release_regions(pdev);
4254err_pci_init:
4255 pci_set_drvdata(pdev, NULL);
4256err_hclge_dev:
4257 return ret;
4258}
4259
4260static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4261{
4262 struct hclge_dev *hdev = ae_dev->priv;
4263 struct hclge_mac *mac = &hdev->hw.mac;
4264
4265 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4266
2a32ca13
AB		 4267 if (IS_ENABLED(CONFIG_PCI_IOV))
4268 hclge_disable_sriov(hdev);
46a3df9f
S		 4269
4270 if (hdev->service_timer.data)
4271 del_timer_sync(&hdev->service_timer);
4272 if (hdev->service_task.func)
4273 cancel_work_sync(&hdev->service_task);
4274
4275 if (mac->phydev)
4276 mdiobus_unregister(mac->mdio_bus);
4277
4278 hclge_destroy_cmd_queue(&hdev->hw);
4279 hclge_pci_uninit(hdev);
4280 ae_dev->priv = NULL;
4281}
4282
4283static const struct hnae3_ae_ops hclge_ops = {
4284 .init_ae_dev = hclge_init_ae_dev,
4285 .uninit_ae_dev = hclge_uninit_ae_dev,
4286 .init_client_instance = hclge_init_client_instance,
4287 .uninit_client_instance = hclge_uninit_client_instance,
4288 .map_ring_to_vector = hclge_map_handle_ring_to_vector,
4289 .unmap_ring_from_vector = hclge_unmap_ring_from_vector,
4290 .get_vector = hclge_get_vector,
4291 .set_promisc_mode = hclge_set_promisc_mode,
4292 .start = hclge_ae_start,
4293 .stop = hclge_ae_stop,
4294 .get_status = hclge_get_status,
4295 .get_ksettings_an_result = hclge_get_ksettings_an_result,
4296 .update_speed_duplex_h = hclge_update_speed_duplex_h,
4297 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
4298 .get_media_type = hclge_get_media_type,
4299 .get_rss_key_size = hclge_get_rss_key_size,
4300 .get_rss_indir_size = hclge_get_rss_indir_size,
4301 .get_rss = hclge_get_rss,
4302 .set_rss = hclge_set_rss,
4303 .get_tc_size = hclge_get_tc_size,
4304 .get_mac_addr = hclge_get_mac_addr,
4305 .set_mac_addr = hclge_set_mac_addr,
4306 .add_uc_addr = hclge_add_uc_addr,
4307 .rm_uc_addr = hclge_rm_uc_addr,
4308 .add_mc_addr = hclge_add_mc_addr,
4309 .rm_mc_addr = hclge_rm_mc_addr,
4310 .set_autoneg = hclge_set_autoneg,
4311 .get_autoneg = hclge_get_autoneg,
4312 .get_pauseparam = hclge_get_pauseparam,
4313 .set_mtu = hclge_set_mtu,
4314 .reset_queue = hclge_reset_tqp,
4315 .get_stats = hclge_get_stats,
4316 .update_stats = hclge_update_stats,
4317 .get_strings = hclge_get_strings,
4318 .get_sset_count = hclge_get_sset_count,
4319 .get_fw_version = hclge_get_fw_version,
4320 .get_mdix_mode = hclge_get_mdix_mode,
4321 .set_vlan_filter = hclge_set_port_vlan_filter,
4322 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
4323};
4324
4325static struct hnae3_ae_algo ae_algo = {
4326 .ops = &hclge_ops,
4327 .name = HCLGE_NAME,
4328 .pdev_id_table = ae_algo_pci_tbl,
4329};
4330
4331static int hclge_init(void)
4332{
4333 pr_info("%s is initializing\n", HCLGE_NAME);
4334
4335 return hnae3_register_ae_algo(&ae_algo);
4336}
4337
4338static void hclge_exit(void)
4339{
4340 hnae3_unregister_ae_algo(&ae_algo);
4341}
4342module_init(hclge_init);
4343module_exit(hclge_exit);
4344
4345MODULE_LICENSE("GPL");
4346MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4347MODULE_DESCRIPTION("HCLGE Driver");
4348MODULE_VERSION(HCLGE_MOD_VERSION);
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