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UBUNTU: SAUCE: {topost} net: hns3: Use roce handle when calling roce callback function
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
4e2e261d
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
46a3df9f
S		 3
4#include <linux/acpi.h>
5#include <linux/device.h>
6#include <linux/etherdevice.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
7393ed39 14#include <linux/if_vlan.h>
d5752031 15#include <net/rtnetlink.h>
46a3df9f 16#include "hclge_cmd.h"
cacde272 17#include "hclge_dcb.h"
46a3df9f 18#include "hclge_main.h"
0cdbdd3e 19#include "hclge_mbx.h"
46a3df9f
S		 20#include "hclge_mdio.h"
21#include "hclge_tm.h"
22#include "hnae3.h"
23
24#define HCLGE_NAME "hclge"
25#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
26#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
27#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
28#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
29
46a3df9f
S		 30static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
31 enum hclge_mta_dmac_sel_type mta_mac_sel,
32 bool enable);
59bc85ec 33static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 34static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 35static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 36
37static struct hnae3_ae_algo ae_algo;
38
39static const struct pci_device_id ae_algo_pci_tbl[] = {
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 47 /* required last entry */
46a3df9f
S		 48 {0, }
49};
50
28d9cec8
YL		 51MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
52
46a3df9f
S		 53static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
54 "Mac Loopback test",
55 "Serdes Loopback test",
56 "Phy Loopback test"
57};
58
59static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
66 {"igu_rx_uni_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
68 {"igu_rx_multi_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
70 {"igu_rx_broad_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
74 {"egu_tx_uni_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
76 {"egu_tx_multi_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
78 {"egu_tx_broad_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
88 {"ssu_tx_in_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
90 {"ssu_tx_out_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
92 {"ssu_rx_in_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
94 {"ssu_rx_out_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
96};
97
98static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
99 {"igu_rx_err_pkt",
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
105 {"egu_tx_1588_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
111 {"ppp_key_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
113 {"ppp_rlt_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
115 {"ssu_key_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
117 {"pkt_curr_buf_cnt",
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
119 {"qcn_fb_rcv_cnt",
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
121 {"qcn_fb_drop_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
205 {"mb_uncopy_num",
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
221};
222
223static const struct hclge_comm_stats_str g_mac_stats_string[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
f3426583
JS		 280 {"mac_tx_oversize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
b42874e4
JS		 294 {"mac_tx_1519_2047_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
296 {"mac_tx_2048_4095_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
298 {"mac_tx_4096_8191_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
b42874e4
JS		 300 {"mac_tx_8192_9216_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
302 {"mac_tx_9217_12287_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
304 {"mac_tx_12288_16383_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
306 {"mac_tx_1519_max_good_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
308 {"mac_tx_1519_max_bad_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 310 {"mac_rx_total_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
312 {"mac_rx_total_oct_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
314 {"mac_rx_good_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
316 {"mac_rx_bad_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
318 {"mac_rx_good_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
320 {"mac_rx_bad_oct_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
322 {"mac_rx_uni_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
324 {"mac_rx_multi_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
326 {"mac_rx_broad_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
328 {"mac_rx_undersize_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
f3426583
JS		 330 {"mac_rx_oversize_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 332 {"mac_rx_64_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
334 {"mac_rx_65_127_oct_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
336 {"mac_rx_128_255_oct_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
338 {"mac_rx_256_511_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
340 {"mac_rx_512_1023_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
342 {"mac_rx_1024_1518_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
b42874e4
JS		 344 {"mac_rx_1519_2047_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
346 {"mac_rx_2048_4095_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
348 {"mac_rx_4096_8191_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
b42874e4
JS		 350 {"mac_rx_8192_9216_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
352 {"mac_rx_9217_12287_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
354 {"mac_rx_12288_16383_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
356 {"mac_rx_1519_max_good_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
358 {"mac_rx_1519_max_bad_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 360
c36317be
JS		 361 {"mac_tx_fragment_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
363 {"mac_tx_undermin_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
365 {"mac_tx_jabber_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
367 {"mac_tx_err_all_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
369 {"mac_tx_from_app_good_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
371 {"mac_tx_from_app_bad_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
373 {"mac_rx_fragment_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
375 {"mac_rx_undermin_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
377 {"mac_rx_jabber_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
379 {"mac_rx_fcs_err_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
381 {"mac_rx_send_app_good_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
383 {"mac_rx_send_app_bad_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 385};
386
635bfb58
FL		 387static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
388 {
389 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
390 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
391 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
392 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
393 .i_port_bitmap = 0x1,
394 },
395};
396
46a3df9f
S		 397static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
398{
399#define HCLGE_64_BIT_CMD_NUM 5
400#define HCLGE_64_BIT_RTN_DATANUM 4
401 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
402 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 403 __le64 *desc_data;
46a3df9f
S		 404 int i, k, n;
405 int ret;
406
407 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
408 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
409 if (ret) {
410 dev_err(&hdev->pdev->dev,
411 "Get 64 bit pkt stats fail, status = %d.\n", ret);
412 return ret;
413 }
414
415 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
416 if (unlikely(i == 0)) {
a90bb9a5 417 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 418 n = HCLGE_64_BIT_RTN_DATANUM - 1;
419 } else {
a90bb9a5 420 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 421 n = HCLGE_64_BIT_RTN_DATANUM;
422 }
423 for (k = 0; k < n; k++) {
a90bb9a5 424 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 425 desc_data++;
426 }
427 }
428
429 return 0;
430}
431
432static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
433{
434 stats->pkt_curr_buf_cnt = 0;
435 stats->pkt_curr_buf_tc0_cnt = 0;
436 stats->pkt_curr_buf_tc1_cnt = 0;
437 stats->pkt_curr_buf_tc2_cnt = 0;
438 stats->pkt_curr_buf_tc3_cnt = 0;
439 stats->pkt_curr_buf_tc4_cnt = 0;
440 stats->pkt_curr_buf_tc5_cnt = 0;
441 stats->pkt_curr_buf_tc6_cnt = 0;
442 stats->pkt_curr_buf_tc7_cnt = 0;
443}
444
445static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
446{
447#define HCLGE_32_BIT_CMD_NUM 8
448#define HCLGE_32_BIT_RTN_DATANUM 8
449
450 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
451 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 452 __le32 *desc_data;
46a3df9f
S		 453 int i, k, n;
454 u64 *data;
455 int ret;
456
457 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
458 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
459
460 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
461 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
462 if (ret) {
463 dev_err(&hdev->pdev->dev,
464 "Get 32 bit pkt stats fail, status = %d.\n", ret);
465
466 return ret;
467 }
468
469 hclge_reset_partial_32bit_counter(all_32_bit_stats);
470 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
471 if (unlikely(i == 0)) {
a90bb9a5
YL		 472 __le16 *desc_data_16bit;
473
46a3df9f 474 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 475 le32_to_cpu(desc[i].data[0]);
476
477 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 478 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 479 le16_to_cpu(*desc_data_16bit);
480
481 desc_data_16bit++;
46a3df9f 482 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 483 le16_to_cpu(*desc_data_16bit);
46a3df9f 484
a90bb9a5 485 desc_data = &desc[i].data[2];
46a3df9f
S		 486 n = HCLGE_32_BIT_RTN_DATANUM - 4;
487 } else {
a90bb9a5 488 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 489 n = HCLGE_32_BIT_RTN_DATANUM;
490 }
491 for (k = 0; k < n; k++) {
a90bb9a5 492 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 493 desc_data++;
494 }
495 }
496
497 return 0;
498}
499
500static int hclge_mac_update_stats(struct hclge_dev *hdev)
501{
b42874e4 502#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 503#define HCLGE_RTN_DATA_NUM 4
504
505 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
506 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 507 __le64 *desc_data;
46a3df9f
S		 508 int i, k, n;
509 int ret;
510
511 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
512 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
513 if (ret) {
514 dev_err(&hdev->pdev->dev,
515 "Get MAC pkt stats fail, status = %d.\n", ret);
516
517 return ret;
518 }
519
520 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
521 if (unlikely(i == 0)) {
a90bb9a5 522 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 523 n = HCLGE_RTN_DATA_NUM - 2;
524 } else {
a90bb9a5 525 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 526 n = HCLGE_RTN_DATA_NUM;
527 }
528 for (k = 0; k < n; k++) {
a90bb9a5 529 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 530 desc_data++;
531 }
532 }
533
534 return 0;
535}
536
537static int hclge_tqps_update_stats(struct hnae3_handle *handle)
538{
539 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
540 struct hclge_vport *vport = hclge_get_vport(handle);
541 struct hclge_dev *hdev = vport->back;
542 struct hnae3_queue *queue;
543 struct hclge_desc desc[1];
544 struct hclge_tqp *tqp;
545 int ret, i;
546
547 for (i = 0; i < kinfo->num_tqps; i++) {
548 queue = handle->kinfo.tqp[i];
549 tqp = container_of(queue, struct hclge_tqp, q);
550 /* command : HCLGE_OPC_QUERY_IGU_STAT */
551 hclge_cmd_setup_basic_desc(&desc[0],
552 HCLGE_OPC_QUERY_RX_STATUS,
553 true);
554
a90bb9a5 555 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 556 ret = hclge_cmd_send(&hdev->hw, desc, 1);
557 if (ret) {
558 dev_err(&hdev->pdev->dev,
559 "Query tqp stat fail, status = %d,queue = %d\n",
560 ret, i);
561 return ret;
562 }
563 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 564 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 565 }
566
567 for (i = 0; i < kinfo->num_tqps; i++) {
568 queue = handle->kinfo.tqp[i];
569 tqp = container_of(queue, struct hclge_tqp, q);
570 /* command : HCLGE_OPC_QUERY_IGU_STAT */
571 hclge_cmd_setup_basic_desc(&desc[0],
572 HCLGE_OPC_QUERY_TX_STATUS,
573 true);
574
a90bb9a5 575 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 576 ret = hclge_cmd_send(&hdev->hw, desc, 1);
577 if (ret) {
578 dev_err(&hdev->pdev->dev,
579 "Query tqp stat fail, status = %d,queue = %d\n",
580 ret, i);
581 return ret;
582 }
583 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 584 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 585 }
586
587 return 0;
588}
589
590static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
591{
592 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
593 struct hclge_tqp *tqp;
594 u64 *buff = data;
595 int i;
596
597 for (i = 0; i < kinfo->num_tqps; i++) {
598 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 599 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 600 }
601
602 for (i = 0; i < kinfo->num_tqps; i++) {
603 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 604 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 605 }
606
607 return buff;
608}
609
610static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
611{
612 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
613
614 return kinfo->num_tqps * (2);
615}
616
617static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
618{
619 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
620 u8 *buff = data;
621 int i = 0;
622
623 for (i = 0; i < kinfo->num_tqps; i++) {
624 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
625 struct hclge_tqp, q);
c36317be 626 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
46a3df9f
S		 627 tqp->index);
628 buff = buff + ETH_GSTRING_LEN;
629 }
630
631 for (i = 0; i < kinfo->num_tqps; i++) {
632 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
633 struct hclge_tqp, q);
c36317be 634 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
46a3df9f
S		 635 tqp->index);
636 buff = buff + ETH_GSTRING_LEN;
637 }
638
639 return buff;
640}
641
642static u64 *hclge_comm_get_stats(void *comm_stats,
643 const struct hclge_comm_stats_str strs[],
644 int size, u64 *data)
645{
646 u64 *buf = data;
647 u32 i;
648
649 for (i = 0; i < size; i++)
650 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
651
652 return buf + size;
653}
654
655static u8 *hclge_comm_get_strings(u32 stringset,
656 const struct hclge_comm_stats_str strs[],
657 int size, u8 *data)
658{
659 char *buff = (char *)data;
660 u32 i;
661
662 if (stringset != ETH_SS_STATS)
663 return buff;
664
665 for (i = 0; i < size; i++) {
666 snprintf(buff, ETH_GSTRING_LEN,
667 strs[i].desc);
668 buff = buff + ETH_GSTRING_LEN;
669 }
670
671 return (u8 *)buff;
672}
673
674static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
675 struct net_device_stats *net_stats)
676{
677 net_stats->tx_dropped = 0;
678 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
679 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
680 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
681
f3426583 682 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 683 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
46a3df9f
S		 684 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
685 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
c36317be 686 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 687
688 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
689 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
690
c36317be 691 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 692 net_stats->rx_length_errors =
693 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
694 net_stats->rx_length_errors +=
f3426583 695 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 696 net_stats->rx_over_errors =
f3426583 697 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 698}
699
700static void hclge_update_stats_for_all(struct hclge_dev *hdev)
701{
702 struct hnae3_handle *handle;
703 int status;
704
705 handle = &hdev->vport[0].nic;
706 if (handle->client) {
707 status = hclge_tqps_update_stats(handle);
708 if (status) {
709 dev_err(&hdev->pdev->dev,
710 "Update TQPS stats fail, status = %d.\n",
711 status);
712 }
713 }
714
715 status = hclge_mac_update_stats(hdev);
716 if (status)
717 dev_err(&hdev->pdev->dev,
718 "Update MAC stats fail, status = %d.\n", status);
719
720 status = hclge_32_bit_update_stats(hdev);
721 if (status)
722 dev_err(&hdev->pdev->dev,
723 "Update 32 bit stats fail, status = %d.\n",
724 status);
725
726 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
727}
728
729static void hclge_update_stats(struct hnae3_handle *handle,
730 struct net_device_stats *net_stats)
731{
732 struct hclge_vport *vport = hclge_get_vport(handle);
733 struct hclge_dev *hdev = vport->back;
734 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
735 int status;
736
7a5d2a39
JS		 737 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
738 return;
739
46a3df9f
S		 740 status = hclge_mac_update_stats(hdev);
741 if (status)
742 dev_err(&hdev->pdev->dev,
743 "Update MAC stats fail, status = %d.\n",
744 status);
745
746 status = hclge_32_bit_update_stats(hdev);
747 if (status)
748 dev_err(&hdev->pdev->dev,
749 "Update 32 bit stats fail, status = %d.\n",
750 status);
751
752 status = hclge_64_bit_update_stats(hdev);
753 if (status)
754 dev_err(&hdev->pdev->dev,
755 "Update 64 bit stats fail, status = %d.\n",
756 status);
757
758 status = hclge_tqps_update_stats(handle);
759 if (status)
760 dev_err(&hdev->pdev->dev,
761 "Update TQPS stats fail, status = %d.\n",
762 status);
763
764 hclge_update_netstat(hw_stats, net_stats);
7a5d2a39
JS		 765
766 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 767}
768
769static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
770{
771#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
772
773 struct hclge_vport *vport = hclge_get_vport(handle);
774 struct hclge_dev *hdev = vport->back;
775 int count = 0;
776
777 /* Loopback test support rules:
778 * mac: only GE mode support
779 * serdes: all mac mode will support include GE/XGE/LGE/CGE
780 * phy: only support when phy device exist on board
781 */
782 if (stringset == ETH_SS_TEST) {
783 /* clear loopback bit flags at first */
784 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
785 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
786 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
787 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
788 count += 1;
789 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
46a3df9f 790 }
2fd5416a
YL		 791
792 count ++;
793 handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK;
46a3df9f
S		 794 } else if (stringset == ETH_SS_STATS) {
795 count = ARRAY_SIZE(g_mac_stats_string) +
796 ARRAY_SIZE(g_all_32bit_stats_string) +
797 ARRAY_SIZE(g_all_64bit_stats_string) +
798 hclge_tqps_get_sset_count(handle, stringset);
799 }
800
801 return count;
802}
803
804static void hclge_get_strings(struct hnae3_handle *handle,
805 u32 stringset,
806 u8 *data)
807{
808 u8 *p = (char *)data;
809 int size;
810
811 if (stringset == ETH_SS_STATS) {
812 size = ARRAY_SIZE(g_mac_stats_string);
813 p = hclge_comm_get_strings(stringset,
814 g_mac_stats_string,
815 size,
816 p);
817 size = ARRAY_SIZE(g_all_32bit_stats_string);
818 p = hclge_comm_get_strings(stringset,
819 g_all_32bit_stats_string,
820 size,
821 p);
822 size = ARRAY_SIZE(g_all_64bit_stats_string);
823 p = hclge_comm_get_strings(stringset,
824 g_all_64bit_stats_string,
825 size,
826 p);
827 p = hclge_tqps_get_strings(handle, p);
828 } else if (stringset == ETH_SS_TEST) {
829 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
830 memcpy(p,
831 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
832 ETH_GSTRING_LEN);
833 p += ETH_GSTRING_LEN;
834 }
835 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
836 memcpy(p,
837 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
838 ETH_GSTRING_LEN);
839 p += ETH_GSTRING_LEN;
840 }
841 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
842 memcpy(p,
843 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
844 ETH_GSTRING_LEN);
845 p += ETH_GSTRING_LEN;
846 }
847 }
848}
849
850static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
851{
852 struct hclge_vport *vport = hclge_get_vport(handle);
853 struct hclge_dev *hdev = vport->back;
854 u64 *p;
855
856 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
857 g_mac_stats_string,
858 ARRAY_SIZE(g_mac_stats_string),
859 data);
860 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
861 g_all_32bit_stats_string,
862 ARRAY_SIZE(g_all_32bit_stats_string),
863 p);
864 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
865 g_all_64bit_stats_string,
866 ARRAY_SIZE(g_all_64bit_stats_string),
867 p);
868 p = hclge_tqps_get_stats(handle, p);
869}
870
871static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 872 struct hclge_func_status_cmd *status)
46a3df9f
S		 873{
874 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
875 return -EINVAL;
876
877 /* Set the pf to main pf */
878 if (status->pf_state & HCLGE_PF_STATE_MAIN)
879 hdev->flag |= HCLGE_FLAG_MAIN;
880 else
881 hdev->flag &= ~HCLGE_FLAG_MAIN;
882
46a3df9f
S		 883 return 0;
884}
885
886static int hclge_query_function_status(struct hclge_dev *hdev)
887{
d44f9b63 888 struct hclge_func_status_cmd *req;
46a3df9f
S		 889 struct hclge_desc desc;
890 int timeout = 0;
891 int ret;
892
893 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 894 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 895
896 do {
897 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
898 if (ret) {
899 dev_err(&hdev->pdev->dev,
900 "query function status failed %d.\n",
901 ret);
902
903 return ret;
904 }
905
906 /* Check pf reset is done */
907 if (req->pf_state)
908 break;
909 usleep_range(1000, 2000);
910 } while (timeout++ < 5);
911
912 ret = hclge_parse_func_status(hdev, req);
913
914 return ret;
915}
916
917static int hclge_query_pf_resource(struct hclge_dev *hdev)
918{
d44f9b63 919 struct hclge_pf_res_cmd *req;
46a3df9f
S		 920 struct hclge_desc desc;
921 int ret;
922
923 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
924 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
925 if (ret) {
926 dev_err(&hdev->pdev->dev,
927 "query pf resource failed %d.\n", ret);
928 return ret;
929 }
930
d44f9b63 931 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 932 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
933 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
934
e92a0843 935 if (hnae3_dev_roce_supported(hdev)) {
887c3820 936 hdev->num_roce_msi =
e22b531b
HT		 937 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
938 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 939
940 /* PF should have NIC vectors and Roce vectors,
941 * NIC vectors are queued before Roce vectors.
942 */
887c3820 943 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 944 } else {
945 hdev->num_msi =
e22b531b
HT		 946 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
947 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 948 }
949
950 return 0;
951}
952
953static int hclge_parse_speed(int speed_cmd, int *speed)
954{
955 switch (speed_cmd) {
956 case 6:
957 *speed = HCLGE_MAC_SPEED_10M;
958 break;
959 case 7:
960 *speed = HCLGE_MAC_SPEED_100M;
961 break;
962 case 0:
963 *speed = HCLGE_MAC_SPEED_1G;
964 break;
965 case 1:
966 *speed = HCLGE_MAC_SPEED_10G;
967 break;
968 case 2:
969 *speed = HCLGE_MAC_SPEED_25G;
970 break;
971 case 3:
972 *speed = HCLGE_MAC_SPEED_40G;
973 break;
974 case 4:
975 *speed = HCLGE_MAC_SPEED_50G;
976 break;
977 case 5:
978 *speed = HCLGE_MAC_SPEED_100G;
979 break;
980 default:
981 return -EINVAL;
982 }
983
984 return 0;
985}
986
d92ceae9
FL		 987static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
988 u8 speed_ability)
989{
990 unsigned long *supported = hdev->hw.mac.supported;
991
992 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
993 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
994 supported);
995
996 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
997 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
998 supported);
999
1000 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1001 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1002 supported);
1003
1004 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1005 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1006 supported);
1007
1008 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1009 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1010 supported);
1011
1012 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
1013 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1014}
1015
1016static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
1017{
1018 u8 media_type = hdev->hw.mac.media_type;
1019
1020 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
1021 return;
1022
1023 hclge_parse_fiber_link_mode(hdev, speed_ability);
1024}
1025
46a3df9f
S		 1026static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1027{
d44f9b63 1028 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1029 u64 mac_addr_tmp_high;
1030 u64 mac_addr_tmp;
1031 int i;
1032
d44f9b63 1033 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 1034
1035 /* get the configuration */
e22b531b
HT		 1036 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1037 HCLGE_CFG_VMDQ_M,
1038 HCLGE_CFG_VMDQ_S);
1039 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1040 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1041 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1042 HCLGE_CFG_TQP_DESC_N_M,
1043 HCLGE_CFG_TQP_DESC_N_S);
1044
1045 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1046 HCLGE_CFG_PHY_ADDR_M,
1047 HCLGE_CFG_PHY_ADDR_S);
1048 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1049 HCLGE_CFG_MEDIA_TP_M,
1050 HCLGE_CFG_MEDIA_TP_S);
1051 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1052 HCLGE_CFG_RX_BUF_LEN_M,
1053 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 1054 /* get mac_address */
1055 mac_addr_tmp = __le32_to_cpu(req->param[2]);
e22b531b
HT		 1056 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1057 HCLGE_CFG_MAC_ADDR_H_M,
1058 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 1059
1060 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1061
e22b531b
HT		 1062 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1063 HCLGE_CFG_DEFAULT_SPEED_M,
1064 HCLGE_CFG_DEFAULT_SPEED_S);
1065 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1066 HCLGE_CFG_RSS_SIZE_M,
1067 HCLGE_CFG_RSS_SIZE_S);
c408e202 1068
46a3df9f
S		 1069 for (i = 0; i < ETH_ALEN; i++)
1070 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1071
d44f9b63 1072 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 1073 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
d92ceae9 1074
e22b531b
HT		 1075 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1076 HCLGE_CFG_SPEED_ABILITY_M,
1077 HCLGE_CFG_SPEED_ABILITY_S);
46a3df9f
S		 1078}
1079
1080/* hclge_get_cfg: query the static parameter from flash
1081 * @hdev: pointer to struct hclge_dev
1082 * @hcfg: the config structure to be getted
1083 */
1084static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1085{
1086 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 1087 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1088 int i, ret;
1089
1090 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1091 u32 offset = 0;
1092
d44f9b63 1093 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1094 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1095 true);
e22b531b
HT		 1096 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1097 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 1098 /* Len should be united by 4 bytes when send to hardware */
e22b531b
HT		 1099 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1100 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1101 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1102 }
1103
1104 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1105 if (ret) {
e125295a 1106 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
46a3df9f
S		 1107 return ret;
1108 }
1109
1110 hclge_parse_cfg(hcfg, desc);
e125295a 1111
46a3df9f
S		 1112 return 0;
1113}
1114
1115static int hclge_get_cap(struct hclge_dev *hdev)
1116{
1117 int ret;
1118
1119 ret = hclge_query_function_status(hdev);
1120 if (ret) {
1121 dev_err(&hdev->pdev->dev,
1122 "query function status error %d.\n", ret);
1123 return ret;
1124 }
1125
1126 /* get pf resource */
1127 ret = hclge_query_pf_resource(hdev);
e125295a
JS		 1128 if (ret)
1129 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
46a3df9f 1130
e125295a 1131 return ret;
46a3df9f
S		 1132}
1133
1134static int hclge_configure(struct hclge_dev *hdev)
1135{
1136 struct hclge_cfg cfg;
1137 int ret, i;
1138
1139 ret = hclge_get_cfg(hdev, &cfg);
1140 if (ret) {
1141 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1142 return ret;
1143 }
1144
1145 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1146 hdev->base_tqp_pid = 0;
c408e202 1147 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 1148 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1149 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1150 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1151 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1152 hdev->num_desc = cfg.tqp_desc_num;
1153 hdev->tm_info.num_pg = 1;
cacde272 1154 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1155 hdev->tm_info.hw_pfc_map = 0;
1156
1157 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1158 if (ret) {
1159 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1160 return ret;
1161 }
1162
d92ceae9
FL		 1163 hclge_parse_link_mode(hdev, cfg.speed_ability);
1164
cacde272
YL		 1165 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1166 (hdev->tc_max < 1)) {
46a3df9f 1167 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1168 hdev->tc_max);
1169 hdev->tc_max = 1;
46a3df9f
S		 1170 }
1171
cacde272
YL		 1172 /* Dev does not support DCB */
1173 if (!hnae3_dev_dcb_supported(hdev)) {
1174 hdev->tc_max = 1;
1175 hdev->pfc_max = 0;
1176 } else {
1177 hdev->pfc_max = hdev->tc_max;
1178 }
1179
1180 hdev->tm_info.num_tc = hdev->tc_max;
1181
46a3df9f 1182 /* Currently not support uncontiuous tc */
cacde272 1183 for (i = 0; i < hdev->tm_info.num_tc; i++)
e22b531b 1184 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 1185
f8362fe1 1186 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 1187
1188 return ret;
1189}
1190
1191static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1192 int tso_mss_max)
1193{
d44f9b63 1194 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1195 struct hclge_desc desc;
a90bb9a5 1196 u16 tso_mss;
46a3df9f
S		 1197
1198 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1199
d44f9b63 1200 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1201
1202 tso_mss = 0;
e22b531b
HT		 1203 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1204 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1205 req->tso_mss_min = cpu_to_le16(tso_mss);
1206
1207 tso_mss = 0;
e22b531b
HT		 1208 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1209 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1210 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1211
1212 return hclge_cmd_send(&hdev->hw, &desc, 1);
1213}
1214
1215static int hclge_alloc_tqps(struct hclge_dev *hdev)
1216{
1217 struct hclge_tqp *tqp;
1218 int i;
1219
1220 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1221 sizeof(struct hclge_tqp), GFP_KERNEL);
1222 if (!hdev->htqp)
1223 return -ENOMEM;
1224
1225 tqp = hdev->htqp;
1226
1227 for (i = 0; i < hdev->num_tqps; i++) {
1228 tqp->dev = &hdev->pdev->dev;
1229 tqp->index = i;
1230
1231 tqp->q.ae_algo = &ae_algo;
1232 tqp->q.buf_size = hdev->rx_buf_len;
1233 tqp->q.desc_num = hdev->num_desc;
1234 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1235 i * HCLGE_TQP_REG_SIZE;
1236
1237 tqp++;
1238 }
1239
1240 return 0;
1241}
1242
1243static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1244 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1245{
d44f9b63 1246 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1247 struct hclge_desc desc;
1248 int ret;
1249
1250 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1251
d44f9b63 1252 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1253 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1254 req->tqp_vf = func_id;
46a3df9f
S		 1255 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1256 1 << HCLGE_TQP_MAP_EN_B;
1257 req->tqp_vid = cpu_to_le16(tqp_vid);
1258
1259 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a
JS		 1260 if (ret)
1261 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
46a3df9f 1262
e125295a 1263 return ret;
46a3df9f
S		 1264}
1265
1266static int hclge_assign_tqp(struct hclge_vport *vport,
1267 struct hnae3_queue **tqp, u16 num_tqps)
1268{
1269 struct hclge_dev *hdev = vport->back;
7df7dad6 1270 int i, alloced;
46a3df9f
S		 1271
1272 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1273 alloced < num_tqps; i++) {
1274 if (!hdev->htqp[i].alloced) {
1275 hdev->htqp[i].q.handle = &vport->nic;
1276 hdev->htqp[i].q.tqp_index = alloced;
1277 tqp[alloced] = &hdev->htqp[i].q;
1278 hdev->htqp[i].alloced = true;
46a3df9f
S		 1279 alloced++;
1280 }
1281 }
1282 vport->alloc_tqps = num_tqps;
1283
1284 return 0;
1285}
1286
1287static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1288{
1289 struct hnae3_handle *nic = &vport->nic;
1290 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1291 struct hclge_dev *hdev = vport->back;
1292 int i, ret;
1293
1294 kinfo->num_desc = hdev->num_desc;
1295 kinfo->rx_buf_len = hdev->rx_buf_len;
1296 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1297 kinfo->rss_size
1298 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1299 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1300
1301 for (i = 0; i < HNAE3_MAX_TC; i++) {
1302 if (hdev->hw_tc_map & BIT(i)) {
1303 kinfo->tc_info[i].enable = true;
1304 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1305 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1306 kinfo->tc_info[i].tc = i;
1307 } else {
1308 /* Set to default queue if TC is disable */
1309 kinfo->tc_info[i].enable = false;
1310 kinfo->tc_info[i].tqp_offset = 0;
1311 kinfo->tc_info[i].tqp_count = 1;
1312 kinfo->tc_info[i].tc = 0;
1313 }
1314 }
1315
1316 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1317 sizeof(struct hnae3_queue *), GFP_KERNEL);
1318 if (!kinfo->tqp)
1319 return -ENOMEM;
1320
1321 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
e125295a 1322 if (ret)
46a3df9f 1323 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
46a3df9f 1324
e125295a 1325 return ret;
46a3df9f
S		 1326}
1327
7df7dad6
L		 1328static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1329 struct hclge_vport *vport)
1330{
1331 struct hnae3_handle *nic = &vport->nic;
1332 struct hnae3_knic_private_info *kinfo;
1333 u16 i;
1334
1335 kinfo = &nic->kinfo;
1336 for (i = 0; i < kinfo->num_tqps; i++) {
1337 struct hclge_tqp *q =
1338 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1339 bool is_pf;
1340 int ret;
1341
1342 is_pf = !(vport->vport_id);
1343 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1344 i, is_pf);
1345 if (ret)
1346 return ret;
1347 }
1348
1349 return 0;
1350}
1351
1352static int hclge_map_tqp(struct hclge_dev *hdev)
1353{
1354 struct hclge_vport *vport = hdev->vport;
1355 u16 i, num_vport;
1356
1357 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1358 for (i = 0; i < num_vport; i++) {
1359 int ret;
1360
1361 ret = hclge_map_tqp_to_vport(hdev, vport);
1362 if (ret)
1363 return ret;
1364
1365 vport++;
1366 }
1367
1368 return 0;
1369}
1370
46a3df9f
S		 1371static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1372{
1373 /* this would be initialized later */
1374}
1375
1376static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1377{
1378 struct hnae3_handle *nic = &vport->nic;
1379 struct hclge_dev *hdev = vport->back;
1380 int ret;
1381
1382 nic->pdev = hdev->pdev;
1383 nic->ae_algo = &ae_algo;
1384 nic->numa_node_mask = hdev->numa_node_mask;
1385
1386 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1387 ret = hclge_knic_setup(vport, num_tqps);
1388 if (ret) {
1389 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1390 ret);
1391 return ret;
1392 }
1393 } else {
1394 hclge_unic_setup(vport, num_tqps);
1395 }
1396
1397 return 0;
1398}
1399
1400static int hclge_alloc_vport(struct hclge_dev *hdev)
1401{
1402 struct pci_dev *pdev = hdev->pdev;
1403 struct hclge_vport *vport;
1404 u32 tqp_main_vport;
1405 u32 tqp_per_vport;
1406 int num_vport, i;
1407 int ret;
1408
1409 /* We need to alloc a vport for main NIC of PF */
1410 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1411
b76edfb2
HT		 1412 if (hdev->num_tqps < num_vport) {
1413 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1414 hdev->num_tqps, num_vport);
1415 return -EINVAL;
1416 }
46a3df9f
S		 1417
1418 /* Alloc the same number of TQPs for every vport */
1419 tqp_per_vport = hdev->num_tqps / num_vport;
1420 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1421
1422 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1423 GFP_KERNEL);
1424 if (!vport)
1425 return -ENOMEM;
1426
1427 hdev->vport = vport;
1428 hdev->num_alloc_vport = num_vport;
1429
bc59f827
FL		 1430 if (IS_ENABLED(CONFIG_PCI_IOV))
1431 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1432
1433 for (i = 0; i < num_vport; i++) {
1434 vport->back = hdev;
1435 vport->vport_id = i;
1436
1437 if (i == 0)
1438 ret = hclge_vport_setup(vport, tqp_main_vport);
1439 else
1440 ret = hclge_vport_setup(vport, tqp_per_vport);
1441 if (ret) {
1442 dev_err(&pdev->dev,
1443 "vport setup failed for vport %d, %d\n",
1444 i, ret);
1445 return ret;
1446 }
1447
1448 vport++;
1449 }
1450
1451 return 0;
1452}
1453
acf61ecd
YL		 1454static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1455 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1456{
1457/* TX buffer size is unit by 128 byte */
1458#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1459#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1460 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1461 struct hclge_desc desc;
1462 int ret;
1463 u8 i;
1464
d44f9b63 1465 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1466
1467 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1468 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1469 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1470
46a3df9f
S		 1471 req->tx_pkt_buff[i] =
1472 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1473 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1474 }
46a3df9f
S		 1475
1476 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 1477 if (ret)
46a3df9f
S		 1478 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1479 ret);
46a3df9f 1480
e125295a 1481 return ret;
46a3df9f
S		 1482}
1483
acf61ecd
YL		 1484static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1485 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1486{
acf61ecd 1487 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1488
e125295a
JS		 1489 if (ret)
1490 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
46a3df9f 1491
e125295a 1492 return ret;
46a3df9f
S		 1493}
1494
1495static int hclge_get_tc_num(struct hclge_dev *hdev)
1496{
1497 int i, cnt = 0;
1498
1499 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1500 if (hdev->hw_tc_map & BIT(i))
1501 cnt++;
1502 return cnt;
1503}
1504
1505static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1506{
1507 int i, cnt = 0;
1508
1509 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1510 if (hdev->hw_tc_map & BIT(i) &&
1511 hdev->tm_info.hw_pfc_map & BIT(i))
1512 cnt++;
1513 return cnt;
1514}
1515
1516/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1517static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1518 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1519{
1520 struct hclge_priv_buf *priv;
1521 int i, cnt = 0;
1522
1523 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1524 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1525 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1526 priv->enable)
1527 cnt++;
1528 }
1529
1530 return cnt;
1531}
1532
1533/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1534static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1535 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1536{
1537 struct hclge_priv_buf *priv;
1538 int i, cnt = 0;
1539
1540 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1541 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1542 if (hdev->hw_tc_map & BIT(i) &&
1543 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1544 priv->enable)
1545 cnt++;
1546 }
1547
1548 return cnt;
1549}
1550
acf61ecd 1551static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1552{
1553 struct hclge_priv_buf *priv;
1554 u32 rx_priv = 0;
1555 int i;
1556
1557 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1558 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1559 if (priv->enable)
1560 rx_priv += priv->buf_size;
1561 }
1562 return rx_priv;
1563}
1564
acf61ecd 1565static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1566{
1567 u32 i, total_tx_size = 0;
1568
1569 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1570 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1571
1572 return total_tx_size;
1573}
1574
acf61ecd
YL		 1575static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1576 struct hclge_pkt_buf_alloc *buf_alloc,
1577 u32 rx_all)
46a3df9f
S		 1578{
1579 u32 shared_buf_min, shared_buf_tc, shared_std;
1580 int tc_num, pfc_enable_num;
1581 u32 shared_buf;
1582 u32 rx_priv;
1583 int i;
1584
1585 tc_num = hclge_get_tc_num(hdev);
1586 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1587
d221df4e
YL		 1588 if (hnae3_dev_dcb_supported(hdev))
1589 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1590 else
1591 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1592
46a3df9f
S		 1593 shared_buf_tc = pfc_enable_num * hdev->mps +
1594 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1595 hdev->mps;
1596 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1597
acf61ecd 1598 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1599 if (rx_all <= rx_priv + shared_std)
1600 return false;
1601
1602 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1603 buf_alloc->s_buf.buf_size = shared_buf;
1604 buf_alloc->s_buf.self.high = shared_buf;
1605 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1606
1607 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1608 if ((hdev->hw_tc_map & BIT(i)) &&
1609 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1610 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1611 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1612 } else {
acf61ecd
YL		 1613 buf_alloc->s_buf.tc_thrd[i].low = 0;
1614 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1615 }
1616 }
1617
1618 return true;
1619}
1620
acf61ecd
YL		 1621static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1622 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1623{
1624 u32 i, total_size;
1625
1626 total_size = hdev->pkt_buf_size;
1627
1628 /* alloc tx buffer for all enabled tc */
1629 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1630 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1631
1632 if (total_size < HCLGE_DEFAULT_TX_BUF)
1633 return -ENOMEM;
1634
1635 if (hdev->hw_tc_map & BIT(i))
1636 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1637 else
1638 priv->tx_buf_size = 0;
1639
1640 total_size -= priv->tx_buf_size;
1641 }
1642
1643 return 0;
1644}
1645
46a3df9f
S		 1646/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1647 * @hdev: pointer to struct hclge_dev
acf61ecd 1648 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1649 * @return: 0: calculate sucessful, negative: fail
1650 */
1db9b1bf
YL		 1651static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1652 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1653{
9ffe79a9 1654 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1655 int no_pfc_priv_num, pfc_priv_num;
1656 struct hclge_priv_buf *priv;
1657 int i;
1658
acf61ecd 1659 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1660
d602a525
YL		 1661 /* When DCB is not supported, rx private
1662 * buffer is not allocated.
1663 */
1664 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1665 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1666 return -ENOMEM;
1667
1668 return 0;
1669 }
1670
46a3df9f
S		 1671 /* step 1, try to alloc private buffer for all enabled tc */
1672 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1673 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1674 if (hdev->hw_tc_map & BIT(i)) {
1675 priv->enable = 1;
1676 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1677 priv->wl.low = hdev->mps;
1678 priv->wl.high = priv->wl.low + hdev->mps;
1679 priv->buf_size = priv->wl.high +
1680 HCLGE_DEFAULT_DV;
1681 } else {
1682 priv->wl.low = 0;
1683 priv->wl.high = 2 * hdev->mps;
1684 priv->buf_size = priv->wl.high;
1685 }
bb1fe9ea
YL		 1686 } else {
1687 priv->enable = 0;
1688 priv->wl.low = 0;
1689 priv->wl.high = 0;
1690 priv->buf_size = 0;
46a3df9f
S		 1691 }
1692 }
1693
acf61ecd 1694 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1695 return 0;
1696
1697 /* step 2, try to decrease the buffer size of
1698 * no pfc TC's private buffer
1699 */
1700 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1701 priv = &buf_alloc->priv_buf[i];
46a3df9f 1702
bb1fe9ea
YL		 1703 priv->enable = 0;
1704 priv->wl.low = 0;
1705 priv->wl.high = 0;
1706 priv->buf_size = 0;
1707
1708 if (!(hdev->hw_tc_map & BIT(i)))
1709 continue;
1710
1711 priv->enable = 1;
46a3df9f
S		 1712
1713 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1714 priv->wl.low = 128;
1715 priv->wl.high = priv->wl.low + hdev->mps;
1716 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1717 } else {
1718 priv->wl.low = 0;
1719 priv->wl.high = hdev->mps;
1720 priv->buf_size = priv->wl.high;
1721 }
1722 }
1723
acf61ecd 1724 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1725 return 0;
1726
1727 /* step 3, try to reduce the number of pfc disabled TCs,
1728 * which have private buffer
1729 */
1730 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1731 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1732
1733 /* let the last to be cleared first */
1734 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1735 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1736
1737 if (hdev->hw_tc_map & BIT(i) &&
1738 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1739 /* Clear the no pfc TC private buffer */
1740 priv->wl.low = 0;
1741 priv->wl.high = 0;
1742 priv->buf_size = 0;
1743 priv->enable = 0;
1744 no_pfc_priv_num--;
1745 }
1746
acf61ecd 1747 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1748 no_pfc_priv_num == 0)
1749 break;
1750 }
1751
acf61ecd 1752 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1753 return 0;
1754
1755 /* step 4, try to reduce the number of pfc enabled TCs
1756 * which have private buffer.
1757 */
acf61ecd 1758 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1759
1760 /* let the last to be cleared first */
1761 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1762 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1763
1764 if (hdev->hw_tc_map & BIT(i) &&
1765 hdev->tm_info.hw_pfc_map & BIT(i)) {
1766 /* Reduce the number of pfc TC with private buffer */
1767 priv->wl.low = 0;
1768 priv->enable = 0;
1769 priv->wl.high = 0;
1770 priv->buf_size = 0;
1771 pfc_priv_num--;
1772 }
1773
acf61ecd 1774 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1775 pfc_priv_num == 0)
1776 break;
1777 }
acf61ecd 1778 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1779 return 0;
1780
1781 return -ENOMEM;
1782}
1783
acf61ecd
YL		 1784static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1785 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1786{
d44f9b63 1787 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1788 struct hclge_desc desc;
1789 int ret;
1790 int i;
1791
1792 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1793 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1794
1795 /* Alloc private buffer TCs */
1796 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1797 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1798
1799 req->buf_num[i] =
1800 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1801 req->buf_num[i] |=
5bca3b94 1802 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1803 }
1804
b8c8bf47 1805 req->shared_buf =
acf61ecd 1806 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1807 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1808
46a3df9f 1809 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 1810 if (ret)
46a3df9f
S		 1811 dev_err(&hdev->pdev->dev,
1812 "rx private buffer alloc cmd failed %d\n", ret);
46a3df9f 1813
e125295a 1814 return ret;
46a3df9f
S		 1815}
1816
acf61ecd
YL		 1817static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1818 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1819{
1820 struct hclge_rx_priv_wl_buf *req;
1821 struct hclge_priv_buf *priv;
1822 struct hclge_desc desc[2];
1823 int i, j;
1824 int ret;
1825
1826 for (i = 0; i < 2; i++) {
1827 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1828 false);
1829 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1830
1831 /* The first descriptor set the NEXT bit to 1 */
1832 if (i == 0)
1833 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1834 else
1835 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1836
1837 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1838 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1839
1840 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1841 req->tc_wl[j].high =
1842 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1843 req->tc_wl[j].high |=
1b9980c7 1844 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1845 req->tc_wl[j].low =
1846 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1847 req->tc_wl[j].low |=
1b9980c7 1848 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1849 }
1850 }
1851
1852 /* Send 2 descriptor at one time */
1853 ret = hclge_cmd_send(&hdev->hw, desc, 2);
e125295a 1854 if (ret)
46a3df9f
S		 1855 dev_err(&hdev->pdev->dev,
1856 "rx private waterline config cmd failed %d\n",
1857 ret);
e125295a 1858 return ret;
46a3df9f
S		 1859}
1860
acf61ecd
YL		 1861static int hclge_common_thrd_config(struct hclge_dev *hdev,
1862 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1863{
acf61ecd 1864 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1865 struct hclge_rx_com_thrd *req;
1866 struct hclge_desc desc[2];
1867 struct hclge_tc_thrd *tc;
1868 int i, j;
1869 int ret;
1870
1871 for (i = 0; i < 2; i++) {
1872 hclge_cmd_setup_basic_desc(&desc[i],
1873 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1874 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1875
1876 /* The first descriptor set the NEXT bit to 1 */
1877 if (i == 0)
1878 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1879 else
1880 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1881
1882 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1883 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1884
1885 req->com_thrd[j].high =
1886 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1887 req->com_thrd[j].high |=
1b9980c7 1888 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1889 req->com_thrd[j].low =
1890 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1891 req->com_thrd[j].low |=
1b9980c7 1892 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1893 }
1894 }
1895
1896 /* Send 2 descriptors at one time */
1897 ret = hclge_cmd_send(&hdev->hw, desc, 2);
e125295a 1898 if (ret)
46a3df9f
S		 1899 dev_err(&hdev->pdev->dev,
1900 "common threshold config cmd failed %d\n", ret);
e125295a 1901 return ret;
46a3df9f
S		 1902}
1903
acf61ecd
YL		 1904static int hclge_common_wl_config(struct hclge_dev *hdev,
1905 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1906{
acf61ecd 1907 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1908 struct hclge_rx_com_wl *req;
1909 struct hclge_desc desc;
1910 int ret;
1911
1912 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1913
1914 req = (struct hclge_rx_com_wl *)desc.data;
1915 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1b9980c7 1916 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1917
1918 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1b9980c7 1919 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1920
1921 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 1922 if (ret)
46a3df9f
S		 1923 dev_err(&hdev->pdev->dev,
1924 "common waterline config cmd failed %d\n", ret);
e125295a 1925 return ret;
46a3df9f
S		 1926}
1927
1928int hclge_buffer_alloc(struct hclge_dev *hdev)
1929{
acf61ecd 1930 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1931 int ret;
1932
acf61ecd
YL		 1933 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1934 if (!pkt_buf)
46a3df9f
S		 1935 return -ENOMEM;
1936
acf61ecd 1937 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1938 if (ret) {
1939 dev_err(&hdev->pdev->dev,
1940 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1941 goto out;
9ffe79a9
YL		 1942 }
1943
acf61ecd 1944 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1945 if (ret) {
1946 dev_err(&hdev->pdev->dev,
1947 "could not alloc tx buffers %d\n", ret);
acf61ecd 1948 goto out;
46a3df9f
S		 1949 }
1950
acf61ecd 1951 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1952 if (ret) {
1953 dev_err(&hdev->pdev->dev,
1954 "could not calc rx priv buffer size for all TCs %d\n",
1955 ret);
acf61ecd 1956 goto out;
46a3df9f
S		 1957 }
1958
acf61ecd 1959 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1960 if (ret) {
1961 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1962 ret);
acf61ecd 1963 goto out;
46a3df9f
S		 1964 }
1965
2daf4a65 1966 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1967 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1968 if (ret) {
1969 dev_err(&hdev->pdev->dev,
1970 "could not configure rx private waterline %d\n",
1971 ret);
acf61ecd 1972 goto out;
2daf4a65 1973 }
46a3df9f 1974
acf61ecd 1975 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1976 if (ret) {
1977 dev_err(&hdev->pdev->dev,
1978 "could not configure common threshold %d\n",
1979 ret);
acf61ecd 1980 goto out;
2daf4a65 1981 }
46a3df9f
S		 1982 }
1983
acf61ecd
YL		 1984 ret = hclge_common_wl_config(hdev, pkt_buf);
1985 if (ret)
46a3df9f
S		 1986 dev_err(&hdev->pdev->dev,
1987 "could not configure common waterline %d\n", ret);
46a3df9f 1988
acf61ecd
YL		 1989out:
1990 kfree(pkt_buf);
1991 return ret;
46a3df9f
S		 1992}
1993
1994static int hclge_init_roce_base_info(struct hclge_vport *vport)
1995{
1996 struct hnae3_handle *roce = &vport->roce;
1997 struct hnae3_handle *nic = &vport->nic;
1998
887c3820 1999 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 2000
2001 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2002 vport->back->num_msi_left == 0)
2003 return -EINVAL;
2004
2005 roce->rinfo.base_vector = vport->back->roce_base_vector;
2006
2007 roce->rinfo.netdev = nic->kinfo.netdev;
2008 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2009
2010 roce->pdev = nic->pdev;
2011 roce->ae_algo = nic->ae_algo;
2012 roce->numa_node_mask = nic->numa_node_mask;
2013
2014 return 0;
2015}
2016
887c3820 2017static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 2018{
2019 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 2020 int vectors;
2021 int i;
46a3df9f 2022
887c3820
SM		 2023 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2024 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2025 if (vectors < 0) {
2026 dev_err(&pdev->dev,
2027 "failed(%d) to allocate MSI/MSI-X vectors\n",
2028 vectors);
2029 return vectors;
46a3df9f 2030 }
887c3820
SM		 2031 if (vectors < hdev->num_msi)
2032 dev_warn(&hdev->pdev->dev,
2033 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2034 hdev->num_msi, vectors);
46a3df9f 2035
887c3820
SM		 2036 hdev->num_msi = vectors;
2037 hdev->num_msi_left = vectors;
2038 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 2039 hdev->roce_base_vector = hdev->base_msi_vector +
2040 HCLGE_ROCE_VECTOR_OFFSET;
2041
46a3df9f
S		 2042 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2043 sizeof(u16), GFP_KERNEL);
887c3820
SM		 2044 if (!hdev->vector_status) {
2045 pci_free_irq_vectors(pdev);
46a3df9f 2046 return -ENOMEM;
887c3820 2047 }
46a3df9f
S		 2048
2049 for (i = 0; i < hdev->num_msi; i++)
2050 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2051
887c3820
SM		 2052 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2053 sizeof(int), GFP_KERNEL);
2054 if (!hdev->vector_irq) {
2055 pci_free_irq_vectors(pdev);
2056 return -ENOMEM;
46a3df9f 2057 }
46a3df9f
S		 2058
2059 return 0;
2060}
2061
2062static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2063{
2064 struct hclge_mac *mac = &hdev->hw.mac;
2065
2066 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2067 mac->duplex = (u8)duplex;
2068 else
2069 mac->duplex = HCLGE_MAC_FULL;
2070
2071 mac->speed = speed;
2072}
2073
2074int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2075{
d44f9b63 2076 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2077 struct hclge_desc desc;
2078 int ret;
2079
d44f9b63 2080 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2081
2082 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2083
e22b531b 2084 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 2085
2086 switch (speed) {
2087 case HCLGE_MAC_SPEED_10M:
e22b531b
HT		 2088 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2089 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 2090 break;
2091 case HCLGE_MAC_SPEED_100M:
e22b531b
HT		 2092 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2093 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 2094 break;
2095 case HCLGE_MAC_SPEED_1G:
e22b531b
HT		 2096 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2097 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 2098 break;
2099 case HCLGE_MAC_SPEED_10G:
e22b531b
HT		 2100 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2101 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 2102 break;
2103 case HCLGE_MAC_SPEED_25G:
e22b531b
HT		 2104 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2105 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 2106 break;
2107 case HCLGE_MAC_SPEED_40G:
e22b531b
HT		 2108 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2109 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 2110 break;
2111 case HCLGE_MAC_SPEED_50G:
e22b531b
HT		 2112 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2113 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 2114 break;
2115 case HCLGE_MAC_SPEED_100G:
e22b531b
HT		 2116 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2117 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 2118 break;
2119 default:
d7629e74 2120 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2121 return -EINVAL;
2122 }
2123
e22b531b
HT		 2124 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2125 1);
46a3df9f
S		 2126
2127 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2128 if (ret) {
2129 dev_err(&hdev->pdev->dev,
2130 "mac speed/duplex config cmd failed %d.\n", ret);
2131 return ret;
2132 }
2133
2134 hclge_check_speed_dup(hdev, duplex, speed);
2135
2136 return 0;
2137}
2138
2139static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2140 u8 duplex)
2141{
2142 struct hclge_vport *vport = hclge_get_vport(handle);
2143 struct hclge_dev *hdev = vport->back;
2144
2145 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2146}
2147
2148static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2149 u8 *duplex)
2150{
d44f9b63 2151 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2152 struct hclge_desc desc;
2153 int speed_tmp;
2154 int ret;
2155
d44f9b63 2156 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2157
2158 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2159 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2160 if (ret) {
2161 dev_err(&hdev->pdev->dev,
2162 "mac speed/autoneg/duplex query cmd failed %d\n",
2163 ret);
2164 return ret;
2165 }
2166
e22b531b
HT		 2167 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2168 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2169 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 2170
2171 ret = hclge_parse_speed(speed_tmp, speed);
e125295a 2172 if (ret)
46a3df9f
S		 2173 dev_err(&hdev->pdev->dev,
2174 "could not parse speed(=%d), %d\n", speed_tmp, ret);
46a3df9f 2175
e125295a 2176 return ret;
46a3df9f
S		 2177}
2178
46a3df9f
S		 2179static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2180{
d44f9b63 2181 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2182 struct hclge_desc desc;
a90bb9a5 2183 u32 flag = 0;
46a3df9f
S		 2184 int ret;
2185
2186 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2187
d44f9b63 2188 req = (struct hclge_config_auto_neg_cmd *)desc.data;
e22b531b 2189 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 2190 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2191
2192 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 2193 if (ret)
46a3df9f
S		 2194 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2195 ret);
46a3df9f 2196
e125295a 2197 return ret;
46a3df9f
S		 2198}
2199
2200static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2201{
2202 struct hclge_vport *vport = hclge_get_vport(handle);
2203 struct hclge_dev *hdev = vport->back;
2204
2205 return hclge_set_autoneg_en(hdev, enable);
2206}
2207
2208static int hclge_get_autoneg(struct hnae3_handle *handle)
2209{
2210 struct hclge_vport *vport = hclge_get_vport(handle);
2211 struct hclge_dev *hdev = vport->back;
9ff804ee
FL		 2212 struct phy_device *phydev = hdev->hw.mac.phydev;
2213
2214 if (phydev)
2215 return phydev->autoneg;
46a3df9f
S		 2216
2217 return hdev->hw.mac.autoneg;
2218}
2219
6f712727
PL		 2220static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2221 bool mask_vlan,
2222 u8 *mac_mask)
2223{
2224 struct hclge_mac_vlan_mask_entry_cmd *req;
2225 struct hclge_desc desc;
2226 int status;
2227
2228 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2229 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2230
e22b531b
HT		 2231 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2232 mask_vlan ? 1 : 0);
6f712727
PL		 2233 ether_addr_copy(req->mac_mask, mac_mask);
2234
2235 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2236 if (status)
2237 dev_err(&hdev->pdev->dev,
2238 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2239 status);
2240
2241 return status;
2242}
2243
46a3df9f
S		 2244static int hclge_mac_init(struct hclge_dev *hdev)
2245{
59bc85ec
FL		 2246 struct hnae3_handle *handle = &hdev->vport[0].nic;
2247 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 2248 struct hclge_mac *mac = &hdev->hw.mac;
6f712727 2249 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
a832d8b5 2250 struct hclge_vport *vport;
59bc85ec 2251 int mtu;
46a3df9f 2252 int ret;
a832d8b5 2253 int i;
46a3df9f
S		 2254
2255 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2256 if (ret) {
2257 dev_err(&hdev->pdev->dev,
2258 "Config mac speed dup fail ret=%d\n", ret);
2259 return ret;
2260 }
2261
2262 mac->link = 0;
2263
46a3df9f 2264 /* Initialize the MTA table work mode */
46a3df9f
S		 2265 hdev->enable_mta = true;
2266 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2267
2268 ret = hclge_set_mta_filter_mode(hdev,
2269 hdev->mta_mac_sel_type,
2270 hdev->enable_mta);
2271 if (ret) {
2272 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2273 ret);
2274 return ret;
2275 }
2276
a832d8b5
XW		 2277 for (i = 0; i < hdev->num_alloc_vport; i++) {
2278 vport = &hdev->vport[i];
2279 vport->accept_mta_mc = false;
2280
2281 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2282 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2283 if (ret) {
2284 dev_err(&hdev->pdev->dev,
2285 "set mta filter mode fail ret=%d\n", ret);
2286 return ret;
2287 }
6f712727
PL		 2288 }
2289
2290 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
59bc85ec 2291 if (ret) {
6f712727
PL		 2292 dev_err(&hdev->pdev->dev,
2293 "set default mac_vlan_mask fail ret=%d\n", ret);
59bc85ec
FL		 2294 return ret;
2295 }
6f712727 2296
59bc85ec
FL		 2297 if (netdev)
2298 mtu = netdev->mtu;
2299 else
2300 mtu = ETH_DATA_LEN;
2301
2302 ret = hclge_set_mtu(handle, mtu);
e125295a 2303 if (ret)
59bc85ec
FL		 2304 dev_err(&hdev->pdev->dev,
2305 "set mtu failed ret=%d\n", ret);
59bc85ec 2306
e125295a 2307 return ret;
46a3df9f
S		 2308}
2309
22fd3468
SM		 2310static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2311{
2312 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2313 schedule_work(&hdev->mbx_service_task);
2314}
2315
ed4a1bb8
SM		 2316static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2317{
2318 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2319 schedule_work(&hdev->rst_service_task);
2320}
2321
46a3df9f
S		 2322static void hclge_task_schedule(struct hclge_dev *hdev)
2323{
2324 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2325 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2326 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2327 (void)schedule_work(&hdev->service_task);
2328}
2329
2330static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2331{
d44f9b63 2332 struct hclge_link_status_cmd *req;
46a3df9f
S		 2333 struct hclge_desc desc;
2334 int link_status;
2335 int ret;
2336
2337 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2338 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2339 if (ret) {
2340 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2341 ret);
2342 return ret;
2343 }
2344
d44f9b63 2345 req = (struct hclge_link_status_cmd *)desc.data;
b28556c9 2346 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
46a3df9f
S		 2347
2348 return !!link_status;
2349}
2350
2351static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2352{
2353 int mac_state;
2354 int link_stat;
2355
2356 mac_state = hclge_get_mac_link_status(hdev);
2357
2358 if (hdev->hw.mac.phydev) {
2359 if (!genphy_read_status(hdev->hw.mac.phydev))
2360 link_stat = mac_state &
2361 hdev->hw.mac.phydev->link;
2362 else
2363 link_stat = 0;
2364
2365 } else {
2366 link_stat = mac_state;
2367 }
2368
2369 return !!link_stat;
2370}
2371
2372static void hclge_update_link_status(struct hclge_dev *hdev)
2373{
15a50665 2374 struct hnae3_client *rclient = hdev->roce_client;
46a3df9f 2375 struct hnae3_client *client = hdev->nic_client;
bc0b7416 2376 struct hnae3_handle *rhandle;
46a3df9f
S		 2377 struct hnae3_handle *handle;
2378 int state;
2379 int i;
2380
2381 if (!client)
2382 return;
2383 state = hclge_get_mac_phy_link(hdev);
2384 if (state != hdev->hw.mac.link) {
2385 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2386 handle = &hdev->vport[i].nic;
2387 client->ops->link_status_change(handle, state);
bc0b7416 2388 rhandle = &hdev->vport[i].roce;
15a50665 2389 if (rclient && rclient->ops->link_status_change)
bc0b7416
WHX		 2390 rclient->ops->link_status_change(rhandle,
2391 state);
46a3df9f
S		 2392 }
2393 hdev->hw.mac.link = state;
2394 }
2395}
2396
2397static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2398{
2399 struct hclge_mac mac = hdev->hw.mac;
2400 u8 duplex;
2401 int speed;
2402 int ret;
2403
2404 /* get the speed and duplex as autoneg'result from mac cmd when phy
2405 * doesn't exit.
2406 */
c040366b 2407 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2408 return 0;
2409
2410 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2411 if (ret) {
2412 dev_err(&hdev->pdev->dev,
2413 "mac autoneg/speed/duplex query failed %d\n", ret);
2414 return ret;
2415 }
2416
2417 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2418 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2419 if (ret) {
2420 dev_err(&hdev->pdev->dev,
2421 "mac speed/duplex config failed %d\n", ret);
2422 return ret;
2423 }
2424 }
2425
2426 return 0;
2427}
2428
2429static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2430{
2431 struct hclge_vport *vport = hclge_get_vport(handle);
2432 struct hclge_dev *hdev = vport->back;
2433
2434 return hclge_update_speed_duplex(hdev);
2435}
2436
2437static int hclge_get_status(struct hnae3_handle *handle)
2438{
2439 struct hclge_vport *vport = hclge_get_vport(handle);
2440 struct hclge_dev *hdev = vport->back;
2441
2442 hclge_update_link_status(hdev);
2443
2444 return hdev->hw.mac.link;
2445}
2446
d039ef68 2447static void hclge_service_timer(struct timer_list *t)
46a3df9f 2448{
d039ef68 2449 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2450
d039ef68 2451 mod_timer(&hdev->service_timer, jiffies + HZ);
7a5d2a39 2452 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2453 hclge_task_schedule(hdev);
2454}
2455
2456static void hclge_service_complete(struct hclge_dev *hdev)
2457{
2458 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2459
2460 /* Flush memory before next watchdog */
2461 smp_mb__before_atomic();
2462 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2463}
2464
202f2014
SM		 2465static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2466{
2467 u32 rst_src_reg;
22fd3468 2468 u32 cmdq_src_reg;
202f2014
SM		 2469
2470 /* fetch the events from their corresponding regs */
2471 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
22fd3468
SM		 2472 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2473
2474 /* Assumption: If by any chance reset and mailbox events are reported
2475 * together then we will only process reset event in this go and will
2476 * defer the processing of the mailbox events. Since, we would have not
2477 * cleared RX CMDQ event this time we would receive again another
2478 * interrupt from H/W just for the mailbox.
2479 */
202f2014
SM		 2480
2481 /* check for vector0 reset event sources */
2482 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2483 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2484 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2485 return HCLGE_VECTOR0_EVENT_RST;
2486 }
2487
2488 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2489 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2490 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2491 return HCLGE_VECTOR0_EVENT_RST;
2492 }
2493
2494 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2495 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2496 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2497 return HCLGE_VECTOR0_EVENT_RST;
2498 }
2499
22fd3468
SM		 2500 /* check for vector0 mailbox(=CMDQ RX) event source */
2501 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2502 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2503 *clearval = cmdq_src_reg;
2504 return HCLGE_VECTOR0_EVENT_MBX;
2505 }
202f2014
SM		 2506
2507 return HCLGE_VECTOR0_EVENT_OTHER;
2508}
2509
2510static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2511 u32 regclr)
2512{
22fd3468
SM		 2513 switch (event_type) {
2514 case HCLGE_VECTOR0_EVENT_RST:
202f2014 2515 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
22fd3468
SM		 2516 break;
2517 case HCLGE_VECTOR0_EVENT_MBX:
2518 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2519 break;
2520 }
202f2014
SM		 2521}
2522
466b0c00
L		 2523static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2524{
2525 writel(enable ? 1 : 0, vector->addr);
2526}
2527
2528static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2529{
2530 struct hclge_dev *hdev = data;
202f2014
SM		 2531 u32 event_cause;
2532 u32 clearval;
466b0c00
L		 2533
2534 hclge_enable_vector(&hdev->misc_vector, false);
202f2014
SM		 2535 event_cause = hclge_check_event_cause(hdev, &clearval);
2536
22fd3468 2537 /* vector 0 interrupt is shared with reset and mailbox source events.*/
202f2014
SM		 2538 switch (event_cause) {
2539 case HCLGE_VECTOR0_EVENT_RST:
ed4a1bb8 2540 hclge_reset_task_schedule(hdev);
202f2014 2541 break;
22fd3468
SM		 2542 case HCLGE_VECTOR0_EVENT_MBX:
2543 /* If we are here then,
2544 * 1. Either we are not handling any mbx task and we are not
2545 * scheduled as well
2546 * OR
2547 * 2. We could be handling a mbx task but nothing more is
2548 * scheduled.
2549 * In both cases, we should schedule mbx task as there are more
2550 * mbx messages reported by this interrupt.
2551 */
2552 hclge_mbx_task_schedule(hdev);
40ee4b71 2553 break;
202f2014 2554 default:
40ee4b71
YL		 2555 dev_warn(&hdev->pdev->dev,
2556 "received unknown or unhandled event of vector0\n");
202f2014
SM		 2557 break;
2558 }
2559
e9a50d09
YL		 2560 /* clear the source of interrupt if it is not cause by reset */
2561 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2562 hclge_clear_event_cause(hdev, event_cause, clearval);
2563 hclge_enable_vector(&hdev->misc_vector, true);
2564 }
466b0c00
L		 2565
2566 return IRQ_HANDLED;
2567}
2568
2569static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2570{
617cb5a2
PL		 2571 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2572 dev_warn(&hdev->pdev->dev,
2573 "vector(vector_id %d) has been freed.\n", vector_id);
2574 return;
2575 }
2576
466b0c00
L		 2577 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2578 hdev->num_msi_left += 1;
2579 hdev->num_msi_used -= 1;
2580}
2581
2582static void hclge_get_misc_vector(struct hclge_dev *hdev)
2583{
2584 struct hclge_misc_vector *vector = &hdev->misc_vector;
2585
2586 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2587
2588 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2589 hdev->vector_status[0] = 0;
2590
2591 hdev->num_msi_left -= 1;
2592 hdev->num_msi_used += 1;
2593}
2594
2595static int hclge_misc_irq_init(struct hclge_dev *hdev)
2596{
2597 int ret;
2598
2599 hclge_get_misc_vector(hdev);
2600
202f2014
SM		 2601 /* this would be explicitly freed in the end */
2602 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2603 0, "hclge_misc", hdev);
466b0c00
L		 2604 if (ret) {
2605 hclge_free_vector(hdev, 0);
2606 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2607 hdev->misc_vector.vector_irq);
2608 }
2609
2610 return ret;
2611}
2612
202f2014
SM		 2613static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2614{
2615 free_irq(hdev->misc_vector.vector_irq, hdev);
2616 hclge_free_vector(hdev, 0);
2617}
2618
4ed340ab
L		 2619static int hclge_notify_client(struct hclge_dev *hdev,
2620 enum hnae3_reset_notify_type type)
2621{
2e5ed0d2 2622 struct hnae3_client *rclient = hdev->roce_client;
4ed340ab 2623 struct hnae3_client *client = hdev->nic_client;
d3f5c892
LO		 2624 struct hnae3_handle *handle;
2625 int ret;
4ed340ab
L		 2626 u16 i;
2627
2628 if (!client->ops->reset_notify)
2629 return -EOPNOTSUPP;
2630
2631 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
d3f5c892 2632 handle = &hdev->vport[i].nic;
4ed340ab 2633 ret = client->ops->reset_notify(handle, type);
2e5ed0d2
WHX		 2634 if (ret) {
2635 dev_err(&hdev->pdev->dev,
2636 "notify nic client failed %d", ret);
4ed340ab 2637 return ret;
2e5ed0d2 2638 }
d3f5c892 2639
2e5ed0d2 2640 if (rclient && rclient->ops->reset_notify) {
d3f5c892 2641 handle = &hdev->vport[i].roce;
2e5ed0d2
WHX		 2642 ret = rclient->ops->reset_notify(handle, type);
2643 if (ret) {
2644 dev_err(&hdev->pdev->dev,
2645 "notify roce client failed %d", ret);
2646 return ret;
2647 }
d3f5c892 2648 }
4ed340ab
L		 2649 }
2650
2651 return 0;
2652}
2653
2654static int hclge_reset_wait(struct hclge_dev *hdev)
2655{
2656#define HCLGE_RESET_WATI_MS 100
2657#define HCLGE_RESET_WAIT_CNT 5
2658 u32 val, reg, reg_bit;
2659 u32 cnt = 0;
2660
2661 switch (hdev->reset_type) {
2662 case HNAE3_GLOBAL_RESET:
2663 reg = HCLGE_GLOBAL_RESET_REG;
2664 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2665 break;
2666 case HNAE3_CORE_RESET:
2667 reg = HCLGE_GLOBAL_RESET_REG;
2668 reg_bit = HCLGE_CORE_RESET_BIT;
2669 break;
2670 case HNAE3_FUNC_RESET:
2671 reg = HCLGE_FUN_RST_ING;
2672 reg_bit = HCLGE_FUN_RST_ING_B;
2673 break;
2674 default:
2675 dev_err(&hdev->pdev->dev,
2676 "Wait for unsupported reset type: %d\n",
2677 hdev->reset_type);
2678 return -EINVAL;
2679 }
2680
2681 val = hclge_read_dev(&hdev->hw, reg);
e22b531b
HT		 2682 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT &&
2683 test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
4ed340ab
L		 2684 msleep(HCLGE_RESET_WATI_MS);
2685 val = hclge_read_dev(&hdev->hw, reg);
2686 cnt++;
2687 }
2688
4ed340ab
L		 2689 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2690 dev_warn(&hdev->pdev->dev,
2691 "Wait for reset timeout: %d\n", hdev->reset_type);
2692 return -EBUSY;
2693 }
2694
2695 return 0;
2696}
2697
13a86fae 2698int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2699{
2700 struct hclge_desc desc;
2701 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2702 int ret;
2703
2704 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
e22b531b 2705 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2706 req->fun_reset_vfid = func_id;
2707
2708 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2709 if (ret)
2710 dev_err(&hdev->pdev->dev,
2711 "send function reset cmd fail, status =%d\n", ret);
2712
2713 return ret;
2714}
2715
d5752031 2716static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2717{
2718 struct pci_dev *pdev = hdev->pdev;
2719 u32 val;
2720
d5752031 2721 switch (hdev->reset_type) {
4ed340ab
L		 2722 case HNAE3_GLOBAL_RESET:
2723 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e22b531b 2724 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2725 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2726 dev_info(&pdev->dev, "Global Reset requested\n");
2727 break;
2728 case HNAE3_CORE_RESET:
2729 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e22b531b 2730 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2731 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2732 dev_info(&pdev->dev, "Core Reset requested\n");
2733 break;
2734 case HNAE3_FUNC_RESET:
2735 dev_info(&pdev->dev, "PF Reset requested\n");
2736 hclge_func_reset_cmd(hdev, 0);
ed4a1bb8
SM		 2737 /* schedule again to check later */
2738 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2739 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2740 break;
2741 default:
2742 dev_warn(&pdev->dev,
d5752031 2743 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2744 break;
2745 }
2746}
2747
d5752031
SM		 2748static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2749 unsigned long *addr)
2750{
2751 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2752
2753 /* return the highest priority reset level amongst all */
2754 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2755 rst_level = HNAE3_GLOBAL_RESET;
2756 else if (test_bit(HNAE3_CORE_RESET, addr))
2757 rst_level = HNAE3_CORE_RESET;
2758 else if (test_bit(HNAE3_IMP_RESET, addr))
2759 rst_level = HNAE3_IMP_RESET;
2760 else if (test_bit(HNAE3_FUNC_RESET, addr))
2761 rst_level = HNAE3_FUNC_RESET;
2762
2763 /* now, clear all other resets */
2764 clear_bit(HNAE3_GLOBAL_RESET, addr);
2765 clear_bit(HNAE3_CORE_RESET, addr);
2766 clear_bit(HNAE3_IMP_RESET, addr);
2767 clear_bit(HNAE3_FUNC_RESET, addr);
2768
2769 return rst_level;
2770}
2771
e9a50d09
YL		 2772static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2773{
2774 u32 clearval = 0;
2775
2776 switch (hdev->reset_type) {
2777 case HNAE3_IMP_RESET:
2778 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2779 break;
2780 case HNAE3_GLOBAL_RESET:
2781 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2782 break;
2783 case HNAE3_CORE_RESET:
2784 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2785 break;
2786 default:
e9a50d09
YL		 2787 break;
2788 }
2789
2790 if (!clearval)
2791 return;
2792
2793 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2794 hclge_enable_vector(&hdev->misc_vector, true);
2795}
2796
d5752031
SM		 2797static void hclge_reset(struct hclge_dev *hdev)
2798{
2799 /* perform reset of the stack & ae device for a client */
2800
2801 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2802
2803 if (!hclge_reset_wait(hdev)) {
2804 rtnl_lock();
2805 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2806 hclge_reset_ae_dev(hdev->ae_dev);
2807 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2808 rtnl_unlock();
e9a50d09
YL		 2809
2810 hclge_clear_reset_cause(hdev);
d5752031
SM		 2811 } else {
2812 /* schedule again to check pending resets later */
2813 set_bit(hdev->reset_type, &hdev->reset_pending);
2814 hclge_reset_task_schedule(hdev);
2815 }
2816
2817 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2818}
2819
4aef908d 2820static void hclge_reset_event(struct hnae3_handle *handle)
4ed340ab
L		 2821{
2822 struct hclge_vport *vport = hclge_get_vport(handle);
2823 struct hclge_dev *hdev = vport->back;
2824
4aef908d
SM		 2825 /* check if this is a new reset request and we are not here just because
2826 * last reset attempt did not succeed and watchdog hit us again. We will
2827 * know this if last reset request did not occur very recently (watchdog
2828 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2829 * In case of new request we reset the "reset level" to PF reset.
2830 */
2831 if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
2832 handle->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2833
4aef908d
SM		 2834 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2835 handle->reset_level);
2836
2837 /* request reset & schedule reset task */
2838 set_bit(handle->reset_level, &hdev->reset_request);
2839 hclge_reset_task_schedule(hdev);
2840
2841 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2842 handle->reset_level++;
2843
2844 handle->last_reset_time = jiffies;
4ed340ab
L		 2845}
2846
2847static void hclge_reset_subtask(struct hclge_dev *hdev)
2848{
d5752031
SM		 2849 /* check if there is any ongoing reset in the hardware. This status can
2850 * be checked from reset_pending. If there is then, we need to wait for
2851 * hardware to complete reset.
2852 * a. If we are able to figure out in reasonable time that hardware
2853 * has fully resetted then, we can proceed with driver, client
2854 * reset.
2855 * b. else, we can come back later to check this status so re-sched
2856 * now.
2857 */
2858 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2859 if (hdev->reset_type != HNAE3_NONE_RESET)
2860 hclge_reset(hdev);
4ed340ab 2861
d5752031
SM		 2862 /* check if we got any *new* reset requests to be honored */
2863 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2864 if (hdev->reset_type != HNAE3_NONE_RESET)
2865 hclge_do_reset(hdev);
4ed340ab 2866
4ed340ab
L		 2867 hdev->reset_type = HNAE3_NONE_RESET;
2868}
2869
ed4a1bb8 2870static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2871{
ed4a1bb8
SM		 2872 struct hclge_dev *hdev =
2873 container_of(work, struct hclge_dev, rst_service_task);
2874
2875 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2876 return;
2877
2878 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2879
4ed340ab 2880 hclge_reset_subtask(hdev);
ed4a1bb8
SM		 2881
2882 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2883}
2884
22fd3468
SM		 2885static void hclge_mailbox_service_task(struct work_struct *work)
2886{
2887 struct hclge_dev *hdev =
2888 container_of(work, struct hclge_dev, mbx_service_task);
2889
2890 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2891 return;
2892
2893 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2894
2895 hclge_mbx_handler(hdev);
2896
2897 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2898}
2899
46a3df9f
S		 2900static void hclge_service_task(struct work_struct *work)
2901{
2902 struct hclge_dev *hdev =
2903 container_of(work, struct hclge_dev, service_task);
2904
7a5d2a39
JS		 2905 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2906 hclge_update_stats_for_all(hdev);
2907 hdev->hw_stats.stats_timer = 0;
2908 }
2909
46a3df9f
S		 2910 hclge_update_speed_duplex(hdev);
2911 hclge_update_link_status(hdev);
46a3df9f
S		 2912 hclge_service_complete(hdev);
2913}
2914
46a3df9f
S		 2915struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2916{
2917 /* VF handle has no client */
2918 if (!handle->client)
2919 return container_of(handle, struct hclge_vport, nic);
2920 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2921 return container_of(handle, struct hclge_vport, roce);
2922 else
2923 return container_of(handle, struct hclge_vport, nic);
2924}
2925
2926static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2927 struct hnae3_vector_info *vector_info)
2928{
2929 struct hclge_vport *vport = hclge_get_vport(handle);
2930 struct hnae3_vector_info *vector = vector_info;
2931 struct hclge_dev *hdev = vport->back;
2932 int alloc = 0;
2933 int i, j;
2934
2935 vector_num = min(hdev->num_msi_left, vector_num);
2936
2937 for (j = 0; j < vector_num; j++) {
2938 for (i = 1; i < hdev->num_msi; i++) {
2939 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2940 vector->vector = pci_irq_vector(hdev->pdev, i);
2941 vector->io_addr = hdev->hw.io_base +
2942 HCLGE_VECTOR_REG_BASE +
2943 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2944 vport->vport_id *
2945 HCLGE_VECTOR_VF_OFFSET;
2946 hdev->vector_status[i] = vport->vport_id;
887c3820 2947 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2948
2949 vector++;
2950 alloc++;
2951
2952 break;
2953 }
2954 }
2955 }
2956 hdev->num_msi_left -= alloc;
2957 hdev->num_msi_used += alloc;
2958
2959 return alloc;
2960}
2961
2962static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2963{
2964 int i;
2965
887c3820
SM		 2966 for (i = 0; i < hdev->num_msi; i++)
2967 if (vector == hdev->vector_irq[i])
2968 return i;
2969
46a3df9f
S		 2970 return -EINVAL;
2971}
2972
7412200c
YL		 2973static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2974{
2975 struct hclge_vport *vport = hclge_get_vport(handle);
2976 struct hclge_dev *hdev = vport->back;
2977 int vector_id;
2978
2979 vector_id = hclge_get_vector_index(hdev, vector);
2980 if (vector_id < 0) {
2981 dev_err(&hdev->pdev->dev,
2982 "Get vector index fail. vector_id =%d\n", vector_id);
2983 return vector_id;
2984 }
2985
2986 hclge_free_vector(hdev, vector_id);
2987
2988 return 0;
2989}
2990
46a3df9f
S		 2991static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2992{
2993 return HCLGE_RSS_KEY_SIZE;
2994}
2995
2996static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2997{
2998 return HCLGE_RSS_IND_TBL_SIZE;
2999}
3000
46a3df9f
S		 3001static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3002 const u8 hfunc, const u8 *key)
3003{
d44f9b63 3004 struct hclge_rss_config_cmd *req;
46a3df9f
S		 3005 struct hclge_desc desc;
3006 int key_offset;
3007 int key_size;
3008 int ret;
3009
d44f9b63 3010 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 3011
3012 for (key_offset = 0; key_offset < 3; key_offset++) {
3013 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3014 false);
3015
3016 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3017 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3018
3019 if (key_offset == 2)
3020 key_size =
3021 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3022 else
3023 key_size = HCLGE_RSS_HASH_KEY_NUM;
3024
3025 memcpy(req->hash_key,
3026 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3027
3028 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3029 if (ret) {
3030 dev_err(&hdev->pdev->dev,
3031 "Configure RSS config fail, status = %d\n",
3032 ret);
3033 return ret;
3034 }
3035 }
3036 return 0;
3037}
3038
dcd4ef5e 3039static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3040{
d44f9b63 3041 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3042 struct hclge_desc desc;
3043 int i, j;
3044 int ret;
3045
d44f9b63 3046 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3047
3048 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3049 hclge_cmd_setup_basic_desc
3050 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3051
a90bb9a5
YL		 3052 req->start_table_index =
3053 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3054 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3055
3056 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3057 req->rss_result[j] =
3058 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3059
3060 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3061 if (ret) {
3062 dev_err(&hdev->pdev->dev,
3063 "Configure rss indir table fail,status = %d\n",
3064 ret);
3065 return ret;
3066 }
3067 }
3068 return 0;
3069}
3070
3071static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3072 u16 *tc_size, u16 *tc_offset)
3073{
d44f9b63 3074 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3075 struct hclge_desc desc;
3076 int ret;
3077 int i;
3078
3079 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3080 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3081
3082 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3083 u16 mode = 0;
3084
e22b531b
HT		 3085 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3086 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3087 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3088 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3089 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3090
3091 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3092 }
3093
3094 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3095 if (ret)
46a3df9f
S		 3096 dev_err(&hdev->pdev->dev,
3097 "Configure rss tc mode fail, status = %d\n", ret);
46a3df9f 3098
e125295a 3099 return ret;
46a3df9f
S		 3100}
3101
3102static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3103{
d44f9b63 3104 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3105 struct hclge_desc desc;
3106 int ret;
3107
3108 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3109
d44f9b63 3110 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef
YL		 3111
3112 /* Get the tuple cfg from pf */
3113 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3114 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3115 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3116 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3117 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3118 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3119 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3120 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
46a3df9f 3121 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3122 if (ret)
46a3df9f
S		 3123 dev_err(&hdev->pdev->dev,
3124 "Configure rss input fail, status = %d\n", ret);
e125295a 3125 return ret;
46a3df9f
S		 3126}
3127
3128static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3129 u8 *key, u8 *hfunc)
3130{
3131 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3132 int i;
3133
3134 /* Get hash algorithm */
3135 if (hfunc)
dcd4ef5e 3136 *hfunc = vport->rss_algo;
46a3df9f
S		 3137
3138 /* Get the RSS Key required by the user */
3139 if (key)
3140 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3141
3142 /* Get indirect table */
3143 if (indir)
3144 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3145 indir[i] = vport->rss_indirection_tbl[i];
3146
3147 return 0;
3148}
3149
3150static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3151 const u8 *key, const u8 hfunc)
3152{
3153 struct hclge_vport *vport = hclge_get_vport(handle);
3154 struct hclge_dev *hdev = vport->back;
3155 u8 hash_algo;
3156 int ret, i;
3157
3158 /* Set the RSS Hash Key if specififed by the user */
3159 if (key) {
46a3df9f
S		 3160
3161 if (hfunc == ETH_RSS_HASH_TOP ||
3162 hfunc == ETH_RSS_HASH_NO_CHANGE)
3163 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3164 else
3165 return -EINVAL;
3166 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3167 if (ret)
3168 return ret;
dcd4ef5e
YL		 3169
3170 /* Update the shadow RSS key with user specified qids */
3171 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3172 vport->rss_algo = hash_algo;
46a3df9f
S		 3173 }
3174
3175 /* Update the shadow RSS table with user specified qids */
3176 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3177 vport->rss_indirection_tbl[i] = indir[i];
3178
3179 /* Update the hardware */
dcd4ef5e 3180 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3181}
3182
f7db940a
L		 3183static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3184{
3185 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3186
3187 if (nfc->data & RXH_L4_B_2_3)
3188 hash_sets |= HCLGE_D_PORT_BIT;
3189 else
3190 hash_sets &= ~HCLGE_D_PORT_BIT;
3191
3192 if (nfc->data & RXH_IP_SRC)
3193 hash_sets |= HCLGE_S_IP_BIT;
3194 else
3195 hash_sets &= ~HCLGE_S_IP_BIT;
3196
3197 if (nfc->data & RXH_IP_DST)
3198 hash_sets |= HCLGE_D_IP_BIT;
3199 else
3200 hash_sets &= ~HCLGE_D_IP_BIT;
3201
3202 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3203 hash_sets |= HCLGE_V_TAG_BIT;
3204
3205 return hash_sets;
3206}
3207
3208static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3209 struct ethtool_rxnfc *nfc)
3210{
3211 struct hclge_vport *vport = hclge_get_vport(handle);
3212 struct hclge_dev *hdev = vport->back;
3213 struct hclge_rss_input_tuple_cmd *req;
3214 struct hclge_desc desc;
3215 u8 tuple_sets;
3216 int ret;
3217
3218 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3219 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3220 return -EINVAL;
3221
3222 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef 3223 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 3224
637053ef
YL		 3225 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3226 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3227 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3228 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3229 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3230 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3231 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3232 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 3233
3234 tuple_sets = hclge_get_rss_hash_bits(nfc);
3235 switch (nfc->flow_type) {
3236 case TCP_V4_FLOW:
3237 req->ipv4_tcp_en = tuple_sets;
3238 break;
3239 case TCP_V6_FLOW:
3240 req->ipv6_tcp_en = tuple_sets;
3241 break;
3242 case UDP_V4_FLOW:
3243 req->ipv4_udp_en = tuple_sets;
3244 break;
3245 case UDP_V6_FLOW:
3246 req->ipv6_udp_en = tuple_sets;
3247 break;
3248 case SCTP_V4_FLOW:
3249 req->ipv4_sctp_en = tuple_sets;
3250 break;
3251 case SCTP_V6_FLOW:
3252 if ((nfc->data & RXH_L4_B_0_1) ||
3253 (nfc->data & RXH_L4_B_2_3))
3254 return -EINVAL;
3255
3256 req->ipv6_sctp_en = tuple_sets;
3257 break;
3258 case IPV4_FLOW:
3259 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3260 break;
3261 case IPV6_FLOW:
3262 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3263 break;
3264 default:
3265 return -EINVAL;
3266 }
3267
3268 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
637053ef 3269 if (ret) {
f7db940a
L		 3270 dev_err(&hdev->pdev->dev,
3271 "Set rss tuple fail, status = %d\n", ret);
637053ef
YL		 3272 return ret;
3273 }
f7db940a 3274
637053ef
YL		 3275 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3276 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3277 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3278 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3279 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3280 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3281 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3282 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3283 return 0;
f7db940a
L		 3284}
3285
07d29954
L		 3286static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3287 struct ethtool_rxnfc *nfc)
3288{
3289 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3290 u8 tuple_sets;
07d29954
L		 3291
3292 nfc->data = 0;
3293
07d29954
L		 3294 switch (nfc->flow_type) {
3295 case TCP_V4_FLOW:
637053ef 3296 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3297 break;
3298 case UDP_V4_FLOW:
637053ef 3299 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3300 break;
3301 case TCP_V6_FLOW:
637053ef 3302 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3303 break;
3304 case UDP_V6_FLOW:
637053ef 3305 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3306 break;
3307 case SCTP_V4_FLOW:
637053ef 3308 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3309 break;
3310 case SCTP_V6_FLOW:
637053ef 3311 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3312 break;
3313 case IPV4_FLOW:
3314 case IPV6_FLOW:
3315 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3316 break;
3317 default:
3318 return -EINVAL;
3319 }
3320
3321 if (!tuple_sets)
3322 return 0;
3323
3324 if (tuple_sets & HCLGE_D_PORT_BIT)
3325 nfc->data |= RXH_L4_B_2_3;
3326 if (tuple_sets & HCLGE_S_PORT_BIT)
3327 nfc->data |= RXH_L4_B_0_1;
3328 if (tuple_sets & HCLGE_D_IP_BIT)
3329 nfc->data |= RXH_IP_DST;
3330 if (tuple_sets & HCLGE_S_IP_BIT)
3331 nfc->data |= RXH_IP_SRC;
3332
3333 return 0;
3334}
3335
46a3df9f
S		 3336static int hclge_get_tc_size(struct hnae3_handle *handle)
3337{
3338 struct hclge_vport *vport = hclge_get_vport(handle);
3339 struct hclge_dev *hdev = vport->back;
3340
3341 return hdev->rss_size_max;
3342}
3343
77f255c1 3344int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3345{
46a3df9f 3346 struct hclge_vport *vport = hdev->vport;
8015bb74
YL		 3347 u8 *rss_indir = vport[0].rss_indirection_tbl;
3348 u16 rss_size = vport[0].alloc_rss_size;
3349 u8 *key = vport[0].rss_hash_key;
3350 u8 hfunc = vport[0].rss_algo;
46a3df9f 3351 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3352 u16 tc_valid[HCLGE_MAX_TC_NUM];
3353 u16 tc_size[HCLGE_MAX_TC_NUM];
8015bb74
YL		 3354 u16 roundup_size;
3355 int i, ret;
68ece54e 3356
46a3df9f
S		 3357 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3358 if (ret)
8015bb74 3359 return ret;
46a3df9f 3360
46a3df9f
S		 3361 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3362 if (ret)
8015bb74 3363 return ret;
46a3df9f
S		 3364
3365 ret = hclge_set_rss_input_tuple(hdev);
3366 if (ret)
8015bb74 3367 return ret;
46a3df9f 3368
68ece54e
YL		 3369 /* Each TC have the same queue size, and tc_size set to hardware is
3370 * the log2 of roundup power of two of rss_size, the acutal queue
3371 * size is limited by indirection table.
3372 */
3373 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3374 dev_err(&hdev->pdev->dev,
3375 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3376 rss_size);
8015bb74 3377 return -EINVAL;
68ece54e
YL		 3378 }
3379
3380 roundup_size = roundup_pow_of_two(rss_size);
3381 roundup_size = ilog2(roundup_size);
3382
46a3df9f 3383 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3384 tc_valid[i] = 0;
46a3df9f 3385
68ece54e
YL		 3386 if (!(hdev->hw_tc_map & BIT(i)))
3387 continue;
3388
3389 tc_valid[i] = 1;
3390 tc_size[i] = roundup_size;
3391 tc_offset[i] = rss_size * i;
46a3df9f 3392 }
68ece54e 3393
8015bb74
YL		 3394 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3395}
46a3df9f 3396
8015bb74
YL		 3397void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3398{
3399 struct hclge_vport *vport = hdev->vport;
3400 int i, j;
46a3df9f 3401
8015bb74
YL		 3402 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3403 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3404 vport[j].rss_indirection_tbl[i] =
3405 i % vport[j].alloc_rss_size;
3406 }
3407}
3408
3409static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3410{
3411 struct hclge_vport *vport = hdev->vport;
3412 int i;
3413
8015bb74
YL		 3414 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3415 vport[i].rss_tuple_sets.ipv4_tcp_en =
3416 HCLGE_RSS_INPUT_TUPLE_OTHER;
3417 vport[i].rss_tuple_sets.ipv4_udp_en =
3418 HCLGE_RSS_INPUT_TUPLE_OTHER;
3419 vport[i].rss_tuple_sets.ipv4_sctp_en =
3420 HCLGE_RSS_INPUT_TUPLE_SCTP;
3421 vport[i].rss_tuple_sets.ipv4_fragment_en =
3422 HCLGE_RSS_INPUT_TUPLE_OTHER;
3423 vport[i].rss_tuple_sets.ipv6_tcp_en =
3424 HCLGE_RSS_INPUT_TUPLE_OTHER;
3425 vport[i].rss_tuple_sets.ipv6_udp_en =
3426 HCLGE_RSS_INPUT_TUPLE_OTHER;
3427 vport[i].rss_tuple_sets.ipv6_sctp_en =
3428 HCLGE_RSS_INPUT_TUPLE_SCTP;
3429 vport[i].rss_tuple_sets.ipv6_fragment_en =
3430 HCLGE_RSS_INPUT_TUPLE_OTHER;
3431
3432 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
823fe868
FL		 3433
3434 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
8015bb74
YL		 3435 }
3436
3437 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3438}
3439
63d7e66f
SM		 3440int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3441 int vector_id, bool en,
3442 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3443{
3444 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3445 struct hnae3_ring_chain_node *node;
3446 struct hclge_desc desc;
63d7e66f
SM		 3447 struct hclge_ctrl_vector_chain_cmd *req
3448 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3449 enum hclge_cmd_status status;
3450 enum hclge_opcode_type op;
3451 u16 tqp_type_and_id;
46a3df9f
S		 3452 int i;
3453
63d7e66f
SM		 3454 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3455 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3456 req->int_vector_id = vector_id;
3457
3458 i = 0;
3459 for (node = ring_chain; node; node = node->next) {
63d7e66f 3460 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
e22b531b
HT		 3461 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3462 HCLGE_INT_TYPE_S,
3463 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3464 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3465 HCLGE_TQP_ID_S, node->tqp_index);
3466 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3467 HCLGE_INT_GL_IDX_S,
3468 hnae3_get_field(node->int_gl_idx,
3469 HNAE3_RING_GL_IDX_M,
3470 HNAE3_RING_GL_IDX_S));
63d7e66f 3471 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3472 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3473 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
63d7e66f 3474 req->vfid = vport->vport_id;
46a3df9f 3475
63d7e66f
SM		 3476 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3477 if (status) {
46a3df9f
S		 3478 dev_err(&hdev->pdev->dev,
3479 "Map TQP fail, status is %d.\n",
63d7e66f
SM		 3480 status);
3481 return -EIO;
46a3df9f
S		 3482 }
3483 i = 0;
3484
3485 hclge_cmd_setup_basic_desc(&desc,
63d7e66f 3486 op,
46a3df9f
S		 3487 false);
3488 req->int_vector_id = vector_id;
3489 }
3490 }
3491
3492 if (i > 0) {
3493 req->int_cause_num = i;
63d7e66f
SM		 3494 req->vfid = vport->vport_id;
3495 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3496 if (status) {
46a3df9f 3497 dev_err(&hdev->pdev->dev,
63d7e66f
SM		 3498 "Map TQP fail, status is %d.\n", status);
3499 return -EIO;
46a3df9f
S		 3500 }
3501 }
3502
3503 return 0;
3504}
3505
63d7e66f
SM		 3506static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3507 int vector,
3508 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3509{
3510 struct hclge_vport *vport = hclge_get_vport(handle);
3511 struct hclge_dev *hdev = vport->back;
3512 int vector_id;
3513
3514 vector_id = hclge_get_vector_index(hdev, vector);
3515 if (vector_id < 0) {
3516 dev_err(&hdev->pdev->dev,
63d7e66f 3517 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3518 return vector_id;
3519 }
3520
63d7e66f 3521 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3522}
3523
63d7e66f
SM		 3524static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3525 int vector,
3526 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3527{
3528 struct hclge_vport *vport = hclge_get_vport(handle);
3529 struct hclge_dev *hdev = vport->back;
63d7e66f 3530 int vector_id, ret;
46a3df9f 3531
f9637cc2
PL		 3532 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3533 return 0;
3534
46a3df9f
S		 3535 vector_id = hclge_get_vector_index(hdev, vector);
3536 if (vector_id < 0) {
3537 dev_err(&handle->pdev->dev,
3538 "Get vector index fail. ret =%d\n", vector_id);
3539 return vector_id;
3540 }
3541
63d7e66f 3542 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
7412200c 3543 if (ret)
63d7e66f
SM		 3544 dev_err(&handle->pdev->dev,
3545 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3546 vector_id,
3547 ret);
46a3df9f 3548
7412200c 3549 return ret;
46a3df9f
S		 3550}
3551
3552int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3553 struct hclge_promisc_param *param)
3554{
d44f9b63 3555 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3556 struct hclge_desc desc;
3557 int ret;
3558
3559 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3560
d44f9b63 3561 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3562 req->vf_id = param->vf_id;
4771e104
PL		 3563
3564 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3565 * pdev revision(0x20), new revision support them. The
3566 * value of this two fields will not return error when driver
3567 * send command to fireware in revision(0x20).
3568 */
3569 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3570 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3571
3572 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3573 if (ret)
46a3df9f
S		 3574 dev_err(&hdev->pdev->dev,
3575 "Set promisc mode fail, status is %d.\n", ret);
e125295a
JS		 3576
3577 return ret;
46a3df9f
S		 3578}
3579
3580void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3581 bool en_mc, bool en_bc, int vport_id)
3582{
3583 if (!param)
3584 return;
3585
3586 memset(param, 0, sizeof(struct hclge_promisc_param));
3587 if (en_uc)
3588 param->enable = HCLGE_PROMISC_EN_UC;
3589 if (en_mc)
3590 param->enable |= HCLGE_PROMISC_EN_MC;
3591 if (en_bc)
3592 param->enable |= HCLGE_PROMISC_EN_BC;
3593 param->vf_id = vport_id;
3594}
3595
e8600a3d
PL		 3596static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3597 bool en_mc_pmc)
46a3df9f
S		 3598{
3599 struct hclge_vport *vport = hclge_get_vport(handle);
3600 struct hclge_dev *hdev = vport->back;
3601 struct hclge_promisc_param param;
3602
e8600a3d
PL		 3603 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3604 vport->vport_id);
46a3df9f
S		 3605 hclge_cmd_set_promisc_mode(hdev, &param);
3606}
3607
3608static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3609{
3610 struct hclge_desc desc;
d44f9b63
YL		 3611 struct hclge_config_mac_mode_cmd *req =
3612 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3613 u32 loop_en = 0;
46a3df9f
S		 3614 int ret;
3615
3616 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
e22b531b
HT		 3617 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3618 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3619 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3620 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3621 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3622 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3623 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3624 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3625 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3626 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3627 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3628 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3629 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3630 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 3631 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3632
3633 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3634 if (ret)
3635 dev_err(&hdev->pdev->dev,
3636 "mac enable fail, ret =%d.\n", ret);
3637}
3638
e67d9ce9 3639static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 3640{
c39c4d98 3641 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 3642 struct hclge_desc desc;
3643 u32 loop_en;
3644 int ret;
3645
e67d9ce9
YL		 3646 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3647 /* 1 Read out the MAC mode config at first */
3648 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3649 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3650 if (ret) {
3651 dev_err(&hdev->pdev->dev,
3652 "mac loopback get fail, ret =%d.\n", ret);
3653 return ret;
3654 }
c39c4d98 3655
e67d9ce9
YL		 3656 /* 2 Then setup the loopback flag */
3657 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
e22b531b 3658 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
e67d9ce9
YL		 3659
3660 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 3661
e67d9ce9
YL		 3662 /* 3 Config mac work mode with loopback flag
3663 * and its original configure parameters
3664 */
3665 hclge_cmd_reuse_desc(&desc, false);
3666 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3667 if (ret)
3668 dev_err(&hdev->pdev->dev,
3669 "mac loopback set fail, ret =%d.\n", ret);
3670 return ret;
3671}
c39c4d98 3672
2fd5416a
YL		 3673static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en)
3674{
3675#define HCLGE_SERDES_RETRY_MS 10
3676#define HCLGE_SERDES_RETRY_NUM 100
3677 struct hclge_serdes_lb_cmd *req;
3678 struct hclge_desc desc;
3679 int ret, i = 0;
3680
3681 req = (struct hclge_serdes_lb_cmd *)&desc.data[0];
3682 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
3683
3684 if (en) {
3685 req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3686 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3687 } else {
3688 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3689 }
3690
3691 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3692 if (ret) {
3693 dev_err(&hdev->pdev->dev,
3694 "serdes loopback set fail, ret = %d\n", ret);
3695 return ret;
3696 }
3697
3698 do {
3699 msleep(HCLGE_SERDES_RETRY_MS);
3700 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3701 true);
3702 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3703 if (ret) {
3704 dev_err(&hdev->pdev->dev,
3705 "serdes loopback get, ret = %d\n", ret);
3706 return ret;
3707 }
3708 } while (++i < HCLGE_SERDES_RETRY_NUM &&
3709 !(req->result & HCLGE_CMD_SERDES_DONE_B));
3710
3711 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3712 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3713 return -EBUSY;
3714 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3715 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3716 return -EIO;
3717 }
3718
3719 return 0;
3720}
3721
e67d9ce9
YL		 3722static int hclge_set_loopback(struct hnae3_handle *handle,
3723 enum hnae3_loop loop_mode, bool en)
3724{
3725 struct hclge_vport *vport = hclge_get_vport(handle);
3726 struct hclge_dev *hdev = vport->back;
3727 int ret;
3728
3729 switch (loop_mode) {
3730 case HNAE3_MAC_INTER_LOOP_MAC:
3731 ret = hclge_set_mac_loopback(hdev, en);
c39c4d98 3732 break;
2fd5416a
YL		 3733 case HNAE3_MAC_INTER_LOOP_SERDES:
3734 ret = hclge_set_serdes_loopback(hdev, en);
3735 break;
c39c4d98
YL		 3736 default:
3737 ret = -ENOTSUPP;
3738 dev_err(&hdev->pdev->dev,
3739 "loop_mode %d is not supported\n", loop_mode);
3740 break;
3741 }
3742
3743 return ret;
3744}
3745
46a3df9f
S		 3746static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3747 int stream_id, bool enable)
3748{
3749 struct hclge_desc desc;
d44f9b63
YL		 3750 struct hclge_cfg_com_tqp_queue_cmd *req =
3751 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3752 int ret;
3753
3754 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3755 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3756 req->stream_id = cpu_to_le16(stream_id);
3757 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3758
3759 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3760 if (ret)
3761 dev_err(&hdev->pdev->dev,
3762 "Tqp enable fail, status =%d.\n", ret);
3763 return ret;
3764}
3765
3766static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3767{
3768 struct hclge_vport *vport = hclge_get_vport(handle);
3769 struct hnae3_queue *queue;
3770 struct hclge_tqp *tqp;
3771 int i;
3772
3773 for (i = 0; i < vport->alloc_tqps; i++) {
3774 queue = handle->kinfo.tqp[i];
3775 tqp = container_of(queue, struct hclge_tqp, q);
3776 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3777 }
3778}
3779
3780static int hclge_ae_start(struct hnae3_handle *handle)
3781{
3782 struct hclge_vport *vport = hclge_get_vport(handle);
3783 struct hclge_dev *hdev = vport->back;
e5e89cda 3784 int i, ret;
46a3df9f 3785
e5e89cda
PL		 3786 for (i = 0; i < vport->alloc_tqps; i++)
3787 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3788
46a3df9f
S		 3789 /* mac enable */
3790 hclge_cfg_mac_mode(hdev, true);
3791 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3792 mod_timer(&hdev->service_timer, jiffies + HZ);
3ae84019 3793 hdev->hw.mac.link = 0;
46a3df9f 3794
f9637cc2
PL		 3795 /* reset tqp stats */
3796 hclge_reset_tqp_stats(handle);
3797
46a3df9f
S		 3798 ret = hclge_mac_start_phy(hdev);
3799 if (ret)
3800 return ret;
3801
46a3df9f
S		 3802 return 0;
3803}
3804
3805static void hclge_ae_stop(struct hnae3_handle *handle)
3806{
3807 struct hclge_vport *vport = hclge_get_vport(handle);
3808 struct hclge_dev *hdev = vport->back;
e5e89cda 3809 int i;
46a3df9f 3810
f9637cc2
PL		 3811 del_timer_sync(&hdev->service_timer);
3812 cancel_work_sync(&hdev->service_task);
42b11ab7 3813 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
f9637cc2 3814
4486f5c9
YL		 3815 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3816 hclge_mac_stop_phy(hdev);
f9637cc2 3817 return;
4486f5c9 3818 }
f9637cc2 3819
e5e89cda
PL		 3820 for (i = 0; i < vport->alloc_tqps; i++)
3821 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3822
46a3df9f
S		 3823 /* Mac disable */
3824 hclge_cfg_mac_mode(hdev, false);
3825
3826 hclge_mac_stop_phy(hdev);
3827
3828 /* reset tqp stats */
3829 hclge_reset_tqp_stats(handle);
b91fb71c
FL		 3830 del_timer_sync(&hdev->service_timer);
3831 cancel_work_sync(&hdev->service_task);
3832 hclge_update_link_status(hdev);
46a3df9f
S		 3833}
3834
3835static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3836 u16 cmdq_resp, u8 resp_code,
3837 enum hclge_mac_vlan_tbl_opcode op)
3838{
3839 struct hclge_dev *hdev = vport->back;
3840 int return_status = -EIO;
3841
3842 if (cmdq_resp) {
3843 dev_err(&hdev->pdev->dev,
3844 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3845 cmdq_resp);
3846 return -EIO;
3847 }
3848
3849 if (op == HCLGE_MAC_VLAN_ADD) {
3850 if ((!resp_code) || (resp_code == 1)) {
3851 return_status = 0;
3852 } else if (resp_code == 2) {
2f894c5b 3853 return_status = -ENOSPC;
46a3df9f
S		 3854 dev_err(&hdev->pdev->dev,
3855 "add mac addr failed for uc_overflow.\n");
3856 } else if (resp_code == 3) {
2f894c5b 3857 return_status = -ENOSPC;
46a3df9f
S		 3858 dev_err(&hdev->pdev->dev,
3859 "add mac addr failed for mc_overflow.\n");
3860 } else {
3861 dev_err(&hdev->pdev->dev,
3862 "add mac addr failed for undefined, code=%d.\n",
3863 resp_code);
3864 }
3865 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3866 if (!resp_code) {
3867 return_status = 0;
3868 } else if (resp_code == 1) {
2f894c5b 3869 return_status = -ENOENT;
46a3df9f
S		 3870 dev_dbg(&hdev->pdev->dev,
3871 "remove mac addr failed for miss.\n");
3872 } else {
3873 dev_err(&hdev->pdev->dev,
3874 "remove mac addr failed for undefined, code=%d.\n",
3875 resp_code);
3876 }
3877 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3878 if (!resp_code) {
3879 return_status = 0;
3880 } else if (resp_code == 1) {
2f894c5b 3881 return_status = -ENOENT;
46a3df9f
S		 3882 dev_dbg(&hdev->pdev->dev,
3883 "lookup mac addr failed for miss.\n");
3884 } else {
3885 dev_err(&hdev->pdev->dev,
3886 "lookup mac addr failed for undefined, code=%d.\n",
3887 resp_code);
3888 }
3889 } else {
2f894c5b 3890 return_status = -EINVAL;
46a3df9f
S		 3891 dev_err(&hdev->pdev->dev,
3892 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3893 op);
3894 }
3895
3896 return return_status;
3897}
3898
3899static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3900{
3901 int word_num;
3902 int bit_num;
3903
3904 if (vfid > 255 || vfid < 0)
3905 return -EIO;
3906
3907 if (vfid >= 0 && vfid <= 191) {
3908 word_num = vfid / 32;
3909 bit_num = vfid % 32;
3910 if (clr)
a90bb9a5 3911 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3912 else
a90bb9a5 3913 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3914 } else {
3915 word_num = (vfid - 192) / 32;
3916 bit_num = vfid % 32;
3917 if (clr)
a90bb9a5 3918 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3919 else
a90bb9a5 3920 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3921 }
3922
3923 return 0;
3924}
3925
3926static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3927{
3928#define HCLGE_DESC_NUMBER 3
3929#define HCLGE_FUNC_NUMBER_PER_DESC 6
3930 int i, j;
3931
3932 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3933 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3934 if (desc[i].data[j])
3935 return false;
3936
3937 return true;
3938}
3939
d44f9b63 3940static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3941 const u8 *addr)
3942{
3943 const unsigned char *mac_addr = addr;
3944 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3945 (mac_addr[0]) | (mac_addr[1] << 8);
3946 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3947
3948 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3949 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3950}
3951
1db9b1bf
YL		 3952static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3953 const u8 *addr)
46a3df9f
S		 3954{
3955 u16 high_val = addr[1] | (addr[0] << 8);
3956 struct hclge_dev *hdev = vport->back;
3957 u32 rsh = 4 - hdev->mta_mac_sel_type;
3958 u16 ret_val = (high_val >> rsh) & 0xfff;
3959
3960 return ret_val;
3961}
3962
3963static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3964 enum hclge_mta_dmac_sel_type mta_mac_sel,
3965 bool enable)
3966{
d44f9b63 3967 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3968 struct hclge_desc desc;
3969 int ret;
3970
d44f9b63 3971 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3972 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3973
e22b531b
HT		 3974 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3975 enable);
3976 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3977 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
46a3df9f
S		 3978
3979 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 3980 if (ret)
46a3df9f
S		 3981 dev_err(&hdev->pdev->dev,
3982 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3983 ret);
46a3df9f 3984
e125295a 3985 return ret;
46a3df9f
S		 3986}
3987
3988int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3989 u8 func_id,
3990 bool enable)
3991{
d44f9b63 3992 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3993 struct hclge_desc desc;
3994 int ret;
3995
d44f9b63 3996 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3997 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3998
e22b531b
HT		 3999 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
4000 enable);
46a3df9f
S		 4001 req->function_id = func_id;
4002
4003 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 4004 if (ret)
46a3df9f
S		 4005 dev_err(&hdev->pdev->dev,
4006 "Config func_id enable failed for cmd_send, ret =%d.\n",
4007 ret);
46a3df9f 4008
e125295a 4009 return ret;
46a3df9f
S		 4010}
4011
4012static int hclge_set_mta_table_item(struct hclge_vport *vport,
4013 u16 idx,
4014 bool enable)
4015{
4016 struct hclge_dev *hdev = vport->back;
d44f9b63 4017 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 4018 struct hclge_desc desc;
a90bb9a5 4019 u16 item_idx = 0;
46a3df9f
S		 4020 int ret;
4021
d44f9b63 4022 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f 4023 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
e22b531b 4024 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
46a3df9f 4025
e22b531b
HT		 4026 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
4027 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 4028 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 4029
4030 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4031 if (ret) {
4032 dev_err(&hdev->pdev->dev,
4033 "Config mta table item failed for cmd_send, ret =%d.\n",
4034 ret);
4035 return ret;
4036 }
4037
a832d8b5
XW		 4038 if (enable)
4039 set_bit(idx, vport->mta_shadow);
4040 else
4041 clear_bit(idx, vport->mta_shadow);
4042
46a3df9f
S		 4043 return 0;
4044}
4045
a832d8b5
XW		 4046static int hclge_update_mta_status(struct hnae3_handle *handle)
4047{
4048 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
4049 struct hclge_vport *vport = hclge_get_vport(handle);
4050 struct net_device *netdev = handle->kinfo.netdev;
4051 struct netdev_hw_addr *ha;
4052 u16 tbl_idx;
4053
4054 memset(mta_status, 0, sizeof(mta_status));
4055
4056 /* update mta_status from mc addr list */
4057 netdev_for_each_mc_addr(ha, netdev) {
4058 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
4059 set_bit(tbl_idx, mta_status);
4060 }
4061
4062 return hclge_update_mta_status_common(vport, mta_status,
4063 0, HCLGE_MTA_TBL_SIZE, true);
4064}
4065
4066int hclge_update_mta_status_common(struct hclge_vport *vport,
4067 unsigned long *status,
4068 u16 idx,
4069 u16 count,
4070 bool update_filter)
4071{
4072 struct hclge_dev *hdev = vport->back;
4073 u16 update_max = idx + count;
4074 u16 check_max;
4075 int ret = 0;
4076 bool used;
4077 u16 i;
4078
4079 /* setup mta check range */
4080 if (update_filter) {
4081 i = 0;
4082 check_max = HCLGE_MTA_TBL_SIZE;
4083 } else {
4084 i = idx;
4085 check_max = update_max;
4086 }
4087
4088 used = false;
4089 /* check and update all mta item */
4090 for (; i < check_max; i++) {
4091 /* ignore unused item */
4092 if (!test_bit(i, vport->mta_shadow))
4093 continue;
4094
4095 /* if i in update range then update it */
4096 if (i >= idx && i < update_max)
4097 if (!test_bit(i - idx, status))
4098 hclge_set_mta_table_item(vport, i, false);
4099
4100 if (!used && test_bit(i, vport->mta_shadow))
4101 used = true;
4102 }
4103
4104 /* no longer use mta, disable it */
4105 if (vport->accept_mta_mc && update_filter && !used) {
4106 ret = hclge_cfg_func_mta_filter(hdev,
4107 vport->vport_id,
4108 false);
4109 if (ret)
4110 dev_err(&hdev->pdev->dev,
4111 "disable func mta filter fail ret=%d\n",
4112 ret);
4113 else
4114 vport->accept_mta_mc = false;
4115 }
4116
4117 return ret;
4118}
4119
46a3df9f 4120static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4121 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 4122{
4123 struct hclge_dev *hdev = vport->back;
4124 struct hclge_desc desc;
4125 u8 resp_code;
a90bb9a5 4126 u16 retval;
46a3df9f
S		 4127 int ret;
4128
4129 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4130
d44f9b63 4131 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4132
4133 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4134 if (ret) {
4135 dev_err(&hdev->pdev->dev,
4136 "del mac addr failed for cmd_send, ret =%d.\n",
4137 ret);
4138 return ret;
4139 }
a90bb9a5
YL		 4140 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4141 retval = le16_to_cpu(desc.retval);
46a3df9f 4142
a90bb9a5 4143 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4144 HCLGE_MAC_VLAN_REMOVE);
4145}
4146
4147static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4148 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4149 struct hclge_desc *desc,
4150 bool is_mc)
4151{
4152 struct hclge_dev *hdev = vport->back;
4153 u8 resp_code;
a90bb9a5 4154 u16 retval;
46a3df9f
S		 4155 int ret;
4156
4157 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4158 if (is_mc) {
4159 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4160 memcpy(desc[0].data,
4161 req,
d44f9b63 4162 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4163 hclge_cmd_setup_basic_desc(&desc[1],
4164 HCLGE_OPC_MAC_VLAN_ADD,
4165 true);
4166 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4167 hclge_cmd_setup_basic_desc(&desc[2],
4168 HCLGE_OPC_MAC_VLAN_ADD,
4169 true);
4170 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4171 } else {
4172 memcpy(desc[0].data,
4173 req,
d44f9b63 4174 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4175 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4176 }
4177 if (ret) {
4178 dev_err(&hdev->pdev->dev,
4179 "lookup mac addr failed for cmd_send, ret =%d.\n",
4180 ret);
4181 return ret;
4182 }
a90bb9a5
YL		 4183 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4184 retval = le16_to_cpu(desc[0].retval);
46a3df9f 4185
a90bb9a5 4186 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4187 HCLGE_MAC_VLAN_LKUP);
4188}
4189
4190static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4191 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4192 struct hclge_desc *mc_desc)
4193{
4194 struct hclge_dev *hdev = vport->back;
4195 int cfg_status;
4196 u8 resp_code;
a90bb9a5 4197 u16 retval;
46a3df9f
S		 4198 int ret;
4199
4200 if (!mc_desc) {
4201 struct hclge_desc desc;
4202
4203 hclge_cmd_setup_basic_desc(&desc,
4204 HCLGE_OPC_MAC_VLAN_ADD,
4205 false);
d44f9b63
YL		 4206 memcpy(desc.data, req,
4207 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4208 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 4209 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4210 retval = le16_to_cpu(desc.retval);
4211
4212 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4213 resp_code,
4214 HCLGE_MAC_VLAN_ADD);
4215 } else {
c3b6f755 4216 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 4217 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4218 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 4219 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4220 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 4221 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4222 memcpy(mc_desc[0].data, req,
d44f9b63 4223 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4224 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 4225 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4226 retval = le16_to_cpu(mc_desc[0].retval);
4227
4228 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4229 resp_code,
4230 HCLGE_MAC_VLAN_ADD);
4231 }
4232
4233 if (ret) {
4234 dev_err(&hdev->pdev->dev,
4235 "add mac addr failed for cmd_send, ret =%d.\n",
4236 ret);
4237 return ret;
4238 }
4239
4240 return cfg_status;
4241}
4242
4243static int hclge_add_uc_addr(struct hnae3_handle *handle,
4244 const unsigned char *addr)
4245{
4246 struct hclge_vport *vport = hclge_get_vport(handle);
4247
4248 return hclge_add_uc_addr_common(vport, addr);
4249}
4250
4251int hclge_add_uc_addr_common(struct hclge_vport *vport,
4252 const unsigned char *addr)
4253{
4254 struct hclge_dev *hdev = vport->back;
d44f9b63 4255 struct hclge_mac_vlan_tbl_entry_cmd req;
bf88f41f 4256 struct hclge_desc desc;
a90bb9a5 4257 u16 egress_port = 0;
04f0c72a 4258 int ret;
46a3df9f
S		 4259
4260 /* mac addr check */
4261 if (is_zero_ether_addr(addr) ||
4262 is_broadcast_ether_addr(addr) ||
4263 is_multicast_ether_addr(addr)) {
4264 dev_err(&hdev->pdev->dev,
4265 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4266 addr,
4267 is_zero_ether_addr(addr),
4268 is_broadcast_ether_addr(addr),
4269 is_multicast_ether_addr(addr));
4270 return -EINVAL;
4271 }
4272
4273 memset(&req, 0, sizeof(req));
e22b531b 4274 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 4275
e22b531b
HT		 4276 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4277 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 4278
4279 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4280
4281 hclge_prepare_mac_addr(&req, addr);
4282
bf88f41f
JS		 4283 /* Lookup the mac address in the mac_vlan table, and add
4284 * it if the entry is inexistent. Repeated unicast entry
4285 * is not allowed in the mac vlan table.
4286 */
4287 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4288 if (ret == -ENOENT)
4289 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4290
4291 /* check if we just hit the duplicate */
4292 if (!ret)
4293 ret = -EINVAL;
4294
4295 dev_err(&hdev->pdev->dev,
4296 "PF failed to add unicast entry(%pM) in the MAC table\n",
4297 addr);
46a3df9f 4298
04f0c72a 4299 return ret;
46a3df9f
S		 4300}
4301
4302static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4303 const unsigned char *addr)
4304{
4305 struct hclge_vport *vport = hclge_get_vport(handle);
4306
4307 return hclge_rm_uc_addr_common(vport, addr);
4308}
4309
4310int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4311 const unsigned char *addr)
4312{
4313 struct hclge_dev *hdev = vport->back;
d44f9b63 4314 struct hclge_mac_vlan_tbl_entry_cmd req;
04f0c72a 4315 int ret;
46a3df9f
S		 4316
4317 /* mac addr check */
4318 if (is_zero_ether_addr(addr) ||
4319 is_broadcast_ether_addr(addr) ||
4320 is_multicast_ether_addr(addr)) {
4321 dev_dbg(&hdev->pdev->dev,
4322 "Remove mac err! invalid mac:%pM.\n",
4323 addr);
4324 return -EINVAL;
4325 }
4326
4327 memset(&req, 0, sizeof(req));
e22b531b
HT		 4328 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4329 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 4330 hclge_prepare_mac_addr(&req, addr);
04f0c72a 4331 ret = hclge_remove_mac_vlan_tbl(vport, &req);
46a3df9f 4332
04f0c72a 4333 return ret;
46a3df9f
S		 4334}
4335
4336static int hclge_add_mc_addr(struct hnae3_handle *handle,
4337 const unsigned char *addr)
4338{
4339 struct hclge_vport *vport = hclge_get_vport(handle);
4340
de4116e0 4341 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 4342}
4343
4344int hclge_add_mc_addr_common(struct hclge_vport *vport,
4345 const unsigned char *addr)
4346{
4347 struct hclge_dev *hdev = vport->back;
d44f9b63 4348 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4349 struct hclge_desc desc[3];
4350 u16 tbl_idx;
4351 int status;
4352
4353 /* mac addr check */
4354 if (!is_multicast_ether_addr(addr)) {
4355 dev_err(&hdev->pdev->dev,
4356 "Add mc mac err! invalid mac:%pM.\n",
4357 addr);
4358 return -EINVAL;
4359 }
4360 memset(&req, 0, sizeof(req));
e22b531b
HT		 4361 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4362 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4363 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4364 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f
S		 4365 hclge_prepare_mac_addr(&req, addr);
4366 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4367 if (!status) {
4368 /* This mac addr exist, update VFID for it */
4369 hclge_update_desc_vfid(desc, vport->vport_id, false);
4370 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4371 } else {
4372 /* This mac addr do not exist, add new entry for it */
4373 memset(desc[0].data, 0, sizeof(desc[0].data));
4374 memset(desc[1].data, 0, sizeof(desc[0].data));
4375 memset(desc[2].data, 0, sizeof(desc[0].data));
4376 hclge_update_desc_vfid(desc, vport->vport_id, false);
4377 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4378 }
4379
a832d8b5
XW		 4380 /* If mc mac vlan table is full, use MTA table */
4381 if (status == -ENOSPC) {
4382 if (!vport->accept_mta_mc) {
4383 status = hclge_cfg_func_mta_filter(hdev,
4384 vport->vport_id,
4385 true);
4386 if (status) {
4387 dev_err(&hdev->pdev->dev,
4388 "set mta filter mode fail ret=%d\n",
4389 status);
4390 return status;
4391 }
4392 vport->accept_mta_mc = true;
4393 }
4394
4395 /* Set MTA table for this MAC address */
4396 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4397 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4398 }
46a3df9f
S		 4399
4400 return status;
4401}
4402
4403static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4404 const unsigned char *addr)
4405{
4406 struct hclge_vport *vport = hclge_get_vport(handle);
4407
4408 return hclge_rm_mc_addr_common(vport, addr);
4409}
4410
4411int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4412 const unsigned char *addr)
4413{
4414 struct hclge_dev *hdev = vport->back;
d44f9b63 4415 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4416 enum hclge_cmd_status status;
4417 struct hclge_desc desc[3];
46a3df9f
S		 4418
4419 /* mac addr check */
4420 if (!is_multicast_ether_addr(addr)) {
4421 dev_dbg(&hdev->pdev->dev,
4422 "Remove mc mac err! invalid mac:%pM.\n",
4423 addr);
4424 return -EINVAL;
4425 }
4426
4427 memset(&req, 0, sizeof(req));
e22b531b
HT		 4428 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4429 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4430 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4431 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f
S		 4432 hclge_prepare_mac_addr(&req, addr);
4433 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4434 if (!status) {
4435 /* This mac addr exist, remove this handle's VFID for it */
4436 hclge_update_desc_vfid(desc, vport->vport_id, true);
4437
4438 if (hclge_is_all_function_id_zero(desc))
4439 /* All the vfid is zero, so need to delete this entry */
4440 status = hclge_remove_mac_vlan_tbl(vport, &req);
4441 else
4442 /* Not all the vfid is zero, update the vfid */
4443 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4444
4445 } else {
a832d8b5
XW		 4446 /* Maybe this mac address is in mta table, but it cannot be
4447 * deleted here because an entry of mta represents an address
4448 * range rather than a specific address. the delete action to
4449 * all entries will take effect in update_mta_status called by
4450 * hns3_nic_set_rx_mode.
4451 */
4452 status = 0;
46a3df9f
S		 4453 }
4454
46a3df9f
S		 4455 return status;
4456}
4457
635bfb58
FL		 4458static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4459 u16 cmdq_resp, u8 resp_code)
4460{
4461#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4462#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4463#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4464#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4465
4466 int return_status;
4467
4468 if (cmdq_resp) {
4469 dev_err(&hdev->pdev->dev,
4470 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4471 cmdq_resp);
4472 return -EIO;
4473 }
4474
4475 switch (resp_code) {
4476 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4477 case HCLGE_ETHERTYPE_ALREADY_ADD:
4478 return_status = 0;
4479 break;
4480 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4481 dev_err(&hdev->pdev->dev,
4482 "add mac ethertype failed for manager table overflow.\n");
4483 return_status = -EIO;
4484 break;
4485 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4486 dev_err(&hdev->pdev->dev,
4487 "add mac ethertype failed for key conflict.\n");
4488 return_status = -EIO;
4489 break;
4490 default:
4491 dev_err(&hdev->pdev->dev,
4492 "add mac ethertype failed for undefined, code=%d.\n",
4493 resp_code);
4494 return_status = -EIO;
4495 }
4496
4497 return return_status;
4498}
4499
4500static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4501 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4502{
4503 struct hclge_desc desc;
4504 u8 resp_code;
4505 u16 retval;
4506 int ret;
4507
4508 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4509 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4510
4511 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4512 if (ret) {
4513 dev_err(&hdev->pdev->dev,
4514 "add mac ethertype failed for cmd_send, ret =%d.\n",
4515 ret);
4516 return ret;
4517 }
4518
4519 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4520 retval = le16_to_cpu(desc.retval);
4521
4522 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4523}
4524
4525static int init_mgr_tbl(struct hclge_dev *hdev)
4526{
4527 int ret;
4528 int i;
4529
4530 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4531 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4532 if (ret) {
4533 dev_err(&hdev->pdev->dev,
4534 "add mac ethertype failed, ret =%d.\n",
4535 ret);
4536 return ret;
4537 }
4538 }
4539
4540 return 0;
4541}
4542
46a3df9f
S		 4543static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4544{
4545 struct hclge_vport *vport = hclge_get_vport(handle);
4546 struct hclge_dev *hdev = vport->back;
4547
4548 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4549}
4550
3cbf5e2d
FL		 4551static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4552 bool is_first)
46a3df9f
S		 4553{
4554 const unsigned char *new_addr = (const unsigned char *)p;
4555 struct hclge_vport *vport = hclge_get_vport(handle);
4556 struct hclge_dev *hdev = vport->back;
20a5c4c0 4557 int ret;
46a3df9f
S		 4558
4559 /* mac addr check */
4560 if (is_zero_ether_addr(new_addr) ||
4561 is_broadcast_ether_addr(new_addr) ||
4562 is_multicast_ether_addr(new_addr)) {
4563 dev_err(&hdev->pdev->dev,
4564 "Change uc mac err! invalid mac:%p.\n",
4565 new_addr);
4566 return -EINVAL;
4567 }
4568
3cbf5e2d 4569 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 4570 dev_warn(&hdev->pdev->dev,
3cbf5e2d 4571 "remove old uc mac address fail.\n");
46a3df9f 4572
20a5c4c0
FL		 4573 ret = hclge_add_uc_addr(handle, new_addr);
4574 if (ret) {
4575 dev_err(&hdev->pdev->dev,
4576 "add uc mac address fail, ret =%d.\n",
4577 ret);
4578
3cbf5e2d
FL		 4579 if (!is_first &&
4580 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 4581 dev_err(&hdev->pdev->dev,
3cbf5e2d 4582 "restore uc mac address fail.\n");
20a5c4c0
FL		 4583
4584 return -EIO;
46a3df9f
S		 4585 }
4586
532fdd5e 4587 ret = hclge_pause_addr_cfg(hdev, new_addr);
20a5c4c0
FL		 4588 if (ret) {
4589 dev_err(&hdev->pdev->dev,
4590 "configure mac pause address fail, ret =%d.\n",
4591 ret);
4592 return -EIO;
4593 }
4594
4595 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4596
4597 return 0;
46a3df9f
S		 4598}
4599
4600static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4601 bool filter_en)
4602{
d44f9b63 4603 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4604 struct hclge_desc desc;
4605 int ret;
4606
4607 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4608
d44f9b63 4609 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4610 req->vlan_type = vlan_type;
4611 req->vlan_fe = filter_en;
4612
4613 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 4614 if (ret)
46a3df9f
S		 4615 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4616 ret);
46a3df9f 4617
e125295a 4618 return ret;
46a3df9f
S		 4619}
4620
d818396d
JS		 4621#define HCLGE_FILTER_TYPE_VF 0
4622#define HCLGE_FILTER_TYPE_PORT 1
4623
4624static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4625{
4626 struct hclge_vport *vport = hclge_get_vport(handle);
4627 struct hclge_dev *hdev = vport->back;
4628
4629 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4630}
4631
4e66632d
YL		 4632static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4633 bool is_kill, u16 vlan, u8 qos,
4634 __be16 proto)
46a3df9f
S		 4635{
4636#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4637 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4638 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4639 struct hclge_desc desc[2];
4640 u8 vf_byte_val;
4641 u8 vf_byte_off;
4642 int ret;
4643
4644 hclge_cmd_setup_basic_desc(&desc[0],
4645 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4646 hclge_cmd_setup_basic_desc(&desc[1],
4647 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4648
4649 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4650
4651 vf_byte_off = vfid / 8;
4652 vf_byte_val = 1 << (vfid % 8);
4653
d44f9b63
YL		 4654 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4655 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4656
a90bb9a5 4657 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4658 req0->vlan_cfg = is_kill;
4659
4660 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4661 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4662 else
4663 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4664
4665 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4666 if (ret) {
4667 dev_err(&hdev->pdev->dev,
4668 "Send vf vlan command fail, ret =%d.\n",
4669 ret);
4670 return ret;
4671 }
4672
4673 if (!is_kill) {
715d610d 4674#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 4675 if (!req0->resp_code || req0->resp_code == 1)
4676 return 0;
4677
715d610d
YL		 4678 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4679 dev_warn(&hdev->pdev->dev,
4680 "vf vlan table is full, vf vlan filter is disabled\n");
4681 return 0;
4682 }
4683
46a3df9f
S		 4684 dev_err(&hdev->pdev->dev,
4685 "Add vf vlan filter fail, ret =%d.\n",
4686 req0->resp_code);
4687 } else {
4688 if (!req0->resp_code)
4689 return 0;
4690
4691 dev_err(&hdev->pdev->dev,
4692 "Kill vf vlan filter fail, ret =%d.\n",
4693 req0->resp_code);
4694 }
4695
4696 return -EIO;
4697}
4698
4e66632d
YL		 4699static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4700 u16 vlan_id, bool is_kill)
46a3df9f 4701{
d44f9b63 4702 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4703 struct hclge_desc desc;
4704 u8 vlan_offset_byte_val;
4705 u8 vlan_offset_byte;
4706 u8 vlan_offset_160;
4707 int ret;
4708
4709 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4710
4711 vlan_offset_160 = vlan_id / 160;
4712 vlan_offset_byte = (vlan_id % 160) / 8;
4713 vlan_offset_byte_val = 1 << (vlan_id % 8);
4714
d44f9b63 4715 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4716 req->vlan_offset = vlan_offset_160;
4717 req->vlan_cfg = is_kill;
4718 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4719
4720 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4e66632d
YL		 4721 if (ret)
4722 dev_err(&hdev->pdev->dev,
4723 "port vlan command, send fail, ret =%d.\n", ret);
4724 return ret;
4725}
4726
4727static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4728 u16 vport_id, u16 vlan_id, u8 qos,
4729 bool is_kill)
4730{
4731 u16 vport_idx, vport_num = 0;
4732 int ret;
4733
4734 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4735 0, proto);
46a3df9f
S		 4736 if (ret) {
4737 dev_err(&hdev->pdev->dev,
4e66632d
YL		 4738 "Set %d vport vlan filter config fail, ret =%d.\n",
4739 vport_id, ret);
46a3df9f
S		 4740 return ret;
4741 }
4742
4e66632d
YL		 4743 /* vlan 0 may be added twice when 8021q module is enabled */
4744 if (!is_kill && !vlan_id &&
4745 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4746 return 0;
4747
4748 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 4749 dev_err(&hdev->pdev->dev,
4e66632d
YL		 4750 "Add port vlan failed, vport %d is already in vlan %d\n",
4751 vport_id, vlan_id);
4752 return -EINVAL;
46a3df9f
S		 4753 }
4754
4e66632d
YL		 4755 if (is_kill &&
4756 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4757 dev_err(&hdev->pdev->dev,
4758 "Delete port vlan failed, vport %d is not in vlan %d\n",
4759 vport_id, vlan_id);
4760 return -EINVAL;
4761 }
4762
4763 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID)
4764 vport_num++;
4765
4766 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4767 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4768 is_kill);
4769
4770 return ret;
4771}
4772
4773int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4774 u16 vlan_id, bool is_kill)
4775{
4776 struct hclge_vport *vport = hclge_get_vport(handle);
4777 struct hclge_dev *hdev = vport->back;
4778
4779 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4780 0, is_kill);
46a3df9f
S		 4781}
4782
4783static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4784 u16 vlan, u8 qos, __be16 proto)
4785{
4786 struct hclge_vport *vport = hclge_get_vport(handle);
4787 struct hclge_dev *hdev = vport->back;
4788
4789 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4790 return -EINVAL;
4791 if (proto != htons(ETH_P_8021Q))
4792 return -EPROTONOSUPPORT;
4793
4e66632d 4794 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 4795}
4796
e62f2a6b
PL		 4797static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4798{
4799 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4800 struct hclge_vport_vtag_tx_cfg_cmd *req;
4801 struct hclge_dev *hdev = vport->back;
4802 struct hclge_desc desc;
4803 int status;
4804
4805 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4806
4807 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4808 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4809 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
e22b531b 4810 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
b75b1a56 4811 vcfg->accept_tag1 ? 1 : 0);
e22b531b 4812 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
b75b1a56 4813 vcfg->accept_untag1 ? 1 : 0);
e22b531b 4814 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
b75b1a56 4815 vcfg->accept_tag2 ? 1 : 0);
e22b531b 4816 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
b75b1a56 4817 vcfg->accept_untag2 ? 1 : 0);
e22b531b 4818 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
e62f2a6b 4819 vcfg->insert_tag1_en ? 1 : 0);
e22b531b 4820 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
e62f2a6b 4821 vcfg->insert_tag2_en ? 1 : 0);
e22b531b 4822 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
e62f2a6b
PL		 4823
4824 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4825 req->vf_bitmap[req->vf_offset] =
4826 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4827
4828 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4829 if (status)
4830 dev_err(&hdev->pdev->dev,
4831 "Send port txvlan cfg command fail, ret =%d\n",
4832 status);
4833
4834 return status;
4835}
4836
4837static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4838{
4839 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4840 struct hclge_vport_vtag_rx_cfg_cmd *req;
4841 struct hclge_dev *hdev = vport->back;
4842 struct hclge_desc desc;
4843 int status;
4844
4845 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4846
4847 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
e22b531b
HT		 4848 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4849 vcfg->strip_tag1_en ? 1 : 0);
4850 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4851 vcfg->strip_tag2_en ? 1 : 0);
4852 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4853 vcfg->vlan1_vlan_prionly ? 1 : 0);
4854 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4855 vcfg->vlan2_vlan_prionly ? 1 : 0);
e62f2a6b
PL		 4856
4857 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4858 req->vf_bitmap[req->vf_offset] =
4859 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4860
4861 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4862 if (status)
4863 dev_err(&hdev->pdev->dev,
4864 "Send port rxvlan cfg command fail, ret =%d\n",
4865 status);
4866
4867 return status;
4868}
4869
4870static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4871{
4872 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4873 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4874 struct hclge_desc desc;
4875 int status;
4876
4877 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4878 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4879 rx_req->ot_fst_vlan_type =
4880 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4881 rx_req->ot_sec_vlan_type =
4882 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4883 rx_req->in_fst_vlan_type =
4884 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4885 rx_req->in_sec_vlan_type =
4886 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4887
4888 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4889 if (status) {
4890 dev_err(&hdev->pdev->dev,
4891 "Send rxvlan protocol type command fail, ret =%d\n",
4892 status);
4893 return status;
4894 }
4895
4896 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4897
4898 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4899 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4900 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4901
4902 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4903 if (status)
4904 dev_err(&hdev->pdev->dev,
4905 "Send txvlan protocol type command fail, ret =%d\n",
4906 status);
4907
4908 return status;
4909}
4910
46a3df9f
S		 4911static int hclge_init_vlan_config(struct hclge_dev *hdev)
4912{
e62f2a6b
PL		 4913#define HCLGE_DEF_VLAN_TYPE 0x8100
4914
5e43aef8 4915 struct hnae3_handle *handle;
e62f2a6b 4916 struct hclge_vport *vport;
46a3df9f 4917 int ret;
e62f2a6b
PL		 4918 int i;
4919
4920 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4921 if (ret)
4922 return ret;
46a3df9f 4923
e62f2a6b 4924 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4925 if (ret)
4926 return ret;
4927
e62f2a6b
PL		 4928 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4929 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4930 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4931 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4932 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4933 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4934
4935 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4936 if (ret)
4937 return ret;
46a3df9f 4938
e62f2a6b
PL		 4939 for (i = 0; i < hdev->num_alloc_vport; i++) {
4940 vport = &hdev->vport[i];
b75b1a56
PL		 4941 vport->txvlan_cfg.accept_tag1 = true;
4942 vport->txvlan_cfg.accept_untag1 = true;
4943
4944 /* accept_tag2 and accept_untag2 are not supported on
4945 * pdev revision(0x20), new revision support them. The
4946 * value of this two fields will not return error when driver
4947 * send command to fireware in revision(0x20).
4948 * This two fields can not configured by user.
4949 */
4950 vport->txvlan_cfg.accept_tag2 = true;
4951 vport->txvlan_cfg.accept_untag2 = true;
4952
e62f2a6b
PL		 4953 vport->txvlan_cfg.insert_tag1_en = false;
4954 vport->txvlan_cfg.insert_tag2_en = false;
4955 vport->txvlan_cfg.default_tag1 = 0;
4956 vport->txvlan_cfg.default_tag2 = 0;
4957
4958 ret = hclge_set_vlan_tx_offload_cfg(vport);
4959 if (ret)
4960 return ret;
4961
4962 vport->rxvlan_cfg.strip_tag1_en = false;
4963 vport->rxvlan_cfg.strip_tag2_en = true;
4964 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4965 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4966
4967 ret = hclge_set_vlan_rx_offload_cfg(vport);
4968 if (ret)
4969 return ret;
4970 }
4971
5e43aef8 4972 handle = &hdev->vport[0].nic;
4e66632d 4973 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4974}
4975
3849d494 4976int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
5f9a7732
PL		 4977{
4978 struct hclge_vport *vport = hclge_get_vport(handle);
4979
4980 vport->rxvlan_cfg.strip_tag1_en = false;
4981 vport->rxvlan_cfg.strip_tag2_en = enable;
4982 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4983 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4984
4985 return hclge_set_vlan_rx_offload_cfg(vport);
4986}
4987
12341881 4988static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 4989{
d44f9b63 4990 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 4991 struct hclge_desc desc;
7393ed39 4992 int max_frm_size;
46a3df9f
S		 4993 int ret;
4994
7393ed39
FL		 4995 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4996
4997 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4998 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 4999 return -EINVAL;
5000
7393ed39
FL		 5001 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
5002
46a3df9f
S		 5003 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
5004
d44f9b63 5005 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
7393ed39 5006 req->max_frm_size = cpu_to_le16(max_frm_size);
51d43446 5007 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
46a3df9f
S		 5008
5009 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
e125295a 5010 if (ret)
46a3df9f 5011 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
e125295a
JS		 5012 else
5013 hdev->mps = max_frm_size;
7393ed39 5014
e125295a 5015 return ret;
46a3df9f
S		 5016}
5017
12341881
FL		 5018static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
5019{
5020 struct hclge_vport *vport = hclge_get_vport(handle);
5021 struct hclge_dev *hdev = vport->back;
5022 int ret;
5023
5024 ret = hclge_set_mac_mtu(hdev, new_mtu);
5025 if (ret) {
5026 dev_err(&hdev->pdev->dev,
5027 "Change mtu fail, ret =%d\n", ret);
5028 return ret;
5029 }
5030
5031 ret = hclge_buffer_alloc(hdev);
5032 if (ret)
5033 dev_err(&hdev->pdev->dev,
5034 "Allocate buffer fail, ret =%d\n", ret);
5035
5036 return ret;
5037}
5038
46a3df9f
S		 5039static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
5040 bool enable)
5041{
d44f9b63 5042 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5043 struct hclge_desc desc;
5044 int ret;
5045
5046 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
5047
d44f9b63 5048 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 5049 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
e22b531b 5050 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 5051
5052 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5053 if (ret) {
5054 dev_err(&hdev->pdev->dev,
5055 "Send tqp reset cmd error, status =%d\n", ret);
5056 return ret;
5057 }
5058
5059 return 0;
5060}
5061
5062static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
5063{
d44f9b63 5064 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 5065 struct hclge_desc desc;
5066 int ret;
5067
5068 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
5069
d44f9b63 5070 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 5071 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5072
5073 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5074 if (ret) {
5075 dev_err(&hdev->pdev->dev,
5076 "Get reset status error, status =%d\n", ret);
5077 return ret;
5078 }
5079
e22b531b 5080 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 5081}
5082
e5e89cda
PL		 5083static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
5084 u16 queue_id)
5085{
5086 struct hnae3_queue *queue;
5087 struct hclge_tqp *tqp;
5088
5089 queue = handle->kinfo.tqp[queue_id];
5090 tqp = container_of(queue, struct hclge_tqp, q);
5091
5092 return tqp->index;
5093}
5094
63d7e66f 5095void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 5096{
5097 struct hclge_vport *vport = hclge_get_vport(handle);
5098 struct hclge_dev *hdev = vport->back;
5099 int reset_try_times = 0;
5100 int reset_status;
e5e89cda 5101 u16 queue_gid;
46a3df9f
S		 5102 int ret;
5103
f9637cc2
PL		 5104 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5105 return;
5106
e5e89cda
PL		 5107 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
5108
46a3df9f
S		 5109 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
5110 if (ret) {
5111 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
5112 return;
5113 }
5114
e5e89cda 5115 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 5116 if (ret) {
5117 dev_warn(&hdev->pdev->dev,
5118 "Send reset tqp cmd fail, ret = %d\n", ret);
5119 return;
5120 }
5121
5122 reset_try_times = 0;
5123 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5124 /* Wait for tqp hw reset */
5125 msleep(20);
e5e89cda 5126 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 5127 if (reset_status)
5128 break;
5129 }
5130
5131 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5132 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5133 return;
5134 }
5135
e5e89cda 5136 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 5137 if (ret) {
5138 dev_warn(&hdev->pdev->dev,
5139 "Deassert the soft reset fail, ret = %d\n", ret);
5140 return;
5141 }
5142}
5143
d3ea7fc4
PL		 5144void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
5145{
5146 struct hclge_dev *hdev = vport->back;
5147 int reset_try_times = 0;
5148 int reset_status;
5149 u16 queue_gid;
5150 int ret;
5151
5152 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
5153
5154 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5155 if (ret) {
5156 dev_warn(&hdev->pdev->dev,
5157 "Send reset tqp cmd fail, ret = %d\n", ret);
5158 return;
5159 }
5160
5161 reset_try_times = 0;
5162 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5163 /* Wait for tqp hw reset */
5164 msleep(20);
5165 reset_status = hclge_get_reset_status(hdev, queue_gid);
5166 if (reset_status)
5167 break;
5168 }
5169
5170 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5171 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5172 return;
5173 }
5174
5175 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5176 if (ret)
5177 dev_warn(&hdev->pdev->dev,
5178 "Deassert the soft reset fail, ret = %d\n", ret);
5179}
5180
46a3df9f
S		 5181static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5182{
5183 struct hclge_vport *vport = hclge_get_vport(handle);
5184 struct hclge_dev *hdev = vport->back;
5185
5186 return hdev->fw_version;
5187}
5188
a2cfbadb
PL		 5189static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5190 u32 *flowctrl_adv)
5191{
5192 struct hclge_vport *vport = hclge_get_vport(handle);
5193 struct hclge_dev *hdev = vport->back;
5194 struct phy_device *phydev = hdev->hw.mac.phydev;
5195
5196 if (!phydev)
5197 return;
5198
5199 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5200 (phydev->advertising & ADVERTISED_Asym_Pause);
5201}
5202
09ea401e
PL		 5203static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5204{
5205 struct phy_device *phydev = hdev->hw.mac.phydev;
5206
5207 if (!phydev)
5208 return;
5209
5210 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
5211
5212 if (rx_en)
5213 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5214
5215 if (tx_en)
5216 phydev->advertising ^= ADVERTISED_Asym_Pause;
5217}
5218
5219static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5220{
09ea401e
PL		 5221 int ret;
5222
5223 if (rx_en && tx_en)
7a28a82a 5224 hdev->fc_mode_last_time = HCLGE_FC_FULL;
09ea401e 5225 else if (rx_en && !tx_en)
7a28a82a 5226 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
09ea401e 5227 else if (!rx_en && tx_en)
7a28a82a 5228 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
09ea401e 5229 else
7a28a82a 5230 hdev->fc_mode_last_time = HCLGE_FC_NONE;
09ea401e 5231
7a28a82a 5232 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
09ea401e 5233 return 0;
09ea401e
PL		 5234
5235 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
5236 if (ret) {
5237 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
5238 ret);
5239 return ret;
5240 }
5241
7a28a82a 5242 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
09ea401e
PL		 5243
5244 return 0;
5245}
5246
6282f2ea
PL		 5247int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5248{
5249 struct phy_device *phydev = hdev->hw.mac.phydev;
5250 u16 remote_advertising = 0;
5251 u16 local_advertising = 0;
5252 u32 rx_pause, tx_pause;
5253 u8 flowctl;
5254
5255 if (!phydev->link || !phydev->autoneg)
5256 return 0;
5257
5258 if (phydev->advertising & ADVERTISED_Pause)
5259 local_advertising = ADVERTISE_PAUSE_CAP;
5260
5261 if (phydev->advertising & ADVERTISED_Asym_Pause)
5262 local_advertising |= ADVERTISE_PAUSE_ASYM;
5263
5264 if (phydev->pause)
5265 remote_advertising = LPA_PAUSE_CAP;
5266
5267 if (phydev->asym_pause)
5268 remote_advertising |= LPA_PAUSE_ASYM;
5269
5270 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5271 remote_advertising);
5272 tx_pause = flowctl & FLOW_CTRL_TX;
5273 rx_pause = flowctl & FLOW_CTRL_RX;
5274
5275 if (phydev->duplex == HCLGE_MAC_HALF) {
5276 tx_pause = 0;
5277 rx_pause = 0;
5278 }
5279
5280 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5281}
5282
46a3df9f
S		 5283static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5284 u32 *rx_en, u32 *tx_en)
5285{
5286 struct hclge_vport *vport = hclge_get_vport(handle);
5287 struct hclge_dev *hdev = vport->back;
5288
5289 *auto_neg = hclge_get_autoneg(handle);
5290
5291 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5292 *rx_en = 0;
5293 *tx_en = 0;
5294 return;
5295 }
5296
5297 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5298 *rx_en = 1;
5299 *tx_en = 0;
5300 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5301 *tx_en = 1;
5302 *rx_en = 0;
5303 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5304 *rx_en = 1;
5305 *tx_en = 1;
5306 } else {
5307 *rx_en = 0;
5308 *tx_en = 0;
5309 }
5310}
5311
09ea401e
PL		 5312static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5313 u32 rx_en, u32 tx_en)
5314{
5315 struct hclge_vport *vport = hclge_get_vport(handle);
5316 struct hclge_dev *hdev = vport->back;
5317 struct phy_device *phydev = hdev->hw.mac.phydev;
5318 u32 fc_autoneg;
5319
09ea401e
PL		 5320 fc_autoneg = hclge_get_autoneg(handle);
5321 if (auto_neg != fc_autoneg) {
5322 dev_info(&hdev->pdev->dev,
5323 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5324 return -EOPNOTSUPP;
5325 }
5326
5327 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5328 dev_info(&hdev->pdev->dev,
5329 "Priority flow control enabled. Cannot set link flow control.\n");
5330 return -EOPNOTSUPP;
5331 }
5332
5333 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5334
5335 if (!fc_autoneg)
5336 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5337
bef24782
FL		 5338 /* Only support flow control negotiation for netdev with
5339 * phy attached for now.
5340 */
5341 if (!phydev)
5342 return -EOPNOTSUPP;
5343
09ea401e
PL		 5344 return phy_start_aneg(phydev);
5345}
5346
46a3df9f
S		 5347static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5348 u8 *auto_neg, u32 *speed, u8 *duplex)
5349{
5350 struct hclge_vport *vport = hclge_get_vport(handle);
5351 struct hclge_dev *hdev = vport->back;
5352
5353 if (speed)
5354 *speed = hdev->hw.mac.speed;
5355 if (duplex)
5356 *duplex = hdev->hw.mac.duplex;
5357 if (auto_neg)
5358 *auto_neg = hdev->hw.mac.autoneg;
5359}
5360
5361static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5362{
5363 struct hclge_vport *vport = hclge_get_vport(handle);
5364 struct hclge_dev *hdev = vport->back;
5365
5366 if (media_type)
5367 *media_type = hdev->hw.mac.media_type;
5368}
5369
5370static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5371 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5372{
5373 struct hclge_vport *vport = hclge_get_vport(handle);
5374 struct hclge_dev *hdev = vport->back;
5375 struct phy_device *phydev = hdev->hw.mac.phydev;
5376 int mdix_ctrl, mdix, retval, is_resolved;
5377
5378 if (!phydev) {
5379 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5380 *tp_mdix = ETH_TP_MDI_INVALID;
5381 return;
5382 }
5383
5384 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5385
5386 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
e22b531b
HT		 5387 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5388 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 5389
5390 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
e22b531b
HT		 5391 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5392 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 5393
5394 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5395
5396 switch (mdix_ctrl) {
5397 case 0x0:
5398 *tp_mdix_ctrl = ETH_TP_MDI;
5399 break;
5400 case 0x1:
5401 *tp_mdix_ctrl = ETH_TP_MDI_X;
5402 break;
5403 case 0x3:
5404 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5405 break;
5406 default:
5407 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5408 break;
5409 }
5410
5411 if (!is_resolved)
5412 *tp_mdix = ETH_TP_MDI_INVALID;
5413 else if (mdix)
5414 *tp_mdix = ETH_TP_MDI_X;
5415 else
5416 *tp_mdix = ETH_TP_MDI;
5417}
5418
5419static int hclge_init_client_instance(struct hnae3_client *client,
5420 struct hnae3_ae_dev *ae_dev)
5421{
5422 struct hclge_dev *hdev = ae_dev->priv;
5423 struct hclge_vport *vport;
5424 int i, ret;
5425
5426 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5427 vport = &hdev->vport[i];
5428
5429 switch (client->type) {
5430 case HNAE3_CLIENT_KNIC:
5431
5432 hdev->nic_client = client;
5433 vport->nic.client = client;
5434 ret = client->ops->init_instance(&vport->nic);
5435 if (ret)
6f636872 5436 return ret;
46a3df9f
S		 5437
5438 if (hdev->roce_client &&
e92a0843 5439 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5440 struct hnae3_client *rc = hdev->roce_client;
5441
5442 ret = hclge_init_roce_base_info(vport);
5443 if (ret)
6f636872 5444 return ret;
46a3df9f
S		 5445
5446 ret = rc->ops->init_instance(&vport->roce);
5447 if (ret)
6f636872 5448 return ret;
46a3df9f
S		 5449 }
5450
5451 break;
5452 case HNAE3_CLIENT_UNIC:
5453 hdev->nic_client = client;
5454 vport->nic.client = client;
5455
5456 ret = client->ops->init_instance(&vport->nic);
5457 if (ret)
6f636872 5458 return ret;
46a3df9f
S		 5459
5460 break;
5461 case HNAE3_CLIENT_ROCE:
e92a0843 5462 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5463 hdev->roce_client = client;
5464 vport->roce.client = client;
5465 }
5466
3a46f34d 5467 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5468 ret = hclge_init_roce_base_info(vport);
5469 if (ret)
6f636872 5470 return ret;
46a3df9f
S		 5471
5472 ret = client->ops->init_instance(&vport->roce);
5473 if (ret)
6f636872 5474 return ret;
46a3df9f
S		 5475 }
5476 }
5477 }
5478
5479 return 0;
46a3df9f
S		 5480}
5481
5482static void hclge_uninit_client_instance(struct hnae3_client *client,
5483 struct hnae3_ae_dev *ae_dev)
5484{
5485 struct hclge_dev *hdev = ae_dev->priv;
5486 struct hclge_vport *vport;
5487 int i;
5488
5489 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5490 vport = &hdev->vport[i];
a17dcf3f 5491 if (hdev->roce_client) {
46a3df9f
S		 5492 hdev->roce_client->ops->uninit_instance(&vport->roce,
5493 0);
a17dcf3f
L		 5494 hdev->roce_client = NULL;
5495 vport->roce.client = NULL;
5496 }
46a3df9f
S		 5497 if (client->type == HNAE3_CLIENT_ROCE)
5498 return;
a17dcf3f 5499 if (client->ops->uninit_instance) {
46a3df9f 5500 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5501 hdev->nic_client = NULL;
5502 vport->nic.client = NULL;
5503 }
46a3df9f
S		 5504 }
5505}
5506
5507static int hclge_pci_init(struct hclge_dev *hdev)
5508{
5509 struct pci_dev *pdev = hdev->pdev;
5510 struct hclge_hw *hw;
5511 int ret;
5512
5513 ret = pci_enable_device(pdev);
5514 if (ret) {
5515 dev_err(&pdev->dev, "failed to enable PCI device\n");
6c46284e 5516 return ret;
46a3df9f
S		 5517 }
5518
5519 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5520 if (ret) {
5521 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5522 if (ret) {
5523 dev_err(&pdev->dev,
5524 "can't set consistent PCI DMA");
5525 goto err_disable_device;
5526 }
5527 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5528 }
5529
5530 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5531 if (ret) {
5532 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5533 goto err_disable_device;
5534 }
5535
5536 pci_set_master(pdev);
5537 hw = &hdev->hw;
46a3df9f
S		 5538 hw->io_base = pcim_iomap(pdev, 2, 0);
5539 if (!hw->io_base) {
5540 dev_err(&pdev->dev, "Can't map configuration register space\n");
5541 ret = -ENOMEM;
5542 goto err_clr_master;
5543 }
5544
709eb41a
L		 5545 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5546
46a3df9f
S		 5547 return 0;
5548err_clr_master:
5549 pci_clear_master(pdev);
5550 pci_release_regions(pdev);
5551err_disable_device:
5552 pci_disable_device(pdev);
46a3df9f
S		 5553
5554 return ret;
5555}
5556
5557static void hclge_pci_uninit(struct hclge_dev *hdev)
5558{
5559 struct pci_dev *pdev = hdev->pdev;
5560
7d6d639b 5561 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 5562 pci_free_irq_vectors(pdev);
46a3df9f
S		 5563 pci_clear_master(pdev);
5564 pci_release_mem_regions(pdev);
5565 pci_disable_device(pdev);
5566}
5567
71d7e8ea
PL		 5568static void hclge_state_init(struct hclge_dev *hdev)
5569{
5570 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5571 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5572 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5573 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5574 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5575 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5576}
5577
5578static void hclge_state_uninit(struct hclge_dev *hdev)
5579{
5580 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5581
5582 if (hdev->service_timer.function)
5583 del_timer_sync(&hdev->service_timer);
5584 if (hdev->service_task.func)
5585 cancel_work_sync(&hdev->service_task);
5586 if (hdev->rst_service_task.func)
5587 cancel_work_sync(&hdev->rst_service_task);
5588 if (hdev->mbx_service_task.func)
5589 cancel_work_sync(&hdev->mbx_service_task);
5590}
5591
46a3df9f
S		 5592static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5593{
5594 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5595 struct hclge_dev *hdev;
5596 int ret;
5597
5598 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5599 if (!hdev) {
5600 ret = -ENOMEM;
e0027501 5601 goto out;
46a3df9f
S		 5602 }
5603
46a3df9f
S		 5604 hdev->pdev = pdev;
5605 hdev->ae_dev = ae_dev;
4ed340ab 5606 hdev->reset_type = HNAE3_NONE_RESET;
46a3df9f
S		 5607 ae_dev->priv = hdev;
5608
46a3df9f
S		 5609 ret = hclge_pci_init(hdev);
5610 if (ret) {
5611 dev_err(&pdev->dev, "PCI init failed\n");
e0027501 5612 goto out;
46a3df9f
S		 5613 }
5614
3efb960f
L		 5615 /* Firmware command queue initialize */
5616 ret = hclge_cmd_queue_init(hdev);
5617 if (ret) {
5618 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
e0027501 5619 goto err_pci_uninit;
3efb960f
L		 5620 }
5621
5622 /* Firmware command initialize */
46a3df9f
S		 5623 ret = hclge_cmd_init(hdev);
5624 if (ret)
e0027501 5625 goto err_cmd_uninit;
46a3df9f
S		 5626
5627 ret = hclge_get_cap(hdev);
5628 if (ret) {
e00e2197
CIK		 5629 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5630 ret);
e0027501 5631 goto err_cmd_uninit;
46a3df9f
S		 5632 }
5633
5634 ret = hclge_configure(hdev);
5635 if (ret) {
5636 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
e0027501 5637 goto err_cmd_uninit;
46a3df9f
S		 5638 }
5639
887c3820 5640 ret = hclge_init_msi(hdev);
46a3df9f 5641 if (ret) {
887c3820 5642 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
e0027501 5643 goto err_cmd_uninit;
46a3df9f
S		 5644 }
5645
466b0c00
L		 5646 ret = hclge_misc_irq_init(hdev);
5647 if (ret) {
5648 dev_err(&pdev->dev,
5649 "Misc IRQ(vector0) init error, ret = %d.\n",
5650 ret);
e0027501 5651 goto err_msi_uninit;
466b0c00
L		 5652 }
5653
46a3df9f
S		 5654 ret = hclge_alloc_tqps(hdev);
5655 if (ret) {
5656 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
e0027501 5657 goto err_msi_irq_uninit;
46a3df9f
S		 5658 }
5659
5660 ret = hclge_alloc_vport(hdev);
5661 if (ret) {
5662 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
e0027501 5663 goto err_msi_irq_uninit;
46a3df9f
S		 5664 }
5665
7df7dad6
L		 5666 ret = hclge_map_tqp(hdev);
5667 if (ret) {
5668 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
bc59f827 5669 goto err_msi_irq_uninit;
7df7dad6
L		 5670 }
5671
dea9a821
HT		 5672 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5673 ret = hclge_mac_mdio_config(hdev);
5674 if (ret) {
5675 dev_err(&hdev->pdev->dev,
5676 "mdio config fail ret=%d\n", ret);
bc59f827 5677 goto err_msi_irq_uninit;
dea9a821 5678 }
cf9cca2d 5679 }
5680
46a3df9f
S		 5681 ret = hclge_mac_init(hdev);
5682 if (ret) {
5683 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
e0027501 5684 goto err_mdiobus_unreg;
46a3df9f 5685 }
46a3df9f
S		 5686
5687 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5688 if (ret) {
5689 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
e0027501 5690 goto err_mdiobus_unreg;
46a3df9f
S		 5691 }
5692
46a3df9f
S		 5693 ret = hclge_init_vlan_config(hdev);
5694 if (ret) {
5695 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
e0027501 5696 goto err_mdiobus_unreg;
46a3df9f
S		 5697 }
5698
5699 ret = hclge_tm_schd_init(hdev);
5700 if (ret) {
5701 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
e0027501 5702 goto err_mdiobus_unreg;
68ece54e
YL		 5703 }
5704
8015bb74 5705 hclge_rss_init_cfg(hdev);
68ece54e
YL		 5706 ret = hclge_rss_init_hw(hdev);
5707 if (ret) {
5708 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
e0027501 5709 goto err_mdiobus_unreg;
46a3df9f
S		 5710 }
5711
635bfb58
FL		 5712 ret = init_mgr_tbl(hdev);
5713 if (ret) {
5714 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
e0027501 5715 goto err_mdiobus_unreg;
635bfb58
FL		 5716 }
5717
cacde272
YL		 5718 hclge_dcb_ops_set(hdev);
5719
d039ef68 5720 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5721 INIT_WORK(&hdev->service_task, hclge_service_task);
ed4a1bb8 5722 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
22fd3468 5723 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5724
466b0c00
L		 5725 /* Enable MISC vector(vector0) */
5726 hclge_enable_vector(&hdev->misc_vector, true);
5727
71d7e8ea 5728 hclge_state_init(hdev);
46a3df9f
S		 5729
5730 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5731 return 0;
5732
e0027501
HT		 5733err_mdiobus_unreg:
5734 if (hdev->hw.mac.phydev)
5735 mdiobus_unregister(hdev->hw.mac.mdio_bus);
e0027501
HT		 5736err_msi_irq_uninit:
5737 hclge_misc_irq_uninit(hdev);
5738err_msi_uninit:
5739 pci_free_irq_vectors(pdev);
5740err_cmd_uninit:
5741 hclge_destroy_cmd_queue(&hdev->hw);
5742err_pci_uninit:
7d6d639b 5743 pcim_iounmap(pdev, hdev->hw.io_base);
e0027501 5744 pci_clear_master(pdev);
46a3df9f 5745 pci_release_regions(pdev);
e0027501 5746 pci_disable_device(pdev);
e0027501 5747out:
46a3df9f
S		 5748 return ret;
5749}
5750
c6dc5213 5751static void hclge_stats_clear(struct hclge_dev *hdev)
5752{
5753 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5754}
5755
4ed340ab
L		 5756static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5757{
5758 struct hclge_dev *hdev = ae_dev->priv;
5759 struct pci_dev *pdev = ae_dev->pdev;
5760 int ret;
5761
5762 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5763
c6dc5213 5764 hclge_stats_clear(hdev);
4e66632d 5765 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 5766
4ed340ab
L		 5767 ret = hclge_cmd_init(hdev);
5768 if (ret) {
5769 dev_err(&pdev->dev, "Cmd queue init failed\n");
5770 return ret;
5771 }
5772
5773 ret = hclge_get_cap(hdev);
5774 if (ret) {
5775 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5776 ret);
5777 return ret;
5778 }
5779
5780 ret = hclge_configure(hdev);
5781 if (ret) {
5782 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5783 return ret;
5784 }
5785
5786 ret = hclge_map_tqp(hdev);
5787 if (ret) {
5788 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5789 return ret;
5790 }
5791
5792 ret = hclge_mac_init(hdev);
5793 if (ret) {
5794 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5795 return ret;
5796 }
5797
4ed340ab
L		 5798 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5799 if (ret) {
5800 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5801 return ret;
5802 }
5803
5804 ret = hclge_init_vlan_config(hdev);
5805 if (ret) {
5806 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5807 return ret;
5808 }
5809
d85f1ab5 5810 ret = hclge_tm_init_hw(hdev);
4ed340ab 5811 if (ret) {
d85f1ab5 5812 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 5813 return ret;
5814 }
5815
5816 ret = hclge_rss_init_hw(hdev);
5817 if (ret) {
5818 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5819 return ret;
5820 }
5821
4ed340ab
L		 5822 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5823 HCLGE_DRIVER_NAME);
5824
5825 return 0;
5826}
5827
46a3df9f
S		 5828static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5829{
5830 struct hclge_dev *hdev = ae_dev->priv;
5831 struct hclge_mac *mac = &hdev->hw.mac;
5832
71d7e8ea 5833 hclge_state_uninit(hdev);
46a3df9f
S		 5834
5835 if (mac->phydev)
5836 mdiobus_unregister(mac->mdio_bus);
5837
466b0c00
L		 5838 /* Disable MISC vector(vector0) */
5839 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 5840 hclge_destroy_cmd_queue(&hdev->hw);
202f2014 5841 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5842 hclge_pci_uninit(hdev);
5843 ae_dev->priv = NULL;
5844}
5845
4f645a90
PL		 5846static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5847{
5848 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5849 struct hclge_vport *vport = hclge_get_vport(handle);
5850 struct hclge_dev *hdev = vport->back;
5851
5852 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5853}
5854
5855static void hclge_get_channels(struct hnae3_handle *handle,
5856 struct ethtool_channels *ch)
5857{
5858 struct hclge_vport *vport = hclge_get_vport(handle);
5859
5860 ch->max_combined = hclge_get_max_channels(handle);
5861 ch->other_count = 1;
5862 ch->max_other = 1;
5863 ch->combined_count = vport->alloc_tqps;
5864}
5865
f1f779ce
PL		 5866static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5867 u16 *free_tqps, u16 *max_rss_size)
5868{
5869 struct hclge_vport *vport = hclge_get_vport(handle);
5870 struct hclge_dev *hdev = vport->back;
5871 u16 temp_tqps = 0;
5872 int i;
5873
5874 for (i = 0; i < hdev->num_tqps; i++) {
5875 if (!hdev->htqp[i].alloced)
5876 temp_tqps++;
5877 }
5878 *free_tqps = temp_tqps;
5879 *max_rss_size = hdev->rss_size_max;
5880}
5881
5882static void hclge_release_tqp(struct hclge_vport *vport)
5883{
5884 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5885 struct hclge_dev *hdev = vport->back;
5886 int i;
5887
5888 for (i = 0; i < kinfo->num_tqps; i++) {
5889 struct hclge_tqp *tqp =
5890 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5891
5892 tqp->q.handle = NULL;
5893 tqp->q.tqp_index = 0;
5894 tqp->alloced = false;
5895 }
5896
5897 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5898 kinfo->tqp = NULL;
5899}
5900
5901static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5902{
5903 struct hclge_vport *vport = hclge_get_vport(handle);
5904 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5905 struct hclge_dev *hdev = vport->back;
5906 int cur_rss_size = kinfo->rss_size;
5907 int cur_tqps = kinfo->num_tqps;
5908 u16 tc_offset[HCLGE_MAX_TC_NUM];
5909 u16 tc_valid[HCLGE_MAX_TC_NUM];
5910 u16 tc_size[HCLGE_MAX_TC_NUM];
5911 u16 roundup_size;
5912 u32 *rss_indir;
5913 int ret, i;
5914
ec7a62b9 5915 /* Free old tqps, and reallocate with new tqp number when nic setup */
f1f779ce
PL		 5916 hclge_release_tqp(vport);
5917
5918 ret = hclge_knic_setup(vport, new_tqps_num);
5919 if (ret) {
5920 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5921 return ret;
5922 }
5923
5924 ret = hclge_map_tqp_to_vport(hdev, vport);
5925 if (ret) {
5926 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5927 return ret;
5928 }
5929
5930 ret = hclge_tm_schd_init(hdev);
5931 if (ret) {
5932 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5933 return ret;
5934 }
5935
5936 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5937 roundup_size = ilog2(roundup_size);
5938 /* Set the RSS TC mode according to the new RSS size */
5939 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5940 tc_valid[i] = 0;
5941
5942 if (!(hdev->hw_tc_map & BIT(i)))
5943 continue;
5944
5945 tc_valid[i] = 1;
5946 tc_size[i] = roundup_size;
5947 tc_offset[i] = kinfo->rss_size * i;
5948 }
5949 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5950 if (ret)
5951 return ret;
5952
5953 /* Reinitializes the rss indirect table according to the new RSS size */
5954 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5955 if (!rss_indir)
5956 return -ENOMEM;
5957
5958 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5959 rss_indir[i] = i % kinfo->rss_size;
5960
5961 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5962 if (ret)
5963 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5964 ret);
5965
5966 kfree(rss_indir);
5967
5968 if (!ret)
5969 dev_info(&hdev->pdev->dev,
5970 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5971 cur_rss_size, kinfo->rss_size,
5972 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5973
5974 return ret;
5975}
5976
db2a3e43
FL		 5977static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5978 u32 *regs_num_64_bit)
5979{
5980 struct hclge_desc desc;
5981 u32 total_num;
5982 int ret;
5983
5984 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5985 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5986 if (ret) {
5987 dev_err(&hdev->pdev->dev,
5988 "Query register number cmd failed, ret = %d.\n", ret);
5989 return ret;
5990 }
5991
5992 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5993 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5994
5995 total_num = *regs_num_32_bit + *regs_num_64_bit;
5996 if (!total_num)
5997 return -EINVAL;
5998
5999 return 0;
6000}
6001
6002static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6003 void *data)
6004{
6005#define HCLGE_32_BIT_REG_RTN_DATANUM 8
6006
6007 struct hclge_desc *desc;
6008 u32 *reg_val = data;
6009 __le32 *desc_data;
6010 int cmd_num;
6011 int i, k, n;
6012 int ret;
6013
6014 if (regs_num == 0)
6015 return 0;
6016
6017 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
6018 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6019 if (!desc)
6020 return -ENOMEM;
6021
6022 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
6023 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6024 if (ret) {
6025 dev_err(&hdev->pdev->dev,
6026 "Query 32 bit register cmd failed, ret = %d.\n", ret);
6027 kfree(desc);
6028 return ret;
6029 }
6030
6031 for (i = 0; i < cmd_num; i++) {
6032 if (i == 0) {
6033 desc_data = (__le32 *)(&desc[i].data[0]);
6034 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
6035 } else {
6036 desc_data = (__le32 *)(&desc[i]);
6037 n = HCLGE_32_BIT_REG_RTN_DATANUM;
6038 }
6039 for (k = 0; k < n; k++) {
6040 *reg_val++ = le32_to_cpu(*desc_data++);
6041
6042 regs_num--;
6043 if (!regs_num)
6044 break;
6045 }
6046 }
6047
6048 kfree(desc);
6049 return 0;
6050}
6051
6052static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6053 void *data)
6054{
6055#define HCLGE_64_BIT_REG_RTN_DATANUM 4
6056
6057 struct hclge_desc *desc;
6058 u64 *reg_val = data;
6059 __le64 *desc_data;
6060 int cmd_num;
6061 int i, k, n;
6062 int ret;
6063
6064 if (regs_num == 0)
6065 return 0;
6066
6067 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
6068 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6069 if (!desc)
6070 return -ENOMEM;
6071
6072 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
6073 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6074 if (ret) {
6075 dev_err(&hdev->pdev->dev,
6076 "Query 64 bit register cmd failed, ret = %d.\n", ret);
6077 kfree(desc);
6078 return ret;
6079 }
6080
6081 for (i = 0; i < cmd_num; i++) {
6082 if (i == 0) {
6083 desc_data = (__le64 *)(&desc[i].data[0]);
6084 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
6085 } else {
6086 desc_data = (__le64 *)(&desc[i]);
6087 n = HCLGE_64_BIT_REG_RTN_DATANUM;
6088 }
6089 for (k = 0; k < n; k++) {
6090 *reg_val++ = le64_to_cpu(*desc_data++);
6091
6092 regs_num--;
6093 if (!regs_num)
6094 break;
6095 }
6096 }
6097
6098 kfree(desc);
6099 return 0;
6100}
6101
6102static int hclge_get_regs_len(struct hnae3_handle *handle)
6103{
6104 struct hclge_vport *vport = hclge_get_vport(handle);
6105 struct hclge_dev *hdev = vport->back;
6106 u32 regs_num_32_bit, regs_num_64_bit;
6107 int ret;
6108
6109 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6110 if (ret) {
6111 dev_err(&hdev->pdev->dev,
6112 "Get register number failed, ret = %d.\n", ret);
6113 return -EOPNOTSUPP;
6114 }
6115
6116 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
6117}
6118
6119static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
6120 void *data)
6121{
6122 struct hclge_vport *vport = hclge_get_vport(handle);
6123 struct hclge_dev *hdev = vport->back;
6124 u32 regs_num_32_bit, regs_num_64_bit;
6125 int ret;
6126
6127 *version = hdev->fw_version;
6128
6129 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6130 if (ret) {
6131 dev_err(&hdev->pdev->dev,
6132 "Get register number failed, ret = %d.\n", ret);
6133 return;
6134 }
6135
6136 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
6137 if (ret) {
6138 dev_err(&hdev->pdev->dev,
6139 "Get 32 bit register failed, ret = %d.\n", ret);
6140 return;
6141 }
6142
6143 data = (u32 *)data + regs_num_32_bit;
6144 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
6145 data);
6146 if (ret)
6147 dev_err(&hdev->pdev->dev,
6148 "Get 64 bit register failed, ret = %d.\n", ret);
6149}
6150
fe3a3e15 6151static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
d9a0884e
JS		 6152{
6153 struct hclge_set_led_state_cmd *req;
6154 struct hclge_desc desc;
6155 int ret;
6156
6157 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
6158
6159 req = (struct hclge_set_led_state_cmd *)desc.data;
e22b531b 6160 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
d9a0884e
JS		 6161 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6162
6163 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6164 if (ret)
6165 dev_err(&hdev->pdev->dev,
6166 "Send set led state cmd error, ret =%d\n", ret);
6167
6168 return ret;
6169}
6170
6171enum hclge_led_status {
6172 HCLGE_LED_OFF,
6173 HCLGE_LED_ON,
6174 HCLGE_LED_NO_CHANGE = 0xFF,
6175};
6176
6177static int hclge_set_led_id(struct hnae3_handle *handle,
6178 enum ethtool_phys_id_state status)
6179{
d9a0884e
JS		 6180 struct hclge_vport *vport = hclge_get_vport(handle);
6181 struct hclge_dev *hdev = vport->back;
d9a0884e
JS		 6182
6183 switch (status) {
6184 case ETHTOOL_ID_ACTIVE:
fe3a3e15 6185 return hclge_set_led_status(hdev, HCLGE_LED_ON);
d9a0884e 6186 case ETHTOOL_ID_INACTIVE:
fe3a3e15 6187 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
d9a0884e 6188 default:
fe3a3e15 6189 return -EINVAL;
d9a0884e 6190 }
d9a0884e
JS		 6191}
6192
d92ceae9
FL		 6193static void hclge_get_link_mode(struct hnae3_handle *handle,
6194 unsigned long *supported,
6195 unsigned long *advertising)
6196{
6197 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
6198 struct hclge_vport *vport = hclge_get_vport(handle);
6199 struct hclge_dev *hdev = vport->back;
6200 unsigned int idx = 0;
6201
6202 for (; idx < size; idx++) {
6203 supported[idx] = hdev->hw.mac.supported[idx];
6204 advertising[idx] = hdev->hw.mac.advertising[idx];
6205 }
6206}
6207
6208static void hclge_get_port_type(struct hnae3_handle *handle,
6209 u8 *port_type)
6210{
6211 struct hclge_vport *vport = hclge_get_vport(handle);
6212 struct hclge_dev *hdev = vport->back;
6213 u8 media_type = hdev->hw.mac.media_type;
6214
6215 switch (media_type) {
6216 case HNAE3_MEDIA_TYPE_FIBER:
6217 *port_type = PORT_FIBRE;
6218 break;
6219 case HNAE3_MEDIA_TYPE_COPPER:
6220 *port_type = PORT_TP;
6221 break;
6222 case HNAE3_MEDIA_TYPE_UNKNOWN:
6223 default:
6224 *port_type = PORT_OTHER;
6225 break;
6226 }
6227}
6228
46a3df9f
S		 6229static const struct hnae3_ae_ops hclge_ops = {
6230 .init_ae_dev = hclge_init_ae_dev,
6231 .uninit_ae_dev = hclge_uninit_ae_dev,
6232 .init_client_instance = hclge_init_client_instance,
6233 .uninit_client_instance = hclge_uninit_client_instance,
63d7e66f
SM		 6234 .map_ring_to_vector = hclge_map_ring_to_vector,
6235 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 6236 .get_vector = hclge_get_vector,
7412200c 6237 .put_vector = hclge_put_vector,
46a3df9f 6238 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 6239 .set_loopback = hclge_set_loopback,
46a3df9f
S		 6240 .start = hclge_ae_start,
6241 .stop = hclge_ae_stop,
6242 .get_status = hclge_get_status,
6243 .get_ksettings_an_result = hclge_get_ksettings_an_result,
6244 .update_speed_duplex_h = hclge_update_speed_duplex_h,
6245 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6246 .get_media_type = hclge_get_media_type,
6247 .get_rss_key_size = hclge_get_rss_key_size,
6248 .get_rss_indir_size = hclge_get_rss_indir_size,
6249 .get_rss = hclge_get_rss,
6250 .set_rss = hclge_set_rss,
f7db940a 6251 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 6252 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 6253 .get_tc_size = hclge_get_tc_size,
6254 .get_mac_addr = hclge_get_mac_addr,
6255 .set_mac_addr = hclge_set_mac_addr,
6256 .add_uc_addr = hclge_add_uc_addr,
6257 .rm_uc_addr = hclge_rm_uc_addr,
6258 .add_mc_addr = hclge_add_mc_addr,
6259 .rm_mc_addr = hclge_rm_mc_addr,
a832d8b5 6260 .update_mta_status = hclge_update_mta_status,
46a3df9f
S		 6261 .set_autoneg = hclge_set_autoneg,
6262 .get_autoneg = hclge_get_autoneg,
6263 .get_pauseparam = hclge_get_pauseparam,
09ea401e 6264 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6265 .set_mtu = hclge_set_mtu,
6266 .reset_queue = hclge_reset_tqp,
6267 .get_stats = hclge_get_stats,
6268 .update_stats = hclge_update_stats,
6269 .get_strings = hclge_get_strings,
6270 .get_sset_count = hclge_get_sset_count,
6271 .get_fw_version = hclge_get_fw_version,
6272 .get_mdix_mode = hclge_get_mdix_mode,
d818396d 6273 .enable_vlan_filter = hclge_enable_vlan_filter,
4e66632d 6274 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 6275 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5f9a7732 6276 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6277 .reset_event = hclge_reset_event,
f1f779ce
PL		 6278 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6279 .set_channels = hclge_set_channels,
4f645a90 6280 .get_channels = hclge_get_channels,
a2cfbadb 6281 .get_flowctrl_adv = hclge_get_flowctrl_adv,
db2a3e43
FL		 6282 .get_regs_len = hclge_get_regs_len,
6283 .get_regs = hclge_get_regs,
d9a0884e 6284 .set_led_id = hclge_set_led_id,
d92ceae9
FL		 6285 .get_link_mode = hclge_get_link_mode,
6286 .get_port_type = hclge_get_port_type,
46a3df9f
S		 6287};
6288
6289static struct hnae3_ae_algo ae_algo = {
6290 .ops = &hclge_ops,
46a3df9f
S		 6291 .pdev_id_table = ae_algo_pci_tbl,
6292};
6293
6294static int hclge_init(void)
6295{
6296 pr_info("%s is initializing\n", HCLGE_NAME);
6297
a4d090cc
FL		 6298 hnae3_register_ae_algo(&ae_algo);
6299
6300 return 0;
46a3df9f
S		 6301}
6302
6303static void hclge_exit(void)
6304{
6305 hnae3_unregister_ae_algo(&ae_algo);
6306}
6307module_init(hclge_init);
6308module_exit(hclge_exit);
6309
6310MODULE_LICENSE("GPL");
6311MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6312MODULE_DESCRIPTION("HCLGE Driver");
6313MODULE_VERSION(HCLGE_MOD_VERSION);
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