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net: hns3: Support two vlan header when setting mtu
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
ef57c40f
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
46a3df9f
S		 3
4#include <linux/acpi.h>
5#include <linux/device.h>
6#include <linux/etherdevice.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
7393ed39 14#include <linux/if_vlan.h>
d5752031 15#include <net/rtnetlink.h>
46a3df9f 16#include "hclge_cmd.h"
cacde272 17#include "hclge_dcb.h"
46a3df9f 18#include "hclge_main.h"
0cdbdd3e 19#include "hclge_mbx.h"
46a3df9f
S		 20#include "hclge_mdio.h"
21#include "hclge_tm.h"
00bb612a 22#include "hclge_err.h"
46a3df9f
S		 23#include "hnae3.h"
24
25#define HCLGE_NAME "hclge"
26#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
27#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
46a3df9f 28
59bc85ec 29static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 30static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 31static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
2da5ec58
JS		 32static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
33 u16 *allocated_size, bool is_alloc);
46a3df9f
S		 34
35static struct hnae3_ae_algo ae_algo;
36
37static const struct pci_device_id ae_algo_pci_tbl[] = {
38 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
39 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 45 /* required last entry */
46a3df9f
S		 46 {0, }
47};
48
28d9cec8
YL		 49MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
50
46a3df9f 51static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
67b8c316 52 "App Loopback test",
86957272
FL		 53 "Serdes serial Loopback test",
54 "Serdes parallel Loopback test",
46a3df9f
S		 55 "Phy Loopback test"
56};
57
46a3df9f
S		 58static const struct hclge_comm_stats_str g_mac_stats_string[] = {
59 {"mac_tx_mac_pause_num",
60 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
61 {"mac_rx_mac_pause_num",
62 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
63 {"mac_tx_pfc_pri0_pkt_num",
64 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
65 {"mac_tx_pfc_pri1_pkt_num",
66 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
67 {"mac_tx_pfc_pri2_pkt_num",
68 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
69 {"mac_tx_pfc_pri3_pkt_num",
70 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
71 {"mac_tx_pfc_pri4_pkt_num",
72 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
73 {"mac_tx_pfc_pri5_pkt_num",
74 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
75 {"mac_tx_pfc_pri6_pkt_num",
76 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
77 {"mac_tx_pfc_pri7_pkt_num",
78 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
79 {"mac_rx_pfc_pri0_pkt_num",
80 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
81 {"mac_rx_pfc_pri1_pkt_num",
82 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
83 {"mac_rx_pfc_pri2_pkt_num",
84 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
85 {"mac_rx_pfc_pri3_pkt_num",
86 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
87 {"mac_rx_pfc_pri4_pkt_num",
88 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
89 {"mac_rx_pfc_pri5_pkt_num",
90 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
91 {"mac_rx_pfc_pri6_pkt_num",
92 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
93 {"mac_rx_pfc_pri7_pkt_num",
94 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
95 {"mac_tx_total_pkt_num",
96 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
97 {"mac_tx_total_oct_num",
98 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
99 {"mac_tx_good_pkt_num",
100 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
101 {"mac_tx_bad_pkt_num",
102 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
103 {"mac_tx_good_oct_num",
104 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
105 {"mac_tx_bad_oct_num",
106 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
107 {"mac_tx_uni_pkt_num",
108 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
109 {"mac_tx_multi_pkt_num",
110 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
111 {"mac_tx_broad_pkt_num",
112 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
113 {"mac_tx_undersize_pkt_num",
114 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
f3426583
JS		 115 {"mac_tx_oversize_pkt_num",
116 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 117 {"mac_tx_64_oct_pkt_num",
118 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
119 {"mac_tx_65_127_oct_pkt_num",
120 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
121 {"mac_tx_128_255_oct_pkt_num",
122 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
123 {"mac_tx_256_511_oct_pkt_num",
124 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
125 {"mac_tx_512_1023_oct_pkt_num",
126 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
127 {"mac_tx_1024_1518_oct_pkt_num",
128 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
b42874e4
JS		 129 {"mac_tx_1519_2047_oct_pkt_num",
130 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
131 {"mac_tx_2048_4095_oct_pkt_num",
132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
133 {"mac_tx_4096_8191_oct_pkt_num",
134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
b42874e4
JS		 135 {"mac_tx_8192_9216_oct_pkt_num",
136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
137 {"mac_tx_9217_12287_oct_pkt_num",
138 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
139 {"mac_tx_12288_16383_oct_pkt_num",
140 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
141 {"mac_tx_1519_max_good_pkt_num",
142 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
143 {"mac_tx_1519_max_bad_pkt_num",
144 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 145 {"mac_rx_total_pkt_num",
146 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
147 {"mac_rx_total_oct_num",
148 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
149 {"mac_rx_good_pkt_num",
150 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
151 {"mac_rx_bad_pkt_num",
152 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
153 {"mac_rx_good_oct_num",
154 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
155 {"mac_rx_bad_oct_num",
156 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
157 {"mac_rx_uni_pkt_num",
158 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
159 {"mac_rx_multi_pkt_num",
160 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
161 {"mac_rx_broad_pkt_num",
162 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
163 {"mac_rx_undersize_pkt_num",
164 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
f3426583
JS		 165 {"mac_rx_oversize_pkt_num",
166 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 167 {"mac_rx_64_oct_pkt_num",
168 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
169 {"mac_rx_65_127_oct_pkt_num",
170 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
171 {"mac_rx_128_255_oct_pkt_num",
172 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
173 {"mac_rx_256_511_oct_pkt_num",
174 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
175 {"mac_rx_512_1023_oct_pkt_num",
176 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
177 {"mac_rx_1024_1518_oct_pkt_num",
178 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
b42874e4
JS		 179 {"mac_rx_1519_2047_oct_pkt_num",
180 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
181 {"mac_rx_2048_4095_oct_pkt_num",
182 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
183 {"mac_rx_4096_8191_oct_pkt_num",
184 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
b42874e4
JS		 185 {"mac_rx_8192_9216_oct_pkt_num",
186 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
187 {"mac_rx_9217_12287_oct_pkt_num",
188 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
189 {"mac_rx_12288_16383_oct_pkt_num",
190 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
191 {"mac_rx_1519_max_good_pkt_num",
192 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
193 {"mac_rx_1519_max_bad_pkt_num",
194 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 195
c36317be
JS		 196 {"mac_tx_fragment_pkt_num",
197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
198 {"mac_tx_undermin_pkt_num",
199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
200 {"mac_tx_jabber_pkt_num",
201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
202 {"mac_tx_err_all_pkt_num",
203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
204 {"mac_tx_from_app_good_pkt_num",
205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
206 {"mac_tx_from_app_bad_pkt_num",
207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
208 {"mac_rx_fragment_pkt_num",
209 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
210 {"mac_rx_undermin_pkt_num",
211 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
212 {"mac_rx_jabber_pkt_num",
213 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
214 {"mac_rx_fcs_err_pkt_num",
215 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
216 {"mac_rx_send_app_good_pkt_num",
217 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
218 {"mac_rx_send_app_bad_pkt_num",
219 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 220};
221
635bfb58
FL		 222static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
223 {
224 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
225 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
226 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
227 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
228 .i_port_bitmap = 0x1,
229 },
230};
231
46a3df9f
S		 232static int hclge_mac_update_stats(struct hclge_dev *hdev)
233{
b42874e4 234#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 235#define HCLGE_RTN_DATA_NUM 4
236
237 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
238 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 239 __le64 *desc_data;
46a3df9f
S		 240 int i, k, n;
241 int ret;
242
243 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
244 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
245 if (ret) {
246 dev_err(&hdev->pdev->dev,
247 "Get MAC pkt stats fail, status = %d.\n", ret);
248
249 return ret;
250 }
251
252 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
253 if (unlikely(i == 0)) {
a90bb9a5 254 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 255 n = HCLGE_RTN_DATA_NUM - 2;
256 } else {
a90bb9a5 257 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 258 n = HCLGE_RTN_DATA_NUM;
259 }
260 for (k = 0; k < n; k++) {
a90bb9a5 261 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 262 desc_data++;
263 }
264 }
265
266 return 0;
267}
268
269static int hclge_tqps_update_stats(struct hnae3_handle *handle)
270{
271 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
272 struct hclge_vport *vport = hclge_get_vport(handle);
273 struct hclge_dev *hdev = vport->back;
274 struct hnae3_queue *queue;
275 struct hclge_desc desc[1];
276 struct hclge_tqp *tqp;
277 int ret, i;
278
279 for (i = 0; i < kinfo->num_tqps; i++) {
280 queue = handle->kinfo.tqp[i];
281 tqp = container_of(queue, struct hclge_tqp, q);
282 /* command : HCLGE_OPC_QUERY_IGU_STAT */
283 hclge_cmd_setup_basic_desc(&desc[0],
284 HCLGE_OPC_QUERY_RX_STATUS,
285 true);
286
a90bb9a5 287 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 288 ret = hclge_cmd_send(&hdev->hw, desc, 1);
289 if (ret) {
290 dev_err(&hdev->pdev->dev,
291 "Query tqp stat fail, status = %d,queue = %d\n",
292 ret, i);
293 return ret;
294 }
295 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 296 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 297 }
298
299 for (i = 0; i < kinfo->num_tqps; i++) {
300 queue = handle->kinfo.tqp[i];
301 tqp = container_of(queue, struct hclge_tqp, q);
302 /* command : HCLGE_OPC_QUERY_IGU_STAT */
303 hclge_cmd_setup_basic_desc(&desc[0],
304 HCLGE_OPC_QUERY_TX_STATUS,
305 true);
306
a90bb9a5 307 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 308 ret = hclge_cmd_send(&hdev->hw, desc, 1);
309 if (ret) {
310 dev_err(&hdev->pdev->dev,
311 "Query tqp stat fail, status = %d,queue = %d\n",
312 ret, i);
313 return ret;
314 }
315 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 316 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 317 }
318
319 return 0;
320}
321
322static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
323{
324 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
325 struct hclge_tqp *tqp;
326 u64 *buff = data;
327 int i;
328
329 for (i = 0; i < kinfo->num_tqps; i++) {
330 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 331 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 332 }
333
334 for (i = 0; i < kinfo->num_tqps; i++) {
335 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 336 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 337 }
338
339 return buff;
340}
341
342static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
343{
344 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
345
346 return kinfo->num_tqps * (2);
347}
348
349static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
350{
351 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
352 u8 *buff = data;
353 int i = 0;
354
355 for (i = 0; i < kinfo->num_tqps; i++) {
356 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
357 struct hclge_tqp, q);
eedff8c0 358 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
46a3df9f
S		 359 tqp->index);
360 buff = buff + ETH_GSTRING_LEN;
361 }
362
363 for (i = 0; i < kinfo->num_tqps; i++) {
364 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
365 struct hclge_tqp, q);
eedff8c0 366 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
46a3df9f
S		 367 tqp->index);
368 buff = buff + ETH_GSTRING_LEN;
369 }
370
371 return buff;
372}
373
374static u64 *hclge_comm_get_stats(void *comm_stats,
375 const struct hclge_comm_stats_str strs[],
376 int size, u64 *data)
377{
378 u64 *buf = data;
379 u32 i;
380
381 for (i = 0; i < size; i++)
382 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
383
384 return buf + size;
385}
386
387static u8 *hclge_comm_get_strings(u32 stringset,
388 const struct hclge_comm_stats_str strs[],
389 int size, u8 *data)
390{
391 char *buff = (char *)data;
392 u32 i;
393
394 if (stringset != ETH_SS_STATS)
395 return buff;
396
397 for (i = 0; i < size; i++) {
398 snprintf(buff, ETH_GSTRING_LEN,
399 strs[i].desc);
400 buff = buff + ETH_GSTRING_LEN;
401 }
402
403 return (u8 *)buff;
404}
405
406static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
407 struct net_device_stats *net_stats)
408{
409 net_stats->tx_dropped = 0;
f3426583 410 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 411 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
c36317be 412 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 413
414 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
415 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
416
c36317be 417 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 418 net_stats->rx_length_errors =
419 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
420 net_stats->rx_length_errors +=
f3426583 421 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 422 net_stats->rx_over_errors =
f3426583 423 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 424}
425
426static void hclge_update_stats_for_all(struct hclge_dev *hdev)
427{
428 struct hnae3_handle *handle;
429 int status;
430
431 handle = &hdev->vport[0].nic;
432 if (handle->client) {
433 status = hclge_tqps_update_stats(handle);
434 if (status) {
435 dev_err(&hdev->pdev->dev,
436 "Update TQPS stats fail, status = %d.\n",
437 status);
438 }
439 }
440
441 status = hclge_mac_update_stats(hdev);
442 if (status)
443 dev_err(&hdev->pdev->dev,
444 "Update MAC stats fail, status = %d.\n", status);
445
46a3df9f
S		 446 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
447}
448
449static void hclge_update_stats(struct hnae3_handle *handle,
450 struct net_device_stats *net_stats)
451{
452 struct hclge_vport *vport = hclge_get_vport(handle);
453 struct hclge_dev *hdev = vport->back;
454 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
455 int status;
456
7a5d2a39
JS		 457 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
458 return;
459
46a3df9f
S		 460 status = hclge_mac_update_stats(hdev);
461 if (status)
462 dev_err(&hdev->pdev->dev,
463 "Update MAC stats fail, status = %d.\n",
464 status);
465
46a3df9f
S		 466 status = hclge_tqps_update_stats(handle);
467 if (status)
468 dev_err(&hdev->pdev->dev,
469 "Update TQPS stats fail, status = %d.\n",
470 status);
471
472 hclge_update_netstat(hw_stats, net_stats);
7a5d2a39
JS		 473
474 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 475}
476
477static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
478{
86957272
FL		 479#define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
480 HNAE3_SUPPORT_PHY_LOOPBACK |\
481 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
482 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
46a3df9f
S		 483
484 struct hclge_vport *vport = hclge_get_vport(handle);
485 struct hclge_dev *hdev = vport->back;
486 int count = 0;
487
488 /* Loopback test support rules:
489 * mac: only GE mode support
490 * serdes: all mac mode will support include GE/XGE/LGE/CGE
491 * phy: only support when phy device exist on board
492 */
493 if (stringset == ETH_SS_TEST) {
494 /* clear loopback bit flags at first */
495 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
735f1df8 496 if (hdev->pdev->revision >= 0x21 ||
86957272 497 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
46a3df9f
S		 498 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
499 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
500 count += 1;
67b8c316 501 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
46a3df9f 502 }
e006bb00 503
86957272
FL		 504 count += 2;
505 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
506 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
46a3df9f
S		 507 } else if (stringset == ETH_SS_STATS) {
508 count = ARRAY_SIZE(g_mac_stats_string) +
46a3df9f
S		 509 hclge_tqps_get_sset_count(handle, stringset);
510 }
511
512 return count;
513}
514
515static void hclge_get_strings(struct hnae3_handle *handle,
516 u32 stringset,
517 u8 *data)
518{
519 u8 *p = (char *)data;
520 int size;
521
522 if (stringset == ETH_SS_STATS) {
523 size = ARRAY_SIZE(g_mac_stats_string);
524 p = hclge_comm_get_strings(stringset,
525 g_mac_stats_string,
526 size,
527 p);
46a3df9f
S		 528 p = hclge_tqps_get_strings(handle, p);
529 } else if (stringset == ETH_SS_TEST) {
67b8c316 530 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
46a3df9f 531 memcpy(p,
67b8c316 532 hns3_nic_test_strs[HNAE3_LOOP_APP],
46a3df9f
S		 533 ETH_GSTRING_LEN);
534 p += ETH_GSTRING_LEN;
535 }
86957272 536 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
46a3df9f 537 memcpy(p,
86957272
FL		 538 hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
539 ETH_GSTRING_LEN);
540 p += ETH_GSTRING_LEN;
541 }
542 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
543 memcpy(p,
544 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
46a3df9f
S		 545 ETH_GSTRING_LEN);
546 p += ETH_GSTRING_LEN;
547 }
548 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
549 memcpy(p,
e05cfaaf 550 hns3_nic_test_strs[HNAE3_LOOP_PHY],
46a3df9f
S		 551 ETH_GSTRING_LEN);
552 p += ETH_GSTRING_LEN;
553 }
554 }
555}
556
557static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
558{
559 struct hclge_vport *vport = hclge_get_vport(handle);
560 struct hclge_dev *hdev = vport->back;
561 u64 *p;
562
563 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
564 g_mac_stats_string,
565 ARRAY_SIZE(g_mac_stats_string),
566 data);
46a3df9f
S		 567 p = hclge_tqps_get_stats(handle, p);
568}
569
570static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 571 struct hclge_func_status_cmd *status)
46a3df9f
S		 572{
573 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
574 return -EINVAL;
575
576 /* Set the pf to main pf */
577 if (status->pf_state & HCLGE_PF_STATE_MAIN)
578 hdev->flag |= HCLGE_FLAG_MAIN;
579 else
580 hdev->flag &= ~HCLGE_FLAG_MAIN;
581
46a3df9f
S		 582 return 0;
583}
584
585static int hclge_query_function_status(struct hclge_dev *hdev)
586{
d44f9b63 587 struct hclge_func_status_cmd *req;
46a3df9f
S		 588 struct hclge_desc desc;
589 int timeout = 0;
590 int ret;
591
592 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 593 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 594
595 do {
596 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
597 if (ret) {
598 dev_err(&hdev->pdev->dev,
599 "query function status failed %d.\n",
600 ret);
601
602 return ret;
603 }
604
605 /* Check pf reset is done */
606 if (req->pf_state)
607 break;
608 usleep_range(1000, 2000);
609 } while (timeout++ < 5);
610
611 ret = hclge_parse_func_status(hdev, req);
612
613 return ret;
614}
615
616static int hclge_query_pf_resource(struct hclge_dev *hdev)
617{
d44f9b63 618 struct hclge_pf_res_cmd *req;
46a3df9f
S		 619 struct hclge_desc desc;
620 int ret;
621
622 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
623 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
624 if (ret) {
625 dev_err(&hdev->pdev->dev,
626 "query pf resource failed %d.\n", ret);
627 return ret;
628 }
629
d44f9b63 630 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 631 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
632 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
633
e92a0843 634 if (hnae3_dev_roce_supported(hdev)) {
5355e6d3
JS		 635 hdev->roce_base_msix_offset =
636 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
637 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
887c3820 638 hdev->num_roce_msi =
ccc23ef3
PL		 639 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
640 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 641
642 /* PF should have NIC vectors and Roce vectors,
643 * NIC vectors are queued before Roce vectors.
644 */
5355e6d3
JS		 645 hdev->num_msi = hdev->num_roce_msi +
646 hdev->roce_base_msix_offset;
46a3df9f
S		 647 } else {
648 hdev->num_msi =
ccc23ef3
PL		 649 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
650 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 651 }
652
653 return 0;
654}
655
656static int hclge_parse_speed(int speed_cmd, int *speed)
657{
658 switch (speed_cmd) {
659 case 6:
660 *speed = HCLGE_MAC_SPEED_10M;
661 break;
662 case 7:
663 *speed = HCLGE_MAC_SPEED_100M;
664 break;
665 case 0:
666 *speed = HCLGE_MAC_SPEED_1G;
667 break;
668 case 1:
669 *speed = HCLGE_MAC_SPEED_10G;
670 break;
671 case 2:
672 *speed = HCLGE_MAC_SPEED_25G;
673 break;
674 case 3:
675 *speed = HCLGE_MAC_SPEED_40G;
676 break;
677 case 4:
678 *speed = HCLGE_MAC_SPEED_50G;
679 break;
680 case 5:
681 *speed = HCLGE_MAC_SPEED_100G;
682 break;
683 default:
684 return -EINVAL;
685 }
686
687 return 0;
688}
689
d92ceae9
FL		 690static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
691 u8 speed_ability)
692{
693 unsigned long *supported = hdev->hw.mac.supported;
694
695 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
696 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
697 supported);
698
699 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
700 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
701 supported);
702
703 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
704 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
705 supported);
706
707 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
708 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
709 supported);
710
711 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
712 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
713 supported);
714
715 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
716 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
717}
718
719static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
720{
721 u8 media_type = hdev->hw.mac.media_type;
722
723 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
724 return;
725
726 hclge_parse_fiber_link_mode(hdev, speed_ability);
727}
728
46a3df9f
S		 729static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
730{
d44f9b63 731 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 732 u64 mac_addr_tmp_high;
733 u64 mac_addr_tmp;
734 int i;
735
d44f9b63 736 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 737
738 /* get the configuration */
ccc23ef3
PL		 739 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
740 HCLGE_CFG_VMDQ_M,
741 HCLGE_CFG_VMDQ_S);
742 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
743 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
744 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
745 HCLGE_CFG_TQP_DESC_N_M,
746 HCLGE_CFG_TQP_DESC_N_S);
747
748 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
749 HCLGE_CFG_PHY_ADDR_M,
750 HCLGE_CFG_PHY_ADDR_S);
751 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
752 HCLGE_CFG_MEDIA_TP_M,
753 HCLGE_CFG_MEDIA_TP_S);
754 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
755 HCLGE_CFG_RX_BUF_LEN_M,
756 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 757 /* get mac_address */
758 mac_addr_tmp = __le32_to_cpu(req->param[2]);
ccc23ef3
PL		 759 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
760 HCLGE_CFG_MAC_ADDR_H_M,
761 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 762
763 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
764
ccc23ef3
PL		 765 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
766 HCLGE_CFG_DEFAULT_SPEED_M,
767 HCLGE_CFG_DEFAULT_SPEED_S);
768 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
769 HCLGE_CFG_RSS_SIZE_M,
770 HCLGE_CFG_RSS_SIZE_S);
c408e202 771
46a3df9f
S		 772 for (i = 0; i < ETH_ALEN; i++)
773 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
774
d44f9b63 775 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 776 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
d92ceae9 777
ccc23ef3
PL		 778 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
779 HCLGE_CFG_SPEED_ABILITY_M,
780 HCLGE_CFG_SPEED_ABILITY_S);
2da5ec58
JS		 781 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
782 HCLGE_CFG_UMV_TBL_SPACE_M,
783 HCLGE_CFG_UMV_TBL_SPACE_S);
784 if (!cfg->umv_space)
785 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
46a3df9f
S		 786}
787
788/* hclge_get_cfg: query the static parameter from flash
789 * @hdev: pointer to struct hclge_dev
790 * @hcfg: the config structure to be getted
791 */
792static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
793{
794 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 795 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 796 int i, ret;
797
798 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 799 u32 offset = 0;
800
d44f9b63 801 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 802 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
803 true);
ccc23ef3
PL		 804 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
805 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 806 /* Len should be united by 4 bytes when send to hardware */
ccc23ef3
PL		 807 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
808 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 809 req->offset = cpu_to_le32(offset);
46a3df9f
S		 810 }
811
812 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
813 if (ret) {
90415e85 814 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
46a3df9f
S		 815 return ret;
816 }
817
818 hclge_parse_cfg(hcfg, desc);
90415e85 819
46a3df9f
S		 820 return 0;
821}
822
823static int hclge_get_cap(struct hclge_dev *hdev)
824{
825 int ret;
826
827 ret = hclge_query_function_status(hdev);
828 if (ret) {
829 dev_err(&hdev->pdev->dev,
830 "query function status error %d.\n", ret);
831 return ret;
832 }
833
834 /* get pf resource */
835 ret = hclge_query_pf_resource(hdev);
90415e85
JS		 836 if (ret)
837 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
46a3df9f 838
90415e85 839 return ret;
46a3df9f
S		 840}
841
842static int hclge_configure(struct hclge_dev *hdev)
843{
844 struct hclge_cfg cfg;
845 int ret, i;
846
847 ret = hclge_get_cfg(hdev, &cfg);
848 if (ret) {
849 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
850 return ret;
851 }
852
853 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
854 hdev->base_tqp_pid = 0;
c408e202 855 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 856 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 857 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 858 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 859 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 860 hdev->num_desc = cfg.tqp_desc_num;
861 hdev->tm_info.num_pg = 1;
cacde272 862 hdev->tc_max = cfg.tc_num;
46a3df9f 863 hdev->tm_info.hw_pfc_map = 0;
2da5ec58 864 hdev->wanted_umv_size = cfg.umv_space;
46a3df9f
S		 865
866 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
867 if (ret) {
868 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
869 return ret;
870 }
871
d92ceae9
FL		 872 hclge_parse_link_mode(hdev, cfg.speed_ability);
873
cacde272
YL		 874 if ((hdev->tc_max > HNAE3_MAX_TC) ||
875 (hdev->tc_max < 1)) {
46a3df9f 876 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 877 hdev->tc_max);
878 hdev->tc_max = 1;
46a3df9f
S		 879 }
880
cacde272
YL		 881 /* Dev does not support DCB */
882 if (!hnae3_dev_dcb_supported(hdev)) {
883 hdev->tc_max = 1;
884 hdev->pfc_max = 0;
885 } else {
886 hdev->pfc_max = hdev->tc_max;
887 }
888
889 hdev->tm_info.num_tc = hdev->tc_max;
890
46a3df9f 891 /* Currently not support uncontiuous tc */
cacde272 892 for (i = 0; i < hdev->tm_info.num_tc; i++)
ccc23ef3 893 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 894
f8362fe1 895 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 896
897 return ret;
898}
899
900static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
901 int tso_mss_max)
902{
d44f9b63 903 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 904 struct hclge_desc desc;
a90bb9a5 905 u16 tso_mss;
46a3df9f
S		 906
907 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
908
d44f9b63 909 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 910
911 tso_mss = 0;
ccc23ef3
PL		 912 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
913 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 914 req->tso_mss_min = cpu_to_le16(tso_mss);
915
916 tso_mss = 0;
ccc23ef3
PL		 917 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
918 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 919 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 920
921 return hclge_cmd_send(&hdev->hw, &desc, 1);
922}
923
73f88b00
PL		 924static int hclge_config_gro(struct hclge_dev *hdev, bool en)
925{
926 struct hclge_cfg_gro_status_cmd *req;
927 struct hclge_desc desc;
928 int ret;
929
930 if (!hnae3_dev_gro_supported(hdev))
931 return 0;
932
933 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
934 req = (struct hclge_cfg_gro_status_cmd *)desc.data;
935
936 req->gro_en = cpu_to_le16(en ? 1 : 0);
937
938 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
939 if (ret)
940 dev_err(&hdev->pdev->dev,
941 "GRO hardware config cmd failed, ret = %d\n", ret);
942
943 return ret;
944}
945
46a3df9f
S		 946static int hclge_alloc_tqps(struct hclge_dev *hdev)
947{
948 struct hclge_tqp *tqp;
949 int i;
950
951 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
952 sizeof(struct hclge_tqp), GFP_KERNEL);
953 if (!hdev->htqp)
954 return -ENOMEM;
955
956 tqp = hdev->htqp;
957
958 for (i = 0; i < hdev->num_tqps; i++) {
959 tqp->dev = &hdev->pdev->dev;
960 tqp->index = i;
961
962 tqp->q.ae_algo = &ae_algo;
963 tqp->q.buf_size = hdev->rx_buf_len;
964 tqp->q.desc_num = hdev->num_desc;
965 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
966 i * HCLGE_TQP_REG_SIZE;
967
968 tqp++;
969 }
970
971 return 0;
972}
973
974static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
975 u16 tqp_pid, u16 tqp_vid, bool is_pf)
976{
d44f9b63 977 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 978 struct hclge_desc desc;
979 int ret;
980
981 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
982
d44f9b63 983 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 984 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 985 req->tqp_vf = func_id;
46a3df9f
S		 986 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
987 1 << HCLGE_TQP_MAP_EN_B;
988 req->tqp_vid = cpu_to_le16(tqp_vid);
989
990 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85
JS		 991 if (ret)
992 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
46a3df9f 993
90415e85 994 return ret;
46a3df9f
S		 995}
996
81356b1f 997static int hclge_assign_tqp(struct hclge_vport *vport)
46a3df9f 998{
81356b1f 999 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
46a3df9f 1000 struct hclge_dev *hdev = vport->back;
7df7dad6 1001 int i, alloced;
46a3df9f
S		 1002
1003 for (i = 0, alloced = 0; i < hdev->num_tqps &&
81356b1f 1004 alloced < kinfo->num_tqps; i++) {
46a3df9f
S		 1005 if (!hdev->htqp[i].alloced) {
1006 hdev->htqp[i].q.handle = &vport->nic;
1007 hdev->htqp[i].q.tqp_index = alloced;
81356b1f
YL		 1008 hdev->htqp[i].q.desc_num = kinfo->num_desc;
1009 kinfo->tqp[alloced] = &hdev->htqp[i].q;
46a3df9f 1010 hdev->htqp[i].alloced = true;
46a3df9f
S		 1011 alloced++;
1012 }
1013 }
81356b1f 1014 vport->alloc_tqps = kinfo->num_tqps;
46a3df9f
S		 1015
1016 return 0;
1017}
1018
81356b1f
YL		 1019static int hclge_knic_setup(struct hclge_vport *vport,
1020 u16 num_tqps, u16 num_desc)
46a3df9f
S		 1021{
1022 struct hnae3_handle *nic = &vport->nic;
1023 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1024 struct hclge_dev *hdev = vport->back;
1025 int i, ret;
1026
81356b1f 1027 kinfo->num_desc = num_desc;
46a3df9f
S		 1028 kinfo->rx_buf_len = hdev->rx_buf_len;
1029 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1030 kinfo->rss_size
1031 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1032 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1033
1034 for (i = 0; i < HNAE3_MAX_TC; i++) {
1035 if (hdev->hw_tc_map & BIT(i)) {
1036 kinfo->tc_info[i].enable = true;
1037 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1038 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1039 kinfo->tc_info[i].tc = i;
1040 } else {
1041 /* Set to default queue if TC is disable */
1042 kinfo->tc_info[i].enable = false;
1043 kinfo->tc_info[i].tqp_offset = 0;
1044 kinfo->tc_info[i].tqp_count = 1;
1045 kinfo->tc_info[i].tc = 0;
1046 }
1047 }
1048
1049 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1050 sizeof(struct hnae3_queue *), GFP_KERNEL);
1051 if (!kinfo->tqp)
1052 return -ENOMEM;
1053
81356b1f 1054 ret = hclge_assign_tqp(vport);
90415e85 1055 if (ret)
46a3df9f 1056 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
46a3df9f 1057
90415e85 1058 return ret;
46a3df9f
S		 1059}
1060
7df7dad6
L		 1061static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1062 struct hclge_vport *vport)
1063{
1064 struct hnae3_handle *nic = &vport->nic;
1065 struct hnae3_knic_private_info *kinfo;
1066 u16 i;
1067
1068 kinfo = &nic->kinfo;
1069 for (i = 0; i < kinfo->num_tqps; i++) {
1070 struct hclge_tqp *q =
1071 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1072 bool is_pf;
1073 int ret;
1074
1075 is_pf = !(vport->vport_id);
1076 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1077 i, is_pf);
1078 if (ret)
1079 return ret;
1080 }
1081
1082 return 0;
1083}
1084
1085static int hclge_map_tqp(struct hclge_dev *hdev)
1086{
1087 struct hclge_vport *vport = hdev->vport;
1088 u16 i, num_vport;
1089
1090 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1091 for (i = 0; i < num_vport; i++) {
1092 int ret;
1093
1094 ret = hclge_map_tqp_to_vport(hdev, vport);
1095 if (ret)
1096 return ret;
1097
1098 vport++;
1099 }
1100
1101 return 0;
1102}
1103
46a3df9f
S		 1104static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1105{
1106 /* this would be initialized later */
1107}
1108
1109static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1110{
1111 struct hnae3_handle *nic = &vport->nic;
1112 struct hclge_dev *hdev = vport->back;
1113 int ret;
1114
1115 nic->pdev = hdev->pdev;
1116 nic->ae_algo = &ae_algo;
1117 nic->numa_node_mask = hdev->numa_node_mask;
1118
1119 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
81356b1f 1120 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
46a3df9f
S		 1121 if (ret) {
1122 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1123 ret);
1124 return ret;
1125 }
1126 } else {
1127 hclge_unic_setup(vport, num_tqps);
1128 }
1129
1130 return 0;
1131}
1132
1133static int hclge_alloc_vport(struct hclge_dev *hdev)
1134{
1135 struct pci_dev *pdev = hdev->pdev;
1136 struct hclge_vport *vport;
1137 u32 tqp_main_vport;
1138 u32 tqp_per_vport;
1139 int num_vport, i;
1140 int ret;
1141
1142 /* We need to alloc a vport for main NIC of PF */
1143 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1144
b76edfb2
HT		 1145 if (hdev->num_tqps < num_vport) {
1146 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1147 hdev->num_tqps, num_vport);
1148 return -EINVAL;
1149 }
46a3df9f
S		 1150
1151 /* Alloc the same number of TQPs for every vport */
1152 tqp_per_vport = hdev->num_tqps / num_vport;
1153 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1154
1155 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1156 GFP_KERNEL);
1157 if (!vport)
1158 return -ENOMEM;
1159
1160 hdev->vport = vport;
1161 hdev->num_alloc_vport = num_vport;
1162
bc59f827
FL		 1163 if (IS_ENABLED(CONFIG_PCI_IOV))
1164 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1165
1166 for (i = 0; i < num_vport; i++) {
1167 vport->back = hdev;
1168 vport->vport_id = i;
1169
1170 if (i == 0)
1171 ret = hclge_vport_setup(vport, tqp_main_vport);
1172 else
1173 ret = hclge_vport_setup(vport, tqp_per_vport);
1174 if (ret) {
1175 dev_err(&pdev->dev,
1176 "vport setup failed for vport %d, %d\n",
1177 i, ret);
1178 return ret;
1179 }
1180
1181 vport++;
1182 }
1183
1184 return 0;
1185}
1186
acf61ecd
YL		 1187static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1188 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1189{
1190/* TX buffer size is unit by 128 byte */
1191#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1192#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1193 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1194 struct hclge_desc desc;
1195 int ret;
1196 u8 i;
1197
d44f9b63 1198 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1199
1200 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1201 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1202 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1203
46a3df9f
S		 1204 req->tx_pkt_buff[i] =
1205 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1206 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1207 }
46a3df9f
S		 1208
1209 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 1210 if (ret)
46a3df9f
S		 1211 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1212 ret);
46a3df9f 1213
90415e85 1214 return ret;
46a3df9f
S		 1215}
1216
acf61ecd
YL		 1217static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1218 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1219{
acf61ecd 1220 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1221
90415e85
JS		 1222 if (ret)
1223 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
46a3df9f 1224
90415e85 1225 return ret;
46a3df9f
S		 1226}
1227
1228static int hclge_get_tc_num(struct hclge_dev *hdev)
1229{
1230 int i, cnt = 0;
1231
1232 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1233 if (hdev->hw_tc_map & BIT(i))
1234 cnt++;
1235 return cnt;
1236}
1237
1238static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1239{
1240 int i, cnt = 0;
1241
1242 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1243 if (hdev->hw_tc_map & BIT(i) &&
1244 hdev->tm_info.hw_pfc_map & BIT(i))
1245 cnt++;
1246 return cnt;
1247}
1248
1249/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1250static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1251 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1252{
1253 struct hclge_priv_buf *priv;
1254 int i, cnt = 0;
1255
1256 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1257 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1258 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1259 priv->enable)
1260 cnt++;
1261 }
1262
1263 return cnt;
1264}
1265
1266/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1267static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1268 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1269{
1270 struct hclge_priv_buf *priv;
1271 int i, cnt = 0;
1272
1273 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1274 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1275 if (hdev->hw_tc_map & BIT(i) &&
1276 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1277 priv->enable)
1278 cnt++;
1279 }
1280
1281 return cnt;
1282}
1283
acf61ecd 1284static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1285{
1286 struct hclge_priv_buf *priv;
1287 u32 rx_priv = 0;
1288 int i;
1289
1290 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1291 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1292 if (priv->enable)
1293 rx_priv += priv->buf_size;
1294 }
1295 return rx_priv;
1296}
1297
acf61ecd 1298static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1299{
1300 u32 i, total_tx_size = 0;
1301
1302 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1303 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1304
1305 return total_tx_size;
1306}
1307
acf61ecd
YL		 1308static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1309 struct hclge_pkt_buf_alloc *buf_alloc,
1310 u32 rx_all)
46a3df9f
S		 1311{
1312 u32 shared_buf_min, shared_buf_tc, shared_std;
1313 int tc_num, pfc_enable_num;
1314 u32 shared_buf;
1315 u32 rx_priv;
1316 int i;
1317
1318 tc_num = hclge_get_tc_num(hdev);
1319 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1320
d221df4e
YL		 1321 if (hnae3_dev_dcb_supported(hdev))
1322 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1323 else
1324 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1325
46a3df9f
S		 1326 shared_buf_tc = pfc_enable_num * hdev->mps +
1327 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1328 hdev->mps;
1329 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1330
acf61ecd 1331 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1332 if (rx_all <= rx_priv + shared_std)
1333 return false;
1334
1335 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1336 buf_alloc->s_buf.buf_size = shared_buf;
1337 buf_alloc->s_buf.self.high = shared_buf;
1338 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1339
1340 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1341 if ((hdev->hw_tc_map & BIT(i)) &&
1342 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1343 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1344 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1345 } else {
acf61ecd
YL		 1346 buf_alloc->s_buf.tc_thrd[i].low = 0;
1347 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1348 }
1349 }
1350
1351 return true;
1352}
1353
acf61ecd
YL		 1354static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1355 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1356{
1357 u32 i, total_size;
1358
1359 total_size = hdev->pkt_buf_size;
1360
1361 /* alloc tx buffer for all enabled tc */
1362 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1363 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1364
1365 if (total_size < HCLGE_DEFAULT_TX_BUF)
1366 return -ENOMEM;
1367
1368 if (hdev->hw_tc_map & BIT(i))
1369 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1370 else
1371 priv->tx_buf_size = 0;
1372
1373 total_size -= priv->tx_buf_size;
1374 }
1375
1376 return 0;
1377}
1378
46a3df9f
S		 1379/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1380 * @hdev: pointer to struct hclge_dev
acf61ecd 1381 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1382 * @return: 0: calculate sucessful, negative: fail
1383 */
1db9b1bf
YL		 1384static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1385 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1386{
d748274d
YL		 1387#define HCLGE_BUF_SIZE_UNIT 128
1388 u32 rx_all = hdev->pkt_buf_size, aligned_mps;
46a3df9f
S		 1389 int no_pfc_priv_num, pfc_priv_num;
1390 struct hclge_priv_buf *priv;
1391 int i;
1392
d748274d 1393 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
acf61ecd 1394 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1395
d602a525
YL		 1396 /* When DCB is not supported, rx private
1397 * buffer is not allocated.
1398 */
1399 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1400 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1401 return -ENOMEM;
1402
1403 return 0;
1404 }
1405
46a3df9f
S		 1406 /* step 1, try to alloc private buffer for all enabled tc */
1407 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1408 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1409 if (hdev->hw_tc_map & BIT(i)) {
1410 priv->enable = 1;
1411 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
d748274d
YL		 1412 priv->wl.low = aligned_mps;
1413 priv->wl.high = priv->wl.low + aligned_mps;
46a3df9f
S		 1414 priv->buf_size = priv->wl.high +
1415 HCLGE_DEFAULT_DV;
1416 } else {
1417 priv->wl.low = 0;
d748274d 1418 priv->wl.high = 2 * aligned_mps;
46a3df9f
S		 1419 priv->buf_size = priv->wl.high;
1420 }
bb1fe9ea
YL		 1421 } else {
1422 priv->enable = 0;
1423 priv->wl.low = 0;
1424 priv->wl.high = 0;
1425 priv->buf_size = 0;
46a3df9f
S		 1426 }
1427 }
1428
acf61ecd 1429 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1430 return 0;
1431
1432 /* step 2, try to decrease the buffer size of
1433 * no pfc TC's private buffer
1434 */
1435 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1436 priv = &buf_alloc->priv_buf[i];
46a3df9f 1437
bb1fe9ea
YL		 1438 priv->enable = 0;
1439 priv->wl.low = 0;
1440 priv->wl.high = 0;
1441 priv->buf_size = 0;
1442
1443 if (!(hdev->hw_tc_map & BIT(i)))
1444 continue;
1445
1446 priv->enable = 1;
46a3df9f
S		 1447
1448 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1449 priv->wl.low = 128;
d748274d 1450 priv->wl.high = priv->wl.low + aligned_mps;
46a3df9f
S		 1451 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1452 } else {
1453 priv->wl.low = 0;
d748274d 1454 priv->wl.high = aligned_mps;
46a3df9f
S		 1455 priv->buf_size = priv->wl.high;
1456 }
1457 }
1458
acf61ecd 1459 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1460 return 0;
1461
1462 /* step 3, try to reduce the number of pfc disabled TCs,
1463 * which have private buffer
1464 */
1465 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1466 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1467
1468 /* let the last to be cleared first */
1469 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1470 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1471
1472 if (hdev->hw_tc_map & BIT(i) &&
1473 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1474 /* Clear the no pfc TC private buffer */
1475 priv->wl.low = 0;
1476 priv->wl.high = 0;
1477 priv->buf_size = 0;
1478 priv->enable = 0;
1479 no_pfc_priv_num--;
1480 }
1481
acf61ecd 1482 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1483 no_pfc_priv_num == 0)
1484 break;
1485 }
1486
acf61ecd 1487 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1488 return 0;
1489
1490 /* step 4, try to reduce the number of pfc enabled TCs
1491 * which have private buffer.
1492 */
acf61ecd 1493 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1494
1495 /* let the last to be cleared first */
1496 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1497 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1498
1499 if (hdev->hw_tc_map & BIT(i) &&
1500 hdev->tm_info.hw_pfc_map & BIT(i)) {
1501 /* Reduce the number of pfc TC with private buffer */
1502 priv->wl.low = 0;
1503 priv->enable = 0;
1504 priv->wl.high = 0;
1505 priv->buf_size = 0;
1506 pfc_priv_num--;
1507 }
1508
acf61ecd 1509 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1510 pfc_priv_num == 0)
1511 break;
1512 }
acf61ecd 1513 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1514 return 0;
1515
1516 return -ENOMEM;
1517}
1518
acf61ecd
YL		 1519static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1520 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1521{
d44f9b63 1522 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1523 struct hclge_desc desc;
1524 int ret;
1525 int i;
1526
1527 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1528 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1529
1530 /* Alloc private buffer TCs */
1531 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1532 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1533
1534 req->buf_num[i] =
1535 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1536 req->buf_num[i] |=
5bca3b94 1537 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1538 }
1539
b8c8bf47 1540 req->shared_buf =
acf61ecd 1541 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1542 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1543
46a3df9f 1544 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 1545 if (ret)
46a3df9f
S		 1546 dev_err(&hdev->pdev->dev,
1547 "rx private buffer alloc cmd failed %d\n", ret);
46a3df9f 1548
90415e85 1549 return ret;
46a3df9f
S		 1550}
1551
acf61ecd
YL		 1552static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1553 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1554{
1555 struct hclge_rx_priv_wl_buf *req;
1556 struct hclge_priv_buf *priv;
1557 struct hclge_desc desc[2];
1558 int i, j;
1559 int ret;
1560
1561 for (i = 0; i < 2; i++) {
1562 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1563 false);
1564 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1565
1566 /* The first descriptor set the NEXT bit to 1 */
1567 if (i == 0)
1568 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1569 else
1570 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1571
1572 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1573 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1574
1575 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1576 req->tc_wl[j].high =
1577 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1578 req->tc_wl[j].high |=
ee6b549b 1579 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1580 req->tc_wl[j].low =
1581 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1582 req->tc_wl[j].low |=
ee6b549b 1583 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1584 }
1585 }
1586
1587 /* Send 2 descriptor at one time */
1588 ret = hclge_cmd_send(&hdev->hw, desc, 2);
90415e85 1589 if (ret)
46a3df9f
S		 1590 dev_err(&hdev->pdev->dev,
1591 "rx private waterline config cmd failed %d\n",
1592 ret);
90415e85 1593 return ret;
46a3df9f
S		 1594}
1595
acf61ecd
YL		 1596static int hclge_common_thrd_config(struct hclge_dev *hdev,
1597 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1598{
acf61ecd 1599 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1600 struct hclge_rx_com_thrd *req;
1601 struct hclge_desc desc[2];
1602 struct hclge_tc_thrd *tc;
1603 int i, j;
1604 int ret;
1605
1606 for (i = 0; i < 2; i++) {
1607 hclge_cmd_setup_basic_desc(&desc[i],
1608 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1609 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1610
1611 /* The first descriptor set the NEXT bit to 1 */
1612 if (i == 0)
1613 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1614 else
1615 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1616
1617 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1618 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1619
1620 req->com_thrd[j].high =
1621 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1622 req->com_thrd[j].high |=
ee6b549b 1623 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1624 req->com_thrd[j].low =
1625 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1626 req->com_thrd[j].low |=
ee6b549b 1627 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1628 }
1629 }
1630
1631 /* Send 2 descriptors at one time */
1632 ret = hclge_cmd_send(&hdev->hw, desc, 2);
90415e85 1633 if (ret)
46a3df9f
S		 1634 dev_err(&hdev->pdev->dev,
1635 "common threshold config cmd failed %d\n", ret);
90415e85 1636 return ret;
46a3df9f
S		 1637}
1638
acf61ecd
YL		 1639static int hclge_common_wl_config(struct hclge_dev *hdev,
1640 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1641{
acf61ecd 1642 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1643 struct hclge_rx_com_wl *req;
1644 struct hclge_desc desc;
1645 int ret;
1646
1647 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1648
1649 req = (struct hclge_rx_com_wl *)desc.data;
1650 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
ee6b549b 1651 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1652
1653 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
ee6b549b 1654 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1655
1656 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 1657 if (ret)
46a3df9f
S		 1658 dev_err(&hdev->pdev->dev,
1659 "common waterline config cmd failed %d\n", ret);
930ff2f6 1660
90415e85 1661 return ret;
46a3df9f
S		 1662}
1663
1664int hclge_buffer_alloc(struct hclge_dev *hdev)
1665{
acf61ecd 1666 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1667 int ret;
1668
acf61ecd
YL		 1669 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1670 if (!pkt_buf)
46a3df9f
S		 1671 return -ENOMEM;
1672
acf61ecd 1673 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1674 if (ret) {
1675 dev_err(&hdev->pdev->dev,
1676 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1677 goto out;
9ffe79a9
YL		 1678 }
1679
acf61ecd 1680 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1681 if (ret) {
1682 dev_err(&hdev->pdev->dev,
1683 "could not alloc tx buffers %d\n", ret);
acf61ecd 1684 goto out;
46a3df9f
S		 1685 }
1686
acf61ecd 1687 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1688 if (ret) {
1689 dev_err(&hdev->pdev->dev,
1690 "could not calc rx priv buffer size for all TCs %d\n",
1691 ret);
acf61ecd 1692 goto out;
46a3df9f
S		 1693 }
1694
acf61ecd 1695 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1696 if (ret) {
1697 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1698 ret);
acf61ecd 1699 goto out;
46a3df9f
S		 1700 }
1701
2daf4a65 1702 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1703 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1704 if (ret) {
1705 dev_err(&hdev->pdev->dev,
1706 "could not configure rx private waterline %d\n",
1707 ret);
acf61ecd 1708 goto out;
2daf4a65 1709 }
46a3df9f 1710
acf61ecd 1711 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1712 if (ret) {
1713 dev_err(&hdev->pdev->dev,
1714 "could not configure common threshold %d\n",
1715 ret);
acf61ecd 1716 goto out;
2daf4a65 1717 }
46a3df9f
S		 1718 }
1719
acf61ecd
YL		 1720 ret = hclge_common_wl_config(hdev, pkt_buf);
1721 if (ret)
46a3df9f
S		 1722 dev_err(&hdev->pdev->dev,
1723 "could not configure common waterline %d\n", ret);
46a3df9f 1724
acf61ecd
YL		 1725out:
1726 kfree(pkt_buf);
1727 return ret;
46a3df9f
S		 1728}
1729
1730static int hclge_init_roce_base_info(struct hclge_vport *vport)
1731{
1732 struct hnae3_handle *roce = &vport->roce;
1733 struct hnae3_handle *nic = &vport->nic;
1734
887c3820 1735 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1736
1737 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1738 vport->back->num_msi_left == 0)
1739 return -EINVAL;
1740
1741 roce->rinfo.base_vector = vport->back->roce_base_vector;
1742
1743 roce->rinfo.netdev = nic->kinfo.netdev;
1744 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1745
1746 roce->pdev = nic->pdev;
1747 roce->ae_algo = nic->ae_algo;
1748 roce->numa_node_mask = nic->numa_node_mask;
1749
1750 return 0;
1751}
1752
887c3820 1753static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1754{
1755 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1756 int vectors;
1757 int i;
46a3df9f 1758
887c3820
SM		 1759 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1760 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1761 if (vectors < 0) {
1762 dev_err(&pdev->dev,
1763 "failed(%d) to allocate MSI/MSI-X vectors\n",
1764 vectors);
1765 return vectors;
46a3df9f 1766 }
887c3820
SM		 1767 if (vectors < hdev->num_msi)
1768 dev_warn(&hdev->pdev->dev,
1769 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1770 hdev->num_msi, vectors);
46a3df9f 1771
887c3820
SM		 1772 hdev->num_msi = vectors;
1773 hdev->num_msi_left = vectors;
1774 hdev->base_msi_vector = pdev->irq;
46a3df9f 1775 hdev->roce_base_vector = hdev->base_msi_vector +
5355e6d3 1776 hdev->roce_base_msix_offset;
46a3df9f 1777
46a3df9f
S		 1778 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1779 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1780 if (!hdev->vector_status) {
1781 pci_free_irq_vectors(pdev);
46a3df9f 1782 return -ENOMEM;
887c3820 1783 }
46a3df9f
S		 1784
1785 for (i = 0; i < hdev->num_msi; i++)
1786 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1787
887c3820
SM		 1788 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1789 sizeof(int), GFP_KERNEL);
1790 if (!hdev->vector_irq) {
1791 pci_free_irq_vectors(pdev);
1792 return -ENOMEM;
46a3df9f 1793 }
46a3df9f
S		 1794
1795 return 0;
1796}
1797
1c780066 1798static u8 hclge_check_speed_dup(u8 duplex, int speed)
46a3df9f 1799{
46a3df9f 1800
1c780066
YL		 1801 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1802 duplex = HCLGE_MAC_FULL;
46a3df9f 1803
1c780066 1804 return duplex;
46a3df9f
S		 1805}
1806
1c780066
YL		 1807static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1808 u8 duplex)
46a3df9f 1809{
d44f9b63 1810 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 1811 struct hclge_desc desc;
1812 int ret;
1813
d44f9b63 1814 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 1815
1816 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1817
ccc23ef3 1818 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 1819
1820 switch (speed) {
1821 case HCLGE_MAC_SPEED_10M:
ccc23ef3
PL		 1822 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1823 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 1824 break;
1825 case HCLGE_MAC_SPEED_100M:
ccc23ef3
PL		 1826 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1827 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 1828 break;
1829 case HCLGE_MAC_SPEED_1G:
ccc23ef3
PL		 1830 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1831 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 1832 break;
1833 case HCLGE_MAC_SPEED_10G:
ccc23ef3
PL		 1834 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1835 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 1836 break;
1837 case HCLGE_MAC_SPEED_25G:
ccc23ef3
PL		 1838 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1839 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 1840 break;
1841 case HCLGE_MAC_SPEED_40G:
ccc23ef3
PL		 1842 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1843 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 1844 break;
1845 case HCLGE_MAC_SPEED_50G:
ccc23ef3
PL		 1846 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1847 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 1848 break;
1849 case HCLGE_MAC_SPEED_100G:
ccc23ef3
PL		 1850 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1851 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 1852 break;
1853 default:
d7629e74 1854 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 1855 return -EINVAL;
1856 }
1857
ccc23ef3
PL		 1858 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1859 1);
46a3df9f
S		 1860
1861 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1862 if (ret) {
1863 dev_err(&hdev->pdev->dev,
1864 "mac speed/duplex config cmd failed %d.\n", ret);
1865 return ret;
1866 }
1867
1c780066
YL		 1868 return 0;
1869}
1870
1871int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1872{
1873 int ret;
1874
1875 duplex = hclge_check_speed_dup(duplex, speed);
1876 if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1877 return 0;
1878
1879 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1880 if (ret)
1881 return ret;
1882
1883 hdev->hw.mac.speed = speed;
1884 hdev->hw.mac.duplex = duplex;
46a3df9f
S		 1885
1886 return 0;
1887}
1888
1889static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1890 u8 duplex)
1891{
1892 struct hclge_vport *vport = hclge_get_vport(handle);
1893 struct hclge_dev *hdev = vport->back;
1894
1895 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1896}
1897
1898static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1899 u8 *duplex)
1900{
d44f9b63 1901 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 1902 struct hclge_desc desc;
1903 int speed_tmp;
1904 int ret;
1905
d44f9b63 1906 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 1907
1908 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1909 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1910 if (ret) {
1911 dev_err(&hdev->pdev->dev,
1912 "mac speed/autoneg/duplex query cmd failed %d\n",
1913 ret);
1914 return ret;
1915 }
1916
ccc23ef3
PL		 1917 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
1918 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
1919 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 1920
1921 ret = hclge_parse_speed(speed_tmp, speed);
90415e85 1922 if (ret)
46a3df9f
S		 1923 dev_err(&hdev->pdev->dev,
1924 "could not parse speed(=%d), %d\n", speed_tmp, ret);
46a3df9f 1925
90415e85 1926 return ret;
46a3df9f
S		 1927}
1928
46a3df9f
S		 1929static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1930{
d44f9b63 1931 struct hclge_config_auto_neg_cmd *req;
46a3df9f 1932 struct hclge_desc desc;
a90bb9a5 1933 u32 flag = 0;
46a3df9f
S		 1934 int ret;
1935
1936 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1937
d44f9b63 1938 req = (struct hclge_config_auto_neg_cmd *)desc.data;
ccc23ef3 1939 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 1940 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 1941
1942 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 1943 if (ret)
46a3df9f
S		 1944 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
1945 ret);
46a3df9f 1946
90415e85 1947 return ret;
46a3df9f
S		 1948}
1949
1950static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
1951{
1952 struct hclge_vport *vport = hclge_get_vport(handle);
1953 struct hclge_dev *hdev = vport->back;
1954
1955 return hclge_set_autoneg_en(hdev, enable);
1956}
1957
1958static int hclge_get_autoneg(struct hnae3_handle *handle)
1959{
1960 struct hclge_vport *vport = hclge_get_vport(handle);
1961 struct hclge_dev *hdev = vport->back;
9ff804ee
FL		 1962 struct phy_device *phydev = hdev->hw.mac.phydev;
1963
1964 if (phydev)
1965 return phydev->autoneg;
46a3df9f
S		 1966
1967 return hdev->hw.mac.autoneg;
1968}
1969
1970static int hclge_mac_init(struct hclge_dev *hdev)
1971{
59bc85ec
FL		 1972 struct hnae3_handle *handle = &hdev->vport[0].nic;
1973 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 1974 struct hclge_mac *mac = &hdev->hw.mac;
59bc85ec 1975 int mtu;
46a3df9f
S		 1976 int ret;
1977
1c780066
YL		 1978 hdev->hw.mac.duplex = HCLGE_MAC_FULL;
1979 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
1980 hdev->hw.mac.duplex);
46a3df9f
S		 1981 if (ret) {
1982 dev_err(&hdev->pdev->dev,
1983 "Config mac speed dup fail ret=%d\n", ret);
1984 return ret;
1985 }
1986
1987 mac->link = 0;
1988
59bc85ec
FL		 1989 if (netdev)
1990 mtu = netdev->mtu;
1991 else
1992 mtu = ETH_DATA_LEN;
1993
1994 ret = hclge_set_mtu(handle, mtu);
90415e85 1995 if (ret)
59bc85ec
FL		 1996 dev_err(&hdev->pdev->dev,
1997 "set mtu failed ret=%d\n", ret);
59bc85ec 1998
90415e85 1999 return ret;
46a3df9f
S		 2000}
2001
22fd3468
SM		 2002static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2003{
2004 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2005 schedule_work(&hdev->mbx_service_task);
2006}
2007
ed4a1bb8
SM		 2008static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2009{
2010 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2011 schedule_work(&hdev->rst_service_task);
2012}
2013
46a3df9f
S		 2014static void hclge_task_schedule(struct hclge_dev *hdev)
2015{
2016 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2017 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2018 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2019 (void)schedule_work(&hdev->service_task);
2020}
2021
2022static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2023{
d44f9b63 2024 struct hclge_link_status_cmd *req;
46a3df9f
S		 2025 struct hclge_desc desc;
2026 int link_status;
2027 int ret;
2028
2029 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2030 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2031 if (ret) {
2032 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2033 ret);
2034 return ret;
2035 }
2036
d44f9b63 2037 req = (struct hclge_link_status_cmd *)desc.data;
e23e21ea 2038 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
46a3df9f
S		 2039
2040 return !!link_status;
2041}
2042
2043static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2044{
2045 int mac_state;
2046 int link_stat;
2047
ed6acb33
PL		 2048 if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2049 return 0;
2050
46a3df9f
S		 2051 mac_state = hclge_get_mac_link_status(hdev);
2052
2053 if (hdev->hw.mac.phydev) {
7ce8e698 2054 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
46a3df9f
S		 2055 link_stat = mac_state &
2056 hdev->hw.mac.phydev->link;
2057 else
2058 link_stat = 0;
2059
2060 } else {
2061 link_stat = mac_state;
2062 }
2063
2064 return !!link_stat;
2065}
2066
2067static void hclge_update_link_status(struct hclge_dev *hdev)
2068{
2069 struct hnae3_client *client = hdev->nic_client;
2070 struct hnae3_handle *handle;
2071 int state;
2072 int i;
2073
2074 if (!client)
2075 return;
2076 state = hclge_get_mac_phy_link(hdev);
2077 if (state != hdev->hw.mac.link) {
2078 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2079 handle = &hdev->vport[i].nic;
2080 client->ops->link_status_change(handle, state);
2081 }
2082 hdev->hw.mac.link = state;
2083 }
2084}
2085
2086static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2087{
2088 struct hclge_mac mac = hdev->hw.mac;
2089 u8 duplex;
2090 int speed;
2091 int ret;
2092
2093 /* get the speed and duplex as autoneg'result from mac cmd when phy
2094 * doesn't exit.
2095 */
c040366b 2096 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2097 return 0;
2098
2099 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2100 if (ret) {
2101 dev_err(&hdev->pdev->dev,
2102 "mac autoneg/speed/duplex query failed %d\n", ret);
2103 return ret;
2104 }
2105
1c780066
YL		 2106 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2107 if (ret) {
2108 dev_err(&hdev->pdev->dev,
2109 "mac speed/duplex config failed %d\n", ret);
2110 return ret;
46a3df9f
S		 2111 }
2112
2113 return 0;
2114}
2115
2116static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2117{
2118 struct hclge_vport *vport = hclge_get_vport(handle);
2119 struct hclge_dev *hdev = vport->back;
2120
2121 return hclge_update_speed_duplex(hdev);
2122}
2123
2124static int hclge_get_status(struct hnae3_handle *handle)
2125{
2126 struct hclge_vport *vport = hclge_get_vport(handle);
2127 struct hclge_dev *hdev = vport->back;
2128
2129 hclge_update_link_status(hdev);
2130
2131 return hdev->hw.mac.link;
2132}
2133
d039ef68 2134static void hclge_service_timer(struct timer_list *t)
46a3df9f 2135{
d039ef68 2136 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2137
d039ef68 2138 mod_timer(&hdev->service_timer, jiffies + HZ);
7a5d2a39 2139 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2140 hclge_task_schedule(hdev);
2141}
2142
2143static void hclge_service_complete(struct hclge_dev *hdev)
2144{
2145 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2146
2147 /* Flush memory before next watchdog */
2148 smp_mb__before_atomic();
2149 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2150}
2151
202f2014
SM		 2152static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2153{
2154 u32 rst_src_reg;
22fd3468 2155 u32 cmdq_src_reg;
202f2014
SM		 2156
2157 /* fetch the events from their corresponding regs */
0bcc9ba1 2158 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
22fd3468
SM		 2159 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2160
2161 /* Assumption: If by any chance reset and mailbox events are reported
2162 * together then we will only process reset event in this go and will
2163 * defer the processing of the mailbox events. Since, we would have not
2164 * cleared RX CMDQ event this time we would receive again another
2165 * interrupt from H/W just for the mailbox.
2166 */
202f2014
SM		 2167
2168 /* check for vector0 reset event sources */
de2eae69
HT		 2169 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2170 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
2171 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2172 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2173 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2174 return HCLGE_VECTOR0_EVENT_RST;
2175 }
2176
202f2014 2177 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
1afdb53a 2178 dev_info(&hdev->pdev->dev, "global reset interrupt\n");
7edef4ce 2179 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
202f2014
SM		 2180 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2181 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2182 return HCLGE_VECTOR0_EVENT_RST;
2183 }
2184
2185 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
1afdb53a 2186 dev_info(&hdev->pdev->dev, "core reset interrupt\n");
7edef4ce 2187 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
202f2014
SM		 2188 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2189 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2190 return HCLGE_VECTOR0_EVENT_RST;
2191 }
2192
22fd3468
SM		 2193 /* check for vector0 mailbox(=CMDQ RX) event source */
2194 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2195 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2196 *clearval = cmdq_src_reg;
2197 return HCLGE_VECTOR0_EVENT_MBX;
2198 }
202f2014
SM		 2199
2200 return HCLGE_VECTOR0_EVENT_OTHER;
2201}
2202
2203static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2204 u32 regclr)
2205{
22fd3468
SM		 2206 switch (event_type) {
2207 case HCLGE_VECTOR0_EVENT_RST:
202f2014 2208 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
22fd3468
SM		 2209 break;
2210 case HCLGE_VECTOR0_EVENT_MBX:
2211 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2212 break;
085920ba
JS		 2213 default:
2214 break;
22fd3468 2215 }
202f2014
SM		 2216}
2217
9ab4ad14
XW		 2218static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2219{
2220 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2221 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2222 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2223 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2224 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2225}
2226
466b0c00
L		 2227static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2228{
2229 writel(enable ? 1 : 0, vector->addr);
2230}
2231
2232static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2233{
2234 struct hclge_dev *hdev = data;
202f2014
SM		 2235 u32 event_cause;
2236 u32 clearval;
466b0c00
L		 2237
2238 hclge_enable_vector(&hdev->misc_vector, false);
202f2014
SM		 2239 event_cause = hclge_check_event_cause(hdev, &clearval);
2240
22fd3468 2241 /* vector 0 interrupt is shared with reset and mailbox source events.*/
202f2014
SM		 2242 switch (event_cause) {
2243 case HCLGE_VECTOR0_EVENT_RST:
ed4a1bb8 2244 hclge_reset_task_schedule(hdev);
202f2014 2245 break;
22fd3468
SM		 2246 case HCLGE_VECTOR0_EVENT_MBX:
2247 /* If we are here then,
2248 * 1. Either we are not handling any mbx task and we are not
2249 * scheduled as well
2250 * OR
2251 * 2. We could be handling a mbx task but nothing more is
2252 * scheduled.
2253 * In both cases, we should schedule mbx task as there are more
2254 * mbx messages reported by this interrupt.
2255 */
2256 hclge_mbx_task_schedule(hdev);
40ee4b71 2257 break;
202f2014 2258 default:
40ee4b71
YL		 2259 dev_warn(&hdev->pdev->dev,
2260 "received unknown or unhandled event of vector0\n");
202f2014
SM		 2261 break;
2262 }
2263
e9a50d09 2264 /* clear the source of interrupt if it is not cause by reset */
c9fc48dc 2265 if (event_cause == HCLGE_VECTOR0_EVENT_MBX) {
e9a50d09
YL		 2266 hclge_clear_event_cause(hdev, event_cause, clearval);
2267 hclge_enable_vector(&hdev->misc_vector, true);
2268 }
466b0c00
L		 2269
2270 return IRQ_HANDLED;
2271}
2272
2273static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2274{
1dc5378f
PL		 2275 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2276 dev_warn(&hdev->pdev->dev,
2277 "vector(vector_id %d) has been freed.\n", vector_id);
2278 return;
2279 }
2280
466b0c00
L		 2281 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2282 hdev->num_msi_left += 1;
2283 hdev->num_msi_used -= 1;
2284}
2285
2286static void hclge_get_misc_vector(struct hclge_dev *hdev)
2287{
2288 struct hclge_misc_vector *vector = &hdev->misc_vector;
2289
2290 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2291
2292 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2293 hdev->vector_status[0] = 0;
2294
2295 hdev->num_msi_left -= 1;
2296 hdev->num_msi_used += 1;
2297}
2298
2299static int hclge_misc_irq_init(struct hclge_dev *hdev)
2300{
2301 int ret;
2302
2303 hclge_get_misc_vector(hdev);
2304
202f2014
SM		 2305 /* this would be explicitly freed in the end */
2306 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2307 0, "hclge_misc", hdev);
466b0c00
L		 2308 if (ret) {
2309 hclge_free_vector(hdev, 0);
2310 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2311 hdev->misc_vector.vector_irq);
2312 }
2313
2314 return ret;
2315}
2316
202f2014
SM		 2317static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2318{
2319 free_irq(hdev->misc_vector.vector_irq, hdev);
2320 hclge_free_vector(hdev, 0);
2321}
2322
4ed340ab
L		 2323static int hclge_notify_client(struct hclge_dev *hdev,
2324 enum hnae3_reset_notify_type type)
2325{
2326 struct hnae3_client *client = hdev->nic_client;
2327 u16 i;
2328
2329 if (!client->ops->reset_notify)
2330 return -EOPNOTSUPP;
2331
2332 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
ad7c82fe 2333 struct hnae3_handle *handle = &hdev->vport[i].nic;
2334 int ret;
b38db544 2335
4ed340ab 2336 ret = client->ops->reset_notify(handle, type);
1afdb53a
HT		 2337 if (ret) {
2338 dev_err(&hdev->pdev->dev,
2339 "notify nic client failed %d(%d)\n", type, ret);
4ed340ab 2340 return ret;
1afdb53a 2341 }
4ed340ab
L		 2342 }
2343
6060dc84 2344 return 0;
4ed340ab
L		 2345}
2346
3db6b633
HT		 2347static int hclge_notify_roce_client(struct hclge_dev *hdev,
2348 enum hnae3_reset_notify_type type)
2349{
2350 struct hnae3_client *client = hdev->roce_client;
2351 int ret = 0;
2352 u16 i;
2353
2354 if (!client)
2355 return 0;
2356
2357 if (!client->ops->reset_notify)
2358 return -EOPNOTSUPP;
2359
2360 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2361 struct hnae3_handle *handle = &hdev->vport[i].roce;
2362
2363 ret = client->ops->reset_notify(handle, type);
2364 if (ret) {
2365 dev_err(&hdev->pdev->dev,
2366 "notify roce client failed %d(%d)",
2367 type, ret);
2368 return ret;
2369 }
2370 }
2371
2372 return ret;
2373}
2374
4ed340ab
L		 2375static int hclge_reset_wait(struct hclge_dev *hdev)
2376{
2377#define HCLGE_RESET_WATI_MS 100
de2eae69 2378#define HCLGE_RESET_WAIT_CNT 200
4ed340ab
L		 2379 u32 val, reg, reg_bit;
2380 u32 cnt = 0;
2381
2382 switch (hdev->reset_type) {
de2eae69
HT		 2383 case HNAE3_IMP_RESET:
2384 reg = HCLGE_GLOBAL_RESET_REG;
2385 reg_bit = HCLGE_IMP_RESET_BIT;
2386 break;
4ed340ab
L		 2387 case HNAE3_GLOBAL_RESET:
2388 reg = HCLGE_GLOBAL_RESET_REG;
2389 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2390 break;
2391 case HNAE3_CORE_RESET:
2392 reg = HCLGE_GLOBAL_RESET_REG;
2393 reg_bit = HCLGE_CORE_RESET_BIT;
2394 break;
2395 case HNAE3_FUNC_RESET:
2396 reg = HCLGE_FUN_RST_ING;
2397 reg_bit = HCLGE_FUN_RST_ING_B;
2398 break;
26977990
HT		 2399 case HNAE3_FLR_RESET:
2400 break;
4ed340ab
L		 2401 default:
2402 dev_err(&hdev->pdev->dev,
2403 "Wait for unsupported reset type: %d\n",
2404 hdev->reset_type);
2405 return -EINVAL;
2406 }
2407
26977990
HT		 2408 if (hdev->reset_type == HNAE3_FLR_RESET) {
2409 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) &&
2410 cnt++ < HCLGE_RESET_WAIT_CNT)
2411 msleep(HCLGE_RESET_WATI_MS);
2412
2413 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) {
2414 dev_err(&hdev->pdev->dev,
2415 "flr wait timeout: %d\n", cnt);
2416 return -EBUSY;
2417 }
2418
2419 return 0;
2420 }
2421
4ed340ab 2422 val = hclge_read_dev(&hdev->hw, reg);
ccc23ef3 2423 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
4ed340ab
L		 2424 msleep(HCLGE_RESET_WATI_MS);
2425 val = hclge_read_dev(&hdev->hw, reg);
2426 cnt++;
2427 }
2428
4ed340ab
L		 2429 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2430 dev_warn(&hdev->pdev->dev,
2431 "Wait for reset timeout: %d\n", hdev->reset_type);
2432 return -EBUSY;
2433 }
2434
2435 return 0;
2436}
2437
7885e906
HT		 2438static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
2439{
2440 struct hclge_vf_rst_cmd *req;
2441 struct hclge_desc desc;
2442
2443 req = (struct hclge_vf_rst_cmd *)desc.data;
2444 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
2445 req->dest_vfid = func_id;
2446
2447 if (reset)
2448 req->vf_rst = 0x1;
2449
2450 return hclge_cmd_send(&hdev->hw, &desc, 1);
2451}
2452
2453int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
2454{
2455 int i;
2456
2457 for (i = hdev->num_vmdq_vport + 1; i < hdev->num_alloc_vport; i++) {
2458 struct hclge_vport *vport = &hdev->vport[i];
2459 int ret;
2460
2461 /* Send cmd to set/clear VF's FUNC_RST_ING */
2462 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
2463 if (ret) {
2464 dev_err(&hdev->pdev->dev,
5f9c2a66 2465 "set vf(%d) rst failed %d!\n",
7885e906
HT		 2466 vport->vport_id, ret);
2467 return ret;
2468 }
2469
2470 if (!reset)
2471 continue;
2472
2473 /* Inform VF to process the reset.
2474 * hclge_inform_reset_assert_to_vf may fail if VF
2475 * driver is not loaded.
2476 */
2477 ret = hclge_inform_reset_assert_to_vf(vport);
2478 if (ret)
2479 dev_warn(&hdev->pdev->dev,
5f9c2a66 2480 "inform reset to vf(%d) failed %d!\n",
7885e906
HT		 2481 vport->vport_id, ret);
2482 }
2483
2484 return 0;
2485}
2486
13a86fae 2487int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2488{
2489 struct hclge_desc desc;
2490 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2491 int ret;
2492
2493 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
ccc23ef3 2494 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2495 req->fun_reset_vfid = func_id;
2496
2497 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2498 if (ret)
2499 dev_err(&hdev->pdev->dev,
2500 "send function reset cmd fail, status =%d\n", ret);
2501
2502 return ret;
2503}
2504
d5752031 2505static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2506{
2507 struct pci_dev *pdev = hdev->pdev;
2508 u32 val;
2509
d5752031 2510 switch (hdev->reset_type) {
4ed340ab
L		 2511 case HNAE3_GLOBAL_RESET:
2512 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
ccc23ef3 2513 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2514 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2515 dev_info(&pdev->dev, "Global Reset requested\n");
2516 break;
2517 case HNAE3_CORE_RESET:
2518 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
ccc23ef3 2519 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2520 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2521 dev_info(&pdev->dev, "Core Reset requested\n");
2522 break;
2523 case HNAE3_FUNC_RESET:
2524 dev_info(&pdev->dev, "PF Reset requested\n");
ed4a1bb8
SM		 2525 /* schedule again to check later */
2526 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2527 hclge_reset_task_schedule(hdev);
4ed340ab 2528 break;
26977990
HT		 2529 case HNAE3_FLR_RESET:
2530 dev_info(&pdev->dev, "FLR requested\n");
2531 /* schedule again to check later */
2532 set_bit(HNAE3_FLR_RESET, &hdev->reset_pending);
2533 hclge_reset_task_schedule(hdev);
2534 break;
4ed340ab
L		 2535 default:
2536 dev_warn(&pdev->dev,
d5752031 2537 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2538 break;
2539 }
2540}
2541
d5752031
SM		 2542static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2543 unsigned long *addr)
2544{
2545 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2546
2547 /* return the highest priority reset level amongst all */
62aff578
HT		 2548 if (test_bit(HNAE3_IMP_RESET, addr)) {
2549 rst_level = HNAE3_IMP_RESET;
2550 clear_bit(HNAE3_IMP_RESET, addr);
2551 clear_bit(HNAE3_GLOBAL_RESET, addr);
2552 clear_bit(HNAE3_CORE_RESET, addr);
2553 clear_bit(HNAE3_FUNC_RESET, addr);
2554 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
d5752031 2555 rst_level = HNAE3_GLOBAL_RESET;
62aff578
HT		 2556 clear_bit(HNAE3_GLOBAL_RESET, addr);
2557 clear_bit(HNAE3_CORE_RESET, addr);
2558 clear_bit(HNAE3_FUNC_RESET, addr);
2559 } else if (test_bit(HNAE3_CORE_RESET, addr)) {
d5752031 2560 rst_level = HNAE3_CORE_RESET;
62aff578
HT		 2561 clear_bit(HNAE3_CORE_RESET, addr);
2562 clear_bit(HNAE3_FUNC_RESET, addr);
2563 } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
d5752031 2564 rst_level = HNAE3_FUNC_RESET;
62aff578 2565 clear_bit(HNAE3_FUNC_RESET, addr);
26977990
HT		 2566 } else if (test_bit(HNAE3_FLR_RESET, addr)) {
2567 rst_level = HNAE3_FLR_RESET;
2568 clear_bit(HNAE3_FLR_RESET, addr);
62aff578 2569 }
d5752031
SM		 2570
2571 return rst_level;
2572}
2573
e9a50d09
YL		 2574static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2575{
2576 u32 clearval = 0;
2577
2578 switch (hdev->reset_type) {
2579 case HNAE3_IMP_RESET:
2580 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2581 break;
2582 case HNAE3_GLOBAL_RESET:
2583 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2584 break;
2585 case HNAE3_CORE_RESET:
2586 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2587 break;
2588 default:
e9a50d09
YL		 2589 break;
2590 }
2591
2592 if (!clearval)
2593 return;
2594
2595 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2596 hclge_enable_vector(&hdev->misc_vector, true);
2597}
2598
7885e906
HT		 2599static int hclge_reset_prepare_down(struct hclge_dev *hdev)
2600{
2601 int ret = 0;
2602
2603 switch (hdev->reset_type) {
2604 case HNAE3_FUNC_RESET:
26977990
HT		 2605 /* fall through */
2606 case HNAE3_FLR_RESET:
7885e906
HT		 2607 ret = hclge_set_all_vf_rst(hdev, true);
2608 break;
2609 default:
2610 break;
2611 }
2612
2613 return ret;
2614}
2615
48ac80db
HT		 2616static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
2617{
de2eae69 2618 u32 reg_val;
48ac80db
HT		 2619 int ret = 0;
2620
2621 switch (hdev->reset_type) {
2622 case HNAE3_FUNC_RESET:
7885e906
HT		 2623 /* There is no mechanism for PF to know if VF has stopped IO
2624 * for now, just wait 100 ms for VF to stop IO
2625 */
2626 msleep(100);
48ac80db
HT		 2627 ret = hclge_func_reset_cmd(hdev, 0);
2628 if (ret) {
2629 dev_err(&hdev->pdev->dev,
7707c27b 2630 "asserting function reset fail %d!\n", ret);
48ac80db
HT		 2631 return ret;
2632 }
2633
2634 /* After performaning pf reset, it is not necessary to do the
2635 * mailbox handling or send any command to firmware, because
2636 * any mailbox handling or command to firmware is only valid
2637 * after hclge_cmd_init is called.
2638 */
2639 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2640 break;
26977990
HT		 2641 case HNAE3_FLR_RESET:
2642 /* There is no mechanism for PF to know if VF has stopped IO
2643 * for now, just wait 100 ms for VF to stop IO
2644 */
2645 msleep(100);
2646 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2647 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
2648 break;
de2eae69
HT		 2649 case HNAE3_IMP_RESET:
2650 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
2651 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
2652 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
2653 break;
48ac80db
HT		 2654 default:
2655 break;
2656 }
2657
2658 dev_info(&hdev->pdev->dev, "prepare wait ok\n");
2659
2660 return ret;
2661}
2662
1afdb53a
HT		 2663static bool hclge_reset_err_handle(struct hclge_dev *hdev, bool is_timeout)
2664{
2665#define MAX_RESET_FAIL_CNT 5
2666#define RESET_UPGRADE_DELAY_SEC 10
2667
2668 if (hdev->reset_pending) {
2669 dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
2670 hdev->reset_pending);
2671 return true;
2672 } else if ((hdev->reset_type != HNAE3_IMP_RESET) &&
2673 (hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) &
2674 BIT(HCLGE_IMP_RESET_BIT))) {
2675 dev_info(&hdev->pdev->dev,
2676 "reset failed because IMP Reset is pending\n");
2677 hclge_clear_reset_cause(hdev);
2678 return false;
2679 } else if (hdev->reset_fail_cnt < MAX_RESET_FAIL_CNT) {
2680 hdev->reset_fail_cnt++;
2681 if (is_timeout) {
2682 set_bit(hdev->reset_type, &hdev->reset_pending);
2683 dev_info(&hdev->pdev->dev,
2684 "re-schedule to wait for hw reset done\n");
2685 return true;
2686 }
2687
2688 dev_info(&hdev->pdev->dev, "Upgrade reset level\n");
2689 hclge_clear_reset_cause(hdev);
2690 mod_timer(&hdev->reset_timer,
2691 jiffies + RESET_UPGRADE_DELAY_SEC * HZ);
2692
2693 return false;
2694 }
2695
2696 hclge_clear_reset_cause(hdev);
2697 dev_err(&hdev->pdev->dev, "Reset fail!\n");
2698 return false;
2699}
2700
7885e906
HT		 2701static int hclge_reset_prepare_up(struct hclge_dev *hdev)
2702{
2703 int ret = 0;
2704
2705 switch (hdev->reset_type) {
2706 case HNAE3_FUNC_RESET:
26977990
HT		 2707 /* fall through */
2708 case HNAE3_FLR_RESET:
7885e906
HT		 2709 ret = hclge_set_all_vf_rst(hdev, false);
2710 break;
2711 default:
2712 break;
2713 }
2714
2715 return ret;
2716}
2717
d5752031
SM		 2718static void hclge_reset(struct hclge_dev *hdev)
2719{
7ce98982 2720 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1afdb53a
HT		 2721 bool is_timeout = false;
2722 int ret;
1a45360a 2723
7ce98982
JS		 2724 /* Initialize ae_dev reset status as well, in case enet layer wants to
2725 * know if device is undergoing reset
2726 */
2727 ae_dev->reset_type = hdev->reset_type;
225c02eb 2728 hdev->reset_count++;
1a2f7bf2 2729 hdev->last_reset_time = jiffies;
d5752031 2730 /* perform reset of the stack & ae device for a client */
1afdb53a
HT		 2731 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
2732 if (ret)
2733 goto err_reset;
2734
7885e906
HT		 2735 ret = hclge_reset_prepare_down(hdev);
2736 if (ret)
2737 goto err_reset;
2738
47622dc9 2739 rtnl_lock();
1afdb53a
HT		 2740 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2741 if (ret)
2742 goto err_reset_lock;
d5752031 2743
1afdb53a 2744 rtnl_unlock();
48ac80db 2745
1afdb53a
HT		 2746 ret = hclge_reset_prepare_wait(hdev);
2747 if (ret)
2748 goto err_reset;
e9a50d09 2749
1afdb53a
HT		 2750 if (hclge_reset_wait(hdev)) {
2751 is_timeout = true;
2752 goto err_reset;
d5752031
SM		 2753 }
2754
1afdb53a
HT		 2755 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
2756 if (ret)
2757 goto err_reset;
2758
2759 rtnl_lock();
2760 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2761 if (ret)
2762 goto err_reset_lock;
2763
2764 ret = hclge_reset_ae_dev(hdev->ae_dev);
2765 if (ret)
2766 goto err_reset_lock;
2767
2768 ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2769 if (ret)
2770 goto err_reset_lock;
2771
2772 hclge_clear_reset_cause(hdev);
2773
7885e906
HT		 2774 ret = hclge_reset_prepare_up(hdev);
2775 if (ret)
2776 goto err_reset_lock;
2777
1afdb53a
HT		 2778 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2779 if (ret)
2780 goto err_reset_lock;
2781
47622dc9 2782 rtnl_unlock();
3db6b633 2783
1afdb53a
HT		 2784 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
2785 if (ret)
2786 goto err_reset;
2787
2788 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
2789 if (ret)
2790 goto err_reset;
2791
2792 return;
2793
2794err_reset_lock:
2795 rtnl_unlock();
2796err_reset:
2797 if (hclge_reset_err_handle(hdev, is_timeout))
2798 hclge_reset_task_schedule(hdev);
d5752031
SM		 2799}
2800
538d8ba0
SJ		 2801static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
2802{
2803 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2804 struct hclge_dev *hdev = ae_dev->priv;
2805
2806 /* We might end up getting called broadly because of 2 below cases:
2807 * 1. Recoverable error was conveyed through APEI and only way to bring
2808 * normalcy is to reset.
2809 * 2. A new reset request from the stack due to timeout
2810 *
2811 * For the first case,error event might not have ae handle available.
2812 * check if this is a new reset request and we are not here just because
4aef908d
SM		 2813 * last reset attempt did not succeed and watchdog hit us again. We will
2814 * know this if last reset request did not occur very recently (watchdog
2815 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2816 * In case of new request we reset the "reset level" to PF reset.
1a45360a
HT		 2817 * And if it is a repeat reset request of the most recent one then we
2818 * want to make sure we throttle the reset request. Therefore, we will
2819 * not allow it again before 3*HZ times.
4aef908d 2820 */
538d8ba0
SJ		 2821 if (!handle)
2822 handle = &hdev->vport[0].nic;
2823
1a2f7bf2 2824 if (time_before(jiffies, (hdev->last_reset_time + 3 * HZ)))
1a45360a 2825 return;
2c883d73 2826 else if (hdev->default_reset_request)
1a2f7bf2 2827 hdev->reset_level =
2c883d73
HT		 2828 hclge_get_reset_level(hdev,
2829 &hdev->default_reset_request);
1a2f7bf2
HT		 2830 else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ)))
2831 hdev->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2832
4aef908d 2833 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
1a2f7bf2 2834 hdev->reset_level);
4aef908d
SM		 2835
2836 /* request reset & schedule reset task */
1a2f7bf2 2837 set_bit(hdev->reset_level, &hdev->reset_request);
4aef908d
SM		 2838 hclge_reset_task_schedule(hdev);
2839
1a2f7bf2
HT		 2840 if (hdev->reset_level < HNAE3_GLOBAL_RESET)
2841 hdev->reset_level++;
4ed340ab
L		 2842}
2843
2c883d73
HT		 2844static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2845 enum hnae3_reset_type rst_type)
2846{
2847 struct hclge_dev *hdev = ae_dev->priv;
2848
2849 set_bit(rst_type, &hdev->default_reset_request);
2850}
2851
1afdb53a
HT		 2852static void hclge_reset_timer(struct timer_list *t)
2853{
2854 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
2855
2856 dev_info(&hdev->pdev->dev,
2857 "triggering global reset in reset timer\n");
2858 set_bit(HNAE3_GLOBAL_RESET, &hdev->default_reset_request);
2859 hclge_reset_event(hdev->pdev, NULL);
2860}
2861
4ed340ab
L		 2862static void hclge_reset_subtask(struct hclge_dev *hdev)
2863{
d5752031
SM		 2864 /* check if there is any ongoing reset in the hardware. This status can
2865 * be checked from reset_pending. If there is then, we need to wait for
2866 * hardware to complete reset.
2867 * a. If we are able to figure out in reasonable time that hardware
2868 * has fully resetted then, we can proceed with driver, client
2869 * reset.
2870 * b. else, we can come back later to check this status so re-sched
2871 * now.
2872 */
1a2f7bf2 2873 hdev->last_reset_time = jiffies;
d5752031
SM		 2874 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2875 if (hdev->reset_type != HNAE3_NONE_RESET)
2876 hclge_reset(hdev);
4ed340ab 2877
d5752031
SM		 2878 /* check if we got any *new* reset requests to be honored */
2879 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2880 if (hdev->reset_type != HNAE3_NONE_RESET)
2881 hclge_do_reset(hdev);
4ed340ab 2882
4ed340ab
L		 2883 hdev->reset_type = HNAE3_NONE_RESET;
2884}
2885
ed4a1bb8 2886static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2887{
ed4a1bb8
SM		 2888 struct hclge_dev *hdev =
2889 container_of(work, struct hclge_dev, rst_service_task);
2890
2891 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2892 return;
2893
2894 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2895
4ed340ab 2896 hclge_reset_subtask(hdev);
ed4a1bb8
SM		 2897
2898 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2899}
2900
22fd3468
SM		 2901static void hclge_mailbox_service_task(struct work_struct *work)
2902{
2903 struct hclge_dev *hdev =
2904 container_of(work, struct hclge_dev, mbx_service_task);
2905
2906 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2907 return;
2908
2909 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2910
2911 hclge_mbx_handler(hdev);
2912
2913 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2914}
2915
46a3df9f
S		 2916static void hclge_service_task(struct work_struct *work)
2917{
2918 struct hclge_dev *hdev =
2919 container_of(work, struct hclge_dev, service_task);
2920
7a5d2a39
JS		 2921 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2922 hclge_update_stats_for_all(hdev);
2923 hdev->hw_stats.stats_timer = 0;
2924 }
2925
46a3df9f
S		 2926 hclge_update_speed_duplex(hdev);
2927 hclge_update_link_status(hdev);
46a3df9f
S		 2928 hclge_service_complete(hdev);
2929}
2930
46a3df9f
S		 2931struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2932{
2933 /* VF handle has no client */
2934 if (!handle->client)
2935 return container_of(handle, struct hclge_vport, nic);
2936 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2937 return container_of(handle, struct hclge_vport, roce);
2938 else
2939 return container_of(handle, struct hclge_vport, nic);
2940}
2941
2942static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2943 struct hnae3_vector_info *vector_info)
2944{
2945 struct hclge_vport *vport = hclge_get_vport(handle);
2946 struct hnae3_vector_info *vector = vector_info;
2947 struct hclge_dev *hdev = vport->back;
2948 int alloc = 0;
2949 int i, j;
2950
2951 vector_num = min(hdev->num_msi_left, vector_num);
2952
2953 for (j = 0; j < vector_num; j++) {
2954 for (i = 1; i < hdev->num_msi; i++) {
2955 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2956 vector->vector = pci_irq_vector(hdev->pdev, i);
2957 vector->io_addr = hdev->hw.io_base +
2958 HCLGE_VECTOR_REG_BASE +
2959 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2960 vport->vport_id *
2961 HCLGE_VECTOR_VF_OFFSET;
2962 hdev->vector_status[i] = vport->vport_id;
887c3820 2963 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2964
2965 vector++;
2966 alloc++;
2967
2968 break;
2969 }
2970 }
2971 }
2972 hdev->num_msi_left -= alloc;
2973 hdev->num_msi_used += alloc;
2974
2975 return alloc;
2976}
2977
2978static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2979{
2980 int i;
2981
887c3820
SM		 2982 for (i = 0; i < hdev->num_msi; i++)
2983 if (vector == hdev->vector_irq[i])
2984 return i;
2985
46a3df9f
S		 2986 return -EINVAL;
2987}
2988
7412200c
YL		 2989static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2990{
2991 struct hclge_vport *vport = hclge_get_vport(handle);
2992 struct hclge_dev *hdev = vport->back;
2993 int vector_id;
2994
2995 vector_id = hclge_get_vector_index(hdev, vector);
2996 if (vector_id < 0) {
2997 dev_err(&hdev->pdev->dev,
2998 "Get vector index fail. vector_id =%d\n", vector_id);
2999 return vector_id;
3000 }
3001
3002 hclge_free_vector(hdev, vector_id);
3003
3004 return 0;
3005}
3006
46a3df9f
S		 3007static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
3008{
3009 return HCLGE_RSS_KEY_SIZE;
3010}
3011
3012static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3013{
3014 return HCLGE_RSS_IND_TBL_SIZE;
3015}
3016
46a3df9f
S		 3017static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3018 const u8 hfunc, const u8 *key)
3019{
d44f9b63 3020 struct hclge_rss_config_cmd *req;
46a3df9f
S		 3021 struct hclge_desc desc;
3022 int key_offset;
3023 int key_size;
3024 int ret;
3025
d44f9b63 3026 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 3027
3028 for (key_offset = 0; key_offset < 3; key_offset++) {
3029 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3030 false);
3031
3032 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3033 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3034
3035 if (key_offset == 2)
3036 key_size =
3037 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3038 else
3039 key_size = HCLGE_RSS_HASH_KEY_NUM;
3040
3041 memcpy(req->hash_key,
3042 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3043
3044 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3045 if (ret) {
3046 dev_err(&hdev->pdev->dev,
3047 "Configure RSS config fail, status = %d\n",
3048 ret);
3049 return ret;
3050 }
3051 }
3052 return 0;
3053}
3054
dcd4ef5e 3055static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3056{
d44f9b63 3057 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3058 struct hclge_desc desc;
3059 int i, j;
3060 int ret;
3061
d44f9b63 3062 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3063
3064 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3065 hclge_cmd_setup_basic_desc
3066 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3067
a90bb9a5
YL		 3068 req->start_table_index =
3069 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3070 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3071
3072 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3073 req->rss_result[j] =
3074 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3075
3076 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3077 if (ret) {
3078 dev_err(&hdev->pdev->dev,
3079 "Configure rss indir table fail,status = %d\n",
3080 ret);
3081 return ret;
3082 }
3083 }
3084 return 0;
3085}
3086
3087static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3088 u16 *tc_size, u16 *tc_offset)
3089{
d44f9b63 3090 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3091 struct hclge_desc desc;
3092 int ret;
3093 int i;
3094
3095 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3096 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3097
3098 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3099 u16 mode = 0;
3100
ccc23ef3
PL		 3101 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3102 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3103 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3104 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3105 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3106
3107 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3108 }
3109
3110 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 3111 if (ret)
46a3df9f
S		 3112 dev_err(&hdev->pdev->dev,
3113 "Configure rss tc mode fail, status = %d\n", ret);
46a3df9f 3114
90415e85 3115 return ret;
46a3df9f
S		 3116}
3117
8e4c877d
PL		 3118static void hclge_get_rss_type(struct hclge_vport *vport)
3119{
3120 if (vport->rss_tuple_sets.ipv4_tcp_en ||
3121 vport->rss_tuple_sets.ipv4_udp_en ||
3122 vport->rss_tuple_sets.ipv4_sctp_en ||
3123 vport->rss_tuple_sets.ipv6_tcp_en ||
3124 vport->rss_tuple_sets.ipv6_udp_en ||
3125 vport->rss_tuple_sets.ipv6_sctp_en)
3126 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4;
3127 else if (vport->rss_tuple_sets.ipv4_fragment_en ||
3128 vport->rss_tuple_sets.ipv6_fragment_en)
3129 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3;
3130 else
3131 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE;
3132}
3133
46a3df9f
S		 3134static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3135{
d44f9b63 3136 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3137 struct hclge_desc desc;
3138 int ret;
3139
3140 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3141
d44f9b63 3142 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef
YL		 3143
3144 /* Get the tuple cfg from pf */
3145 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3146 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3147 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3148 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3149 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3150 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3151 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3152 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
8e4c877d 3153 hclge_get_rss_type(&hdev->vport[0]);
46a3df9f 3154 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 3155 if (ret)
46a3df9f
S		 3156 dev_err(&hdev->pdev->dev,
3157 "Configure rss input fail, status = %d\n", ret);
90415e85 3158 return ret;
46a3df9f
S		 3159}
3160
3161static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3162 u8 *key, u8 *hfunc)
3163{
3164 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3165 int i;
3166
3167 /* Get hash algorithm */
6868d695
JS		 3168 if (hfunc) {
3169 switch (vport->rss_algo) {
3170 case HCLGE_RSS_HASH_ALGO_TOEPLITZ:
3171 *hfunc = ETH_RSS_HASH_TOP;
3172 break;
3173 case HCLGE_RSS_HASH_ALGO_SIMPLE:
3174 *hfunc = ETH_RSS_HASH_XOR;
3175 break;
3176 default:
3177 *hfunc = ETH_RSS_HASH_UNKNOWN;
3178 break;
3179 }
3180 }
46a3df9f
S		 3181
3182 /* Get the RSS Key required by the user */
3183 if (key)
3184 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3185
3186 /* Get indirect table */
3187 if (indir)
3188 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3189 indir[i] = vport->rss_indirection_tbl[i];
3190
3191 return 0;
3192}
3193
3194static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3195 const u8 *key, const u8 hfunc)
3196{
3197 struct hclge_vport *vport = hclge_get_vport(handle);
3198 struct hclge_dev *hdev = vport->back;
3199 u8 hash_algo;
3200 int ret, i;
3201
3202 /* Set the RSS Hash Key if specififed by the user */
3203 if (key) {
6868d695
JS		 3204 switch (hfunc) {
3205 case ETH_RSS_HASH_TOP:
46a3df9f 3206 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
6868d695
JS		 3207 break;
3208 case ETH_RSS_HASH_XOR:
3209 hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
3210 break;
3211 case ETH_RSS_HASH_NO_CHANGE:
3212 hash_algo = vport->rss_algo;
3213 break;
3214 default:
46a3df9f 3215 return -EINVAL;
6868d695
JS		 3216 }
3217
46a3df9f
S		 3218 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3219 if (ret)
3220 return ret;
dcd4ef5e
YL		 3221
3222 /* Update the shadow RSS key with user specified qids */
3223 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3224 vport->rss_algo = hash_algo;
46a3df9f
S		 3225 }
3226
3227 /* Update the shadow RSS table with user specified qids */
3228 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3229 vport->rss_indirection_tbl[i] = indir[i];
3230
3231 /* Update the hardware */
dcd4ef5e 3232 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3233}
3234
f7db940a
L		 3235static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3236{
3237 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3238
3239 if (nfc->data & RXH_L4_B_2_3)
3240 hash_sets |= HCLGE_D_PORT_BIT;
3241 else
3242 hash_sets &= ~HCLGE_D_PORT_BIT;
3243
3244 if (nfc->data & RXH_IP_SRC)
3245 hash_sets |= HCLGE_S_IP_BIT;
3246 else
3247 hash_sets &= ~HCLGE_S_IP_BIT;
3248
3249 if (nfc->data & RXH_IP_DST)
3250 hash_sets |= HCLGE_D_IP_BIT;
3251 else
3252 hash_sets &= ~HCLGE_D_IP_BIT;
3253
3254 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3255 hash_sets |= HCLGE_V_TAG_BIT;
3256
3257 return hash_sets;
3258}
3259
3260static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3261 struct ethtool_rxnfc *nfc)
3262{
3263 struct hclge_vport *vport = hclge_get_vport(handle);
3264 struct hclge_dev *hdev = vport->back;
3265 struct hclge_rss_input_tuple_cmd *req;
3266 struct hclge_desc desc;
3267 u8 tuple_sets;
3268 int ret;
3269
3270 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3271 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3272 return -EINVAL;
3273
3274 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
637053ef 3275 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 3276
637053ef
YL		 3277 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3278 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3279 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3280 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3281 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3282 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3283 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3284 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 3285
3286 tuple_sets = hclge_get_rss_hash_bits(nfc);
3287 switch (nfc->flow_type) {
3288 case TCP_V4_FLOW:
3289 req->ipv4_tcp_en = tuple_sets;
3290 break;
3291 case TCP_V6_FLOW:
3292 req->ipv6_tcp_en = tuple_sets;
3293 break;
3294 case UDP_V4_FLOW:
3295 req->ipv4_udp_en = tuple_sets;
3296 break;
3297 case UDP_V6_FLOW:
3298 req->ipv6_udp_en = tuple_sets;
3299 break;
3300 case SCTP_V4_FLOW:
3301 req->ipv4_sctp_en = tuple_sets;
3302 break;
3303 case SCTP_V6_FLOW:
3304 if ((nfc->data & RXH_L4_B_0_1) ||
3305 (nfc->data & RXH_L4_B_2_3))
3306 return -EINVAL;
3307
3308 req->ipv6_sctp_en = tuple_sets;
3309 break;
3310 case IPV4_FLOW:
3311 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3312 break;
3313 case IPV6_FLOW:
3314 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3315 break;
3316 default:
3317 return -EINVAL;
3318 }
3319
3320 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
637053ef 3321 if (ret) {
f7db940a
L		 3322 dev_err(&hdev->pdev->dev,
3323 "Set rss tuple fail, status = %d\n", ret);
637053ef
YL		 3324 return ret;
3325 }
f7db940a 3326
637053ef
YL		 3327 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3328 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3329 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3330 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3331 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3332 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3333 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3334 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
8e4c877d 3335 hclge_get_rss_type(vport);
637053ef 3336 return 0;
f7db940a
L		 3337}
3338
07d29954
L		 3339static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3340 struct ethtool_rxnfc *nfc)
3341{
3342 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3343 u8 tuple_sets;
07d29954
L		 3344
3345 nfc->data = 0;
3346
07d29954
L		 3347 switch (nfc->flow_type) {
3348 case TCP_V4_FLOW:
637053ef 3349 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3350 break;
3351 case UDP_V4_FLOW:
637053ef 3352 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3353 break;
3354 case TCP_V6_FLOW:
637053ef 3355 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3356 break;
3357 case UDP_V6_FLOW:
637053ef 3358 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3359 break;
3360 case SCTP_V4_FLOW:
637053ef 3361 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3362 break;
3363 case SCTP_V6_FLOW:
637053ef 3364 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3365 break;
3366 case IPV4_FLOW:
3367 case IPV6_FLOW:
3368 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3369 break;
3370 default:
3371 return -EINVAL;
3372 }
3373
3374 if (!tuple_sets)
3375 return 0;
3376
3377 if (tuple_sets & HCLGE_D_PORT_BIT)
3378 nfc->data |= RXH_L4_B_2_3;
3379 if (tuple_sets & HCLGE_S_PORT_BIT)
3380 nfc->data |= RXH_L4_B_0_1;
3381 if (tuple_sets & HCLGE_D_IP_BIT)
3382 nfc->data |= RXH_IP_DST;
3383 if (tuple_sets & HCLGE_S_IP_BIT)
3384 nfc->data |= RXH_IP_SRC;
3385
3386 return 0;
3387}
3388
46a3df9f
S		 3389static int hclge_get_tc_size(struct hnae3_handle *handle)
3390{
3391 struct hclge_vport *vport = hclge_get_vport(handle);
3392 struct hclge_dev *hdev = vport->back;
3393
3394 return hdev->rss_size_max;
3395}
3396
77f255c1 3397int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3398{
46a3df9f 3399 struct hclge_vport *vport = hdev->vport;
8015bb74
YL		 3400 u8 *rss_indir = vport[0].rss_indirection_tbl;
3401 u16 rss_size = vport[0].alloc_rss_size;
3402 u8 *key = vport[0].rss_hash_key;
3403 u8 hfunc = vport[0].rss_algo;
46a3df9f 3404 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3405 u16 tc_valid[HCLGE_MAX_TC_NUM];
3406 u16 tc_size[HCLGE_MAX_TC_NUM];
8015bb74
YL		 3407 u16 roundup_size;
3408 int i, ret;
68ece54e 3409
46a3df9f
S		 3410 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3411 if (ret)
8015bb74 3412 return ret;
46a3df9f 3413
46a3df9f
S		 3414 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3415 if (ret)
8015bb74 3416 return ret;
46a3df9f
S		 3417
3418 ret = hclge_set_rss_input_tuple(hdev);
3419 if (ret)
8015bb74 3420 return ret;
46a3df9f 3421
68ece54e
YL		 3422 /* Each TC have the same queue size, and tc_size set to hardware is
3423 * the log2 of roundup power of two of rss_size, the acutal queue
3424 * size is limited by indirection table.
3425 */
3426 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3427 dev_err(&hdev->pdev->dev,
3428 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3429 rss_size);
8015bb74 3430 return -EINVAL;
68ece54e
YL		 3431 }
3432
3433 roundup_size = roundup_pow_of_two(rss_size);
3434 roundup_size = ilog2(roundup_size);
3435
46a3df9f 3436 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3437 tc_valid[i] = 0;
46a3df9f 3438
68ece54e
YL		 3439 if (!(hdev->hw_tc_map & BIT(i)))
3440 continue;
3441
3442 tc_valid[i] = 1;
3443 tc_size[i] = roundup_size;
3444 tc_offset[i] = rss_size * i;
46a3df9f 3445 }
68ece54e 3446
8015bb74
YL		 3447 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3448}
46a3df9f 3449
8015bb74
YL		 3450void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3451{
3452 struct hclge_vport *vport = hdev->vport;
3453 int i, j;
46a3df9f 3454
8015bb74
YL		 3455 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3456 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3457 vport[j].rss_indirection_tbl[i] =
3458 i % vport[j].alloc_rss_size;
3459 }
3460}
3461
3462static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3463{
3464 struct hclge_vport *vport = hdev->vport;
3465 int i;
3466
8015bb74
YL		 3467 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3468 vport[i].rss_tuple_sets.ipv4_tcp_en =
3469 HCLGE_RSS_INPUT_TUPLE_OTHER;
3470 vport[i].rss_tuple_sets.ipv4_udp_en =
3471 HCLGE_RSS_INPUT_TUPLE_OTHER;
3472 vport[i].rss_tuple_sets.ipv4_sctp_en =
3473 HCLGE_RSS_INPUT_TUPLE_SCTP;
3474 vport[i].rss_tuple_sets.ipv4_fragment_en =
3475 HCLGE_RSS_INPUT_TUPLE_OTHER;
3476 vport[i].rss_tuple_sets.ipv6_tcp_en =
3477 HCLGE_RSS_INPUT_TUPLE_OTHER;
3478 vport[i].rss_tuple_sets.ipv6_udp_en =
3479 HCLGE_RSS_INPUT_TUPLE_OTHER;
3480 vport[i].rss_tuple_sets.ipv6_sctp_en =
3481 HCLGE_RSS_INPUT_TUPLE_SCTP;
3482 vport[i].rss_tuple_sets.ipv6_fragment_en =
3483 HCLGE_RSS_INPUT_TUPLE_OTHER;
3484
3485 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
823fe868
FL		 3486
3487 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
8015bb74
YL		 3488 }
3489
3490 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3491}
3492
63d7e66f
SM		 3493int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3494 int vector_id, bool en,
3495 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3496{
3497 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3498 struct hnae3_ring_chain_node *node;
3499 struct hclge_desc desc;
63d7e66f
SM		 3500 struct hclge_ctrl_vector_chain_cmd *req
3501 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3502 enum hclge_cmd_status status;
3503 enum hclge_opcode_type op;
3504 u16 tqp_type_and_id;
46a3df9f
S		 3505 int i;
3506
63d7e66f
SM		 3507 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3508 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3509 req->int_vector_id = vector_id;
3510
3511 i = 0;
3512 for (node = ring_chain; node; node = node->next) {
63d7e66f 3513 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
ccc23ef3
PL		 3514 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3515 HCLGE_INT_TYPE_S,
3516 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3517 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3518 HCLGE_TQP_ID_S, node->tqp_index);
3519 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3520 HCLGE_INT_GL_IDX_S,
3521 hnae3_get_field(node->int_gl_idx,
3522 HNAE3_RING_GL_IDX_M,
3523 HNAE3_RING_GL_IDX_S));
63d7e66f 3524 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3525 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3526 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
63d7e66f 3527 req->vfid = vport->vport_id;
46a3df9f 3528
63d7e66f
SM		 3529 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3530 if (status) {
46a3df9f
S		 3531 dev_err(&hdev->pdev->dev,
3532 "Map TQP fail, status is %d.\n",
63d7e66f
SM		 3533 status);
3534 return -EIO;
46a3df9f
S		 3535 }
3536 i = 0;
3537
3538 hclge_cmd_setup_basic_desc(&desc,
63d7e66f 3539 op,
46a3df9f
S		 3540 false);
3541 req->int_vector_id = vector_id;
3542 }
3543 }
3544
3545 if (i > 0) {
3546 req->int_cause_num = i;
63d7e66f
SM		 3547 req->vfid = vport->vport_id;
3548 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3549 if (status) {
46a3df9f 3550 dev_err(&hdev->pdev->dev,
63d7e66f
SM		 3551 "Map TQP fail, status is %d.\n", status);
3552 return -EIO;
46a3df9f
S		 3553 }
3554 }
3555
3556 return 0;
3557}
3558
63d7e66f
SM		 3559static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3560 int vector,
3561 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3562{
3563 struct hclge_vport *vport = hclge_get_vport(handle);
3564 struct hclge_dev *hdev = vport->back;
3565 int vector_id;
3566
3567 vector_id = hclge_get_vector_index(hdev, vector);
3568 if (vector_id < 0) {
3569 dev_err(&hdev->pdev->dev,
63d7e66f 3570 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3571 return vector_id;
3572 }
3573
63d7e66f 3574 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3575}
3576
63d7e66f
SM		 3577static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3578 int vector,
3579 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3580{
3581 struct hclge_vport *vport = hclge_get_vport(handle);
3582 struct hclge_dev *hdev = vport->back;
63d7e66f 3583 int vector_id, ret;
46a3df9f 3584
f9637cc2
PL		 3585 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3586 return 0;
3587
46a3df9f
S		 3588 vector_id = hclge_get_vector_index(hdev, vector);
3589 if (vector_id < 0) {
3590 dev_err(&handle->pdev->dev,
3591 "Get vector index fail. ret =%d\n", vector_id);
3592 return vector_id;
3593 }
3594
63d7e66f 3595 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
7412200c 3596 if (ret)
63d7e66f
SM		 3597 dev_err(&handle->pdev->dev,
3598 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3599 vector_id,
3600 ret);
46a3df9f 3601
7412200c 3602 return ret;
46a3df9f
S		 3603}
3604
3605int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3606 struct hclge_promisc_param *param)
3607{
d44f9b63 3608 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3609 struct hclge_desc desc;
3610 int ret;
3611
3612 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3613
d44f9b63 3614 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3615 req->vf_id = param->vf_id;
4771e104
PL		 3616
3617 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3618 * pdev revision(0x20), new revision support them. The
3619 * value of this two fields will not return error when driver
3620 * send command to fireware in revision(0x20).
3621 */
3622 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3623 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3624
3625 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 3626 if (ret)
46a3df9f
S		 3627 dev_err(&hdev->pdev->dev,
3628 "Set promisc mode fail, status is %d.\n", ret);
90415e85
JS		 3629
3630 return ret;
46a3df9f
S		 3631}
3632
3633void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3634 bool en_mc, bool en_bc, int vport_id)
3635{
3636 if (!param)
3637 return;
3638
3639 memset(param, 0, sizeof(struct hclge_promisc_param));
3640 if (en_uc)
3641 param->enable = HCLGE_PROMISC_EN_UC;
3642 if (en_mc)
3643 param->enable |= HCLGE_PROMISC_EN_MC;
3644 if (en_bc)
3645 param->enable |= HCLGE_PROMISC_EN_BC;
3646 param->vf_id = vport_id;
3647}
3648
abe62a63
HT		 3649static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3650 bool en_mc_pmc)
46a3df9f
S		 3651{
3652 struct hclge_vport *vport = hclge_get_vport(handle);
3653 struct hclge_dev *hdev = vport->back;
3654 struct hclge_promisc_param param;
3655
e8600a3d
PL		 3656 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3657 vport->vport_id);
abe62a63 3658 return hclge_cmd_set_promisc_mode(hdev, &param);
46a3df9f
S		 3659}
3660
10a954bc
JS		 3661static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
3662{
3663 struct hclge_get_fd_mode_cmd *req;
3664 struct hclge_desc desc;
3665 int ret;
3666
3667 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
3668
3669 req = (struct hclge_get_fd_mode_cmd *)desc.data;
3670
3671 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3672 if (ret) {
3673 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
3674 return ret;
3675 }
3676
3677 *fd_mode = req->mode;
3678
3679 return ret;
3680}
3681
3682static int hclge_get_fd_allocation(struct hclge_dev *hdev,
3683 u32 *stage1_entry_num,
3684 u32 *stage2_entry_num,
3685 u16 *stage1_counter_num,
3686 u16 *stage2_counter_num)
3687{
3688 struct hclge_get_fd_allocation_cmd *req;
3689 struct hclge_desc desc;
3690 int ret;
3691
3692 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
3693
3694 req = (struct hclge_get_fd_allocation_cmd *)desc.data;
3695
3696 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3697 if (ret) {
3698 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
3699 ret);
3700 return ret;
3701 }
3702
3703 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
3704 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
3705 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
3706 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
3707
3708 return ret;
3709}
3710
3711static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num)
3712{
3713 struct hclge_set_fd_key_config_cmd *req;
3714 struct hclge_fd_key_cfg *stage;
3715 struct hclge_desc desc;
3716 int ret;
3717
3718 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
3719
3720 req = (struct hclge_set_fd_key_config_cmd *)desc.data;
3721 stage = &hdev->fd_cfg.key_cfg[stage_num];
3722 req->stage = stage_num;
3723 req->key_select = stage->key_sel;
3724 req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
3725 req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
3726 req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
3727 req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
3728 req->tuple_mask = cpu_to_le32(~stage->tuple_active);
3729 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
3730
3731 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3732 if (ret)
3733 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
3734
3735 return ret;
3736}
3737
3738static int hclge_init_fd_config(struct hclge_dev *hdev)
3739{
3740#define LOW_2_WORDS 0x03
3741 struct hclge_fd_key_cfg *key_cfg;
3742 int ret;
3743
3744 if (!hnae3_dev_fd_supported(hdev))
3745 return 0;
3746
3747 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
3748 if (ret)
3749 return ret;
3750
3751 switch (hdev->fd_cfg.fd_mode) {
3752 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
3753 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
3754 break;
3755 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
3756 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
3757 break;
3758 default:
3759 dev_err(&hdev->pdev->dev,
3760 "Unsupported flow director mode %d\n",
3761 hdev->fd_cfg.fd_mode);
3762 return -EOPNOTSUPP;
3763 }
3764
3765 hdev->fd_cfg.fd_en = true;
3766 hdev->fd_cfg.proto_support =
3767 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW |
3768 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW;
3769 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
3770 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE,
3771 key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
3772 key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
3773 key_cfg->outer_sipv6_word_en = 0;
3774 key_cfg->outer_dipv6_word_en = 0;
3775
3776 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
3777 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
3778 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3779 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3780
3781 /* If use max 400bit key, we can support tuples for ether type */
3782 if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) {
3783 hdev->fd_cfg.proto_support |= ETHER_FLOW;
3784 key_cfg->tuple_active |=
3785 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
3786 }
3787
3788 /* roce_type is used to filter roce frames
3789 * dst_vport is used to specify the rule
3790 */
3791 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
3792
3793 ret = hclge_get_fd_allocation(hdev,
3794 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
3795 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
3796 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
3797 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
3798 if (ret)
3799 return ret;
3800
3801 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
3802}
3803
7b829126
JS		 3804static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
3805 int loc, u8 *key, bool is_add)
3806{
3807 struct hclge_fd_tcam_config_1_cmd *req1;
3808 struct hclge_fd_tcam_config_2_cmd *req2;
3809 struct hclge_fd_tcam_config_3_cmd *req3;
3810 struct hclge_desc desc[3];
3811 int ret;
3812
3813 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
3814 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3815 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
3816 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3817 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
3818
3819 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
3820 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
3821 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
3822
3823 req1->stage = stage;
3824 req1->xy_sel = sel_x ? 1 : 0;
3825 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
3826 req1->index = cpu_to_le32(loc);
3827 req1->entry_vld = sel_x ? is_add : 0;
3828
3829 if (key) {
3830 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
3831 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
3832 sizeof(req2->tcam_data));
3833 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
3834 sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
3835 }
3836
3837 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3838 if (ret)
3839 dev_err(&hdev->pdev->dev,
3840 "config tcam key fail, ret=%d\n",
3841 ret);
3842
3843 return ret;
3844}
3845
3846static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
3847 struct hclge_fd_ad_data *action)
3848{
3849 struct hclge_fd_ad_config_cmd *req;
3850 struct hclge_desc desc;
3851 u64 ad_data = 0;
3852 int ret;
3853
3854 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
3855
3856 req = (struct hclge_fd_ad_config_cmd *)desc.data;
3857 req->index = cpu_to_le32(loc);
3858 req->stage = stage;
3859
3860 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
3861 action->write_rule_id_to_bd);
3862 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
3863 action->rule_id);
3864 ad_data <<= 32;
3865 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
3866 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
3867 action->forward_to_direct_queue);
3868 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
3869 action->queue_id);
3870 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
3871 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
3872 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
3873 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
3874 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
3875 action->counter_id);
3876
3877 req->ad_data = cpu_to_le64(ad_data);
3878 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3879 if (ret)
3880 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
3881
3882 return ret;
3883}
3884
3885static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
3886 struct hclge_fd_rule *rule)
3887{
3888 u16 tmp_x_s, tmp_y_s;
3889 u32 tmp_x_l, tmp_y_l;
3890 int i;
3891
3892 if (rule->unused_tuple & tuple_bit)
3893 return true;
3894
3895 switch (tuple_bit) {
3896 case 0:
3897 return false;
3898 case BIT(INNER_DST_MAC):
3899 for (i = 0; i < 6; i++) {
3900 calc_x(key_x[5 - i], rule->tuples.dst_mac[i],
3901 rule->tuples_mask.dst_mac[i]);
3902 calc_y(key_y[5 - i], rule->tuples.dst_mac[i],
3903 rule->tuples_mask.dst_mac[i]);
3904 }
3905
3906 return true;
3907 case BIT(INNER_SRC_MAC):
3908 for (i = 0; i < 6; i++) {
3909 calc_x(key_x[5 - i], rule->tuples.src_mac[i],
3910 rule->tuples.src_mac[i]);
3911 calc_y(key_y[5 - i], rule->tuples.src_mac[i],
3912 rule->tuples.src_mac[i]);
3913 }
3914
3915 return true;
3916 case BIT(INNER_VLAN_TAG_FST):
3917 calc_x(tmp_x_s, rule->tuples.vlan_tag1,
3918 rule->tuples_mask.vlan_tag1);
3919 calc_y(tmp_y_s, rule->tuples.vlan_tag1,
3920 rule->tuples_mask.vlan_tag1);
3921 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3922 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3923
3924 return true;
3925 case BIT(INNER_ETH_TYPE):
3926 calc_x(tmp_x_s, rule->tuples.ether_proto,
3927 rule->tuples_mask.ether_proto);
3928 calc_y(tmp_y_s, rule->tuples.ether_proto,
3929 rule->tuples_mask.ether_proto);
3930 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3931 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3932
3933 return true;
3934 case BIT(INNER_IP_TOS):
3935 calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3936 calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3937
3938 return true;
3939 case BIT(INNER_IP_PROTO):
3940 calc_x(*key_x, rule->tuples.ip_proto,
3941 rule->tuples_mask.ip_proto);
3942 calc_y(*key_y, rule->tuples.ip_proto,
3943 rule->tuples_mask.ip_proto);
3944
3945 return true;
3946 case BIT(INNER_SRC_IP):
3947 calc_x(tmp_x_l, rule->tuples.src_ip[3],
3948 rule->tuples_mask.src_ip[3]);
3949 calc_y(tmp_y_l, rule->tuples.src_ip[3],
3950 rule->tuples_mask.src_ip[3]);
3951 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3952 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3953
3954 return true;
3955 case BIT(INNER_DST_IP):
3956 calc_x(tmp_x_l, rule->tuples.dst_ip[3],
3957 rule->tuples_mask.dst_ip[3]);
3958 calc_y(tmp_y_l, rule->tuples.dst_ip[3],
3959 rule->tuples_mask.dst_ip[3]);
3960 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3961 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3962
3963 return true;
3964 case BIT(INNER_SRC_PORT):
3965 calc_x(tmp_x_s, rule->tuples.src_port,
3966 rule->tuples_mask.src_port);
3967 calc_y(tmp_y_s, rule->tuples.src_port,
3968 rule->tuples_mask.src_port);
3969 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3970 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3971
3972 return true;
3973 case BIT(INNER_DST_PORT):
3974 calc_x(tmp_x_s, rule->tuples.dst_port,
3975 rule->tuples_mask.dst_port);
3976 calc_y(tmp_y_s, rule->tuples.dst_port,
3977 rule->tuples_mask.dst_port);
3978 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3979 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3980
3981 return true;
3982 default:
3983 return false;
3984 }
3985}
3986
3987static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
3988 u8 vf_id, u8 network_port_id)
3989{
3990 u32 port_number = 0;
3991
3992 if (port_type == HOST_PORT) {
3993 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
3994 pf_id);
3995 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
3996 vf_id);
3997 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
3998 } else {
3999 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
4000 HCLGE_NETWORK_PORT_ID_S, network_port_id);
4001 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
4002 }
4003
4004 return port_number;
4005}
4006
4007static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
4008 __le32 *key_x, __le32 *key_y,
4009 struct hclge_fd_rule *rule)
4010{
4011 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
4012 u8 cur_pos = 0, tuple_size, shift_bits;
4013 int i;
4014
4015 for (i = 0; i < MAX_META_DATA; i++) {
4016 tuple_size = meta_data_key_info[i].key_length;
4017 tuple_bit = key_cfg->meta_data_active & BIT(i);
4018
4019 switch (tuple_bit) {
4020 case BIT(ROCE_TYPE):
4021 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
4022 cur_pos += tuple_size;
4023 break;
4024 case BIT(DST_VPORT):
4025 port_number = hclge_get_port_number(HOST_PORT, 0,
4026 rule->vf_id, 0);
4027 hnae3_set_field(meta_data,
4028 GENMASK(cur_pos + tuple_size, cur_pos),
4029 cur_pos, port_number);
4030 cur_pos += tuple_size;
4031 break;
4032 default:
4033 break;
4034 }
4035 }
4036
4037 calc_x(tmp_x, meta_data, 0xFFFFFFFF);
4038 calc_y(tmp_y, meta_data, 0xFFFFFFFF);
4039 shift_bits = sizeof(meta_data) * 8 - cur_pos;
4040
4041 *key_x = cpu_to_le32(tmp_x << shift_bits);
4042 *key_y = cpu_to_le32(tmp_y << shift_bits);
4043}
4044
4045/* A complete key is combined with meta data key and tuple key.
4046 * Meta data key is stored at the MSB region, and tuple key is stored at
4047 * the LSB region, unused bits will be filled 0.
4048 */
4049static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
4050 struct hclge_fd_rule *rule)
4051{
4052 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
4053 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
4054 u8 *cur_key_x, *cur_key_y;
4055 int i, ret, tuple_size;
4056 u8 meta_data_region;
4057
4058 memset(key_x, 0, sizeof(key_x));
4059 memset(key_y, 0, sizeof(key_y));
4060 cur_key_x = key_x;
4061 cur_key_y = key_y;
4062
4063 for (i = 0 ; i < MAX_TUPLE; i++) {
4064 bool tuple_valid;
4065 u32 check_tuple;
4066
4067 tuple_size = tuple_key_info[i].key_length / 8;
4068 check_tuple = key_cfg->tuple_active & BIT(i);
4069
4070 tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
4071 cur_key_y, rule);
4072 if (tuple_valid) {
4073 cur_key_x += tuple_size;
4074 cur_key_y += tuple_size;
4075 }
4076 }
4077
4078 meta_data_region = hdev->fd_cfg.max_key_length / 8 -
4079 MAX_META_DATA_LENGTH / 8;
4080
4081 hclge_fd_convert_meta_data(key_cfg,
4082 (__le32 *)(key_x + meta_data_region),
4083 (__le32 *)(key_y + meta_data_region),
4084 rule);
4085
4086 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
4087 true);
4088 if (ret) {
4089 dev_err(&hdev->pdev->dev,
4090 "fd key_y config fail, loc=%d, ret=%d\n",
4091 rule->queue_id, ret);
4092 return ret;
4093 }
4094
4095 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
4096 true);
4097 if (ret)
4098 dev_err(&hdev->pdev->dev,
4099 "fd key_x config fail, loc=%d, ret=%d\n",
4100 rule->queue_id, ret);
4101 return ret;
4102}
4103
4104static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
4105 struct hclge_fd_rule *rule)
4106{
4107 struct hclge_fd_ad_data ad_data;
4108
4109 ad_data.ad_id = rule->location;
4110
4111 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4112 ad_data.drop_packet = true;
4113 ad_data.forward_to_direct_queue = false;
4114 ad_data.queue_id = 0;
4115 } else {
4116 ad_data.drop_packet = false;
4117 ad_data.forward_to_direct_queue = true;
4118 ad_data.queue_id = rule->queue_id;
4119 }
4120
4121 ad_data.use_counter = false;
4122 ad_data.counter_id = 0;
4123
4124 ad_data.use_next_stage = false;
4125 ad_data.next_input_key = 0;
4126
4127 ad_data.write_rule_id_to_bd = true;
4128 ad_data.rule_id = rule->location;
4129
4130 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
4131}
4132
3ca8e27c
JS		 4133static int hclge_fd_check_spec(struct hclge_dev *hdev,
4134 struct ethtool_rx_flow_spec *fs, u32 *unused)
4135{
4136 struct ethtool_tcpip4_spec *tcp_ip4_spec;
4137 struct ethtool_usrip4_spec *usr_ip4_spec;
4138 struct ethtool_tcpip6_spec *tcp_ip6_spec;
4139 struct ethtool_usrip6_spec *usr_ip6_spec;
4140 struct ethhdr *ether_spec;
4141
4142 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4143 return -EINVAL;
4144
4145 if (!(fs->flow_type & hdev->fd_cfg.proto_support))
4146 return -EOPNOTSUPP;
4147
4148 if ((fs->flow_type & FLOW_EXT) &&
4149 (fs->h_ext.data[0] != 0 || fs->h_ext.data[1] != 0)) {
4150 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
4151 return -EOPNOTSUPP;
4152 }
4153
4154 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4155 case SCTP_V4_FLOW:
4156 case TCP_V4_FLOW:
4157 case UDP_V4_FLOW:
4158 tcp_ip4_spec = &fs->h_u.tcp_ip4_spec;
4159 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
4160
4161 if (!tcp_ip4_spec->ip4src)
4162 *unused |= BIT(INNER_SRC_IP);
4163
4164 if (!tcp_ip4_spec->ip4dst)
4165 *unused |= BIT(INNER_DST_IP);
4166
4167 if (!tcp_ip4_spec->psrc)
4168 *unused |= BIT(INNER_SRC_PORT);
4169
4170 if (!tcp_ip4_spec->pdst)
4171 *unused |= BIT(INNER_DST_PORT);
4172
4173 if (!tcp_ip4_spec->tos)
4174 *unused |= BIT(INNER_IP_TOS);
4175
4176 break;
4177 case IP_USER_FLOW:
4178 usr_ip4_spec = &fs->h_u.usr_ip4_spec;
4179 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4180 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
4181
4182 if (!usr_ip4_spec->ip4src)
4183 *unused |= BIT(INNER_SRC_IP);
4184
4185 if (!usr_ip4_spec->ip4dst)
4186 *unused |= BIT(INNER_DST_IP);
4187
4188 if (!usr_ip4_spec->tos)
4189 *unused |= BIT(INNER_IP_TOS);
4190
4191 if (!usr_ip4_spec->proto)
4192 *unused |= BIT(INNER_IP_PROTO);
4193
4194 if (usr_ip4_spec->l4_4_bytes)
4195 return -EOPNOTSUPP;
4196
4197 if (usr_ip4_spec->ip_ver != ETH_RX_NFC_IP4)
4198 return -EOPNOTSUPP;
4199
4200 break;
4201 case SCTP_V6_FLOW:
4202 case TCP_V6_FLOW:
4203 case UDP_V6_FLOW:
4204 tcp_ip6_spec = &fs->h_u.tcp_ip6_spec;
4205 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4206 BIT(INNER_IP_TOS);
4207
4208 if (!tcp_ip6_spec->ip6src[0] && !tcp_ip6_spec->ip6src[1] &&
4209 !tcp_ip6_spec->ip6src[2] && !tcp_ip6_spec->ip6src[3])
4210 *unused |= BIT(INNER_SRC_IP);
4211
4212 if (!tcp_ip6_spec->ip6dst[0] && !tcp_ip6_spec->ip6dst[1] &&
4213 !tcp_ip6_spec->ip6dst[2] && !tcp_ip6_spec->ip6dst[3])
4214 *unused |= BIT(INNER_DST_IP);
4215
4216 if (!tcp_ip6_spec->psrc)
4217 *unused |= BIT(INNER_SRC_PORT);
4218
4219 if (!tcp_ip6_spec->pdst)
4220 *unused |= BIT(INNER_DST_PORT);
4221
4222 if (tcp_ip6_spec->tclass)
4223 return -EOPNOTSUPP;
4224
4225 break;
4226 case IPV6_USER_FLOW:
4227 usr_ip6_spec = &fs->h_u.usr_ip6_spec;
4228 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4229 BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) |
4230 BIT(INNER_DST_PORT);
4231
4232 if (!usr_ip6_spec->ip6src[0] && !usr_ip6_spec->ip6src[1] &&
4233 !usr_ip6_spec->ip6src[2] && !usr_ip6_spec->ip6src[3])
4234 *unused |= BIT(INNER_SRC_IP);
4235
4236 if (!usr_ip6_spec->ip6dst[0] && !usr_ip6_spec->ip6dst[1] &&
4237 !usr_ip6_spec->ip6dst[2] && !usr_ip6_spec->ip6dst[3])
4238 *unused |= BIT(INNER_DST_IP);
4239
4240 if (!usr_ip6_spec->l4_proto)
4241 *unused |= BIT(INNER_IP_PROTO);
4242
4243 if (usr_ip6_spec->tclass)
4244 return -EOPNOTSUPP;
4245
4246 if (usr_ip6_spec->l4_4_bytes)
4247 return -EOPNOTSUPP;
4248
4249 break;
4250 case ETHER_FLOW:
4251 ether_spec = &fs->h_u.ether_spec;
4252 *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
4253 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
4254 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
4255
4256 if (is_zero_ether_addr(ether_spec->h_source))
4257 *unused |= BIT(INNER_SRC_MAC);
4258
4259 if (is_zero_ether_addr(ether_spec->h_dest))
4260 *unused |= BIT(INNER_DST_MAC);
4261
4262 if (!ether_spec->h_proto)
4263 *unused |= BIT(INNER_ETH_TYPE);
4264
4265 break;
4266 default:
4267 return -EOPNOTSUPP;
4268 }
4269
4270 if ((fs->flow_type & FLOW_EXT)) {
4271 if (fs->h_ext.vlan_etype)
4272 return -EOPNOTSUPP;
4273 if (!fs->h_ext.vlan_tci)
4274 *unused |= BIT(INNER_VLAN_TAG_FST);
4275
4276 if (fs->m_ext.vlan_tci) {
4277 if (be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID)
4278 return -EINVAL;
4279 }
4280 } else {
4281 *unused |= BIT(INNER_VLAN_TAG_FST);
4282 }
4283
4284 if (fs->flow_type & FLOW_MAC_EXT) {
4285 if (!(hdev->fd_cfg.proto_support & ETHER_FLOW))
4286 return -EOPNOTSUPP;
4287
4288 if (is_zero_ether_addr(fs->h_ext.h_dest))
4289 *unused |= BIT(INNER_DST_MAC);
4290 else
4291 *unused &= ~(BIT(INNER_DST_MAC));
4292 }
4293
4294 return 0;
4295}
4296
4297static bool hclge_fd_rule_exist(struct hclge_dev *hdev, u16 location)
4298{
4299 struct hclge_fd_rule *rule = NULL;
4300 struct hlist_node *node2;
4301
4302 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4303 if (rule->location >= location)
4304 break;
4305 }
4306
4307 return rule && rule->location == location;
4308}
4309
4310static int hclge_fd_update_rule_list(struct hclge_dev *hdev,
4311 struct hclge_fd_rule *new_rule,
4312 u16 location,
4313 bool is_add)
4314{
4315 struct hclge_fd_rule *rule = NULL, *parent = NULL;
4316 struct hlist_node *node2;
4317
4318 if (is_add && !new_rule)
4319 return -EINVAL;
4320
4321 hlist_for_each_entry_safe(rule, node2,
4322 &hdev->fd_rule_list, rule_node) {
4323 if (rule->location >= location)
4324 break;
4325 parent = rule;
4326 }
4327
4328 if (rule && rule->location == location) {
4329 hlist_del(&rule->rule_node);
4330 kfree(rule);
4331 hdev->hclge_fd_rule_num--;
4332
4333 if (!is_add)
4334 return 0;
4335
4336 } else if (!is_add) {
4337 dev_err(&hdev->pdev->dev,
4338 "delete fail, rule %d is inexistent\n",
4339 location);
4340 return -EINVAL;
4341 }
4342
4343 INIT_HLIST_NODE(&new_rule->rule_node);
4344
4345 if (parent)
4346 hlist_add_behind(&new_rule->rule_node, &parent->rule_node);
4347 else
4348 hlist_add_head(&new_rule->rule_node, &hdev->fd_rule_list);
4349
4350 hdev->hclge_fd_rule_num++;
4351
4352 return 0;
4353}
4354
4355static int hclge_fd_get_tuple(struct hclge_dev *hdev,
4356 struct ethtool_rx_flow_spec *fs,
4357 struct hclge_fd_rule *rule)
4358{
4359 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
4360
4361 switch (flow_type) {
4362 case SCTP_V4_FLOW:
4363 case TCP_V4_FLOW:
4364 case UDP_V4_FLOW:
4365 rule->tuples.src_ip[3] =
4366 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
4367 rule->tuples_mask.src_ip[3] =
4368 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
4369
4370 rule->tuples.dst_ip[3] =
4371 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
4372 rule->tuples_mask.dst_ip[3] =
4373 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
4374
4375 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
4376 rule->tuples_mask.src_port =
4377 be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
4378
4379 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
4380 rule->tuples_mask.dst_port =
4381 be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
4382
4383 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
4384 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
4385
4386 rule->tuples.ether_proto = ETH_P_IP;
4387 rule->tuples_mask.ether_proto = 0xFFFF;
4388
4389 break;
4390 case IP_USER_FLOW:
4391 rule->tuples.src_ip[3] =
4392 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
4393 rule->tuples_mask.src_ip[3] =
4394 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
4395
4396 rule->tuples.dst_ip[3] =
4397 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
4398 rule->tuples_mask.dst_ip[3] =
4399 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
4400
4401 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
4402 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
4403
4404 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
4405 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
4406
4407 rule->tuples.ether_proto = ETH_P_IP;
4408 rule->tuples_mask.ether_proto = 0xFFFF;
4409
4410 break;
4411 case SCTP_V6_FLOW:
4412 case TCP_V6_FLOW:
4413 case UDP_V6_FLOW:
4414 be32_to_cpu_array(rule->tuples.src_ip,
4415 fs->h_u.tcp_ip6_spec.ip6src, 4);
4416 be32_to_cpu_array(rule->tuples_mask.src_ip,
4417 fs->m_u.tcp_ip6_spec.ip6src, 4);
4418
4419 be32_to_cpu_array(rule->tuples.dst_ip,
4420 fs->h_u.tcp_ip6_spec.ip6dst, 4);
4421 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4422 fs->m_u.tcp_ip6_spec.ip6dst, 4);
4423
4424 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
4425 rule->tuples_mask.src_port =
4426 be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
4427
4428 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
4429 rule->tuples_mask.dst_port =
4430 be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
4431
4432 rule->tuples.ether_proto = ETH_P_IPV6;
4433 rule->tuples_mask.ether_proto = 0xFFFF;
4434
4435 break;
4436 case IPV6_USER_FLOW:
4437 be32_to_cpu_array(rule->tuples.src_ip,
4438 fs->h_u.usr_ip6_spec.ip6src, 4);
4439 be32_to_cpu_array(rule->tuples_mask.src_ip,
4440 fs->m_u.usr_ip6_spec.ip6src, 4);
4441
4442 be32_to_cpu_array(rule->tuples.dst_ip,
4443 fs->h_u.usr_ip6_spec.ip6dst, 4);
4444 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4445 fs->m_u.usr_ip6_spec.ip6dst, 4);
4446
4447 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
4448 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
4449
4450 rule->tuples.ether_proto = ETH_P_IPV6;
4451 rule->tuples_mask.ether_proto = 0xFFFF;
4452
4453 break;
4454 case ETHER_FLOW:
4455 ether_addr_copy(rule->tuples.src_mac,
4456 fs->h_u.ether_spec.h_source);
4457 ether_addr_copy(rule->tuples_mask.src_mac,
4458 fs->m_u.ether_spec.h_source);
4459
4460 ether_addr_copy(rule->tuples.dst_mac,
4461 fs->h_u.ether_spec.h_dest);
4462 ether_addr_copy(rule->tuples_mask.dst_mac,
4463 fs->m_u.ether_spec.h_dest);
4464
4465 rule->tuples.ether_proto =
4466 be16_to_cpu(fs->h_u.ether_spec.h_proto);
4467 rule->tuples_mask.ether_proto =
4468 be16_to_cpu(fs->m_u.ether_spec.h_proto);
4469
4470 break;
4471 default:
4472 return -EOPNOTSUPP;
4473 }
4474
4475 switch (flow_type) {
4476 case SCTP_V4_FLOW:
4477 case SCTP_V6_FLOW:
4478 rule->tuples.ip_proto = IPPROTO_SCTP;
4479 rule->tuples_mask.ip_proto = 0xFF;
4480 break;
4481 case TCP_V4_FLOW:
4482 case TCP_V6_FLOW:
4483 rule->tuples.ip_proto = IPPROTO_TCP;
4484 rule->tuples_mask.ip_proto = 0xFF;
4485 break;
4486 case UDP_V4_FLOW:
4487 case UDP_V6_FLOW:
4488 rule->tuples.ip_proto = IPPROTO_UDP;
4489 rule->tuples_mask.ip_proto = 0xFF;
4490 break;
4491 default:
4492 break;
4493 }
4494
4495 if ((fs->flow_type & FLOW_EXT)) {
4496 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
4497 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
4498 }
4499
4500 if (fs->flow_type & FLOW_MAC_EXT) {
4501 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
4502 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
4503 }
4504
4505 return 0;
4506}
4507
4508static int hclge_add_fd_entry(struct hnae3_handle *handle,
4509 struct ethtool_rxnfc *cmd)
4510{
4511 struct hclge_vport *vport = hclge_get_vport(handle);
4512 struct hclge_dev *hdev = vport->back;
4513 u16 dst_vport_id = 0, q_index = 0;
4514 struct ethtool_rx_flow_spec *fs;
4515 struct hclge_fd_rule *rule;
4516 u32 unused = 0;
4517 u8 action;
4518 int ret;
4519
4520 if (!hnae3_dev_fd_supported(hdev))
4521 return -EOPNOTSUPP;
4522
4523 if (!hdev->fd_cfg.fd_en) {
4524 dev_warn(&hdev->pdev->dev,
4525 "Please enable flow director first\n");
4526 return -EOPNOTSUPP;
4527 }
4528
4529 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4530
4531 ret = hclge_fd_check_spec(hdev, fs, &unused);
4532 if (ret) {
4533 dev_err(&hdev->pdev->dev, "Check fd spec failed\n");
4534 return ret;
4535 }
4536
4537 if (fs->ring_cookie == RX_CLS_FLOW_DISC) {
4538 action = HCLGE_FD_ACTION_DROP_PACKET;
4539 } else {
4540 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
4541 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
4542 u16 tqps;
4543
4544 dst_vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
4545 tqps = vf ? hdev->vport[vf].alloc_tqps : vport->alloc_tqps;
4546
4547 if (ring >= tqps) {
4548 dev_err(&hdev->pdev->dev,
4549 "Error: queue id (%d) > max tqp num (%d)\n",
4550 ring, tqps - 1);
4551 return -EINVAL;
4552 }
4553
4554 if (vf > hdev->num_req_vfs) {
4555 dev_err(&hdev->pdev->dev,
4556 "Error: vf id (%d) > max vf num (%d)\n",
4557 vf, hdev->num_req_vfs);
4558 return -EINVAL;
4559 }
4560
4561 action = HCLGE_FD_ACTION_ACCEPT_PACKET;
4562 q_index = ring;
4563 }
4564
4565 rule = kzalloc(sizeof(*rule), GFP_KERNEL);
4566 if (!rule)
4567 return -ENOMEM;
4568
4569 ret = hclge_fd_get_tuple(hdev, fs, rule);
4570 if (ret)
4571 goto free_rule;
4572
4573 rule->flow_type = fs->flow_type;
4574
4575 rule->location = fs->location;
4576 rule->unused_tuple = unused;
4577 rule->vf_id = dst_vport_id;
4578 rule->queue_id = q_index;
4579 rule->action = action;
4580
4581 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4582 if (ret)
4583 goto free_rule;
4584
4585 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4586 if (ret)
4587 goto free_rule;
4588
4589 ret = hclge_fd_update_rule_list(hdev, rule, fs->location, true);
4590 if (ret)
4591 goto free_rule;
4592
4593 return ret;
4594
4595free_rule:
4596 kfree(rule);
4597 return ret;
4598}
4599
4600static int hclge_del_fd_entry(struct hnae3_handle *handle,
4601 struct ethtool_rxnfc *cmd)
4602{
4603 struct hclge_vport *vport = hclge_get_vport(handle);
4604 struct hclge_dev *hdev = vport->back;
4605 struct ethtool_rx_flow_spec *fs;
4606 int ret;
4607
4608 if (!hnae3_dev_fd_supported(hdev))
4609 return -EOPNOTSUPP;
4610
4611 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4612
4613 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4614 return -EINVAL;
4615
4616 if (!hclge_fd_rule_exist(hdev, fs->location)) {
4617 dev_err(&hdev->pdev->dev,
4618 "Delete fail, rule %d is inexistent\n",
4619 fs->location);
4620 return -ENOENT;
4621 }
4622
4623 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4624 fs->location, NULL, false);
4625 if (ret)
4626 return ret;
4627
4628 return hclge_fd_update_rule_list(hdev, NULL, fs->location,
4629 false);
4630}
4631
7ce98982
JS		 4632static void hclge_del_all_fd_entries(struct hnae3_handle *handle,
4633 bool clear_list)
4634{
4635 struct hclge_vport *vport = hclge_get_vport(handle);
4636 struct hclge_dev *hdev = vport->back;
4637 struct hclge_fd_rule *rule;
4638 struct hlist_node *node;
4639
4640 if (!hnae3_dev_fd_supported(hdev))
4641 return;
4642
4643 if (clear_list) {
4644 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4645 rule_node) {
4646 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4647 rule->location, NULL, false);
4648 hlist_del(&rule->rule_node);
4649 kfree(rule);
4650 hdev->hclge_fd_rule_num--;
4651 }
4652 } else {
4653 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4654 rule_node)
4655 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4656 rule->location, NULL, false);
4657 }
4658}
4659
4660static int hclge_restore_fd_entries(struct hnae3_handle *handle)
4661{
4662 struct hclge_vport *vport = hclge_get_vport(handle);
4663 struct hclge_dev *hdev = vport->back;
4664 struct hclge_fd_rule *rule;
4665 struct hlist_node *node;
4666 int ret;
4667
1afdb53a
HT		 4668 /* Return ok here, because reset error handling will check this
4669 * return value. If error is returned here, the reset process will
4670 * fail.
4671 */
7ce98982 4672 if (!hnae3_dev_fd_supported(hdev))
1afdb53a 4673 return 0;
7ce98982
JS		 4674
4675 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
4676 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4677 if (!ret)
4678 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4679
4680 if (ret) {
4681 dev_warn(&hdev->pdev->dev,
4682 "Restore rule %d failed, remove it\n",
4683 rule->location);
4684 hlist_del(&rule->rule_node);
4685 kfree(rule);
4686 hdev->hclge_fd_rule_num--;
4687 }
4688 }
4689 return 0;
4690}
4691
295043a7
JS		 4692static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
4693 struct ethtool_rxnfc *cmd)
4694{
4695 struct hclge_vport *vport = hclge_get_vport(handle);
4696 struct hclge_dev *hdev = vport->back;
4697
4698 if (!hnae3_dev_fd_supported(hdev))
4699 return -EOPNOTSUPP;
4700
4701 cmd->rule_cnt = hdev->hclge_fd_rule_num;
4702 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4703
4704 return 0;
4705}
4706
4707static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
4708 struct ethtool_rxnfc *cmd)
4709{
4710 struct hclge_vport *vport = hclge_get_vport(handle);
4711 struct hclge_fd_rule *rule = NULL;
4712 struct hclge_dev *hdev = vport->back;
4713 struct ethtool_rx_flow_spec *fs;
4714 struct hlist_node *node2;
4715
4716 if (!hnae3_dev_fd_supported(hdev))
4717 return -EOPNOTSUPP;
4718
4719 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4720
4721 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4722 if (rule->location >= fs->location)
4723 break;
4724 }
4725
4726 if (!rule || fs->location != rule->location)
4727 return -ENOENT;
4728
4729 fs->flow_type = rule->flow_type;
4730 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4731 case SCTP_V4_FLOW:
4732 case TCP_V4_FLOW:
4733 case UDP_V4_FLOW:
4734 fs->h_u.tcp_ip4_spec.ip4src =
4735 cpu_to_be32(rule->tuples.src_ip[3]);
4736 fs->m_u.tcp_ip4_spec.ip4src =
4737 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4738 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4739
4740 fs->h_u.tcp_ip4_spec.ip4dst =
4741 cpu_to_be32(rule->tuples.dst_ip[3]);
4742 fs->m_u.tcp_ip4_spec.ip4dst =
4743 rule->unused_tuple & BIT(INNER_DST_IP) ?
4744 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4745
4746 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4747 fs->m_u.tcp_ip4_spec.psrc =
4748 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4749 0 : cpu_to_be16(rule->tuples_mask.src_port);
4750
4751 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4752 fs->m_u.tcp_ip4_spec.pdst =
4753 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4754 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4755
4756 fs->h_u.tcp_ip4_spec.tos = rule->tuples.ip_tos;
4757 fs->m_u.tcp_ip4_spec.tos =
4758 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4759 0 : rule->tuples_mask.ip_tos;
4760
4761 break;
4762 case IP_USER_FLOW:
4763 fs->h_u.usr_ip4_spec.ip4src =
4764 cpu_to_be32(rule->tuples.src_ip[3]);
4765 fs->m_u.tcp_ip4_spec.ip4src =
4766 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4767 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4768
4769 fs->h_u.usr_ip4_spec.ip4dst =
4770 cpu_to_be32(rule->tuples.dst_ip[3]);
4771 fs->m_u.usr_ip4_spec.ip4dst =
4772 rule->unused_tuple & BIT(INNER_DST_IP) ?
4773 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4774
4775 fs->h_u.usr_ip4_spec.tos = rule->tuples.ip_tos;
4776 fs->m_u.usr_ip4_spec.tos =
4777 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4778 0 : rule->tuples_mask.ip_tos;
4779
4780 fs->h_u.usr_ip4_spec.proto = rule->tuples.ip_proto;
4781 fs->m_u.usr_ip4_spec.proto =
4782 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4783 0 : rule->tuples_mask.ip_proto;
4784
4785 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
4786
4787 break;
4788 case SCTP_V6_FLOW:
4789 case TCP_V6_FLOW:
4790 case UDP_V6_FLOW:
4791 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6src,
4792 rule->tuples.src_ip, 4);
4793 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4794 memset(fs->m_u.tcp_ip6_spec.ip6src, 0, sizeof(int) * 4);
4795 else
4796 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6src,
4797 rule->tuples_mask.src_ip, 4);
4798
4799 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6dst,
4800 rule->tuples.dst_ip, 4);
4801 if (rule->unused_tuple & BIT(INNER_DST_IP))
4802 memset(fs->m_u.tcp_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4803 else
4804 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6dst,
4805 rule->tuples_mask.dst_ip, 4);
4806
4807 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4808 fs->m_u.tcp_ip6_spec.psrc =
4809 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4810 0 : cpu_to_be16(rule->tuples_mask.src_port);
4811
4812 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4813 fs->m_u.tcp_ip6_spec.pdst =
4814 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4815 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4816
4817 break;
4818 case IPV6_USER_FLOW:
4819 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6src,
4820 rule->tuples.src_ip, 4);
4821 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4822 memset(fs->m_u.usr_ip6_spec.ip6src, 0, sizeof(int) * 4);
4823 else
4824 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6src,
4825 rule->tuples_mask.src_ip, 4);
4826
4827 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6dst,
4828 rule->tuples.dst_ip, 4);
4829 if (rule->unused_tuple & BIT(INNER_DST_IP))
4830 memset(fs->m_u.usr_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4831 else
4832 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6dst,
4833 rule->tuples_mask.dst_ip, 4);
4834
4835 fs->h_u.usr_ip6_spec.l4_proto = rule->tuples.ip_proto;
4836 fs->m_u.usr_ip6_spec.l4_proto =
4837 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4838 0 : rule->tuples_mask.ip_proto;
4839
4840 break;
4841 case ETHER_FLOW:
4842 ether_addr_copy(fs->h_u.ether_spec.h_source,
4843 rule->tuples.src_mac);
4844 if (rule->unused_tuple & BIT(INNER_SRC_MAC))
4845 eth_zero_addr(fs->m_u.ether_spec.h_source);
4846 else
4847 ether_addr_copy(fs->m_u.ether_spec.h_source,
4848 rule->tuples_mask.src_mac);
4849
4850 ether_addr_copy(fs->h_u.ether_spec.h_dest,
4851 rule->tuples.dst_mac);
4852 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4853 eth_zero_addr(fs->m_u.ether_spec.h_dest);
4854 else
4855 ether_addr_copy(fs->m_u.ether_spec.h_dest,
4856 rule->tuples_mask.dst_mac);
4857
4858 fs->h_u.ether_spec.h_proto =
4859 cpu_to_be16(rule->tuples.ether_proto);
4860 fs->m_u.ether_spec.h_proto =
4861 rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
4862 0 : cpu_to_be16(rule->tuples_mask.ether_proto);
4863
4864 break;
4865 default:
4866 return -EOPNOTSUPP;
4867 }
4868
4869 if (fs->flow_type & FLOW_EXT) {
4870 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
4871 fs->m_ext.vlan_tci =
4872 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
4873 cpu_to_be16(VLAN_VID_MASK) :
4874 cpu_to_be16(rule->tuples_mask.vlan_tag1);
4875 }
4876
4877 if (fs->flow_type & FLOW_MAC_EXT) {
4878 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
4879 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4880 eth_zero_addr(fs->m_u.ether_spec.h_dest);
4881 else
4882 ether_addr_copy(fs->m_u.ether_spec.h_dest,
4883 rule->tuples_mask.dst_mac);
4884 }
4885
4886 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4887 fs->ring_cookie = RX_CLS_FLOW_DISC;
4888 } else {
4889 u64 vf_id;
4890
4891 fs->ring_cookie = rule->queue_id;
4892 vf_id = rule->vf_id;
4893 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
4894 fs->ring_cookie |= vf_id;
4895 }
4896
4897 return 0;
4898}
4899
4900static int hclge_get_all_rules(struct hnae3_handle *handle,
4901 struct ethtool_rxnfc *cmd, u32 *rule_locs)
4902{
4903 struct hclge_vport *vport = hclge_get_vport(handle);
4904 struct hclge_dev *hdev = vport->back;
4905 struct hclge_fd_rule *rule;
4906 struct hlist_node *node2;
4907 int cnt = 0;
4908
4909 if (!hnae3_dev_fd_supported(hdev))
4910 return -EOPNOTSUPP;
4911
4912 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4913
4914 hlist_for_each_entry_safe(rule, node2,
4915 &hdev->fd_rule_list, rule_node) {
4916 if (cnt == cmd->rule_cnt)
4917 return -EMSGSIZE;
4918
4919 rule_locs[cnt] = rule->location;
4920 cnt++;
4921 }
4922
4923 cmd->rule_cnt = cnt;
4924
4925 return 0;
4926}
4927
225c02eb
HT		 4928static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
4929{
4930 struct hclge_vport *vport = hclge_get_vport(handle);
4931 struct hclge_dev *hdev = vport->back;
4932
4933 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
4934 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
4935}
4936
4937static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
4938{
4939 struct hclge_vport *vport = hclge_get_vport(handle);
4940 struct hclge_dev *hdev = vport->back;
4941
4942 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4943}
4944
4945static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
4946{
4947 struct hclge_vport *vport = hclge_get_vport(handle);
4948 struct hclge_dev *hdev = vport->back;
4949
4950 return hdev->reset_count;
4951}
4952
d1f04a80
JS		 4953static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
4954{
4955 struct hclge_vport *vport = hclge_get_vport(handle);
4956 struct hclge_dev *hdev = vport->back;
4957
4958 hdev->fd_cfg.fd_en = enable;
4959 if (!enable)
4960 hclge_del_all_fd_entries(handle, false);
4961 else
4962 hclge_restore_fd_entries(handle);
4963}
4964
46a3df9f
S		 4965static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
4966{
4967 struct hclge_desc desc;
d44f9b63
YL		 4968 struct hclge_config_mac_mode_cmd *req =
4969 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 4970 u32 loop_en = 0;
46a3df9f
S		 4971 int ret;
4972
4973 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
ccc23ef3
PL		 4974 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
4975 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
4976 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
4977 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
4978 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
4979 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
4980 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
4981 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
4982 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
4983 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
4984 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
4985 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
4986 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
4987 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 4988 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 4989
4990 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4991 if (ret)
4992 dev_err(&hdev->pdev->dev,
4993 "mac enable fail, ret =%d.\n", ret);
4994}
4995
67b8c316 4996static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 4997{
c39c4d98 4998 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 4999 struct hclge_desc desc;
5000 u32 loop_en;
5001 int ret;
5002
e67d9ce9
YL		 5003 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
5004 /* 1 Read out the MAC mode config at first */
5005 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
5006 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5007 if (ret) {
5008 dev_err(&hdev->pdev->dev,
5009 "mac loopback get fail, ret =%d.\n", ret);
5010 return ret;
5011 }
c39c4d98 5012
e67d9ce9
YL		 5013 /* 2 Then setup the loopback flag */
5014 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
ccc23ef3 5015 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
3ebc5e0b
YL		 5016 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
5017 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
e67d9ce9
YL		 5018
5019 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 5020
e67d9ce9
YL		 5021 /* 3 Config mac work mode with loopback flag
5022 * and its original configure parameters
5023 */
5024 hclge_cmd_reuse_desc(&desc, false);
5025 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5026 if (ret)
5027 dev_err(&hdev->pdev->dev,
5028 "mac loopback set fail, ret =%d.\n", ret);
5029 return ret;
5030}
c39c4d98 5031
86957272
FL		 5032static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
5033 enum hnae3_loop loop_mode)
e006bb00
PL		 5034{
5035#define HCLGE_SERDES_RETRY_MS 10
5036#define HCLGE_SERDES_RETRY_NUM 100
5037 struct hclge_serdes_lb_cmd *req;
5038 struct hclge_desc desc;
5039 int ret, i = 0;
86957272 5040 u8 loop_mode_b;
e006bb00 5041
855f03fb 5042 req = (struct hclge_serdes_lb_cmd *)desc.data;
e006bb00
PL		 5043 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
5044
86957272
FL		 5045 switch (loop_mode) {
5046 case HNAE3_LOOP_SERIAL_SERDES:
5047 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
5048 break;
5049 case HNAE3_LOOP_PARALLEL_SERDES:
5050 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
5051 break;
5052 default:
5053 dev_err(&hdev->pdev->dev,
5054 "unsupported serdes loopback mode %d\n", loop_mode);
5055 return -ENOTSUPP;
5056 }
5057
e006bb00 5058 if (en) {
86957272
FL		 5059 req->enable = loop_mode_b;
5060 req->mask = loop_mode_b;
e006bb00 5061 } else {
86957272 5062 req->mask = loop_mode_b;
e006bb00
PL		 5063 }
5064
5065 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5066 if (ret) {
5067 dev_err(&hdev->pdev->dev,
5068 "serdes loopback set fail, ret = %d\n", ret);
5069 return ret;
5070 }
5071
5072 do {
5073 msleep(HCLGE_SERDES_RETRY_MS);
5074 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
5075 true);
5076 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5077 if (ret) {
5078 dev_err(&hdev->pdev->dev,
5079 "serdes loopback get, ret = %d\n", ret);
5080 return ret;
5081 }
5082 } while (++i < HCLGE_SERDES_RETRY_NUM &&
5083 !(req->result & HCLGE_CMD_SERDES_DONE_B));
5084
5085 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
5086 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
5087 return -EBUSY;
5088 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
5089 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
5090 return -EIO;
5091 }
5092
3ebc5e0b 5093 hclge_cfg_mac_mode(hdev, en);
e006bb00
PL		 5094 return 0;
5095}
5096
3ebc5e0b
YL		 5097static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
5098 int stream_id, bool enable)
5099{
5100 struct hclge_desc desc;
5101 struct hclge_cfg_com_tqp_queue_cmd *req =
5102 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
5103 int ret;
5104
5105 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
5106 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
5107 req->stream_id = cpu_to_le16(stream_id);
5108 req->enable |= enable << HCLGE_TQP_ENABLE_B;
5109
5110 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5111 if (ret)
5112 dev_err(&hdev->pdev->dev,
5113 "Tqp enable fail, status =%d.\n", ret);
5114 return ret;
5115}
5116
e67d9ce9
YL		 5117static int hclge_set_loopback(struct hnae3_handle *handle,
5118 enum hnae3_loop loop_mode, bool en)
5119{
5120 struct hclge_vport *vport = hclge_get_vport(handle);
5121 struct hclge_dev *hdev = vport->back;
3ebc5e0b 5122 int i, ret;
e67d9ce9
YL		 5123
5124 switch (loop_mode) {
67b8c316
FL		 5125 case HNAE3_LOOP_APP:
5126 ret = hclge_set_app_loopback(hdev, en);
c39c4d98 5127 break;
86957272
FL		 5128 case HNAE3_LOOP_SERIAL_SERDES:
5129 case HNAE3_LOOP_PARALLEL_SERDES:
5130 ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
e006bb00 5131 break;
c39c4d98
YL		 5132 default:
5133 ret = -ENOTSUPP;
5134 dev_err(&hdev->pdev->dev,
5135 "loop_mode %d is not supported\n", loop_mode);
5136 break;
5137 }
5138
3ebc5e0b
YL		 5139 for (i = 0; i < vport->alloc_tqps; i++) {
5140 ret = hclge_tqp_enable(hdev, i, 0, en);
5141 if (ret)
5142 return ret;
5143 }
46a3df9f 5144
3ebc5e0b 5145 return 0;
46a3df9f
S		 5146}
5147
5148static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
5149{
5150 struct hclge_vport *vport = hclge_get_vport(handle);
5151 struct hnae3_queue *queue;
5152 struct hclge_tqp *tqp;
5153 int i;
5154
5155 for (i = 0; i < vport->alloc_tqps; i++) {
5156 queue = handle->kinfo.tqp[i];
5157 tqp = container_of(queue, struct hclge_tqp, q);
5158 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
5159 }
5160}
5161
5162static int hclge_ae_start(struct hnae3_handle *handle)
5163{
5164 struct hclge_vport *vport = hclge_get_vport(handle);
5165 struct hclge_dev *hdev = vport->back;
46a3df9f 5166
46a3df9f
S		 5167 /* mac enable */
5168 hclge_cfg_mac_mode(hdev, true);
5169 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 5170 mod_timer(&hdev->service_timer, jiffies + HZ);
3ae84019 5171 hdev->hw.mac.link = 0;
46a3df9f 5172
f9637cc2
PL		 5173 /* reset tqp stats */
5174 hclge_reset_tqp_stats(handle);
5175
dda6b7d5 5176 hclge_mac_start_phy(hdev);
46a3df9f 5177
46a3df9f
S		 5178 return 0;
5179}
5180
5181static void hclge_ae_stop(struct hnae3_handle *handle)
5182{
5183 struct hclge_vport *vport = hclge_get_vport(handle);
5184 struct hclge_dev *hdev = vport->back;
46a3df9f 5185
4ee3e5a8
FL		 5186 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5187
f9637cc2
PL		 5188 del_timer_sync(&hdev->service_timer);
5189 cancel_work_sync(&hdev->service_task);
42b11ab7 5190 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
f9637cc2 5191
48ac80db
HT		 5192 /* If it is not PF reset, the firmware will disable the MAC,
5193 * so it only need to stop phy here.
5194 */
5195 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
5196 hdev->reset_type != HNAE3_FUNC_RESET) {
4486f5c9 5197 hclge_mac_stop_phy(hdev);
f9637cc2 5198 return;
4486f5c9 5199 }
f9637cc2 5200
46a3df9f
S		 5201 /* Mac disable */
5202 hclge_cfg_mac_mode(hdev, false);
5203
5204 hclge_mac_stop_phy(hdev);
5205
5206 /* reset tqp stats */
5207 hclge_reset_tqp_stats(handle);
b91fb71c
FL		 5208 del_timer_sync(&hdev->service_timer);
5209 cancel_work_sync(&hdev->service_task);
5210 hclge_update_link_status(hdev);
46a3df9f
S		 5211}
5212
5213static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
5214 u16 cmdq_resp, u8 resp_code,
5215 enum hclge_mac_vlan_tbl_opcode op)
5216{
5217 struct hclge_dev *hdev = vport->back;
5218 int return_status = -EIO;
5219
5220 if (cmdq_resp) {
5221 dev_err(&hdev->pdev->dev,
5222 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
5223 cmdq_resp);
5224 return -EIO;
5225 }
5226
5227 if (op == HCLGE_MAC_VLAN_ADD) {
5228 if ((!resp_code) || (resp_code == 1)) {
5229 return_status = 0;
5230 } else if (resp_code == 2) {
2f894c5b 5231 return_status = -ENOSPC;
46a3df9f
S		 5232 dev_err(&hdev->pdev->dev,
5233 "add mac addr failed for uc_overflow.\n");
5234 } else if (resp_code == 3) {
2f894c5b 5235 return_status = -ENOSPC;
46a3df9f
S		 5236 dev_err(&hdev->pdev->dev,
5237 "add mac addr failed for mc_overflow.\n");
5238 } else {
5239 dev_err(&hdev->pdev->dev,
5240 "add mac addr failed for undefined, code=%d.\n",
5241 resp_code);
5242 }
5243 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
5244 if (!resp_code) {
5245 return_status = 0;
5246 } else if (resp_code == 1) {
2f894c5b 5247 return_status = -ENOENT;
46a3df9f
S		 5248 dev_dbg(&hdev->pdev->dev,
5249 "remove mac addr failed for miss.\n");
5250 } else {
5251 dev_err(&hdev->pdev->dev,
5252 "remove mac addr failed for undefined, code=%d.\n",
5253 resp_code);
5254 }
5255 } else if (op == HCLGE_MAC_VLAN_LKUP) {
5256 if (!resp_code) {
5257 return_status = 0;
5258 } else if (resp_code == 1) {
2f894c5b 5259 return_status = -ENOENT;
46a3df9f
S		 5260 dev_dbg(&hdev->pdev->dev,
5261 "lookup mac addr failed for miss.\n");
5262 } else {
5263 dev_err(&hdev->pdev->dev,
5264 "lookup mac addr failed for undefined, code=%d.\n",
5265 resp_code);
5266 }
5267 } else {
2f894c5b 5268 return_status = -EINVAL;
46a3df9f
S		 5269 dev_err(&hdev->pdev->dev,
5270 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
5271 op);
5272 }
5273
5274 return return_status;
5275}
5276
5277static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
5278{
5279 int word_num;
5280 int bit_num;
5281
5282 if (vfid > 255 || vfid < 0)
5283 return -EIO;
5284
5285 if (vfid >= 0 && vfid <= 191) {
5286 word_num = vfid / 32;
5287 bit_num = vfid % 32;
5288 if (clr)
a90bb9a5 5289 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 5290 else
a90bb9a5 5291 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 5292 } else {
5293 word_num = (vfid - 192) / 32;
5294 bit_num = vfid % 32;
5295 if (clr)
a90bb9a5 5296 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 5297 else
a90bb9a5 5298 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 5299 }
5300
5301 return 0;
5302}
5303
5304static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
5305{
5306#define HCLGE_DESC_NUMBER 3
5307#define HCLGE_FUNC_NUMBER_PER_DESC 6
5308 int i, j;
5309
5310 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
5311 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
5312 if (desc[i].data[j])
5313 return false;
5314
5315 return true;
5316}
5317
d44f9b63 5318static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 5319 const u8 *addr)
5320{
5321 const unsigned char *mac_addr = addr;
5322 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
5323 (mac_addr[0]) | (mac_addr[1] << 8);
5324 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
5325
5326 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
5327 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
5328}
5329
46a3df9f 5330static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5331 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 5332{
5333 struct hclge_dev *hdev = vport->back;
5334 struct hclge_desc desc;
5335 u8 resp_code;
a90bb9a5 5336 u16 retval;
46a3df9f
S		 5337 int ret;
5338
5339 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
5340
d44f9b63 5341 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5342
5343 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5344 if (ret) {
5345 dev_err(&hdev->pdev->dev,
5346 "del mac addr failed for cmd_send, ret =%d.\n",
5347 ret);
5348 return ret;
5349 }
a90bb9a5
YL		 5350 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5351 retval = le16_to_cpu(desc.retval);
46a3df9f 5352
a90bb9a5 5353 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 5354 HCLGE_MAC_VLAN_REMOVE);
5355}
5356
5357static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5358 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 5359 struct hclge_desc *desc,
5360 bool is_mc)
5361{
5362 struct hclge_dev *hdev = vport->back;
5363 u8 resp_code;
a90bb9a5 5364 u16 retval;
46a3df9f
S		 5365 int ret;
5366
5367 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
5368 if (is_mc) {
5369 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5370 memcpy(desc[0].data,
5371 req,
d44f9b63 5372 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5373 hclge_cmd_setup_basic_desc(&desc[1],
5374 HCLGE_OPC_MAC_VLAN_ADD,
5375 true);
5376 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5377 hclge_cmd_setup_basic_desc(&desc[2],
5378 HCLGE_OPC_MAC_VLAN_ADD,
5379 true);
5380 ret = hclge_cmd_send(&hdev->hw, desc, 3);
5381 } else {
5382 memcpy(desc[0].data,
5383 req,
d44f9b63 5384 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5385 ret = hclge_cmd_send(&hdev->hw, desc, 1);
5386 }
5387 if (ret) {
5388 dev_err(&hdev->pdev->dev,
5389 "lookup mac addr failed for cmd_send, ret =%d.\n",
5390 ret);
5391 return ret;
5392 }
a90bb9a5
YL		 5393 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
5394 retval = le16_to_cpu(desc[0].retval);
46a3df9f 5395
a90bb9a5 5396 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 5397 HCLGE_MAC_VLAN_LKUP);
5398}
5399
5400static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5401 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 5402 struct hclge_desc *mc_desc)
5403{
5404 struct hclge_dev *hdev = vport->back;
5405 int cfg_status;
5406 u8 resp_code;
a90bb9a5 5407 u16 retval;
46a3df9f
S		 5408 int ret;
5409
5410 if (!mc_desc) {
5411 struct hclge_desc desc;
5412
5413 hclge_cmd_setup_basic_desc(&desc,
5414 HCLGE_OPC_MAC_VLAN_ADD,
5415 false);
d44f9b63
YL		 5416 memcpy(desc.data, req,
5417 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 5418 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 5419 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5420 retval = le16_to_cpu(desc.retval);
5421
5422 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 5423 resp_code,
5424 HCLGE_MAC_VLAN_ADD);
5425 } else {
c3b6f755 5426 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 5427 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 5428 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 5429 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 5430 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 5431 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
5432 memcpy(mc_desc[0].data, req,
d44f9b63 5433 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 5434 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 5435 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
5436 retval = le16_to_cpu(mc_desc[0].retval);
5437
5438 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 5439 resp_code,
5440 HCLGE_MAC_VLAN_ADD);
5441 }
5442
5443 if (ret) {
5444 dev_err(&hdev->pdev->dev,
5445 "add mac addr failed for cmd_send, ret =%d.\n",
5446 ret);
5447 return ret;
5448 }
5449
5450 return cfg_status;
5451}
5452
2da5ec58
JS		 5453static int hclge_init_umv_space(struct hclge_dev *hdev)
5454{
5455 u16 allocated_size = 0;
5456 int ret;
5457
5458 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size,
5459 true);
5460 if (ret)
5461 return ret;
5462
5463 if (allocated_size < hdev->wanted_umv_size)
5464 dev_warn(&hdev->pdev->dev,
5465 "Alloc umv space failed, want %d, get %d\n",
5466 hdev->wanted_umv_size, allocated_size);
5467
5468 mutex_init(&hdev->umv_mutex);
5469 hdev->max_umv_size = allocated_size;
5470 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_req_vfs + 2);
5471 hdev->share_umv_size = hdev->priv_umv_size +
5472 hdev->max_umv_size % (hdev->num_req_vfs + 2);
5473
5474 return 0;
5475}
5476
5477static int hclge_uninit_umv_space(struct hclge_dev *hdev)
5478{
5479 int ret;
5480
5481 if (hdev->max_umv_size > 0) {
5482 ret = hclge_set_umv_space(hdev, hdev->max_umv_size, NULL,
5483 false);
5484 if (ret)
5485 return ret;
5486 hdev->max_umv_size = 0;
5487 }
5488 mutex_destroy(&hdev->umv_mutex);
5489
5490 return 0;
5491}
5492
5493static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
5494 u16 *allocated_size, bool is_alloc)
5495{
5496 struct hclge_umv_spc_alc_cmd *req;
5497 struct hclge_desc desc;
5498 int ret;
5499
5500 req = (struct hclge_umv_spc_alc_cmd *)desc.data;
5501 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
5502 hnae3_set_bit(req->allocate, HCLGE_UMV_SPC_ALC_B, !is_alloc);
5503 req->space_size = cpu_to_le32(space_size);
5504
5505 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5506 if (ret) {
5507 dev_err(&hdev->pdev->dev,
5508 "%s umv space failed for cmd_send, ret =%d\n",
5509 is_alloc ? "allocate" : "free", ret);
5510 return ret;
5511 }
5512
5513 if (is_alloc && allocated_size)
5514 *allocated_size = le32_to_cpu(desc.data[1]);
5515
5516 return 0;
5517}
5518
5519static void hclge_reset_umv_space(struct hclge_dev *hdev)
5520{
5521 struct hclge_vport *vport;
5522 int i;
5523
5524 for (i = 0; i < hdev->num_alloc_vport; i++) {
5525 vport = &hdev->vport[i];
5526 vport->used_umv_num = 0;
5527 }
5528
5529 mutex_lock(&hdev->umv_mutex);
5530 hdev->share_umv_size = hdev->priv_umv_size +
5531 hdev->max_umv_size % (hdev->num_req_vfs + 2);
5532 mutex_unlock(&hdev->umv_mutex);
5533}
5534
5535static bool hclge_is_umv_space_full(struct hclge_vport *vport)
5536{
5537 struct hclge_dev *hdev = vport->back;
5538 bool is_full;
5539
5540 mutex_lock(&hdev->umv_mutex);
5541 is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
5542 hdev->share_umv_size == 0);
5543 mutex_unlock(&hdev->umv_mutex);
5544
5545 return is_full;
5546}
5547
5548static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
5549{
5550 struct hclge_dev *hdev = vport->back;
5551
5552 mutex_lock(&hdev->umv_mutex);
5553 if (is_free) {
5554 if (vport->used_umv_num > hdev->priv_umv_size)
5555 hdev->share_umv_size++;
5556 vport->used_umv_num--;
5557 } else {
5558 if (vport->used_umv_num >= hdev->priv_umv_size)
5559 hdev->share_umv_size--;
5560 vport->used_umv_num++;
5561 }
5562 mutex_unlock(&hdev->umv_mutex);
5563}
5564
46a3df9f
S		 5565static int hclge_add_uc_addr(struct hnae3_handle *handle,
5566 const unsigned char *addr)
5567{
5568 struct hclge_vport *vport = hclge_get_vport(handle);
5569
5570 return hclge_add_uc_addr_common(vport, addr);
5571}
5572
5573int hclge_add_uc_addr_common(struct hclge_vport *vport,
5574 const unsigned char *addr)
5575{
5576 struct hclge_dev *hdev = vport->back;
d44f9b63 5577 struct hclge_mac_vlan_tbl_entry_cmd req;
bf88f41f 5578 struct hclge_desc desc;
a90bb9a5 5579 u16 egress_port = 0;
04f0c72a 5580 int ret;
46a3df9f
S		 5581
5582 /* mac addr check */
5583 if (is_zero_ether_addr(addr) ||
5584 is_broadcast_ether_addr(addr) ||
5585 is_multicast_ether_addr(addr)) {
5586 dev_err(&hdev->pdev->dev,
5587 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
5588 addr,
5589 is_zero_ether_addr(addr),
5590 is_broadcast_ether_addr(addr),
5591 is_multicast_ether_addr(addr));
5592 return -EINVAL;
5593 }
5594
5595 memset(&req, 0, sizeof(req));
ccc23ef3 5596 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 5597
ccc23ef3
PL		 5598 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
5599 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 5600
5601 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 5602
5603 hclge_prepare_mac_addr(&req, addr);
5604
bf88f41f
JS		 5605 /* Lookup the mac address in the mac_vlan table, and add
5606 * it if the entry is inexistent. Repeated unicast entry
5607 * is not allowed in the mac vlan table.
5608 */
5609 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
2da5ec58
JS		 5610 if (ret == -ENOENT) {
5611 if (!hclge_is_umv_space_full(vport)) {
5612 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
5613 if (!ret)
5614 hclge_update_umv_space(vport, false);
5615 return ret;
5616 }
5617
5618 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
5619 hdev->priv_umv_size);
5620
5621 return -ENOSPC;
5622 }
bf88f41f
JS		 5623
5624 /* check if we just hit the duplicate */
5625 if (!ret)
5626 ret = -EINVAL;
5627
5628 dev_err(&hdev->pdev->dev,
5629 "PF failed to add unicast entry(%pM) in the MAC table\n",
5630 addr);
46a3df9f 5631
04f0c72a 5632 return ret;
46a3df9f
S		 5633}
5634
5635static int hclge_rm_uc_addr(struct hnae3_handle *handle,
5636 const unsigned char *addr)
5637{
5638 struct hclge_vport *vport = hclge_get_vport(handle);
5639
5640 return hclge_rm_uc_addr_common(vport, addr);
5641}
5642
5643int hclge_rm_uc_addr_common(struct hclge_vport *vport,
5644 const unsigned char *addr)
5645{
5646 struct hclge_dev *hdev = vport->back;
d44f9b63 5647 struct hclge_mac_vlan_tbl_entry_cmd req;
04f0c72a 5648 int ret;
46a3df9f
S		 5649
5650 /* mac addr check */
5651 if (is_zero_ether_addr(addr) ||
5652 is_broadcast_ether_addr(addr) ||
5653 is_multicast_ether_addr(addr)) {
5654 dev_dbg(&hdev->pdev->dev,
5655 "Remove mac err! invalid mac:%pM.\n",
5656 addr);
5657 return -EINVAL;
5658 }
5659
5660 memset(&req, 0, sizeof(req));
ccc23ef3
PL		 5661 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5662 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 5663 hclge_prepare_mac_addr(&req, addr);
04f0c72a 5664 ret = hclge_remove_mac_vlan_tbl(vport, &req);
2da5ec58
JS		 5665 if (!ret)
5666 hclge_update_umv_space(vport, true);
46a3df9f 5667
04f0c72a 5668 return ret;
46a3df9f
S		 5669}
5670
5671static int hclge_add_mc_addr(struct hnae3_handle *handle,
5672 const unsigned char *addr)
5673{
5674 struct hclge_vport *vport = hclge_get_vport(handle);
5675
2bf8098b 5676 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 5677}
5678
5679int hclge_add_mc_addr_common(struct hclge_vport *vport,
5680 const unsigned char *addr)
5681{
5682 struct hclge_dev *hdev = vport->back;
d44f9b63 5683 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 5684 struct hclge_desc desc[3];
46a3df9f
S		 5685 int status;
5686
5687 /* mac addr check */
5688 if (!is_multicast_ether_addr(addr)) {
5689 dev_err(&hdev->pdev->dev,
5690 "Add mc mac err! invalid mac:%pM.\n",
5691 addr);
5692 return -EINVAL;
5693 }
5694 memset(&req, 0, sizeof(req));
ccc23ef3
PL		 5695 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5696 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5697 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
738a3401 5698 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 5699 hclge_prepare_mac_addr(&req, addr);
5700 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5701 if (!status) {
5702 /* This mac addr exist, update VFID for it */
5703 hclge_update_desc_vfid(desc, vport->vport_id, false);
5704 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5705 } else {
5706 /* This mac addr do not exist, add new entry for it */
5707 memset(desc[0].data, 0, sizeof(desc[0].data));
5708 memset(desc[1].data, 0, sizeof(desc[0].data));
5709 memset(desc[2].data, 0, sizeof(desc[0].data));
5710 hclge_update_desc_vfid(desc, vport->vport_id, false);
5711 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5712 }
5713
55b049be
JS		 5714 if (status == -ENOSPC)
5715 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
46a3df9f
S		 5716
5717 return status;
5718}
5719
5720static int hclge_rm_mc_addr(struct hnae3_handle *handle,
5721 const unsigned char *addr)
5722{
5723 struct hclge_vport *vport = hclge_get_vport(handle);
5724
5725 return hclge_rm_mc_addr_common(vport, addr);
5726}
5727
5728int hclge_rm_mc_addr_common(struct hclge_vport *vport,
5729 const unsigned char *addr)
5730{
5731 struct hclge_dev *hdev = vport->back;
d44f9b63 5732 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 5733 enum hclge_cmd_status status;
5734 struct hclge_desc desc[3];
46a3df9f
S		 5735
5736 /* mac addr check */
5737 if (!is_multicast_ether_addr(addr)) {
5738 dev_dbg(&hdev->pdev->dev,
5739 "Remove mc mac err! invalid mac:%pM.\n",
5740 addr);
5741 return -EINVAL;
5742 }
5743
5744 memset(&req, 0, sizeof(req));
ccc23ef3
PL		 5745 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5746 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5747 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
738a3401 5748 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 5749 hclge_prepare_mac_addr(&req, addr);
5750 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5751 if (!status) {
5752 /* This mac addr exist, remove this handle's VFID for it */
5753 hclge_update_desc_vfid(desc, vport->vport_id, true);
5754
5755 if (hclge_is_all_function_id_zero(desc))
5756 /* All the vfid is zero, so need to delete this entry */
5757 status = hclge_remove_mac_vlan_tbl(vport, &req);
5758 else
5759 /* Not all the vfid is zero, update the vfid */
5760 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5761
5762 } else {
a832d8b5
XW		 5763 /* Maybe this mac address is in mta table, but it cannot be
5764 * deleted here because an entry of mta represents an address
5765 * range rather than a specific address. the delete action to
5766 * all entries will take effect in update_mta_status called by
5767 * hns3_nic_set_rx_mode.
5768 */
5769 status = 0;
46a3df9f
S		 5770 }
5771
46a3df9f
S		 5772 return status;
5773}
5774
635bfb58
FL		 5775static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
5776 u16 cmdq_resp, u8 resp_code)
5777{
5778#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
5779#define HCLGE_ETHERTYPE_ALREADY_ADD 1
5780#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
5781#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
5782
5783 int return_status;
5784
5785 if (cmdq_resp) {
5786 dev_err(&hdev->pdev->dev,
5787 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
5788 cmdq_resp);
5789 return -EIO;
5790 }
5791
5792 switch (resp_code) {
5793 case HCLGE_ETHERTYPE_SUCCESS_ADD:
5794 case HCLGE_ETHERTYPE_ALREADY_ADD:
5795 return_status = 0;
5796 break;
5797 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
5798 dev_err(&hdev->pdev->dev,
5799 "add mac ethertype failed for manager table overflow.\n");
5800 return_status = -EIO;
5801 break;
5802 case HCLGE_ETHERTYPE_KEY_CONFLICT:
5803 dev_err(&hdev->pdev->dev,
5804 "add mac ethertype failed for key conflict.\n");
5805 return_status = -EIO;
5806 break;
5807 default:
5808 dev_err(&hdev->pdev->dev,
5809 "add mac ethertype failed for undefined, code=%d.\n",
5810 resp_code);
5811 return_status = -EIO;
5812 }
5813
5814 return return_status;
5815}
5816
5817static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
5818 const struct hclge_mac_mgr_tbl_entry_cmd *req)
5819{
5820 struct hclge_desc desc;
5821 u8 resp_code;
5822 u16 retval;
5823 int ret;
5824
5825 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
5826 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
5827
5828 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5829 if (ret) {
5830 dev_err(&hdev->pdev->dev,
5831 "add mac ethertype failed for cmd_send, ret =%d.\n",
5832 ret);
5833 return ret;
5834 }
5835
5836 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5837 retval = le16_to_cpu(desc.retval);
5838
5839 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
5840}
5841
5842static int init_mgr_tbl(struct hclge_dev *hdev)
5843{
5844 int ret;
5845 int i;
5846
5847 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
5848 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
5849 if (ret) {
5850 dev_err(&hdev->pdev->dev,
5851 "add mac ethertype failed, ret =%d.\n",
5852 ret);
5853 return ret;
5854 }
5855 }
5856
5857 return 0;
5858}
5859
46a3df9f
S		 5860static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
5861{
5862 struct hclge_vport *vport = hclge_get_vport(handle);
5863 struct hclge_dev *hdev = vport->back;
5864
5865 ether_addr_copy(p, hdev->hw.mac.mac_addr);
5866}
5867
3cbf5e2d
FL		 5868static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
5869 bool is_first)
46a3df9f
S		 5870{
5871 const unsigned char *new_addr = (const unsigned char *)p;
5872 struct hclge_vport *vport = hclge_get_vport(handle);
5873 struct hclge_dev *hdev = vport->back;
20a5c4c0 5874 int ret;
46a3df9f
S		 5875
5876 /* mac addr check */
5877 if (is_zero_ether_addr(new_addr) ||
5878 is_broadcast_ether_addr(new_addr) ||
5879 is_multicast_ether_addr(new_addr)) {
5880 dev_err(&hdev->pdev->dev,
5881 "Change uc mac err! invalid mac:%p.\n",
5882 new_addr);
5883 return -EINVAL;
5884 }
5885
3cbf5e2d 5886 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 5887 dev_warn(&hdev->pdev->dev,
3cbf5e2d 5888 "remove old uc mac address fail.\n");
46a3df9f 5889
20a5c4c0
FL		 5890 ret = hclge_add_uc_addr(handle, new_addr);
5891 if (ret) {
5892 dev_err(&hdev->pdev->dev,
5893 "add uc mac address fail, ret =%d.\n",
5894 ret);
5895
3cbf5e2d
FL		 5896 if (!is_first &&
5897 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
20a5c4c0 5898 dev_err(&hdev->pdev->dev,
3cbf5e2d 5899 "restore uc mac address fail.\n");
20a5c4c0
FL		 5900
5901 return -EIO;
46a3df9f
S		 5902 }
5903
532fdd5e 5904 ret = hclge_pause_addr_cfg(hdev, new_addr);
20a5c4c0
FL		 5905 if (ret) {
5906 dev_err(&hdev->pdev->dev,
5907 "configure mac pause address fail, ret =%d.\n",
5908 ret);
5909 return -EIO;
5910 }
5911
5912 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
5913
5914 return 0;
46a3df9f
S		 5915}
5916
a185d723
XW		 5917static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
5918 int cmd)
5919{
5920 struct hclge_vport *vport = hclge_get_vport(handle);
5921 struct hclge_dev *hdev = vport->back;
5922
5923 if (!hdev->hw.mac.phydev)
5924 return -EOPNOTSUPP;
5925
5926 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
5927}
5928
46a3df9f 5929static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
0e44d430 5930 u8 fe_type, bool filter_en)
46a3df9f 5931{
d44f9b63 5932 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 5933 struct hclge_desc desc;
5934 int ret;
5935
5936 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
5937
d44f9b63 5938 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f 5939 req->vlan_type = vlan_type;
0e44d430 5940 req->vlan_fe = filter_en ? fe_type : 0;
46a3df9f
S		 5941
5942 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 5943 if (ret)
46a3df9f
S		 5944 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
5945 ret);
46a3df9f 5946
90415e85 5947 return ret;
46a3df9f
S		 5948}
5949
d818396d
JS		 5950#define HCLGE_FILTER_TYPE_VF 0
5951#define HCLGE_FILTER_TYPE_PORT 1
0e44d430
ZL		 5952#define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0)
5953#define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0)
5954#define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1)
5955#define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2)
5956#define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3)
5957#define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \
5958 | HCLGE_FILTER_FE_ROCE_EGRESS_B)
5959#define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \
5960 | HCLGE_FILTER_FE_ROCE_INGRESS_B)
d818396d
JS		 5961
5962static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
5963{
5964 struct hclge_vport *vport = hclge_get_vport(handle);
5965 struct hclge_dev *hdev = vport->back;
5966
0e44d430
ZL		 5967 if (hdev->pdev->revision >= 0x21) {
5968 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5969 HCLGE_FILTER_FE_EGRESS, enable);
5970 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
5971 HCLGE_FILTER_FE_INGRESS, enable);
5972 } else {
5973 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5974 HCLGE_FILTER_FE_EGRESS_V1_B, enable);
5975 }
1e3653db
JS		 5976 if (enable)
5977 handle->netdev_flags |= HNAE3_VLAN_FLTR;
5978 else
5979 handle->netdev_flags &= ~HNAE3_VLAN_FLTR;
d818396d
JS		 5980}
5981
4e66632d
YL		 5982static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
5983 bool is_kill, u16 vlan, u8 qos,
5984 __be16 proto)
46a3df9f
S		 5985{
5986#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 5987 struct hclge_vlan_filter_vf_cfg_cmd *req0;
5988 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 5989 struct hclge_desc desc[2];
5990 u8 vf_byte_val;
5991 u8 vf_byte_off;
5992 int ret;
5993
5994 hclge_cmd_setup_basic_desc(&desc[0],
5995 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
5996 hclge_cmd_setup_basic_desc(&desc[1],
5997 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
5998
5999 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
6000
6001 vf_byte_off = vfid / 8;
6002 vf_byte_val = 1 << (vfid % 8);
6003
d44f9b63
YL		 6004 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
6005 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 6006
a90bb9a5 6007 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 6008 req0->vlan_cfg = is_kill;
6009
6010 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
6011 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
6012 else
6013 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
6014
6015 ret = hclge_cmd_send(&hdev->hw, desc, 2);
6016 if (ret) {
6017 dev_err(&hdev->pdev->dev,
6018 "Send vf vlan command fail, ret =%d.\n",
6019 ret);
6020 return ret;
6021 }
6022
6023 if (!is_kill) {
715d610d 6024#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 6025 if (!req0->resp_code || req0->resp_code == 1)
6026 return 0;
6027
715d610d
YL		 6028 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
6029 dev_warn(&hdev->pdev->dev,
6030 "vf vlan table is full, vf vlan filter is disabled\n");
6031 return 0;
6032 }
6033
46a3df9f
S		 6034 dev_err(&hdev->pdev->dev,
6035 "Add vf vlan filter fail, ret =%d.\n",
6036 req0->resp_code);
6037 } else {
29d3a843 6038#define HCLGE_VF_VLAN_DEL_NO_FOUND 1
46a3df9f
S		 6039 if (!req0->resp_code)
6040 return 0;
6041
29d3a843
YL		 6042 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
6043 dev_warn(&hdev->pdev->dev,
6044 "vlan %d filter is not in vf vlan table\n",
6045 vlan);
6046 return 0;
6047 }
6048
46a3df9f
S		 6049 dev_err(&hdev->pdev->dev,
6050 "Kill vf vlan filter fail, ret =%d.\n",
6051 req0->resp_code);
6052 }
6053
6054 return -EIO;
6055}
6056
4e66632d
YL		 6057static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
6058 u16 vlan_id, bool is_kill)
46a3df9f 6059{
d44f9b63 6060 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 6061 struct hclge_desc desc;
6062 u8 vlan_offset_byte_val;
6063 u8 vlan_offset_byte;
6064 u8 vlan_offset_160;
6065 int ret;
6066
6067 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
6068
6069 vlan_offset_160 = vlan_id / 160;
6070 vlan_offset_byte = (vlan_id % 160) / 8;
6071 vlan_offset_byte_val = 1 << (vlan_id % 8);
6072
d44f9b63 6073 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 6074 req->vlan_offset = vlan_offset_160;
6075 req->vlan_cfg = is_kill;
6076 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
6077
6078 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4e66632d
YL		 6079 if (ret)
6080 dev_err(&hdev->pdev->dev,
6081 "port vlan command, send fail, ret =%d.\n", ret);
6082 return ret;
6083}
6084
6085static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
6086 u16 vport_id, u16 vlan_id, u8 qos,
6087 bool is_kill)
6088{
6089 u16 vport_idx, vport_num = 0;
6090 int ret;
6091
4935129c
YL		 6092 if (is_kill && !vlan_id)
6093 return 0;
6094
4e66632d
YL		 6095 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
6096 0, proto);
46a3df9f
S		 6097 if (ret) {
6098 dev_err(&hdev->pdev->dev,
4e66632d
YL		 6099 "Set %d vport vlan filter config fail, ret =%d.\n",
6100 vport_id, ret);
46a3df9f
S		 6101 return ret;
6102 }
6103
4e66632d
YL		 6104 /* vlan 0 may be added twice when 8021q module is enabled */
6105 if (!is_kill && !vlan_id &&
6106 test_bit(vport_id, hdev->vlan_table[vlan_id]))
6107 return 0;
6108
6109 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 6110 dev_err(&hdev->pdev->dev,
4e66632d
YL		 6111 "Add port vlan failed, vport %d is already in vlan %d\n",
6112 vport_id, vlan_id);
6113 return -EINVAL;
46a3df9f
S		 6114 }
6115
4e66632d
YL		 6116 if (is_kill &&
6117 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
6118 dev_err(&hdev->pdev->dev,
6119 "Delete port vlan failed, vport %d is not in vlan %d\n",
6120 vport_id, vlan_id);
6121 return -EINVAL;
6122 }
6123
3c6d4f43 6124 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
4e66632d
YL		 6125 vport_num++;
6126
6127 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
6128 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
6129 is_kill);
6130
6131 return ret;
6132}
6133
6134int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
6135 u16 vlan_id, bool is_kill)
6136{
6137 struct hclge_vport *vport = hclge_get_vport(handle);
6138 struct hclge_dev *hdev = vport->back;
6139
6140 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
6141 0, is_kill);
46a3df9f
S		 6142}
6143
6144static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
6145 u16 vlan, u8 qos, __be16 proto)
6146{
6147 struct hclge_vport *vport = hclge_get_vport(handle);
6148 struct hclge_dev *hdev = vport->back;
6149
6150 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
6151 return -EINVAL;
6152 if (proto != htons(ETH_P_8021Q))
6153 return -EPROTONOSUPPORT;
6154
4e66632d 6155 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 6156}
6157
e62f2a6b
PL		 6158static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
6159{
6160 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
6161 struct hclge_vport_vtag_tx_cfg_cmd *req;
6162 struct hclge_dev *hdev = vport->back;
6163 struct hclge_desc desc;
6164 int status;
6165
6166 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
6167
6168 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
6169 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
6170 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
ccc23ef3
PL		 6171 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
6172 vcfg->accept_tag1 ? 1 : 0);
6173 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
6174 vcfg->accept_untag1 ? 1 : 0);
6175 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
6176 vcfg->accept_tag2 ? 1 : 0);
6177 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
6178 vcfg->accept_untag2 ? 1 : 0);
6179 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
6180 vcfg->insert_tag1_en ? 1 : 0);
6181 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
6182 vcfg->insert_tag2_en ? 1 : 0);
6183 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
e62f2a6b
PL		 6184
6185 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6186 req->vf_bitmap[req->vf_offset] =
6187 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6188
6189 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6190 if (status)
6191 dev_err(&hdev->pdev->dev,
6192 "Send port txvlan cfg command fail, ret =%d\n",
6193 status);
6194
6195 return status;
6196}
6197
6198static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
6199{
6200 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
6201 struct hclge_vport_vtag_rx_cfg_cmd *req;
6202 struct hclge_dev *hdev = vport->back;
6203 struct hclge_desc desc;
6204 int status;
6205
6206 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
6207
6208 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
ccc23ef3
PL		 6209 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
6210 vcfg->strip_tag1_en ? 1 : 0);
6211 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
6212 vcfg->strip_tag2_en ? 1 : 0);
6213 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
6214 vcfg->vlan1_vlan_prionly ? 1 : 0);
6215 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
6216 vcfg->vlan2_vlan_prionly ? 1 : 0);
e62f2a6b
PL		 6217
6218 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6219 req->vf_bitmap[req->vf_offset] =
6220 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6221
6222 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6223 if (status)
6224 dev_err(&hdev->pdev->dev,
6225 "Send port rxvlan cfg command fail, ret =%d\n",
6226 status);
6227
6228 return status;
6229}
6230
6231static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
6232{
6233 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
6234 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
6235 struct hclge_desc desc;
6236 int status;
6237
6238 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
6239 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
6240 rx_req->ot_fst_vlan_type =
6241 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
6242 rx_req->ot_sec_vlan_type =
6243 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
6244 rx_req->in_fst_vlan_type =
6245 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
6246 rx_req->in_sec_vlan_type =
6247 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
6248
6249 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6250 if (status) {
6251 dev_err(&hdev->pdev->dev,
6252 "Send rxvlan protocol type command fail, ret =%d\n",
6253 status);
6254 return status;
6255 }
6256
6257 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
6258
855f03fb 6259 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
e62f2a6b
PL		 6260 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
6261 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
6262
6263 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6264 if (status)
6265 dev_err(&hdev->pdev->dev,
6266 "Send txvlan protocol type command fail, ret =%d\n",
6267 status);
6268
6269 return status;
6270}
6271
46a3df9f
S		 6272static int hclge_init_vlan_config(struct hclge_dev *hdev)
6273{
e62f2a6b
PL		 6274#define HCLGE_DEF_VLAN_TYPE 0x8100
6275
1e3653db 6276 struct hnae3_handle *handle = &hdev->vport[0].nic;
e62f2a6b 6277 struct hclge_vport *vport;
46a3df9f 6278 int ret;
e62f2a6b
PL		 6279 int i;
6280
0e44d430
ZL		 6281 if (hdev->pdev->revision >= 0x21) {
6282 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6283 HCLGE_FILTER_FE_EGRESS, true);
6284 if (ret)
6285 return ret;
46a3df9f 6286
0e44d430
ZL		 6287 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
6288 HCLGE_FILTER_FE_INGRESS, true);
6289 if (ret)
6290 return ret;
6291 } else {
6292 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6293 HCLGE_FILTER_FE_EGRESS_V1_B,
6294 true);
6295 if (ret)
6296 return ret;
6297 }
46a3df9f 6298
1e3653db
JS		 6299 handle->netdev_flags |= HNAE3_VLAN_FLTR;
6300
e62f2a6b
PL		 6301 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6302 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6303 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6304 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6305 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
6306 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
6307
6308 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 6309 if (ret)
6310 return ret;
46a3df9f 6311
e62f2a6b
PL		 6312 for (i = 0; i < hdev->num_alloc_vport; i++) {
6313 vport = &hdev->vport[i];
b75b1a56
PL		 6314 vport->txvlan_cfg.accept_tag1 = true;
6315 vport->txvlan_cfg.accept_untag1 = true;
6316
6317 /* accept_tag2 and accept_untag2 are not supported on
6318 * pdev revision(0x20), new revision support them. The
6319 * value of this two fields will not return error when driver
6320 * send command to fireware in revision(0x20).
6321 * This two fields can not configured by user.
6322 */
6323 vport->txvlan_cfg.accept_tag2 = true;
6324 vport->txvlan_cfg.accept_untag2 = true;
6325
e62f2a6b
PL		 6326 vport->txvlan_cfg.insert_tag1_en = false;
6327 vport->txvlan_cfg.insert_tag2_en = false;
6328 vport->txvlan_cfg.default_tag1 = 0;
6329 vport->txvlan_cfg.default_tag2 = 0;
6330
6331 ret = hclge_set_vlan_tx_offload_cfg(vport);
6332 if (ret)
6333 return ret;
6334
6335 vport->rxvlan_cfg.strip_tag1_en = false;
6336 vport->rxvlan_cfg.strip_tag2_en = true;
6337 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6338 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6339
6340 ret = hclge_set_vlan_rx_offload_cfg(vport);
6341 if (ret)
6342 return ret;
6343 }
6344
4e66632d 6345 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 6346}
6347
3849d494 6348int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
5f9a7732
PL		 6349{
6350 struct hclge_vport *vport = hclge_get_vport(handle);
6351
6352 vport->rxvlan_cfg.strip_tag1_en = false;
6353 vport->rxvlan_cfg.strip_tag2_en = enable;
6354 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6355 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6356
6357 return hclge_set_vlan_rx_offload_cfg(vport);
6358}
6359
12341881 6360static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 6361{
d44f9b63 6362 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 6363 struct hclge_desc desc;
7393ed39 6364 int max_frm_size;
46a3df9f
S		 6365 int ret;
6366
bd975002 6367 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN;
7393ed39
FL		 6368
6369 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
6370 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 6371 return -EINVAL;
6372
7393ed39
FL		 6373 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
6374
46a3df9f
S		 6375 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
6376
d44f9b63 6377 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
7393ed39 6378 req->max_frm_size = cpu_to_le16(max_frm_size);
b86fdbf3 6379 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
46a3df9f
S		 6380
6381 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
90415e85 6382 if (ret)
46a3df9f 6383 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
90415e85
JS		 6384 else
6385 hdev->mps = max_frm_size;
930ff2f6 6386
90415e85 6387 return ret;
46a3df9f
S		 6388}
6389
12341881
FL		 6390static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
6391{
6392 struct hclge_vport *vport = hclge_get_vport(handle);
6393 struct hclge_dev *hdev = vport->back;
6394 int ret;
6395
6396 ret = hclge_set_mac_mtu(hdev, new_mtu);
6397 if (ret) {
6398 dev_err(&hdev->pdev->dev,
6399 "Change mtu fail, ret =%d\n", ret);
6400 return ret;
6401 }
6402
6403 ret = hclge_buffer_alloc(hdev);
6404 if (ret)
6405 dev_err(&hdev->pdev->dev,
6406 "Allocate buffer fail, ret =%d\n", ret);
6407
6408 return ret;
6409}
6410
46a3df9f
S		 6411static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
6412 bool enable)
6413{
d44f9b63 6414 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 6415 struct hclge_desc desc;
6416 int ret;
6417
6418 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
6419
d44f9b63 6420 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 6421 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
ccc23ef3 6422 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 6423
6424 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6425 if (ret) {
6426 dev_err(&hdev->pdev->dev,
6427 "Send tqp reset cmd error, status =%d\n", ret);
6428 return ret;
6429 }
6430
6431 return 0;
6432}
6433
6434static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
6435{
d44f9b63 6436 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 6437 struct hclge_desc desc;
6438 int ret;
6439
6440 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
6441
d44f9b63 6442 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 6443 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6444
6445 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6446 if (ret) {
6447 dev_err(&hdev->pdev->dev,
6448 "Get reset status error, status =%d\n", ret);
6449 return ret;
6450 }
6451
ccc23ef3 6452 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 6453}
6454
e5e89cda
PL		 6455static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
6456 u16 queue_id)
6457{
6458 struct hnae3_queue *queue;
6459 struct hclge_tqp *tqp;
6460
6461 queue = handle->kinfo.tqp[queue_id];
6462 tqp = container_of(queue, struct hclge_tqp, q);
6463
6464 return tqp->index;
6465}
6466
abe62a63 6467int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 6468{
6469 struct hclge_vport *vport = hclge_get_vport(handle);
6470 struct hclge_dev *hdev = vport->back;
6471 int reset_try_times = 0;
6472 int reset_status;
e5e89cda 6473 u16 queue_gid;
abe62a63 6474 int ret = 0;
46a3df9f 6475
e5e89cda
PL		 6476 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
6477
46a3df9f
S		 6478 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
6479 if (ret) {
abe62a63
HT		 6480 dev_err(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
6481 return ret;
46a3df9f
S		 6482 }
6483
e5e89cda 6484 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f 6485 if (ret) {
abe62a63
HT		 6486 dev_err(&hdev->pdev->dev,
6487 "Send reset tqp cmd fail, ret = %d\n", ret);
6488 return ret;
46a3df9f
S		 6489 }
6490
6491 reset_try_times = 0;
6492 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6493 /* Wait for tqp hw reset */
6494 msleep(20);
e5e89cda 6495 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 6496 if (reset_status)
6497 break;
6498 }
6499
6500 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
abe62a63
HT		 6501 dev_err(&hdev->pdev->dev, "Reset TQP fail\n");
6502 return ret;
46a3df9f
S		 6503 }
6504
e5e89cda 6505 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
abe62a63
HT		 6506 if (ret)
6507 dev_err(&hdev->pdev->dev,
6508 "Deassert the soft reset fail, ret = %d\n", ret);
6509
6510 return ret;
46a3df9f
S		 6511}
6512
d3ea7fc4
PL		 6513void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
6514{
6515 struct hclge_dev *hdev = vport->back;
6516 int reset_try_times = 0;
6517 int reset_status;
6518 u16 queue_gid;
6519 int ret;
6520
6521 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
6522
6523 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6524 if (ret) {
6525 dev_warn(&hdev->pdev->dev,
6526 "Send reset tqp cmd fail, ret = %d\n", ret);
6527 return;
6528 }
6529
6530 reset_try_times = 0;
6531 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6532 /* Wait for tqp hw reset */
6533 msleep(20);
6534 reset_status = hclge_get_reset_status(hdev, queue_gid);
6535 if (reset_status)
6536 break;
6537 }
6538
6539 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6540 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
6541 return;
6542 }
6543
6544 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6545 if (ret)
6546 dev_warn(&hdev->pdev->dev,
6547 "Deassert the soft reset fail, ret = %d\n", ret);
6548}
6549
46a3df9f
S		 6550static u32 hclge_get_fw_version(struct hnae3_handle *handle)
6551{
6552 struct hclge_vport *vport = hclge_get_vport(handle);
6553 struct hclge_dev *hdev = vport->back;
6554
6555 return hdev->fw_version;
6556}
6557
09ea401e
PL		 6558static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6559{
6560 struct phy_device *phydev = hdev->hw.mac.phydev;
6561
6562 if (!phydev)
6563 return;
6564
6565 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
6566
6567 if (rx_en)
6568 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
6569
6570 if (tx_en)
6571 phydev->advertising ^= ADVERTISED_Asym_Pause;
6572}
6573
6574static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6575{
09ea401e
PL		 6576 int ret;
6577
6578 if (rx_en && tx_en)
7a28a82a 6579 hdev->fc_mode_last_time = HCLGE_FC_FULL;
09ea401e 6580 else if (rx_en && !tx_en)
7a28a82a 6581 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
09ea401e 6582 else if (!rx_en && tx_en)
7a28a82a 6583 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
09ea401e 6584 else
7a28a82a 6585 hdev->fc_mode_last_time = HCLGE_FC_NONE;
09ea401e 6586
7a28a82a 6587 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
09ea401e 6588 return 0;
09ea401e
PL		 6589
6590 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
6591 if (ret) {
6592 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
6593 ret);
6594 return ret;
6595 }
6596
7a28a82a 6597 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
09ea401e
PL		 6598
6599 return 0;
6600}
6601
6282f2ea
PL		 6602int hclge_cfg_flowctrl(struct hclge_dev *hdev)
6603{
6604 struct phy_device *phydev = hdev->hw.mac.phydev;
6605 u16 remote_advertising = 0;
6606 u16 local_advertising = 0;
6607 u32 rx_pause, tx_pause;
6608 u8 flowctl;
6609
6610 if (!phydev->link || !phydev->autoneg)
6611 return 0;
6612
6613 if (phydev->advertising & ADVERTISED_Pause)
6614 local_advertising = ADVERTISE_PAUSE_CAP;
6615
6616 if (phydev->advertising & ADVERTISED_Asym_Pause)
6617 local_advertising |= ADVERTISE_PAUSE_ASYM;
6618
6619 if (phydev->pause)
6620 remote_advertising = LPA_PAUSE_CAP;
6621
6622 if (phydev->asym_pause)
6623 remote_advertising |= LPA_PAUSE_ASYM;
6624
6625 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
6626 remote_advertising);
6627 tx_pause = flowctl & FLOW_CTRL_TX;
6628 rx_pause = flowctl & FLOW_CTRL_RX;
6629
6630 if (phydev->duplex == HCLGE_MAC_HALF) {
6631 tx_pause = 0;
6632 rx_pause = 0;
6633 }
6634
6635 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
6636}
6637
46a3df9f
S		 6638static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
6639 u32 *rx_en, u32 *tx_en)
6640{
6641 struct hclge_vport *vport = hclge_get_vport(handle);
6642 struct hclge_dev *hdev = vport->back;
6643
6644 *auto_neg = hclge_get_autoneg(handle);
6645
6646 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6647 *rx_en = 0;
6648 *tx_en = 0;
6649 return;
6650 }
6651
6652 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
6653 *rx_en = 1;
6654 *tx_en = 0;
6655 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
6656 *tx_en = 1;
6657 *rx_en = 0;
6658 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
6659 *rx_en = 1;
6660 *tx_en = 1;
6661 } else {
6662 *rx_en = 0;
6663 *tx_en = 0;
6664 }
6665}
6666
09ea401e
PL		 6667static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
6668 u32 rx_en, u32 tx_en)
6669{
6670 struct hclge_vport *vport = hclge_get_vport(handle);
6671 struct hclge_dev *hdev = vport->back;
6672 struct phy_device *phydev = hdev->hw.mac.phydev;
6673 u32 fc_autoneg;
6674
09ea401e
PL		 6675 fc_autoneg = hclge_get_autoneg(handle);
6676 if (auto_neg != fc_autoneg) {
6677 dev_info(&hdev->pdev->dev,
6678 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
6679 return -EOPNOTSUPP;
6680 }
6681
6682 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6683 dev_info(&hdev->pdev->dev,
6684 "Priority flow control enabled. Cannot set link flow control.\n");
6685 return -EOPNOTSUPP;
6686 }
6687
6688 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
6689
6690 if (!fc_autoneg)
6691 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
6692
bef24782
FL		 6693 /* Only support flow control negotiation for netdev with
6694 * phy attached for now.
6695 */
6696 if (!phydev)
6697 return -EOPNOTSUPP;
6698
09ea401e
PL		 6699 return phy_start_aneg(phydev);
6700}
6701
46a3df9f
S		 6702static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
6703 u8 *auto_neg, u32 *speed, u8 *duplex)
6704{
6705 struct hclge_vport *vport = hclge_get_vport(handle);
6706 struct hclge_dev *hdev = vport->back;
6707
6708 if (speed)
6709 *speed = hdev->hw.mac.speed;
6710 if (duplex)
6711 *duplex = hdev->hw.mac.duplex;
6712 if (auto_neg)
6713 *auto_neg = hdev->hw.mac.autoneg;
6714}
6715
6716static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
6717{
6718 struct hclge_vport *vport = hclge_get_vport(handle);
6719 struct hclge_dev *hdev = vport->back;
6720
6721 if (media_type)
6722 *media_type = hdev->hw.mac.media_type;
6723}
6724
6725static void hclge_get_mdix_mode(struct hnae3_handle *handle,
6726 u8 *tp_mdix_ctrl, u8 *tp_mdix)
6727{
6728 struct hclge_vport *vport = hclge_get_vport(handle);
6729 struct hclge_dev *hdev = vport->back;
6730 struct phy_device *phydev = hdev->hw.mac.phydev;
6731 int mdix_ctrl, mdix, retval, is_resolved;
6732
6733 if (!phydev) {
6734 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6735 *tp_mdix = ETH_TP_MDI_INVALID;
6736 return;
6737 }
6738
6739 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
6740
6741 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
ccc23ef3
PL		 6742 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
6743 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 6744
6745 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
ccc23ef3
PL		 6746 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
6747 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 6748
6749 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
6750
6751 switch (mdix_ctrl) {
6752 case 0x0:
6753 *tp_mdix_ctrl = ETH_TP_MDI;
6754 break;
6755 case 0x1:
6756 *tp_mdix_ctrl = ETH_TP_MDI_X;
6757 break;
6758 case 0x3:
6759 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
6760 break;
6761 default:
6762 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6763 break;
6764 }
6765
6766 if (!is_resolved)
6767 *tp_mdix = ETH_TP_MDI_INVALID;
6768 else if (mdix)
6769 *tp_mdix = ETH_TP_MDI_X;
6770 else
6771 *tp_mdix = ETH_TP_MDI;
6772}
6773
dda6b7d5
FL		 6774static int hclge_init_instance_hw(struct hclge_dev *hdev)
6775{
6776 return hclge_mac_connect_phy(hdev);
6777}
6778
6779static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
6780{
6781 hclge_mac_disconnect_phy(hdev);
6782}
6783
46a3df9f
S		 6784static int hclge_init_client_instance(struct hnae3_client *client,
6785 struct hnae3_ae_dev *ae_dev)
6786{
6787 struct hclge_dev *hdev = ae_dev->priv;
6788 struct hclge_vport *vport;
6789 int i, ret;
6790
6791 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
6792 vport = &hdev->vport[i];
6793
6794 switch (client->type) {
6795 case HNAE3_CLIENT_KNIC:
6796
6797 hdev->nic_client = client;
6798 vport->nic.client = client;
6799 ret = client->ops->init_instance(&vport->nic);
6800 if (ret)
2f59de78 6801 goto clear_nic;
46a3df9f 6802
dda6b7d5
FL		 6803 ret = hclge_init_instance_hw(hdev);
6804 if (ret) {
6805 client->ops->uninit_instance(&vport->nic,
6806 0);
2f59de78 6807 goto clear_nic;
dda6b7d5
FL		 6808 }
6809
8ed41eeb
JS		 6810 hnae3_set_client_init_flag(client, ae_dev, 1);
6811
46a3df9f 6812 if (hdev->roce_client &&
e92a0843 6813 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 6814 struct hnae3_client *rc = hdev->roce_client;
6815
6816 ret = hclge_init_roce_base_info(vport);
6817 if (ret)
2f59de78 6818 goto clear_roce;
46a3df9f
S		 6819
6820 ret = rc->ops->init_instance(&vport->roce);
6821 if (ret)
2f59de78 6822 goto clear_roce;
8ed41eeb
JS		 6823
6824 hnae3_set_client_init_flag(hdev->roce_client,
6825 ae_dev, 1);
46a3df9f
S		 6826 }
6827
6828 break;
6829 case HNAE3_CLIENT_UNIC:
6830 hdev->nic_client = client;
6831 vport->nic.client = client;
6832
6833 ret = client->ops->init_instance(&vport->nic);
6834 if (ret)
2f59de78 6835 goto clear_nic;
46a3df9f 6836
8ed41eeb
JS		 6837 hnae3_set_client_init_flag(client, ae_dev, 1);
6838
46a3df9f
S		 6839 break;
6840 case HNAE3_CLIENT_ROCE:
e92a0843 6841 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 6842 hdev->roce_client = client;
6843 vport->roce.client = client;
6844 }
6845
3a46f34d 6846 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 6847 ret = hclge_init_roce_base_info(vport);
6848 if (ret)
2f59de78 6849 goto clear_roce;
46a3df9f
S		 6850
6851 ret = client->ops->init_instance(&vport->roce);
6852 if (ret)
2f59de78 6853 goto clear_roce;
8ed41eeb
JS		 6854
6855 hnae3_set_client_init_flag(client, ae_dev, 1);
46a3df9f 6856 }
085920ba
JS		 6857
6858 break;
6859 default:
6860 return -EINVAL;
46a3df9f
S		 6861 }
6862 }
6863
6864 return 0;
2f59de78
JS		 6865
6866clear_nic:
6867 hdev->nic_client = NULL;
6868 vport->nic.client = NULL;
6869 return ret;
6870clear_roce:
6871 hdev->roce_client = NULL;
6872 vport->roce.client = NULL;
6873 return ret;
46a3df9f
S		 6874}
6875
6876static void hclge_uninit_client_instance(struct hnae3_client *client,
6877 struct hnae3_ae_dev *ae_dev)
6878{
6879 struct hclge_dev *hdev = ae_dev->priv;
6880 struct hclge_vport *vport;
6881 int i;
6882
6883 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
6884 vport = &hdev->vport[i];
a17dcf3f 6885 if (hdev->roce_client) {
46a3df9f
S		 6886 hdev->roce_client->ops->uninit_instance(&vport->roce,
6887 0);
a17dcf3f
L		 6888 hdev->roce_client = NULL;
6889 vport->roce.client = NULL;
6890 }
46a3df9f
S		 6891 if (client->type == HNAE3_CLIENT_ROCE)
6892 return;
2f59de78 6893 if (hdev->nic_client && client->ops->uninit_instance) {
dda6b7d5 6894 hclge_uninit_instance_hw(hdev);
46a3df9f 6895 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 6896 hdev->nic_client = NULL;
6897 vport->nic.client = NULL;
6898 }
46a3df9f
S		 6899 }
6900}
6901
6902static int hclge_pci_init(struct hclge_dev *hdev)
6903{
6904 struct pci_dev *pdev = hdev->pdev;
6905 struct hclge_hw *hw;
6906 int ret;
6907
6908 ret = pci_enable_device(pdev);
6909 if (ret) {
6910 dev_err(&pdev->dev, "failed to enable PCI device\n");
6c46284e 6911 return ret;
46a3df9f
S		 6912 }
6913
6914 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6915 if (ret) {
6916 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
6917 if (ret) {
6918 dev_err(&pdev->dev,
6919 "can't set consistent PCI DMA");
6920 goto err_disable_device;
6921 }
6922 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
6923 }
6924
6925 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
6926 if (ret) {
6927 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
6928 goto err_disable_device;
6929 }
6930
6931 pci_set_master(pdev);
6932 hw = &hdev->hw;
46a3df9f
S		 6933 hw->io_base = pcim_iomap(pdev, 2, 0);
6934 if (!hw->io_base) {
6935 dev_err(&pdev->dev, "Can't map configuration register space\n");
6936 ret = -ENOMEM;
6937 goto err_clr_master;
6938 }
6939
709eb41a
L		 6940 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
6941
46a3df9f
S		 6942 return 0;
6943err_clr_master:
6944 pci_clear_master(pdev);
6945 pci_release_regions(pdev);
6946err_disable_device:
6947 pci_disable_device(pdev);
46a3df9f
S		 6948
6949 return ret;
6950}
6951
6952static void hclge_pci_uninit(struct hclge_dev *hdev)
6953{
6954 struct pci_dev *pdev = hdev->pdev;
6955
7d6d639b 6956 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 6957 pci_free_irq_vectors(pdev);
46a3df9f
S		 6958 pci_clear_master(pdev);
6959 pci_release_mem_regions(pdev);
6960 pci_disable_device(pdev);
6961}
6962
2ec3d9f0
PL		 6963static void hclge_state_init(struct hclge_dev *hdev)
6964{
6965 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
6966 set_bit(HCLGE_STATE_DOWN, &hdev->state);
6967 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
6968 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
6969 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
6970 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
6971}
6972
6973static void hclge_state_uninit(struct hclge_dev *hdev)
6974{
6975 set_bit(HCLGE_STATE_DOWN, &hdev->state);
6976
6977 if (hdev->service_timer.function)
6978 del_timer_sync(&hdev->service_timer);
1afdb53a
HT		 6979 if (hdev->reset_timer.function)
6980 del_timer_sync(&hdev->reset_timer);
2ec3d9f0
PL		 6981 if (hdev->service_task.func)
6982 cancel_work_sync(&hdev->service_task);
6983 if (hdev->rst_service_task.func)
6984 cancel_work_sync(&hdev->rst_service_task);
6985 if (hdev->mbx_service_task.func)
6986 cancel_work_sync(&hdev->mbx_service_task);
6987}
6988
26977990
HT		 6989static void hclge_flr_prepare(struct hnae3_ae_dev *ae_dev)
6990{
6991#define HCLGE_FLR_WAIT_MS 100
6992#define HCLGE_FLR_WAIT_CNT 50
6993 struct hclge_dev *hdev = ae_dev->priv;
6994 int cnt = 0;
6995
6996 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
6997 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state);
6998 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request);
6999 hclge_reset_event(hdev->pdev, NULL);
7000
7001 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) &&
7002 cnt++ < HCLGE_FLR_WAIT_CNT)
7003 msleep(HCLGE_FLR_WAIT_MS);
7004
7005 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state))
7006 dev_err(&hdev->pdev->dev,
7007 "flr wait down timeout: %d\n", cnt);
7008}
7009
7010static void hclge_flr_done(struct hnae3_ae_dev *ae_dev)
7011{
7012 struct hclge_dev *hdev = ae_dev->priv;
7013
7014 set_bit(HNAE3_FLR_DONE, &hdev->flr_state);
7015}
7016
46a3df9f
S		 7017static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
7018{
7019 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 7020 struct hclge_dev *hdev;
7021 int ret;
7022
7023 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
7024 if (!hdev) {
7025 ret = -ENOMEM;
e0027501 7026 goto out;
46a3df9f
S		 7027 }
7028
46a3df9f
S		 7029 hdev->pdev = pdev;
7030 hdev->ae_dev = ae_dev;
4ed340ab 7031 hdev->reset_type = HNAE3_NONE_RESET;
1a2f7bf2 7032 hdev->reset_level = HNAE3_FUNC_RESET;
46a3df9f
S		 7033 ae_dev->priv = hdev;
7034
46a3df9f
S		 7035 ret = hclge_pci_init(hdev);
7036 if (ret) {
7037 dev_err(&pdev->dev, "PCI init failed\n");
e0027501 7038 goto out;
46a3df9f
S		 7039 }
7040
3efb960f
L		 7041 /* Firmware command queue initialize */
7042 ret = hclge_cmd_queue_init(hdev);
7043 if (ret) {
7044 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
e0027501 7045 goto err_pci_uninit;
3efb960f
L		 7046 }
7047
7048 /* Firmware command initialize */
46a3df9f
S		 7049 ret = hclge_cmd_init(hdev);
7050 if (ret)
e0027501 7051 goto err_cmd_uninit;
46a3df9f
S		 7052
7053 ret = hclge_get_cap(hdev);
7054 if (ret) {
e00e2197
CIK		 7055 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
7056 ret);
e0027501 7057 goto err_cmd_uninit;
46a3df9f
S		 7058 }
7059
7060 ret = hclge_configure(hdev);
7061 if (ret) {
7062 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
e0027501 7063 goto err_cmd_uninit;
46a3df9f
S		 7064 }
7065
887c3820 7066 ret = hclge_init_msi(hdev);
46a3df9f 7067 if (ret) {
887c3820 7068 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
e0027501 7069 goto err_cmd_uninit;
46a3df9f
S		 7070 }
7071
466b0c00
L		 7072 ret = hclge_misc_irq_init(hdev);
7073 if (ret) {
7074 dev_err(&pdev->dev,
7075 "Misc IRQ(vector0) init error, ret = %d.\n",
7076 ret);
e0027501 7077 goto err_msi_uninit;
466b0c00
L		 7078 }
7079
46a3df9f
S		 7080 ret = hclge_alloc_tqps(hdev);
7081 if (ret) {
7082 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
e0027501 7083 goto err_msi_irq_uninit;
46a3df9f
S		 7084 }
7085
7086 ret = hclge_alloc_vport(hdev);
7087 if (ret) {
7088 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
e0027501 7089 goto err_msi_irq_uninit;
46a3df9f
S		 7090 }
7091
7df7dad6
L		 7092 ret = hclge_map_tqp(hdev);
7093 if (ret) {
7094 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
bc59f827 7095 goto err_msi_irq_uninit;
7df7dad6
L		 7096 }
7097
dea9a821
HT		 7098 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
7099 ret = hclge_mac_mdio_config(hdev);
7100 if (ret) {
7101 dev_err(&hdev->pdev->dev,
7102 "mdio config fail ret=%d\n", ret);
bc59f827 7103 goto err_msi_irq_uninit;
dea9a821 7104 }
cf9cca2d 7105 }
7106
2da5ec58
JS		 7107 ret = hclge_init_umv_space(hdev);
7108 if (ret) {
7109 dev_err(&pdev->dev, "umv space init error, ret=%d.\n", ret);
7110 goto err_msi_irq_uninit;
7111 }
7112
46a3df9f
S		 7113 ret = hclge_mac_init(hdev);
7114 if (ret) {
7115 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
e0027501 7116 goto err_mdiobus_unreg;
46a3df9f 7117 }
46a3df9f
S		 7118
7119 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7120 if (ret) {
7121 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
e0027501 7122 goto err_mdiobus_unreg;
46a3df9f
S		 7123 }
7124
73f88b00
PL		 7125 ret = hclge_config_gro(hdev, true);
7126 if (ret)
7127 goto err_mdiobus_unreg;
7128
46a3df9f
S		 7129 ret = hclge_init_vlan_config(hdev);
7130 if (ret) {
7131 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
e0027501 7132 goto err_mdiobus_unreg;
46a3df9f
S		 7133 }
7134
7135 ret = hclge_tm_schd_init(hdev);
7136 if (ret) {
7137 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
e0027501 7138 goto err_mdiobus_unreg;
68ece54e
YL		 7139 }
7140
8015bb74 7141 hclge_rss_init_cfg(hdev);
68ece54e
YL		 7142 ret = hclge_rss_init_hw(hdev);
7143 if (ret) {
7144 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
e0027501 7145 goto err_mdiobus_unreg;
46a3df9f
S		 7146 }
7147
635bfb58
FL		 7148 ret = init_mgr_tbl(hdev);
7149 if (ret) {
7150 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
e0027501 7151 goto err_mdiobus_unreg;
635bfb58
FL		 7152 }
7153
10a954bc
JS		 7154 ret = hclge_init_fd_config(hdev);
7155 if (ret) {
7156 dev_err(&pdev->dev,
7157 "fd table init fail, ret=%d\n", ret);
7158 goto err_mdiobus_unreg;
7159 }
7160
9f53588e
SJ		 7161 ret = hclge_hw_error_set_state(hdev, true);
7162 if (ret) {
7163 dev_err(&pdev->dev,
7164 "hw error interrupts enable failed, ret =%d\n", ret);
7165 goto err_mdiobus_unreg;
7166 }
7167
cacde272
YL		 7168 hclge_dcb_ops_set(hdev);
7169
d039ef68 7170 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
1afdb53a 7171 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
46a3df9f 7172 INIT_WORK(&hdev->service_task, hclge_service_task);
ed4a1bb8 7173 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
22fd3468 7174 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 7175
9ab4ad14
XW		 7176 hclge_clear_all_event_cause(hdev);
7177
466b0c00
L		 7178 /* Enable MISC vector(vector0) */
7179 hclge_enable_vector(&hdev->misc_vector, true);
7180
2ec3d9f0 7181 hclge_state_init(hdev);
1a2f7bf2 7182 hdev->last_reset_time = jiffies;
46a3df9f
S		 7183
7184 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
7185 return 0;
7186
e0027501
HT		 7187err_mdiobus_unreg:
7188 if (hdev->hw.mac.phydev)
7189 mdiobus_unregister(hdev->hw.mac.mdio_bus);
e0027501
HT		 7190err_msi_irq_uninit:
7191 hclge_misc_irq_uninit(hdev);
7192err_msi_uninit:
7193 pci_free_irq_vectors(pdev);
7194err_cmd_uninit:
7195 hclge_destroy_cmd_queue(&hdev->hw);
7196err_pci_uninit:
7d6d639b 7197 pcim_iounmap(pdev, hdev->hw.io_base);
e0027501 7198 pci_clear_master(pdev);
46a3df9f 7199 pci_release_regions(pdev);
e0027501 7200 pci_disable_device(pdev);
e0027501 7201out:
46a3df9f
S		 7202 return ret;
7203}
7204
c6dc5213 7205static void hclge_stats_clear(struct hclge_dev *hdev)
7206{
7207 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
7208}
7209
4ed340ab
L		 7210static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
7211{
7212 struct hclge_dev *hdev = ae_dev->priv;
7213 struct pci_dev *pdev = ae_dev->pdev;
7214 int ret;
7215
7216 set_bit(HCLGE_STATE_DOWN, &hdev->state);
7217
c6dc5213 7218 hclge_stats_clear(hdev);
4e66632d 7219 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 7220
4ed340ab
L		 7221 ret = hclge_cmd_init(hdev);
7222 if (ret) {
7223 dev_err(&pdev->dev, "Cmd queue init failed\n");
7224 return ret;
7225 }
7226
7227 ret = hclge_get_cap(hdev);
7228 if (ret) {
7229 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
7230 ret);
7231 return ret;
7232 }
7233
7234 ret = hclge_configure(hdev);
7235 if (ret) {
7236 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
7237 return ret;
7238 }
7239
7240 ret = hclge_map_tqp(hdev);
7241 if (ret) {
7242 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
7243 return ret;
7244 }
7245
2da5ec58
JS		 7246 hclge_reset_umv_space(hdev);
7247
4ed340ab
L		 7248 ret = hclge_mac_init(hdev);
7249 if (ret) {
7250 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
7251 return ret;
7252 }
7253
4ed340ab
L		 7254 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7255 if (ret) {
7256 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
7257 return ret;
7258 }
7259
73f88b00
PL		 7260 ret = hclge_config_gro(hdev, true);
7261 if (ret)
7262 return ret;
7263
4ed340ab
L		 7264 ret = hclge_init_vlan_config(hdev);
7265 if (ret) {
7266 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
7267 return ret;
7268 }
7269
d85f1ab5 7270 ret = hclge_tm_init_hw(hdev);
4ed340ab 7271 if (ret) {
d85f1ab5 7272 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 7273 return ret;
7274 }
7275
7276 ret = hclge_rss_init_hw(hdev);
7277 if (ret) {
7278 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
7279 return ret;
7280 }
7281
10a954bc
JS		 7282 ret = hclge_init_fd_config(hdev);
7283 if (ret) {
7284 dev_err(&pdev->dev,
7285 "fd table init fail, ret=%d\n", ret);
7286 return ret;
7287 }
7288
78807a3d
SJ		 7289 /* Re-enable the TM hw error interrupts because
7290 * they get disabled on core/global reset.
7291 */
7292 if (hclge_enable_tm_hw_error(hdev, true))
7293 dev_err(&pdev->dev, "failed to enable TM hw error interrupts\n");
7294
4ed340ab
L		 7295 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
7296 HCLGE_DRIVER_NAME);
7297
7298 return 0;
7299}
7300
46a3df9f
S		 7301static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
7302{
7303 struct hclge_dev *hdev = ae_dev->priv;
7304 struct hclge_mac *mac = &hdev->hw.mac;
7305
2ec3d9f0 7306 hclge_state_uninit(hdev);
46a3df9f
S		 7307
7308 if (mac->phydev)
7309 mdiobus_unregister(mac->mdio_bus);
7310
2da5ec58
JS		 7311 hclge_uninit_umv_space(hdev);
7312
466b0c00
L		 7313 /* Disable MISC vector(vector0) */
7314 hclge_enable_vector(&hdev->misc_vector, false);
9ab4ad14
XW		 7315 synchronize_irq(hdev->misc_vector.vector_irq);
7316
9f53588e 7317 hclge_hw_error_set_state(hdev, false);
46a3df9f 7318 hclge_destroy_cmd_queue(&hdev->hw);
202f2014 7319 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 7320 hclge_pci_uninit(hdev);
7321 ae_dev->priv = NULL;
7322}
7323
4f645a90
PL		 7324static u32 hclge_get_max_channels(struct hnae3_handle *handle)
7325{
7326 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
7327 struct hclge_vport *vport = hclge_get_vport(handle);
7328 struct hclge_dev *hdev = vport->back;
7329
7330 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
7331}
7332
7333static void hclge_get_channels(struct hnae3_handle *handle,
7334 struct ethtool_channels *ch)
7335{
7336 struct hclge_vport *vport = hclge_get_vport(handle);
7337
7338 ch->max_combined = hclge_get_max_channels(handle);
7339 ch->other_count = 1;
7340 ch->max_other = 1;
7341 ch->combined_count = vport->alloc_tqps;
7342}
7343
f1f779ce 7344static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
08ca3d58 7345 u16 *alloc_tqps, u16 *max_rss_size)
f1f779ce
PL		 7346{
7347 struct hclge_vport *vport = hclge_get_vport(handle);
7348 struct hclge_dev *hdev = vport->back;
f1f779ce 7349
08ca3d58 7350 *alloc_tqps = vport->alloc_tqps;
f1f779ce
PL		 7351 *max_rss_size = hdev->rss_size_max;
7352}
7353
7354static void hclge_release_tqp(struct hclge_vport *vport)
7355{
7356 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7357 struct hclge_dev *hdev = vport->back;
7358 int i;
7359
7360 for (i = 0; i < kinfo->num_tqps; i++) {
7361 struct hclge_tqp *tqp =
7362 container_of(kinfo->tqp[i], struct hclge_tqp, q);
7363
7364 tqp->q.handle = NULL;
7365 tqp->q.tqp_index = 0;
7366 tqp->alloced = false;
7367 }
7368
7369 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
7370 kinfo->tqp = NULL;
7371}
7372
7373static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
7374{
7375 struct hclge_vport *vport = hclge_get_vport(handle);
7376 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7377 struct hclge_dev *hdev = vport->back;
7378 int cur_rss_size = kinfo->rss_size;
7379 int cur_tqps = kinfo->num_tqps;
7380 u16 tc_offset[HCLGE_MAX_TC_NUM];
7381 u16 tc_valid[HCLGE_MAX_TC_NUM];
7382 u16 tc_size[HCLGE_MAX_TC_NUM];
7383 u16 roundup_size;
7384 u32 *rss_indir;
7385 int ret, i;
7386
f73c9107 7387 /* Free old tqps, and reallocate with new tqp number when nic setup */
f1f779ce
PL		 7388 hclge_release_tqp(vport);
7389
81356b1f 7390 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
f1f779ce
PL		 7391 if (ret) {
7392 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
7393 return ret;
7394 }
7395
7396 ret = hclge_map_tqp_to_vport(hdev, vport);
7397 if (ret) {
7398 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
7399 return ret;
7400 }
7401
7402 ret = hclge_tm_schd_init(hdev);
7403 if (ret) {
7404 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
7405 return ret;
7406 }
7407
7408 roundup_size = roundup_pow_of_two(kinfo->rss_size);
7409 roundup_size = ilog2(roundup_size);
7410 /* Set the RSS TC mode according to the new RSS size */
7411 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
7412 tc_valid[i] = 0;
7413
7414 if (!(hdev->hw_tc_map & BIT(i)))
7415 continue;
7416
7417 tc_valid[i] = 1;
7418 tc_size[i] = roundup_size;
7419 tc_offset[i] = kinfo->rss_size * i;
7420 }
7421 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
7422 if (ret)
7423 return ret;
7424
7425 /* Reinitializes the rss indirect table according to the new RSS size */
7426 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
7427 if (!rss_indir)
7428 return -ENOMEM;
7429
7430 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
7431 rss_indir[i] = i % kinfo->rss_size;
7432
7433 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
7434 if (ret)
7435 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
7436 ret);
7437
7438 kfree(rss_indir);
7439
7440 if (!ret)
7441 dev_info(&hdev->pdev->dev,
7442 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
7443 cur_rss_size, kinfo->rss_size,
7444 cur_tqps, kinfo->rss_size * kinfo->num_tc);
7445
7446 return ret;
7447}
7448
db2a3e43
FL		 7449static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
7450 u32 *regs_num_64_bit)
7451{
7452 struct hclge_desc desc;
7453 u32 total_num;
7454 int ret;
7455
7456 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
7457 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7458 if (ret) {
7459 dev_err(&hdev->pdev->dev,
7460 "Query register number cmd failed, ret = %d.\n", ret);
7461 return ret;
7462 }
7463
7464 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
7465 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
7466
7467 total_num = *regs_num_32_bit + *regs_num_64_bit;
7468 if (!total_num)
7469 return -EINVAL;
7470
7471 return 0;
7472}
7473
7474static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7475 void *data)
7476{
7477#define HCLGE_32_BIT_REG_RTN_DATANUM 8
7478
7479 struct hclge_desc *desc;
7480 u32 *reg_val = data;
7481 __le32 *desc_data;
7482 int cmd_num;
7483 int i, k, n;
7484 int ret;
7485
7486 if (regs_num == 0)
7487 return 0;
7488
7489 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
7490 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7491 if (!desc)
7492 return -ENOMEM;
7493
7494 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
7495 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7496 if (ret) {
7497 dev_err(&hdev->pdev->dev,
7498 "Query 32 bit register cmd failed, ret = %d.\n", ret);
7499 kfree(desc);
7500 return ret;
7501 }
7502
7503 for (i = 0; i < cmd_num; i++) {
7504 if (i == 0) {
7505 desc_data = (__le32 *)(&desc[i].data[0]);
7506 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
7507 } else {
7508 desc_data = (__le32 *)(&desc[i]);
7509 n = HCLGE_32_BIT_REG_RTN_DATANUM;
7510 }
7511 for (k = 0; k < n; k++) {
7512 *reg_val++ = le32_to_cpu(*desc_data++);
7513
7514 regs_num--;
7515 if (!regs_num)
7516 break;
7517 }
7518 }
7519
7520 kfree(desc);
7521 return 0;
7522}
7523
7524static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7525 void *data)
7526{
7527#define HCLGE_64_BIT_REG_RTN_DATANUM 4
7528
7529 struct hclge_desc *desc;
7530 u64 *reg_val = data;
7531 __le64 *desc_data;
7532 int cmd_num;
7533 int i, k, n;
7534 int ret;
7535
7536 if (regs_num == 0)
7537 return 0;
7538
7539 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
7540 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7541 if (!desc)
7542 return -ENOMEM;
7543
7544 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
7545 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7546 if (ret) {
7547 dev_err(&hdev->pdev->dev,
7548 "Query 64 bit register cmd failed, ret = %d.\n", ret);
7549 kfree(desc);
7550 return ret;
7551 }
7552
7553 for (i = 0; i < cmd_num; i++) {
7554 if (i == 0) {
7555 desc_data = (__le64 *)(&desc[i].data[0]);
7556 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
7557 } else {
7558 desc_data = (__le64 *)(&desc[i]);
7559 n = HCLGE_64_BIT_REG_RTN_DATANUM;
7560 }
7561 for (k = 0; k < n; k++) {
7562 *reg_val++ = le64_to_cpu(*desc_data++);
7563
7564 regs_num--;
7565 if (!regs_num)
7566 break;
7567 }
7568 }
7569
7570 kfree(desc);
7571 return 0;
7572}
7573
7574static int hclge_get_regs_len(struct hnae3_handle *handle)
7575{
7576 struct hclge_vport *vport = hclge_get_vport(handle);
7577 struct hclge_dev *hdev = vport->back;
7578 u32 regs_num_32_bit, regs_num_64_bit;
7579 int ret;
7580
7581 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7582 if (ret) {
7583 dev_err(&hdev->pdev->dev,
7584 "Get register number failed, ret = %d.\n", ret);
7585 return -EOPNOTSUPP;
7586 }
7587
7588 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
7589}
7590
7591static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
7592 void *data)
7593{
7594 struct hclge_vport *vport = hclge_get_vport(handle);
7595 struct hclge_dev *hdev = vport->back;
7596 u32 regs_num_32_bit, regs_num_64_bit;
7597 int ret;
7598
7599 *version = hdev->fw_version;
7600
7601 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7602 if (ret) {
7603 dev_err(&hdev->pdev->dev,
7604 "Get register number failed, ret = %d.\n", ret);
7605 return;
7606 }
7607
7608 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
7609 if (ret) {
7610 dev_err(&hdev->pdev->dev,
7611 "Get 32 bit register failed, ret = %d.\n", ret);
7612 return;
7613 }
7614
7615 data = (u32 *)data + regs_num_32_bit;
7616 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
7617 data);
7618 if (ret)
7619 dev_err(&hdev->pdev->dev,
7620 "Get 64 bit register failed, ret = %d.\n", ret);
7621}
7622
fe3a3e15 7623static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
d9a0884e
JS		 7624{
7625 struct hclge_set_led_state_cmd *req;
7626 struct hclge_desc desc;
7627 int ret;
7628
7629 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
7630
7631 req = (struct hclge_set_led_state_cmd *)desc.data;
ccc23ef3
PL		 7632 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
7633 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
d9a0884e
JS		 7634
7635 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7636 if (ret)
7637 dev_err(&hdev->pdev->dev,
7638 "Send set led state cmd error, ret =%d\n", ret);
7639
7640 return ret;
7641}
7642
7643enum hclge_led_status {
7644 HCLGE_LED_OFF,
7645 HCLGE_LED_ON,
7646 HCLGE_LED_NO_CHANGE = 0xFF,
7647};
7648
7649static int hclge_set_led_id(struct hnae3_handle *handle,
7650 enum ethtool_phys_id_state status)
7651{
d9a0884e
JS		 7652 struct hclge_vport *vport = hclge_get_vport(handle);
7653 struct hclge_dev *hdev = vport->back;
d9a0884e
JS		 7654
7655 switch (status) {
7656 case ETHTOOL_ID_ACTIVE:
fe3a3e15 7657 return hclge_set_led_status(hdev, HCLGE_LED_ON);
d9a0884e 7658 case ETHTOOL_ID_INACTIVE:
fe3a3e15 7659 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
d9a0884e 7660 default:
fe3a3e15 7661 return -EINVAL;
d9a0884e 7662 }
d9a0884e
JS		 7663}
7664
d92ceae9
FL		 7665static void hclge_get_link_mode(struct hnae3_handle *handle,
7666 unsigned long *supported,
7667 unsigned long *advertising)
7668{
7669 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
7670 struct hclge_vport *vport = hclge_get_vport(handle);
7671 struct hclge_dev *hdev = vport->back;
7672 unsigned int idx = 0;
7673
7674 for (; idx < size; idx++) {
7675 supported[idx] = hdev->hw.mac.supported[idx];
7676 advertising[idx] = hdev->hw.mac.advertising[idx];
7677 }
7678}
7679
46a3df9f
S		 7680static const struct hnae3_ae_ops hclge_ops = {
7681 .init_ae_dev = hclge_init_ae_dev,
7682 .uninit_ae_dev = hclge_uninit_ae_dev,
26977990
HT		 7683 .flr_prepare = hclge_flr_prepare,
7684 .flr_done = hclge_flr_done,
46a3df9f
S		 7685 .init_client_instance = hclge_init_client_instance,
7686 .uninit_client_instance = hclge_uninit_client_instance,
63d7e66f
SM		 7687 .map_ring_to_vector = hclge_map_ring_to_vector,
7688 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 7689 .get_vector = hclge_get_vector,
7412200c 7690 .put_vector = hclge_put_vector,
46a3df9f 7691 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 7692 .set_loopback = hclge_set_loopback,
46a3df9f
S		 7693 .start = hclge_ae_start,
7694 .stop = hclge_ae_stop,
7695 .get_status = hclge_get_status,
7696 .get_ksettings_an_result = hclge_get_ksettings_an_result,
7697 .update_speed_duplex_h = hclge_update_speed_duplex_h,
7698 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
7699 .get_media_type = hclge_get_media_type,
7700 .get_rss_key_size = hclge_get_rss_key_size,
7701 .get_rss_indir_size = hclge_get_rss_indir_size,
7702 .get_rss = hclge_get_rss,
7703 .set_rss = hclge_set_rss,
f7db940a 7704 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 7705 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 7706 .get_tc_size = hclge_get_tc_size,
7707 .get_mac_addr = hclge_get_mac_addr,
7708 .set_mac_addr = hclge_set_mac_addr,
a185d723 7709 .do_ioctl = hclge_do_ioctl,
46a3df9f
S		 7710 .add_uc_addr = hclge_add_uc_addr,
7711 .rm_uc_addr = hclge_rm_uc_addr,
7712 .add_mc_addr = hclge_add_mc_addr,
7713 .rm_mc_addr = hclge_rm_mc_addr,
7714 .set_autoneg = hclge_set_autoneg,
7715 .get_autoneg = hclge_get_autoneg,
7716 .get_pauseparam = hclge_get_pauseparam,
09ea401e 7717 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 7718 .set_mtu = hclge_set_mtu,
7719 .reset_queue = hclge_reset_tqp,
7720 .get_stats = hclge_get_stats,
7721 .update_stats = hclge_update_stats,
7722 .get_strings = hclge_get_strings,
7723 .get_sset_count = hclge_get_sset_count,
7724 .get_fw_version = hclge_get_fw_version,
7725 .get_mdix_mode = hclge_get_mdix_mode,
d818396d 7726 .enable_vlan_filter = hclge_enable_vlan_filter,
4e66632d 7727 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 7728 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5f9a7732 7729 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 7730 .reset_event = hclge_reset_event,
2c883d73 7731 .set_default_reset_request = hclge_set_def_reset_request,
f1f779ce
PL		 7732 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
7733 .set_channels = hclge_set_channels,
4f645a90 7734 .get_channels = hclge_get_channels,
db2a3e43
FL		 7735 .get_regs_len = hclge_get_regs_len,
7736 .get_regs = hclge_get_regs,
d9a0884e 7737 .set_led_id = hclge_set_led_id,
d92ceae9 7738 .get_link_mode = hclge_get_link_mode,
3ca8e27c
JS		 7739 .add_fd_entry = hclge_add_fd_entry,
7740 .del_fd_entry = hclge_del_fd_entry,
7ce98982 7741 .del_all_fd_entries = hclge_del_all_fd_entries,
295043a7
JS		 7742 .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
7743 .get_fd_rule_info = hclge_get_fd_rule_info,
7744 .get_fd_all_rules = hclge_get_all_rules,
7ce98982 7745 .restore_fd_rules = hclge_restore_fd_entries,
d1f04a80 7746 .enable_fd = hclge_enable_fd,
00bb612a 7747 .process_hw_error = hclge_process_ras_hw_error,
225c02eb
HT		 7748 .get_hw_reset_stat = hclge_get_hw_reset_stat,
7749 .ae_dev_resetting = hclge_ae_dev_resetting,
7750 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
46a3df9f
S		 7751};
7752
7753static struct hnae3_ae_algo ae_algo = {
7754 .ops = &hclge_ops,
46a3df9f
S		 7755 .pdev_id_table = ae_algo_pci_tbl,
7756};
7757
7758static int hclge_init(void)
7759{
7760 pr_info("%s is initializing\n", HCLGE_NAME);
7761
a4d090cc
FL		 7762 hnae3_register_ae_algo(&ae_algo);
7763
7764 return 0;
46a3df9f
S		 7765}
7766
7767static void hclge_exit(void)
7768{
7769 hnae3_unregister_ae_algo(&ae_algo);
7770}
7771module_init(hclge_init);
7772module_exit(hclge_exit);
7773
7774MODULE_LICENSE("GPL");
7775MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
7776MODULE_DESCRIPTION("HCLGE Driver");
7777MODULE_VERSION(HCLGE_MOD_VERSION);
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