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net: hns3: add ethtool -p support for fiber port
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
7393ed39 20#include <linux/if_vlan.h>
d5752031 21#include <net/rtnetlink.h>
46a3df9f 22#include "hclge_cmd.h"
cacde272 23#include "hclge_dcb.h"
46a3df9f 24#include "hclge_main.h"
0cdbdd3e 25#include "hclge_mbx.h"
46a3df9f
S		 26#include "hclge_mdio.h"
27#include "hclge_tm.h"
28#include "hnae3.h"
29
30#define HCLGE_NAME "hclge"
31#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35
46a3df9f
S		 36static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
37 enum hclge_mta_dmac_sel_type mta_mac_sel,
38 bool enable);
59bc85ec 39static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 40static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 41static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 42
43static struct hnae3_ae_algo ae_algo;
44
45static const struct pci_device_id ae_algo_pci_tbl[] = {
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 53 /* required last entry */
46a3df9f
S		 54 {0, }
55};
56
57static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
58 "Mac Loopback test",
59 "Serdes Loopback test",
60 "Phy Loopback test"
61};
62
63static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
64 {"igu_rx_oversize_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
66 {"igu_rx_undersize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
68 {"igu_rx_out_all_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
70 {"igu_rx_uni_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
72 {"igu_rx_multi_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
74 {"igu_rx_broad_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
76 {"egu_tx_out_all_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
78 {"egu_tx_uni_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
80 {"egu_tx_multi_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
82 {"egu_tx_broad_pkt",
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
84 {"ssu_ppp_mac_key_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
86 {"ssu_ppp_host_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
88 {"ppp_ssu_mac_rlt_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
90 {"ppp_ssu_host_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
92 {"ssu_tx_in_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
94 {"ssu_tx_out_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
96 {"ssu_rx_in_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
98 {"ssu_rx_out_num",
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
100};
101
102static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
103 {"igu_rx_err_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
105 {"igu_rx_no_eof_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
107 {"igu_rx_no_sof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
109 {"egu_tx_1588_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
111 {"ssu_full_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
113 {"ssu_part_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
115 {"ppp_key_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
117 {"ppp_rlt_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
119 {"ssu_key_drop_num",
120 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
121 {"pkt_curr_buf_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
123 {"qcn_fb_rcv_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
125 {"qcn_fb_drop_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
127 {"qcn_fb_invaild_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
129 {"rx_packet_tc0_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
131 {"rx_packet_tc1_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
133 {"rx_packet_tc2_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
135 {"rx_packet_tc3_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
137 {"rx_packet_tc4_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
139 {"rx_packet_tc5_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
141 {"rx_packet_tc6_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
143 {"rx_packet_tc7_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
145 {"rx_packet_tc0_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
147 {"rx_packet_tc1_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
149 {"rx_packet_tc2_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
151 {"rx_packet_tc3_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
153 {"rx_packet_tc4_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
155 {"rx_packet_tc5_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
157 {"rx_packet_tc6_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
159 {"rx_packet_tc7_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
161 {"tx_packet_tc0_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
163 {"tx_packet_tc1_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
165 {"tx_packet_tc2_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
167 {"tx_packet_tc3_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
169 {"tx_packet_tc4_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
171 {"tx_packet_tc5_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
173 {"tx_packet_tc6_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
175 {"tx_packet_tc7_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
177 {"tx_packet_tc0_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
179 {"tx_packet_tc1_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
181 {"tx_packet_tc2_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
183 {"tx_packet_tc3_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
185 {"tx_packet_tc4_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
187 {"tx_packet_tc5_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
189 {"tx_packet_tc6_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
191 {"tx_packet_tc7_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
193 {"pkt_curr_buf_tc0_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
195 {"pkt_curr_buf_tc1_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
197 {"pkt_curr_buf_tc2_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
199 {"pkt_curr_buf_tc3_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
201 {"pkt_curr_buf_tc4_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
203 {"pkt_curr_buf_tc5_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
205 {"pkt_curr_buf_tc6_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
207 {"pkt_curr_buf_tc7_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
209 {"mb_uncopy_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
211 {"lo_pri_unicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
213 {"hi_pri_multicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
215 {"lo_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
217 {"rx_oq_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
219 {"tx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
221 {"nic_l2_err_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
223 {"roc_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
225};
226
227static const struct hclge_comm_stats_str g_mac_stats_string[] = {
228 {"mac_tx_mac_pause_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
230 {"mac_rx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
232 {"mac_tx_pfc_pri0_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
234 {"mac_tx_pfc_pri1_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
236 {"mac_tx_pfc_pri2_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
238 {"mac_tx_pfc_pri3_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
240 {"mac_tx_pfc_pri4_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
242 {"mac_tx_pfc_pri5_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
244 {"mac_tx_pfc_pri6_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
246 {"mac_tx_pfc_pri7_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
248 {"mac_rx_pfc_pri0_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
250 {"mac_rx_pfc_pri1_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
252 {"mac_rx_pfc_pri2_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
254 {"mac_rx_pfc_pri3_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
256 {"mac_rx_pfc_pri4_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
258 {"mac_rx_pfc_pri5_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
260 {"mac_rx_pfc_pri6_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
262 {"mac_rx_pfc_pri7_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
264 {"mac_tx_total_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
266 {"mac_tx_total_oct_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
268 {"mac_tx_good_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
270 {"mac_tx_bad_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
272 {"mac_tx_good_oct_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
274 {"mac_tx_bad_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
276 {"mac_tx_uni_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
278 {"mac_tx_multi_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
280 {"mac_tx_broad_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
282 {"mac_tx_undersize_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
f3426583
JS		 284 {"mac_tx_oversize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 286 {"mac_tx_64_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
288 {"mac_tx_65_127_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
290 {"mac_tx_128_255_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
292 {"mac_tx_256_511_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
294 {"mac_tx_512_1023_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
296 {"mac_tx_1024_1518_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
b42874e4
JS		 298 {"mac_tx_1519_2047_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
300 {"mac_tx_2048_4095_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
302 {"mac_tx_4096_8191_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
304 {"mac_tx_8192_12287_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_12287_oct_pkt_num)},
306 {"mac_tx_8192_9216_oct_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
308 {"mac_tx_9217_12287_oct_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
310 {"mac_tx_12288_16383_oct_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
312 {"mac_tx_1519_max_good_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
314 {"mac_tx_1519_max_bad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 316 {"mac_rx_total_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
318 {"mac_rx_total_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
320 {"mac_rx_good_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
322 {"mac_rx_bad_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
324 {"mac_rx_good_oct_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
326 {"mac_rx_bad_oct_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
328 {"mac_rx_uni_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
330 {"mac_rx_multi_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
332 {"mac_rx_broad_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
334 {"mac_rx_undersize_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
f3426583
JS		 336 {"mac_rx_oversize_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 338 {"mac_rx_64_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
340 {"mac_rx_65_127_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
342 {"mac_rx_128_255_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
344 {"mac_rx_256_511_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
346 {"mac_rx_512_1023_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
348 {"mac_rx_1024_1518_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
b42874e4
JS		 350 {"mac_rx_1519_2047_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
352 {"mac_rx_2048_4095_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
354 {"mac_rx_4096_8191_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
356 {"mac_rx_8192_12287_oct_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_12287_oct_pkt_num)},
358 {"mac_rx_8192_9216_oct_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
360 {"mac_rx_9217_12287_oct_pkt_num",
361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
362 {"mac_rx_12288_16383_oct_pkt_num",
363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
364 {"mac_rx_1519_max_good_pkt_num",
365 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
366 {"mac_rx_1519_max_bad_pkt_num",
367 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 368
c36317be
JS		 369 {"mac_tx_fragment_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
371 {"mac_tx_undermin_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
373 {"mac_tx_jabber_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
375 {"mac_tx_err_all_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
377 {"mac_tx_from_app_good_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
379 {"mac_tx_from_app_bad_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
381 {"mac_rx_fragment_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
383 {"mac_rx_undermin_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
385 {"mac_rx_jabber_pkt_num",
386 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
387 {"mac_rx_fcs_err_pkt_num",
388 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
389 {"mac_rx_send_app_good_pkt_num",
390 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
391 {"mac_rx_send_app_bad_pkt_num",
392 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 393};
394
635bfb58
FL		 395static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
396 {
397 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
398 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
399 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
400 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
401 .i_port_bitmap = 0x1,
402 },
403};
404
46a3df9f
S		 405static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
406{
407#define HCLGE_64_BIT_CMD_NUM 5
408#define HCLGE_64_BIT_RTN_DATANUM 4
409 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
410 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 411 __le64 *desc_data;
46a3df9f
S		 412 int i, k, n;
413 int ret;
414
415 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
416 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
417 if (ret) {
418 dev_err(&hdev->pdev->dev,
419 "Get 64 bit pkt stats fail, status = %d.\n", ret);
420 return ret;
421 }
422
423 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
424 if (unlikely(i == 0)) {
a90bb9a5 425 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 426 n = HCLGE_64_BIT_RTN_DATANUM - 1;
427 } else {
a90bb9a5 428 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 429 n = HCLGE_64_BIT_RTN_DATANUM;
430 }
431 for (k = 0; k < n; k++) {
a90bb9a5 432 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 433 desc_data++;
434 }
435 }
436
437 return 0;
438}
439
440static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
441{
442 stats->pkt_curr_buf_cnt = 0;
443 stats->pkt_curr_buf_tc0_cnt = 0;
444 stats->pkt_curr_buf_tc1_cnt = 0;
445 stats->pkt_curr_buf_tc2_cnt = 0;
446 stats->pkt_curr_buf_tc3_cnt = 0;
447 stats->pkt_curr_buf_tc4_cnt = 0;
448 stats->pkt_curr_buf_tc5_cnt = 0;
449 stats->pkt_curr_buf_tc6_cnt = 0;
450 stats->pkt_curr_buf_tc7_cnt = 0;
451}
452
453static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
454{
455#define HCLGE_32_BIT_CMD_NUM 8
456#define HCLGE_32_BIT_RTN_DATANUM 8
457
458 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
459 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 460 __le32 *desc_data;
46a3df9f
S		 461 int i, k, n;
462 u64 *data;
463 int ret;
464
465 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
466 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
467
468 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
469 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
470 if (ret) {
471 dev_err(&hdev->pdev->dev,
472 "Get 32 bit pkt stats fail, status = %d.\n", ret);
473
474 return ret;
475 }
476
477 hclge_reset_partial_32bit_counter(all_32_bit_stats);
478 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
479 if (unlikely(i == 0)) {
a90bb9a5
YL		 480 __le16 *desc_data_16bit;
481
46a3df9f 482 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 483 le32_to_cpu(desc[i].data[0]);
484
485 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 486 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 487 le16_to_cpu(*desc_data_16bit);
488
489 desc_data_16bit++;
46a3df9f 490 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 491 le16_to_cpu(*desc_data_16bit);
46a3df9f 492
a90bb9a5 493 desc_data = &desc[i].data[2];
46a3df9f
S		 494 n = HCLGE_32_BIT_RTN_DATANUM - 4;
495 } else {
a90bb9a5 496 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 497 n = HCLGE_32_BIT_RTN_DATANUM;
498 }
499 for (k = 0; k < n; k++) {
a90bb9a5 500 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 501 desc_data++;
502 }
503 }
504
505 return 0;
506}
507
508static int hclge_mac_update_stats(struct hclge_dev *hdev)
509{
b42874e4 510#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 511#define HCLGE_RTN_DATA_NUM 4
512
513 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
514 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 515 __le64 *desc_data;
46a3df9f
S		 516 int i, k, n;
517 int ret;
518
519 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
520 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
521 if (ret) {
522 dev_err(&hdev->pdev->dev,
523 "Get MAC pkt stats fail, status = %d.\n", ret);
524
525 return ret;
526 }
527
528 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
529 if (unlikely(i == 0)) {
a90bb9a5 530 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 531 n = HCLGE_RTN_DATA_NUM - 2;
532 } else {
a90bb9a5 533 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 534 n = HCLGE_RTN_DATA_NUM;
535 }
536 for (k = 0; k < n; k++) {
a90bb9a5 537 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 538 desc_data++;
539 }
540 }
541
542 return 0;
543}
544
545static int hclge_tqps_update_stats(struct hnae3_handle *handle)
546{
547 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
548 struct hclge_vport *vport = hclge_get_vport(handle);
549 struct hclge_dev *hdev = vport->back;
550 struct hnae3_queue *queue;
551 struct hclge_desc desc[1];
552 struct hclge_tqp *tqp;
553 int ret, i;
554
555 for (i = 0; i < kinfo->num_tqps; i++) {
556 queue = handle->kinfo.tqp[i];
557 tqp = container_of(queue, struct hclge_tqp, q);
558 /* command : HCLGE_OPC_QUERY_IGU_STAT */
559 hclge_cmd_setup_basic_desc(&desc[0],
560 HCLGE_OPC_QUERY_RX_STATUS,
561 true);
562
a90bb9a5 563 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 564 ret = hclge_cmd_send(&hdev->hw, desc, 1);
565 if (ret) {
566 dev_err(&hdev->pdev->dev,
567 "Query tqp stat fail, status = %d,queue = %d\n",
568 ret, i);
569 return ret;
570 }
571 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 572 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 573 }
574
575 for (i = 0; i < kinfo->num_tqps; i++) {
576 queue = handle->kinfo.tqp[i];
577 tqp = container_of(queue, struct hclge_tqp, q);
578 /* command : HCLGE_OPC_QUERY_IGU_STAT */
579 hclge_cmd_setup_basic_desc(&desc[0],
580 HCLGE_OPC_QUERY_TX_STATUS,
581 true);
582
a90bb9a5 583 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 584 ret = hclge_cmd_send(&hdev->hw, desc, 1);
585 if (ret) {
586 dev_err(&hdev->pdev->dev,
587 "Query tqp stat fail, status = %d,queue = %d\n",
588 ret, i);
589 return ret;
590 }
591 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 592 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 593 }
594
595 return 0;
596}
597
598static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
599{
600 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
601 struct hclge_tqp *tqp;
602 u64 *buff = data;
603 int i;
604
605 for (i = 0; i < kinfo->num_tqps; i++) {
606 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 607 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 608 }
609
610 for (i = 0; i < kinfo->num_tqps; i++) {
611 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 612 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 613 }
614
615 return buff;
616}
617
618static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
619{
620 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
621
622 return kinfo->num_tqps * (2);
623}
624
625static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
626{
627 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
628 u8 *buff = data;
629 int i = 0;
630
631 for (i = 0; i < kinfo->num_tqps; i++) {
632 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
633 struct hclge_tqp, q);
c36317be 634 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
46a3df9f
S		 635 tqp->index);
636 buff = buff + ETH_GSTRING_LEN;
637 }
638
639 for (i = 0; i < kinfo->num_tqps; i++) {
640 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
641 struct hclge_tqp, q);
c36317be 642 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
46a3df9f
S		 643 tqp->index);
644 buff = buff + ETH_GSTRING_LEN;
645 }
646
647 return buff;
648}
649
650static u64 *hclge_comm_get_stats(void *comm_stats,
651 const struct hclge_comm_stats_str strs[],
652 int size, u64 *data)
653{
654 u64 *buf = data;
655 u32 i;
656
657 for (i = 0; i < size; i++)
658 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
659
660 return buf + size;
661}
662
663static u8 *hclge_comm_get_strings(u32 stringset,
664 const struct hclge_comm_stats_str strs[],
665 int size, u8 *data)
666{
667 char *buff = (char *)data;
668 u32 i;
669
670 if (stringset != ETH_SS_STATS)
671 return buff;
672
673 for (i = 0; i < size; i++) {
674 snprintf(buff, ETH_GSTRING_LEN,
675 strs[i].desc);
676 buff = buff + ETH_GSTRING_LEN;
677 }
678
679 return (u8 *)buff;
680}
681
682static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
683 struct net_device_stats *net_stats)
684{
685 net_stats->tx_dropped = 0;
686 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
687 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
688 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
689
f3426583 690 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 691 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
46a3df9f
S		 692 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
693 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
c36317be 694 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 695
696 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
697 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
698
c36317be 699 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 700 net_stats->rx_length_errors =
701 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
702 net_stats->rx_length_errors +=
f3426583 703 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 704 net_stats->rx_over_errors =
f3426583 705 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 706}
707
708static void hclge_update_stats_for_all(struct hclge_dev *hdev)
709{
710 struct hnae3_handle *handle;
711 int status;
712
713 handle = &hdev->vport[0].nic;
714 if (handle->client) {
715 status = hclge_tqps_update_stats(handle);
716 if (status) {
717 dev_err(&hdev->pdev->dev,
718 "Update TQPS stats fail, status = %d.\n",
719 status);
720 }
721 }
722
723 status = hclge_mac_update_stats(hdev);
724 if (status)
725 dev_err(&hdev->pdev->dev,
726 "Update MAC stats fail, status = %d.\n", status);
727
728 status = hclge_32_bit_update_stats(hdev);
729 if (status)
730 dev_err(&hdev->pdev->dev,
731 "Update 32 bit stats fail, status = %d.\n",
732 status);
733
734 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
735}
736
737static void hclge_update_stats(struct hnae3_handle *handle,
738 struct net_device_stats *net_stats)
739{
740 struct hclge_vport *vport = hclge_get_vport(handle);
741 struct hclge_dev *hdev = vport->back;
742 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
743 int status;
744
7a5d2a39
JS		 745 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
746 return;
747
46a3df9f
S		 748 status = hclge_mac_update_stats(hdev);
749 if (status)
750 dev_err(&hdev->pdev->dev,
751 "Update MAC stats fail, status = %d.\n",
752 status);
753
754 status = hclge_32_bit_update_stats(hdev);
755 if (status)
756 dev_err(&hdev->pdev->dev,
757 "Update 32 bit stats fail, status = %d.\n",
758 status);
759
760 status = hclge_64_bit_update_stats(hdev);
761 if (status)
762 dev_err(&hdev->pdev->dev,
763 "Update 64 bit stats fail, status = %d.\n",
764 status);
765
766 status = hclge_tqps_update_stats(handle);
767 if (status)
768 dev_err(&hdev->pdev->dev,
769 "Update TQPS stats fail, status = %d.\n",
770 status);
771
772 hclge_update_netstat(hw_stats, net_stats);
7a5d2a39
JS		 773
774 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 775}
776
777static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
778{
779#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
780
781 struct hclge_vport *vport = hclge_get_vport(handle);
782 struct hclge_dev *hdev = vport->back;
783 int count = 0;
784
785 /* Loopback test support rules:
786 * mac: only GE mode support
787 * serdes: all mac mode will support include GE/XGE/LGE/CGE
788 * phy: only support when phy device exist on board
789 */
790 if (stringset == ETH_SS_TEST) {
791 /* clear loopback bit flags at first */
792 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
793 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
794 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
795 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
796 count += 1;
797 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
798 } else {
799 count = -EOPNOTSUPP;
800 }
801 } else if (stringset == ETH_SS_STATS) {
802 count = ARRAY_SIZE(g_mac_stats_string) +
803 ARRAY_SIZE(g_all_32bit_stats_string) +
804 ARRAY_SIZE(g_all_64bit_stats_string) +
805 hclge_tqps_get_sset_count(handle, stringset);
806 }
807
808 return count;
809}
810
811static void hclge_get_strings(struct hnae3_handle *handle,
812 u32 stringset,
813 u8 *data)
814{
815 u8 *p = (char *)data;
816 int size;
817
818 if (stringset == ETH_SS_STATS) {
819 size = ARRAY_SIZE(g_mac_stats_string);
820 p = hclge_comm_get_strings(stringset,
821 g_mac_stats_string,
822 size,
823 p);
824 size = ARRAY_SIZE(g_all_32bit_stats_string);
825 p = hclge_comm_get_strings(stringset,
826 g_all_32bit_stats_string,
827 size,
828 p);
829 size = ARRAY_SIZE(g_all_64bit_stats_string);
830 p = hclge_comm_get_strings(stringset,
831 g_all_64bit_stats_string,
832 size,
833 p);
834 p = hclge_tqps_get_strings(handle, p);
835 } else if (stringset == ETH_SS_TEST) {
836 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
837 memcpy(p,
838 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
839 ETH_GSTRING_LEN);
840 p += ETH_GSTRING_LEN;
841 }
842 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
843 memcpy(p,
844 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
845 ETH_GSTRING_LEN);
846 p += ETH_GSTRING_LEN;
847 }
848 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
849 memcpy(p,
850 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
851 ETH_GSTRING_LEN);
852 p += ETH_GSTRING_LEN;
853 }
854 }
855}
856
857static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
858{
859 struct hclge_vport *vport = hclge_get_vport(handle);
860 struct hclge_dev *hdev = vport->back;
861 u64 *p;
862
863 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
864 g_mac_stats_string,
865 ARRAY_SIZE(g_mac_stats_string),
866 data);
867 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
868 g_all_32bit_stats_string,
869 ARRAY_SIZE(g_all_32bit_stats_string),
870 p);
871 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
872 g_all_64bit_stats_string,
873 ARRAY_SIZE(g_all_64bit_stats_string),
874 p);
875 p = hclge_tqps_get_stats(handle, p);
876}
877
878static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 879 struct hclge_func_status_cmd *status)
46a3df9f
S		 880{
881 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
882 return -EINVAL;
883
884 /* Set the pf to main pf */
885 if (status->pf_state & HCLGE_PF_STATE_MAIN)
886 hdev->flag |= HCLGE_FLAG_MAIN;
887 else
888 hdev->flag &= ~HCLGE_FLAG_MAIN;
889
46a3df9f
S		 890 return 0;
891}
892
893static int hclge_query_function_status(struct hclge_dev *hdev)
894{
d44f9b63 895 struct hclge_func_status_cmd *req;
46a3df9f
S		 896 struct hclge_desc desc;
897 int timeout = 0;
898 int ret;
899
900 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 901 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 902
903 do {
904 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
905 if (ret) {
906 dev_err(&hdev->pdev->dev,
907 "query function status failed %d.\n",
908 ret);
909
910 return ret;
911 }
912
913 /* Check pf reset is done */
914 if (req->pf_state)
915 break;
916 usleep_range(1000, 2000);
917 } while (timeout++ < 5);
918
919 ret = hclge_parse_func_status(hdev, req);
920
921 return ret;
922}
923
924static int hclge_query_pf_resource(struct hclge_dev *hdev)
925{
d44f9b63 926 struct hclge_pf_res_cmd *req;
46a3df9f
S		 927 struct hclge_desc desc;
928 int ret;
929
930 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
931 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
932 if (ret) {
933 dev_err(&hdev->pdev->dev,
934 "query pf resource failed %d.\n", ret);
935 return ret;
936 }
937
d44f9b63 938 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 939 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
940 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
941
e92a0843 942 if (hnae3_dev_roce_supported(hdev)) {
887c3820 943 hdev->num_roce_msi =
46a3df9f
S		 944 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
945 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
946
947 /* PF should have NIC vectors and Roce vectors,
948 * NIC vectors are queued before Roce vectors.
949 */
887c3820 950 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 951 } else {
952 hdev->num_msi =
953 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
954 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
955 }
956
957 return 0;
958}
959
960static int hclge_parse_speed(int speed_cmd, int *speed)
961{
962 switch (speed_cmd) {
963 case 6:
964 *speed = HCLGE_MAC_SPEED_10M;
965 break;
966 case 7:
967 *speed = HCLGE_MAC_SPEED_100M;
968 break;
969 case 0:
970 *speed = HCLGE_MAC_SPEED_1G;
971 break;
972 case 1:
973 *speed = HCLGE_MAC_SPEED_10G;
974 break;
975 case 2:
976 *speed = HCLGE_MAC_SPEED_25G;
977 break;
978 case 3:
979 *speed = HCLGE_MAC_SPEED_40G;
980 break;
981 case 4:
982 *speed = HCLGE_MAC_SPEED_50G;
983 break;
984 case 5:
985 *speed = HCLGE_MAC_SPEED_100G;
986 break;
987 default:
988 return -EINVAL;
989 }
990
991 return 0;
992}
993
994static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
995{
d44f9b63 996 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 997 u64 mac_addr_tmp_high;
998 u64 mac_addr_tmp;
999 int i;
1000
d44f9b63 1001 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 1002
1003 /* get the configuration */
1004 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1005 HCLGE_CFG_VMDQ_M,
1006 HCLGE_CFG_VMDQ_S);
1007 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1008 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1009 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1010 HCLGE_CFG_TQP_DESC_N_M,
1011 HCLGE_CFG_TQP_DESC_N_S);
1012
1013 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
1014 HCLGE_CFG_PHY_ADDR_M,
1015 HCLGE_CFG_PHY_ADDR_S);
1016 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
1017 HCLGE_CFG_MEDIA_TP_M,
1018 HCLGE_CFG_MEDIA_TP_S);
1019 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
1020 HCLGE_CFG_RX_BUF_LEN_M,
1021 HCLGE_CFG_RX_BUF_LEN_S);
1022 /* get mac_address */
1023 mac_addr_tmp = __le32_to_cpu(req->param[2]);
1024 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
1025 HCLGE_CFG_MAC_ADDR_H_M,
1026 HCLGE_CFG_MAC_ADDR_H_S);
1027
1028 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1029
1030 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
1031 HCLGE_CFG_DEFAULT_SPEED_M,
1032 HCLGE_CFG_DEFAULT_SPEED_S);
c408e202
PL		 1033 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]),
1034 HCLGE_CFG_RSS_SIZE_M,
1035 HCLGE_CFG_RSS_SIZE_S);
1036
46a3df9f
S		 1037 for (i = 0; i < ETH_ALEN; i++)
1038 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1039
d44f9b63 1040 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f
S		 1041 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1042}
1043
1044/* hclge_get_cfg: query the static parameter from flash
1045 * @hdev: pointer to struct hclge_dev
1046 * @hcfg: the config structure to be getted
1047 */
1048static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1049{
1050 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 1051 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1052 int i, ret;
1053
1054 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1055 u32 offset = 0;
1056
d44f9b63 1057 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1058 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1059 true);
a90bb9a5 1060 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
46a3df9f
S		 1061 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1062 /* Len should be united by 4 bytes when send to hardware */
a90bb9a5 1063 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
46a3df9f 1064 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1065 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1066 }
1067
1068 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1069 if (ret) {
1070 dev_err(&hdev->pdev->dev,
1071 "get config failed %d.\n", ret);
1072 return ret;
1073 }
1074
1075 hclge_parse_cfg(hcfg, desc);
1076 return 0;
1077}
1078
1079static int hclge_get_cap(struct hclge_dev *hdev)
1080{
1081 int ret;
1082
1083 ret = hclge_query_function_status(hdev);
1084 if (ret) {
1085 dev_err(&hdev->pdev->dev,
1086 "query function status error %d.\n", ret);
1087 return ret;
1088 }
1089
1090 /* get pf resource */
1091 ret = hclge_query_pf_resource(hdev);
1092 if (ret) {
1093 dev_err(&hdev->pdev->dev,
1094 "query pf resource error %d.\n", ret);
1095 return ret;
1096 }
1097
1098 return 0;
1099}
1100
1101static int hclge_configure(struct hclge_dev *hdev)
1102{
1103 struct hclge_cfg cfg;
1104 int ret, i;
1105
1106 ret = hclge_get_cfg(hdev, &cfg);
1107 if (ret) {
1108 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1109 return ret;
1110 }
1111
1112 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1113 hdev->base_tqp_pid = 0;
c408e202 1114 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 1115 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1116 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1117 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1118 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1119 hdev->num_desc = cfg.tqp_desc_num;
1120 hdev->tm_info.num_pg = 1;
cacde272 1121 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1122 hdev->tm_info.hw_pfc_map = 0;
1123
1124 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1125 if (ret) {
1126 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1127 return ret;
1128 }
1129
cacde272
YL		 1130 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1131 (hdev->tc_max < 1)) {
46a3df9f 1132 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1133 hdev->tc_max);
1134 hdev->tc_max = 1;
46a3df9f
S		 1135 }
1136
cacde272
YL		 1137 /* Dev does not support DCB */
1138 if (!hnae3_dev_dcb_supported(hdev)) {
1139 hdev->tc_max = 1;
1140 hdev->pfc_max = 0;
1141 } else {
1142 hdev->pfc_max = hdev->tc_max;
1143 }
1144
1145 hdev->tm_info.num_tc = hdev->tc_max;
1146
46a3df9f 1147 /* Currently not support uncontiuous tc */
cacde272 1148 for (i = 0; i < hdev->tm_info.num_tc; i++)
46a3df9f
S		 1149 hnae_set_bit(hdev->hw_tc_map, i, 1);
1150
f8362fe1 1151 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 1152
1153 return ret;
1154}
1155
1156static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1157 int tso_mss_max)
1158{
d44f9b63 1159 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1160 struct hclge_desc desc;
a90bb9a5 1161 u16 tso_mss;
46a3df9f
S		 1162
1163 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1164
d44f9b63 1165 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1166
1167 tso_mss = 0;
1168 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1169 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1170 req->tso_mss_min = cpu_to_le16(tso_mss);
1171
1172 tso_mss = 0;
1173 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1174 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1175 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1176
1177 return hclge_cmd_send(&hdev->hw, &desc, 1);
1178}
1179
1180static int hclge_alloc_tqps(struct hclge_dev *hdev)
1181{
1182 struct hclge_tqp *tqp;
1183 int i;
1184
1185 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1186 sizeof(struct hclge_tqp), GFP_KERNEL);
1187 if (!hdev->htqp)
1188 return -ENOMEM;
1189
1190 tqp = hdev->htqp;
1191
1192 for (i = 0; i < hdev->num_tqps; i++) {
1193 tqp->dev = &hdev->pdev->dev;
1194 tqp->index = i;
1195
1196 tqp->q.ae_algo = &ae_algo;
1197 tqp->q.buf_size = hdev->rx_buf_len;
1198 tqp->q.desc_num = hdev->num_desc;
1199 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1200 i * HCLGE_TQP_REG_SIZE;
1201
1202 tqp++;
1203 }
1204
1205 return 0;
1206}
1207
1208static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1209 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1210{
d44f9b63 1211 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1212 struct hclge_desc desc;
1213 int ret;
1214
1215 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1216
d44f9b63 1217 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1218 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1219 req->tqp_vf = func_id;
46a3df9f
S		 1220 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1221 1 << HCLGE_TQP_MAP_EN_B;
1222 req->tqp_vid = cpu_to_le16(tqp_vid);
1223
1224 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1225 if (ret) {
1226 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1227 ret);
1228 return ret;
1229 }
1230
1231 return 0;
1232}
1233
1234static int hclge_assign_tqp(struct hclge_vport *vport,
1235 struct hnae3_queue **tqp, u16 num_tqps)
1236{
1237 struct hclge_dev *hdev = vport->back;
7df7dad6 1238 int i, alloced;
46a3df9f
S		 1239
1240 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1241 alloced < num_tqps; i++) {
1242 if (!hdev->htqp[i].alloced) {
1243 hdev->htqp[i].q.handle = &vport->nic;
1244 hdev->htqp[i].q.tqp_index = alloced;
1245 tqp[alloced] = &hdev->htqp[i].q;
1246 hdev->htqp[i].alloced = true;
46a3df9f
S		 1247 alloced++;
1248 }
1249 }
1250 vport->alloc_tqps = num_tqps;
1251
1252 return 0;
1253}
1254
1255static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1256{
1257 struct hnae3_handle *nic = &vport->nic;
1258 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1259 struct hclge_dev *hdev = vport->back;
1260 int i, ret;
1261
1262 kinfo->num_desc = hdev->num_desc;
1263 kinfo->rx_buf_len = hdev->rx_buf_len;
1264 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1265 kinfo->rss_size
1266 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1267 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1268
1269 for (i = 0; i < HNAE3_MAX_TC; i++) {
1270 if (hdev->hw_tc_map & BIT(i)) {
1271 kinfo->tc_info[i].enable = true;
1272 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1273 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1274 kinfo->tc_info[i].tc = i;
1275 } else {
1276 /* Set to default queue if TC is disable */
1277 kinfo->tc_info[i].enable = false;
1278 kinfo->tc_info[i].tqp_offset = 0;
1279 kinfo->tc_info[i].tqp_count = 1;
1280 kinfo->tc_info[i].tc = 0;
1281 }
1282 }
1283
1284 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1285 sizeof(struct hnae3_queue *), GFP_KERNEL);
1286 if (!kinfo->tqp)
1287 return -ENOMEM;
1288
1289 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1290 if (ret) {
1291 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1292 return -EINVAL;
1293 }
1294
1295 return 0;
1296}
1297
7df7dad6
L		 1298static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1299 struct hclge_vport *vport)
1300{
1301 struct hnae3_handle *nic = &vport->nic;
1302 struct hnae3_knic_private_info *kinfo;
1303 u16 i;
1304
1305 kinfo = &nic->kinfo;
1306 for (i = 0; i < kinfo->num_tqps; i++) {
1307 struct hclge_tqp *q =
1308 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1309 bool is_pf;
1310 int ret;
1311
1312 is_pf = !(vport->vport_id);
1313 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1314 i, is_pf);
1315 if (ret)
1316 return ret;
1317 }
1318
1319 return 0;
1320}
1321
1322static int hclge_map_tqp(struct hclge_dev *hdev)
1323{
1324 struct hclge_vport *vport = hdev->vport;
1325 u16 i, num_vport;
1326
1327 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1328 for (i = 0; i < num_vport; i++) {
1329 int ret;
1330
1331 ret = hclge_map_tqp_to_vport(hdev, vport);
1332 if (ret)
1333 return ret;
1334
1335 vport++;
1336 }
1337
1338 return 0;
1339}
1340
46a3df9f
S		 1341static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1342{
1343 /* this would be initialized later */
1344}
1345
1346static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1347{
1348 struct hnae3_handle *nic = &vport->nic;
1349 struct hclge_dev *hdev = vport->back;
1350 int ret;
1351
1352 nic->pdev = hdev->pdev;
1353 nic->ae_algo = &ae_algo;
1354 nic->numa_node_mask = hdev->numa_node_mask;
1355
1356 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1357 ret = hclge_knic_setup(vport, num_tqps);
1358 if (ret) {
1359 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1360 ret);
1361 return ret;
1362 }
1363 } else {
1364 hclge_unic_setup(vport, num_tqps);
1365 }
1366
1367 return 0;
1368}
1369
1370static int hclge_alloc_vport(struct hclge_dev *hdev)
1371{
1372 struct pci_dev *pdev = hdev->pdev;
1373 struct hclge_vport *vport;
1374 u32 tqp_main_vport;
1375 u32 tqp_per_vport;
1376 int num_vport, i;
1377 int ret;
1378
1379 /* We need to alloc a vport for main NIC of PF */
1380 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1381
1382 if (hdev->num_tqps < num_vport)
1383 num_vport = hdev->num_tqps;
1384
1385 /* Alloc the same number of TQPs for every vport */
1386 tqp_per_vport = hdev->num_tqps / num_vport;
1387 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1388
1389 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1390 GFP_KERNEL);
1391 if (!vport)
1392 return -ENOMEM;
1393
1394 hdev->vport = vport;
1395 hdev->num_alloc_vport = num_vport;
1396
1397#ifdef CONFIG_PCI_IOV
1398 /* Enable SRIOV */
1399 if (hdev->num_req_vfs) {
1400 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1401 hdev->num_req_vfs);
1402 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1403 if (ret) {
1404 hdev->num_alloc_vfs = 0;
1405 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1406 ret);
1407 return ret;
1408 }
1409 }
1410 hdev->num_alloc_vfs = hdev->num_req_vfs;
1411#endif
1412
1413 for (i = 0; i < num_vport; i++) {
1414 vport->back = hdev;
1415 vport->vport_id = i;
1416
1417 if (i == 0)
1418 ret = hclge_vport_setup(vport, tqp_main_vport);
1419 else
1420 ret = hclge_vport_setup(vport, tqp_per_vport);
1421 if (ret) {
1422 dev_err(&pdev->dev,
1423 "vport setup failed for vport %d, %d\n",
1424 i, ret);
1425 return ret;
1426 }
1427
1428 vport++;
1429 }
1430
1431 return 0;
1432}
1433
acf61ecd
YL		 1434static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1435 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1436{
1437/* TX buffer size is unit by 128 byte */
1438#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1439#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1440 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1441 struct hclge_desc desc;
1442 int ret;
1443 u8 i;
1444
d44f9b63 1445 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1446
1447 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1448 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1449 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1450
46a3df9f
S		 1451 req->tx_pkt_buff[i] =
1452 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1453 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1454 }
46a3df9f
S		 1455
1456 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1457 if (ret) {
1458 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1459 ret);
1460 return ret;
1461 }
1462
1463 return 0;
1464}
1465
acf61ecd
YL		 1466static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1467 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1468{
acf61ecd 1469 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1470
1471 if (ret) {
1472 dev_err(&hdev->pdev->dev,
1473 "tx buffer alloc failed %d\n", ret);
1474 return ret;
1475 }
1476
1477 return 0;
1478}
1479
1480static int hclge_get_tc_num(struct hclge_dev *hdev)
1481{
1482 int i, cnt = 0;
1483
1484 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1485 if (hdev->hw_tc_map & BIT(i))
1486 cnt++;
1487 return cnt;
1488}
1489
1490static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1491{
1492 int i, cnt = 0;
1493
1494 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1495 if (hdev->hw_tc_map & BIT(i) &&
1496 hdev->tm_info.hw_pfc_map & BIT(i))
1497 cnt++;
1498 return cnt;
1499}
1500
1501/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1502static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1503 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1504{
1505 struct hclge_priv_buf *priv;
1506 int i, cnt = 0;
1507
1508 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1509 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1510 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1511 priv->enable)
1512 cnt++;
1513 }
1514
1515 return cnt;
1516}
1517
1518/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1519static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1520 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1521{
1522 struct hclge_priv_buf *priv;
1523 int i, cnt = 0;
1524
1525 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1526 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1527 if (hdev->hw_tc_map & BIT(i) &&
1528 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1529 priv->enable)
1530 cnt++;
1531 }
1532
1533 return cnt;
1534}
1535
acf61ecd 1536static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1537{
1538 struct hclge_priv_buf *priv;
1539 u32 rx_priv = 0;
1540 int i;
1541
1542 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1543 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1544 if (priv->enable)
1545 rx_priv += priv->buf_size;
1546 }
1547 return rx_priv;
1548}
1549
acf61ecd 1550static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1551{
1552 u32 i, total_tx_size = 0;
1553
1554 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1555 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1556
1557 return total_tx_size;
1558}
1559
acf61ecd
YL		 1560static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1561 struct hclge_pkt_buf_alloc *buf_alloc,
1562 u32 rx_all)
46a3df9f
S		 1563{
1564 u32 shared_buf_min, shared_buf_tc, shared_std;
1565 int tc_num, pfc_enable_num;
1566 u32 shared_buf;
1567 u32 rx_priv;
1568 int i;
1569
1570 tc_num = hclge_get_tc_num(hdev);
1571 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1572
d221df4e
YL		 1573 if (hnae3_dev_dcb_supported(hdev))
1574 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1575 else
1576 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1577
46a3df9f
S		 1578 shared_buf_tc = pfc_enable_num * hdev->mps +
1579 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1580 hdev->mps;
1581 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1582
acf61ecd 1583 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1584 if (rx_all <= rx_priv + shared_std)
1585 return false;
1586
1587 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1588 buf_alloc->s_buf.buf_size = shared_buf;
1589 buf_alloc->s_buf.self.high = shared_buf;
1590 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1591
1592 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1593 if ((hdev->hw_tc_map & BIT(i)) &&
1594 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1595 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1596 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1597 } else {
acf61ecd
YL		 1598 buf_alloc->s_buf.tc_thrd[i].low = 0;
1599 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1600 }
1601 }
1602
1603 return true;
1604}
1605
acf61ecd
YL		 1606static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1607 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1608{
1609 u32 i, total_size;
1610
1611 total_size = hdev->pkt_buf_size;
1612
1613 /* alloc tx buffer for all enabled tc */
1614 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1615 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1616
1617 if (total_size < HCLGE_DEFAULT_TX_BUF)
1618 return -ENOMEM;
1619
1620 if (hdev->hw_tc_map & BIT(i))
1621 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1622 else
1623 priv->tx_buf_size = 0;
1624
1625 total_size -= priv->tx_buf_size;
1626 }
1627
1628 return 0;
1629}
1630
46a3df9f
S		 1631/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1632 * @hdev: pointer to struct hclge_dev
acf61ecd 1633 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1634 * @return: 0: calculate sucessful, negative: fail
1635 */
1db9b1bf
YL		 1636static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1637 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1638{
9ffe79a9 1639 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1640 int no_pfc_priv_num, pfc_priv_num;
1641 struct hclge_priv_buf *priv;
1642 int i;
1643
acf61ecd 1644 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1645
d602a525
YL		 1646 /* When DCB is not supported, rx private
1647 * buffer is not allocated.
1648 */
1649 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1650 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1651 return -ENOMEM;
1652
1653 return 0;
1654 }
1655
46a3df9f
S		 1656 /* step 1, try to alloc private buffer for all enabled tc */
1657 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1658 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1659 if (hdev->hw_tc_map & BIT(i)) {
1660 priv->enable = 1;
1661 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1662 priv->wl.low = hdev->mps;
1663 priv->wl.high = priv->wl.low + hdev->mps;
1664 priv->buf_size = priv->wl.high +
1665 HCLGE_DEFAULT_DV;
1666 } else {
1667 priv->wl.low = 0;
1668 priv->wl.high = 2 * hdev->mps;
1669 priv->buf_size = priv->wl.high;
1670 }
bb1fe9ea
YL		 1671 } else {
1672 priv->enable = 0;
1673 priv->wl.low = 0;
1674 priv->wl.high = 0;
1675 priv->buf_size = 0;
46a3df9f
S		 1676 }
1677 }
1678
acf61ecd 1679 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1680 return 0;
1681
1682 /* step 2, try to decrease the buffer size of
1683 * no pfc TC's private buffer
1684 */
1685 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1686 priv = &buf_alloc->priv_buf[i];
46a3df9f 1687
bb1fe9ea
YL		 1688 priv->enable = 0;
1689 priv->wl.low = 0;
1690 priv->wl.high = 0;
1691 priv->buf_size = 0;
1692
1693 if (!(hdev->hw_tc_map & BIT(i)))
1694 continue;
1695
1696 priv->enable = 1;
46a3df9f
S		 1697
1698 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1699 priv->wl.low = 128;
1700 priv->wl.high = priv->wl.low + hdev->mps;
1701 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1702 } else {
1703 priv->wl.low = 0;
1704 priv->wl.high = hdev->mps;
1705 priv->buf_size = priv->wl.high;
1706 }
1707 }
1708
acf61ecd 1709 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1710 return 0;
1711
1712 /* step 3, try to reduce the number of pfc disabled TCs,
1713 * which have private buffer
1714 */
1715 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1716 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1717
1718 /* let the last to be cleared first */
1719 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1720 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1721
1722 if (hdev->hw_tc_map & BIT(i) &&
1723 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1724 /* Clear the no pfc TC private buffer */
1725 priv->wl.low = 0;
1726 priv->wl.high = 0;
1727 priv->buf_size = 0;
1728 priv->enable = 0;
1729 no_pfc_priv_num--;
1730 }
1731
acf61ecd 1732 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1733 no_pfc_priv_num == 0)
1734 break;
1735 }
1736
acf61ecd 1737 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1738 return 0;
1739
1740 /* step 4, try to reduce the number of pfc enabled TCs
1741 * which have private buffer.
1742 */
acf61ecd 1743 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1744
1745 /* let the last to be cleared first */
1746 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1747 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1748
1749 if (hdev->hw_tc_map & BIT(i) &&
1750 hdev->tm_info.hw_pfc_map & BIT(i)) {
1751 /* Reduce the number of pfc TC with private buffer */
1752 priv->wl.low = 0;
1753 priv->enable = 0;
1754 priv->wl.high = 0;
1755 priv->buf_size = 0;
1756 pfc_priv_num--;
1757 }
1758
acf61ecd 1759 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1760 pfc_priv_num == 0)
1761 break;
1762 }
acf61ecd 1763 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1764 return 0;
1765
1766 return -ENOMEM;
1767}
1768
acf61ecd
YL		 1769static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1770 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1771{
d44f9b63 1772 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1773 struct hclge_desc desc;
1774 int ret;
1775 int i;
1776
1777 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1778 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1779
1780 /* Alloc private buffer TCs */
1781 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1782 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1783
1784 req->buf_num[i] =
1785 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1786 req->buf_num[i] |=
5bca3b94 1787 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1788 }
1789
b8c8bf47 1790 req->shared_buf =
acf61ecd 1791 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1792 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1793
46a3df9f
S		 1794 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1795 if (ret) {
1796 dev_err(&hdev->pdev->dev,
1797 "rx private buffer alloc cmd failed %d\n", ret);
1798 return ret;
1799 }
1800
1801 return 0;
1802}
1803
1804#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1805
acf61ecd
YL		 1806static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1807 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1808{
1809 struct hclge_rx_priv_wl_buf *req;
1810 struct hclge_priv_buf *priv;
1811 struct hclge_desc desc[2];
1812 int i, j;
1813 int ret;
1814
1815 for (i = 0; i < 2; i++) {
1816 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1817 false);
1818 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1819
1820 /* The first descriptor set the NEXT bit to 1 */
1821 if (i == 0)
1822 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1823 else
1824 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1825
1826 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1827 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1828
1829 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1830 req->tc_wl[j].high =
1831 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1832 req->tc_wl[j].high |=
1833 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1834 HCLGE_RX_PRIV_EN_B);
1835 req->tc_wl[j].low =
1836 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1837 req->tc_wl[j].low |=
1838 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1839 HCLGE_RX_PRIV_EN_B);
1840 }
1841 }
1842
1843 /* Send 2 descriptor at one time */
1844 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1845 if (ret) {
1846 dev_err(&hdev->pdev->dev,
1847 "rx private waterline config cmd failed %d\n",
1848 ret);
1849 return ret;
1850 }
1851 return 0;
1852}
1853
acf61ecd
YL		 1854static int hclge_common_thrd_config(struct hclge_dev *hdev,
1855 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1856{
acf61ecd 1857 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1858 struct hclge_rx_com_thrd *req;
1859 struct hclge_desc desc[2];
1860 struct hclge_tc_thrd *tc;
1861 int i, j;
1862 int ret;
1863
1864 for (i = 0; i < 2; i++) {
1865 hclge_cmd_setup_basic_desc(&desc[i],
1866 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1867 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1868
1869 /* The first descriptor set the NEXT bit to 1 */
1870 if (i == 0)
1871 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1872 else
1873 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1874
1875 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1876 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1877
1878 req->com_thrd[j].high =
1879 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1880 req->com_thrd[j].high |=
1881 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1882 HCLGE_RX_PRIV_EN_B);
1883 req->com_thrd[j].low =
1884 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1885 req->com_thrd[j].low |=
1886 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1887 HCLGE_RX_PRIV_EN_B);
1888 }
1889 }
1890
1891 /* Send 2 descriptors at one time */
1892 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1893 if (ret) {
1894 dev_err(&hdev->pdev->dev,
1895 "common threshold config cmd failed %d\n", ret);
1896 return ret;
1897 }
1898 return 0;
1899}
1900
acf61ecd
YL		 1901static int hclge_common_wl_config(struct hclge_dev *hdev,
1902 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1903{
acf61ecd 1904 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1905 struct hclge_rx_com_wl *req;
1906 struct hclge_desc desc;
1907 int ret;
1908
1909 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1910
1911 req = (struct hclge_rx_com_wl *)desc.data;
1912 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1913 req->com_wl.high |=
1914 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1915 HCLGE_RX_PRIV_EN_B);
1916
1917 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1918 req->com_wl.low |=
1919 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1920 HCLGE_RX_PRIV_EN_B);
1921
1922 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1923 if (ret) {
1924 dev_err(&hdev->pdev->dev,
1925 "common waterline config cmd failed %d\n", ret);
1926 return ret;
1927 }
1928
1929 return 0;
1930}
1931
1932int hclge_buffer_alloc(struct hclge_dev *hdev)
1933{
acf61ecd 1934 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1935 int ret;
1936
acf61ecd
YL		 1937 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1938 if (!pkt_buf)
46a3df9f
S		 1939 return -ENOMEM;
1940
acf61ecd 1941 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1942 if (ret) {
1943 dev_err(&hdev->pdev->dev,
1944 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1945 goto out;
9ffe79a9
YL		 1946 }
1947
acf61ecd 1948 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1949 if (ret) {
1950 dev_err(&hdev->pdev->dev,
1951 "could not alloc tx buffers %d\n", ret);
acf61ecd 1952 goto out;
46a3df9f
S		 1953 }
1954
acf61ecd 1955 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1956 if (ret) {
1957 dev_err(&hdev->pdev->dev,
1958 "could not calc rx priv buffer size for all TCs %d\n",
1959 ret);
acf61ecd 1960 goto out;
46a3df9f
S		 1961 }
1962
acf61ecd 1963 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1964 if (ret) {
1965 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1966 ret);
acf61ecd 1967 goto out;
46a3df9f
S		 1968 }
1969
2daf4a65 1970 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1971 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1972 if (ret) {
1973 dev_err(&hdev->pdev->dev,
1974 "could not configure rx private waterline %d\n",
1975 ret);
acf61ecd 1976 goto out;
2daf4a65 1977 }
46a3df9f 1978
acf61ecd 1979 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1980 if (ret) {
1981 dev_err(&hdev->pdev->dev,
1982 "could not configure common threshold %d\n",
1983 ret);
acf61ecd 1984 goto out;
2daf4a65 1985 }
46a3df9f
S		 1986 }
1987
acf61ecd
YL		 1988 ret = hclge_common_wl_config(hdev, pkt_buf);
1989 if (ret)
46a3df9f
S		 1990 dev_err(&hdev->pdev->dev,
1991 "could not configure common waterline %d\n", ret);
46a3df9f 1992
acf61ecd
YL		 1993out:
1994 kfree(pkt_buf);
1995 return ret;
46a3df9f
S		 1996}
1997
1998static int hclge_init_roce_base_info(struct hclge_vport *vport)
1999{
2000 struct hnae3_handle *roce = &vport->roce;
2001 struct hnae3_handle *nic = &vport->nic;
2002
887c3820 2003 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 2004
2005 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2006 vport->back->num_msi_left == 0)
2007 return -EINVAL;
2008
2009 roce->rinfo.base_vector = vport->back->roce_base_vector;
2010
2011 roce->rinfo.netdev = nic->kinfo.netdev;
2012 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2013
2014 roce->pdev = nic->pdev;
2015 roce->ae_algo = nic->ae_algo;
2016 roce->numa_node_mask = nic->numa_node_mask;
2017
2018 return 0;
2019}
2020
887c3820 2021static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 2022{
2023 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 2024 int vectors;
2025 int i;
46a3df9f 2026
887c3820
SM		 2027 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2028 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2029 if (vectors < 0) {
2030 dev_err(&pdev->dev,
2031 "failed(%d) to allocate MSI/MSI-X vectors\n",
2032 vectors);
2033 return vectors;
46a3df9f 2034 }
887c3820
SM		 2035 if (vectors < hdev->num_msi)
2036 dev_warn(&hdev->pdev->dev,
2037 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2038 hdev->num_msi, vectors);
46a3df9f 2039
887c3820
SM		 2040 hdev->num_msi = vectors;
2041 hdev->num_msi_left = vectors;
2042 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 2043 hdev->roce_base_vector = hdev->base_msi_vector +
2044 HCLGE_ROCE_VECTOR_OFFSET;
2045
46a3df9f
S		 2046 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2047 sizeof(u16), GFP_KERNEL);
887c3820
SM		 2048 if (!hdev->vector_status) {
2049 pci_free_irq_vectors(pdev);
46a3df9f 2050 return -ENOMEM;
887c3820 2051 }
46a3df9f
S		 2052
2053 for (i = 0; i < hdev->num_msi; i++)
2054 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2055
887c3820
SM		 2056 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2057 sizeof(int), GFP_KERNEL);
2058 if (!hdev->vector_irq) {
2059 pci_free_irq_vectors(pdev);
2060 return -ENOMEM;
46a3df9f 2061 }
46a3df9f
S		 2062
2063 return 0;
2064}
2065
2066static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2067{
2068 struct hclge_mac *mac = &hdev->hw.mac;
2069
2070 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2071 mac->duplex = (u8)duplex;
2072 else
2073 mac->duplex = HCLGE_MAC_FULL;
2074
2075 mac->speed = speed;
2076}
2077
2078int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2079{
d44f9b63 2080 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2081 struct hclge_desc desc;
2082 int ret;
2083
d44f9b63 2084 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2085
2086 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2087
2088 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2089
2090 switch (speed) {
2091 case HCLGE_MAC_SPEED_10M:
2092 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2093 HCLGE_CFG_SPEED_S, 6);
2094 break;
2095 case HCLGE_MAC_SPEED_100M:
2096 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2097 HCLGE_CFG_SPEED_S, 7);
2098 break;
2099 case HCLGE_MAC_SPEED_1G:
2100 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2101 HCLGE_CFG_SPEED_S, 0);
2102 break;
2103 case HCLGE_MAC_SPEED_10G:
2104 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2105 HCLGE_CFG_SPEED_S, 1);
2106 break;
2107 case HCLGE_MAC_SPEED_25G:
2108 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2109 HCLGE_CFG_SPEED_S, 2);
2110 break;
2111 case HCLGE_MAC_SPEED_40G:
2112 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2113 HCLGE_CFG_SPEED_S, 3);
2114 break;
2115 case HCLGE_MAC_SPEED_50G:
2116 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2117 HCLGE_CFG_SPEED_S, 4);
2118 break;
2119 case HCLGE_MAC_SPEED_100G:
2120 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2121 HCLGE_CFG_SPEED_S, 5);
2122 break;
2123 default:
d7629e74 2124 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2125 return -EINVAL;
2126 }
2127
2128 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2129 1);
2130
2131 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2132 if (ret) {
2133 dev_err(&hdev->pdev->dev,
2134 "mac speed/duplex config cmd failed %d.\n", ret);
2135 return ret;
2136 }
2137
2138 hclge_check_speed_dup(hdev, duplex, speed);
2139
2140 return 0;
2141}
2142
2143static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2144 u8 duplex)
2145{
2146 struct hclge_vport *vport = hclge_get_vport(handle);
2147 struct hclge_dev *hdev = vport->back;
2148
2149 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2150}
2151
2152static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2153 u8 *duplex)
2154{
d44f9b63 2155 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2156 struct hclge_desc desc;
2157 int speed_tmp;
2158 int ret;
2159
d44f9b63 2160 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2161
2162 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2163 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2164 if (ret) {
2165 dev_err(&hdev->pdev->dev,
2166 "mac speed/autoneg/duplex query cmd failed %d\n",
2167 ret);
2168 return ret;
2169 }
2170
2171 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2172 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2173 HCLGE_QUERY_SPEED_S);
2174
2175 ret = hclge_parse_speed(speed_tmp, speed);
2176 if (ret) {
2177 dev_err(&hdev->pdev->dev,
2178 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2179 return -EIO;
2180 }
2181
2182 return 0;
2183}
2184
46a3df9f
S		 2185static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2186{
d44f9b63 2187 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2188 struct hclge_desc desc;
a90bb9a5 2189 u32 flag = 0;
46a3df9f
S		 2190 int ret;
2191
2192 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2193
d44f9b63 2194 req = (struct hclge_config_auto_neg_cmd *)desc.data;
a90bb9a5
YL		 2195 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2196 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2197
2198 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2199 if (ret) {
2200 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2201 ret);
2202 return ret;
2203 }
2204
2205 return 0;
2206}
2207
2208static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2209{
2210 struct hclge_vport *vport = hclge_get_vport(handle);
2211 struct hclge_dev *hdev = vport->back;
2212
2213 return hclge_set_autoneg_en(hdev, enable);
2214}
2215
2216static int hclge_get_autoneg(struct hnae3_handle *handle)
2217{
2218 struct hclge_vport *vport = hclge_get_vport(handle);
2219 struct hclge_dev *hdev = vport->back;
9ff804ee
FL		 2220 struct phy_device *phydev = hdev->hw.mac.phydev;
2221
2222 if (phydev)
2223 return phydev->autoneg;
46a3df9f
S		 2224
2225 return hdev->hw.mac.autoneg;
2226}
2227
6f712727
PL		 2228static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2229 bool mask_vlan,
2230 u8 *mac_mask)
2231{
2232 struct hclge_mac_vlan_mask_entry_cmd *req;
2233 struct hclge_desc desc;
2234 int status;
2235
2236 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2237 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2238
2239 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2240 mask_vlan ? 1 : 0);
2241 ether_addr_copy(req->mac_mask, mac_mask);
2242
2243 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2244 if (status)
2245 dev_err(&hdev->pdev->dev,
2246 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2247 status);
2248
2249 return status;
2250}
2251
46a3df9f
S		 2252static int hclge_mac_init(struct hclge_dev *hdev)
2253{
59bc85ec
FL		 2254 struct hnae3_handle *handle = &hdev->vport[0].nic;
2255 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 2256 struct hclge_mac *mac = &hdev->hw.mac;
6f712727 2257 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
59bc85ec 2258 int mtu;
46a3df9f
S		 2259 int ret;
2260
2261 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2262 if (ret) {
2263 dev_err(&hdev->pdev->dev,
2264 "Config mac speed dup fail ret=%d\n", ret);
2265 return ret;
2266 }
2267
2268 mac->link = 0;
2269
46a3df9f
S		 2270 /* Initialize the MTA table work mode */
2271 hdev->accept_mta_mc = true;
2272 hdev->enable_mta = true;
2273 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2274
2275 ret = hclge_set_mta_filter_mode(hdev,
2276 hdev->mta_mac_sel_type,
2277 hdev->enable_mta);
2278 if (ret) {
2279 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2280 ret);
2281 return ret;
2282 }
2283
6f712727
PL		 2284 ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2285 if (ret) {
2286 dev_err(&hdev->pdev->dev,
2287 "set mta filter mode fail ret=%d\n", ret);
2288 return ret;
2289 }
2290
2291 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
59bc85ec 2292 if (ret) {
6f712727
PL		 2293 dev_err(&hdev->pdev->dev,
2294 "set default mac_vlan_mask fail ret=%d\n", ret);
59bc85ec
FL		 2295 return ret;
2296 }
6f712727 2297
59bc85ec
FL		 2298 if (netdev)
2299 mtu = netdev->mtu;
2300 else
2301 mtu = ETH_DATA_LEN;
2302
2303 ret = hclge_set_mtu(handle, mtu);
2304 if (ret) {
2305 dev_err(&hdev->pdev->dev,
2306 "set mtu failed ret=%d\n", ret);
2307 return ret;
2308 }
2309
2310 return 0;
46a3df9f
S		 2311}
2312
22fd3468
SM		 2313static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2314{
2315 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2316 schedule_work(&hdev->mbx_service_task);
2317}
2318
ed4a1bb8
SM		 2319static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2320{
2321 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2322 schedule_work(&hdev->rst_service_task);
2323}
2324
46a3df9f
S		 2325static void hclge_task_schedule(struct hclge_dev *hdev)
2326{
2327 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2328 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2329 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2330 (void)schedule_work(&hdev->service_task);
2331}
2332
2333static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2334{
d44f9b63 2335 struct hclge_link_status_cmd *req;
46a3df9f
S		 2336 struct hclge_desc desc;
2337 int link_status;
2338 int ret;
2339
2340 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2341 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2342 if (ret) {
2343 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2344 ret);
2345 return ret;
2346 }
2347
d44f9b63 2348 req = (struct hclge_link_status_cmd *)desc.data;
46a3df9f
S		 2349 link_status = req->status & HCLGE_LINK_STATUS;
2350
2351 return !!link_status;
2352}
2353
2354static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2355{
2356 int mac_state;
2357 int link_stat;
2358
2359 mac_state = hclge_get_mac_link_status(hdev);
2360
2361 if (hdev->hw.mac.phydev) {
2362 if (!genphy_read_status(hdev->hw.mac.phydev))
2363 link_stat = mac_state &
2364 hdev->hw.mac.phydev->link;
2365 else
2366 link_stat = 0;
2367
2368 } else {
2369 link_stat = mac_state;
2370 }
2371
2372 return !!link_stat;
2373}
2374
2375static void hclge_update_link_status(struct hclge_dev *hdev)
2376{
2377 struct hnae3_client *client = hdev->nic_client;
2378 struct hnae3_handle *handle;
2379 int state;
2380 int i;
2381
2382 if (!client)
2383 return;
2384 state = hclge_get_mac_phy_link(hdev);
2385 if (state != hdev->hw.mac.link) {
2386 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2387 handle = &hdev->vport[i].nic;
2388 client->ops->link_status_change(handle, state);
2389 }
2390 hdev->hw.mac.link = state;
2391 }
2392}
2393
2394static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2395{
2396 struct hclge_mac mac = hdev->hw.mac;
2397 u8 duplex;
2398 int speed;
2399 int ret;
2400
2401 /* get the speed and duplex as autoneg'result from mac cmd when phy
2402 * doesn't exit.
2403 */
c040366b 2404 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2405 return 0;
2406
2407 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2408 if (ret) {
2409 dev_err(&hdev->pdev->dev,
2410 "mac autoneg/speed/duplex query failed %d\n", ret);
2411 return ret;
2412 }
2413
2414 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2415 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2416 if (ret) {
2417 dev_err(&hdev->pdev->dev,
2418 "mac speed/duplex config failed %d\n", ret);
2419 return ret;
2420 }
2421 }
2422
2423 return 0;
2424}
2425
2426static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2427{
2428 struct hclge_vport *vport = hclge_get_vport(handle);
2429 struct hclge_dev *hdev = vport->back;
2430
2431 return hclge_update_speed_duplex(hdev);
2432}
2433
2434static int hclge_get_status(struct hnae3_handle *handle)
2435{
2436 struct hclge_vport *vport = hclge_get_vport(handle);
2437 struct hclge_dev *hdev = vport->back;
2438
2439 hclge_update_link_status(hdev);
2440
2441 return hdev->hw.mac.link;
2442}
2443
d039ef68 2444static void hclge_service_timer(struct timer_list *t)
46a3df9f 2445{
d039ef68 2446 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2447
d039ef68 2448 mod_timer(&hdev->service_timer, jiffies + HZ);
7a5d2a39 2449 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2450 hclge_task_schedule(hdev);
2451}
2452
2453static void hclge_service_complete(struct hclge_dev *hdev)
2454{
2455 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2456
2457 /* Flush memory before next watchdog */
2458 smp_mb__before_atomic();
2459 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2460}
2461
202f2014
SM		 2462static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2463{
2464 u32 rst_src_reg;
22fd3468 2465 u32 cmdq_src_reg;
202f2014
SM		 2466
2467 /* fetch the events from their corresponding regs */
2468 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
22fd3468
SM		 2469 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2470
2471 /* Assumption: If by any chance reset and mailbox events are reported
2472 * together then we will only process reset event in this go and will
2473 * defer the processing of the mailbox events. Since, we would have not
2474 * cleared RX CMDQ event this time we would receive again another
2475 * interrupt from H/W just for the mailbox.
2476 */
202f2014
SM		 2477
2478 /* check for vector0 reset event sources */
2479 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2480 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2481 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2482 return HCLGE_VECTOR0_EVENT_RST;
2483 }
2484
2485 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2486 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2487 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2488 return HCLGE_VECTOR0_EVENT_RST;
2489 }
2490
2491 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2492 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2493 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2494 return HCLGE_VECTOR0_EVENT_RST;
2495 }
2496
22fd3468
SM		 2497 /* check for vector0 mailbox(=CMDQ RX) event source */
2498 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2499 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2500 *clearval = cmdq_src_reg;
2501 return HCLGE_VECTOR0_EVENT_MBX;
2502 }
202f2014
SM		 2503
2504 return HCLGE_VECTOR0_EVENT_OTHER;
2505}
2506
2507static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2508 u32 regclr)
2509{
22fd3468
SM		 2510 switch (event_type) {
2511 case HCLGE_VECTOR0_EVENT_RST:
202f2014 2512 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
22fd3468
SM		 2513 break;
2514 case HCLGE_VECTOR0_EVENT_MBX:
2515 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2516 break;
2517 }
202f2014
SM		 2518}
2519
466b0c00
L		 2520static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2521{
2522 writel(enable ? 1 : 0, vector->addr);
2523}
2524
2525static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2526{
2527 struct hclge_dev *hdev = data;
202f2014
SM		 2528 u32 event_cause;
2529 u32 clearval;
466b0c00
L		 2530
2531 hclge_enable_vector(&hdev->misc_vector, false);
202f2014
SM		 2532 event_cause = hclge_check_event_cause(hdev, &clearval);
2533
22fd3468 2534 /* vector 0 interrupt is shared with reset and mailbox source events.*/
202f2014
SM		 2535 switch (event_cause) {
2536 case HCLGE_VECTOR0_EVENT_RST:
ed4a1bb8 2537 hclge_reset_task_schedule(hdev);
202f2014 2538 break;
22fd3468
SM		 2539 case HCLGE_VECTOR0_EVENT_MBX:
2540 /* If we are here then,
2541 * 1. Either we are not handling any mbx task and we are not
2542 * scheduled as well
2543 * OR
2544 * 2. We could be handling a mbx task but nothing more is
2545 * scheduled.
2546 * In both cases, we should schedule mbx task as there are more
2547 * mbx messages reported by this interrupt.
2548 */
2549 hclge_mbx_task_schedule(hdev);
2550
202f2014
SM		 2551 default:
2552 dev_dbg(&hdev->pdev->dev,
2553 "received unknown or unhandled event of vector0\n");
2554 break;
2555 }
2556
2557 /* we should clear the source of interrupt */
2558 hclge_clear_event_cause(hdev, event_cause, clearval);
2559 hclge_enable_vector(&hdev->misc_vector, true);
466b0c00
L		 2560
2561 return IRQ_HANDLED;
2562}
2563
2564static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2565{
2566 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2567 hdev->num_msi_left += 1;
2568 hdev->num_msi_used -= 1;
2569}
2570
2571static void hclge_get_misc_vector(struct hclge_dev *hdev)
2572{
2573 struct hclge_misc_vector *vector = &hdev->misc_vector;
2574
2575 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2576
2577 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2578 hdev->vector_status[0] = 0;
2579
2580 hdev->num_msi_left -= 1;
2581 hdev->num_msi_used += 1;
2582}
2583
2584static int hclge_misc_irq_init(struct hclge_dev *hdev)
2585{
2586 int ret;
2587
2588 hclge_get_misc_vector(hdev);
2589
202f2014
SM		 2590 /* this would be explicitly freed in the end */
2591 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2592 0, "hclge_misc", hdev);
466b0c00
L		 2593 if (ret) {
2594 hclge_free_vector(hdev, 0);
2595 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2596 hdev->misc_vector.vector_irq);
2597 }
2598
2599 return ret;
2600}
2601
202f2014
SM		 2602static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2603{
2604 free_irq(hdev->misc_vector.vector_irq, hdev);
2605 hclge_free_vector(hdev, 0);
2606}
2607
4ed340ab
L		 2608static int hclge_notify_client(struct hclge_dev *hdev,
2609 enum hnae3_reset_notify_type type)
2610{
2611 struct hnae3_client *client = hdev->nic_client;
2612 u16 i;
2613
2614 if (!client->ops->reset_notify)
2615 return -EOPNOTSUPP;
2616
2617 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2618 struct hnae3_handle *handle = &hdev->vport[i].nic;
2619 int ret;
2620
2621 ret = client->ops->reset_notify(handle, type);
2622 if (ret)
2623 return ret;
2624 }
2625
2626 return 0;
2627}
2628
2629static int hclge_reset_wait(struct hclge_dev *hdev)
2630{
2631#define HCLGE_RESET_WATI_MS 100
2632#define HCLGE_RESET_WAIT_CNT 5
2633 u32 val, reg, reg_bit;
2634 u32 cnt = 0;
2635
2636 switch (hdev->reset_type) {
2637 case HNAE3_GLOBAL_RESET:
2638 reg = HCLGE_GLOBAL_RESET_REG;
2639 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2640 break;
2641 case HNAE3_CORE_RESET:
2642 reg = HCLGE_GLOBAL_RESET_REG;
2643 reg_bit = HCLGE_CORE_RESET_BIT;
2644 break;
2645 case HNAE3_FUNC_RESET:
2646 reg = HCLGE_FUN_RST_ING;
2647 reg_bit = HCLGE_FUN_RST_ING_B;
2648 break;
2649 default:
2650 dev_err(&hdev->pdev->dev,
2651 "Wait for unsupported reset type: %d\n",
2652 hdev->reset_type);
2653 return -EINVAL;
2654 }
2655
2656 val = hclge_read_dev(&hdev->hw, reg);
2657 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2658 msleep(HCLGE_RESET_WATI_MS);
2659 val = hclge_read_dev(&hdev->hw, reg);
2660 cnt++;
2661 }
2662
4ed340ab
L		 2663 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2664 dev_warn(&hdev->pdev->dev,
2665 "Wait for reset timeout: %d\n", hdev->reset_type);
2666 return -EBUSY;
2667 }
2668
2669 return 0;
2670}
2671
2672static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2673{
2674 struct hclge_desc desc;
2675 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2676 int ret;
2677
2678 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2679 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2680 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2681 req->fun_reset_vfid = func_id;
2682
2683 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2684 if (ret)
2685 dev_err(&hdev->pdev->dev,
2686 "send function reset cmd fail, status =%d\n", ret);
2687
2688 return ret;
2689}
2690
d5752031 2691static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2692{
2693 struct pci_dev *pdev = hdev->pdev;
2694 u32 val;
2695
d5752031 2696 switch (hdev->reset_type) {
4ed340ab
L		 2697 case HNAE3_GLOBAL_RESET:
2698 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2699 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2700 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2701 dev_info(&pdev->dev, "Global Reset requested\n");
2702 break;
2703 case HNAE3_CORE_RESET:
2704 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2705 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2706 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2707 dev_info(&pdev->dev, "Core Reset requested\n");
2708 break;
2709 case HNAE3_FUNC_RESET:
2710 dev_info(&pdev->dev, "PF Reset requested\n");
2711 hclge_func_reset_cmd(hdev, 0);
ed4a1bb8
SM		 2712 /* schedule again to check later */
2713 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2714 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2715 break;
2716 default:
2717 dev_warn(&pdev->dev,
d5752031 2718 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2719 break;
2720 }
2721}
2722
d5752031
SM		 2723static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2724 unsigned long *addr)
2725{
2726 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2727
2728 /* return the highest priority reset level amongst all */
2729 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2730 rst_level = HNAE3_GLOBAL_RESET;
2731 else if (test_bit(HNAE3_CORE_RESET, addr))
2732 rst_level = HNAE3_CORE_RESET;
2733 else if (test_bit(HNAE3_IMP_RESET, addr))
2734 rst_level = HNAE3_IMP_RESET;
2735 else if (test_bit(HNAE3_FUNC_RESET, addr))
2736 rst_level = HNAE3_FUNC_RESET;
2737
2738 /* now, clear all other resets */
2739 clear_bit(HNAE3_GLOBAL_RESET, addr);
2740 clear_bit(HNAE3_CORE_RESET, addr);
2741 clear_bit(HNAE3_IMP_RESET, addr);
2742 clear_bit(HNAE3_FUNC_RESET, addr);
2743
2744 return rst_level;
2745}
2746
2747static void hclge_reset(struct hclge_dev *hdev)
2748{
2749 /* perform reset of the stack & ae device for a client */
2750
2751 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2752
2753 if (!hclge_reset_wait(hdev)) {
2754 rtnl_lock();
2755 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2756 hclge_reset_ae_dev(hdev->ae_dev);
2757 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2758 rtnl_unlock();
2759 } else {
2760 /* schedule again to check pending resets later */
2761 set_bit(hdev->reset_type, &hdev->reset_pending);
2762 hclge_reset_task_schedule(hdev);
2763 }
2764
2765 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2766}
2767
4ed340ab
L		 2768static void hclge_reset_event(struct hnae3_handle *handle,
2769 enum hnae3_reset_type reset)
2770{
2771 struct hclge_vport *vport = hclge_get_vport(handle);
2772 struct hclge_dev *hdev = vport->back;
2773
2774 dev_info(&hdev->pdev->dev,
2775 "Receive reset event , reset_type is %d", reset);
2776
2777 switch (reset) {
2778 case HNAE3_FUNC_RESET:
2779 case HNAE3_CORE_RESET:
2780 case HNAE3_GLOBAL_RESET:
ed4a1bb8
SM		 2781 /* request reset & schedule reset task */
2782 set_bit(reset, &hdev->reset_request);
2783 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2784 break;
2785 default:
2786 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2787 break;
2788 }
2789}
2790
2791static void hclge_reset_subtask(struct hclge_dev *hdev)
2792{
d5752031
SM		 2793 /* check if there is any ongoing reset in the hardware. This status can
2794 * be checked from reset_pending. If there is then, we need to wait for
2795 * hardware to complete reset.
2796 * a. If we are able to figure out in reasonable time that hardware
2797 * has fully resetted then, we can proceed with driver, client
2798 * reset.
2799 * b. else, we can come back later to check this status so re-sched
2800 * now.
2801 */
2802 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2803 if (hdev->reset_type != HNAE3_NONE_RESET)
2804 hclge_reset(hdev);
4ed340ab 2805
d5752031
SM		 2806 /* check if we got any *new* reset requests to be honored */
2807 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2808 if (hdev->reset_type != HNAE3_NONE_RESET)
2809 hclge_do_reset(hdev);
4ed340ab 2810
4ed340ab
L		 2811 hdev->reset_type = HNAE3_NONE_RESET;
2812}
2813
ed4a1bb8 2814static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2815{
ed4a1bb8
SM		 2816 struct hclge_dev *hdev =
2817 container_of(work, struct hclge_dev, rst_service_task);
2818
2819 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2820 return;
2821
2822 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2823
4ed340ab 2824 hclge_reset_subtask(hdev);
ed4a1bb8
SM		 2825
2826 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2827}
2828
22fd3468
SM		 2829static void hclge_mailbox_service_task(struct work_struct *work)
2830{
2831 struct hclge_dev *hdev =
2832 container_of(work, struct hclge_dev, mbx_service_task);
2833
2834 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2835 return;
2836
2837 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2838
2839 hclge_mbx_handler(hdev);
2840
2841 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2842}
2843
46a3df9f
S		 2844static void hclge_service_task(struct work_struct *work)
2845{
2846 struct hclge_dev *hdev =
2847 container_of(work, struct hclge_dev, service_task);
2848
7a5d2a39
JS		 2849 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2850 hclge_update_stats_for_all(hdev);
2851 hdev->hw_stats.stats_timer = 0;
2852 }
2853
46a3df9f
S		 2854 hclge_update_speed_duplex(hdev);
2855 hclge_update_link_status(hdev);
46a3df9f
S		 2856 hclge_service_complete(hdev);
2857}
2858
2859static void hclge_disable_sriov(struct hclge_dev *hdev)
2860{
2a32ca13
AB		 2861 /* If our VFs are assigned we cannot shut down SR-IOV
2862 * without causing issues, so just leave the hardware
2863 * available but disabled
2864 */
2865 if (pci_vfs_assigned(hdev->pdev)) {
2866 dev_warn(&hdev->pdev->dev,
2867 "disabling driver while VFs are assigned\n");
2868 return;
2869 }
46a3df9f 2870
2a32ca13 2871 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2872}
2873
2874struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2875{
2876 /* VF handle has no client */
2877 if (!handle->client)
2878 return container_of(handle, struct hclge_vport, nic);
2879 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2880 return container_of(handle, struct hclge_vport, roce);
2881 else
2882 return container_of(handle, struct hclge_vport, nic);
2883}
2884
2885static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2886 struct hnae3_vector_info *vector_info)
2887{
2888 struct hclge_vport *vport = hclge_get_vport(handle);
2889 struct hnae3_vector_info *vector = vector_info;
2890 struct hclge_dev *hdev = vport->back;
2891 int alloc = 0;
2892 int i, j;
2893
2894 vector_num = min(hdev->num_msi_left, vector_num);
2895
2896 for (j = 0; j < vector_num; j++) {
2897 for (i = 1; i < hdev->num_msi; i++) {
2898 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2899 vector->vector = pci_irq_vector(hdev->pdev, i);
2900 vector->io_addr = hdev->hw.io_base +
2901 HCLGE_VECTOR_REG_BASE +
2902 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2903 vport->vport_id *
2904 HCLGE_VECTOR_VF_OFFSET;
2905 hdev->vector_status[i] = vport->vport_id;
887c3820 2906 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2907
2908 vector++;
2909 alloc++;
2910
2911 break;
2912 }
2913 }
2914 }
2915 hdev->num_msi_left -= alloc;
2916 hdev->num_msi_used += alloc;
2917
2918 return alloc;
2919}
2920
2921static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2922{
2923 int i;
2924
887c3820
SM		 2925 for (i = 0; i < hdev->num_msi; i++)
2926 if (vector == hdev->vector_irq[i])
2927 return i;
2928
46a3df9f
S		 2929 return -EINVAL;
2930}
2931
2932static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2933{
2934 return HCLGE_RSS_KEY_SIZE;
2935}
2936
2937static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2938{
2939 return HCLGE_RSS_IND_TBL_SIZE;
2940}
2941
2942static int hclge_get_rss_algo(struct hclge_dev *hdev)
2943{
d44f9b63 2944 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2945 struct hclge_desc desc;
2946 int rss_hash_algo;
2947 int ret;
2948
2949 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2950
2951 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2952 if (ret) {
2953 dev_err(&hdev->pdev->dev,
2954 "Get link status error, status =%d\n", ret);
2955 return ret;
2956 }
2957
d44f9b63 2958 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2959 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2960
2961 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2962 return ETH_RSS_HASH_TOP;
2963
2964 return -EINVAL;
2965}
2966
2967static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2968 const u8 hfunc, const u8 *key)
2969{
d44f9b63 2970 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2971 struct hclge_desc desc;
2972 int key_offset;
2973 int key_size;
2974 int ret;
2975
d44f9b63 2976 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2977
2978 for (key_offset = 0; key_offset < 3; key_offset++) {
2979 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2980 false);
2981
2982 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2983 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2984
2985 if (key_offset == 2)
2986 key_size =
2987 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2988 else
2989 key_size = HCLGE_RSS_HASH_KEY_NUM;
2990
2991 memcpy(req->hash_key,
2992 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2993
2994 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2995 if (ret) {
2996 dev_err(&hdev->pdev->dev,
2997 "Configure RSS config fail, status = %d\n",
2998 ret);
2999 return ret;
3000 }
3001 }
3002 return 0;
3003}
3004
3005static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
3006{
d44f9b63 3007 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3008 struct hclge_desc desc;
3009 int i, j;
3010 int ret;
3011
d44f9b63 3012 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3013
3014 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3015 hclge_cmd_setup_basic_desc
3016 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3017
a90bb9a5
YL		 3018 req->start_table_index =
3019 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3020 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3021
3022 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3023 req->rss_result[j] =
3024 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3025
3026 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3027 if (ret) {
3028 dev_err(&hdev->pdev->dev,
3029 "Configure rss indir table fail,status = %d\n",
3030 ret);
3031 return ret;
3032 }
3033 }
3034 return 0;
3035}
3036
3037static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3038 u16 *tc_size, u16 *tc_offset)
3039{
d44f9b63 3040 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3041 struct hclge_desc desc;
3042 int ret;
3043 int i;
3044
3045 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3046 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3047
3048 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3049 u16 mode = 0;
3050
3051 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3052 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
46a3df9f 3053 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
a90bb9a5 3054 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
46a3df9f 3055 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3056
3057 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3058 }
3059
3060 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3061 if (ret) {
3062 dev_err(&hdev->pdev->dev,
3063 "Configure rss tc mode fail, status = %d\n", ret);
3064 return ret;
3065 }
3066
3067 return 0;
3068}
3069
3070static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3071{
d44f9b63 3072 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3073 struct hclge_desc desc;
3074 int ret;
3075
3076 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3077
d44f9b63 3078 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
46a3df9f
S		 3079 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3080 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3081 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3082 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3083 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3084 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3085 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3086 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3087 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3088 if (ret) {
3089 dev_err(&hdev->pdev->dev,
3090 "Configure rss input fail, status = %d\n", ret);
3091 return ret;
3092 }
3093
3094 return 0;
3095}
3096
3097static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3098 u8 *key, u8 *hfunc)
3099{
3100 struct hclge_vport *vport = hclge_get_vport(handle);
3101 struct hclge_dev *hdev = vport->back;
3102 int i;
3103
3104 /* Get hash algorithm */
3105 if (hfunc)
3106 *hfunc = hclge_get_rss_algo(hdev);
3107
3108 /* Get the RSS Key required by the user */
3109 if (key)
3110 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3111
3112 /* Get indirect table */
3113 if (indir)
3114 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3115 indir[i] = vport->rss_indirection_tbl[i];
3116
3117 return 0;
3118}
3119
3120static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3121 const u8 *key, const u8 hfunc)
3122{
3123 struct hclge_vport *vport = hclge_get_vport(handle);
3124 struct hclge_dev *hdev = vport->back;
3125 u8 hash_algo;
3126 int ret, i;
3127
3128 /* Set the RSS Hash Key if specififed by the user */
3129 if (key) {
3130 /* Update the shadow RSS key with user specified qids */
3131 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3132
3133 if (hfunc == ETH_RSS_HASH_TOP ||
3134 hfunc == ETH_RSS_HASH_NO_CHANGE)
3135 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3136 else
3137 return -EINVAL;
3138 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3139 if (ret)
3140 return ret;
3141 }
3142
3143 /* Update the shadow RSS table with user specified qids */
3144 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3145 vport->rss_indirection_tbl[i] = indir[i];
3146
3147 /* Update the hardware */
3148 ret = hclge_set_rss_indir_table(hdev, indir);
3149 return ret;
3150}
3151
f7db940a
L		 3152static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3153{
3154 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3155
3156 if (nfc->data & RXH_L4_B_2_3)
3157 hash_sets |= HCLGE_D_PORT_BIT;
3158 else
3159 hash_sets &= ~HCLGE_D_PORT_BIT;
3160
3161 if (nfc->data & RXH_IP_SRC)
3162 hash_sets |= HCLGE_S_IP_BIT;
3163 else
3164 hash_sets &= ~HCLGE_S_IP_BIT;
3165
3166 if (nfc->data & RXH_IP_DST)
3167 hash_sets |= HCLGE_D_IP_BIT;
3168 else
3169 hash_sets &= ~HCLGE_D_IP_BIT;
3170
3171 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3172 hash_sets |= HCLGE_V_TAG_BIT;
3173
3174 return hash_sets;
3175}
3176
3177static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3178 struct ethtool_rxnfc *nfc)
3179{
3180 struct hclge_vport *vport = hclge_get_vport(handle);
3181 struct hclge_dev *hdev = vport->back;
3182 struct hclge_rss_input_tuple_cmd *req;
3183 struct hclge_desc desc;
3184 u8 tuple_sets;
3185 int ret;
3186
3187 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3188 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3189 return -EINVAL;
3190
3191 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3192 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3193 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3194 if (ret) {
3195 dev_err(&hdev->pdev->dev,
3196 "Read rss tuple fail, status = %d\n", ret);
3197 return ret;
3198 }
3199
3200 hclge_cmd_reuse_desc(&desc, false);
3201
3202 tuple_sets = hclge_get_rss_hash_bits(nfc);
3203 switch (nfc->flow_type) {
3204 case TCP_V4_FLOW:
3205 req->ipv4_tcp_en = tuple_sets;
3206 break;
3207 case TCP_V6_FLOW:
3208 req->ipv6_tcp_en = tuple_sets;
3209 break;
3210 case UDP_V4_FLOW:
3211 req->ipv4_udp_en = tuple_sets;
3212 break;
3213 case UDP_V6_FLOW:
3214 req->ipv6_udp_en = tuple_sets;
3215 break;
3216 case SCTP_V4_FLOW:
3217 req->ipv4_sctp_en = tuple_sets;
3218 break;
3219 case SCTP_V6_FLOW:
3220 if ((nfc->data & RXH_L4_B_0_1) ||
3221 (nfc->data & RXH_L4_B_2_3))
3222 return -EINVAL;
3223
3224 req->ipv6_sctp_en = tuple_sets;
3225 break;
3226 case IPV4_FLOW:
3227 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3228 break;
3229 case IPV6_FLOW:
3230 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3231 break;
3232 default:
3233 return -EINVAL;
3234 }
3235
3236 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3237 if (ret)
3238 dev_err(&hdev->pdev->dev,
3239 "Set rss tuple fail, status = %d\n", ret);
3240
3241 return ret;
3242}
3243
07d29954
L		 3244static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3245 struct ethtool_rxnfc *nfc)
3246{
3247 struct hclge_vport *vport = hclge_get_vport(handle);
3248 struct hclge_dev *hdev = vport->back;
3249 struct hclge_rss_input_tuple_cmd *req;
3250 struct hclge_desc desc;
3251 u8 tuple_sets;
3252 int ret;
3253
3254 nfc->data = 0;
3255
3256 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3257 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3258 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3259 if (ret) {
3260 dev_err(&hdev->pdev->dev,
3261 "Read rss tuple fail, status = %d\n", ret);
3262 return ret;
3263 }
3264
3265 switch (nfc->flow_type) {
3266 case TCP_V4_FLOW:
3267 tuple_sets = req->ipv4_tcp_en;
3268 break;
3269 case UDP_V4_FLOW:
3270 tuple_sets = req->ipv4_udp_en;
3271 break;
3272 case TCP_V6_FLOW:
3273 tuple_sets = req->ipv6_tcp_en;
3274 break;
3275 case UDP_V6_FLOW:
3276 tuple_sets = req->ipv6_udp_en;
3277 break;
3278 case SCTP_V4_FLOW:
3279 tuple_sets = req->ipv4_sctp_en;
3280 break;
3281 case SCTP_V6_FLOW:
3282 tuple_sets = req->ipv6_sctp_en;
3283 break;
3284 case IPV4_FLOW:
3285 case IPV6_FLOW:
3286 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3287 break;
3288 default:
3289 return -EINVAL;
3290 }
3291
3292 if (!tuple_sets)
3293 return 0;
3294
3295 if (tuple_sets & HCLGE_D_PORT_BIT)
3296 nfc->data |= RXH_L4_B_2_3;
3297 if (tuple_sets & HCLGE_S_PORT_BIT)
3298 nfc->data |= RXH_L4_B_0_1;
3299 if (tuple_sets & HCLGE_D_IP_BIT)
3300 nfc->data |= RXH_IP_DST;
3301 if (tuple_sets & HCLGE_S_IP_BIT)
3302 nfc->data |= RXH_IP_SRC;
3303
3304 return 0;
3305}
3306
46a3df9f
S		 3307static int hclge_get_tc_size(struct hnae3_handle *handle)
3308{
3309 struct hclge_vport *vport = hclge_get_vport(handle);
3310 struct hclge_dev *hdev = vport->back;
3311
3312 return hdev->rss_size_max;
3313}
3314
77f255c1 3315int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f
S		 3316{
3317 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3318 struct hclge_vport *vport = hdev->vport;
3319 u16 tc_offset[HCLGE_MAX_TC_NUM];
3320 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3321 u16 tc_valid[HCLGE_MAX_TC_NUM];
3322 u16 tc_size[HCLGE_MAX_TC_NUM];
3323 u32 *rss_indir = NULL;
68ece54e 3324 u16 rss_size = 0, roundup_size;
46a3df9f
S		 3325 const u8 *key;
3326 int i, ret, j;
3327
3328 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3329 if (!rss_indir)
3330 return -ENOMEM;
3331
3332 /* Get default RSS key */
3333 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3334
3335 /* Initialize RSS indirect table for each vport */
3336 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3337 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3338 vport[j].rss_indirection_tbl[i] =
68ece54e
YL		 3339 i % vport[j].alloc_rss_size;
3340
3341 /* vport 0 is for PF */
3342 if (j != 0)
3343 continue;
3344
3345 rss_size = vport[j].alloc_rss_size;
46a3df9f
S		 3346 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3347 }
3348 }
3349 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3350 if (ret)
3351 goto err;
3352
3353 key = rss_key;
3354 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3355 if (ret)
3356 goto err;
3357
3358 ret = hclge_set_rss_input_tuple(hdev);
3359 if (ret)
3360 goto err;
3361
68ece54e
YL		 3362 /* Each TC have the same queue size, and tc_size set to hardware is
3363 * the log2 of roundup power of two of rss_size, the acutal queue
3364 * size is limited by indirection table.
3365 */
3366 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3367 dev_err(&hdev->pdev->dev,
3368 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3369 rss_size);
81359617
CJ		 3370 ret = -EINVAL;
3371 goto err;
68ece54e
YL		 3372 }
3373
3374 roundup_size = roundup_pow_of_two(rss_size);
3375 roundup_size = ilog2(roundup_size);
3376
46a3df9f 3377 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3378 tc_valid[i] = 0;
46a3df9f 3379
68ece54e
YL		 3380 if (!(hdev->hw_tc_map & BIT(i)))
3381 continue;
3382
3383 tc_valid[i] = 1;
3384 tc_size[i] = roundup_size;
3385 tc_offset[i] = rss_size * i;
46a3df9f 3386 }
68ece54e 3387
46a3df9f
S		 3388 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3389
3390err:
3391 kfree(rss_indir);
3392
3393 return ret;
3394}
3395
63d7e66f
SM		 3396int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3397 int vector_id, bool en,
3398 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3399{
3400 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3401 struct hnae3_ring_chain_node *node;
3402 struct hclge_desc desc;
63d7e66f
SM		 3403 struct hclge_ctrl_vector_chain_cmd *req
3404 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3405 enum hclge_cmd_status status;
3406 enum hclge_opcode_type op;
3407 u16 tqp_type_and_id;
46a3df9f
S		 3408 int i;
3409
63d7e66f
SM		 3410 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3411 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3412 req->int_vector_id = vector_id;
3413
3414 i = 0;
3415 for (node = ring_chain; node; node = node->next) {
63d7e66f
SM		 3416 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3417 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3418 HCLGE_INT_TYPE_S,
46a3df9f 3419 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
63d7e66f
SM		 3420 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3421 HCLGE_TQP_ID_S, node->tqp_index);
f230c6c5
FL		 3422 hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3423 HCLGE_INT_GL_IDX_S,
3424 hnae_get_field(node->int_gl_idx,
3425 HNAE3_RING_GL_IDX_M,
3426 HNAE3_RING_GL_IDX_S));
63d7e66f 3427 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3428 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3429 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
63d7e66f 3430 req->vfid = vport->vport_id;
46a3df9f 3431
63d7e66f
SM		 3432 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3433 if (status) {
46a3df9f
S		 3434 dev_err(&hdev->pdev->dev,
3435 "Map TQP fail, status is %d.\n",
63d7e66f
SM		 3436 status);
3437 return -EIO;
46a3df9f
S		 3438 }
3439 i = 0;
3440
3441 hclge_cmd_setup_basic_desc(&desc,
63d7e66f 3442 op,
46a3df9f
S		 3443 false);
3444 req->int_vector_id = vector_id;
3445 }
3446 }
3447
3448 if (i > 0) {
3449 req->int_cause_num = i;
63d7e66f
SM		 3450 req->vfid = vport->vport_id;
3451 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3452 if (status) {
46a3df9f 3453 dev_err(&hdev->pdev->dev,
63d7e66f
SM		 3454 "Map TQP fail, status is %d.\n", status);
3455 return -EIO;
46a3df9f
S		 3456 }
3457 }
3458
3459 return 0;
3460}
3461
63d7e66f
SM		 3462static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3463 int vector,
3464 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3465{
3466 struct hclge_vport *vport = hclge_get_vport(handle);
3467 struct hclge_dev *hdev = vport->back;
3468 int vector_id;
3469
3470 vector_id = hclge_get_vector_index(hdev, vector);
3471 if (vector_id < 0) {
3472 dev_err(&hdev->pdev->dev,
63d7e66f 3473 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3474 return vector_id;
3475 }
3476
63d7e66f 3477 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3478}
3479
63d7e66f
SM		 3480static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3481 int vector,
3482 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3483{
3484 struct hclge_vport *vport = hclge_get_vport(handle);
3485 struct hclge_dev *hdev = vport->back;
63d7e66f 3486 int vector_id, ret;
46a3df9f
S		 3487
3488 vector_id = hclge_get_vector_index(hdev, vector);
3489 if (vector_id < 0) {
3490 dev_err(&handle->pdev->dev,
3491 "Get vector index fail. ret =%d\n", vector_id);
3492 return vector_id;
3493 }
3494
63d7e66f
SM		 3495 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3496 if (ret) {
3497 dev_err(&handle->pdev->dev,
3498 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3499 vector_id,
3500 ret);
3501 return ret;
46a3df9f
S		 3502 }
3503
63d7e66f
SM		 3504 /* Free this MSIX or MSI vector */
3505 hclge_free_vector(hdev, vector_id);
46a3df9f
S		 3506
3507 return 0;
3508}
3509
3510int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3511 struct hclge_promisc_param *param)
3512{
d44f9b63 3513 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3514 struct hclge_desc desc;
3515 int ret;
3516
3517 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3518
d44f9b63 3519 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f
S		 3520 req->vf_id = param->vf_id;
3521 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3522
3523 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3524 if (ret) {
3525 dev_err(&hdev->pdev->dev,
3526 "Set promisc mode fail, status is %d.\n", ret);
3527 return ret;
3528 }
3529 return 0;
3530}
3531
3532void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3533 bool en_mc, bool en_bc, int vport_id)
3534{
3535 if (!param)
3536 return;
3537
3538 memset(param, 0, sizeof(struct hclge_promisc_param));
3539 if (en_uc)
3540 param->enable = HCLGE_PROMISC_EN_UC;
3541 if (en_mc)
3542 param->enable |= HCLGE_PROMISC_EN_MC;
3543 if (en_bc)
3544 param->enable |= HCLGE_PROMISC_EN_BC;
3545 param->vf_id = vport_id;
3546}
3547
3548static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3549{
3550 struct hclge_vport *vport = hclge_get_vport(handle);
3551 struct hclge_dev *hdev = vport->back;
3552 struct hclge_promisc_param param;
3553
3554 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3555 hclge_cmd_set_promisc_mode(hdev, &param);
3556}
3557
3558static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3559{
3560 struct hclge_desc desc;
d44f9b63
YL		 3561 struct hclge_config_mac_mode_cmd *req =
3562 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3563 u32 loop_en = 0;
46a3df9f
S		 3564 int ret;
3565
3566 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
a90bb9a5
YL		 3567 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3568 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3569 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3570 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3571 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3572 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3573 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3574 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3575 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3576 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3577 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3578 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3579 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3580 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3581 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3582
3583 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3584 if (ret)
3585 dev_err(&hdev->pdev->dev,
3586 "mac enable fail, ret =%d.\n", ret);
3587}
3588
c39c4d98
YL		 3589static int hclge_set_loopback(struct hnae3_handle *handle,
3590 enum hnae3_loop loop_mode, bool en)
3591{
3592 struct hclge_vport *vport = hclge_get_vport(handle);
3593 struct hclge_config_mac_mode_cmd *req;
3594 struct hclge_dev *hdev = vport->back;
3595 struct hclge_desc desc;
3596 u32 loop_en;
3597 int ret;
3598
3599 switch (loop_mode) {
3600 case HNAE3_MAC_INTER_LOOP_MAC:
3601 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3602 /* 1 Read out the MAC mode config at first */
3603 hclge_cmd_setup_basic_desc(&desc,
3604 HCLGE_OPC_CONFIG_MAC_MODE,
3605 true);
3606 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3607 if (ret) {
3608 dev_err(&hdev->pdev->dev,
3609 "mac loopback get fail, ret =%d.\n",
3610 ret);
3611 return ret;
3612 }
3613
3614 /* 2 Then setup the loopback flag */
3615 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3616 if (en)
3617 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3618 else
3619 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3620
3621 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3622
3623 /* 3 Config mac work mode with loopback flag
3624 * and its original configure parameters
3625 */
3626 hclge_cmd_reuse_desc(&desc, false);
3627 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3628 if (ret)
3629 dev_err(&hdev->pdev->dev,
3630 "mac loopback set fail, ret =%d.\n", ret);
3631 break;
3632 default:
3633 ret = -ENOTSUPP;
3634 dev_err(&hdev->pdev->dev,
3635 "loop_mode %d is not supported\n", loop_mode);
3636 break;
3637 }
3638
3639 return ret;
3640}
3641
46a3df9f
S		 3642static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3643 int stream_id, bool enable)
3644{
3645 struct hclge_desc desc;
d44f9b63
YL		 3646 struct hclge_cfg_com_tqp_queue_cmd *req =
3647 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3648 int ret;
3649
3650 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3651 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3652 req->stream_id = cpu_to_le16(stream_id);
3653 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3654
3655 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3656 if (ret)
3657 dev_err(&hdev->pdev->dev,
3658 "Tqp enable fail, status =%d.\n", ret);
3659 return ret;
3660}
3661
3662static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3663{
3664 struct hclge_vport *vport = hclge_get_vport(handle);
3665 struct hnae3_queue *queue;
3666 struct hclge_tqp *tqp;
3667 int i;
3668
3669 for (i = 0; i < vport->alloc_tqps; i++) {
3670 queue = handle->kinfo.tqp[i];
3671 tqp = container_of(queue, struct hclge_tqp, q);
3672 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3673 }
3674}
3675
3676static int hclge_ae_start(struct hnae3_handle *handle)
3677{
3678 struct hclge_vport *vport = hclge_get_vport(handle);
3679 struct hclge_dev *hdev = vport->back;
3680 int i, queue_id, ret;
3681
3682 for (i = 0; i < vport->alloc_tqps; i++) {
3683 /* todo clear interrupt */
3684 /* ring enable */
3685 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3686 if (queue_id < 0) {
3687 dev_warn(&hdev->pdev->dev,
3688 "Get invalid queue id, ignore it\n");
3689 continue;
3690 }
3691
3692 hclge_tqp_enable(hdev, queue_id, 0, true);
3693 }
3694 /* mac enable */
3695 hclge_cfg_mac_mode(hdev, true);
3696 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3697 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 3698
3699 ret = hclge_mac_start_phy(hdev);
3700 if (ret)
3701 return ret;
3702
3703 /* reset tqp stats */
3704 hclge_reset_tqp_stats(handle);
3705
3706 return 0;
3707}
3708
3709static void hclge_ae_stop(struct hnae3_handle *handle)
3710{
3711 struct hclge_vport *vport = hclge_get_vport(handle);
3712 struct hclge_dev *hdev = vport->back;
3713 int i, queue_id;
3714
3715 for (i = 0; i < vport->alloc_tqps; i++) {
3716 /* Ring disable */
3717 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3718 if (queue_id < 0) {
3719 dev_warn(&hdev->pdev->dev,
3720 "Get invalid queue id, ignore it\n");
3721 continue;
3722 }
3723
3724 hclge_tqp_enable(hdev, queue_id, 0, false);
3725 }
3726 /* Mac disable */
3727 hclge_cfg_mac_mode(hdev, false);
3728
3729 hclge_mac_stop_phy(hdev);
3730
3731 /* reset tqp stats */
3732 hclge_reset_tqp_stats(handle);
3733}
3734
3735static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3736 u16 cmdq_resp, u8 resp_code,
3737 enum hclge_mac_vlan_tbl_opcode op)
3738{
3739 struct hclge_dev *hdev = vport->back;
3740 int return_status = -EIO;
3741
3742 if (cmdq_resp) {
3743 dev_err(&hdev->pdev->dev,
3744 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3745 cmdq_resp);
3746 return -EIO;
3747 }
3748
3749 if (op == HCLGE_MAC_VLAN_ADD) {
3750 if ((!resp_code) || (resp_code == 1)) {
3751 return_status = 0;
3752 } else if (resp_code == 2) {
3753 return_status = -EIO;
3754 dev_err(&hdev->pdev->dev,
3755 "add mac addr failed for uc_overflow.\n");
3756 } else if (resp_code == 3) {
3757 return_status = -EIO;
3758 dev_err(&hdev->pdev->dev,
3759 "add mac addr failed for mc_overflow.\n");
3760 } else {
3761 dev_err(&hdev->pdev->dev,
3762 "add mac addr failed for undefined, code=%d.\n",
3763 resp_code);
3764 }
3765 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3766 if (!resp_code) {
3767 return_status = 0;
3768 } else if (resp_code == 1) {
3769 return_status = -EIO;
3770 dev_dbg(&hdev->pdev->dev,
3771 "remove mac addr failed for miss.\n");
3772 } else {
3773 dev_err(&hdev->pdev->dev,
3774 "remove mac addr failed for undefined, code=%d.\n",
3775 resp_code);
3776 }
3777 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3778 if (!resp_code) {
3779 return_status = 0;
3780 } else if (resp_code == 1) {
3781 return_status = -EIO;
3782 dev_dbg(&hdev->pdev->dev,
3783 "lookup mac addr failed for miss.\n");
3784 } else {
3785 dev_err(&hdev->pdev->dev,
3786 "lookup mac addr failed for undefined, code=%d.\n",
3787 resp_code);
3788 }
3789 } else {
3790 return_status = -EIO;
3791 dev_err(&hdev->pdev->dev,
3792 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3793 op);
3794 }
3795
3796 return return_status;
3797}
3798
3799static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3800{
3801 int word_num;
3802 int bit_num;
3803
3804 if (vfid > 255 || vfid < 0)
3805 return -EIO;
3806
3807 if (vfid >= 0 && vfid <= 191) {
3808 word_num = vfid / 32;
3809 bit_num = vfid % 32;
3810 if (clr)
a90bb9a5 3811 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3812 else
a90bb9a5 3813 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3814 } else {
3815 word_num = (vfid - 192) / 32;
3816 bit_num = vfid % 32;
3817 if (clr)
a90bb9a5 3818 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3819 else
a90bb9a5 3820 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3821 }
3822
3823 return 0;
3824}
3825
3826static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3827{
3828#define HCLGE_DESC_NUMBER 3
3829#define HCLGE_FUNC_NUMBER_PER_DESC 6
3830 int i, j;
3831
3832 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3833 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3834 if (desc[i].data[j])
3835 return false;
3836
3837 return true;
3838}
3839
d44f9b63 3840static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3841 const u8 *addr)
3842{
3843 const unsigned char *mac_addr = addr;
3844 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3845 (mac_addr[0]) | (mac_addr[1] << 8);
3846 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3847
3848 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3849 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3850}
3851
1db9b1bf
YL		 3852static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3853 const u8 *addr)
46a3df9f
S		 3854{
3855 u16 high_val = addr[1] | (addr[0] << 8);
3856 struct hclge_dev *hdev = vport->back;
3857 u32 rsh = 4 - hdev->mta_mac_sel_type;
3858 u16 ret_val = (high_val >> rsh) & 0xfff;
3859
3860 return ret_val;
3861}
3862
3863static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3864 enum hclge_mta_dmac_sel_type mta_mac_sel,
3865 bool enable)
3866{
d44f9b63 3867 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3868 struct hclge_desc desc;
3869 int ret;
3870
d44f9b63 3871 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3872 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3873
3874 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3875 enable);
3876 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3877 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3878
3879 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3880 if (ret) {
3881 dev_err(&hdev->pdev->dev,
3882 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3883 ret);
3884 return ret;
3885 }
3886
3887 return 0;
3888}
3889
3890int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3891 u8 func_id,
3892 bool enable)
3893{
d44f9b63 3894 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3895 struct hclge_desc desc;
3896 int ret;
3897
d44f9b63 3898 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3899 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3900
3901 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3902 enable);
3903 req->function_id = func_id;
3904
3905 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3906 if (ret) {
3907 dev_err(&hdev->pdev->dev,
3908 "Config func_id enable failed for cmd_send, ret =%d.\n",
3909 ret);
3910 return ret;
3911 }
3912
3913 return 0;
3914}
3915
3916static int hclge_set_mta_table_item(struct hclge_vport *vport,
3917 u16 idx,
3918 bool enable)
3919{
3920 struct hclge_dev *hdev = vport->back;
d44f9b63 3921 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3922 struct hclge_desc desc;
a90bb9a5 3923 u16 item_idx = 0;
46a3df9f
S		 3924 int ret;
3925
d44f9b63 3926 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f
S		 3927 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3928 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3929
a90bb9a5 3930 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
46a3df9f 3931 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3932 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3933
3934 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3935 if (ret) {
3936 dev_err(&hdev->pdev->dev,
3937 "Config mta table item failed for cmd_send, ret =%d.\n",
3938 ret);
3939 return ret;
3940 }
3941
3942 return 0;
3943}
3944
3945static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3946 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3947{
3948 struct hclge_dev *hdev = vport->back;
3949 struct hclge_desc desc;
3950 u8 resp_code;
a90bb9a5 3951 u16 retval;
46a3df9f
S		 3952 int ret;
3953
3954 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3955
d44f9b63 3956 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3957
3958 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3959 if (ret) {
3960 dev_err(&hdev->pdev->dev,
3961 "del mac addr failed for cmd_send, ret =%d.\n",
3962 ret);
3963 return ret;
3964 }
a90bb9a5
YL		 3965 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3966 retval = le16_to_cpu(desc.retval);
46a3df9f 3967
a90bb9a5 3968 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3969 HCLGE_MAC_VLAN_REMOVE);
3970}
3971
3972static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3973 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3974 struct hclge_desc *desc,
3975 bool is_mc)
3976{
3977 struct hclge_dev *hdev = vport->back;
3978 u8 resp_code;
a90bb9a5 3979 u16 retval;
46a3df9f
S		 3980 int ret;
3981
3982 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3983 if (is_mc) {
3984 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3985 memcpy(desc[0].data,
3986 req,
d44f9b63 3987 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3988 hclge_cmd_setup_basic_desc(&desc[1],
3989 HCLGE_OPC_MAC_VLAN_ADD,
3990 true);
3991 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3992 hclge_cmd_setup_basic_desc(&desc[2],
3993 HCLGE_OPC_MAC_VLAN_ADD,
3994 true);
3995 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3996 } else {
3997 memcpy(desc[0].data,
3998 req,
d44f9b63 3999 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4000 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4001 }
4002 if (ret) {
4003 dev_err(&hdev->pdev->dev,
4004 "lookup mac addr failed for cmd_send, ret =%d.\n",
4005 ret);
4006 return ret;
4007 }
a90bb9a5
YL		 4008 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4009 retval = le16_to_cpu(desc[0].retval);
46a3df9f 4010
a90bb9a5 4011 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4012 HCLGE_MAC_VLAN_LKUP);
4013}
4014
4015static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4016 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4017 struct hclge_desc *mc_desc)
4018{
4019 struct hclge_dev *hdev = vport->back;
4020 int cfg_status;
4021 u8 resp_code;
a90bb9a5 4022 u16 retval;
46a3df9f
S		 4023 int ret;
4024
4025 if (!mc_desc) {
4026 struct hclge_desc desc;
4027
4028 hclge_cmd_setup_basic_desc(&desc,
4029 HCLGE_OPC_MAC_VLAN_ADD,
4030 false);
d44f9b63
YL		 4031 memcpy(desc.data, req,
4032 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4033 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 4034 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4035 retval = le16_to_cpu(desc.retval);
4036
4037 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4038 resp_code,
4039 HCLGE_MAC_VLAN_ADD);
4040 } else {
c3b6f755 4041 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 4042 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4043 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 4044 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4045 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 4046 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4047 memcpy(mc_desc[0].data, req,
d44f9b63 4048 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4049 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 4050 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4051 retval = le16_to_cpu(mc_desc[0].retval);
4052
4053 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4054 resp_code,
4055 HCLGE_MAC_VLAN_ADD);
4056 }
4057
4058 if (ret) {
4059 dev_err(&hdev->pdev->dev,
4060 "add mac addr failed for cmd_send, ret =%d.\n",
4061 ret);
4062 return ret;
4063 }
4064
4065 return cfg_status;
4066}
4067
4068static int hclge_add_uc_addr(struct hnae3_handle *handle,
4069 const unsigned char *addr)
4070{
4071 struct hclge_vport *vport = hclge_get_vport(handle);
4072
4073 return hclge_add_uc_addr_common(vport, addr);
4074}
4075
4076int hclge_add_uc_addr_common(struct hclge_vport *vport,
4077 const unsigned char *addr)
4078{
4079 struct hclge_dev *hdev = vport->back;
d44f9b63 4080 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 4081 enum hclge_cmd_status status;
a90bb9a5 4082 u16 egress_port = 0;
46a3df9f
S		 4083
4084 /* mac addr check */
4085 if (is_zero_ether_addr(addr) ||
4086 is_broadcast_ether_addr(addr) ||
4087 is_multicast_ether_addr(addr)) {
4088 dev_err(&hdev->pdev->dev,
4089 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4090 addr,
4091 is_zero_ether_addr(addr),
4092 is_broadcast_ether_addr(addr),
4093 is_multicast_ether_addr(addr));
4094 return -EINVAL;
4095 }
4096
4097 memset(&req, 0, sizeof(req));
4098 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4099 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4100 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4101 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
a90bb9a5
YL		 4102
4103 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4104 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4105 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
46a3df9f 4106 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5 4107 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
46a3df9f 4108 HCLGE_MAC_EPORT_PFID_S, 0);
a90bb9a5
YL		 4109
4110 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4111
4112 hclge_prepare_mac_addr(&req, addr);
4113
4114 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
4115
4116 return status;
4117}
4118
4119static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4120 const unsigned char *addr)
4121{
4122 struct hclge_vport *vport = hclge_get_vport(handle);
4123
4124 return hclge_rm_uc_addr_common(vport, addr);
4125}
4126
4127int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4128 const unsigned char *addr)
4129{
4130 struct hclge_dev *hdev = vport->back;
d44f9b63 4131 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4132 enum hclge_cmd_status status;
4133
4134 /* mac addr check */
4135 if (is_zero_ether_addr(addr) ||
4136 is_broadcast_ether_addr(addr) ||
4137 is_multicast_ether_addr(addr)) {
4138 dev_dbg(&hdev->pdev->dev,
4139 "Remove mac err! invalid mac:%pM.\n",
4140 addr);
4141 return -EINVAL;
4142 }
4143
4144 memset(&req, 0, sizeof(req));
4145 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4146 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4147 hclge_prepare_mac_addr(&req, addr);
4148 status = hclge_remove_mac_vlan_tbl(vport, &req);
4149
4150 return status;
4151}
4152
4153static int hclge_add_mc_addr(struct hnae3_handle *handle,
4154 const unsigned char *addr)
4155{
4156 struct hclge_vport *vport = hclge_get_vport(handle);
4157
4158 return hclge_add_mc_addr_common(vport, addr);
4159}
4160
4161int hclge_add_mc_addr_common(struct hclge_vport *vport,
4162 const unsigned char *addr)
4163{
4164 struct hclge_dev *hdev = vport->back;
d44f9b63 4165 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4166 struct hclge_desc desc[3];
4167 u16 tbl_idx;
4168 int status;
4169
4170 /* mac addr check */
4171 if (!is_multicast_ether_addr(addr)) {
4172 dev_err(&hdev->pdev->dev,
4173 "Add mc mac err! invalid mac:%pM.\n",
4174 addr);
4175 return -EINVAL;
4176 }
4177 memset(&req, 0, sizeof(req));
4178 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4179 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4180 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4181 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4182 hclge_prepare_mac_addr(&req, addr);
4183 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4184 if (!status) {
4185 /* This mac addr exist, update VFID for it */
4186 hclge_update_desc_vfid(desc, vport->vport_id, false);
4187 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4188 } else {
4189 /* This mac addr do not exist, add new entry for it */
4190 memset(desc[0].data, 0, sizeof(desc[0].data));
4191 memset(desc[1].data, 0, sizeof(desc[0].data));
4192 memset(desc[2].data, 0, sizeof(desc[0].data));
4193 hclge_update_desc_vfid(desc, vport->vport_id, false);
4194 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4195 }
4196
4197 /* Set MTA table for this MAC address */
4198 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4199 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4200
4201 return status;
4202}
4203
4204static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4205 const unsigned char *addr)
4206{
4207 struct hclge_vport *vport = hclge_get_vport(handle);
4208
4209 return hclge_rm_mc_addr_common(vport, addr);
4210}
4211
4212int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4213 const unsigned char *addr)
4214{
4215 struct hclge_dev *hdev = vport->back;
d44f9b63 4216 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4217 enum hclge_cmd_status status;
4218 struct hclge_desc desc[3];
4219 u16 tbl_idx;
4220
4221 /* mac addr check */
4222 if (!is_multicast_ether_addr(addr)) {
4223 dev_dbg(&hdev->pdev->dev,
4224 "Remove mc mac err! invalid mac:%pM.\n",
4225 addr);
4226 return -EINVAL;
4227 }
4228
4229 memset(&req, 0, sizeof(req));
4230 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4231 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4232 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4233 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4234 hclge_prepare_mac_addr(&req, addr);
4235 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4236 if (!status) {
4237 /* This mac addr exist, remove this handle's VFID for it */
4238 hclge_update_desc_vfid(desc, vport->vport_id, true);
4239
4240 if (hclge_is_all_function_id_zero(desc))
4241 /* All the vfid is zero, so need to delete this entry */
4242 status = hclge_remove_mac_vlan_tbl(vport, &req);
4243 else
4244 /* Not all the vfid is zero, update the vfid */
4245 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4246
4247 } else {
4248 /* This mac addr do not exist, can't delete it */
4249 dev_err(&hdev->pdev->dev,
d7629e74 4250 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 4251 status);
4252 return -EIO;
4253 }
4254
4255 /* Set MTB table for this MAC address */
4256 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4257 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4258
4259 return status;
4260}
4261
635bfb58
FL		 4262static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4263 u16 cmdq_resp, u8 resp_code)
4264{
4265#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4266#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4267#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4268#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4269
4270 int return_status;
4271
4272 if (cmdq_resp) {
4273 dev_err(&hdev->pdev->dev,
4274 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4275 cmdq_resp);
4276 return -EIO;
4277 }
4278
4279 switch (resp_code) {
4280 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4281 case HCLGE_ETHERTYPE_ALREADY_ADD:
4282 return_status = 0;
4283 break;
4284 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4285 dev_err(&hdev->pdev->dev,
4286 "add mac ethertype failed for manager table overflow.\n");
4287 return_status = -EIO;
4288 break;
4289 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4290 dev_err(&hdev->pdev->dev,
4291 "add mac ethertype failed for key conflict.\n");
4292 return_status = -EIO;
4293 break;
4294 default:
4295 dev_err(&hdev->pdev->dev,
4296 "add mac ethertype failed for undefined, code=%d.\n",
4297 resp_code);
4298 return_status = -EIO;
4299 }
4300
4301 return return_status;
4302}
4303
4304static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4305 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4306{
4307 struct hclge_desc desc;
4308 u8 resp_code;
4309 u16 retval;
4310 int ret;
4311
4312 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4313 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4314
4315 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4316 if (ret) {
4317 dev_err(&hdev->pdev->dev,
4318 "add mac ethertype failed for cmd_send, ret =%d.\n",
4319 ret);
4320 return ret;
4321 }
4322
4323 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4324 retval = le16_to_cpu(desc.retval);
4325
4326 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4327}
4328
4329static int init_mgr_tbl(struct hclge_dev *hdev)
4330{
4331 int ret;
4332 int i;
4333
4334 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4335 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4336 if (ret) {
4337 dev_err(&hdev->pdev->dev,
4338 "add mac ethertype failed, ret =%d.\n",
4339 ret);
4340 return ret;
4341 }
4342 }
4343
4344 return 0;
4345}
4346
46a3df9f
S		 4347static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4348{
4349 struct hclge_vport *vport = hclge_get_vport(handle);
4350 struct hclge_dev *hdev = vport->back;
4351
4352 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4353}
4354
4355static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4356{
4357 const unsigned char *new_addr = (const unsigned char *)p;
4358 struct hclge_vport *vport = hclge_get_vport(handle);
4359 struct hclge_dev *hdev = vport->back;
20a5c4c0 4360 int ret;
46a3df9f
S		 4361
4362 /* mac addr check */
4363 if (is_zero_ether_addr(new_addr) ||
4364 is_broadcast_ether_addr(new_addr) ||
4365 is_multicast_ether_addr(new_addr)) {
4366 dev_err(&hdev->pdev->dev,
4367 "Change uc mac err! invalid mac:%p.\n",
4368 new_addr);
4369 return -EINVAL;
4370 }
4371
20a5c4c0
FL		 4372 ret = hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4373 if (ret)
4374 dev_warn(&hdev->pdev->dev,
4375 "remove old uc mac address fail, ret =%d.\n",
4376 ret);
46a3df9f 4377
20a5c4c0
FL		 4378 ret = hclge_add_uc_addr(handle, new_addr);
4379 if (ret) {
4380 dev_err(&hdev->pdev->dev,
4381 "add uc mac address fail, ret =%d.\n",
4382 ret);
4383
4384 ret = hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr);
4385 if (ret) {
4386 dev_err(&hdev->pdev->dev,
4387 "restore uc mac address fail, ret =%d.\n",
4388 ret);
4389 }
4390
4391 return -EIO;
46a3df9f
S		 4392 }
4393
20a5c4c0
FL		 4394 ret = hclge_mac_pause_addr_cfg(hdev, new_addr);
4395 if (ret) {
4396 dev_err(&hdev->pdev->dev,
4397 "configure mac pause address fail, ret =%d.\n",
4398 ret);
4399 return -EIO;
4400 }
4401
4402 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4403
4404 return 0;
46a3df9f
S		 4405}
4406
4407static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4408 bool filter_en)
4409{
d44f9b63 4410 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4411 struct hclge_desc desc;
4412 int ret;
4413
4414 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4415
d44f9b63 4416 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4417 req->vlan_type = vlan_type;
4418 req->vlan_fe = filter_en;
4419
4420 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4421 if (ret) {
4422 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4423 ret);
4424 return ret;
4425 }
4426
4427 return 0;
4428}
4429
d818396d
JS		 4430#define HCLGE_FILTER_TYPE_VF 0
4431#define HCLGE_FILTER_TYPE_PORT 1
4432
4433static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4434{
4435 struct hclge_vport *vport = hclge_get_vport(handle);
4436 struct hclge_dev *hdev = vport->back;
4437
4438 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4439}
4440
46a3df9f
S		 4441int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4442 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4443{
4444#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4445 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4446 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4447 struct hclge_desc desc[2];
4448 u8 vf_byte_val;
4449 u8 vf_byte_off;
4450 int ret;
4451
4452 hclge_cmd_setup_basic_desc(&desc[0],
4453 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4454 hclge_cmd_setup_basic_desc(&desc[1],
4455 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4456
4457 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4458
4459 vf_byte_off = vfid / 8;
4460 vf_byte_val = 1 << (vfid % 8);
4461
d44f9b63
YL		 4462 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4463 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4464
a90bb9a5 4465 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4466 req0->vlan_cfg = is_kill;
4467
4468 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4469 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4470 else
4471 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4472
4473 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4474 if (ret) {
4475 dev_err(&hdev->pdev->dev,
4476 "Send vf vlan command fail, ret =%d.\n",
4477 ret);
4478 return ret;
4479 }
4480
4481 if (!is_kill) {
4482 if (!req0->resp_code || req0->resp_code == 1)
4483 return 0;
4484
4485 dev_err(&hdev->pdev->dev,
4486 "Add vf vlan filter fail, ret =%d.\n",
4487 req0->resp_code);
4488 } else {
4489 if (!req0->resp_code)
4490 return 0;
4491
4492 dev_err(&hdev->pdev->dev,
4493 "Kill vf vlan filter fail, ret =%d.\n",
4494 req0->resp_code);
4495 }
4496
4497 return -EIO;
4498}
4499
4500static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4501 __be16 proto, u16 vlan_id,
4502 bool is_kill)
4503{
4504 struct hclge_vport *vport = hclge_get_vport(handle);
4505 struct hclge_dev *hdev = vport->back;
d44f9b63 4506 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4507 struct hclge_desc desc;
4508 u8 vlan_offset_byte_val;
4509 u8 vlan_offset_byte;
4510 u8 vlan_offset_160;
4511 int ret;
4512
4513 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4514
4515 vlan_offset_160 = vlan_id / 160;
4516 vlan_offset_byte = (vlan_id % 160) / 8;
4517 vlan_offset_byte_val = 1 << (vlan_id % 8);
4518
d44f9b63 4519 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4520 req->vlan_offset = vlan_offset_160;
4521 req->vlan_cfg = is_kill;
4522 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4523
4524 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4525 if (ret) {
4526 dev_err(&hdev->pdev->dev,
4527 "port vlan command, send fail, ret =%d.\n",
4528 ret);
4529 return ret;
4530 }
4531
4532 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4533 if (ret) {
4534 dev_err(&hdev->pdev->dev,
4535 "Set pf vlan filter config fail, ret =%d.\n",
4536 ret);
4537 return -EIO;
4538 }
4539
4540 return 0;
4541}
4542
4543static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4544 u16 vlan, u8 qos, __be16 proto)
4545{
4546 struct hclge_vport *vport = hclge_get_vport(handle);
4547 struct hclge_dev *hdev = vport->back;
4548
4549 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4550 return -EINVAL;
4551 if (proto != htons(ETH_P_8021Q))
4552 return -EPROTONOSUPPORT;
4553
4554 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4555}
4556
e62f2a6b
PL		 4557static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4558{
4559 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4560 struct hclge_vport_vtag_tx_cfg_cmd *req;
4561 struct hclge_dev *hdev = vport->back;
4562 struct hclge_desc desc;
4563 int status;
4564
4565 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4566
4567 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4568 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4569 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4570 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B,
4571 vcfg->accept_tag ? 1 : 0);
4572 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B,
4573 vcfg->accept_untag ? 1 : 0);
4574 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4575 vcfg->insert_tag1_en ? 1 : 0);
4576 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4577 vcfg->insert_tag2_en ? 1 : 0);
4578 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4579
4580 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4581 req->vf_bitmap[req->vf_offset] =
4582 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4583
4584 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4585 if (status)
4586 dev_err(&hdev->pdev->dev,
4587 "Send port txvlan cfg command fail, ret =%d\n",
4588 status);
4589
4590 return status;
4591}
4592
4593static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4594{
4595 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4596 struct hclge_vport_vtag_rx_cfg_cmd *req;
4597 struct hclge_dev *hdev = vport->back;
4598 struct hclge_desc desc;
4599 int status;
4600
4601 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4602
4603 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4604 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4605 vcfg->strip_tag1_en ? 1 : 0);
4606 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4607 vcfg->strip_tag2_en ? 1 : 0);
4608 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4609 vcfg->vlan1_vlan_prionly ? 1 : 0);
4610 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4611 vcfg->vlan2_vlan_prionly ? 1 : 0);
4612
4613 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4614 req->vf_bitmap[req->vf_offset] =
4615 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4616
4617 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4618 if (status)
4619 dev_err(&hdev->pdev->dev,
4620 "Send port rxvlan cfg command fail, ret =%d\n",
4621 status);
4622
4623 return status;
4624}
4625
4626static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4627{
4628 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4629 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4630 struct hclge_desc desc;
4631 int status;
4632
4633 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4634 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4635 rx_req->ot_fst_vlan_type =
4636 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4637 rx_req->ot_sec_vlan_type =
4638 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4639 rx_req->in_fst_vlan_type =
4640 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4641 rx_req->in_sec_vlan_type =
4642 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4643
4644 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4645 if (status) {
4646 dev_err(&hdev->pdev->dev,
4647 "Send rxvlan protocol type command fail, ret =%d\n",
4648 status);
4649 return status;
4650 }
4651
4652 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4653
4654 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4655 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4656 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4657
4658 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4659 if (status)
4660 dev_err(&hdev->pdev->dev,
4661 "Send txvlan protocol type command fail, ret =%d\n",
4662 status);
4663
4664 return status;
4665}
4666
46a3df9f
S		 4667static int hclge_init_vlan_config(struct hclge_dev *hdev)
4668{
e62f2a6b
PL		 4669#define HCLGE_DEF_VLAN_TYPE 0x8100
4670
5e43aef8 4671 struct hnae3_handle *handle;
e62f2a6b 4672 struct hclge_vport *vport;
46a3df9f 4673 int ret;
e62f2a6b
PL		 4674 int i;
4675
4676 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4677 if (ret)
4678 return ret;
46a3df9f 4679
e62f2a6b 4680 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4681 if (ret)
4682 return ret;
4683
e62f2a6b
PL		 4684 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4685 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4686 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4687 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4688 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4689 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4690
4691 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4692 if (ret)
4693 return ret;
46a3df9f 4694
e62f2a6b
PL		 4695 for (i = 0; i < hdev->num_alloc_vport; i++) {
4696 vport = &hdev->vport[i];
4697 vport->txvlan_cfg.accept_tag = true;
4698 vport->txvlan_cfg.accept_untag = true;
4699 vport->txvlan_cfg.insert_tag1_en = false;
4700 vport->txvlan_cfg.insert_tag2_en = false;
4701 vport->txvlan_cfg.default_tag1 = 0;
4702 vport->txvlan_cfg.default_tag2 = 0;
4703
4704 ret = hclge_set_vlan_tx_offload_cfg(vport);
4705 if (ret)
4706 return ret;
4707
4708 vport->rxvlan_cfg.strip_tag1_en = false;
4709 vport->rxvlan_cfg.strip_tag2_en = true;
4710 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4711 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4712
4713 ret = hclge_set_vlan_rx_offload_cfg(vport);
4714 if (ret)
4715 return ret;
4716 }
4717
5e43aef8
L		 4718 handle = &hdev->vport[0].nic;
4719 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4720}
4721
5f9a7732
PL		 4722static int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4723{
4724 struct hclge_vport *vport = hclge_get_vport(handle);
4725
4726 vport->rxvlan_cfg.strip_tag1_en = false;
4727 vport->rxvlan_cfg.strip_tag2_en = enable;
4728 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4729 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4730
4731 return hclge_set_vlan_rx_offload_cfg(vport);
4732}
4733
46a3df9f
S		 4734static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4735{
4736 struct hclge_vport *vport = hclge_get_vport(handle);
d44f9b63 4737 struct hclge_config_max_frm_size_cmd *req;
46a3df9f
S		 4738 struct hclge_dev *hdev = vport->back;
4739 struct hclge_desc desc;
7393ed39 4740 int max_frm_size;
46a3df9f
S		 4741 int ret;
4742
7393ed39
FL		 4743 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4744
4745 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4746 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 4747 return -EINVAL;
4748
7393ed39
FL		 4749 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
4750
46a3df9f
S		 4751 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4752
d44f9b63 4753 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
7393ed39 4754 req->max_frm_size = cpu_to_le16(max_frm_size);
46a3df9f
S		 4755
4756 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4757 if (ret) {
4758 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4759 return ret;
4760 }
4761
7393ed39
FL		 4762 hdev->mps = max_frm_size;
4763
46a3df9f
S		 4764 return 0;
4765}
4766
4767static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4768 bool enable)
4769{
d44f9b63 4770 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4771 struct hclge_desc desc;
4772 int ret;
4773
4774 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4775
d44f9b63 4776 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4777 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4778 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4779
4780 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4781 if (ret) {
4782 dev_err(&hdev->pdev->dev,
4783 "Send tqp reset cmd error, status =%d\n", ret);
4784 return ret;
4785 }
4786
4787 return 0;
4788}
4789
4790static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4791{
d44f9b63 4792 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4793 struct hclge_desc desc;
4794 int ret;
4795
4796 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4797
d44f9b63 4798 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4799 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4800
4801 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4802 if (ret) {
4803 dev_err(&hdev->pdev->dev,
4804 "Get reset status error, status =%d\n", ret);
4805 return ret;
4806 }
4807
4808 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4809}
4810
63d7e66f 4811void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 4812{
4813 struct hclge_vport *vport = hclge_get_vport(handle);
4814 struct hclge_dev *hdev = vport->back;
4815 int reset_try_times = 0;
4816 int reset_status;
4817 int ret;
4818
4819 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4820 if (ret) {
4821 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4822 return;
4823 }
4824
4825 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4826 if (ret) {
4827 dev_warn(&hdev->pdev->dev,
4828 "Send reset tqp cmd fail, ret = %d\n", ret);
4829 return;
4830 }
4831
4832 reset_try_times = 0;
4833 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4834 /* Wait for tqp hw reset */
4835 msleep(20);
4836 reset_status = hclge_get_reset_status(hdev, queue_id);
4837 if (reset_status)
4838 break;
4839 }
4840
4841 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4842 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4843 return;
4844 }
4845
4846 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4847 if (ret) {
4848 dev_warn(&hdev->pdev->dev,
4849 "Deassert the soft reset fail, ret = %d\n", ret);
4850 return;
4851 }
4852}
4853
4854static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4855{
4856 struct hclge_vport *vport = hclge_get_vport(handle);
4857 struct hclge_dev *hdev = vport->back;
4858
4859 return hdev->fw_version;
4860}
4861
a2cfbadb
PL		 4862static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
4863 u32 *flowctrl_adv)
4864{
4865 struct hclge_vport *vport = hclge_get_vport(handle);
4866 struct hclge_dev *hdev = vport->back;
4867 struct phy_device *phydev = hdev->hw.mac.phydev;
4868
4869 if (!phydev)
4870 return;
4871
4872 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
4873 (phydev->advertising & ADVERTISED_Asym_Pause);
4874}
4875
09ea401e
PL		 4876static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4877{
4878 struct phy_device *phydev = hdev->hw.mac.phydev;
4879
4880 if (!phydev)
4881 return;
4882
4883 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
4884
4885 if (rx_en)
4886 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
4887
4888 if (tx_en)
4889 phydev->advertising ^= ADVERTISED_Asym_Pause;
4890}
4891
4892static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4893{
09ea401e
PL		 4894 int ret;
4895
4896 if (rx_en && tx_en)
7a28a82a 4897 hdev->fc_mode_last_time = HCLGE_FC_FULL;
09ea401e 4898 else if (rx_en && !tx_en)
7a28a82a 4899 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
09ea401e 4900 else if (!rx_en && tx_en)
7a28a82a 4901 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
09ea401e 4902 else
7a28a82a 4903 hdev->fc_mode_last_time = HCLGE_FC_NONE;
09ea401e 4904
7a28a82a 4905 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
09ea401e 4906 return 0;
09ea401e
PL		 4907
4908 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
4909 if (ret) {
4910 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
4911 ret);
4912 return ret;
4913 }
4914
7a28a82a 4915 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
09ea401e
PL		 4916
4917 return 0;
4918}
4919
6282f2ea
PL		 4920int hclge_cfg_flowctrl(struct hclge_dev *hdev)
4921{
4922 struct phy_device *phydev = hdev->hw.mac.phydev;
4923 u16 remote_advertising = 0;
4924 u16 local_advertising = 0;
4925 u32 rx_pause, tx_pause;
4926 u8 flowctl;
4927
4928 if (!phydev->link || !phydev->autoneg)
4929 return 0;
4930
4931 if (phydev->advertising & ADVERTISED_Pause)
4932 local_advertising = ADVERTISE_PAUSE_CAP;
4933
4934 if (phydev->advertising & ADVERTISED_Asym_Pause)
4935 local_advertising |= ADVERTISE_PAUSE_ASYM;
4936
4937 if (phydev->pause)
4938 remote_advertising = LPA_PAUSE_CAP;
4939
4940 if (phydev->asym_pause)
4941 remote_advertising |= LPA_PAUSE_ASYM;
4942
4943 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
4944 remote_advertising);
4945 tx_pause = flowctl & FLOW_CTRL_TX;
4946 rx_pause = flowctl & FLOW_CTRL_RX;
4947
4948 if (phydev->duplex == HCLGE_MAC_HALF) {
4949 tx_pause = 0;
4950 rx_pause = 0;
4951 }
4952
4953 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
4954}
4955
46a3df9f
S		 4956static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4957 u32 *rx_en, u32 *tx_en)
4958{
4959 struct hclge_vport *vport = hclge_get_vport(handle);
4960 struct hclge_dev *hdev = vport->back;
4961
4962 *auto_neg = hclge_get_autoneg(handle);
4963
4964 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4965 *rx_en = 0;
4966 *tx_en = 0;
4967 return;
4968 }
4969
4970 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4971 *rx_en = 1;
4972 *tx_en = 0;
4973 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4974 *tx_en = 1;
4975 *rx_en = 0;
4976 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4977 *rx_en = 1;
4978 *tx_en = 1;
4979 } else {
4980 *rx_en = 0;
4981 *tx_en = 0;
4982 }
4983}
4984
09ea401e
PL		 4985static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
4986 u32 rx_en, u32 tx_en)
4987{
4988 struct hclge_vport *vport = hclge_get_vport(handle);
4989 struct hclge_dev *hdev = vport->back;
4990 struct phy_device *phydev = hdev->hw.mac.phydev;
4991 u32 fc_autoneg;
4992
4993 /* Only support flow control negotiation for netdev with
4994 * phy attached for now.
4995 */
4996 if (!phydev)
4997 return -EOPNOTSUPP;
4998
4999 fc_autoneg = hclge_get_autoneg(handle);
5000 if (auto_neg != fc_autoneg) {
5001 dev_info(&hdev->pdev->dev,
5002 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5003 return -EOPNOTSUPP;
5004 }
5005
5006 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5007 dev_info(&hdev->pdev->dev,
5008 "Priority flow control enabled. Cannot set link flow control.\n");
5009 return -EOPNOTSUPP;
5010 }
5011
5012 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5013
5014 if (!fc_autoneg)
5015 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5016
5017 return phy_start_aneg(phydev);
5018}
5019
46a3df9f
S		 5020static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5021 u8 *auto_neg, u32 *speed, u8 *duplex)
5022{
5023 struct hclge_vport *vport = hclge_get_vport(handle);
5024 struct hclge_dev *hdev = vport->back;
5025
5026 if (speed)
5027 *speed = hdev->hw.mac.speed;
5028 if (duplex)
5029 *duplex = hdev->hw.mac.duplex;
5030 if (auto_neg)
5031 *auto_neg = hdev->hw.mac.autoneg;
5032}
5033
5034static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5035{
5036 struct hclge_vport *vport = hclge_get_vport(handle);
5037 struct hclge_dev *hdev = vport->back;
5038
5039 if (media_type)
5040 *media_type = hdev->hw.mac.media_type;
5041}
5042
5043static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5044 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5045{
5046 struct hclge_vport *vport = hclge_get_vport(handle);
5047 struct hclge_dev *hdev = vport->back;
5048 struct phy_device *phydev = hdev->hw.mac.phydev;
5049 int mdix_ctrl, mdix, retval, is_resolved;
5050
5051 if (!phydev) {
5052 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5053 *tp_mdix = ETH_TP_MDI_INVALID;
5054 return;
5055 }
5056
5057 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5058
5059 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
5060 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5061 HCLGE_PHY_MDIX_CTRL_S);
5062
5063 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
5064 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5065 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
5066
5067 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5068
5069 switch (mdix_ctrl) {
5070 case 0x0:
5071 *tp_mdix_ctrl = ETH_TP_MDI;
5072 break;
5073 case 0x1:
5074 *tp_mdix_ctrl = ETH_TP_MDI_X;
5075 break;
5076 case 0x3:
5077 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5078 break;
5079 default:
5080 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5081 break;
5082 }
5083
5084 if (!is_resolved)
5085 *tp_mdix = ETH_TP_MDI_INVALID;
5086 else if (mdix)
5087 *tp_mdix = ETH_TP_MDI_X;
5088 else
5089 *tp_mdix = ETH_TP_MDI;
5090}
5091
5092static int hclge_init_client_instance(struct hnae3_client *client,
5093 struct hnae3_ae_dev *ae_dev)
5094{
5095 struct hclge_dev *hdev = ae_dev->priv;
5096 struct hclge_vport *vport;
5097 int i, ret;
5098
5099 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5100 vport = &hdev->vport[i];
5101
5102 switch (client->type) {
5103 case HNAE3_CLIENT_KNIC:
5104
5105 hdev->nic_client = client;
5106 vport->nic.client = client;
5107 ret = client->ops->init_instance(&vport->nic);
5108 if (ret)
5109 goto err;
5110
5111 if (hdev->roce_client &&
e92a0843 5112 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5113 struct hnae3_client *rc = hdev->roce_client;
5114
5115 ret = hclge_init_roce_base_info(vport);
5116 if (ret)
5117 goto err;
5118
5119 ret = rc->ops->init_instance(&vport->roce);
5120 if (ret)
5121 goto err;
5122 }
5123
5124 break;
5125 case HNAE3_CLIENT_UNIC:
5126 hdev->nic_client = client;
5127 vport->nic.client = client;
5128
5129 ret = client->ops->init_instance(&vport->nic);
5130 if (ret)
5131 goto err;
5132
5133 break;
5134 case HNAE3_CLIENT_ROCE:
e92a0843 5135 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5136 hdev->roce_client = client;
5137 vport->roce.client = client;
5138 }
5139
3a46f34d 5140 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5141 ret = hclge_init_roce_base_info(vport);
5142 if (ret)
5143 goto err;
5144
5145 ret = client->ops->init_instance(&vport->roce);
5146 if (ret)
5147 goto err;
5148 }
5149 }
5150 }
5151
5152 return 0;
5153err:
5154 return ret;
5155}
5156
5157static void hclge_uninit_client_instance(struct hnae3_client *client,
5158 struct hnae3_ae_dev *ae_dev)
5159{
5160 struct hclge_dev *hdev = ae_dev->priv;
5161 struct hclge_vport *vport;
5162 int i;
5163
5164 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5165 vport = &hdev->vport[i];
a17dcf3f 5166 if (hdev->roce_client) {
46a3df9f
S		 5167 hdev->roce_client->ops->uninit_instance(&vport->roce,
5168 0);
a17dcf3f
L		 5169 hdev->roce_client = NULL;
5170 vport->roce.client = NULL;
5171 }
46a3df9f
S		 5172 if (client->type == HNAE3_CLIENT_ROCE)
5173 return;
a17dcf3f 5174 if (client->ops->uninit_instance) {
46a3df9f 5175 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5176 hdev->nic_client = NULL;
5177 vport->nic.client = NULL;
5178 }
46a3df9f
S		 5179 }
5180}
5181
5182static int hclge_pci_init(struct hclge_dev *hdev)
5183{
5184 struct pci_dev *pdev = hdev->pdev;
5185 struct hclge_hw *hw;
5186 int ret;
5187
5188 ret = pci_enable_device(pdev);
5189 if (ret) {
5190 dev_err(&pdev->dev, "failed to enable PCI device\n");
5191 goto err_no_drvdata;
5192 }
5193
5194 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5195 if (ret) {
5196 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5197 if (ret) {
5198 dev_err(&pdev->dev,
5199 "can't set consistent PCI DMA");
5200 goto err_disable_device;
5201 }
5202 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5203 }
5204
5205 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5206 if (ret) {
5207 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5208 goto err_disable_device;
5209 }
5210
5211 pci_set_master(pdev);
5212 hw = &hdev->hw;
5213 hw->back = hdev;
5214 hw->io_base = pcim_iomap(pdev, 2, 0);
5215 if (!hw->io_base) {
5216 dev_err(&pdev->dev, "Can't map configuration register space\n");
5217 ret = -ENOMEM;
5218 goto err_clr_master;
5219 }
5220
709eb41a
L		 5221 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5222
46a3df9f
S		 5223 return 0;
5224err_clr_master:
5225 pci_clear_master(pdev);
5226 pci_release_regions(pdev);
5227err_disable_device:
5228 pci_disable_device(pdev);
5229err_no_drvdata:
5230 pci_set_drvdata(pdev, NULL);
5231
5232 return ret;
5233}
5234
5235static void hclge_pci_uninit(struct hclge_dev *hdev)
5236{
5237 struct pci_dev *pdev = hdev->pdev;
5238
887c3820 5239 pci_free_irq_vectors(pdev);
46a3df9f
S		 5240 pci_clear_master(pdev);
5241 pci_release_mem_regions(pdev);
5242 pci_disable_device(pdev);
5243}
5244
5245static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5246{
5247 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5248 struct hclge_dev *hdev;
5249 int ret;
5250
5251 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5252 if (!hdev) {
5253 ret = -ENOMEM;
5254 goto err_hclge_dev;
5255 }
5256
46a3df9f
S		 5257 hdev->pdev = pdev;
5258 hdev->ae_dev = ae_dev;
4ed340ab 5259 hdev->reset_type = HNAE3_NONE_RESET;
ed4a1bb8 5260 hdev->reset_request = 0;
202f2014 5261 hdev->reset_pending = 0;
46a3df9f
S		 5262 ae_dev->priv = hdev;
5263
46a3df9f
S		 5264 ret = hclge_pci_init(hdev);
5265 if (ret) {
5266 dev_err(&pdev->dev, "PCI init failed\n");
5267 goto err_pci_init;
5268 }
5269
3efb960f
L		 5270 /* Firmware command queue initialize */
5271 ret = hclge_cmd_queue_init(hdev);
5272 if (ret) {
5273 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5274 return ret;
5275 }
5276
5277 /* Firmware command initialize */
46a3df9f
S		 5278 ret = hclge_cmd_init(hdev);
5279 if (ret)
5280 goto err_cmd_init;
5281
5282 ret = hclge_get_cap(hdev);
5283 if (ret) {
e00e2197
CIK		 5284 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5285 ret);
46a3df9f
S		 5286 return ret;
5287 }
5288
5289 ret = hclge_configure(hdev);
5290 if (ret) {
5291 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5292 return ret;
5293 }
5294
887c3820 5295 ret = hclge_init_msi(hdev);
46a3df9f 5296 if (ret) {
887c3820 5297 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
46a3df9f
S		 5298 return ret;
5299 }
5300
466b0c00
L		 5301 ret = hclge_misc_irq_init(hdev);
5302 if (ret) {
5303 dev_err(&pdev->dev,
5304 "Misc IRQ(vector0) init error, ret = %d.\n",
5305 ret);
5306 return ret;
5307 }
5308
46a3df9f
S		 5309 ret = hclge_alloc_tqps(hdev);
5310 if (ret) {
5311 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5312 return ret;
5313 }
5314
5315 ret = hclge_alloc_vport(hdev);
5316 if (ret) {
5317 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5318 return ret;
5319 }
5320
7df7dad6
L		 5321 ret = hclge_map_tqp(hdev);
5322 if (ret) {
5323 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5324 return ret;
5325 }
5326
cf9cca2d 5327 ret = hclge_mac_mdio_config(hdev);
5328 if (ret) {
5329 dev_warn(&hdev->pdev->dev,
5330 "mdio config fail ret=%d\n", ret);
5331 return ret;
5332 }
5333
46a3df9f
S		 5334 ret = hclge_mac_init(hdev);
5335 if (ret) {
5336 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5337 return ret;
5338 }
5339 ret = hclge_buffer_alloc(hdev);
5340 if (ret) {
5341 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5342 return ret;
5343 }
5344
5345 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5346 if (ret) {
5347 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5348 return ret;
5349 }
5350
46a3df9f
S		 5351 ret = hclge_init_vlan_config(hdev);
5352 if (ret) {
5353 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5354 return ret;
5355 }
5356
5357 ret = hclge_tm_schd_init(hdev);
5358 if (ret) {
5359 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5360 return ret;
68ece54e
YL		 5361 }
5362
5363 ret = hclge_rss_init_hw(hdev);
5364 if (ret) {
5365 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5366 return ret;
46a3df9f
S		 5367 }
5368
635bfb58
FL		 5369 ret = init_mgr_tbl(hdev);
5370 if (ret) {
5371 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
5372 return ret;
5373 }
5374
cacde272
YL		 5375 hclge_dcb_ops_set(hdev);
5376
d039ef68 5377 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5378 INIT_WORK(&hdev->service_task, hclge_service_task);
ed4a1bb8 5379 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
22fd3468 5380 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5381
466b0c00
L		 5382 /* Enable MISC vector(vector0) */
5383 hclge_enable_vector(&hdev->misc_vector, true);
5384
46a3df9f
S		 5385 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5386 set_bit(HCLGE_STATE_DOWN, &hdev->state);
ed4a1bb8
SM		 5387 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5388 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
22fd3468
SM		 5389 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5390 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
46a3df9f
S		 5391
5392 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5393 return 0;
5394
5395err_cmd_init:
5396 pci_release_regions(pdev);
5397err_pci_init:
5398 pci_set_drvdata(pdev, NULL);
5399err_hclge_dev:
5400 return ret;
5401}
5402
c6dc5213 5403static void hclge_stats_clear(struct hclge_dev *hdev)
5404{
5405 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5406}
5407
4ed340ab
L		 5408static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5409{
5410 struct hclge_dev *hdev = ae_dev->priv;
5411 struct pci_dev *pdev = ae_dev->pdev;
5412 int ret;
5413
5414 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5415
c6dc5213 5416 hclge_stats_clear(hdev);
5417
4ed340ab
L		 5418 ret = hclge_cmd_init(hdev);
5419 if (ret) {
5420 dev_err(&pdev->dev, "Cmd queue init failed\n");
5421 return ret;
5422 }
5423
5424 ret = hclge_get_cap(hdev);
5425 if (ret) {
5426 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5427 ret);
5428 return ret;
5429 }
5430
5431 ret = hclge_configure(hdev);
5432 if (ret) {
5433 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5434 return ret;
5435 }
5436
5437 ret = hclge_map_tqp(hdev);
5438 if (ret) {
5439 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5440 return ret;
5441 }
5442
5443 ret = hclge_mac_init(hdev);
5444 if (ret) {
5445 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5446 return ret;
5447 }
5448
5449 ret = hclge_buffer_alloc(hdev);
5450 if (ret) {
5451 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5452 return ret;
5453 }
5454
5455 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5456 if (ret) {
5457 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5458 return ret;
5459 }
5460
5461 ret = hclge_init_vlan_config(hdev);
5462 if (ret) {
5463 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5464 return ret;
5465 }
5466
5467 ret = hclge_tm_schd_init(hdev);
5468 if (ret) {
5469 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5470 return ret;
5471 }
5472
5473 ret = hclge_rss_init_hw(hdev);
5474 if (ret) {
5475 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5476 return ret;
5477 }
5478
5479 /* Enable MISC vector(vector0) */
5480 hclge_enable_vector(&hdev->misc_vector, true);
5481
5482 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5483 HCLGE_DRIVER_NAME);
5484
5485 return 0;
5486}
5487
46a3df9f
S		 5488static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5489{
5490 struct hclge_dev *hdev = ae_dev->priv;
5491 struct hclge_mac *mac = &hdev->hw.mac;
5492
5493 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5494
2a32ca13
AB		 5495 if (IS_ENABLED(CONFIG_PCI_IOV))
5496 hclge_disable_sriov(hdev);
46a3df9f 5497
d039ef68 5498 if (hdev->service_timer.function)
46a3df9f
S		 5499 del_timer_sync(&hdev->service_timer);
5500 if (hdev->service_task.func)
5501 cancel_work_sync(&hdev->service_task);
ed4a1bb8
SM		 5502 if (hdev->rst_service_task.func)
5503 cancel_work_sync(&hdev->rst_service_task);
22fd3468
SM		 5504 if (hdev->mbx_service_task.func)
5505 cancel_work_sync(&hdev->mbx_service_task);
46a3df9f
S		 5506
5507 if (mac->phydev)
5508 mdiobus_unregister(mac->mdio_bus);
5509
466b0c00
L		 5510 /* Disable MISC vector(vector0) */
5511 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 5512 hclge_destroy_cmd_queue(&hdev->hw);
202f2014 5513 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5514 hclge_pci_uninit(hdev);
5515 ae_dev->priv = NULL;
5516}
5517
4f645a90
PL		 5518static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5519{
5520 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5521 struct hclge_vport *vport = hclge_get_vport(handle);
5522 struct hclge_dev *hdev = vport->back;
5523
5524 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5525}
5526
5527static void hclge_get_channels(struct hnae3_handle *handle,
5528 struct ethtool_channels *ch)
5529{
5530 struct hclge_vport *vport = hclge_get_vport(handle);
5531
5532 ch->max_combined = hclge_get_max_channels(handle);
5533 ch->other_count = 1;
5534 ch->max_other = 1;
5535 ch->combined_count = vport->alloc_tqps;
5536}
5537
f1f779ce
PL		 5538static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5539 u16 *free_tqps, u16 *max_rss_size)
5540{
5541 struct hclge_vport *vport = hclge_get_vport(handle);
5542 struct hclge_dev *hdev = vport->back;
5543 u16 temp_tqps = 0;
5544 int i;
5545
5546 for (i = 0; i < hdev->num_tqps; i++) {
5547 if (!hdev->htqp[i].alloced)
5548 temp_tqps++;
5549 }
5550 *free_tqps = temp_tqps;
5551 *max_rss_size = hdev->rss_size_max;
5552}
5553
5554static void hclge_release_tqp(struct hclge_vport *vport)
5555{
5556 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5557 struct hclge_dev *hdev = vport->back;
5558 int i;
5559
5560 for (i = 0; i < kinfo->num_tqps; i++) {
5561 struct hclge_tqp *tqp =
5562 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5563
5564 tqp->q.handle = NULL;
5565 tqp->q.tqp_index = 0;
5566 tqp->alloced = false;
5567 }
5568
5569 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5570 kinfo->tqp = NULL;
5571}
5572
5573static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5574{
5575 struct hclge_vport *vport = hclge_get_vport(handle);
5576 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5577 struct hclge_dev *hdev = vport->back;
5578 int cur_rss_size = kinfo->rss_size;
5579 int cur_tqps = kinfo->num_tqps;
5580 u16 tc_offset[HCLGE_MAX_TC_NUM];
5581 u16 tc_valid[HCLGE_MAX_TC_NUM];
5582 u16 tc_size[HCLGE_MAX_TC_NUM];
5583 u16 roundup_size;
5584 u32 *rss_indir;
5585 int ret, i;
5586
5587 hclge_release_tqp(vport);
5588
5589 ret = hclge_knic_setup(vport, new_tqps_num);
5590 if (ret) {
5591 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5592 return ret;
5593 }
5594
5595 ret = hclge_map_tqp_to_vport(hdev, vport);
5596 if (ret) {
5597 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5598 return ret;
5599 }
5600
5601 ret = hclge_tm_schd_init(hdev);
5602 if (ret) {
5603 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5604 return ret;
5605 }
5606
5607 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5608 roundup_size = ilog2(roundup_size);
5609 /* Set the RSS TC mode according to the new RSS size */
5610 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5611 tc_valid[i] = 0;
5612
5613 if (!(hdev->hw_tc_map & BIT(i)))
5614 continue;
5615
5616 tc_valid[i] = 1;
5617 tc_size[i] = roundup_size;
5618 tc_offset[i] = kinfo->rss_size * i;
5619 }
5620 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5621 if (ret)
5622 return ret;
5623
5624 /* Reinitializes the rss indirect table according to the new RSS size */
5625 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5626 if (!rss_indir)
5627 return -ENOMEM;
5628
5629 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5630 rss_indir[i] = i % kinfo->rss_size;
5631
5632 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5633 if (ret)
5634 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5635 ret);
5636
5637 kfree(rss_indir);
5638
5639 if (!ret)
5640 dev_info(&hdev->pdev->dev,
5641 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5642 cur_rss_size, kinfo->rss_size,
5643 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5644
5645 return ret;
5646}
5647
db2a3e43
FL		 5648static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5649 u32 *regs_num_64_bit)
5650{
5651 struct hclge_desc desc;
5652 u32 total_num;
5653 int ret;
5654
5655 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5656 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5657 if (ret) {
5658 dev_err(&hdev->pdev->dev,
5659 "Query register number cmd failed, ret = %d.\n", ret);
5660 return ret;
5661 }
5662
5663 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5664 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5665
5666 total_num = *regs_num_32_bit + *regs_num_64_bit;
5667 if (!total_num)
5668 return -EINVAL;
5669
5670 return 0;
5671}
5672
5673static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5674 void *data)
5675{
5676#define HCLGE_32_BIT_REG_RTN_DATANUM 8
5677
5678 struct hclge_desc *desc;
5679 u32 *reg_val = data;
5680 __le32 *desc_data;
5681 int cmd_num;
5682 int i, k, n;
5683 int ret;
5684
5685 if (regs_num == 0)
5686 return 0;
5687
5688 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
5689 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5690 if (!desc)
5691 return -ENOMEM;
5692
5693 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
5694 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5695 if (ret) {
5696 dev_err(&hdev->pdev->dev,
5697 "Query 32 bit register cmd failed, ret = %d.\n", ret);
5698 kfree(desc);
5699 return ret;
5700 }
5701
5702 for (i = 0; i < cmd_num; i++) {
5703 if (i == 0) {
5704 desc_data = (__le32 *)(&desc[i].data[0]);
5705 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
5706 } else {
5707 desc_data = (__le32 *)(&desc[i]);
5708 n = HCLGE_32_BIT_REG_RTN_DATANUM;
5709 }
5710 for (k = 0; k < n; k++) {
5711 *reg_val++ = le32_to_cpu(*desc_data++);
5712
5713 regs_num--;
5714 if (!regs_num)
5715 break;
5716 }
5717 }
5718
5719 kfree(desc);
5720 return 0;
5721}
5722
5723static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5724 void *data)
5725{
5726#define HCLGE_64_BIT_REG_RTN_DATANUM 4
5727
5728 struct hclge_desc *desc;
5729 u64 *reg_val = data;
5730 __le64 *desc_data;
5731 int cmd_num;
5732 int i, k, n;
5733 int ret;
5734
5735 if (regs_num == 0)
5736 return 0;
5737
5738 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
5739 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5740 if (!desc)
5741 return -ENOMEM;
5742
5743 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
5744 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5745 if (ret) {
5746 dev_err(&hdev->pdev->dev,
5747 "Query 64 bit register cmd failed, ret = %d.\n", ret);
5748 kfree(desc);
5749 return ret;
5750 }
5751
5752 for (i = 0; i < cmd_num; i++) {
5753 if (i == 0) {
5754 desc_data = (__le64 *)(&desc[i].data[0]);
5755 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
5756 } else {
5757 desc_data = (__le64 *)(&desc[i]);
5758 n = HCLGE_64_BIT_REG_RTN_DATANUM;
5759 }
5760 for (k = 0; k < n; k++) {
5761 *reg_val++ = le64_to_cpu(*desc_data++);
5762
5763 regs_num--;
5764 if (!regs_num)
5765 break;
5766 }
5767 }
5768
5769 kfree(desc);
5770 return 0;
5771}
5772
5773static int hclge_get_regs_len(struct hnae3_handle *handle)
5774{
5775 struct hclge_vport *vport = hclge_get_vport(handle);
5776 struct hclge_dev *hdev = vport->back;
5777 u32 regs_num_32_bit, regs_num_64_bit;
5778 int ret;
5779
5780 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5781 if (ret) {
5782 dev_err(&hdev->pdev->dev,
5783 "Get register number failed, ret = %d.\n", ret);
5784 return -EOPNOTSUPP;
5785 }
5786
5787 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
5788}
5789
5790static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
5791 void *data)
5792{
5793 struct hclge_vport *vport = hclge_get_vport(handle);
5794 struct hclge_dev *hdev = vport->back;
5795 u32 regs_num_32_bit, regs_num_64_bit;
5796 int ret;
5797
5798 *version = hdev->fw_version;
5799
5800 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5801 if (ret) {
5802 dev_err(&hdev->pdev->dev,
5803 "Get register number failed, ret = %d.\n", ret);
5804 return;
5805 }
5806
5807 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
5808 if (ret) {
5809 dev_err(&hdev->pdev->dev,
5810 "Get 32 bit register failed, ret = %d.\n", ret);
5811 return;
5812 }
5813
5814 data = (u32 *)data + regs_num_32_bit;
5815 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
5816 data);
5817 if (ret)
5818 dev_err(&hdev->pdev->dev,
5819 "Get 64 bit register failed, ret = %d.\n", ret);
5820}
5821
d9a0884e
JS		 5822static int hclge_set_led_status_sfp(struct hclge_dev *hdev, u8 speed_led_status,
5823 u8 act_led_status, u8 link_led_status,
5824 u8 locate_led_status)
5825{
5826 struct hclge_set_led_state_cmd *req;
5827 struct hclge_desc desc;
5828 int ret;
5829
5830 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
5831
5832 req = (struct hclge_set_led_state_cmd *)desc.data;
5833 hnae_set_field(req->port_speed_led_config, HCLGE_LED_PORT_SPEED_STATE_M,
5834 HCLGE_LED_PORT_SPEED_STATE_S, speed_led_status);
5835 hnae_set_field(req->link_led_config, HCLGE_LED_ACTIVITY_STATE_M,
5836 HCLGE_LED_ACTIVITY_STATE_S, act_led_status);
5837 hnae_set_field(req->activity_led_config, HCLGE_LED_LINK_STATE_M,
5838 HCLGE_LED_LINK_STATE_S, link_led_status);
5839 hnae_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
5840 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
5841
5842 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5843 if (ret)
5844 dev_err(&hdev->pdev->dev,
5845 "Send set led state cmd error, ret =%d\n", ret);
5846
5847 return ret;
5848}
5849
5850enum hclge_led_status {
5851 HCLGE_LED_OFF,
5852 HCLGE_LED_ON,
5853 HCLGE_LED_NO_CHANGE = 0xFF,
5854};
5855
5856static int hclge_set_led_id(struct hnae3_handle *handle,
5857 enum ethtool_phys_id_state status)
5858{
5859#define BLINK_FREQUENCY 2
5860 struct hclge_vport *vport = hclge_get_vport(handle);
5861 struct hclge_dev *hdev = vport->back;
5862 struct phy_device *phydev = hdev->hw.mac.phydev;
5863 int ret = 0;
5864
5865 if (phydev || hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
5866 return -EOPNOTSUPP;
5867
5868 switch (status) {
5869 case ETHTOOL_ID_ACTIVE:
5870 ret = hclge_set_led_status_sfp(hdev,
5871 HCLGE_LED_NO_CHANGE,
5872 HCLGE_LED_NO_CHANGE,
5873 HCLGE_LED_NO_CHANGE,
5874 HCLGE_LED_ON);
5875 break;
5876 case ETHTOOL_ID_INACTIVE:
5877 ret = hclge_set_led_status_sfp(hdev,
5878 HCLGE_LED_NO_CHANGE,
5879 HCLGE_LED_NO_CHANGE,
5880 HCLGE_LED_NO_CHANGE,
5881 HCLGE_LED_OFF);
5882 break;
5883 default:
5884 ret = -EINVAL;
5885 break;
5886 }
5887
5888 return ret;
5889}
5890
46a3df9f
S		 5891static const struct hnae3_ae_ops hclge_ops = {
5892 .init_ae_dev = hclge_init_ae_dev,
5893 .uninit_ae_dev = hclge_uninit_ae_dev,
5894 .init_client_instance = hclge_init_client_instance,
5895 .uninit_client_instance = hclge_uninit_client_instance,
63d7e66f
SM		 5896 .map_ring_to_vector = hclge_map_ring_to_vector,
5897 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f
S		 5898 .get_vector = hclge_get_vector,
5899 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 5900 .set_loopback = hclge_set_loopback,
46a3df9f
S		 5901 .start = hclge_ae_start,
5902 .stop = hclge_ae_stop,
5903 .get_status = hclge_get_status,
5904 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5905 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5906 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5907 .get_media_type = hclge_get_media_type,
5908 .get_rss_key_size = hclge_get_rss_key_size,
5909 .get_rss_indir_size = hclge_get_rss_indir_size,
5910 .get_rss = hclge_get_rss,
5911 .set_rss = hclge_set_rss,
f7db940a 5912 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 5913 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 5914 .get_tc_size = hclge_get_tc_size,
5915 .get_mac_addr = hclge_get_mac_addr,
5916 .set_mac_addr = hclge_set_mac_addr,
5917 .add_uc_addr = hclge_add_uc_addr,
5918 .rm_uc_addr = hclge_rm_uc_addr,
5919 .add_mc_addr = hclge_add_mc_addr,
5920 .rm_mc_addr = hclge_rm_mc_addr,
5921 .set_autoneg = hclge_set_autoneg,
5922 .get_autoneg = hclge_get_autoneg,
5923 .get_pauseparam = hclge_get_pauseparam,
09ea401e 5924 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 5925 .set_mtu = hclge_set_mtu,
5926 .reset_queue = hclge_reset_tqp,
5927 .get_stats = hclge_get_stats,
5928 .update_stats = hclge_update_stats,
5929 .get_strings = hclge_get_strings,
5930 .get_sset_count = hclge_get_sset_count,
5931 .get_fw_version = hclge_get_fw_version,
5932 .get_mdix_mode = hclge_get_mdix_mode,
d818396d 5933 .enable_vlan_filter = hclge_enable_vlan_filter,
46a3df9f
S		 5934 .set_vlan_filter = hclge_set_port_vlan_filter,
5935 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5f9a7732 5936 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 5937 .reset_event = hclge_reset_event,
f1f779ce
PL		 5938 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
5939 .set_channels = hclge_set_channels,
4f645a90 5940 .get_channels = hclge_get_channels,
a2cfbadb 5941 .get_flowctrl_adv = hclge_get_flowctrl_adv,
db2a3e43
FL		 5942 .get_regs_len = hclge_get_regs_len,
5943 .get_regs = hclge_get_regs,
d9a0884e 5944 .set_led_id = hclge_set_led_id,
46a3df9f
S		 5945};
5946
5947static struct hnae3_ae_algo ae_algo = {
5948 .ops = &hclge_ops,
5949 .name = HCLGE_NAME,
5950 .pdev_id_table = ae_algo_pci_tbl,
5951};
5952
5953static int hclge_init(void)
5954{
5955 pr_info("%s is initializing\n", HCLGE_NAME);
5956
5957 return hnae3_register_ae_algo(&ae_algo);
5958}
5959
5960static void hclge_exit(void)
5961{
5962 hnae3_unregister_ae_algo(&ae_algo);
5963}
5964module_init(hclge_init);
5965module_exit(hclge_exit);
5966
5967MODULE_LICENSE("GPL");
5968MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5969MODULE_DESCRIPTION("HCLGE Driver");
5970MODULE_VERSION(HCLGE_MOD_VERSION);
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