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net: hns3: refactor the hclge_get/set_rss function
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
7393ed39 20#include <linux/if_vlan.h>
d5752031 21#include <net/rtnetlink.h>
46a3df9f 22#include "hclge_cmd.h"
cacde272 23#include "hclge_dcb.h"
46a3df9f 24#include "hclge_main.h"
0cdbdd3e 25#include "hclge_mbx.h"
46a3df9f
S		 26#include "hclge_mdio.h"
27#include "hclge_tm.h"
28#include "hnae3.h"
29
30#define HCLGE_NAME "hclge"
31#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35
46a3df9f
S		 36static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
37 enum hclge_mta_dmac_sel_type mta_mac_sel,
38 bool enable);
59bc85ec 39static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 40static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 41static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
fe36292f 42static int hclge_update_led_status(struct hclge_dev *hdev);
46a3df9f
S		 43
44static struct hnae3_ae_algo ae_algo;
45
46static const struct pci_device_id ae_algo_pci_tbl[] = {
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 54 /* required last entry */
46a3df9f
S		 55 {0, }
56};
57
28d9cec8
YL		 58MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
59
46a3df9f
S		 60static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
61 "Mac Loopback test",
62 "Serdes Loopback test",
63 "Phy Loopback test"
64};
65
66static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
67 {"igu_rx_oversize_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
69 {"igu_rx_undersize_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
71 {"igu_rx_out_all_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
73 {"igu_rx_uni_pkt",
74 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
75 {"igu_rx_multi_pkt",
76 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
77 {"igu_rx_broad_pkt",
78 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
79 {"egu_tx_out_all_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
81 {"egu_tx_uni_pkt",
82 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
83 {"egu_tx_multi_pkt",
84 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
85 {"egu_tx_broad_pkt",
86 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
87 {"ssu_ppp_mac_key_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
89 {"ssu_ppp_host_key_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
91 {"ppp_ssu_mac_rlt_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
93 {"ppp_ssu_host_rlt_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
95 {"ssu_tx_in_num",
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
97 {"ssu_tx_out_num",
98 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
99 {"ssu_rx_in_num",
100 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
101 {"ssu_rx_out_num",
102 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
103};
104
105static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
106 {"igu_rx_err_pkt",
107 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
108 {"igu_rx_no_eof_pkt",
109 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
110 {"igu_rx_no_sof_pkt",
111 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
112 {"egu_tx_1588_pkt",
113 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
114 {"ssu_full_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
116 {"ssu_part_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
118 {"ppp_key_drop_num",
119 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
120 {"ppp_rlt_drop_num",
121 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
122 {"ssu_key_drop_num",
123 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
124 {"pkt_curr_buf_cnt",
125 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
126 {"qcn_fb_rcv_cnt",
127 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
128 {"qcn_fb_drop_cnt",
129 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
130 {"qcn_fb_invaild_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
132 {"rx_packet_tc0_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
134 {"rx_packet_tc1_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
136 {"rx_packet_tc2_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
138 {"rx_packet_tc3_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
140 {"rx_packet_tc4_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
142 {"rx_packet_tc5_in_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
144 {"rx_packet_tc6_in_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
146 {"rx_packet_tc7_in_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
148 {"rx_packet_tc0_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
150 {"rx_packet_tc1_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
152 {"rx_packet_tc2_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
154 {"rx_packet_tc3_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
156 {"rx_packet_tc4_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
158 {"rx_packet_tc5_out_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
160 {"rx_packet_tc6_out_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
162 {"rx_packet_tc7_out_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
164 {"tx_packet_tc0_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
166 {"tx_packet_tc1_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
168 {"tx_packet_tc2_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
170 {"tx_packet_tc3_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
172 {"tx_packet_tc4_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
174 {"tx_packet_tc5_in_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
176 {"tx_packet_tc6_in_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
178 {"tx_packet_tc7_in_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
180 {"tx_packet_tc0_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
182 {"tx_packet_tc1_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
184 {"tx_packet_tc2_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
186 {"tx_packet_tc3_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
188 {"tx_packet_tc4_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
190 {"tx_packet_tc5_out_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
192 {"tx_packet_tc6_out_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
194 {"tx_packet_tc7_out_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
196 {"pkt_curr_buf_tc0_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
198 {"pkt_curr_buf_tc1_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
200 {"pkt_curr_buf_tc2_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
202 {"pkt_curr_buf_tc3_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
204 {"pkt_curr_buf_tc4_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
206 {"pkt_curr_buf_tc5_cnt",
207 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
208 {"pkt_curr_buf_tc6_cnt",
209 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
210 {"pkt_curr_buf_tc7_cnt",
211 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
212 {"mb_uncopy_num",
213 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
214 {"lo_pri_unicast_rlt_drop_num",
215 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
216 {"hi_pri_multicast_rlt_drop_num",
217 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
218 {"lo_pri_multicast_rlt_drop_num",
219 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
220 {"rx_oq_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
222 {"tx_oq_drop_pkt_cnt",
223 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
224 {"nic_l2_err_drop_pkt_cnt",
225 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
226 {"roc_l2_err_drop_pkt_cnt",
227 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
228};
229
230static const struct hclge_comm_stats_str g_mac_stats_string[] = {
231 {"mac_tx_mac_pause_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
233 {"mac_rx_mac_pause_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
235 {"mac_tx_pfc_pri0_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
237 {"mac_tx_pfc_pri1_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
239 {"mac_tx_pfc_pri2_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
241 {"mac_tx_pfc_pri3_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
243 {"mac_tx_pfc_pri4_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
245 {"mac_tx_pfc_pri5_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
247 {"mac_tx_pfc_pri6_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
249 {"mac_tx_pfc_pri7_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
251 {"mac_rx_pfc_pri0_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
253 {"mac_rx_pfc_pri1_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
255 {"mac_rx_pfc_pri2_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
257 {"mac_rx_pfc_pri3_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
259 {"mac_rx_pfc_pri4_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
261 {"mac_rx_pfc_pri5_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
263 {"mac_rx_pfc_pri6_pkt_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
265 {"mac_rx_pfc_pri7_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
267 {"mac_tx_total_pkt_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
269 {"mac_tx_total_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
271 {"mac_tx_good_pkt_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
273 {"mac_tx_bad_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
275 {"mac_tx_good_oct_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
277 {"mac_tx_bad_oct_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
279 {"mac_tx_uni_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
281 {"mac_tx_multi_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
283 {"mac_tx_broad_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
285 {"mac_tx_undersize_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
f3426583
JS		 287 {"mac_tx_oversize_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 289 {"mac_tx_64_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
291 {"mac_tx_65_127_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
293 {"mac_tx_128_255_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
295 {"mac_tx_256_511_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
297 {"mac_tx_512_1023_oct_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
299 {"mac_tx_1024_1518_oct_pkt_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
b42874e4
JS		 301 {"mac_tx_1519_2047_oct_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
303 {"mac_tx_2048_4095_oct_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
305 {"mac_tx_4096_8191_oct_pkt_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
307 {"mac_tx_8192_12287_oct_pkt_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_12287_oct_pkt_num)},
309 {"mac_tx_8192_9216_oct_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
311 {"mac_tx_9217_12287_oct_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
313 {"mac_tx_12288_16383_oct_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
315 {"mac_tx_1519_max_good_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
317 {"mac_tx_1519_max_bad_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 319 {"mac_rx_total_pkt_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
321 {"mac_rx_total_oct_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
323 {"mac_rx_good_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
325 {"mac_rx_bad_pkt_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
327 {"mac_rx_good_oct_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
329 {"mac_rx_bad_oct_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
331 {"mac_rx_uni_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
333 {"mac_rx_multi_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
335 {"mac_rx_broad_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
337 {"mac_rx_undersize_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
f3426583
JS		 339 {"mac_rx_oversize_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 341 {"mac_rx_64_oct_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
343 {"mac_rx_65_127_oct_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
345 {"mac_rx_128_255_oct_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
347 {"mac_rx_256_511_oct_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
349 {"mac_rx_512_1023_oct_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
351 {"mac_rx_1024_1518_oct_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
b42874e4
JS		 353 {"mac_rx_1519_2047_oct_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
355 {"mac_rx_2048_4095_oct_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
357 {"mac_rx_4096_8191_oct_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
359 {"mac_rx_8192_12287_oct_pkt_num",
360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_12287_oct_pkt_num)},
361 {"mac_rx_8192_9216_oct_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
363 {"mac_rx_9217_12287_oct_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
365 {"mac_rx_12288_16383_oct_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
367 {"mac_rx_1519_max_good_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
369 {"mac_rx_1519_max_bad_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 371
c36317be
JS		 372 {"mac_tx_fragment_pkt_num",
373 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
374 {"mac_tx_undermin_pkt_num",
375 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
376 {"mac_tx_jabber_pkt_num",
377 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
378 {"mac_tx_err_all_pkt_num",
379 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
380 {"mac_tx_from_app_good_pkt_num",
381 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
382 {"mac_tx_from_app_bad_pkt_num",
383 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
384 {"mac_rx_fragment_pkt_num",
385 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
386 {"mac_rx_undermin_pkt_num",
387 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
388 {"mac_rx_jabber_pkt_num",
389 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
390 {"mac_rx_fcs_err_pkt_num",
391 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
392 {"mac_rx_send_app_good_pkt_num",
393 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
394 {"mac_rx_send_app_bad_pkt_num",
395 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 396};
397
635bfb58
FL		 398static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
399 {
400 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
401 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
402 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
403 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
404 .i_port_bitmap = 0x1,
405 },
406};
407
46a3df9f
S		 408static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
409{
410#define HCLGE_64_BIT_CMD_NUM 5
411#define HCLGE_64_BIT_RTN_DATANUM 4
412 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
413 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 414 __le64 *desc_data;
46a3df9f
S		 415 int i, k, n;
416 int ret;
417
418 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
419 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
420 if (ret) {
421 dev_err(&hdev->pdev->dev,
422 "Get 64 bit pkt stats fail, status = %d.\n", ret);
423 return ret;
424 }
425
426 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
427 if (unlikely(i == 0)) {
a90bb9a5 428 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 429 n = HCLGE_64_BIT_RTN_DATANUM - 1;
430 } else {
a90bb9a5 431 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 432 n = HCLGE_64_BIT_RTN_DATANUM;
433 }
434 for (k = 0; k < n; k++) {
a90bb9a5 435 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 436 desc_data++;
437 }
438 }
439
440 return 0;
441}
442
443static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
444{
445 stats->pkt_curr_buf_cnt = 0;
446 stats->pkt_curr_buf_tc0_cnt = 0;
447 stats->pkt_curr_buf_tc1_cnt = 0;
448 stats->pkt_curr_buf_tc2_cnt = 0;
449 stats->pkt_curr_buf_tc3_cnt = 0;
450 stats->pkt_curr_buf_tc4_cnt = 0;
451 stats->pkt_curr_buf_tc5_cnt = 0;
452 stats->pkt_curr_buf_tc6_cnt = 0;
453 stats->pkt_curr_buf_tc7_cnt = 0;
454}
455
456static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
457{
458#define HCLGE_32_BIT_CMD_NUM 8
459#define HCLGE_32_BIT_RTN_DATANUM 8
460
461 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
462 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 463 __le32 *desc_data;
46a3df9f
S		 464 int i, k, n;
465 u64 *data;
466 int ret;
467
468 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
469 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
470
471 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
472 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
473 if (ret) {
474 dev_err(&hdev->pdev->dev,
475 "Get 32 bit pkt stats fail, status = %d.\n", ret);
476
477 return ret;
478 }
479
480 hclge_reset_partial_32bit_counter(all_32_bit_stats);
481 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
482 if (unlikely(i == 0)) {
a90bb9a5
YL		 483 __le16 *desc_data_16bit;
484
46a3df9f 485 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 486 le32_to_cpu(desc[i].data[0]);
487
488 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 489 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 490 le16_to_cpu(*desc_data_16bit);
491
492 desc_data_16bit++;
46a3df9f 493 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 494 le16_to_cpu(*desc_data_16bit);
46a3df9f 495
a90bb9a5 496 desc_data = &desc[i].data[2];
46a3df9f
S		 497 n = HCLGE_32_BIT_RTN_DATANUM - 4;
498 } else {
a90bb9a5 499 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 500 n = HCLGE_32_BIT_RTN_DATANUM;
501 }
502 for (k = 0; k < n; k++) {
a90bb9a5 503 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 504 desc_data++;
505 }
506 }
507
508 return 0;
509}
510
fe36292f
JS		 511static int hclge_mac_get_traffic_stats(struct hclge_dev *hdev)
512{
513 struct hclge_mac_stats *mac_stats = &hdev->hw_stats.mac_stats;
514 struct hclge_desc desc;
515 __le64 *desc_data;
516 int ret;
517
518 /* for fiber port, need to query the total rx/tx packets statstics,
519 * used for data transferring checking.
520 */
521 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
522 return 0;
523
524 if (test_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
525 return 0;
526
527 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_STATS_MAC_TRAFFIC, true);
528 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
529 if (ret) {
530 dev_err(&hdev->pdev->dev,
531 "Get MAC total pkt stats fail, ret = %d\n", ret);
532
533 return ret;
534 }
535
536 desc_data = (__le64 *)(&desc.data[0]);
537 mac_stats->mac_tx_total_pkt_num += le64_to_cpu(*desc_data++);
538 mac_stats->mac_rx_total_pkt_num += le64_to_cpu(*desc_data);
539
540 return 0;
541}
542
46a3df9f
S		 543static int hclge_mac_update_stats(struct hclge_dev *hdev)
544{
b42874e4 545#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 546#define HCLGE_RTN_DATA_NUM 4
547
548 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
549 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 550 __le64 *desc_data;
46a3df9f
S		 551 int i, k, n;
552 int ret;
553
554 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
555 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
556 if (ret) {
557 dev_err(&hdev->pdev->dev,
558 "Get MAC pkt stats fail, status = %d.\n", ret);
559
560 return ret;
561 }
562
563 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
564 if (unlikely(i == 0)) {
a90bb9a5 565 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 566 n = HCLGE_RTN_DATA_NUM - 2;
567 } else {
a90bb9a5 568 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 569 n = HCLGE_RTN_DATA_NUM;
570 }
571 for (k = 0; k < n; k++) {
a90bb9a5 572 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 573 desc_data++;
574 }
575 }
576
577 return 0;
578}
579
580static int hclge_tqps_update_stats(struct hnae3_handle *handle)
581{
582 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
583 struct hclge_vport *vport = hclge_get_vport(handle);
584 struct hclge_dev *hdev = vport->back;
585 struct hnae3_queue *queue;
586 struct hclge_desc desc[1];
587 struct hclge_tqp *tqp;
588 int ret, i;
589
590 for (i = 0; i < kinfo->num_tqps; i++) {
591 queue = handle->kinfo.tqp[i];
592 tqp = container_of(queue, struct hclge_tqp, q);
593 /* command : HCLGE_OPC_QUERY_IGU_STAT */
594 hclge_cmd_setup_basic_desc(&desc[0],
595 HCLGE_OPC_QUERY_RX_STATUS,
596 true);
597
a90bb9a5 598 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 599 ret = hclge_cmd_send(&hdev->hw, desc, 1);
600 if (ret) {
601 dev_err(&hdev->pdev->dev,
602 "Query tqp stat fail, status = %d,queue = %d\n",
603 ret, i);
604 return ret;
605 }
606 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 607 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 608 }
609
610 for (i = 0; i < kinfo->num_tqps; i++) {
611 queue = handle->kinfo.tqp[i];
612 tqp = container_of(queue, struct hclge_tqp, q);
613 /* command : HCLGE_OPC_QUERY_IGU_STAT */
614 hclge_cmd_setup_basic_desc(&desc[0],
615 HCLGE_OPC_QUERY_TX_STATUS,
616 true);
617
a90bb9a5 618 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 619 ret = hclge_cmd_send(&hdev->hw, desc, 1);
620 if (ret) {
621 dev_err(&hdev->pdev->dev,
622 "Query tqp stat fail, status = %d,queue = %d\n",
623 ret, i);
624 return ret;
625 }
626 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 627 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 628 }
629
630 return 0;
631}
632
633static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
634{
635 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
636 struct hclge_tqp *tqp;
637 u64 *buff = data;
638 int i;
639
640 for (i = 0; i < kinfo->num_tqps; i++) {
641 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 642 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 643 }
644
645 for (i = 0; i < kinfo->num_tqps; i++) {
646 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 647 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 648 }
649
650 return buff;
651}
652
653static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
654{
655 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
656
657 return kinfo->num_tqps * (2);
658}
659
660static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
661{
662 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
663 u8 *buff = data;
664 int i = 0;
665
666 for (i = 0; i < kinfo->num_tqps; i++) {
667 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
668 struct hclge_tqp, q);
c36317be 669 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
46a3df9f
S		 670 tqp->index);
671 buff = buff + ETH_GSTRING_LEN;
672 }
673
674 for (i = 0; i < kinfo->num_tqps; i++) {
675 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
676 struct hclge_tqp, q);
c36317be 677 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
46a3df9f
S		 678 tqp->index);
679 buff = buff + ETH_GSTRING_LEN;
680 }
681
682 return buff;
683}
684
685static u64 *hclge_comm_get_stats(void *comm_stats,
686 const struct hclge_comm_stats_str strs[],
687 int size, u64 *data)
688{
689 u64 *buf = data;
690 u32 i;
691
692 for (i = 0; i < size; i++)
693 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
694
695 return buf + size;
696}
697
698static u8 *hclge_comm_get_strings(u32 stringset,
699 const struct hclge_comm_stats_str strs[],
700 int size, u8 *data)
701{
702 char *buff = (char *)data;
703 u32 i;
704
705 if (stringset != ETH_SS_STATS)
706 return buff;
707
708 for (i = 0; i < size; i++) {
709 snprintf(buff, ETH_GSTRING_LEN,
710 strs[i].desc);
711 buff = buff + ETH_GSTRING_LEN;
712 }
713
714 return (u8 *)buff;
715}
716
717static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
718 struct net_device_stats *net_stats)
719{
720 net_stats->tx_dropped = 0;
721 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
722 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
723 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
724
f3426583 725 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 726 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
46a3df9f
S		 727 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
728 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
c36317be 729 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 730
731 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
732 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
733
c36317be 734 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 735 net_stats->rx_length_errors =
736 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
737 net_stats->rx_length_errors +=
f3426583 738 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 739 net_stats->rx_over_errors =
f3426583 740 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 741}
742
743static void hclge_update_stats_for_all(struct hclge_dev *hdev)
744{
745 struct hnae3_handle *handle;
746 int status;
747
748 handle = &hdev->vport[0].nic;
749 if (handle->client) {
750 status = hclge_tqps_update_stats(handle);
751 if (status) {
752 dev_err(&hdev->pdev->dev,
753 "Update TQPS stats fail, status = %d.\n",
754 status);
755 }
756 }
757
758 status = hclge_mac_update_stats(hdev);
759 if (status)
760 dev_err(&hdev->pdev->dev,
761 "Update MAC stats fail, status = %d.\n", status);
762
763 status = hclge_32_bit_update_stats(hdev);
764 if (status)
765 dev_err(&hdev->pdev->dev,
766 "Update 32 bit stats fail, status = %d.\n",
767 status);
768
769 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
770}
771
772static void hclge_update_stats(struct hnae3_handle *handle,
773 struct net_device_stats *net_stats)
774{
775 struct hclge_vport *vport = hclge_get_vport(handle);
776 struct hclge_dev *hdev = vport->back;
777 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
778 int status;
779
7a5d2a39
JS		 780 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
781 return;
782
46a3df9f
S		 783 status = hclge_mac_update_stats(hdev);
784 if (status)
785 dev_err(&hdev->pdev->dev,
786 "Update MAC stats fail, status = %d.\n",
787 status);
788
789 status = hclge_32_bit_update_stats(hdev);
790 if (status)
791 dev_err(&hdev->pdev->dev,
792 "Update 32 bit stats fail, status = %d.\n",
793 status);
794
795 status = hclge_64_bit_update_stats(hdev);
796 if (status)
797 dev_err(&hdev->pdev->dev,
798 "Update 64 bit stats fail, status = %d.\n",
799 status);
800
801 status = hclge_tqps_update_stats(handle);
802 if (status)
803 dev_err(&hdev->pdev->dev,
804 "Update TQPS stats fail, status = %d.\n",
805 status);
806
807 hclge_update_netstat(hw_stats, net_stats);
7a5d2a39
JS		 808
809 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 810}
811
812static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
813{
814#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
815
816 struct hclge_vport *vport = hclge_get_vport(handle);
817 struct hclge_dev *hdev = vport->back;
818 int count = 0;
819
820 /* Loopback test support rules:
821 * mac: only GE mode support
822 * serdes: all mac mode will support include GE/XGE/LGE/CGE
823 * phy: only support when phy device exist on board
824 */
825 if (stringset == ETH_SS_TEST) {
826 /* clear loopback bit flags at first */
827 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
828 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
829 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
830 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
831 count += 1;
832 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
833 } else {
834 count = -EOPNOTSUPP;
835 }
836 } else if (stringset == ETH_SS_STATS) {
837 count = ARRAY_SIZE(g_mac_stats_string) +
838 ARRAY_SIZE(g_all_32bit_stats_string) +
839 ARRAY_SIZE(g_all_64bit_stats_string) +
840 hclge_tqps_get_sset_count(handle, stringset);
841 }
842
843 return count;
844}
845
846static void hclge_get_strings(struct hnae3_handle *handle,
847 u32 stringset,
848 u8 *data)
849{
850 u8 *p = (char *)data;
851 int size;
852
853 if (stringset == ETH_SS_STATS) {
854 size = ARRAY_SIZE(g_mac_stats_string);
855 p = hclge_comm_get_strings(stringset,
856 g_mac_stats_string,
857 size,
858 p);
859 size = ARRAY_SIZE(g_all_32bit_stats_string);
860 p = hclge_comm_get_strings(stringset,
861 g_all_32bit_stats_string,
862 size,
863 p);
864 size = ARRAY_SIZE(g_all_64bit_stats_string);
865 p = hclge_comm_get_strings(stringset,
866 g_all_64bit_stats_string,
867 size,
868 p);
869 p = hclge_tqps_get_strings(handle, p);
870 } else if (stringset == ETH_SS_TEST) {
871 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
872 memcpy(p,
873 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
874 ETH_GSTRING_LEN);
875 p += ETH_GSTRING_LEN;
876 }
877 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
878 memcpy(p,
879 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
880 ETH_GSTRING_LEN);
881 p += ETH_GSTRING_LEN;
882 }
883 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
884 memcpy(p,
885 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
886 ETH_GSTRING_LEN);
887 p += ETH_GSTRING_LEN;
888 }
889 }
890}
891
892static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
893{
894 struct hclge_vport *vport = hclge_get_vport(handle);
895 struct hclge_dev *hdev = vport->back;
896 u64 *p;
897
898 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
899 g_mac_stats_string,
900 ARRAY_SIZE(g_mac_stats_string),
901 data);
902 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
903 g_all_32bit_stats_string,
904 ARRAY_SIZE(g_all_32bit_stats_string),
905 p);
906 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
907 g_all_64bit_stats_string,
908 ARRAY_SIZE(g_all_64bit_stats_string),
909 p);
910 p = hclge_tqps_get_stats(handle, p);
911}
912
913static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 914 struct hclge_func_status_cmd *status)
46a3df9f
S		 915{
916 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
917 return -EINVAL;
918
919 /* Set the pf to main pf */
920 if (status->pf_state & HCLGE_PF_STATE_MAIN)
921 hdev->flag |= HCLGE_FLAG_MAIN;
922 else
923 hdev->flag &= ~HCLGE_FLAG_MAIN;
924
46a3df9f
S		 925 return 0;
926}
927
928static int hclge_query_function_status(struct hclge_dev *hdev)
929{
d44f9b63 930 struct hclge_func_status_cmd *req;
46a3df9f
S		 931 struct hclge_desc desc;
932 int timeout = 0;
933 int ret;
934
935 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 936 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 937
938 do {
939 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
940 if (ret) {
941 dev_err(&hdev->pdev->dev,
942 "query function status failed %d.\n",
943 ret);
944
945 return ret;
946 }
947
948 /* Check pf reset is done */
949 if (req->pf_state)
950 break;
951 usleep_range(1000, 2000);
952 } while (timeout++ < 5);
953
954 ret = hclge_parse_func_status(hdev, req);
955
956 return ret;
957}
958
959static int hclge_query_pf_resource(struct hclge_dev *hdev)
960{
d44f9b63 961 struct hclge_pf_res_cmd *req;
46a3df9f
S		 962 struct hclge_desc desc;
963 int ret;
964
965 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
966 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
967 if (ret) {
968 dev_err(&hdev->pdev->dev,
969 "query pf resource failed %d.\n", ret);
970 return ret;
971 }
972
d44f9b63 973 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 974 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
975 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
976
e92a0843 977 if (hnae3_dev_roce_supported(hdev)) {
887c3820 978 hdev->num_roce_msi =
46a3df9f
S		 979 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
980 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
981
982 /* PF should have NIC vectors and Roce vectors,
983 * NIC vectors are queued before Roce vectors.
984 */
887c3820 985 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 986 } else {
987 hdev->num_msi =
988 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
989 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
990 }
991
992 return 0;
993}
994
995static int hclge_parse_speed(int speed_cmd, int *speed)
996{
997 switch (speed_cmd) {
998 case 6:
999 *speed = HCLGE_MAC_SPEED_10M;
1000 break;
1001 case 7:
1002 *speed = HCLGE_MAC_SPEED_100M;
1003 break;
1004 case 0:
1005 *speed = HCLGE_MAC_SPEED_1G;
1006 break;
1007 case 1:
1008 *speed = HCLGE_MAC_SPEED_10G;
1009 break;
1010 case 2:
1011 *speed = HCLGE_MAC_SPEED_25G;
1012 break;
1013 case 3:
1014 *speed = HCLGE_MAC_SPEED_40G;
1015 break;
1016 case 4:
1017 *speed = HCLGE_MAC_SPEED_50G;
1018 break;
1019 case 5:
1020 *speed = HCLGE_MAC_SPEED_100G;
1021 break;
1022 default:
1023 return -EINVAL;
1024 }
1025
1026 return 0;
1027}
1028
1029static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1030{
d44f9b63 1031 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1032 u64 mac_addr_tmp_high;
1033 u64 mac_addr_tmp;
1034 int i;
1035
d44f9b63 1036 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 1037
1038 /* get the configuration */
1039 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1040 HCLGE_CFG_VMDQ_M,
1041 HCLGE_CFG_VMDQ_S);
1042 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1043 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1044 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1045 HCLGE_CFG_TQP_DESC_N_M,
1046 HCLGE_CFG_TQP_DESC_N_S);
1047
1048 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
1049 HCLGE_CFG_PHY_ADDR_M,
1050 HCLGE_CFG_PHY_ADDR_S);
1051 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
1052 HCLGE_CFG_MEDIA_TP_M,
1053 HCLGE_CFG_MEDIA_TP_S);
1054 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
1055 HCLGE_CFG_RX_BUF_LEN_M,
1056 HCLGE_CFG_RX_BUF_LEN_S);
1057 /* get mac_address */
1058 mac_addr_tmp = __le32_to_cpu(req->param[2]);
1059 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
1060 HCLGE_CFG_MAC_ADDR_H_M,
1061 HCLGE_CFG_MAC_ADDR_H_S);
1062
1063 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1064
1065 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
1066 HCLGE_CFG_DEFAULT_SPEED_M,
1067 HCLGE_CFG_DEFAULT_SPEED_S);
c408e202
PL		 1068 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]),
1069 HCLGE_CFG_RSS_SIZE_M,
1070 HCLGE_CFG_RSS_SIZE_S);
1071
46a3df9f
S		 1072 for (i = 0; i < ETH_ALEN; i++)
1073 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1074
d44f9b63 1075 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f
S		 1076 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1077}
1078
1079/* hclge_get_cfg: query the static parameter from flash
1080 * @hdev: pointer to struct hclge_dev
1081 * @hcfg: the config structure to be getted
1082 */
1083static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1084{
1085 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 1086 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1087 int i, ret;
1088
1089 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1090 u32 offset = 0;
1091
d44f9b63 1092 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1093 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1094 true);
a90bb9a5 1095 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
46a3df9f
S		 1096 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1097 /* Len should be united by 4 bytes when send to hardware */
a90bb9a5 1098 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
46a3df9f 1099 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1100 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1101 }
1102
1103 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1104 if (ret) {
1105 dev_err(&hdev->pdev->dev,
1106 "get config failed %d.\n", ret);
1107 return ret;
1108 }
1109
1110 hclge_parse_cfg(hcfg, desc);
1111 return 0;
1112}
1113
1114static int hclge_get_cap(struct hclge_dev *hdev)
1115{
1116 int ret;
1117
1118 ret = hclge_query_function_status(hdev);
1119 if (ret) {
1120 dev_err(&hdev->pdev->dev,
1121 "query function status error %d.\n", ret);
1122 return ret;
1123 }
1124
1125 /* get pf resource */
1126 ret = hclge_query_pf_resource(hdev);
1127 if (ret) {
1128 dev_err(&hdev->pdev->dev,
1129 "query pf resource error %d.\n", ret);
1130 return ret;
1131 }
1132
1133 return 0;
1134}
1135
1136static int hclge_configure(struct hclge_dev *hdev)
1137{
1138 struct hclge_cfg cfg;
1139 int ret, i;
1140
1141 ret = hclge_get_cfg(hdev, &cfg);
1142 if (ret) {
1143 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1144 return ret;
1145 }
1146
1147 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1148 hdev->base_tqp_pid = 0;
c408e202 1149 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 1150 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1151 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1152 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1153 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1154 hdev->num_desc = cfg.tqp_desc_num;
1155 hdev->tm_info.num_pg = 1;
cacde272 1156 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1157 hdev->tm_info.hw_pfc_map = 0;
1158
1159 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1160 if (ret) {
1161 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1162 return ret;
1163 }
1164
cacde272
YL		 1165 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1166 (hdev->tc_max < 1)) {
46a3df9f 1167 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1168 hdev->tc_max);
1169 hdev->tc_max = 1;
46a3df9f
S		 1170 }
1171
cacde272
YL		 1172 /* Dev does not support DCB */
1173 if (!hnae3_dev_dcb_supported(hdev)) {
1174 hdev->tc_max = 1;
1175 hdev->pfc_max = 0;
1176 } else {
1177 hdev->pfc_max = hdev->tc_max;
1178 }
1179
1180 hdev->tm_info.num_tc = hdev->tc_max;
1181
46a3df9f 1182 /* Currently not support uncontiuous tc */
cacde272 1183 for (i = 0; i < hdev->tm_info.num_tc; i++)
46a3df9f
S		 1184 hnae_set_bit(hdev->hw_tc_map, i, 1);
1185
f8362fe1 1186 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 1187
1188 return ret;
1189}
1190
1191static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1192 int tso_mss_max)
1193{
d44f9b63 1194 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1195 struct hclge_desc desc;
a90bb9a5 1196 u16 tso_mss;
46a3df9f
S		 1197
1198 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1199
d44f9b63 1200 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1201
1202 tso_mss = 0;
1203 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1204 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1205 req->tso_mss_min = cpu_to_le16(tso_mss);
1206
1207 tso_mss = 0;
1208 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1209 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1210 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1211
1212 return hclge_cmd_send(&hdev->hw, &desc, 1);
1213}
1214
1215static int hclge_alloc_tqps(struct hclge_dev *hdev)
1216{
1217 struct hclge_tqp *tqp;
1218 int i;
1219
1220 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1221 sizeof(struct hclge_tqp), GFP_KERNEL);
1222 if (!hdev->htqp)
1223 return -ENOMEM;
1224
1225 tqp = hdev->htqp;
1226
1227 for (i = 0; i < hdev->num_tqps; i++) {
1228 tqp->dev = &hdev->pdev->dev;
1229 tqp->index = i;
1230
1231 tqp->q.ae_algo = &ae_algo;
1232 tqp->q.buf_size = hdev->rx_buf_len;
1233 tqp->q.desc_num = hdev->num_desc;
1234 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1235 i * HCLGE_TQP_REG_SIZE;
1236
1237 tqp++;
1238 }
1239
1240 return 0;
1241}
1242
1243static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1244 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1245{
d44f9b63 1246 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1247 struct hclge_desc desc;
1248 int ret;
1249
1250 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1251
d44f9b63 1252 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1253 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1254 req->tqp_vf = func_id;
46a3df9f
S		 1255 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1256 1 << HCLGE_TQP_MAP_EN_B;
1257 req->tqp_vid = cpu_to_le16(tqp_vid);
1258
1259 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1260 if (ret) {
1261 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1262 ret);
1263 return ret;
1264 }
1265
1266 return 0;
1267}
1268
1269static int hclge_assign_tqp(struct hclge_vport *vport,
1270 struct hnae3_queue **tqp, u16 num_tqps)
1271{
1272 struct hclge_dev *hdev = vport->back;
7df7dad6 1273 int i, alloced;
46a3df9f
S		 1274
1275 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1276 alloced < num_tqps; i++) {
1277 if (!hdev->htqp[i].alloced) {
1278 hdev->htqp[i].q.handle = &vport->nic;
1279 hdev->htqp[i].q.tqp_index = alloced;
1280 tqp[alloced] = &hdev->htqp[i].q;
1281 hdev->htqp[i].alloced = true;
46a3df9f
S		 1282 alloced++;
1283 }
1284 }
1285 vport->alloc_tqps = num_tqps;
1286
1287 return 0;
1288}
1289
1290static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1291{
1292 struct hnae3_handle *nic = &vport->nic;
1293 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1294 struct hclge_dev *hdev = vport->back;
1295 int i, ret;
1296
1297 kinfo->num_desc = hdev->num_desc;
1298 kinfo->rx_buf_len = hdev->rx_buf_len;
1299 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1300 kinfo->rss_size
1301 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1302 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1303
1304 for (i = 0; i < HNAE3_MAX_TC; i++) {
1305 if (hdev->hw_tc_map & BIT(i)) {
1306 kinfo->tc_info[i].enable = true;
1307 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1308 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1309 kinfo->tc_info[i].tc = i;
1310 } else {
1311 /* Set to default queue if TC is disable */
1312 kinfo->tc_info[i].enable = false;
1313 kinfo->tc_info[i].tqp_offset = 0;
1314 kinfo->tc_info[i].tqp_count = 1;
1315 kinfo->tc_info[i].tc = 0;
1316 }
1317 }
1318
1319 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1320 sizeof(struct hnae3_queue *), GFP_KERNEL);
1321 if (!kinfo->tqp)
1322 return -ENOMEM;
1323
1324 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1325 if (ret) {
1326 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1327 return -EINVAL;
1328 }
1329
1330 return 0;
1331}
1332
7df7dad6
L		 1333static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1334 struct hclge_vport *vport)
1335{
1336 struct hnae3_handle *nic = &vport->nic;
1337 struct hnae3_knic_private_info *kinfo;
1338 u16 i;
1339
1340 kinfo = &nic->kinfo;
1341 for (i = 0; i < kinfo->num_tqps; i++) {
1342 struct hclge_tqp *q =
1343 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1344 bool is_pf;
1345 int ret;
1346
1347 is_pf = !(vport->vport_id);
1348 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1349 i, is_pf);
1350 if (ret)
1351 return ret;
1352 }
1353
1354 return 0;
1355}
1356
1357static int hclge_map_tqp(struct hclge_dev *hdev)
1358{
1359 struct hclge_vport *vport = hdev->vport;
1360 u16 i, num_vport;
1361
1362 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1363 for (i = 0; i < num_vport; i++) {
1364 int ret;
1365
1366 ret = hclge_map_tqp_to_vport(hdev, vport);
1367 if (ret)
1368 return ret;
1369
1370 vport++;
1371 }
1372
1373 return 0;
1374}
1375
46a3df9f
S		 1376static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1377{
1378 /* this would be initialized later */
1379}
1380
1381static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1382{
1383 struct hnae3_handle *nic = &vport->nic;
1384 struct hclge_dev *hdev = vport->back;
1385 int ret;
1386
1387 nic->pdev = hdev->pdev;
1388 nic->ae_algo = &ae_algo;
1389 nic->numa_node_mask = hdev->numa_node_mask;
1390
1391 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1392 ret = hclge_knic_setup(vport, num_tqps);
1393 if (ret) {
1394 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1395 ret);
1396 return ret;
1397 }
1398 } else {
1399 hclge_unic_setup(vport, num_tqps);
1400 }
1401
1402 return 0;
1403}
1404
1405static int hclge_alloc_vport(struct hclge_dev *hdev)
1406{
1407 struct pci_dev *pdev = hdev->pdev;
1408 struct hclge_vport *vport;
1409 u32 tqp_main_vport;
1410 u32 tqp_per_vport;
1411 int num_vport, i;
1412 int ret;
1413
1414 /* We need to alloc a vport for main NIC of PF */
1415 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1416
1417 if (hdev->num_tqps < num_vport)
1418 num_vport = hdev->num_tqps;
1419
1420 /* Alloc the same number of TQPs for every vport */
1421 tqp_per_vport = hdev->num_tqps / num_vport;
1422 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1423
1424 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1425 GFP_KERNEL);
1426 if (!vport)
1427 return -ENOMEM;
1428
1429 hdev->vport = vport;
1430 hdev->num_alloc_vport = num_vport;
1431
1432#ifdef CONFIG_PCI_IOV
1433 /* Enable SRIOV */
1434 if (hdev->num_req_vfs) {
1435 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1436 hdev->num_req_vfs);
1437 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1438 if (ret) {
1439 hdev->num_alloc_vfs = 0;
1440 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1441 ret);
1442 return ret;
1443 }
1444 }
1445 hdev->num_alloc_vfs = hdev->num_req_vfs;
1446#endif
1447
1448 for (i = 0; i < num_vport; i++) {
1449 vport->back = hdev;
1450 vport->vport_id = i;
1451
1452 if (i == 0)
1453 ret = hclge_vport_setup(vport, tqp_main_vport);
1454 else
1455 ret = hclge_vport_setup(vport, tqp_per_vport);
1456 if (ret) {
1457 dev_err(&pdev->dev,
1458 "vport setup failed for vport %d, %d\n",
1459 i, ret);
1460 return ret;
1461 }
1462
1463 vport++;
1464 }
1465
1466 return 0;
1467}
1468
acf61ecd
YL		 1469static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1470 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1471{
1472/* TX buffer size is unit by 128 byte */
1473#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1474#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1475 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1476 struct hclge_desc desc;
1477 int ret;
1478 u8 i;
1479
d44f9b63 1480 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1481
1482 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1483 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1484 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1485
46a3df9f
S		 1486 req->tx_pkt_buff[i] =
1487 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1488 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1489 }
46a3df9f
S		 1490
1491 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1492 if (ret) {
1493 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1494 ret);
1495 return ret;
1496 }
1497
1498 return 0;
1499}
1500
acf61ecd
YL		 1501static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1502 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1503{
acf61ecd 1504 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1505
1506 if (ret) {
1507 dev_err(&hdev->pdev->dev,
1508 "tx buffer alloc failed %d\n", ret);
1509 return ret;
1510 }
1511
1512 return 0;
1513}
1514
1515static int hclge_get_tc_num(struct hclge_dev *hdev)
1516{
1517 int i, cnt = 0;
1518
1519 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1520 if (hdev->hw_tc_map & BIT(i))
1521 cnt++;
1522 return cnt;
1523}
1524
1525static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1526{
1527 int i, cnt = 0;
1528
1529 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1530 if (hdev->hw_tc_map & BIT(i) &&
1531 hdev->tm_info.hw_pfc_map & BIT(i))
1532 cnt++;
1533 return cnt;
1534}
1535
1536/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1537static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1538 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1539{
1540 struct hclge_priv_buf *priv;
1541 int i, cnt = 0;
1542
1543 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1544 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1545 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1546 priv->enable)
1547 cnt++;
1548 }
1549
1550 return cnt;
1551}
1552
1553/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1554static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1555 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1556{
1557 struct hclge_priv_buf *priv;
1558 int i, cnt = 0;
1559
1560 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1561 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1562 if (hdev->hw_tc_map & BIT(i) &&
1563 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1564 priv->enable)
1565 cnt++;
1566 }
1567
1568 return cnt;
1569}
1570
acf61ecd 1571static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1572{
1573 struct hclge_priv_buf *priv;
1574 u32 rx_priv = 0;
1575 int i;
1576
1577 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1578 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1579 if (priv->enable)
1580 rx_priv += priv->buf_size;
1581 }
1582 return rx_priv;
1583}
1584
acf61ecd 1585static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1586{
1587 u32 i, total_tx_size = 0;
1588
1589 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1590 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1591
1592 return total_tx_size;
1593}
1594
acf61ecd
YL		 1595static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1596 struct hclge_pkt_buf_alloc *buf_alloc,
1597 u32 rx_all)
46a3df9f
S		 1598{
1599 u32 shared_buf_min, shared_buf_tc, shared_std;
1600 int tc_num, pfc_enable_num;
1601 u32 shared_buf;
1602 u32 rx_priv;
1603 int i;
1604
1605 tc_num = hclge_get_tc_num(hdev);
1606 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1607
d221df4e
YL		 1608 if (hnae3_dev_dcb_supported(hdev))
1609 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1610 else
1611 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1612
46a3df9f
S		 1613 shared_buf_tc = pfc_enable_num * hdev->mps +
1614 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1615 hdev->mps;
1616 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1617
acf61ecd 1618 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1619 if (rx_all <= rx_priv + shared_std)
1620 return false;
1621
1622 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1623 buf_alloc->s_buf.buf_size = shared_buf;
1624 buf_alloc->s_buf.self.high = shared_buf;
1625 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1626
1627 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1628 if ((hdev->hw_tc_map & BIT(i)) &&
1629 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1630 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1631 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1632 } else {
acf61ecd
YL		 1633 buf_alloc->s_buf.tc_thrd[i].low = 0;
1634 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1635 }
1636 }
1637
1638 return true;
1639}
1640
acf61ecd
YL		 1641static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1642 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1643{
1644 u32 i, total_size;
1645
1646 total_size = hdev->pkt_buf_size;
1647
1648 /* alloc tx buffer for all enabled tc */
1649 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1650 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1651
1652 if (total_size < HCLGE_DEFAULT_TX_BUF)
1653 return -ENOMEM;
1654
1655 if (hdev->hw_tc_map & BIT(i))
1656 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1657 else
1658 priv->tx_buf_size = 0;
1659
1660 total_size -= priv->tx_buf_size;
1661 }
1662
1663 return 0;
1664}
1665
46a3df9f
S		 1666/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1667 * @hdev: pointer to struct hclge_dev
acf61ecd 1668 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1669 * @return: 0: calculate sucessful, negative: fail
1670 */
1db9b1bf
YL		 1671static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1672 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1673{
9ffe79a9 1674 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1675 int no_pfc_priv_num, pfc_priv_num;
1676 struct hclge_priv_buf *priv;
1677 int i;
1678
acf61ecd 1679 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1680
d602a525
YL		 1681 /* When DCB is not supported, rx private
1682 * buffer is not allocated.
1683 */
1684 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1685 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1686 return -ENOMEM;
1687
1688 return 0;
1689 }
1690
46a3df9f
S		 1691 /* step 1, try to alloc private buffer for all enabled tc */
1692 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1693 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1694 if (hdev->hw_tc_map & BIT(i)) {
1695 priv->enable = 1;
1696 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1697 priv->wl.low = hdev->mps;
1698 priv->wl.high = priv->wl.low + hdev->mps;
1699 priv->buf_size = priv->wl.high +
1700 HCLGE_DEFAULT_DV;
1701 } else {
1702 priv->wl.low = 0;
1703 priv->wl.high = 2 * hdev->mps;
1704 priv->buf_size = priv->wl.high;
1705 }
bb1fe9ea
YL		 1706 } else {
1707 priv->enable = 0;
1708 priv->wl.low = 0;
1709 priv->wl.high = 0;
1710 priv->buf_size = 0;
46a3df9f
S		 1711 }
1712 }
1713
acf61ecd 1714 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1715 return 0;
1716
1717 /* step 2, try to decrease the buffer size of
1718 * no pfc TC's private buffer
1719 */
1720 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1721 priv = &buf_alloc->priv_buf[i];
46a3df9f 1722
bb1fe9ea
YL		 1723 priv->enable = 0;
1724 priv->wl.low = 0;
1725 priv->wl.high = 0;
1726 priv->buf_size = 0;
1727
1728 if (!(hdev->hw_tc_map & BIT(i)))
1729 continue;
1730
1731 priv->enable = 1;
46a3df9f
S		 1732
1733 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1734 priv->wl.low = 128;
1735 priv->wl.high = priv->wl.low + hdev->mps;
1736 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1737 } else {
1738 priv->wl.low = 0;
1739 priv->wl.high = hdev->mps;
1740 priv->buf_size = priv->wl.high;
1741 }
1742 }
1743
acf61ecd 1744 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1745 return 0;
1746
1747 /* step 3, try to reduce the number of pfc disabled TCs,
1748 * which have private buffer
1749 */
1750 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1751 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1752
1753 /* let the last to be cleared first */
1754 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1755 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1756
1757 if (hdev->hw_tc_map & BIT(i) &&
1758 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1759 /* Clear the no pfc TC private buffer */
1760 priv->wl.low = 0;
1761 priv->wl.high = 0;
1762 priv->buf_size = 0;
1763 priv->enable = 0;
1764 no_pfc_priv_num--;
1765 }
1766
acf61ecd 1767 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1768 no_pfc_priv_num == 0)
1769 break;
1770 }
1771
acf61ecd 1772 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1773 return 0;
1774
1775 /* step 4, try to reduce the number of pfc enabled TCs
1776 * which have private buffer.
1777 */
acf61ecd 1778 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1779
1780 /* let the last to be cleared first */
1781 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1782 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1783
1784 if (hdev->hw_tc_map & BIT(i) &&
1785 hdev->tm_info.hw_pfc_map & BIT(i)) {
1786 /* Reduce the number of pfc TC with private buffer */
1787 priv->wl.low = 0;
1788 priv->enable = 0;
1789 priv->wl.high = 0;
1790 priv->buf_size = 0;
1791 pfc_priv_num--;
1792 }
1793
acf61ecd 1794 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1795 pfc_priv_num == 0)
1796 break;
1797 }
acf61ecd 1798 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1799 return 0;
1800
1801 return -ENOMEM;
1802}
1803
acf61ecd
YL		 1804static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1805 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1806{
d44f9b63 1807 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1808 struct hclge_desc desc;
1809 int ret;
1810 int i;
1811
1812 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1813 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1814
1815 /* Alloc private buffer TCs */
1816 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1817 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1818
1819 req->buf_num[i] =
1820 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1821 req->buf_num[i] |=
5bca3b94 1822 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1823 }
1824
b8c8bf47 1825 req->shared_buf =
acf61ecd 1826 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1827 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1828
46a3df9f
S		 1829 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1830 if (ret) {
1831 dev_err(&hdev->pdev->dev,
1832 "rx private buffer alloc cmd failed %d\n", ret);
1833 return ret;
1834 }
1835
1836 return 0;
1837}
1838
1839#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1840
acf61ecd
YL		 1841static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1842 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1843{
1844 struct hclge_rx_priv_wl_buf *req;
1845 struct hclge_priv_buf *priv;
1846 struct hclge_desc desc[2];
1847 int i, j;
1848 int ret;
1849
1850 for (i = 0; i < 2; i++) {
1851 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1852 false);
1853 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1854
1855 /* The first descriptor set the NEXT bit to 1 */
1856 if (i == 0)
1857 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1858 else
1859 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1860
1861 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1862 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1863
1864 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1865 req->tc_wl[j].high =
1866 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1867 req->tc_wl[j].high |=
1868 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1869 HCLGE_RX_PRIV_EN_B);
1870 req->tc_wl[j].low =
1871 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1872 req->tc_wl[j].low |=
1873 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1874 HCLGE_RX_PRIV_EN_B);
1875 }
1876 }
1877
1878 /* Send 2 descriptor at one time */
1879 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1880 if (ret) {
1881 dev_err(&hdev->pdev->dev,
1882 "rx private waterline config cmd failed %d\n",
1883 ret);
1884 return ret;
1885 }
1886 return 0;
1887}
1888
acf61ecd
YL		 1889static int hclge_common_thrd_config(struct hclge_dev *hdev,
1890 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1891{
acf61ecd 1892 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1893 struct hclge_rx_com_thrd *req;
1894 struct hclge_desc desc[2];
1895 struct hclge_tc_thrd *tc;
1896 int i, j;
1897 int ret;
1898
1899 for (i = 0; i < 2; i++) {
1900 hclge_cmd_setup_basic_desc(&desc[i],
1901 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1902 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1903
1904 /* The first descriptor set the NEXT bit to 1 */
1905 if (i == 0)
1906 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1907 else
1908 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1909
1910 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1911 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1912
1913 req->com_thrd[j].high =
1914 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1915 req->com_thrd[j].high |=
1916 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1917 HCLGE_RX_PRIV_EN_B);
1918 req->com_thrd[j].low =
1919 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1920 req->com_thrd[j].low |=
1921 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1922 HCLGE_RX_PRIV_EN_B);
1923 }
1924 }
1925
1926 /* Send 2 descriptors at one time */
1927 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1928 if (ret) {
1929 dev_err(&hdev->pdev->dev,
1930 "common threshold config cmd failed %d\n", ret);
1931 return ret;
1932 }
1933 return 0;
1934}
1935
acf61ecd
YL		 1936static int hclge_common_wl_config(struct hclge_dev *hdev,
1937 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1938{
acf61ecd 1939 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1940 struct hclge_rx_com_wl *req;
1941 struct hclge_desc desc;
1942 int ret;
1943
1944 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1945
1946 req = (struct hclge_rx_com_wl *)desc.data;
1947 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1948 req->com_wl.high |=
1949 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1950 HCLGE_RX_PRIV_EN_B);
1951
1952 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1953 req->com_wl.low |=
1954 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1955 HCLGE_RX_PRIV_EN_B);
1956
1957 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1958 if (ret) {
1959 dev_err(&hdev->pdev->dev,
1960 "common waterline config cmd failed %d\n", ret);
1961 return ret;
1962 }
1963
1964 return 0;
1965}
1966
1967int hclge_buffer_alloc(struct hclge_dev *hdev)
1968{
acf61ecd 1969 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1970 int ret;
1971
acf61ecd
YL		 1972 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1973 if (!pkt_buf)
46a3df9f
S		 1974 return -ENOMEM;
1975
acf61ecd 1976 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1977 if (ret) {
1978 dev_err(&hdev->pdev->dev,
1979 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1980 goto out;
9ffe79a9
YL		 1981 }
1982
acf61ecd 1983 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1984 if (ret) {
1985 dev_err(&hdev->pdev->dev,
1986 "could not alloc tx buffers %d\n", ret);
acf61ecd 1987 goto out;
46a3df9f
S		 1988 }
1989
acf61ecd 1990 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1991 if (ret) {
1992 dev_err(&hdev->pdev->dev,
1993 "could not calc rx priv buffer size for all TCs %d\n",
1994 ret);
acf61ecd 1995 goto out;
46a3df9f
S		 1996 }
1997
acf61ecd 1998 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1999 if (ret) {
2000 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
2001 ret);
acf61ecd 2002 goto out;
46a3df9f
S		 2003 }
2004
2daf4a65 2005 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 2006 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 2007 if (ret) {
2008 dev_err(&hdev->pdev->dev,
2009 "could not configure rx private waterline %d\n",
2010 ret);
acf61ecd 2011 goto out;
2daf4a65 2012 }
46a3df9f 2013
acf61ecd 2014 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 2015 if (ret) {
2016 dev_err(&hdev->pdev->dev,
2017 "could not configure common threshold %d\n",
2018 ret);
acf61ecd 2019 goto out;
2daf4a65 2020 }
46a3df9f
S		 2021 }
2022
acf61ecd
YL		 2023 ret = hclge_common_wl_config(hdev, pkt_buf);
2024 if (ret)
46a3df9f
S		 2025 dev_err(&hdev->pdev->dev,
2026 "could not configure common waterline %d\n", ret);
46a3df9f 2027
acf61ecd
YL		 2028out:
2029 kfree(pkt_buf);
2030 return ret;
46a3df9f
S		 2031}
2032
2033static int hclge_init_roce_base_info(struct hclge_vport *vport)
2034{
2035 struct hnae3_handle *roce = &vport->roce;
2036 struct hnae3_handle *nic = &vport->nic;
2037
887c3820 2038 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 2039
2040 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2041 vport->back->num_msi_left == 0)
2042 return -EINVAL;
2043
2044 roce->rinfo.base_vector = vport->back->roce_base_vector;
2045
2046 roce->rinfo.netdev = nic->kinfo.netdev;
2047 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2048
2049 roce->pdev = nic->pdev;
2050 roce->ae_algo = nic->ae_algo;
2051 roce->numa_node_mask = nic->numa_node_mask;
2052
2053 return 0;
2054}
2055
887c3820 2056static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 2057{
2058 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 2059 int vectors;
2060 int i;
46a3df9f 2061
887c3820
SM		 2062 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2063 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2064 if (vectors < 0) {
2065 dev_err(&pdev->dev,
2066 "failed(%d) to allocate MSI/MSI-X vectors\n",
2067 vectors);
2068 return vectors;
46a3df9f 2069 }
887c3820
SM		 2070 if (vectors < hdev->num_msi)
2071 dev_warn(&hdev->pdev->dev,
2072 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2073 hdev->num_msi, vectors);
46a3df9f 2074
887c3820
SM		 2075 hdev->num_msi = vectors;
2076 hdev->num_msi_left = vectors;
2077 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 2078 hdev->roce_base_vector = hdev->base_msi_vector +
2079 HCLGE_ROCE_VECTOR_OFFSET;
2080
46a3df9f
S		 2081 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2082 sizeof(u16), GFP_KERNEL);
887c3820
SM		 2083 if (!hdev->vector_status) {
2084 pci_free_irq_vectors(pdev);
46a3df9f 2085 return -ENOMEM;
887c3820 2086 }
46a3df9f
S		 2087
2088 for (i = 0; i < hdev->num_msi; i++)
2089 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2090
887c3820
SM		 2091 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2092 sizeof(int), GFP_KERNEL);
2093 if (!hdev->vector_irq) {
2094 pci_free_irq_vectors(pdev);
2095 return -ENOMEM;
46a3df9f 2096 }
46a3df9f
S		 2097
2098 return 0;
2099}
2100
2101static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2102{
2103 struct hclge_mac *mac = &hdev->hw.mac;
2104
2105 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2106 mac->duplex = (u8)duplex;
2107 else
2108 mac->duplex = HCLGE_MAC_FULL;
2109
2110 mac->speed = speed;
2111}
2112
2113int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2114{
d44f9b63 2115 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2116 struct hclge_desc desc;
2117 int ret;
2118
d44f9b63 2119 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2120
2121 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2122
2123 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2124
2125 switch (speed) {
2126 case HCLGE_MAC_SPEED_10M:
2127 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2128 HCLGE_CFG_SPEED_S, 6);
2129 break;
2130 case HCLGE_MAC_SPEED_100M:
2131 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2132 HCLGE_CFG_SPEED_S, 7);
2133 break;
2134 case HCLGE_MAC_SPEED_1G:
2135 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2136 HCLGE_CFG_SPEED_S, 0);
2137 break;
2138 case HCLGE_MAC_SPEED_10G:
2139 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2140 HCLGE_CFG_SPEED_S, 1);
2141 break;
2142 case HCLGE_MAC_SPEED_25G:
2143 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2144 HCLGE_CFG_SPEED_S, 2);
2145 break;
2146 case HCLGE_MAC_SPEED_40G:
2147 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2148 HCLGE_CFG_SPEED_S, 3);
2149 break;
2150 case HCLGE_MAC_SPEED_50G:
2151 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2152 HCLGE_CFG_SPEED_S, 4);
2153 break;
2154 case HCLGE_MAC_SPEED_100G:
2155 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2156 HCLGE_CFG_SPEED_S, 5);
2157 break;
2158 default:
d7629e74 2159 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2160 return -EINVAL;
2161 }
2162
2163 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2164 1);
2165
2166 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2167 if (ret) {
2168 dev_err(&hdev->pdev->dev,
2169 "mac speed/duplex config cmd failed %d.\n", ret);
2170 return ret;
2171 }
2172
2173 hclge_check_speed_dup(hdev, duplex, speed);
2174
2175 return 0;
2176}
2177
2178static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2179 u8 duplex)
2180{
2181 struct hclge_vport *vport = hclge_get_vport(handle);
2182 struct hclge_dev *hdev = vport->back;
2183
2184 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2185}
2186
2187static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2188 u8 *duplex)
2189{
d44f9b63 2190 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2191 struct hclge_desc desc;
2192 int speed_tmp;
2193 int ret;
2194
d44f9b63 2195 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2196
2197 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2198 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2199 if (ret) {
2200 dev_err(&hdev->pdev->dev,
2201 "mac speed/autoneg/duplex query cmd failed %d\n",
2202 ret);
2203 return ret;
2204 }
2205
2206 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2207 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2208 HCLGE_QUERY_SPEED_S);
2209
2210 ret = hclge_parse_speed(speed_tmp, speed);
2211 if (ret) {
2212 dev_err(&hdev->pdev->dev,
2213 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2214 return -EIO;
2215 }
2216
2217 return 0;
2218}
2219
46a3df9f
S		 2220static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2221{
d44f9b63 2222 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2223 struct hclge_desc desc;
a90bb9a5 2224 u32 flag = 0;
46a3df9f
S		 2225 int ret;
2226
2227 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2228
d44f9b63 2229 req = (struct hclge_config_auto_neg_cmd *)desc.data;
a90bb9a5
YL		 2230 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2231 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2232
2233 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2234 if (ret) {
2235 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2236 ret);
2237 return ret;
2238 }
2239
2240 return 0;
2241}
2242
2243static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2244{
2245 struct hclge_vport *vport = hclge_get_vport(handle);
2246 struct hclge_dev *hdev = vport->back;
2247
2248 return hclge_set_autoneg_en(hdev, enable);
2249}
2250
2251static int hclge_get_autoneg(struct hnae3_handle *handle)
2252{
2253 struct hclge_vport *vport = hclge_get_vport(handle);
2254 struct hclge_dev *hdev = vport->back;
9ff804ee
FL		 2255 struct phy_device *phydev = hdev->hw.mac.phydev;
2256
2257 if (phydev)
2258 return phydev->autoneg;
46a3df9f
S		 2259
2260 return hdev->hw.mac.autoneg;
2261}
2262
6f712727
PL		 2263static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2264 bool mask_vlan,
2265 u8 *mac_mask)
2266{
2267 struct hclge_mac_vlan_mask_entry_cmd *req;
2268 struct hclge_desc desc;
2269 int status;
2270
2271 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2272 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2273
2274 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2275 mask_vlan ? 1 : 0);
2276 ether_addr_copy(req->mac_mask, mac_mask);
2277
2278 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2279 if (status)
2280 dev_err(&hdev->pdev->dev,
2281 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2282 status);
2283
2284 return status;
2285}
2286
46a3df9f
S		 2287static int hclge_mac_init(struct hclge_dev *hdev)
2288{
59bc85ec
FL		 2289 struct hnae3_handle *handle = &hdev->vport[0].nic;
2290 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 2291 struct hclge_mac *mac = &hdev->hw.mac;
6f712727 2292 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
59bc85ec 2293 int mtu;
46a3df9f
S		 2294 int ret;
2295
2296 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2297 if (ret) {
2298 dev_err(&hdev->pdev->dev,
2299 "Config mac speed dup fail ret=%d\n", ret);
2300 return ret;
2301 }
2302
2303 mac->link = 0;
2304
46a3df9f
S		 2305 /* Initialize the MTA table work mode */
2306 hdev->accept_mta_mc = true;
2307 hdev->enable_mta = true;
2308 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2309
2310 ret = hclge_set_mta_filter_mode(hdev,
2311 hdev->mta_mac_sel_type,
2312 hdev->enable_mta);
2313 if (ret) {
2314 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2315 ret);
2316 return ret;
2317 }
2318
6f712727
PL		 2319 ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2320 if (ret) {
2321 dev_err(&hdev->pdev->dev,
2322 "set mta filter mode fail ret=%d\n", ret);
2323 return ret;
2324 }
2325
2326 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
59bc85ec 2327 if (ret) {
6f712727
PL		 2328 dev_err(&hdev->pdev->dev,
2329 "set default mac_vlan_mask fail ret=%d\n", ret);
59bc85ec
FL		 2330 return ret;
2331 }
6f712727 2332
59bc85ec
FL		 2333 if (netdev)
2334 mtu = netdev->mtu;
2335 else
2336 mtu = ETH_DATA_LEN;
2337
2338 ret = hclge_set_mtu(handle, mtu);
2339 if (ret) {
2340 dev_err(&hdev->pdev->dev,
2341 "set mtu failed ret=%d\n", ret);
2342 return ret;
2343 }
2344
2345 return 0;
46a3df9f
S		 2346}
2347
22fd3468
SM		 2348static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2349{
2350 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2351 schedule_work(&hdev->mbx_service_task);
2352}
2353
ed4a1bb8
SM		 2354static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2355{
2356 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2357 schedule_work(&hdev->rst_service_task);
2358}
2359
46a3df9f
S		 2360static void hclge_task_schedule(struct hclge_dev *hdev)
2361{
2362 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2363 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2364 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2365 (void)schedule_work(&hdev->service_task);
2366}
2367
2368static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2369{
d44f9b63 2370 struct hclge_link_status_cmd *req;
46a3df9f
S		 2371 struct hclge_desc desc;
2372 int link_status;
2373 int ret;
2374
2375 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2376 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2377 if (ret) {
2378 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2379 ret);
2380 return ret;
2381 }
2382
d44f9b63 2383 req = (struct hclge_link_status_cmd *)desc.data;
46a3df9f
S		 2384 link_status = req->status & HCLGE_LINK_STATUS;
2385
2386 return !!link_status;
2387}
2388
2389static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2390{
2391 int mac_state;
2392 int link_stat;
2393
2394 mac_state = hclge_get_mac_link_status(hdev);
2395
2396 if (hdev->hw.mac.phydev) {
2397 if (!genphy_read_status(hdev->hw.mac.phydev))
2398 link_stat = mac_state &
2399 hdev->hw.mac.phydev->link;
2400 else
2401 link_stat = 0;
2402
2403 } else {
2404 link_stat = mac_state;
2405 }
2406
2407 return !!link_stat;
2408}
2409
2410static void hclge_update_link_status(struct hclge_dev *hdev)
2411{
2412 struct hnae3_client *client = hdev->nic_client;
2413 struct hnae3_handle *handle;
2414 int state;
2415 int i;
2416
2417 if (!client)
2418 return;
2419 state = hclge_get_mac_phy_link(hdev);
2420 if (state != hdev->hw.mac.link) {
2421 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2422 handle = &hdev->vport[i].nic;
2423 client->ops->link_status_change(handle, state);
2424 }
2425 hdev->hw.mac.link = state;
2426 }
2427}
2428
2429static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2430{
2431 struct hclge_mac mac = hdev->hw.mac;
2432 u8 duplex;
2433 int speed;
2434 int ret;
2435
2436 /* get the speed and duplex as autoneg'result from mac cmd when phy
2437 * doesn't exit.
2438 */
c040366b 2439 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2440 return 0;
2441
2442 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2443 if (ret) {
2444 dev_err(&hdev->pdev->dev,
2445 "mac autoneg/speed/duplex query failed %d\n", ret);
2446 return ret;
2447 }
2448
2449 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2450 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2451 if (ret) {
2452 dev_err(&hdev->pdev->dev,
2453 "mac speed/duplex config failed %d\n", ret);
2454 return ret;
2455 }
2456 }
2457
2458 return 0;
2459}
2460
2461static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2462{
2463 struct hclge_vport *vport = hclge_get_vport(handle);
2464 struct hclge_dev *hdev = vport->back;
2465
2466 return hclge_update_speed_duplex(hdev);
2467}
2468
2469static int hclge_get_status(struct hnae3_handle *handle)
2470{
2471 struct hclge_vport *vport = hclge_get_vport(handle);
2472 struct hclge_dev *hdev = vport->back;
2473
2474 hclge_update_link_status(hdev);
2475
2476 return hdev->hw.mac.link;
2477}
2478
d039ef68 2479static void hclge_service_timer(struct timer_list *t)
46a3df9f 2480{
d039ef68 2481 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2482
d039ef68 2483 mod_timer(&hdev->service_timer, jiffies + HZ);
7a5d2a39 2484 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2485 hclge_task_schedule(hdev);
2486}
2487
2488static void hclge_service_complete(struct hclge_dev *hdev)
2489{
2490 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2491
2492 /* Flush memory before next watchdog */
2493 smp_mb__before_atomic();
2494 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2495}
2496
202f2014
SM		 2497static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2498{
2499 u32 rst_src_reg;
22fd3468 2500 u32 cmdq_src_reg;
202f2014
SM		 2501
2502 /* fetch the events from their corresponding regs */
2503 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
22fd3468
SM		 2504 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2505
2506 /* Assumption: If by any chance reset and mailbox events are reported
2507 * together then we will only process reset event in this go and will
2508 * defer the processing of the mailbox events. Since, we would have not
2509 * cleared RX CMDQ event this time we would receive again another
2510 * interrupt from H/W just for the mailbox.
2511 */
202f2014
SM		 2512
2513 /* check for vector0 reset event sources */
2514 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2515 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2516 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2517 return HCLGE_VECTOR0_EVENT_RST;
2518 }
2519
2520 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2521 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2522 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2523 return HCLGE_VECTOR0_EVENT_RST;
2524 }
2525
2526 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2527 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2528 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2529 return HCLGE_VECTOR0_EVENT_RST;
2530 }
2531
22fd3468
SM		 2532 /* check for vector0 mailbox(=CMDQ RX) event source */
2533 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2534 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2535 *clearval = cmdq_src_reg;
2536 return HCLGE_VECTOR0_EVENT_MBX;
2537 }
202f2014
SM		 2538
2539 return HCLGE_VECTOR0_EVENT_OTHER;
2540}
2541
2542static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2543 u32 regclr)
2544{
22fd3468
SM		 2545 switch (event_type) {
2546 case HCLGE_VECTOR0_EVENT_RST:
202f2014 2547 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
22fd3468
SM		 2548 break;
2549 case HCLGE_VECTOR0_EVENT_MBX:
2550 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2551 break;
2552 }
202f2014
SM		 2553}
2554
466b0c00
L		 2555static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2556{
2557 writel(enable ? 1 : 0, vector->addr);
2558}
2559
2560static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2561{
2562 struct hclge_dev *hdev = data;
202f2014
SM		 2563 u32 event_cause;
2564 u32 clearval;
466b0c00
L		 2565
2566 hclge_enable_vector(&hdev->misc_vector, false);
202f2014
SM		 2567 event_cause = hclge_check_event_cause(hdev, &clearval);
2568
22fd3468 2569 /* vector 0 interrupt is shared with reset and mailbox source events.*/
202f2014
SM		 2570 switch (event_cause) {
2571 case HCLGE_VECTOR0_EVENT_RST:
ed4a1bb8 2572 hclge_reset_task_schedule(hdev);
202f2014 2573 break;
22fd3468
SM		 2574 case HCLGE_VECTOR0_EVENT_MBX:
2575 /* If we are here then,
2576 * 1. Either we are not handling any mbx task and we are not
2577 * scheduled as well
2578 * OR
2579 * 2. We could be handling a mbx task but nothing more is
2580 * scheduled.
2581 * In both cases, we should schedule mbx task as there are more
2582 * mbx messages reported by this interrupt.
2583 */
2584 hclge_mbx_task_schedule(hdev);
2585
202f2014
SM		 2586 default:
2587 dev_dbg(&hdev->pdev->dev,
2588 "received unknown or unhandled event of vector0\n");
2589 break;
2590 }
2591
2592 /* we should clear the source of interrupt */
2593 hclge_clear_event_cause(hdev, event_cause, clearval);
2594 hclge_enable_vector(&hdev->misc_vector, true);
466b0c00
L		 2595
2596 return IRQ_HANDLED;
2597}
2598
2599static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2600{
2601 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2602 hdev->num_msi_left += 1;
2603 hdev->num_msi_used -= 1;
2604}
2605
2606static void hclge_get_misc_vector(struct hclge_dev *hdev)
2607{
2608 struct hclge_misc_vector *vector = &hdev->misc_vector;
2609
2610 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2611
2612 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2613 hdev->vector_status[0] = 0;
2614
2615 hdev->num_msi_left -= 1;
2616 hdev->num_msi_used += 1;
2617}
2618
2619static int hclge_misc_irq_init(struct hclge_dev *hdev)
2620{
2621 int ret;
2622
2623 hclge_get_misc_vector(hdev);
2624
202f2014
SM		 2625 /* this would be explicitly freed in the end */
2626 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2627 0, "hclge_misc", hdev);
466b0c00
L		 2628 if (ret) {
2629 hclge_free_vector(hdev, 0);
2630 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2631 hdev->misc_vector.vector_irq);
2632 }
2633
2634 return ret;
2635}
2636
202f2014
SM		 2637static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2638{
2639 free_irq(hdev->misc_vector.vector_irq, hdev);
2640 hclge_free_vector(hdev, 0);
2641}
2642
4ed340ab
L		 2643static int hclge_notify_client(struct hclge_dev *hdev,
2644 enum hnae3_reset_notify_type type)
2645{
2646 struct hnae3_client *client = hdev->nic_client;
2647 u16 i;
2648
2649 if (!client->ops->reset_notify)
2650 return -EOPNOTSUPP;
2651
2652 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2653 struct hnae3_handle *handle = &hdev->vport[i].nic;
2654 int ret;
2655
2656 ret = client->ops->reset_notify(handle, type);
2657 if (ret)
2658 return ret;
2659 }
2660
2661 return 0;
2662}
2663
2664static int hclge_reset_wait(struct hclge_dev *hdev)
2665{
2666#define HCLGE_RESET_WATI_MS 100
2667#define HCLGE_RESET_WAIT_CNT 5
2668 u32 val, reg, reg_bit;
2669 u32 cnt = 0;
2670
2671 switch (hdev->reset_type) {
2672 case HNAE3_GLOBAL_RESET:
2673 reg = HCLGE_GLOBAL_RESET_REG;
2674 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2675 break;
2676 case HNAE3_CORE_RESET:
2677 reg = HCLGE_GLOBAL_RESET_REG;
2678 reg_bit = HCLGE_CORE_RESET_BIT;
2679 break;
2680 case HNAE3_FUNC_RESET:
2681 reg = HCLGE_FUN_RST_ING;
2682 reg_bit = HCLGE_FUN_RST_ING_B;
2683 break;
2684 default:
2685 dev_err(&hdev->pdev->dev,
2686 "Wait for unsupported reset type: %d\n",
2687 hdev->reset_type);
2688 return -EINVAL;
2689 }
2690
2691 val = hclge_read_dev(&hdev->hw, reg);
2692 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2693 msleep(HCLGE_RESET_WATI_MS);
2694 val = hclge_read_dev(&hdev->hw, reg);
2695 cnt++;
2696 }
2697
4ed340ab
L		 2698 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2699 dev_warn(&hdev->pdev->dev,
2700 "Wait for reset timeout: %d\n", hdev->reset_type);
2701 return -EBUSY;
2702 }
2703
2704 return 0;
2705}
2706
2707static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2708{
2709 struct hclge_desc desc;
2710 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2711 int ret;
2712
2713 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2714 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2715 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2716 req->fun_reset_vfid = func_id;
2717
2718 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2719 if (ret)
2720 dev_err(&hdev->pdev->dev,
2721 "send function reset cmd fail, status =%d\n", ret);
2722
2723 return ret;
2724}
2725
d5752031 2726static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2727{
2728 struct pci_dev *pdev = hdev->pdev;
2729 u32 val;
2730
d5752031 2731 switch (hdev->reset_type) {
4ed340ab
L		 2732 case HNAE3_GLOBAL_RESET:
2733 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2734 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2735 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2736 dev_info(&pdev->dev, "Global Reset requested\n");
2737 break;
2738 case HNAE3_CORE_RESET:
2739 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2740 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2741 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2742 dev_info(&pdev->dev, "Core Reset requested\n");
2743 break;
2744 case HNAE3_FUNC_RESET:
2745 dev_info(&pdev->dev, "PF Reset requested\n");
2746 hclge_func_reset_cmd(hdev, 0);
ed4a1bb8
SM		 2747 /* schedule again to check later */
2748 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2749 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2750 break;
2751 default:
2752 dev_warn(&pdev->dev,
d5752031 2753 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2754 break;
2755 }
2756}
2757
d5752031
SM		 2758static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2759 unsigned long *addr)
2760{
2761 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2762
2763 /* return the highest priority reset level amongst all */
2764 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2765 rst_level = HNAE3_GLOBAL_RESET;
2766 else if (test_bit(HNAE3_CORE_RESET, addr))
2767 rst_level = HNAE3_CORE_RESET;
2768 else if (test_bit(HNAE3_IMP_RESET, addr))
2769 rst_level = HNAE3_IMP_RESET;
2770 else if (test_bit(HNAE3_FUNC_RESET, addr))
2771 rst_level = HNAE3_FUNC_RESET;
2772
2773 /* now, clear all other resets */
2774 clear_bit(HNAE3_GLOBAL_RESET, addr);
2775 clear_bit(HNAE3_CORE_RESET, addr);
2776 clear_bit(HNAE3_IMP_RESET, addr);
2777 clear_bit(HNAE3_FUNC_RESET, addr);
2778
2779 return rst_level;
2780}
2781
2782static void hclge_reset(struct hclge_dev *hdev)
2783{
2784 /* perform reset of the stack & ae device for a client */
2785
2786 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2787
2788 if (!hclge_reset_wait(hdev)) {
2789 rtnl_lock();
2790 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2791 hclge_reset_ae_dev(hdev->ae_dev);
2792 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2793 rtnl_unlock();
2794 } else {
2795 /* schedule again to check pending resets later */
2796 set_bit(hdev->reset_type, &hdev->reset_pending);
2797 hclge_reset_task_schedule(hdev);
2798 }
2799
2800 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2801}
2802
4ed340ab
L		 2803static void hclge_reset_event(struct hnae3_handle *handle,
2804 enum hnae3_reset_type reset)
2805{
2806 struct hclge_vport *vport = hclge_get_vport(handle);
2807 struct hclge_dev *hdev = vport->back;
2808
2809 dev_info(&hdev->pdev->dev,
2810 "Receive reset event , reset_type is %d", reset);
2811
2812 switch (reset) {
2813 case HNAE3_FUNC_RESET:
2814 case HNAE3_CORE_RESET:
2815 case HNAE3_GLOBAL_RESET:
ed4a1bb8
SM		 2816 /* request reset & schedule reset task */
2817 set_bit(reset, &hdev->reset_request);
2818 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2819 break;
2820 default:
2821 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2822 break;
2823 }
2824}
2825
2826static void hclge_reset_subtask(struct hclge_dev *hdev)
2827{
d5752031
SM		 2828 /* check if there is any ongoing reset in the hardware. This status can
2829 * be checked from reset_pending. If there is then, we need to wait for
2830 * hardware to complete reset.
2831 * a. If we are able to figure out in reasonable time that hardware
2832 * has fully resetted then, we can proceed with driver, client
2833 * reset.
2834 * b. else, we can come back later to check this status so re-sched
2835 * now.
2836 */
2837 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2838 if (hdev->reset_type != HNAE3_NONE_RESET)
2839 hclge_reset(hdev);
4ed340ab 2840
d5752031
SM		 2841 /* check if we got any *new* reset requests to be honored */
2842 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2843 if (hdev->reset_type != HNAE3_NONE_RESET)
2844 hclge_do_reset(hdev);
4ed340ab 2845
4ed340ab
L		 2846 hdev->reset_type = HNAE3_NONE_RESET;
2847}
2848
ed4a1bb8 2849static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2850{
ed4a1bb8
SM		 2851 struct hclge_dev *hdev =
2852 container_of(work, struct hclge_dev, rst_service_task);
2853
2854 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2855 return;
2856
2857 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2858
4ed340ab 2859 hclge_reset_subtask(hdev);
ed4a1bb8
SM		 2860
2861 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2862}
2863
22fd3468
SM		 2864static void hclge_mailbox_service_task(struct work_struct *work)
2865{
2866 struct hclge_dev *hdev =
2867 container_of(work, struct hclge_dev, mbx_service_task);
2868
2869 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2870 return;
2871
2872 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2873
2874 hclge_mbx_handler(hdev);
2875
2876 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2877}
2878
46a3df9f
S		 2879static void hclge_service_task(struct work_struct *work)
2880{
2881 struct hclge_dev *hdev =
2882 container_of(work, struct hclge_dev, service_task);
2883
fe36292f
JS		 2884 /* The total rx/tx packets statstics are wanted to be updated
2885 * per second. Both hclge_update_stats_for_all() and
2886 * hclge_mac_get_traffic_stats() can do it.
2887 */
7a5d2a39
JS		 2888 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2889 hclge_update_stats_for_all(hdev);
2890 hdev->hw_stats.stats_timer = 0;
fe36292f
JS		 2891 } else {
2892 hclge_mac_get_traffic_stats(hdev);
7a5d2a39
JS		 2893 }
2894
46a3df9f
S		 2895 hclge_update_speed_duplex(hdev);
2896 hclge_update_link_status(hdev);
fe36292f 2897 hclge_update_led_status(hdev);
46a3df9f
S		 2898 hclge_service_complete(hdev);
2899}
2900
2901static void hclge_disable_sriov(struct hclge_dev *hdev)
2902{
2a32ca13
AB		 2903 /* If our VFs are assigned we cannot shut down SR-IOV
2904 * without causing issues, so just leave the hardware
2905 * available but disabled
2906 */
2907 if (pci_vfs_assigned(hdev->pdev)) {
2908 dev_warn(&hdev->pdev->dev,
2909 "disabling driver while VFs are assigned\n");
2910 return;
2911 }
46a3df9f 2912
2a32ca13 2913 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2914}
2915
2916struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2917{
2918 /* VF handle has no client */
2919 if (!handle->client)
2920 return container_of(handle, struct hclge_vport, nic);
2921 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2922 return container_of(handle, struct hclge_vport, roce);
2923 else
2924 return container_of(handle, struct hclge_vport, nic);
2925}
2926
2927static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2928 struct hnae3_vector_info *vector_info)
2929{
2930 struct hclge_vport *vport = hclge_get_vport(handle);
2931 struct hnae3_vector_info *vector = vector_info;
2932 struct hclge_dev *hdev = vport->back;
2933 int alloc = 0;
2934 int i, j;
2935
2936 vector_num = min(hdev->num_msi_left, vector_num);
2937
2938 for (j = 0; j < vector_num; j++) {
2939 for (i = 1; i < hdev->num_msi; i++) {
2940 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2941 vector->vector = pci_irq_vector(hdev->pdev, i);
2942 vector->io_addr = hdev->hw.io_base +
2943 HCLGE_VECTOR_REG_BASE +
2944 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2945 vport->vport_id *
2946 HCLGE_VECTOR_VF_OFFSET;
2947 hdev->vector_status[i] = vport->vport_id;
887c3820 2948 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2949
2950 vector++;
2951 alloc++;
2952
2953 break;
2954 }
2955 }
2956 }
2957 hdev->num_msi_left -= alloc;
2958 hdev->num_msi_used += alloc;
2959
2960 return alloc;
2961}
2962
2963static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2964{
2965 int i;
2966
887c3820
SM		 2967 for (i = 0; i < hdev->num_msi; i++)
2968 if (vector == hdev->vector_irq[i])
2969 return i;
2970
46a3df9f
S		 2971 return -EINVAL;
2972}
2973
2974static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2975{
2976 return HCLGE_RSS_KEY_SIZE;
2977}
2978
2979static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2980{
2981 return HCLGE_RSS_IND_TBL_SIZE;
2982}
2983
46a3df9f
S		 2984static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2985 const u8 hfunc, const u8 *key)
2986{
d44f9b63 2987 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2988 struct hclge_desc desc;
2989 int key_offset;
2990 int key_size;
2991 int ret;
2992
d44f9b63 2993 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2994
2995 for (key_offset = 0; key_offset < 3; key_offset++) {
2996 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2997 false);
2998
2999 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3000 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3001
3002 if (key_offset == 2)
3003 key_size =
3004 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3005 else
3006 key_size = HCLGE_RSS_HASH_KEY_NUM;
3007
3008 memcpy(req->hash_key,
3009 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3010
3011 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3012 if (ret) {
3013 dev_err(&hdev->pdev->dev,
3014 "Configure RSS config fail, status = %d\n",
3015 ret);
3016 return ret;
3017 }
3018 }
3019 return 0;
3020}
3021
dcd4ef5e 3022static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3023{
d44f9b63 3024 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3025 struct hclge_desc desc;
3026 int i, j;
3027 int ret;
3028
d44f9b63 3029 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3030
3031 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3032 hclge_cmd_setup_basic_desc
3033 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3034
a90bb9a5
YL		 3035 req->start_table_index =
3036 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3037 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3038
3039 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3040 req->rss_result[j] =
3041 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3042
3043 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3044 if (ret) {
3045 dev_err(&hdev->pdev->dev,
3046 "Configure rss indir table fail,status = %d\n",
3047 ret);
3048 return ret;
3049 }
3050 }
3051 return 0;
3052}
3053
3054static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3055 u16 *tc_size, u16 *tc_offset)
3056{
d44f9b63 3057 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3058 struct hclge_desc desc;
3059 int ret;
3060 int i;
3061
3062 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3063 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3064
3065 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3066 u16 mode = 0;
3067
3068 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3069 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
46a3df9f 3070 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
a90bb9a5 3071 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
46a3df9f 3072 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3073
3074 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3075 }
3076
3077 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3078 if (ret) {
3079 dev_err(&hdev->pdev->dev,
3080 "Configure rss tc mode fail, status = %d\n", ret);
3081 return ret;
3082 }
3083
3084 return 0;
3085}
3086
3087static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3088{
d44f9b63 3089 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3090 struct hclge_desc desc;
3091 int ret;
3092
3093 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3094
d44f9b63 3095 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
46a3df9f
S		 3096 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3097 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3098 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3099 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3100 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3101 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3102 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3103 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3104 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3105 if (ret) {
3106 dev_err(&hdev->pdev->dev,
3107 "Configure rss input fail, status = %d\n", ret);
3108 return ret;
3109 }
3110
3111 return 0;
3112}
3113
3114static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3115 u8 *key, u8 *hfunc)
3116{
3117 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3118 int i;
3119
3120 /* Get hash algorithm */
3121 if (hfunc)
dcd4ef5e 3122 *hfunc = vport->rss_algo;
46a3df9f
S		 3123
3124 /* Get the RSS Key required by the user */
3125 if (key)
3126 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3127
3128 /* Get indirect table */
3129 if (indir)
3130 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3131 indir[i] = vport->rss_indirection_tbl[i];
3132
3133 return 0;
3134}
3135
3136static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3137 const u8 *key, const u8 hfunc)
3138{
3139 struct hclge_vport *vport = hclge_get_vport(handle);
3140 struct hclge_dev *hdev = vport->back;
3141 u8 hash_algo;
3142 int ret, i;
3143
3144 /* Set the RSS Hash Key if specififed by the user */
3145 if (key) {
46a3df9f
S		 3146
3147 if (hfunc == ETH_RSS_HASH_TOP ||
3148 hfunc == ETH_RSS_HASH_NO_CHANGE)
3149 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3150 else
3151 return -EINVAL;
3152 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3153 if (ret)
3154 return ret;
dcd4ef5e
YL		 3155
3156 /* Update the shadow RSS key with user specified qids */
3157 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3158 vport->rss_algo = hash_algo;
46a3df9f
S		 3159 }
3160
3161 /* Update the shadow RSS table with user specified qids */
3162 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3163 vport->rss_indirection_tbl[i] = indir[i];
3164
3165 /* Update the hardware */
dcd4ef5e 3166 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3167}
3168
f7db940a
L		 3169static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3170{
3171 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3172
3173 if (nfc->data & RXH_L4_B_2_3)
3174 hash_sets |= HCLGE_D_PORT_BIT;
3175 else
3176 hash_sets &= ~HCLGE_D_PORT_BIT;
3177
3178 if (nfc->data & RXH_IP_SRC)
3179 hash_sets |= HCLGE_S_IP_BIT;
3180 else
3181 hash_sets &= ~HCLGE_S_IP_BIT;
3182
3183 if (nfc->data & RXH_IP_DST)
3184 hash_sets |= HCLGE_D_IP_BIT;
3185 else
3186 hash_sets &= ~HCLGE_D_IP_BIT;
3187
3188 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3189 hash_sets |= HCLGE_V_TAG_BIT;
3190
3191 return hash_sets;
3192}
3193
3194static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3195 struct ethtool_rxnfc *nfc)
3196{
3197 struct hclge_vport *vport = hclge_get_vport(handle);
3198 struct hclge_dev *hdev = vport->back;
3199 struct hclge_rss_input_tuple_cmd *req;
3200 struct hclge_desc desc;
3201 u8 tuple_sets;
3202 int ret;
3203
3204 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3205 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3206 return -EINVAL;
3207
3208 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3209 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3210 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3211 if (ret) {
3212 dev_err(&hdev->pdev->dev,
3213 "Read rss tuple fail, status = %d\n", ret);
3214 return ret;
3215 }
3216
3217 hclge_cmd_reuse_desc(&desc, false);
3218
3219 tuple_sets = hclge_get_rss_hash_bits(nfc);
3220 switch (nfc->flow_type) {
3221 case TCP_V4_FLOW:
3222 req->ipv4_tcp_en = tuple_sets;
3223 break;
3224 case TCP_V6_FLOW:
3225 req->ipv6_tcp_en = tuple_sets;
3226 break;
3227 case UDP_V4_FLOW:
3228 req->ipv4_udp_en = tuple_sets;
3229 break;
3230 case UDP_V6_FLOW:
3231 req->ipv6_udp_en = tuple_sets;
3232 break;
3233 case SCTP_V4_FLOW:
3234 req->ipv4_sctp_en = tuple_sets;
3235 break;
3236 case SCTP_V6_FLOW:
3237 if ((nfc->data & RXH_L4_B_0_1) ||
3238 (nfc->data & RXH_L4_B_2_3))
3239 return -EINVAL;
3240
3241 req->ipv6_sctp_en = tuple_sets;
3242 break;
3243 case IPV4_FLOW:
3244 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3245 break;
3246 case IPV6_FLOW:
3247 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3248 break;
3249 default:
3250 return -EINVAL;
3251 }
3252
3253 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3254 if (ret)
3255 dev_err(&hdev->pdev->dev,
3256 "Set rss tuple fail, status = %d\n", ret);
3257
3258 return ret;
3259}
3260
07d29954
L		 3261static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3262 struct ethtool_rxnfc *nfc)
3263{
3264 struct hclge_vport *vport = hclge_get_vport(handle);
3265 struct hclge_dev *hdev = vport->back;
3266 struct hclge_rss_input_tuple_cmd *req;
3267 struct hclge_desc desc;
3268 u8 tuple_sets;
3269 int ret;
3270
3271 nfc->data = 0;
3272
3273 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3274 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3275 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3276 if (ret) {
3277 dev_err(&hdev->pdev->dev,
3278 "Read rss tuple fail, status = %d\n", ret);
3279 return ret;
3280 }
3281
3282 switch (nfc->flow_type) {
3283 case TCP_V4_FLOW:
3284 tuple_sets = req->ipv4_tcp_en;
3285 break;
3286 case UDP_V4_FLOW:
3287 tuple_sets = req->ipv4_udp_en;
3288 break;
3289 case TCP_V6_FLOW:
3290 tuple_sets = req->ipv6_tcp_en;
3291 break;
3292 case UDP_V6_FLOW:
3293 tuple_sets = req->ipv6_udp_en;
3294 break;
3295 case SCTP_V4_FLOW:
3296 tuple_sets = req->ipv4_sctp_en;
3297 break;
3298 case SCTP_V6_FLOW:
3299 tuple_sets = req->ipv6_sctp_en;
3300 break;
3301 case IPV4_FLOW:
3302 case IPV6_FLOW:
3303 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3304 break;
3305 default:
3306 return -EINVAL;
3307 }
3308
3309 if (!tuple_sets)
3310 return 0;
3311
3312 if (tuple_sets & HCLGE_D_PORT_BIT)
3313 nfc->data |= RXH_L4_B_2_3;
3314 if (tuple_sets & HCLGE_S_PORT_BIT)
3315 nfc->data |= RXH_L4_B_0_1;
3316 if (tuple_sets & HCLGE_D_IP_BIT)
3317 nfc->data |= RXH_IP_DST;
3318 if (tuple_sets & HCLGE_S_IP_BIT)
3319 nfc->data |= RXH_IP_SRC;
3320
3321 return 0;
3322}
3323
46a3df9f
S		 3324static int hclge_get_tc_size(struct hnae3_handle *handle)
3325{
3326 struct hclge_vport *vport = hclge_get_vport(handle);
3327 struct hclge_dev *hdev = vport->back;
3328
3329 return hdev->rss_size_max;
3330}
3331
77f255c1 3332int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f
S		 3333{
3334 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3335 struct hclge_vport *vport = hdev->vport;
3336 u16 tc_offset[HCLGE_MAX_TC_NUM];
3337 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3338 u16 tc_valid[HCLGE_MAX_TC_NUM];
3339 u16 tc_size[HCLGE_MAX_TC_NUM];
3340 u32 *rss_indir = NULL;
68ece54e 3341 u16 rss_size = 0, roundup_size;
46a3df9f
S		 3342 const u8 *key;
3343 int i, ret, j;
3344
3345 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3346 if (!rss_indir)
3347 return -ENOMEM;
3348
3349 /* Get default RSS key */
3350 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3351
3352 /* Initialize RSS indirect table for each vport */
3353 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3354 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3355 vport[j].rss_indirection_tbl[i] =
68ece54e
YL		 3356 i % vport[j].alloc_rss_size;
3357
3358 /* vport 0 is for PF */
3359 if (j != 0)
3360 continue;
3361
3362 rss_size = vport[j].alloc_rss_size;
46a3df9f
S		 3363 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3364 }
3365 }
3366 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3367 if (ret)
3368 goto err;
3369
3370 key = rss_key;
3371 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3372 if (ret)
3373 goto err;
3374
3375 ret = hclge_set_rss_input_tuple(hdev);
3376 if (ret)
3377 goto err;
3378
68ece54e
YL		 3379 /* Each TC have the same queue size, and tc_size set to hardware is
3380 * the log2 of roundup power of two of rss_size, the acutal queue
3381 * size is limited by indirection table.
3382 */
3383 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3384 dev_err(&hdev->pdev->dev,
3385 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3386 rss_size);
81359617
CJ		 3387 ret = -EINVAL;
3388 goto err;
68ece54e
YL		 3389 }
3390
3391 roundup_size = roundup_pow_of_two(rss_size);
3392 roundup_size = ilog2(roundup_size);
3393
46a3df9f 3394 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3395 tc_valid[i] = 0;
46a3df9f 3396
68ece54e
YL		 3397 if (!(hdev->hw_tc_map & BIT(i)))
3398 continue;
3399
3400 tc_valid[i] = 1;
3401 tc_size[i] = roundup_size;
3402 tc_offset[i] = rss_size * i;
46a3df9f 3403 }
68ece54e 3404
46a3df9f
S		 3405 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3406
3407err:
3408 kfree(rss_indir);
3409
3410 return ret;
3411}
3412
63d7e66f
SM		 3413int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3414 int vector_id, bool en,
3415 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3416{
3417 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3418 struct hnae3_ring_chain_node *node;
3419 struct hclge_desc desc;
63d7e66f
SM		 3420 struct hclge_ctrl_vector_chain_cmd *req
3421 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3422 enum hclge_cmd_status status;
3423 enum hclge_opcode_type op;
3424 u16 tqp_type_and_id;
46a3df9f
S		 3425 int i;
3426
63d7e66f
SM		 3427 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3428 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3429 req->int_vector_id = vector_id;
3430
3431 i = 0;
3432 for (node = ring_chain; node; node = node->next) {
63d7e66f
SM		 3433 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3434 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3435 HCLGE_INT_TYPE_S,
46a3df9f 3436 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
63d7e66f
SM		 3437 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3438 HCLGE_TQP_ID_S, node->tqp_index);
f230c6c5
FL		 3439 hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3440 HCLGE_INT_GL_IDX_S,
3441 hnae_get_field(node->int_gl_idx,
3442 HNAE3_RING_GL_IDX_M,
3443 HNAE3_RING_GL_IDX_S));
63d7e66f 3444 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3445 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3446 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
63d7e66f 3447 req->vfid = vport->vport_id;
46a3df9f 3448
63d7e66f
SM		 3449 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3450 if (status) {
46a3df9f
S		 3451 dev_err(&hdev->pdev->dev,
3452 "Map TQP fail, status is %d.\n",
63d7e66f
SM		 3453 status);
3454 return -EIO;
46a3df9f
S		 3455 }
3456 i = 0;
3457
3458 hclge_cmd_setup_basic_desc(&desc,
63d7e66f 3459 op,
46a3df9f
S		 3460 false);
3461 req->int_vector_id = vector_id;
3462 }
3463 }
3464
3465 if (i > 0) {
3466 req->int_cause_num = i;
63d7e66f
SM		 3467 req->vfid = vport->vport_id;
3468 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3469 if (status) {
46a3df9f 3470 dev_err(&hdev->pdev->dev,
63d7e66f
SM		 3471 "Map TQP fail, status is %d.\n", status);
3472 return -EIO;
46a3df9f
S		 3473 }
3474 }
3475
3476 return 0;
3477}
3478
63d7e66f
SM		 3479static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3480 int vector,
3481 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3482{
3483 struct hclge_vport *vport = hclge_get_vport(handle);
3484 struct hclge_dev *hdev = vport->back;
3485 int vector_id;
3486
3487 vector_id = hclge_get_vector_index(hdev, vector);
3488 if (vector_id < 0) {
3489 dev_err(&hdev->pdev->dev,
63d7e66f 3490 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3491 return vector_id;
3492 }
3493
63d7e66f 3494 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3495}
3496
63d7e66f
SM		 3497static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3498 int vector,
3499 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3500{
3501 struct hclge_vport *vport = hclge_get_vport(handle);
3502 struct hclge_dev *hdev = vport->back;
63d7e66f 3503 int vector_id, ret;
46a3df9f
S		 3504
3505 vector_id = hclge_get_vector_index(hdev, vector);
3506 if (vector_id < 0) {
3507 dev_err(&handle->pdev->dev,
3508 "Get vector index fail. ret =%d\n", vector_id);
3509 return vector_id;
3510 }
3511
63d7e66f
SM		 3512 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3513 if (ret) {
3514 dev_err(&handle->pdev->dev,
3515 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3516 vector_id,
3517 ret);
3518 return ret;
46a3df9f
S		 3519 }
3520
63d7e66f
SM		 3521 /* Free this MSIX or MSI vector */
3522 hclge_free_vector(hdev, vector_id);
46a3df9f
S		 3523
3524 return 0;
3525}
3526
3527int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3528 struct hclge_promisc_param *param)
3529{
d44f9b63 3530 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3531 struct hclge_desc desc;
3532 int ret;
3533
3534 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3535
d44f9b63 3536 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f
S		 3537 req->vf_id = param->vf_id;
3538 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3539
3540 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3541 if (ret) {
3542 dev_err(&hdev->pdev->dev,
3543 "Set promisc mode fail, status is %d.\n", ret);
3544 return ret;
3545 }
3546 return 0;
3547}
3548
3549void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3550 bool en_mc, bool en_bc, int vport_id)
3551{
3552 if (!param)
3553 return;
3554
3555 memset(param, 0, sizeof(struct hclge_promisc_param));
3556 if (en_uc)
3557 param->enable = HCLGE_PROMISC_EN_UC;
3558 if (en_mc)
3559 param->enable |= HCLGE_PROMISC_EN_MC;
3560 if (en_bc)
3561 param->enable |= HCLGE_PROMISC_EN_BC;
3562 param->vf_id = vport_id;
3563}
3564
3565static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3566{
3567 struct hclge_vport *vport = hclge_get_vport(handle);
3568 struct hclge_dev *hdev = vport->back;
3569 struct hclge_promisc_param param;
3570
3571 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3572 hclge_cmd_set_promisc_mode(hdev, &param);
3573}
3574
3575static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3576{
3577 struct hclge_desc desc;
d44f9b63
YL		 3578 struct hclge_config_mac_mode_cmd *req =
3579 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3580 u32 loop_en = 0;
46a3df9f
S		 3581 int ret;
3582
3583 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
a90bb9a5
YL		 3584 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3585 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3586 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3587 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3588 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3589 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3590 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3591 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3592 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3593 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3594 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3595 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3596 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3597 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3598 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3599
3600 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3601 if (ret)
3602 dev_err(&hdev->pdev->dev,
3603 "mac enable fail, ret =%d.\n", ret);
3604}
3605
c39c4d98
YL		 3606static int hclge_set_loopback(struct hnae3_handle *handle,
3607 enum hnae3_loop loop_mode, bool en)
3608{
3609 struct hclge_vport *vport = hclge_get_vport(handle);
3610 struct hclge_config_mac_mode_cmd *req;
3611 struct hclge_dev *hdev = vport->back;
3612 struct hclge_desc desc;
3613 u32 loop_en;
3614 int ret;
3615
3616 switch (loop_mode) {
3617 case HNAE3_MAC_INTER_LOOP_MAC:
3618 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3619 /* 1 Read out the MAC mode config at first */
3620 hclge_cmd_setup_basic_desc(&desc,
3621 HCLGE_OPC_CONFIG_MAC_MODE,
3622 true);
3623 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3624 if (ret) {
3625 dev_err(&hdev->pdev->dev,
3626 "mac loopback get fail, ret =%d.\n",
3627 ret);
3628 return ret;
3629 }
3630
3631 /* 2 Then setup the loopback flag */
3632 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3633 if (en)
3634 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3635 else
3636 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3637
3638 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3639
3640 /* 3 Config mac work mode with loopback flag
3641 * and its original configure parameters
3642 */
3643 hclge_cmd_reuse_desc(&desc, false);
3644 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3645 if (ret)
3646 dev_err(&hdev->pdev->dev,
3647 "mac loopback set fail, ret =%d.\n", ret);
3648 break;
3649 default:
3650 ret = -ENOTSUPP;
3651 dev_err(&hdev->pdev->dev,
3652 "loop_mode %d is not supported\n", loop_mode);
3653 break;
3654 }
3655
3656 return ret;
3657}
3658
46a3df9f
S		 3659static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3660 int stream_id, bool enable)
3661{
3662 struct hclge_desc desc;
d44f9b63
YL		 3663 struct hclge_cfg_com_tqp_queue_cmd *req =
3664 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3665 int ret;
3666
3667 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3668 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3669 req->stream_id = cpu_to_le16(stream_id);
3670 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3671
3672 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3673 if (ret)
3674 dev_err(&hdev->pdev->dev,
3675 "Tqp enable fail, status =%d.\n", ret);
3676 return ret;
3677}
3678
3679static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3680{
3681 struct hclge_vport *vport = hclge_get_vport(handle);
3682 struct hnae3_queue *queue;
3683 struct hclge_tqp *tqp;
3684 int i;
3685
3686 for (i = 0; i < vport->alloc_tqps; i++) {
3687 queue = handle->kinfo.tqp[i];
3688 tqp = container_of(queue, struct hclge_tqp, q);
3689 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3690 }
3691}
3692
3693static int hclge_ae_start(struct hnae3_handle *handle)
3694{
3695 struct hclge_vport *vport = hclge_get_vport(handle);
3696 struct hclge_dev *hdev = vport->back;
e5e89cda 3697 int i, ret;
46a3df9f 3698
e5e89cda
PL		 3699 for (i = 0; i < vport->alloc_tqps; i++)
3700 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3701
46a3df9f
S		 3702 /* mac enable */
3703 hclge_cfg_mac_mode(hdev, true);
3704 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3705 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 3706
3707 ret = hclge_mac_start_phy(hdev);
3708 if (ret)
3709 return ret;
3710
3711 /* reset tqp stats */
3712 hclge_reset_tqp_stats(handle);
3713
3714 return 0;
3715}
3716
3717static void hclge_ae_stop(struct hnae3_handle *handle)
3718{
3719 struct hclge_vport *vport = hclge_get_vport(handle);
3720 struct hclge_dev *hdev = vport->back;
e5e89cda 3721 int i;
46a3df9f 3722
e5e89cda
PL		 3723 for (i = 0; i < vport->alloc_tqps; i++)
3724 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3725
46a3df9f
S		 3726 /* Mac disable */
3727 hclge_cfg_mac_mode(hdev, false);
3728
3729 hclge_mac_stop_phy(hdev);
3730
3731 /* reset tqp stats */
3732 hclge_reset_tqp_stats(handle);
3733}
3734
3735static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3736 u16 cmdq_resp, u8 resp_code,
3737 enum hclge_mac_vlan_tbl_opcode op)
3738{
3739 struct hclge_dev *hdev = vport->back;
3740 int return_status = -EIO;
3741
3742 if (cmdq_resp) {
3743 dev_err(&hdev->pdev->dev,
3744 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3745 cmdq_resp);
3746 return -EIO;
3747 }
3748
3749 if (op == HCLGE_MAC_VLAN_ADD) {
3750 if ((!resp_code) || (resp_code == 1)) {
3751 return_status = 0;
3752 } else if (resp_code == 2) {
3753 return_status = -EIO;
3754 dev_err(&hdev->pdev->dev,
3755 "add mac addr failed for uc_overflow.\n");
3756 } else if (resp_code == 3) {
3757 return_status = -EIO;
3758 dev_err(&hdev->pdev->dev,
3759 "add mac addr failed for mc_overflow.\n");
3760 } else {
3761 dev_err(&hdev->pdev->dev,
3762 "add mac addr failed for undefined, code=%d.\n",
3763 resp_code);
3764 }
3765 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3766 if (!resp_code) {
3767 return_status = 0;
3768 } else if (resp_code == 1) {
3769 return_status = -EIO;
3770 dev_dbg(&hdev->pdev->dev,
3771 "remove mac addr failed for miss.\n");
3772 } else {
3773 dev_err(&hdev->pdev->dev,
3774 "remove mac addr failed for undefined, code=%d.\n",
3775 resp_code);
3776 }
3777 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3778 if (!resp_code) {
3779 return_status = 0;
3780 } else if (resp_code == 1) {
3781 return_status = -EIO;
3782 dev_dbg(&hdev->pdev->dev,
3783 "lookup mac addr failed for miss.\n");
3784 } else {
3785 dev_err(&hdev->pdev->dev,
3786 "lookup mac addr failed for undefined, code=%d.\n",
3787 resp_code);
3788 }
3789 } else {
3790 return_status = -EIO;
3791 dev_err(&hdev->pdev->dev,
3792 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3793 op);
3794 }
3795
3796 return return_status;
3797}
3798
3799static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3800{
3801 int word_num;
3802 int bit_num;
3803
3804 if (vfid > 255 || vfid < 0)
3805 return -EIO;
3806
3807 if (vfid >= 0 && vfid <= 191) {
3808 word_num = vfid / 32;
3809 bit_num = vfid % 32;
3810 if (clr)
a90bb9a5 3811 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3812 else
a90bb9a5 3813 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3814 } else {
3815 word_num = (vfid - 192) / 32;
3816 bit_num = vfid % 32;
3817 if (clr)
a90bb9a5 3818 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3819 else
a90bb9a5 3820 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3821 }
3822
3823 return 0;
3824}
3825
3826static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3827{
3828#define HCLGE_DESC_NUMBER 3
3829#define HCLGE_FUNC_NUMBER_PER_DESC 6
3830 int i, j;
3831
3832 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3833 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3834 if (desc[i].data[j])
3835 return false;
3836
3837 return true;
3838}
3839
d44f9b63 3840static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3841 const u8 *addr)
3842{
3843 const unsigned char *mac_addr = addr;
3844 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3845 (mac_addr[0]) | (mac_addr[1] << 8);
3846 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3847
3848 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3849 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3850}
3851
1db9b1bf
YL		 3852static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3853 const u8 *addr)
46a3df9f
S		 3854{
3855 u16 high_val = addr[1] | (addr[0] << 8);
3856 struct hclge_dev *hdev = vport->back;
3857 u32 rsh = 4 - hdev->mta_mac_sel_type;
3858 u16 ret_val = (high_val >> rsh) & 0xfff;
3859
3860 return ret_val;
3861}
3862
3863static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3864 enum hclge_mta_dmac_sel_type mta_mac_sel,
3865 bool enable)
3866{
d44f9b63 3867 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3868 struct hclge_desc desc;
3869 int ret;
3870
d44f9b63 3871 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3872 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3873
3874 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3875 enable);
3876 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3877 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3878
3879 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3880 if (ret) {
3881 dev_err(&hdev->pdev->dev,
3882 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3883 ret);
3884 return ret;
3885 }
3886
3887 return 0;
3888}
3889
3890int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3891 u8 func_id,
3892 bool enable)
3893{
d44f9b63 3894 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3895 struct hclge_desc desc;
3896 int ret;
3897
d44f9b63 3898 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3899 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3900
3901 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3902 enable);
3903 req->function_id = func_id;
3904
3905 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3906 if (ret) {
3907 dev_err(&hdev->pdev->dev,
3908 "Config func_id enable failed for cmd_send, ret =%d.\n",
3909 ret);
3910 return ret;
3911 }
3912
3913 return 0;
3914}
3915
3916static int hclge_set_mta_table_item(struct hclge_vport *vport,
3917 u16 idx,
3918 bool enable)
3919{
3920 struct hclge_dev *hdev = vport->back;
d44f9b63 3921 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3922 struct hclge_desc desc;
a90bb9a5 3923 u16 item_idx = 0;
46a3df9f
S		 3924 int ret;
3925
d44f9b63 3926 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f
S		 3927 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3928 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3929
a90bb9a5 3930 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
46a3df9f 3931 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3932 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3933
3934 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3935 if (ret) {
3936 dev_err(&hdev->pdev->dev,
3937 "Config mta table item failed for cmd_send, ret =%d.\n",
3938 ret);
3939 return ret;
3940 }
3941
3942 return 0;
3943}
3944
3945static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3946 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3947{
3948 struct hclge_dev *hdev = vport->back;
3949 struct hclge_desc desc;
3950 u8 resp_code;
a90bb9a5 3951 u16 retval;
46a3df9f
S		 3952 int ret;
3953
3954 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3955
d44f9b63 3956 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3957
3958 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3959 if (ret) {
3960 dev_err(&hdev->pdev->dev,
3961 "del mac addr failed for cmd_send, ret =%d.\n",
3962 ret);
3963 return ret;
3964 }
a90bb9a5
YL		 3965 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3966 retval = le16_to_cpu(desc.retval);
46a3df9f 3967
a90bb9a5 3968 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3969 HCLGE_MAC_VLAN_REMOVE);
3970}
3971
3972static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3973 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3974 struct hclge_desc *desc,
3975 bool is_mc)
3976{
3977 struct hclge_dev *hdev = vport->back;
3978 u8 resp_code;
a90bb9a5 3979 u16 retval;
46a3df9f
S		 3980 int ret;
3981
3982 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3983 if (is_mc) {
3984 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3985 memcpy(desc[0].data,
3986 req,
d44f9b63 3987 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3988 hclge_cmd_setup_basic_desc(&desc[1],
3989 HCLGE_OPC_MAC_VLAN_ADD,
3990 true);
3991 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3992 hclge_cmd_setup_basic_desc(&desc[2],
3993 HCLGE_OPC_MAC_VLAN_ADD,
3994 true);
3995 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3996 } else {
3997 memcpy(desc[0].data,
3998 req,
d44f9b63 3999 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4000 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4001 }
4002 if (ret) {
4003 dev_err(&hdev->pdev->dev,
4004 "lookup mac addr failed for cmd_send, ret =%d.\n",
4005 ret);
4006 return ret;
4007 }
a90bb9a5
YL		 4008 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4009 retval = le16_to_cpu(desc[0].retval);
46a3df9f 4010
a90bb9a5 4011 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4012 HCLGE_MAC_VLAN_LKUP);
4013}
4014
4015static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4016 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4017 struct hclge_desc *mc_desc)
4018{
4019 struct hclge_dev *hdev = vport->back;
4020 int cfg_status;
4021 u8 resp_code;
a90bb9a5 4022 u16 retval;
46a3df9f
S		 4023 int ret;
4024
4025 if (!mc_desc) {
4026 struct hclge_desc desc;
4027
4028 hclge_cmd_setup_basic_desc(&desc,
4029 HCLGE_OPC_MAC_VLAN_ADD,
4030 false);
d44f9b63
YL		 4031 memcpy(desc.data, req,
4032 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4033 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 4034 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4035 retval = le16_to_cpu(desc.retval);
4036
4037 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4038 resp_code,
4039 HCLGE_MAC_VLAN_ADD);
4040 } else {
c3b6f755 4041 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 4042 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4043 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 4044 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4045 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 4046 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4047 memcpy(mc_desc[0].data, req,
d44f9b63 4048 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4049 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 4050 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4051 retval = le16_to_cpu(mc_desc[0].retval);
4052
4053 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4054 resp_code,
4055 HCLGE_MAC_VLAN_ADD);
4056 }
4057
4058 if (ret) {
4059 dev_err(&hdev->pdev->dev,
4060 "add mac addr failed for cmd_send, ret =%d.\n",
4061 ret);
4062 return ret;
4063 }
4064
4065 return cfg_status;
4066}
4067
4068static int hclge_add_uc_addr(struct hnae3_handle *handle,
4069 const unsigned char *addr)
4070{
4071 struct hclge_vport *vport = hclge_get_vport(handle);
4072
4073 return hclge_add_uc_addr_common(vport, addr);
4074}
4075
4076int hclge_add_uc_addr_common(struct hclge_vport *vport,
4077 const unsigned char *addr)
4078{
4079 struct hclge_dev *hdev = vport->back;
d44f9b63 4080 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 4081 enum hclge_cmd_status status;
a90bb9a5 4082 u16 egress_port = 0;
46a3df9f
S		 4083
4084 /* mac addr check */
4085 if (is_zero_ether_addr(addr) ||
4086 is_broadcast_ether_addr(addr) ||
4087 is_multicast_ether_addr(addr)) {
4088 dev_err(&hdev->pdev->dev,
4089 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4090 addr,
4091 is_zero_ether_addr(addr),
4092 is_broadcast_ether_addr(addr),
4093 is_multicast_ether_addr(addr));
4094 return -EINVAL;
4095 }
4096
4097 memset(&req, 0, sizeof(req));
4098 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4099 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4100 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4101 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
a90bb9a5
YL		 4102
4103 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4104 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4105 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
46a3df9f 4106 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5 4107 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
46a3df9f 4108 HCLGE_MAC_EPORT_PFID_S, 0);
a90bb9a5
YL		 4109
4110 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4111
4112 hclge_prepare_mac_addr(&req, addr);
4113
4114 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
4115
4116 return status;
4117}
4118
4119static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4120 const unsigned char *addr)
4121{
4122 struct hclge_vport *vport = hclge_get_vport(handle);
4123
4124 return hclge_rm_uc_addr_common(vport, addr);
4125}
4126
4127int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4128 const unsigned char *addr)
4129{
4130 struct hclge_dev *hdev = vport->back;
d44f9b63 4131 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4132 enum hclge_cmd_status status;
4133
4134 /* mac addr check */
4135 if (is_zero_ether_addr(addr) ||
4136 is_broadcast_ether_addr(addr) ||
4137 is_multicast_ether_addr(addr)) {
4138 dev_dbg(&hdev->pdev->dev,
4139 "Remove mac err! invalid mac:%pM.\n",
4140 addr);
4141 return -EINVAL;
4142 }
4143
4144 memset(&req, 0, sizeof(req));
4145 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4146 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4147 hclge_prepare_mac_addr(&req, addr);
4148 status = hclge_remove_mac_vlan_tbl(vport, &req);
4149
4150 return status;
4151}
4152
4153static int hclge_add_mc_addr(struct hnae3_handle *handle,
4154 const unsigned char *addr)
4155{
4156 struct hclge_vport *vport = hclge_get_vport(handle);
4157
4158 return hclge_add_mc_addr_common(vport, addr);
4159}
4160
4161int hclge_add_mc_addr_common(struct hclge_vport *vport,
4162 const unsigned char *addr)
4163{
4164 struct hclge_dev *hdev = vport->back;
d44f9b63 4165 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4166 struct hclge_desc desc[3];
4167 u16 tbl_idx;
4168 int status;
4169
4170 /* mac addr check */
4171 if (!is_multicast_ether_addr(addr)) {
4172 dev_err(&hdev->pdev->dev,
4173 "Add mc mac err! invalid mac:%pM.\n",
4174 addr);
4175 return -EINVAL;
4176 }
4177 memset(&req, 0, sizeof(req));
4178 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4179 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4180 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4181 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4182 hclge_prepare_mac_addr(&req, addr);
4183 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4184 if (!status) {
4185 /* This mac addr exist, update VFID for it */
4186 hclge_update_desc_vfid(desc, vport->vport_id, false);
4187 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4188 } else {
4189 /* This mac addr do not exist, add new entry for it */
4190 memset(desc[0].data, 0, sizeof(desc[0].data));
4191 memset(desc[1].data, 0, sizeof(desc[0].data));
4192 memset(desc[2].data, 0, sizeof(desc[0].data));
4193 hclge_update_desc_vfid(desc, vport->vport_id, false);
4194 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4195 }
4196
4197 /* Set MTA table for this MAC address */
4198 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4199 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4200
4201 return status;
4202}
4203
4204static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4205 const unsigned char *addr)
4206{
4207 struct hclge_vport *vport = hclge_get_vport(handle);
4208
4209 return hclge_rm_mc_addr_common(vport, addr);
4210}
4211
4212int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4213 const unsigned char *addr)
4214{
4215 struct hclge_dev *hdev = vport->back;
d44f9b63 4216 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4217 enum hclge_cmd_status status;
4218 struct hclge_desc desc[3];
4219 u16 tbl_idx;
4220
4221 /* mac addr check */
4222 if (!is_multicast_ether_addr(addr)) {
4223 dev_dbg(&hdev->pdev->dev,
4224 "Remove mc mac err! invalid mac:%pM.\n",
4225 addr);
4226 return -EINVAL;
4227 }
4228
4229 memset(&req, 0, sizeof(req));
4230 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4231 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4232 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4233 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4234 hclge_prepare_mac_addr(&req, addr);
4235 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4236 if (!status) {
4237 /* This mac addr exist, remove this handle's VFID for it */
4238 hclge_update_desc_vfid(desc, vport->vport_id, true);
4239
4240 if (hclge_is_all_function_id_zero(desc))
4241 /* All the vfid is zero, so need to delete this entry */
4242 status = hclge_remove_mac_vlan_tbl(vport, &req);
4243 else
4244 /* Not all the vfid is zero, update the vfid */
4245 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4246
4247 } else {
4248 /* This mac addr do not exist, can't delete it */
4249 dev_err(&hdev->pdev->dev,
d7629e74 4250 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 4251 status);
4252 return -EIO;
4253 }
4254
4255 /* Set MTB table for this MAC address */
4256 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4257 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4258
4259 return status;
4260}
4261
635bfb58
FL		 4262static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4263 u16 cmdq_resp, u8 resp_code)
4264{
4265#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4266#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4267#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4268#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4269
4270 int return_status;
4271
4272 if (cmdq_resp) {
4273 dev_err(&hdev->pdev->dev,
4274 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4275 cmdq_resp);
4276 return -EIO;
4277 }
4278
4279 switch (resp_code) {
4280 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4281 case HCLGE_ETHERTYPE_ALREADY_ADD:
4282 return_status = 0;
4283 break;
4284 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4285 dev_err(&hdev->pdev->dev,
4286 "add mac ethertype failed for manager table overflow.\n");
4287 return_status = -EIO;
4288 break;
4289 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4290 dev_err(&hdev->pdev->dev,
4291 "add mac ethertype failed for key conflict.\n");
4292 return_status = -EIO;
4293 break;
4294 default:
4295 dev_err(&hdev->pdev->dev,
4296 "add mac ethertype failed for undefined, code=%d.\n",
4297 resp_code);
4298 return_status = -EIO;
4299 }
4300
4301 return return_status;
4302}
4303
4304static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4305 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4306{
4307 struct hclge_desc desc;
4308 u8 resp_code;
4309 u16 retval;
4310 int ret;
4311
4312 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4313 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4314
4315 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4316 if (ret) {
4317 dev_err(&hdev->pdev->dev,
4318 "add mac ethertype failed for cmd_send, ret =%d.\n",
4319 ret);
4320 return ret;
4321 }
4322
4323 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4324 retval = le16_to_cpu(desc.retval);
4325
4326 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4327}
4328
4329static int init_mgr_tbl(struct hclge_dev *hdev)
4330{
4331 int ret;
4332 int i;
4333
4334 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4335 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4336 if (ret) {
4337 dev_err(&hdev->pdev->dev,
4338 "add mac ethertype failed, ret =%d.\n",
4339 ret);
4340 return ret;
4341 }
4342 }
4343
4344 return 0;
4345}
4346
46a3df9f
S		 4347static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4348{
4349 struct hclge_vport *vport = hclge_get_vport(handle);
4350 struct hclge_dev *hdev = vport->back;
4351
4352 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4353}
4354
4355static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4356{
4357 const unsigned char *new_addr = (const unsigned char *)p;
4358 struct hclge_vport *vport = hclge_get_vport(handle);
4359 struct hclge_dev *hdev = vport->back;
20a5c4c0 4360 int ret;
46a3df9f
S		 4361
4362 /* mac addr check */
4363 if (is_zero_ether_addr(new_addr) ||
4364 is_broadcast_ether_addr(new_addr) ||
4365 is_multicast_ether_addr(new_addr)) {
4366 dev_err(&hdev->pdev->dev,
4367 "Change uc mac err! invalid mac:%p.\n",
4368 new_addr);
4369 return -EINVAL;
4370 }
4371
20a5c4c0
FL		 4372 ret = hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4373 if (ret)
4374 dev_warn(&hdev->pdev->dev,
4375 "remove old uc mac address fail, ret =%d.\n",
4376 ret);
46a3df9f 4377
20a5c4c0
FL		 4378 ret = hclge_add_uc_addr(handle, new_addr);
4379 if (ret) {
4380 dev_err(&hdev->pdev->dev,
4381 "add uc mac address fail, ret =%d.\n",
4382 ret);
4383
4384 ret = hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr);
4385 if (ret) {
4386 dev_err(&hdev->pdev->dev,
4387 "restore uc mac address fail, ret =%d.\n",
4388 ret);
4389 }
4390
4391 return -EIO;
46a3df9f
S		 4392 }
4393
20a5c4c0
FL		 4394 ret = hclge_mac_pause_addr_cfg(hdev, new_addr);
4395 if (ret) {
4396 dev_err(&hdev->pdev->dev,
4397 "configure mac pause address fail, ret =%d.\n",
4398 ret);
4399 return -EIO;
4400 }
4401
4402 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4403
4404 return 0;
46a3df9f
S		 4405}
4406
4407static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4408 bool filter_en)
4409{
d44f9b63 4410 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4411 struct hclge_desc desc;
4412 int ret;
4413
4414 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4415
d44f9b63 4416 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4417 req->vlan_type = vlan_type;
4418 req->vlan_fe = filter_en;
4419
4420 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4421 if (ret) {
4422 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4423 ret);
4424 return ret;
4425 }
4426
4427 return 0;
4428}
4429
d818396d
JS		 4430#define HCLGE_FILTER_TYPE_VF 0
4431#define HCLGE_FILTER_TYPE_PORT 1
4432
4433static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4434{
4435 struct hclge_vport *vport = hclge_get_vport(handle);
4436 struct hclge_dev *hdev = vport->back;
4437
4438 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4439}
4440
46a3df9f
S		 4441int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4442 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4443{
4444#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4445 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4446 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4447 struct hclge_desc desc[2];
4448 u8 vf_byte_val;
4449 u8 vf_byte_off;
4450 int ret;
4451
4452 hclge_cmd_setup_basic_desc(&desc[0],
4453 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4454 hclge_cmd_setup_basic_desc(&desc[1],
4455 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4456
4457 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4458
4459 vf_byte_off = vfid / 8;
4460 vf_byte_val = 1 << (vfid % 8);
4461
d44f9b63
YL		 4462 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4463 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4464
a90bb9a5 4465 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4466 req0->vlan_cfg = is_kill;
4467
4468 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4469 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4470 else
4471 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4472
4473 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4474 if (ret) {
4475 dev_err(&hdev->pdev->dev,
4476 "Send vf vlan command fail, ret =%d.\n",
4477 ret);
4478 return ret;
4479 }
4480
4481 if (!is_kill) {
4482 if (!req0->resp_code || req0->resp_code == 1)
4483 return 0;
4484
4485 dev_err(&hdev->pdev->dev,
4486 "Add vf vlan filter fail, ret =%d.\n",
4487 req0->resp_code);
4488 } else {
4489 if (!req0->resp_code)
4490 return 0;
4491
4492 dev_err(&hdev->pdev->dev,
4493 "Kill vf vlan filter fail, ret =%d.\n",
4494 req0->resp_code);
4495 }
4496
4497 return -EIO;
4498}
4499
4500static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4501 __be16 proto, u16 vlan_id,
4502 bool is_kill)
4503{
4504 struct hclge_vport *vport = hclge_get_vport(handle);
4505 struct hclge_dev *hdev = vport->back;
d44f9b63 4506 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4507 struct hclge_desc desc;
4508 u8 vlan_offset_byte_val;
4509 u8 vlan_offset_byte;
4510 u8 vlan_offset_160;
4511 int ret;
4512
4513 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4514
4515 vlan_offset_160 = vlan_id / 160;
4516 vlan_offset_byte = (vlan_id % 160) / 8;
4517 vlan_offset_byte_val = 1 << (vlan_id % 8);
4518
d44f9b63 4519 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4520 req->vlan_offset = vlan_offset_160;
4521 req->vlan_cfg = is_kill;
4522 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4523
4524 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4525 if (ret) {
4526 dev_err(&hdev->pdev->dev,
4527 "port vlan command, send fail, ret =%d.\n",
4528 ret);
4529 return ret;
4530 }
4531
4532 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4533 if (ret) {
4534 dev_err(&hdev->pdev->dev,
4535 "Set pf vlan filter config fail, ret =%d.\n",
4536 ret);
4537 return -EIO;
4538 }
4539
4540 return 0;
4541}
4542
4543static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4544 u16 vlan, u8 qos, __be16 proto)
4545{
4546 struct hclge_vport *vport = hclge_get_vport(handle);
4547 struct hclge_dev *hdev = vport->back;
4548
4549 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4550 return -EINVAL;
4551 if (proto != htons(ETH_P_8021Q))
4552 return -EPROTONOSUPPORT;
4553
4554 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4555}
4556
e62f2a6b
PL		 4557static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4558{
4559 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4560 struct hclge_vport_vtag_tx_cfg_cmd *req;
4561 struct hclge_dev *hdev = vport->back;
4562 struct hclge_desc desc;
4563 int status;
4564
4565 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4566
4567 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4568 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4569 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4570 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B,
4571 vcfg->accept_tag ? 1 : 0);
4572 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B,
4573 vcfg->accept_untag ? 1 : 0);
4574 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4575 vcfg->insert_tag1_en ? 1 : 0);
4576 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4577 vcfg->insert_tag2_en ? 1 : 0);
4578 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4579
4580 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4581 req->vf_bitmap[req->vf_offset] =
4582 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4583
4584 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4585 if (status)
4586 dev_err(&hdev->pdev->dev,
4587 "Send port txvlan cfg command fail, ret =%d\n",
4588 status);
4589
4590 return status;
4591}
4592
4593static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4594{
4595 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4596 struct hclge_vport_vtag_rx_cfg_cmd *req;
4597 struct hclge_dev *hdev = vport->back;
4598 struct hclge_desc desc;
4599 int status;
4600
4601 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4602
4603 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4604 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4605 vcfg->strip_tag1_en ? 1 : 0);
4606 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4607 vcfg->strip_tag2_en ? 1 : 0);
4608 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4609 vcfg->vlan1_vlan_prionly ? 1 : 0);
4610 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4611 vcfg->vlan2_vlan_prionly ? 1 : 0);
4612
4613 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4614 req->vf_bitmap[req->vf_offset] =
4615 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4616
4617 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4618 if (status)
4619 dev_err(&hdev->pdev->dev,
4620 "Send port rxvlan cfg command fail, ret =%d\n",
4621 status);
4622
4623 return status;
4624}
4625
4626static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4627{
4628 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4629 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4630 struct hclge_desc desc;
4631 int status;
4632
4633 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4634 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4635 rx_req->ot_fst_vlan_type =
4636 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4637 rx_req->ot_sec_vlan_type =
4638 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4639 rx_req->in_fst_vlan_type =
4640 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4641 rx_req->in_sec_vlan_type =
4642 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4643
4644 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4645 if (status) {
4646 dev_err(&hdev->pdev->dev,
4647 "Send rxvlan protocol type command fail, ret =%d\n",
4648 status);
4649 return status;
4650 }
4651
4652 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4653
4654 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4655 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4656 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4657
4658 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4659 if (status)
4660 dev_err(&hdev->pdev->dev,
4661 "Send txvlan protocol type command fail, ret =%d\n",
4662 status);
4663
4664 return status;
4665}
4666
46a3df9f
S		 4667static int hclge_init_vlan_config(struct hclge_dev *hdev)
4668{
e62f2a6b
PL		 4669#define HCLGE_DEF_VLAN_TYPE 0x8100
4670
5e43aef8 4671 struct hnae3_handle *handle;
e62f2a6b 4672 struct hclge_vport *vport;
46a3df9f 4673 int ret;
e62f2a6b
PL		 4674 int i;
4675
4676 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4677 if (ret)
4678 return ret;
46a3df9f 4679
e62f2a6b 4680 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4681 if (ret)
4682 return ret;
4683
e62f2a6b
PL		 4684 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4685 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4686 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4687 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4688 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4689 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4690
4691 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4692 if (ret)
4693 return ret;
46a3df9f 4694
e62f2a6b
PL		 4695 for (i = 0; i < hdev->num_alloc_vport; i++) {
4696 vport = &hdev->vport[i];
4697 vport->txvlan_cfg.accept_tag = true;
4698 vport->txvlan_cfg.accept_untag = true;
4699 vport->txvlan_cfg.insert_tag1_en = false;
4700 vport->txvlan_cfg.insert_tag2_en = false;
4701 vport->txvlan_cfg.default_tag1 = 0;
4702 vport->txvlan_cfg.default_tag2 = 0;
4703
4704 ret = hclge_set_vlan_tx_offload_cfg(vport);
4705 if (ret)
4706 return ret;
4707
4708 vport->rxvlan_cfg.strip_tag1_en = false;
4709 vport->rxvlan_cfg.strip_tag2_en = true;
4710 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4711 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4712
4713 ret = hclge_set_vlan_rx_offload_cfg(vport);
4714 if (ret)
4715 return ret;
4716 }
4717
5e43aef8
L		 4718 handle = &hdev->vport[0].nic;
4719 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4720}
4721
5f9a7732
PL		 4722static int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4723{
4724 struct hclge_vport *vport = hclge_get_vport(handle);
4725
4726 vport->rxvlan_cfg.strip_tag1_en = false;
4727 vport->rxvlan_cfg.strip_tag2_en = enable;
4728 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4729 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4730
4731 return hclge_set_vlan_rx_offload_cfg(vport);
4732}
4733
46a3df9f
S		 4734static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4735{
4736 struct hclge_vport *vport = hclge_get_vport(handle);
d44f9b63 4737 struct hclge_config_max_frm_size_cmd *req;
46a3df9f
S		 4738 struct hclge_dev *hdev = vport->back;
4739 struct hclge_desc desc;
7393ed39 4740 int max_frm_size;
46a3df9f
S		 4741 int ret;
4742
7393ed39
FL		 4743 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4744
4745 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4746 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 4747 return -EINVAL;
4748
7393ed39
FL		 4749 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
4750
46a3df9f
S		 4751 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4752
d44f9b63 4753 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
7393ed39 4754 req->max_frm_size = cpu_to_le16(max_frm_size);
46a3df9f
S		 4755
4756 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4757 if (ret) {
4758 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4759 return ret;
4760 }
4761
7393ed39
FL		 4762 hdev->mps = max_frm_size;
4763
46a3df9f
S		 4764 return 0;
4765}
4766
4767static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4768 bool enable)
4769{
d44f9b63 4770 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4771 struct hclge_desc desc;
4772 int ret;
4773
4774 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4775
d44f9b63 4776 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4777 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4778 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4779
4780 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4781 if (ret) {
4782 dev_err(&hdev->pdev->dev,
4783 "Send tqp reset cmd error, status =%d\n", ret);
4784 return ret;
4785 }
4786
4787 return 0;
4788}
4789
4790static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4791{
d44f9b63 4792 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4793 struct hclge_desc desc;
4794 int ret;
4795
4796 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4797
d44f9b63 4798 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4799 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4800
4801 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4802 if (ret) {
4803 dev_err(&hdev->pdev->dev,
4804 "Get reset status error, status =%d\n", ret);
4805 return ret;
4806 }
4807
4808 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4809}
4810
e5e89cda
PL		 4811static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
4812 u16 queue_id)
4813{
4814 struct hnae3_queue *queue;
4815 struct hclge_tqp *tqp;
4816
4817 queue = handle->kinfo.tqp[queue_id];
4818 tqp = container_of(queue, struct hclge_tqp, q);
4819
4820 return tqp->index;
4821}
4822
63d7e66f 4823void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 4824{
4825 struct hclge_vport *vport = hclge_get_vport(handle);
4826 struct hclge_dev *hdev = vport->back;
4827 int reset_try_times = 0;
4828 int reset_status;
e5e89cda 4829 u16 queue_gid;
46a3df9f
S		 4830 int ret;
4831
e5e89cda
PL		 4832 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
4833
46a3df9f
S		 4834 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4835 if (ret) {
4836 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4837 return;
4838 }
4839
e5e89cda 4840 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 4841 if (ret) {
4842 dev_warn(&hdev->pdev->dev,
4843 "Send reset tqp cmd fail, ret = %d\n", ret);
4844 return;
4845 }
4846
4847 reset_try_times = 0;
4848 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4849 /* Wait for tqp hw reset */
4850 msleep(20);
e5e89cda 4851 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 4852 if (reset_status)
4853 break;
4854 }
4855
4856 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4857 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4858 return;
4859 }
4860
e5e89cda 4861 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 4862 if (ret) {
4863 dev_warn(&hdev->pdev->dev,
4864 "Deassert the soft reset fail, ret = %d\n", ret);
4865 return;
4866 }
4867}
4868
4869static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4870{
4871 struct hclge_vport *vport = hclge_get_vport(handle);
4872 struct hclge_dev *hdev = vport->back;
4873
4874 return hdev->fw_version;
4875}
4876
a2cfbadb
PL		 4877static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
4878 u32 *flowctrl_adv)
4879{
4880 struct hclge_vport *vport = hclge_get_vport(handle);
4881 struct hclge_dev *hdev = vport->back;
4882 struct phy_device *phydev = hdev->hw.mac.phydev;
4883
4884 if (!phydev)
4885 return;
4886
4887 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
4888 (phydev->advertising & ADVERTISED_Asym_Pause);
4889}
4890
09ea401e
PL		 4891static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4892{
4893 struct phy_device *phydev = hdev->hw.mac.phydev;
4894
4895 if (!phydev)
4896 return;
4897
4898 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
4899
4900 if (rx_en)
4901 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
4902
4903 if (tx_en)
4904 phydev->advertising ^= ADVERTISED_Asym_Pause;
4905}
4906
4907static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4908{
09ea401e
PL		 4909 int ret;
4910
4911 if (rx_en && tx_en)
7a28a82a 4912 hdev->fc_mode_last_time = HCLGE_FC_FULL;
09ea401e 4913 else if (rx_en && !tx_en)
7a28a82a 4914 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
09ea401e 4915 else if (!rx_en && tx_en)
7a28a82a 4916 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
09ea401e 4917 else
7a28a82a 4918 hdev->fc_mode_last_time = HCLGE_FC_NONE;
09ea401e 4919
7a28a82a 4920 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
09ea401e 4921 return 0;
09ea401e
PL		 4922
4923 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
4924 if (ret) {
4925 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
4926 ret);
4927 return ret;
4928 }
4929
7a28a82a 4930 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
09ea401e
PL		 4931
4932 return 0;
4933}
4934
6282f2ea
PL		 4935int hclge_cfg_flowctrl(struct hclge_dev *hdev)
4936{
4937 struct phy_device *phydev = hdev->hw.mac.phydev;
4938 u16 remote_advertising = 0;
4939 u16 local_advertising = 0;
4940 u32 rx_pause, tx_pause;
4941 u8 flowctl;
4942
4943 if (!phydev->link || !phydev->autoneg)
4944 return 0;
4945
4946 if (phydev->advertising & ADVERTISED_Pause)
4947 local_advertising = ADVERTISE_PAUSE_CAP;
4948
4949 if (phydev->advertising & ADVERTISED_Asym_Pause)
4950 local_advertising |= ADVERTISE_PAUSE_ASYM;
4951
4952 if (phydev->pause)
4953 remote_advertising = LPA_PAUSE_CAP;
4954
4955 if (phydev->asym_pause)
4956 remote_advertising |= LPA_PAUSE_ASYM;
4957
4958 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
4959 remote_advertising);
4960 tx_pause = flowctl & FLOW_CTRL_TX;
4961 rx_pause = flowctl & FLOW_CTRL_RX;
4962
4963 if (phydev->duplex == HCLGE_MAC_HALF) {
4964 tx_pause = 0;
4965 rx_pause = 0;
4966 }
4967
4968 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
4969}
4970
46a3df9f
S		 4971static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4972 u32 *rx_en, u32 *tx_en)
4973{
4974 struct hclge_vport *vport = hclge_get_vport(handle);
4975 struct hclge_dev *hdev = vport->back;
4976
4977 *auto_neg = hclge_get_autoneg(handle);
4978
4979 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4980 *rx_en = 0;
4981 *tx_en = 0;
4982 return;
4983 }
4984
4985 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4986 *rx_en = 1;
4987 *tx_en = 0;
4988 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4989 *tx_en = 1;
4990 *rx_en = 0;
4991 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4992 *rx_en = 1;
4993 *tx_en = 1;
4994 } else {
4995 *rx_en = 0;
4996 *tx_en = 0;
4997 }
4998}
4999
09ea401e
PL		 5000static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5001 u32 rx_en, u32 tx_en)
5002{
5003 struct hclge_vport *vport = hclge_get_vport(handle);
5004 struct hclge_dev *hdev = vport->back;
5005 struct phy_device *phydev = hdev->hw.mac.phydev;
5006 u32 fc_autoneg;
5007
5008 /* Only support flow control negotiation for netdev with
5009 * phy attached for now.
5010 */
5011 if (!phydev)
5012 return -EOPNOTSUPP;
5013
5014 fc_autoneg = hclge_get_autoneg(handle);
5015 if (auto_neg != fc_autoneg) {
5016 dev_info(&hdev->pdev->dev,
5017 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5018 return -EOPNOTSUPP;
5019 }
5020
5021 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5022 dev_info(&hdev->pdev->dev,
5023 "Priority flow control enabled. Cannot set link flow control.\n");
5024 return -EOPNOTSUPP;
5025 }
5026
5027 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5028
5029 if (!fc_autoneg)
5030 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5031
5032 return phy_start_aneg(phydev);
5033}
5034
46a3df9f
S		 5035static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5036 u8 *auto_neg, u32 *speed, u8 *duplex)
5037{
5038 struct hclge_vport *vport = hclge_get_vport(handle);
5039 struct hclge_dev *hdev = vport->back;
5040
5041 if (speed)
5042 *speed = hdev->hw.mac.speed;
5043 if (duplex)
5044 *duplex = hdev->hw.mac.duplex;
5045 if (auto_neg)
5046 *auto_neg = hdev->hw.mac.autoneg;
5047}
5048
5049static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5050{
5051 struct hclge_vport *vport = hclge_get_vport(handle);
5052 struct hclge_dev *hdev = vport->back;
5053
5054 if (media_type)
5055 *media_type = hdev->hw.mac.media_type;
5056}
5057
5058static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5059 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5060{
5061 struct hclge_vport *vport = hclge_get_vport(handle);
5062 struct hclge_dev *hdev = vport->back;
5063 struct phy_device *phydev = hdev->hw.mac.phydev;
5064 int mdix_ctrl, mdix, retval, is_resolved;
5065
5066 if (!phydev) {
5067 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5068 *tp_mdix = ETH_TP_MDI_INVALID;
5069 return;
5070 }
5071
5072 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5073
5074 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
5075 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5076 HCLGE_PHY_MDIX_CTRL_S);
5077
5078 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
5079 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5080 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
5081
5082 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5083
5084 switch (mdix_ctrl) {
5085 case 0x0:
5086 *tp_mdix_ctrl = ETH_TP_MDI;
5087 break;
5088 case 0x1:
5089 *tp_mdix_ctrl = ETH_TP_MDI_X;
5090 break;
5091 case 0x3:
5092 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5093 break;
5094 default:
5095 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5096 break;
5097 }
5098
5099 if (!is_resolved)
5100 *tp_mdix = ETH_TP_MDI_INVALID;
5101 else if (mdix)
5102 *tp_mdix = ETH_TP_MDI_X;
5103 else
5104 *tp_mdix = ETH_TP_MDI;
5105}
5106
5107static int hclge_init_client_instance(struct hnae3_client *client,
5108 struct hnae3_ae_dev *ae_dev)
5109{
5110 struct hclge_dev *hdev = ae_dev->priv;
5111 struct hclge_vport *vport;
5112 int i, ret;
5113
5114 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5115 vport = &hdev->vport[i];
5116
5117 switch (client->type) {
5118 case HNAE3_CLIENT_KNIC:
5119
5120 hdev->nic_client = client;
5121 vport->nic.client = client;
5122 ret = client->ops->init_instance(&vport->nic);
5123 if (ret)
5124 goto err;
5125
5126 if (hdev->roce_client &&
e92a0843 5127 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5128 struct hnae3_client *rc = hdev->roce_client;
5129
5130 ret = hclge_init_roce_base_info(vport);
5131 if (ret)
5132 goto err;
5133
5134 ret = rc->ops->init_instance(&vport->roce);
5135 if (ret)
5136 goto err;
5137 }
5138
5139 break;
5140 case HNAE3_CLIENT_UNIC:
5141 hdev->nic_client = client;
5142 vport->nic.client = client;
5143
5144 ret = client->ops->init_instance(&vport->nic);
5145 if (ret)
5146 goto err;
5147
5148 break;
5149 case HNAE3_CLIENT_ROCE:
e92a0843 5150 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5151 hdev->roce_client = client;
5152 vport->roce.client = client;
5153 }
5154
3a46f34d 5155 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5156 ret = hclge_init_roce_base_info(vport);
5157 if (ret)
5158 goto err;
5159
5160 ret = client->ops->init_instance(&vport->roce);
5161 if (ret)
5162 goto err;
5163 }
5164 }
5165 }
5166
5167 return 0;
5168err:
5169 return ret;
5170}
5171
5172static void hclge_uninit_client_instance(struct hnae3_client *client,
5173 struct hnae3_ae_dev *ae_dev)
5174{
5175 struct hclge_dev *hdev = ae_dev->priv;
5176 struct hclge_vport *vport;
5177 int i;
5178
5179 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5180 vport = &hdev->vport[i];
a17dcf3f 5181 if (hdev->roce_client) {
46a3df9f
S		 5182 hdev->roce_client->ops->uninit_instance(&vport->roce,
5183 0);
a17dcf3f
L		 5184 hdev->roce_client = NULL;
5185 vport->roce.client = NULL;
5186 }
46a3df9f
S		 5187 if (client->type == HNAE3_CLIENT_ROCE)
5188 return;
a17dcf3f 5189 if (client->ops->uninit_instance) {
46a3df9f 5190 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5191 hdev->nic_client = NULL;
5192 vport->nic.client = NULL;
5193 }
46a3df9f
S		 5194 }
5195}
5196
5197static int hclge_pci_init(struct hclge_dev *hdev)
5198{
5199 struct pci_dev *pdev = hdev->pdev;
5200 struct hclge_hw *hw;
5201 int ret;
5202
5203 ret = pci_enable_device(pdev);
5204 if (ret) {
5205 dev_err(&pdev->dev, "failed to enable PCI device\n");
5206 goto err_no_drvdata;
5207 }
5208
5209 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5210 if (ret) {
5211 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5212 if (ret) {
5213 dev_err(&pdev->dev,
5214 "can't set consistent PCI DMA");
5215 goto err_disable_device;
5216 }
5217 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5218 }
5219
5220 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5221 if (ret) {
5222 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5223 goto err_disable_device;
5224 }
5225
5226 pci_set_master(pdev);
5227 hw = &hdev->hw;
5228 hw->back = hdev;
5229 hw->io_base = pcim_iomap(pdev, 2, 0);
5230 if (!hw->io_base) {
5231 dev_err(&pdev->dev, "Can't map configuration register space\n");
5232 ret = -ENOMEM;
5233 goto err_clr_master;
5234 }
5235
709eb41a
L		 5236 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5237
46a3df9f
S		 5238 return 0;
5239err_clr_master:
5240 pci_clear_master(pdev);
5241 pci_release_regions(pdev);
5242err_disable_device:
5243 pci_disable_device(pdev);
5244err_no_drvdata:
5245 pci_set_drvdata(pdev, NULL);
5246
5247 return ret;
5248}
5249
5250static void hclge_pci_uninit(struct hclge_dev *hdev)
5251{
5252 struct pci_dev *pdev = hdev->pdev;
5253
887c3820 5254 pci_free_irq_vectors(pdev);
46a3df9f
S		 5255 pci_clear_master(pdev);
5256 pci_release_mem_regions(pdev);
5257 pci_disable_device(pdev);
5258}
5259
5260static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5261{
5262 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5263 struct hclge_dev *hdev;
5264 int ret;
5265
5266 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5267 if (!hdev) {
5268 ret = -ENOMEM;
5269 goto err_hclge_dev;
5270 }
5271
46a3df9f
S		 5272 hdev->pdev = pdev;
5273 hdev->ae_dev = ae_dev;
4ed340ab 5274 hdev->reset_type = HNAE3_NONE_RESET;
ed4a1bb8 5275 hdev->reset_request = 0;
202f2014 5276 hdev->reset_pending = 0;
46a3df9f
S		 5277 ae_dev->priv = hdev;
5278
46a3df9f
S		 5279 ret = hclge_pci_init(hdev);
5280 if (ret) {
5281 dev_err(&pdev->dev, "PCI init failed\n");
5282 goto err_pci_init;
5283 }
5284
3efb960f
L		 5285 /* Firmware command queue initialize */
5286 ret = hclge_cmd_queue_init(hdev);
5287 if (ret) {
5288 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5289 return ret;
5290 }
5291
5292 /* Firmware command initialize */
46a3df9f
S		 5293 ret = hclge_cmd_init(hdev);
5294 if (ret)
5295 goto err_cmd_init;
5296
5297 ret = hclge_get_cap(hdev);
5298 if (ret) {
e00e2197
CIK		 5299 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5300 ret);
46a3df9f
S		 5301 return ret;
5302 }
5303
5304 ret = hclge_configure(hdev);
5305 if (ret) {
5306 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5307 return ret;
5308 }
5309
887c3820 5310 ret = hclge_init_msi(hdev);
46a3df9f 5311 if (ret) {
887c3820 5312 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
46a3df9f
S		 5313 return ret;
5314 }
5315
466b0c00
L		 5316 ret = hclge_misc_irq_init(hdev);
5317 if (ret) {
5318 dev_err(&pdev->dev,
5319 "Misc IRQ(vector0) init error, ret = %d.\n",
5320 ret);
5321 return ret;
5322 }
5323
46a3df9f
S		 5324 ret = hclge_alloc_tqps(hdev);
5325 if (ret) {
5326 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5327 return ret;
5328 }
5329
5330 ret = hclge_alloc_vport(hdev);
5331 if (ret) {
5332 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5333 return ret;
5334 }
5335
7df7dad6
L		 5336 ret = hclge_map_tqp(hdev);
5337 if (ret) {
5338 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5339 return ret;
5340 }
5341
cf9cca2d 5342 ret = hclge_mac_mdio_config(hdev);
5343 if (ret) {
5344 dev_warn(&hdev->pdev->dev,
5345 "mdio config fail ret=%d\n", ret);
5346 return ret;
5347 }
5348
46a3df9f
S		 5349 ret = hclge_mac_init(hdev);
5350 if (ret) {
5351 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5352 return ret;
5353 }
5354 ret = hclge_buffer_alloc(hdev);
5355 if (ret) {
5356 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5357 return ret;
5358 }
5359
5360 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5361 if (ret) {
5362 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5363 return ret;
5364 }
5365
46a3df9f
S		 5366 ret = hclge_init_vlan_config(hdev);
5367 if (ret) {
5368 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5369 return ret;
5370 }
5371
5372 ret = hclge_tm_schd_init(hdev);
5373 if (ret) {
5374 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5375 return ret;
68ece54e
YL		 5376 }
5377
5378 ret = hclge_rss_init_hw(hdev);
5379 if (ret) {
5380 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5381 return ret;
46a3df9f
S		 5382 }
5383
635bfb58
FL		 5384 ret = init_mgr_tbl(hdev);
5385 if (ret) {
5386 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
5387 return ret;
5388 }
5389
cacde272
YL		 5390 hclge_dcb_ops_set(hdev);
5391
d039ef68 5392 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5393 INIT_WORK(&hdev->service_task, hclge_service_task);
ed4a1bb8 5394 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
22fd3468 5395 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5396
466b0c00
L		 5397 /* Enable MISC vector(vector0) */
5398 hclge_enable_vector(&hdev->misc_vector, true);
5399
46a3df9f
S		 5400 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5401 set_bit(HCLGE_STATE_DOWN, &hdev->state);
ed4a1bb8
SM		 5402 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5403 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
22fd3468
SM		 5404 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5405 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
46a3df9f
S		 5406
5407 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5408 return 0;
5409
5410err_cmd_init:
5411 pci_release_regions(pdev);
5412err_pci_init:
5413 pci_set_drvdata(pdev, NULL);
5414err_hclge_dev:
5415 return ret;
5416}
5417
c6dc5213 5418static void hclge_stats_clear(struct hclge_dev *hdev)
5419{
5420 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5421}
5422
4ed340ab
L		 5423static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5424{
5425 struct hclge_dev *hdev = ae_dev->priv;
5426 struct pci_dev *pdev = ae_dev->pdev;
5427 int ret;
5428
5429 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5430
c6dc5213 5431 hclge_stats_clear(hdev);
5432
4ed340ab
L		 5433 ret = hclge_cmd_init(hdev);
5434 if (ret) {
5435 dev_err(&pdev->dev, "Cmd queue init failed\n");
5436 return ret;
5437 }
5438
5439 ret = hclge_get_cap(hdev);
5440 if (ret) {
5441 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5442 ret);
5443 return ret;
5444 }
5445
5446 ret = hclge_configure(hdev);
5447 if (ret) {
5448 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5449 return ret;
5450 }
5451
5452 ret = hclge_map_tqp(hdev);
5453 if (ret) {
5454 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5455 return ret;
5456 }
5457
5458 ret = hclge_mac_init(hdev);
5459 if (ret) {
5460 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5461 return ret;
5462 }
5463
5464 ret = hclge_buffer_alloc(hdev);
5465 if (ret) {
5466 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5467 return ret;
5468 }
5469
5470 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5471 if (ret) {
5472 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5473 return ret;
5474 }
5475
5476 ret = hclge_init_vlan_config(hdev);
5477 if (ret) {
5478 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5479 return ret;
5480 }
5481
5482 ret = hclge_tm_schd_init(hdev);
5483 if (ret) {
5484 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5485 return ret;
5486 }
5487
5488 ret = hclge_rss_init_hw(hdev);
5489 if (ret) {
5490 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5491 return ret;
5492 }
5493
5494 /* Enable MISC vector(vector0) */
5495 hclge_enable_vector(&hdev->misc_vector, true);
5496
5497 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5498 HCLGE_DRIVER_NAME);
5499
5500 return 0;
5501}
5502
46a3df9f
S		 5503static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5504{
5505 struct hclge_dev *hdev = ae_dev->priv;
5506 struct hclge_mac *mac = &hdev->hw.mac;
5507
5508 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5509
2a32ca13
AB		 5510 if (IS_ENABLED(CONFIG_PCI_IOV))
5511 hclge_disable_sriov(hdev);
46a3df9f 5512
d039ef68 5513 if (hdev->service_timer.function)
46a3df9f
S		 5514 del_timer_sync(&hdev->service_timer);
5515 if (hdev->service_task.func)
5516 cancel_work_sync(&hdev->service_task);
ed4a1bb8
SM		 5517 if (hdev->rst_service_task.func)
5518 cancel_work_sync(&hdev->rst_service_task);
22fd3468
SM		 5519 if (hdev->mbx_service_task.func)
5520 cancel_work_sync(&hdev->mbx_service_task);
46a3df9f
S		 5521
5522 if (mac->phydev)
5523 mdiobus_unregister(mac->mdio_bus);
5524
466b0c00
L		 5525 /* Disable MISC vector(vector0) */
5526 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 5527 hclge_destroy_cmd_queue(&hdev->hw);
202f2014 5528 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5529 hclge_pci_uninit(hdev);
5530 ae_dev->priv = NULL;
5531}
5532
4f645a90
PL		 5533static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5534{
5535 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5536 struct hclge_vport *vport = hclge_get_vport(handle);
5537 struct hclge_dev *hdev = vport->back;
5538
5539 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5540}
5541
5542static void hclge_get_channels(struct hnae3_handle *handle,
5543 struct ethtool_channels *ch)
5544{
5545 struct hclge_vport *vport = hclge_get_vport(handle);
5546
5547 ch->max_combined = hclge_get_max_channels(handle);
5548 ch->other_count = 1;
5549 ch->max_other = 1;
5550 ch->combined_count = vport->alloc_tqps;
5551}
5552
f1f779ce
PL		 5553static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5554 u16 *free_tqps, u16 *max_rss_size)
5555{
5556 struct hclge_vport *vport = hclge_get_vport(handle);
5557 struct hclge_dev *hdev = vport->back;
5558 u16 temp_tqps = 0;
5559 int i;
5560
5561 for (i = 0; i < hdev->num_tqps; i++) {
5562 if (!hdev->htqp[i].alloced)
5563 temp_tqps++;
5564 }
5565 *free_tqps = temp_tqps;
5566 *max_rss_size = hdev->rss_size_max;
5567}
5568
5569static void hclge_release_tqp(struct hclge_vport *vport)
5570{
5571 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5572 struct hclge_dev *hdev = vport->back;
5573 int i;
5574
5575 for (i = 0; i < kinfo->num_tqps; i++) {
5576 struct hclge_tqp *tqp =
5577 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5578
5579 tqp->q.handle = NULL;
5580 tqp->q.tqp_index = 0;
5581 tqp->alloced = false;
5582 }
5583
5584 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5585 kinfo->tqp = NULL;
5586}
5587
5588static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5589{
5590 struct hclge_vport *vport = hclge_get_vport(handle);
5591 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5592 struct hclge_dev *hdev = vport->back;
5593 int cur_rss_size = kinfo->rss_size;
5594 int cur_tqps = kinfo->num_tqps;
5595 u16 tc_offset[HCLGE_MAX_TC_NUM];
5596 u16 tc_valid[HCLGE_MAX_TC_NUM];
5597 u16 tc_size[HCLGE_MAX_TC_NUM];
5598 u16 roundup_size;
5599 u32 *rss_indir;
5600 int ret, i;
5601
5602 hclge_release_tqp(vport);
5603
5604 ret = hclge_knic_setup(vport, new_tqps_num);
5605 if (ret) {
5606 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5607 return ret;
5608 }
5609
5610 ret = hclge_map_tqp_to_vport(hdev, vport);
5611 if (ret) {
5612 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5613 return ret;
5614 }
5615
5616 ret = hclge_tm_schd_init(hdev);
5617 if (ret) {
5618 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5619 return ret;
5620 }
5621
5622 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5623 roundup_size = ilog2(roundup_size);
5624 /* Set the RSS TC mode according to the new RSS size */
5625 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5626 tc_valid[i] = 0;
5627
5628 if (!(hdev->hw_tc_map & BIT(i)))
5629 continue;
5630
5631 tc_valid[i] = 1;
5632 tc_size[i] = roundup_size;
5633 tc_offset[i] = kinfo->rss_size * i;
5634 }
5635 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5636 if (ret)
5637 return ret;
5638
5639 /* Reinitializes the rss indirect table according to the new RSS size */
5640 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5641 if (!rss_indir)
5642 return -ENOMEM;
5643
5644 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5645 rss_indir[i] = i % kinfo->rss_size;
5646
5647 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5648 if (ret)
5649 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5650 ret);
5651
5652 kfree(rss_indir);
5653
5654 if (!ret)
5655 dev_info(&hdev->pdev->dev,
5656 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5657 cur_rss_size, kinfo->rss_size,
5658 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5659
5660 return ret;
5661}
5662
db2a3e43
FL		 5663static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5664 u32 *regs_num_64_bit)
5665{
5666 struct hclge_desc desc;
5667 u32 total_num;
5668 int ret;
5669
5670 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5671 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5672 if (ret) {
5673 dev_err(&hdev->pdev->dev,
5674 "Query register number cmd failed, ret = %d.\n", ret);
5675 return ret;
5676 }
5677
5678 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5679 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5680
5681 total_num = *regs_num_32_bit + *regs_num_64_bit;
5682 if (!total_num)
5683 return -EINVAL;
5684
5685 return 0;
5686}
5687
5688static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5689 void *data)
5690{
5691#define HCLGE_32_BIT_REG_RTN_DATANUM 8
5692
5693 struct hclge_desc *desc;
5694 u32 *reg_val = data;
5695 __le32 *desc_data;
5696 int cmd_num;
5697 int i, k, n;
5698 int ret;
5699
5700 if (regs_num == 0)
5701 return 0;
5702
5703 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
5704 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5705 if (!desc)
5706 return -ENOMEM;
5707
5708 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
5709 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5710 if (ret) {
5711 dev_err(&hdev->pdev->dev,
5712 "Query 32 bit register cmd failed, ret = %d.\n", ret);
5713 kfree(desc);
5714 return ret;
5715 }
5716
5717 for (i = 0; i < cmd_num; i++) {
5718 if (i == 0) {
5719 desc_data = (__le32 *)(&desc[i].data[0]);
5720 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
5721 } else {
5722 desc_data = (__le32 *)(&desc[i]);
5723 n = HCLGE_32_BIT_REG_RTN_DATANUM;
5724 }
5725 for (k = 0; k < n; k++) {
5726 *reg_val++ = le32_to_cpu(*desc_data++);
5727
5728 regs_num--;
5729 if (!regs_num)
5730 break;
5731 }
5732 }
5733
5734 kfree(desc);
5735 return 0;
5736}
5737
5738static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5739 void *data)
5740{
5741#define HCLGE_64_BIT_REG_RTN_DATANUM 4
5742
5743 struct hclge_desc *desc;
5744 u64 *reg_val = data;
5745 __le64 *desc_data;
5746 int cmd_num;
5747 int i, k, n;
5748 int ret;
5749
5750 if (regs_num == 0)
5751 return 0;
5752
5753 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
5754 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5755 if (!desc)
5756 return -ENOMEM;
5757
5758 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
5759 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5760 if (ret) {
5761 dev_err(&hdev->pdev->dev,
5762 "Query 64 bit register cmd failed, ret = %d.\n", ret);
5763 kfree(desc);
5764 return ret;
5765 }
5766
5767 for (i = 0; i < cmd_num; i++) {
5768 if (i == 0) {
5769 desc_data = (__le64 *)(&desc[i].data[0]);
5770 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
5771 } else {
5772 desc_data = (__le64 *)(&desc[i]);
5773 n = HCLGE_64_BIT_REG_RTN_DATANUM;
5774 }
5775 for (k = 0; k < n; k++) {
5776 *reg_val++ = le64_to_cpu(*desc_data++);
5777
5778 regs_num--;
5779 if (!regs_num)
5780 break;
5781 }
5782 }
5783
5784 kfree(desc);
5785 return 0;
5786}
5787
5788static int hclge_get_regs_len(struct hnae3_handle *handle)
5789{
5790 struct hclge_vport *vport = hclge_get_vport(handle);
5791 struct hclge_dev *hdev = vport->back;
5792 u32 regs_num_32_bit, regs_num_64_bit;
5793 int ret;
5794
5795 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5796 if (ret) {
5797 dev_err(&hdev->pdev->dev,
5798 "Get register number failed, ret = %d.\n", ret);
5799 return -EOPNOTSUPP;
5800 }
5801
5802 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
5803}
5804
5805static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
5806 void *data)
5807{
5808 struct hclge_vport *vport = hclge_get_vport(handle);
5809 struct hclge_dev *hdev = vport->back;
5810 u32 regs_num_32_bit, regs_num_64_bit;
5811 int ret;
5812
5813 *version = hdev->fw_version;
5814
5815 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5816 if (ret) {
5817 dev_err(&hdev->pdev->dev,
5818 "Get register number failed, ret = %d.\n", ret);
5819 return;
5820 }
5821
5822 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
5823 if (ret) {
5824 dev_err(&hdev->pdev->dev,
5825 "Get 32 bit register failed, ret = %d.\n", ret);
5826 return;
5827 }
5828
5829 data = (u32 *)data + regs_num_32_bit;
5830 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
5831 data);
5832 if (ret)
5833 dev_err(&hdev->pdev->dev,
5834 "Get 64 bit register failed, ret = %d.\n", ret);
5835}
5836
d9a0884e
JS		 5837static int hclge_set_led_status_sfp(struct hclge_dev *hdev, u8 speed_led_status,
5838 u8 act_led_status, u8 link_led_status,
5839 u8 locate_led_status)
5840{
5841 struct hclge_set_led_state_cmd *req;
5842 struct hclge_desc desc;
5843 int ret;
5844
5845 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
5846
5847 req = (struct hclge_set_led_state_cmd *)desc.data;
5848 hnae_set_field(req->port_speed_led_config, HCLGE_LED_PORT_SPEED_STATE_M,
5849 HCLGE_LED_PORT_SPEED_STATE_S, speed_led_status);
5850 hnae_set_field(req->link_led_config, HCLGE_LED_ACTIVITY_STATE_M,
5851 HCLGE_LED_ACTIVITY_STATE_S, act_led_status);
5852 hnae_set_field(req->activity_led_config, HCLGE_LED_LINK_STATE_M,
5853 HCLGE_LED_LINK_STATE_S, link_led_status);
5854 hnae_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
5855 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
5856
5857 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5858 if (ret)
5859 dev_err(&hdev->pdev->dev,
5860 "Send set led state cmd error, ret =%d\n", ret);
5861
5862 return ret;
5863}
5864
5865enum hclge_led_status {
5866 HCLGE_LED_OFF,
5867 HCLGE_LED_ON,
5868 HCLGE_LED_NO_CHANGE = 0xFF,
5869};
5870
5871static int hclge_set_led_id(struct hnae3_handle *handle,
5872 enum ethtool_phys_id_state status)
5873{
5874#define BLINK_FREQUENCY 2
5875 struct hclge_vport *vport = hclge_get_vport(handle);
5876 struct hclge_dev *hdev = vport->back;
5877 struct phy_device *phydev = hdev->hw.mac.phydev;
5878 int ret = 0;
5879
5880 if (phydev || hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
5881 return -EOPNOTSUPP;
5882
5883 switch (status) {
5884 case ETHTOOL_ID_ACTIVE:
5885 ret = hclge_set_led_status_sfp(hdev,
5886 HCLGE_LED_NO_CHANGE,
5887 HCLGE_LED_NO_CHANGE,
5888 HCLGE_LED_NO_CHANGE,
5889 HCLGE_LED_ON);
5890 break;
5891 case ETHTOOL_ID_INACTIVE:
5892 ret = hclge_set_led_status_sfp(hdev,
5893 HCLGE_LED_NO_CHANGE,
5894 HCLGE_LED_NO_CHANGE,
5895 HCLGE_LED_NO_CHANGE,
5896 HCLGE_LED_OFF);
5897 break;
5898 default:
5899 ret = -EINVAL;
5900 break;
5901 }
5902
5903 return ret;
5904}
5905
fe36292f
JS		 5906enum hclge_led_port_speed {
5907 HCLGE_SPEED_LED_FOR_1G,
5908 HCLGE_SPEED_LED_FOR_10G,
5909 HCLGE_SPEED_LED_FOR_25G,
5910 HCLGE_SPEED_LED_FOR_40G,
5911 HCLGE_SPEED_LED_FOR_50G,
5912 HCLGE_SPEED_LED_FOR_100G,
5913};
5914
5915static u8 hclge_led_get_speed_status(u32 speed)
5916{
5917 u8 speed_led;
5918
5919 switch (speed) {
5920 case HCLGE_MAC_SPEED_1G:
5921 speed_led = HCLGE_SPEED_LED_FOR_1G;
5922 break;
5923 case HCLGE_MAC_SPEED_10G:
5924 speed_led = HCLGE_SPEED_LED_FOR_10G;
5925 break;
5926 case HCLGE_MAC_SPEED_25G:
5927 speed_led = HCLGE_SPEED_LED_FOR_25G;
5928 break;
5929 case HCLGE_MAC_SPEED_40G:
5930 speed_led = HCLGE_SPEED_LED_FOR_40G;
5931 break;
5932 case HCLGE_MAC_SPEED_50G:
5933 speed_led = HCLGE_SPEED_LED_FOR_50G;
5934 break;
5935 case HCLGE_MAC_SPEED_100G:
5936 speed_led = HCLGE_SPEED_LED_FOR_100G;
5937 break;
5938 default:
5939 speed_led = HCLGE_LED_NO_CHANGE;
5940 }
5941
5942 return speed_led;
5943}
5944
5945static int hclge_update_led_status(struct hclge_dev *hdev)
5946{
5947 u8 port_speed_status, link_status, activity_status;
5948 u64 rx_pkts, tx_pkts;
5949
5950 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
5951 return 0;
5952
5953 port_speed_status = hclge_led_get_speed_status(hdev->hw.mac.speed);
5954
5955 rx_pkts = hdev->hw_stats.mac_stats.mac_rx_total_pkt_num;
5956 tx_pkts = hdev->hw_stats.mac_stats.mac_tx_total_pkt_num;
5957 if (rx_pkts != hdev->rx_pkts_for_led ||
5958 tx_pkts != hdev->tx_pkts_for_led)
5959 activity_status = HCLGE_LED_ON;
5960 else
5961 activity_status = HCLGE_LED_OFF;
5962 hdev->rx_pkts_for_led = rx_pkts;
5963 hdev->tx_pkts_for_led = tx_pkts;
5964
5965 if (hdev->hw.mac.link)
5966 link_status = HCLGE_LED_ON;
5967 else
5968 link_status = HCLGE_LED_OFF;
5969
5970 return hclge_set_led_status_sfp(hdev, port_speed_status,
5971 activity_status, link_status,
5972 HCLGE_LED_NO_CHANGE);
5973}
5974
46a3df9f
S		 5975static const struct hnae3_ae_ops hclge_ops = {
5976 .init_ae_dev = hclge_init_ae_dev,
5977 .uninit_ae_dev = hclge_uninit_ae_dev,
5978 .init_client_instance = hclge_init_client_instance,
5979 .uninit_client_instance = hclge_uninit_client_instance,
63d7e66f
SM		 5980 .map_ring_to_vector = hclge_map_ring_to_vector,
5981 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f
S		 5982 .get_vector = hclge_get_vector,
5983 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 5984 .set_loopback = hclge_set_loopback,
46a3df9f
S		 5985 .start = hclge_ae_start,
5986 .stop = hclge_ae_stop,
5987 .get_status = hclge_get_status,
5988 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5989 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5990 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5991 .get_media_type = hclge_get_media_type,
5992 .get_rss_key_size = hclge_get_rss_key_size,
5993 .get_rss_indir_size = hclge_get_rss_indir_size,
5994 .get_rss = hclge_get_rss,
5995 .set_rss = hclge_set_rss,
f7db940a 5996 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 5997 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 5998 .get_tc_size = hclge_get_tc_size,
5999 .get_mac_addr = hclge_get_mac_addr,
6000 .set_mac_addr = hclge_set_mac_addr,
6001 .add_uc_addr = hclge_add_uc_addr,
6002 .rm_uc_addr = hclge_rm_uc_addr,
6003 .add_mc_addr = hclge_add_mc_addr,
6004 .rm_mc_addr = hclge_rm_mc_addr,
6005 .set_autoneg = hclge_set_autoneg,
6006 .get_autoneg = hclge_get_autoneg,
6007 .get_pauseparam = hclge_get_pauseparam,
09ea401e 6008 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6009 .set_mtu = hclge_set_mtu,
6010 .reset_queue = hclge_reset_tqp,
6011 .get_stats = hclge_get_stats,
6012 .update_stats = hclge_update_stats,
6013 .get_strings = hclge_get_strings,
6014 .get_sset_count = hclge_get_sset_count,
6015 .get_fw_version = hclge_get_fw_version,
6016 .get_mdix_mode = hclge_get_mdix_mode,
d818396d 6017 .enable_vlan_filter = hclge_enable_vlan_filter,
46a3df9f
S		 6018 .set_vlan_filter = hclge_set_port_vlan_filter,
6019 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5f9a7732 6020 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6021 .reset_event = hclge_reset_event,
f1f779ce
PL		 6022 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6023 .set_channels = hclge_set_channels,
4f645a90 6024 .get_channels = hclge_get_channels,
a2cfbadb 6025 .get_flowctrl_adv = hclge_get_flowctrl_adv,
db2a3e43
FL		 6026 .get_regs_len = hclge_get_regs_len,
6027 .get_regs = hclge_get_regs,
d9a0884e 6028 .set_led_id = hclge_set_led_id,
46a3df9f
S		 6029};
6030
6031static struct hnae3_ae_algo ae_algo = {
6032 .ops = &hclge_ops,
6033 .name = HCLGE_NAME,
6034 .pdev_id_table = ae_algo_pci_tbl,
6035};
6036
6037static int hclge_init(void)
6038{
6039 pr_info("%s is initializing\n", HCLGE_NAME);
6040
6041 return hnae3_register_ae_algo(&ae_algo);
6042}
6043
6044static void hclge_exit(void)
6045{
6046 hnae3_unregister_ae_algo(&ae_algo);
6047}
6048module_init(hclge_init);
6049module_exit(hclge_exit);
6050
6051MODULE_LICENSE("GPL");
6052MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6053MODULE_DESCRIPTION("HCLGE Driver");
6054MODULE_VERSION(HCLGE_MOD_VERSION);
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