]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: hns3: reallocate tx/rx buffer after changing mtu
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
2866ccb2 20#include <linux/if_vlan.h>
f2f432f2 21#include <net/rtnetlink.h>
46a3df9f 22#include "hclge_cmd.h"
cacde272 23#include "hclge_dcb.h"
46a3df9f 24#include "hclge_main.h"
dde1a86e 25#include "hclge_mbx.h"
46a3df9f
S		 26#include "hclge_mdio.h"
27#include "hclge_tm.h"
28#include "hnae3.h"
29
30#define HCLGE_NAME "hclge"
31#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35
46a3df9f
S		 36static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
37 enum hclge_mta_dmac_sel_type mta_mac_sel,
38 bool enable);
f9fd82a9 39static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 40static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 41static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
716aaac1 42static int hclge_update_led_status(struct hclge_dev *hdev);
46a3df9f
S		 43
44static struct hnae3_ae_algo ae_algo;
45
46static const struct pci_device_id ae_algo_pci_tbl[] = {
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 54 /* required last entry */
46a3df9f
S		 55 {0, }
56};
57
58static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
59 "Mac Loopback test",
60 "Serdes Loopback test",
61 "Phy Loopback test"
62};
63
64static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
65 {"igu_rx_oversize_pkt",
66 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
67 {"igu_rx_undersize_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
69 {"igu_rx_out_all_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
71 {"igu_rx_uni_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
73 {"igu_rx_multi_pkt",
74 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
75 {"igu_rx_broad_pkt",
76 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
77 {"egu_tx_out_all_pkt",
78 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
79 {"egu_tx_uni_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
81 {"egu_tx_multi_pkt",
82 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
83 {"egu_tx_broad_pkt",
84 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
85 {"ssu_ppp_mac_key_num",
86 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
87 {"ssu_ppp_host_key_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
89 {"ppp_ssu_mac_rlt_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
91 {"ppp_ssu_host_rlt_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
93 {"ssu_tx_in_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
95 {"ssu_tx_out_num",
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
97 {"ssu_rx_in_num",
98 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
99 {"ssu_rx_out_num",
100 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
101};
102
103static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
104 {"igu_rx_err_pkt",
105 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
106 {"igu_rx_no_eof_pkt",
107 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
108 {"igu_rx_no_sof_pkt",
109 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
110 {"egu_tx_1588_pkt",
111 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
112 {"ssu_full_drop_num",
113 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
114 {"ssu_part_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
116 {"ppp_key_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
118 {"ppp_rlt_drop_num",
119 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
120 {"ssu_key_drop_num",
121 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
122 {"pkt_curr_buf_cnt",
123 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
124 {"qcn_fb_rcv_cnt",
125 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
126 {"qcn_fb_drop_cnt",
127 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
128 {"qcn_fb_invaild_cnt",
129 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
130 {"rx_packet_tc0_in_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
132 {"rx_packet_tc1_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
134 {"rx_packet_tc2_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
136 {"rx_packet_tc3_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
138 {"rx_packet_tc4_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
140 {"rx_packet_tc5_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
142 {"rx_packet_tc6_in_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
144 {"rx_packet_tc7_in_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
146 {"rx_packet_tc0_out_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
148 {"rx_packet_tc1_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
150 {"rx_packet_tc2_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
152 {"rx_packet_tc3_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
154 {"rx_packet_tc4_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
156 {"rx_packet_tc5_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
158 {"rx_packet_tc6_out_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
160 {"rx_packet_tc7_out_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
162 {"tx_packet_tc0_in_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
164 {"tx_packet_tc1_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
166 {"tx_packet_tc2_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
168 {"tx_packet_tc3_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
170 {"tx_packet_tc4_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
172 {"tx_packet_tc5_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
174 {"tx_packet_tc6_in_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
176 {"tx_packet_tc7_in_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
178 {"tx_packet_tc0_out_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
180 {"tx_packet_tc1_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
182 {"tx_packet_tc2_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
184 {"tx_packet_tc3_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
186 {"tx_packet_tc4_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
188 {"tx_packet_tc5_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
190 {"tx_packet_tc6_out_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
192 {"tx_packet_tc7_out_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
194 {"pkt_curr_buf_tc0_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
196 {"pkt_curr_buf_tc1_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
198 {"pkt_curr_buf_tc2_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
200 {"pkt_curr_buf_tc3_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
202 {"pkt_curr_buf_tc4_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
204 {"pkt_curr_buf_tc5_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
206 {"pkt_curr_buf_tc6_cnt",
207 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
208 {"pkt_curr_buf_tc7_cnt",
209 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
210 {"mb_uncopy_num",
211 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
212 {"lo_pri_unicast_rlt_drop_num",
213 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
214 {"hi_pri_multicast_rlt_drop_num",
215 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
216 {"lo_pri_multicast_rlt_drop_num",
217 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
218 {"rx_oq_drop_pkt_cnt",
219 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
220 {"tx_oq_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
222 {"nic_l2_err_drop_pkt_cnt",
223 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
224 {"roc_l2_err_drop_pkt_cnt",
225 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
226};
227
228static const struct hclge_comm_stats_str g_mac_stats_string[] = {
229 {"mac_tx_mac_pause_num",
230 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
231 {"mac_rx_mac_pause_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
233 {"mac_tx_pfc_pri0_pkt_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
235 {"mac_tx_pfc_pri1_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
237 {"mac_tx_pfc_pri2_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
239 {"mac_tx_pfc_pri3_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
241 {"mac_tx_pfc_pri4_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
243 {"mac_tx_pfc_pri5_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
245 {"mac_tx_pfc_pri6_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
247 {"mac_tx_pfc_pri7_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
249 {"mac_rx_pfc_pri0_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
251 {"mac_rx_pfc_pri1_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
253 {"mac_rx_pfc_pri2_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
255 {"mac_rx_pfc_pri3_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
257 {"mac_rx_pfc_pri4_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
259 {"mac_rx_pfc_pri5_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
261 {"mac_rx_pfc_pri6_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
263 {"mac_rx_pfc_pri7_pkt_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
265 {"mac_tx_total_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
267 {"mac_tx_total_oct_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
269 {"mac_tx_good_pkt_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
271 {"mac_tx_bad_pkt_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
273 {"mac_tx_good_oct_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
275 {"mac_tx_bad_oct_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
277 {"mac_tx_uni_pkt_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
279 {"mac_tx_multi_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
281 {"mac_tx_broad_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
283 {"mac_tx_undersize_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
200a88c6
JS		 285 {"mac_tx_oversize_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 287 {"mac_tx_64_oct_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
289 {"mac_tx_65_127_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
291 {"mac_tx_128_255_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
293 {"mac_tx_256_511_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
295 {"mac_tx_512_1023_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
297 {"mac_tx_1024_1518_oct_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
91f384f6
JS		 299 {"mac_tx_1519_2047_oct_pkt_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
301 {"mac_tx_2048_4095_oct_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
303 {"mac_tx_4096_8191_oct_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
305 {"mac_tx_8192_12287_oct_pkt_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_12287_oct_pkt_num)},
307 {"mac_tx_8192_9216_oct_pkt_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
309 {"mac_tx_9217_12287_oct_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
311 {"mac_tx_12288_16383_oct_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
313 {"mac_tx_1519_max_good_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
315 {"mac_tx_1519_max_bad_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 317 {"mac_rx_total_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
319 {"mac_rx_total_oct_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
321 {"mac_rx_good_pkt_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
323 {"mac_rx_bad_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
325 {"mac_rx_good_oct_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
327 {"mac_rx_bad_oct_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
329 {"mac_rx_uni_pkt_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
331 {"mac_rx_multi_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
333 {"mac_rx_broad_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
335 {"mac_rx_undersize_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
200a88c6
JS		 337 {"mac_rx_oversize_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 339 {"mac_rx_64_oct_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
341 {"mac_rx_65_127_oct_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
343 {"mac_rx_128_255_oct_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
345 {"mac_rx_256_511_oct_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
347 {"mac_rx_512_1023_oct_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
349 {"mac_rx_1024_1518_oct_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
91f384f6
JS		 351 {"mac_rx_1519_2047_oct_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
353 {"mac_rx_2048_4095_oct_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
355 {"mac_rx_4096_8191_oct_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
357 {"mac_rx_8192_12287_oct_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_12287_oct_pkt_num)},
359 {"mac_rx_8192_9216_oct_pkt_num",
360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
361 {"mac_rx_9217_12287_oct_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
363 {"mac_rx_12288_16383_oct_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
365 {"mac_rx_1519_max_good_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
367 {"mac_rx_1519_max_bad_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 369
a6c51c26
JS		 370 {"mac_tx_fragment_pkt_num",
371 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
372 {"mac_tx_undermin_pkt_num",
373 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
374 {"mac_tx_jabber_pkt_num",
375 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
376 {"mac_tx_err_all_pkt_num",
377 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
378 {"mac_tx_from_app_good_pkt_num",
379 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
380 {"mac_tx_from_app_bad_pkt_num",
381 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
382 {"mac_rx_fragment_pkt_num",
383 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
384 {"mac_rx_undermin_pkt_num",
385 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
386 {"mac_rx_jabber_pkt_num",
387 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
388 {"mac_rx_fcs_err_pkt_num",
389 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
390 {"mac_rx_send_app_good_pkt_num",
391 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
392 {"mac_rx_send_app_bad_pkt_num",
393 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 394};
395
f5aac71c
FL		 396static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
397 {
398 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
399 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
400 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
401 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
402 .i_port_bitmap = 0x1,
403 },
404};
405
46a3df9f
S		 406static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
407{
408#define HCLGE_64_BIT_CMD_NUM 5
409#define HCLGE_64_BIT_RTN_DATANUM 4
410 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
411 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 412 __le64 *desc_data;
46a3df9f
S		 413 int i, k, n;
414 int ret;
415
416 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
417 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
418 if (ret) {
419 dev_err(&hdev->pdev->dev,
420 "Get 64 bit pkt stats fail, status = %d.\n", ret);
421 return ret;
422 }
423
424 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
425 if (unlikely(i == 0)) {
a90bb9a5 426 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 427 n = HCLGE_64_BIT_RTN_DATANUM - 1;
428 } else {
a90bb9a5 429 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 430 n = HCLGE_64_BIT_RTN_DATANUM;
431 }
432 for (k = 0; k < n; k++) {
a90bb9a5 433 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 434 desc_data++;
435 }
436 }
437
438 return 0;
439}
440
441static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
442{
443 stats->pkt_curr_buf_cnt = 0;
444 stats->pkt_curr_buf_tc0_cnt = 0;
445 stats->pkt_curr_buf_tc1_cnt = 0;
446 stats->pkt_curr_buf_tc2_cnt = 0;
447 stats->pkt_curr_buf_tc3_cnt = 0;
448 stats->pkt_curr_buf_tc4_cnt = 0;
449 stats->pkt_curr_buf_tc5_cnt = 0;
450 stats->pkt_curr_buf_tc6_cnt = 0;
451 stats->pkt_curr_buf_tc7_cnt = 0;
452}
453
454static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
455{
456#define HCLGE_32_BIT_CMD_NUM 8
457#define HCLGE_32_BIT_RTN_DATANUM 8
458
459 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
460 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 461 __le32 *desc_data;
46a3df9f
S		 462 int i, k, n;
463 u64 *data;
464 int ret;
465
466 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
467 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
468
469 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
470 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
471 if (ret) {
472 dev_err(&hdev->pdev->dev,
473 "Get 32 bit pkt stats fail, status = %d.\n", ret);
474
475 return ret;
476 }
477
478 hclge_reset_partial_32bit_counter(all_32_bit_stats);
479 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
480 if (unlikely(i == 0)) {
a90bb9a5
YL		 481 __le16 *desc_data_16bit;
482
46a3df9f 483 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 484 le32_to_cpu(desc[i].data[0]);
485
486 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 487 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 488 le16_to_cpu(*desc_data_16bit);
489
490 desc_data_16bit++;
46a3df9f 491 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 492 le16_to_cpu(*desc_data_16bit);
46a3df9f 493
a90bb9a5 494 desc_data = &desc[i].data[2];
46a3df9f
S		 495 n = HCLGE_32_BIT_RTN_DATANUM - 4;
496 } else {
a90bb9a5 497 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 498 n = HCLGE_32_BIT_RTN_DATANUM;
499 }
500 for (k = 0; k < n; k++) {
a90bb9a5 501 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 502 desc_data++;
503 }
504 }
505
506 return 0;
507}
508
716aaac1
JS		 509static int hclge_mac_get_traffic_stats(struct hclge_dev *hdev)
510{
511 struct hclge_mac_stats *mac_stats = &hdev->hw_stats.mac_stats;
512 struct hclge_desc desc;
513 __le64 *desc_data;
514 int ret;
515
516 /* for fiber port, need to query the total rx/tx packets statstics,
517 * used for data transferring checking.
518 */
519 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
520 return 0;
521
522 if (test_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
523 return 0;
524
525 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_STATS_MAC_TRAFFIC, true);
526 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
527 if (ret) {
528 dev_err(&hdev->pdev->dev,
529 "Get MAC total pkt stats fail, ret = %d\n", ret);
530
531 return ret;
532 }
533
534 desc_data = (__le64 *)(&desc.data[0]);
535 mac_stats->mac_tx_total_pkt_num += le64_to_cpu(*desc_data++);
536 mac_stats->mac_rx_total_pkt_num += le64_to_cpu(*desc_data);
537
538 return 0;
539}
540
46a3df9f
S		 541static int hclge_mac_update_stats(struct hclge_dev *hdev)
542{
91f384f6 543#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 544#define HCLGE_RTN_DATA_NUM 4
545
546 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
547 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 548 __le64 *desc_data;
46a3df9f
S		 549 int i, k, n;
550 int ret;
551
552 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
553 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
554 if (ret) {
555 dev_err(&hdev->pdev->dev,
556 "Get MAC pkt stats fail, status = %d.\n", ret);
557
558 return ret;
559 }
560
561 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
562 if (unlikely(i == 0)) {
a90bb9a5 563 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 564 n = HCLGE_RTN_DATA_NUM - 2;
565 } else {
a90bb9a5 566 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 567 n = HCLGE_RTN_DATA_NUM;
568 }
569 for (k = 0; k < n; k++) {
a90bb9a5 570 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 571 desc_data++;
572 }
573 }
574
575 return 0;
576}
577
578static int hclge_tqps_update_stats(struct hnae3_handle *handle)
579{
580 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
581 struct hclge_vport *vport = hclge_get_vport(handle);
582 struct hclge_dev *hdev = vport->back;
583 struct hnae3_queue *queue;
584 struct hclge_desc desc[1];
585 struct hclge_tqp *tqp;
586 int ret, i;
587
588 for (i = 0; i < kinfo->num_tqps; i++) {
589 queue = handle->kinfo.tqp[i];
590 tqp = container_of(queue, struct hclge_tqp, q);
591 /* command : HCLGE_OPC_QUERY_IGU_STAT */
592 hclge_cmd_setup_basic_desc(&desc[0],
593 HCLGE_OPC_QUERY_RX_STATUS,
594 true);
595
a90bb9a5 596 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 597 ret = hclge_cmd_send(&hdev->hw, desc, 1);
598 if (ret) {
599 dev_err(&hdev->pdev->dev,
600 "Query tqp stat fail, status = %d,queue = %d\n",
601 ret, i);
602 return ret;
603 }
604 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
cf72fa63 605 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 606 }
607
608 for (i = 0; i < kinfo->num_tqps; i++) {
609 queue = handle->kinfo.tqp[i];
610 tqp = container_of(queue, struct hclge_tqp, q);
611 /* command : HCLGE_OPC_QUERY_IGU_STAT */
612 hclge_cmd_setup_basic_desc(&desc[0],
613 HCLGE_OPC_QUERY_TX_STATUS,
614 true);
615
a90bb9a5 616 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 617 ret = hclge_cmd_send(&hdev->hw, desc, 1);
618 if (ret) {
619 dev_err(&hdev->pdev->dev,
620 "Query tqp stat fail, status = %d,queue = %d\n",
621 ret, i);
622 return ret;
623 }
624 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
cf72fa63 625 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 626 }
627
628 return 0;
629}
630
631static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
632{
633 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
634 struct hclge_tqp *tqp;
635 u64 *buff = data;
636 int i;
637
638 for (i = 0; i < kinfo->num_tqps; i++) {
639 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 640 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 641 }
642
643 for (i = 0; i < kinfo->num_tqps; i++) {
644 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 645 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 646 }
647
648 return buff;
649}
650
651static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
652{
653 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
654
655 return kinfo->num_tqps * (2);
656}
657
658static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
659{
660 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
661 u8 *buff = data;
662 int i = 0;
663
664 for (i = 0; i < kinfo->num_tqps; i++) {
665 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
666 struct hclge_tqp, q);
a6c51c26 667 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
46a3df9f
S		 668 tqp->index);
669 buff = buff + ETH_GSTRING_LEN;
670 }
671
672 for (i = 0; i < kinfo->num_tqps; i++) {
673 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
674 struct hclge_tqp, q);
a6c51c26 675 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
46a3df9f
S		 676 tqp->index);
677 buff = buff + ETH_GSTRING_LEN;
678 }
679
680 return buff;
681}
682
683static u64 *hclge_comm_get_stats(void *comm_stats,
684 const struct hclge_comm_stats_str strs[],
685 int size, u64 *data)
686{
687 u64 *buf = data;
688 u32 i;
689
690 for (i = 0; i < size; i++)
691 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
692
693 return buf + size;
694}
695
696static u8 *hclge_comm_get_strings(u32 stringset,
697 const struct hclge_comm_stats_str strs[],
698 int size, u8 *data)
699{
700 char *buff = (char *)data;
701 u32 i;
702
703 if (stringset != ETH_SS_STATS)
704 return buff;
705
706 for (i = 0; i < size; i++) {
707 snprintf(buff, ETH_GSTRING_LEN,
708 strs[i].desc);
709 buff = buff + ETH_GSTRING_LEN;
710 }
711
712 return (u8 *)buff;
713}
714
715static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
716 struct net_device_stats *net_stats)
717{
718 net_stats->tx_dropped = 0;
719 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
720 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
721 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
722
200a88c6 723 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 724 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
46a3df9f
S		 725 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
726 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
a6c51c26 727 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 728
729 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
730 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
731
a6c51c26 732 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 733 net_stats->rx_length_errors =
734 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
735 net_stats->rx_length_errors +=
200a88c6 736 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 737 net_stats->rx_over_errors =
200a88c6 738 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 739}
740
741static void hclge_update_stats_for_all(struct hclge_dev *hdev)
742{
743 struct hnae3_handle *handle;
744 int status;
745
746 handle = &hdev->vport[0].nic;
747 if (handle->client) {
748 status = hclge_tqps_update_stats(handle);
749 if (status) {
750 dev_err(&hdev->pdev->dev,
751 "Update TQPS stats fail, status = %d.\n",
752 status);
753 }
754 }
755
756 status = hclge_mac_update_stats(hdev);
757 if (status)
758 dev_err(&hdev->pdev->dev,
759 "Update MAC stats fail, status = %d.\n", status);
760
761 status = hclge_32_bit_update_stats(hdev);
762 if (status)
763 dev_err(&hdev->pdev->dev,
764 "Update 32 bit stats fail, status = %d.\n",
765 status);
766
767 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
768}
769
770static void hclge_update_stats(struct hnae3_handle *handle,
771 struct net_device_stats *net_stats)
772{
773 struct hclge_vport *vport = hclge_get_vport(handle);
774 struct hclge_dev *hdev = vport->back;
775 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
776 int status;
777
c5f65480
JS		 778 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
779 return;
780
46a3df9f
S		 781 status = hclge_mac_update_stats(hdev);
782 if (status)
783 dev_err(&hdev->pdev->dev,
784 "Update MAC stats fail, status = %d.\n",
785 status);
786
787 status = hclge_32_bit_update_stats(hdev);
788 if (status)
789 dev_err(&hdev->pdev->dev,
790 "Update 32 bit stats fail, status = %d.\n",
791 status);
792
793 status = hclge_64_bit_update_stats(hdev);
794 if (status)
795 dev_err(&hdev->pdev->dev,
796 "Update 64 bit stats fail, status = %d.\n",
797 status);
798
799 status = hclge_tqps_update_stats(handle);
800 if (status)
801 dev_err(&hdev->pdev->dev,
802 "Update TQPS stats fail, status = %d.\n",
803 status);
804
805 hclge_update_netstat(hw_stats, net_stats);
c5f65480
JS		 806
807 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 808}
809
810static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
811{
812#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
813
814 struct hclge_vport *vport = hclge_get_vport(handle);
815 struct hclge_dev *hdev = vport->back;
816 int count = 0;
817
818 /* Loopback test support rules:
819 * mac: only GE mode support
820 * serdes: all mac mode will support include GE/XGE/LGE/CGE
821 * phy: only support when phy device exist on board
822 */
823 if (stringset == ETH_SS_TEST) {
824 /* clear loopback bit flags at first */
825 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
826 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
827 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
828 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
829 count += 1;
830 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
831 } else {
832 count = -EOPNOTSUPP;
833 }
834 } else if (stringset == ETH_SS_STATS) {
835 count = ARRAY_SIZE(g_mac_stats_string) +
836 ARRAY_SIZE(g_all_32bit_stats_string) +
837 ARRAY_SIZE(g_all_64bit_stats_string) +
838 hclge_tqps_get_sset_count(handle, stringset);
839 }
840
841 return count;
842}
843
844static void hclge_get_strings(struct hnae3_handle *handle,
845 u32 stringset,
846 u8 *data)
847{
848 u8 *p = (char *)data;
849 int size;
850
851 if (stringset == ETH_SS_STATS) {
852 size = ARRAY_SIZE(g_mac_stats_string);
853 p = hclge_comm_get_strings(stringset,
854 g_mac_stats_string,
855 size,
856 p);
857 size = ARRAY_SIZE(g_all_32bit_stats_string);
858 p = hclge_comm_get_strings(stringset,
859 g_all_32bit_stats_string,
860 size,
861 p);
862 size = ARRAY_SIZE(g_all_64bit_stats_string);
863 p = hclge_comm_get_strings(stringset,
864 g_all_64bit_stats_string,
865 size,
866 p);
867 p = hclge_tqps_get_strings(handle, p);
868 } else if (stringset == ETH_SS_TEST) {
869 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
870 memcpy(p,
871 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
872 ETH_GSTRING_LEN);
873 p += ETH_GSTRING_LEN;
874 }
875 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
876 memcpy(p,
877 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
878 ETH_GSTRING_LEN);
879 p += ETH_GSTRING_LEN;
880 }
881 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
882 memcpy(p,
883 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
884 ETH_GSTRING_LEN);
885 p += ETH_GSTRING_LEN;
886 }
887 }
888}
889
890static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
891{
892 struct hclge_vport *vport = hclge_get_vport(handle);
893 struct hclge_dev *hdev = vport->back;
894 u64 *p;
895
896 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
897 g_mac_stats_string,
898 ARRAY_SIZE(g_mac_stats_string),
899 data);
900 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
901 g_all_32bit_stats_string,
902 ARRAY_SIZE(g_all_32bit_stats_string),
903 p);
904 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
905 g_all_64bit_stats_string,
906 ARRAY_SIZE(g_all_64bit_stats_string),
907 p);
908 p = hclge_tqps_get_stats(handle, p);
909}
910
911static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 912 struct hclge_func_status_cmd *status)
46a3df9f
S		 913{
914 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
915 return -EINVAL;
916
917 /* Set the pf to main pf */
918 if (status->pf_state & HCLGE_PF_STATE_MAIN)
919 hdev->flag |= HCLGE_FLAG_MAIN;
920 else
921 hdev->flag &= ~HCLGE_FLAG_MAIN;
922
46a3df9f
S		 923 return 0;
924}
925
926static int hclge_query_function_status(struct hclge_dev *hdev)
927{
d44f9b63 928 struct hclge_func_status_cmd *req;
46a3df9f
S		 929 struct hclge_desc desc;
930 int timeout = 0;
931 int ret;
932
933 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 934 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 935
936 do {
937 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
938 if (ret) {
939 dev_err(&hdev->pdev->dev,
940 "query function status failed %d.\n",
941 ret);
942
943 return ret;
944 }
945
946 /* Check pf reset is done */
947 if (req->pf_state)
948 break;
949 usleep_range(1000, 2000);
950 } while (timeout++ < 5);
951
952 ret = hclge_parse_func_status(hdev, req);
953
954 return ret;
955}
956
957static int hclge_query_pf_resource(struct hclge_dev *hdev)
958{
d44f9b63 959 struct hclge_pf_res_cmd *req;
46a3df9f
S		 960 struct hclge_desc desc;
961 int ret;
962
963 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
964 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
965 if (ret) {
966 dev_err(&hdev->pdev->dev,
967 "query pf resource failed %d.\n", ret);
968 return ret;
969 }
970
d44f9b63 971 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 972 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
973 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
974
e92a0843 975 if (hnae3_dev_roce_supported(hdev)) {
887c3820 976 hdev->num_roce_msi =
46a3df9f
S		 977 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
978 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
979
980 /* PF should have NIC vectors and Roce vectors,
981 * NIC vectors are queued before Roce vectors.
982 */
887c3820 983 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 984 } else {
985 hdev->num_msi =
986 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
987 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
988 }
989
990 return 0;
991}
992
993static int hclge_parse_speed(int speed_cmd, int *speed)
994{
995 switch (speed_cmd) {
996 case 6:
997 *speed = HCLGE_MAC_SPEED_10M;
998 break;
999 case 7:
1000 *speed = HCLGE_MAC_SPEED_100M;
1001 break;
1002 case 0:
1003 *speed = HCLGE_MAC_SPEED_1G;
1004 break;
1005 case 1:
1006 *speed = HCLGE_MAC_SPEED_10G;
1007 break;
1008 case 2:
1009 *speed = HCLGE_MAC_SPEED_25G;
1010 break;
1011 case 3:
1012 *speed = HCLGE_MAC_SPEED_40G;
1013 break;
1014 case 4:
1015 *speed = HCLGE_MAC_SPEED_50G;
1016 break;
1017 case 5:
1018 *speed = HCLGE_MAC_SPEED_100G;
1019 break;
1020 default:
1021 return -EINVAL;
1022 }
1023
1024 return 0;
1025}
1026
1027static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1028{
d44f9b63 1029 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1030 u64 mac_addr_tmp_high;
1031 u64 mac_addr_tmp;
1032 int i;
1033
d44f9b63 1034 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 1035
1036 /* get the configuration */
1037 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1038 HCLGE_CFG_VMDQ_M,
1039 HCLGE_CFG_VMDQ_S);
1040 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1041 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1042 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
1043 HCLGE_CFG_TQP_DESC_N_M,
1044 HCLGE_CFG_TQP_DESC_N_S);
1045
1046 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
1047 HCLGE_CFG_PHY_ADDR_M,
1048 HCLGE_CFG_PHY_ADDR_S);
1049 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
1050 HCLGE_CFG_MEDIA_TP_M,
1051 HCLGE_CFG_MEDIA_TP_S);
1052 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
1053 HCLGE_CFG_RX_BUF_LEN_M,
1054 HCLGE_CFG_RX_BUF_LEN_S);
1055 /* get mac_address */
1056 mac_addr_tmp = __le32_to_cpu(req->param[2]);
1057 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
1058 HCLGE_CFG_MAC_ADDR_H_M,
1059 HCLGE_CFG_MAC_ADDR_H_S);
1060
1061 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1062
1063 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
1064 HCLGE_CFG_DEFAULT_SPEED_M,
1065 HCLGE_CFG_DEFAULT_SPEED_S);
0e7a40cd
PL		 1066 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]),
1067 HCLGE_CFG_RSS_SIZE_M,
1068 HCLGE_CFG_RSS_SIZE_S);
1069
46a3df9f
S		 1070 for (i = 0; i < ETH_ALEN; i++)
1071 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1072
d44f9b63 1073 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f
S		 1074 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1075}
1076
1077/* hclge_get_cfg: query the static parameter from flash
1078 * @hdev: pointer to struct hclge_dev
1079 * @hcfg: the config structure to be getted
1080 */
1081static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1082{
1083 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 1084 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 1085 int i, ret;
1086
1087 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1088 u32 offset = 0;
1089
d44f9b63 1090 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1091 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1092 true);
a90bb9a5 1093 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
46a3df9f
S		 1094 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1095 /* Len should be united by 4 bytes when send to hardware */
a90bb9a5 1096 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
46a3df9f 1097 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1098 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1099 }
1100
1101 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1102 if (ret) {
1103 dev_err(&hdev->pdev->dev,
1104 "get config failed %d.\n", ret);
1105 return ret;
1106 }
1107
1108 hclge_parse_cfg(hcfg, desc);
1109 return 0;
1110}
1111
1112static int hclge_get_cap(struct hclge_dev *hdev)
1113{
1114 int ret;
1115
1116 ret = hclge_query_function_status(hdev);
1117 if (ret) {
1118 dev_err(&hdev->pdev->dev,
1119 "query function status error %d.\n", ret);
1120 return ret;
1121 }
1122
1123 /* get pf resource */
1124 ret = hclge_query_pf_resource(hdev);
1125 if (ret) {
1126 dev_err(&hdev->pdev->dev,
1127 "query pf resource error %d.\n", ret);
1128 return ret;
1129 }
1130
1131 return 0;
1132}
1133
1134static int hclge_configure(struct hclge_dev *hdev)
1135{
1136 struct hclge_cfg cfg;
1137 int ret, i;
1138
1139 ret = hclge_get_cfg(hdev, &cfg);
1140 if (ret) {
1141 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1142 return ret;
1143 }
1144
1145 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1146 hdev->base_tqp_pid = 0;
0e7a40cd 1147 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 1148 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1149 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1150 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1151 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1152 hdev->num_desc = cfg.tqp_desc_num;
1153 hdev->tm_info.num_pg = 1;
cacde272 1154 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1155 hdev->tm_info.hw_pfc_map = 0;
1156
1157 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1158 if (ret) {
1159 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1160 return ret;
1161 }
1162
cacde272
YL		 1163 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1164 (hdev->tc_max < 1)) {
46a3df9f 1165 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1166 hdev->tc_max);
1167 hdev->tc_max = 1;
46a3df9f
S		 1168 }
1169
cacde272
YL		 1170 /* Dev does not support DCB */
1171 if (!hnae3_dev_dcb_supported(hdev)) {
1172 hdev->tc_max = 1;
1173 hdev->pfc_max = 0;
1174 } else {
1175 hdev->pfc_max = hdev->tc_max;
1176 }
1177
1178 hdev->tm_info.num_tc = hdev->tc_max;
1179
46a3df9f 1180 /* Currently not support uncontiuous tc */
cacde272 1181 for (i = 0; i < hdev->tm_info.num_tc; i++)
46a3df9f
S		 1182 hnae_set_bit(hdev->hw_tc_map, i, 1);
1183
71b83869 1184 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 1185
1186 return ret;
1187}
1188
1189static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1190 int tso_mss_max)
1191{
d44f9b63 1192 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1193 struct hclge_desc desc;
a90bb9a5 1194 u16 tso_mss;
46a3df9f
S		 1195
1196 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1197
d44f9b63 1198 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1199
1200 tso_mss = 0;
1201 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1202 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1203 req->tso_mss_min = cpu_to_le16(tso_mss);
1204
1205 tso_mss = 0;
1206 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1207 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1208 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1209
1210 return hclge_cmd_send(&hdev->hw, &desc, 1);
1211}
1212
1213static int hclge_alloc_tqps(struct hclge_dev *hdev)
1214{
1215 struct hclge_tqp *tqp;
1216 int i;
1217
1218 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1219 sizeof(struct hclge_tqp), GFP_KERNEL);
1220 if (!hdev->htqp)
1221 return -ENOMEM;
1222
1223 tqp = hdev->htqp;
1224
1225 for (i = 0; i < hdev->num_tqps; i++) {
1226 tqp->dev = &hdev->pdev->dev;
1227 tqp->index = i;
1228
1229 tqp->q.ae_algo = &ae_algo;
1230 tqp->q.buf_size = hdev->rx_buf_len;
1231 tqp->q.desc_num = hdev->num_desc;
1232 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1233 i * HCLGE_TQP_REG_SIZE;
1234
1235 tqp++;
1236 }
1237
1238 return 0;
1239}
1240
1241static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1242 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1243{
d44f9b63 1244 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1245 struct hclge_desc desc;
1246 int ret;
1247
1248 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1249
d44f9b63 1250 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1251 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1252 req->tqp_vf = func_id;
46a3df9f
S		 1253 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1254 1 << HCLGE_TQP_MAP_EN_B;
1255 req->tqp_vid = cpu_to_le16(tqp_vid);
1256
1257 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1258 if (ret) {
1259 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1260 ret);
1261 return ret;
1262 }
1263
1264 return 0;
1265}
1266
1267static int hclge_assign_tqp(struct hclge_vport *vport,
1268 struct hnae3_queue **tqp, u16 num_tqps)
1269{
1270 struct hclge_dev *hdev = vport->back;
7df7dad6 1271 int i, alloced;
46a3df9f
S		 1272
1273 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1274 alloced < num_tqps; i++) {
1275 if (!hdev->htqp[i].alloced) {
1276 hdev->htqp[i].q.handle = &vport->nic;
1277 hdev->htqp[i].q.tqp_index = alloced;
1278 tqp[alloced] = &hdev->htqp[i].q;
1279 hdev->htqp[i].alloced = true;
46a3df9f
S		 1280 alloced++;
1281 }
1282 }
1283 vport->alloc_tqps = num_tqps;
1284
1285 return 0;
1286}
1287
1288static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1289{
1290 struct hnae3_handle *nic = &vport->nic;
1291 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1292 struct hclge_dev *hdev = vport->back;
1293 int i, ret;
1294
1295 kinfo->num_desc = hdev->num_desc;
1296 kinfo->rx_buf_len = hdev->rx_buf_len;
1297 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1298 kinfo->rss_size
1299 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1300 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1301
1302 for (i = 0; i < HNAE3_MAX_TC; i++) {
1303 if (hdev->hw_tc_map & BIT(i)) {
1304 kinfo->tc_info[i].enable = true;
1305 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1306 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1307 kinfo->tc_info[i].tc = i;
1308 } else {
1309 /* Set to default queue if TC is disable */
1310 kinfo->tc_info[i].enable = false;
1311 kinfo->tc_info[i].tqp_offset = 0;
1312 kinfo->tc_info[i].tqp_count = 1;
1313 kinfo->tc_info[i].tc = 0;
1314 }
1315 }
1316
1317 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1318 sizeof(struct hnae3_queue *), GFP_KERNEL);
1319 if (!kinfo->tqp)
1320 return -ENOMEM;
1321
1322 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1323 if (ret) {
1324 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1325 return -EINVAL;
1326 }
1327
1328 return 0;
1329}
1330
7df7dad6
L		 1331static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1332 struct hclge_vport *vport)
1333{
1334 struct hnae3_handle *nic = &vport->nic;
1335 struct hnae3_knic_private_info *kinfo;
1336 u16 i;
1337
1338 kinfo = &nic->kinfo;
1339 for (i = 0; i < kinfo->num_tqps; i++) {
1340 struct hclge_tqp *q =
1341 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1342 bool is_pf;
1343 int ret;
1344
1345 is_pf = !(vport->vport_id);
1346 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1347 i, is_pf);
1348 if (ret)
1349 return ret;
1350 }
1351
1352 return 0;
1353}
1354
1355static int hclge_map_tqp(struct hclge_dev *hdev)
1356{
1357 struct hclge_vport *vport = hdev->vport;
1358 u16 i, num_vport;
1359
1360 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1361 for (i = 0; i < num_vport; i++) {
1362 int ret;
1363
1364 ret = hclge_map_tqp_to_vport(hdev, vport);
1365 if (ret)
1366 return ret;
1367
1368 vport++;
1369 }
1370
1371 return 0;
1372}
1373
46a3df9f
S		 1374static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1375{
1376 /* this would be initialized later */
1377}
1378
1379static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1380{
1381 struct hnae3_handle *nic = &vport->nic;
1382 struct hclge_dev *hdev = vport->back;
1383 int ret;
1384
1385 nic->pdev = hdev->pdev;
1386 nic->ae_algo = &ae_algo;
1387 nic->numa_node_mask = hdev->numa_node_mask;
1388
1389 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1390 ret = hclge_knic_setup(vport, num_tqps);
1391 if (ret) {
1392 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1393 ret);
1394 return ret;
1395 }
1396 } else {
1397 hclge_unic_setup(vport, num_tqps);
1398 }
1399
1400 return 0;
1401}
1402
1403static int hclge_alloc_vport(struct hclge_dev *hdev)
1404{
1405 struct pci_dev *pdev = hdev->pdev;
1406 struct hclge_vport *vport;
1407 u32 tqp_main_vport;
1408 u32 tqp_per_vport;
1409 int num_vport, i;
1410 int ret;
1411
1412 /* We need to alloc a vport for main NIC of PF */
1413 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1414
1415 if (hdev->num_tqps < num_vport)
1416 num_vport = hdev->num_tqps;
1417
1418 /* Alloc the same number of TQPs for every vport */
1419 tqp_per_vport = hdev->num_tqps / num_vport;
1420 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1421
1422 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1423 GFP_KERNEL);
1424 if (!vport)
1425 return -ENOMEM;
1426
1427 hdev->vport = vport;
1428 hdev->num_alloc_vport = num_vport;
1429
1430#ifdef CONFIG_PCI_IOV
1431 /* Enable SRIOV */
1432 if (hdev->num_req_vfs) {
1433 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1434 hdev->num_req_vfs);
1435 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1436 if (ret) {
1437 hdev->num_alloc_vfs = 0;
1438 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1439 ret);
1440 return ret;
1441 }
1442 }
1443 hdev->num_alloc_vfs = hdev->num_req_vfs;
1444#endif
1445
1446 for (i = 0; i < num_vport; i++) {
1447 vport->back = hdev;
1448 vport->vport_id = i;
1449
1450 if (i == 0)
1451 ret = hclge_vport_setup(vport, tqp_main_vport);
1452 else
1453 ret = hclge_vport_setup(vport, tqp_per_vport);
1454 if (ret) {
1455 dev_err(&pdev->dev,
1456 "vport setup failed for vport %d, %d\n",
1457 i, ret);
1458 return ret;
1459 }
1460
1461 vport++;
1462 }
1463
1464 return 0;
1465}
1466
acf61ecd
YL		 1467static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1468 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1469{
1470/* TX buffer size is unit by 128 byte */
1471#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1472#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1473 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1474 struct hclge_desc desc;
1475 int ret;
1476 u8 i;
1477
d44f9b63 1478 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1479
1480 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1481 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1482 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1483
46a3df9f
S		 1484 req->tx_pkt_buff[i] =
1485 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1486 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1487 }
46a3df9f
S		 1488
1489 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1490 if (ret) {
1491 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1492 ret);
1493 return ret;
1494 }
1495
1496 return 0;
1497}
1498
acf61ecd
YL		 1499static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1500 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1501{
acf61ecd 1502 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1503
1504 if (ret) {
1505 dev_err(&hdev->pdev->dev,
1506 "tx buffer alloc failed %d\n", ret);
1507 return ret;
1508 }
1509
1510 return 0;
1511}
1512
1513static int hclge_get_tc_num(struct hclge_dev *hdev)
1514{
1515 int i, cnt = 0;
1516
1517 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1518 if (hdev->hw_tc_map & BIT(i))
1519 cnt++;
1520 return cnt;
1521}
1522
1523static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1524{
1525 int i, cnt = 0;
1526
1527 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1528 if (hdev->hw_tc_map & BIT(i) &&
1529 hdev->tm_info.hw_pfc_map & BIT(i))
1530 cnt++;
1531 return cnt;
1532}
1533
1534/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1535static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1536 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1537{
1538 struct hclge_priv_buf *priv;
1539 int i, cnt = 0;
1540
1541 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1542 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1543 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1544 priv->enable)
1545 cnt++;
1546 }
1547
1548 return cnt;
1549}
1550
1551/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1552static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1553 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1554{
1555 struct hclge_priv_buf *priv;
1556 int i, cnt = 0;
1557
1558 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1559 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1560 if (hdev->hw_tc_map & BIT(i) &&
1561 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1562 priv->enable)
1563 cnt++;
1564 }
1565
1566 return cnt;
1567}
1568
acf61ecd 1569static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1570{
1571 struct hclge_priv_buf *priv;
1572 u32 rx_priv = 0;
1573 int i;
1574
1575 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1576 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1577 if (priv->enable)
1578 rx_priv += priv->buf_size;
1579 }
1580 return rx_priv;
1581}
1582
acf61ecd 1583static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1584{
1585 u32 i, total_tx_size = 0;
1586
1587 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1588 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1589
1590 return total_tx_size;
1591}
1592
acf61ecd
YL		 1593static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1594 struct hclge_pkt_buf_alloc *buf_alloc,
1595 u32 rx_all)
46a3df9f
S		 1596{
1597 u32 shared_buf_min, shared_buf_tc, shared_std;
1598 int tc_num, pfc_enable_num;
1599 u32 shared_buf;
1600 u32 rx_priv;
1601 int i;
1602
1603 tc_num = hclge_get_tc_num(hdev);
1604 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1605
d221df4e
YL		 1606 if (hnae3_dev_dcb_supported(hdev))
1607 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1608 else
1609 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1610
46a3df9f
S		 1611 shared_buf_tc = pfc_enable_num * hdev->mps +
1612 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1613 hdev->mps;
1614 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1615
acf61ecd 1616 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1617 if (rx_all <= rx_priv + shared_std)
1618 return false;
1619
1620 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1621 buf_alloc->s_buf.buf_size = shared_buf;
1622 buf_alloc->s_buf.self.high = shared_buf;
1623 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1624
1625 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1626 if ((hdev->hw_tc_map & BIT(i)) &&
1627 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1628 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1629 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1630 } else {
acf61ecd
YL		 1631 buf_alloc->s_buf.tc_thrd[i].low = 0;
1632 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1633 }
1634 }
1635
1636 return true;
1637}
1638
acf61ecd
YL		 1639static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1640 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1641{
1642 u32 i, total_size;
1643
1644 total_size = hdev->pkt_buf_size;
1645
1646 /* alloc tx buffer for all enabled tc */
1647 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1648 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1649
1650 if (total_size < HCLGE_DEFAULT_TX_BUF)
1651 return -ENOMEM;
1652
1653 if (hdev->hw_tc_map & BIT(i))
1654 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1655 else
1656 priv->tx_buf_size = 0;
1657
1658 total_size -= priv->tx_buf_size;
1659 }
1660
1661 return 0;
1662}
1663
46a3df9f
S		 1664/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1665 * @hdev: pointer to struct hclge_dev
acf61ecd 1666 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1667 * @return: 0: calculate sucessful, negative: fail
1668 */
1db9b1bf
YL		 1669static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1670 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1671{
9ffe79a9 1672 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1673 int no_pfc_priv_num, pfc_priv_num;
1674 struct hclge_priv_buf *priv;
1675 int i;
1676
acf61ecd 1677 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1678
d602a525
YL		 1679 /* When DCB is not supported, rx private
1680 * buffer is not allocated.
1681 */
1682 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1683 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1684 return -ENOMEM;
1685
1686 return 0;
1687 }
1688
46a3df9f
S		 1689 /* step 1, try to alloc private buffer for all enabled tc */
1690 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1691 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1692 if (hdev->hw_tc_map & BIT(i)) {
1693 priv->enable = 1;
1694 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1695 priv->wl.low = hdev->mps;
1696 priv->wl.high = priv->wl.low + hdev->mps;
1697 priv->buf_size = priv->wl.high +
1698 HCLGE_DEFAULT_DV;
1699 } else {
1700 priv->wl.low = 0;
1701 priv->wl.high = 2 * hdev->mps;
1702 priv->buf_size = priv->wl.high;
1703 }
bb1fe9ea
YL		 1704 } else {
1705 priv->enable = 0;
1706 priv->wl.low = 0;
1707 priv->wl.high = 0;
1708 priv->buf_size = 0;
46a3df9f
S		 1709 }
1710 }
1711
acf61ecd 1712 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1713 return 0;
1714
1715 /* step 2, try to decrease the buffer size of
1716 * no pfc TC's private buffer
1717 */
1718 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1719 priv = &buf_alloc->priv_buf[i];
46a3df9f 1720
bb1fe9ea
YL		 1721 priv->enable = 0;
1722 priv->wl.low = 0;
1723 priv->wl.high = 0;
1724 priv->buf_size = 0;
1725
1726 if (!(hdev->hw_tc_map & BIT(i)))
1727 continue;
1728
1729 priv->enable = 1;
46a3df9f
S		 1730
1731 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1732 priv->wl.low = 128;
1733 priv->wl.high = priv->wl.low + hdev->mps;
1734 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1735 } else {
1736 priv->wl.low = 0;
1737 priv->wl.high = hdev->mps;
1738 priv->buf_size = priv->wl.high;
1739 }
1740 }
1741
acf61ecd 1742 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1743 return 0;
1744
1745 /* step 3, try to reduce the number of pfc disabled TCs,
1746 * which have private buffer
1747 */
1748 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1749 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1750
1751 /* let the last to be cleared first */
1752 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1753 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1754
1755 if (hdev->hw_tc_map & BIT(i) &&
1756 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1757 /* Clear the no pfc TC private buffer */
1758 priv->wl.low = 0;
1759 priv->wl.high = 0;
1760 priv->buf_size = 0;
1761 priv->enable = 0;
1762 no_pfc_priv_num--;
1763 }
1764
acf61ecd 1765 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1766 no_pfc_priv_num == 0)
1767 break;
1768 }
1769
acf61ecd 1770 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1771 return 0;
1772
1773 /* step 4, try to reduce the number of pfc enabled TCs
1774 * which have private buffer.
1775 */
acf61ecd 1776 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1777
1778 /* let the last to be cleared first */
1779 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1780 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1781
1782 if (hdev->hw_tc_map & BIT(i) &&
1783 hdev->tm_info.hw_pfc_map & BIT(i)) {
1784 /* Reduce the number of pfc TC with private buffer */
1785 priv->wl.low = 0;
1786 priv->enable = 0;
1787 priv->wl.high = 0;
1788 priv->buf_size = 0;
1789 pfc_priv_num--;
1790 }
1791
acf61ecd 1792 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1793 pfc_priv_num == 0)
1794 break;
1795 }
acf61ecd 1796 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1797 return 0;
1798
1799 return -ENOMEM;
1800}
1801
acf61ecd
YL		 1802static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1803 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1804{
d44f9b63 1805 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1806 struct hclge_desc desc;
1807 int ret;
1808 int i;
1809
1810 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1811 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1812
1813 /* Alloc private buffer TCs */
1814 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1815 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1816
1817 req->buf_num[i] =
1818 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1819 req->buf_num[i] |=
5bca3b94 1820 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1821 }
1822
b8c8bf47 1823 req->shared_buf =
acf61ecd 1824 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1825 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1826
46a3df9f
S		 1827 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1828 if (ret) {
1829 dev_err(&hdev->pdev->dev,
1830 "rx private buffer alloc cmd failed %d\n", ret);
1831 return ret;
1832 }
1833
1834 return 0;
1835}
1836
1837#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1838
acf61ecd
YL		 1839static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1840 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1841{
1842 struct hclge_rx_priv_wl_buf *req;
1843 struct hclge_priv_buf *priv;
1844 struct hclge_desc desc[2];
1845 int i, j;
1846 int ret;
1847
1848 for (i = 0; i < 2; i++) {
1849 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1850 false);
1851 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1852
1853 /* The first descriptor set the NEXT bit to 1 */
1854 if (i == 0)
1855 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1856 else
1857 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1858
1859 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1860 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1861
1862 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1863 req->tc_wl[j].high =
1864 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1865 req->tc_wl[j].high |=
1866 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1867 HCLGE_RX_PRIV_EN_B);
1868 req->tc_wl[j].low =
1869 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1870 req->tc_wl[j].low |=
1871 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1872 HCLGE_RX_PRIV_EN_B);
1873 }
1874 }
1875
1876 /* Send 2 descriptor at one time */
1877 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1878 if (ret) {
1879 dev_err(&hdev->pdev->dev,
1880 "rx private waterline config cmd failed %d\n",
1881 ret);
1882 return ret;
1883 }
1884 return 0;
1885}
1886
acf61ecd
YL		 1887static int hclge_common_thrd_config(struct hclge_dev *hdev,
1888 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1889{
acf61ecd 1890 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1891 struct hclge_rx_com_thrd *req;
1892 struct hclge_desc desc[2];
1893 struct hclge_tc_thrd *tc;
1894 int i, j;
1895 int ret;
1896
1897 for (i = 0; i < 2; i++) {
1898 hclge_cmd_setup_basic_desc(&desc[i],
1899 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1900 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1901
1902 /* The first descriptor set the NEXT bit to 1 */
1903 if (i == 0)
1904 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1905 else
1906 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1907
1908 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1909 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1910
1911 req->com_thrd[j].high =
1912 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1913 req->com_thrd[j].high |=
1914 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1915 HCLGE_RX_PRIV_EN_B);
1916 req->com_thrd[j].low =
1917 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1918 req->com_thrd[j].low |=
1919 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1920 HCLGE_RX_PRIV_EN_B);
1921 }
1922 }
1923
1924 /* Send 2 descriptors at one time */
1925 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1926 if (ret) {
1927 dev_err(&hdev->pdev->dev,
1928 "common threshold config cmd failed %d\n", ret);
1929 return ret;
1930 }
1931 return 0;
1932}
1933
acf61ecd
YL		 1934static int hclge_common_wl_config(struct hclge_dev *hdev,
1935 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1936{
acf61ecd 1937 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1938 struct hclge_rx_com_wl *req;
1939 struct hclge_desc desc;
1940 int ret;
1941
1942 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1943
1944 req = (struct hclge_rx_com_wl *)desc.data;
1945 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1946 req->com_wl.high |=
1947 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1948 HCLGE_RX_PRIV_EN_B);
1949
1950 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1951 req->com_wl.low |=
1952 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1953 HCLGE_RX_PRIV_EN_B);
1954
1955 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1956 if (ret) {
1957 dev_err(&hdev->pdev->dev,
1958 "common waterline config cmd failed %d\n", ret);
1959 return ret;
1960 }
1961
1962 return 0;
1963}
1964
1965int hclge_buffer_alloc(struct hclge_dev *hdev)
1966{
acf61ecd 1967 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1968 int ret;
1969
acf61ecd
YL		 1970 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1971 if (!pkt_buf)
46a3df9f
S		 1972 return -ENOMEM;
1973
acf61ecd 1974 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1975 if (ret) {
1976 dev_err(&hdev->pdev->dev,
1977 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1978 goto out;
9ffe79a9
YL		 1979 }
1980
acf61ecd 1981 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1982 if (ret) {
1983 dev_err(&hdev->pdev->dev,
1984 "could not alloc tx buffers %d\n", ret);
acf61ecd 1985 goto out;
46a3df9f
S		 1986 }
1987
acf61ecd 1988 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1989 if (ret) {
1990 dev_err(&hdev->pdev->dev,
1991 "could not calc rx priv buffer size for all TCs %d\n",
1992 ret);
acf61ecd 1993 goto out;
46a3df9f
S		 1994 }
1995
acf61ecd 1996 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1997 if (ret) {
1998 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1999 ret);
acf61ecd 2000 goto out;
46a3df9f
S		 2001 }
2002
2daf4a65 2003 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 2004 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 2005 if (ret) {
2006 dev_err(&hdev->pdev->dev,
2007 "could not configure rx private waterline %d\n",
2008 ret);
acf61ecd 2009 goto out;
2daf4a65 2010 }
46a3df9f 2011
acf61ecd 2012 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 2013 if (ret) {
2014 dev_err(&hdev->pdev->dev,
2015 "could not configure common threshold %d\n",
2016 ret);
acf61ecd 2017 goto out;
2daf4a65 2018 }
46a3df9f
S		 2019 }
2020
acf61ecd
YL		 2021 ret = hclge_common_wl_config(hdev, pkt_buf);
2022 if (ret)
46a3df9f
S		 2023 dev_err(&hdev->pdev->dev,
2024 "could not configure common waterline %d\n", ret);
46a3df9f 2025
acf61ecd
YL		 2026out:
2027 kfree(pkt_buf);
2028 return ret;
46a3df9f
S		 2029}
2030
2031static int hclge_init_roce_base_info(struct hclge_vport *vport)
2032{
2033 struct hnae3_handle *roce = &vport->roce;
2034 struct hnae3_handle *nic = &vport->nic;
2035
887c3820 2036 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 2037
2038 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2039 vport->back->num_msi_left == 0)
2040 return -EINVAL;
2041
2042 roce->rinfo.base_vector = vport->back->roce_base_vector;
2043
2044 roce->rinfo.netdev = nic->kinfo.netdev;
2045 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2046
2047 roce->pdev = nic->pdev;
2048 roce->ae_algo = nic->ae_algo;
2049 roce->numa_node_mask = nic->numa_node_mask;
2050
2051 return 0;
2052}
2053
887c3820 2054static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 2055{
2056 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 2057 int vectors;
2058 int i;
46a3df9f 2059
887c3820
SM		 2060 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2061 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2062 if (vectors < 0) {
2063 dev_err(&pdev->dev,
2064 "failed(%d) to allocate MSI/MSI-X vectors\n",
2065 vectors);
2066 return vectors;
46a3df9f 2067 }
887c3820
SM		 2068 if (vectors < hdev->num_msi)
2069 dev_warn(&hdev->pdev->dev,
2070 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2071 hdev->num_msi, vectors);
46a3df9f 2072
887c3820
SM		 2073 hdev->num_msi = vectors;
2074 hdev->num_msi_left = vectors;
2075 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 2076 hdev->roce_base_vector = hdev->base_msi_vector +
2077 HCLGE_ROCE_VECTOR_OFFSET;
2078
46a3df9f
S		 2079 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2080 sizeof(u16), GFP_KERNEL);
887c3820
SM		 2081 if (!hdev->vector_status) {
2082 pci_free_irq_vectors(pdev);
46a3df9f 2083 return -ENOMEM;
887c3820 2084 }
46a3df9f
S		 2085
2086 for (i = 0; i < hdev->num_msi; i++)
2087 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2088
887c3820
SM		 2089 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2090 sizeof(int), GFP_KERNEL);
2091 if (!hdev->vector_irq) {
2092 pci_free_irq_vectors(pdev);
2093 return -ENOMEM;
46a3df9f 2094 }
46a3df9f
S		 2095
2096 return 0;
2097}
2098
2099static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2100{
2101 struct hclge_mac *mac = &hdev->hw.mac;
2102
2103 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2104 mac->duplex = (u8)duplex;
2105 else
2106 mac->duplex = HCLGE_MAC_FULL;
2107
2108 mac->speed = speed;
2109}
2110
2111int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2112{
d44f9b63 2113 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2114 struct hclge_desc desc;
2115 int ret;
2116
d44f9b63 2117 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2118
2119 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2120
2121 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2122
2123 switch (speed) {
2124 case HCLGE_MAC_SPEED_10M:
2125 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2126 HCLGE_CFG_SPEED_S, 6);
2127 break;
2128 case HCLGE_MAC_SPEED_100M:
2129 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2130 HCLGE_CFG_SPEED_S, 7);
2131 break;
2132 case HCLGE_MAC_SPEED_1G:
2133 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2134 HCLGE_CFG_SPEED_S, 0);
2135 break;
2136 case HCLGE_MAC_SPEED_10G:
2137 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2138 HCLGE_CFG_SPEED_S, 1);
2139 break;
2140 case HCLGE_MAC_SPEED_25G:
2141 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2142 HCLGE_CFG_SPEED_S, 2);
2143 break;
2144 case HCLGE_MAC_SPEED_40G:
2145 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2146 HCLGE_CFG_SPEED_S, 3);
2147 break;
2148 case HCLGE_MAC_SPEED_50G:
2149 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2150 HCLGE_CFG_SPEED_S, 4);
2151 break;
2152 case HCLGE_MAC_SPEED_100G:
2153 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2154 HCLGE_CFG_SPEED_S, 5);
2155 break;
2156 default:
d7629e74 2157 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2158 return -EINVAL;
2159 }
2160
2161 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2162 1);
2163
2164 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2165 if (ret) {
2166 dev_err(&hdev->pdev->dev,
2167 "mac speed/duplex config cmd failed %d.\n", ret);
2168 return ret;
2169 }
2170
2171 hclge_check_speed_dup(hdev, duplex, speed);
2172
2173 return 0;
2174}
2175
2176static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2177 u8 duplex)
2178{
2179 struct hclge_vport *vport = hclge_get_vport(handle);
2180 struct hclge_dev *hdev = vport->back;
2181
2182 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2183}
2184
2185static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2186 u8 *duplex)
2187{
d44f9b63 2188 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2189 struct hclge_desc desc;
2190 int speed_tmp;
2191 int ret;
2192
d44f9b63 2193 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2194
2195 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2196 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2197 if (ret) {
2198 dev_err(&hdev->pdev->dev,
2199 "mac speed/autoneg/duplex query cmd failed %d\n",
2200 ret);
2201 return ret;
2202 }
2203
2204 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2205 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2206 HCLGE_QUERY_SPEED_S);
2207
2208 ret = hclge_parse_speed(speed_tmp, speed);
2209 if (ret) {
2210 dev_err(&hdev->pdev->dev,
2211 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2212 return -EIO;
2213 }
2214
2215 return 0;
2216}
2217
46a3df9f
S		 2218static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2219{
d44f9b63 2220 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2221 struct hclge_desc desc;
a90bb9a5 2222 u32 flag = 0;
46a3df9f
S		 2223 int ret;
2224
2225 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2226
d44f9b63 2227 req = (struct hclge_config_auto_neg_cmd *)desc.data;
a90bb9a5
YL		 2228 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2229 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2230
2231 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2232 if (ret) {
2233 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2234 ret);
2235 return ret;
2236 }
2237
2238 return 0;
2239}
2240
2241static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2242{
2243 struct hclge_vport *vport = hclge_get_vport(handle);
2244 struct hclge_dev *hdev = vport->back;
2245
2246 return hclge_set_autoneg_en(hdev, enable);
2247}
2248
2249static int hclge_get_autoneg(struct hnae3_handle *handle)
2250{
2251 struct hclge_vport *vport = hclge_get_vport(handle);
2252 struct hclge_dev *hdev = vport->back;
27b5bf49
FL		 2253 struct phy_device *phydev = hdev->hw.mac.phydev;
2254
2255 if (phydev)
2256 return phydev->autoneg;
46a3df9f
S		 2257
2258 return hdev->hw.mac.autoneg;
2259}
2260
7564094c
PL		 2261static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2262 bool mask_vlan,
2263 u8 *mac_mask)
2264{
2265 struct hclge_mac_vlan_mask_entry_cmd *req;
2266 struct hclge_desc desc;
2267 int status;
2268
2269 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2270 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2271
2272 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2273 mask_vlan ? 1 : 0);
2274 ether_addr_copy(req->mac_mask, mac_mask);
2275
2276 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2277 if (status)
2278 dev_err(&hdev->pdev->dev,
2279 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2280 status);
2281
2282 return status;
2283}
2284
46a3df9f
S		 2285static int hclge_mac_init(struct hclge_dev *hdev)
2286{
f9fd82a9
FL		 2287 struct hnae3_handle *handle = &hdev->vport[0].nic;
2288 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 2289 struct hclge_mac *mac = &hdev->hw.mac;
7564094c 2290 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
f9fd82a9 2291 int mtu;
46a3df9f
S		 2292 int ret;
2293
2294 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2295 if (ret) {
2296 dev_err(&hdev->pdev->dev,
2297 "Config mac speed dup fail ret=%d\n", ret);
2298 return ret;
2299 }
2300
2301 mac->link = 0;
2302
46a3df9f
S		 2303 /* Initialize the MTA table work mode */
2304 hdev->accept_mta_mc = true;
2305 hdev->enable_mta = true;
2306 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2307
2308 ret = hclge_set_mta_filter_mode(hdev,
2309 hdev->mta_mac_sel_type,
2310 hdev->enable_mta);
2311 if (ret) {
2312 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2313 ret);
2314 return ret;
2315 }
2316
7564094c
PL		 2317 ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2318 if (ret) {
2319 dev_err(&hdev->pdev->dev,
2320 "set mta filter mode fail ret=%d\n", ret);
2321 return ret;
2322 }
2323
2324 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
f9fd82a9 2325 if (ret) {
7564094c
PL		 2326 dev_err(&hdev->pdev->dev,
2327 "set default mac_vlan_mask fail ret=%d\n", ret);
f9fd82a9
FL		 2328 return ret;
2329 }
7564094c 2330
f9fd82a9
FL		 2331 if (netdev)
2332 mtu = netdev->mtu;
2333 else
2334 mtu = ETH_DATA_LEN;
2335
2336 ret = hclge_set_mtu(handle, mtu);
2337 if (ret) {
2338 dev_err(&hdev->pdev->dev,
2339 "set mtu failed ret=%d\n", ret);
2340 return ret;
2341 }
2342
2343 return 0;
46a3df9f
S		 2344}
2345
c1a81619
SM		 2346static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2347{
2348 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2349 schedule_work(&hdev->mbx_service_task);
2350}
2351
cb1b9f77
SM		 2352static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2353{
2354 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2355 schedule_work(&hdev->rst_service_task);
2356}
2357
46a3df9f
S		 2358static void hclge_task_schedule(struct hclge_dev *hdev)
2359{
2360 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2361 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2362 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2363 (void)schedule_work(&hdev->service_task);
2364}
2365
2366static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2367{
d44f9b63 2368 struct hclge_link_status_cmd *req;
46a3df9f
S		 2369 struct hclge_desc desc;
2370 int link_status;
2371 int ret;
2372
2373 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2374 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2375 if (ret) {
2376 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2377 ret);
2378 return ret;
2379 }
2380
d44f9b63 2381 req = (struct hclge_link_status_cmd *)desc.data;
46a3df9f
S		 2382 link_status = req->status & HCLGE_LINK_STATUS;
2383
2384 return !!link_status;
2385}
2386
2387static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2388{
2389 int mac_state;
2390 int link_stat;
2391
2392 mac_state = hclge_get_mac_link_status(hdev);
2393
2394 if (hdev->hw.mac.phydev) {
2395 if (!genphy_read_status(hdev->hw.mac.phydev))
2396 link_stat = mac_state &
2397 hdev->hw.mac.phydev->link;
2398 else
2399 link_stat = 0;
2400
2401 } else {
2402 link_stat = mac_state;
2403 }
2404
2405 return !!link_stat;
2406}
2407
2408static void hclge_update_link_status(struct hclge_dev *hdev)
2409{
2410 struct hnae3_client *client = hdev->nic_client;
2411 struct hnae3_handle *handle;
2412 int state;
2413 int i;
2414
2415 if (!client)
2416 return;
2417 state = hclge_get_mac_phy_link(hdev);
2418 if (state != hdev->hw.mac.link) {
2419 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2420 handle = &hdev->vport[i].nic;
2421 client->ops->link_status_change(handle, state);
2422 }
2423 hdev->hw.mac.link = state;
2424 }
2425}
2426
2427static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2428{
2429 struct hclge_mac mac = hdev->hw.mac;
2430 u8 duplex;
2431 int speed;
2432 int ret;
2433
2434 /* get the speed and duplex as autoneg'result from mac cmd when phy
2435 * doesn't exit.
2436 */
c040366b 2437 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2438 return 0;
2439
2440 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2441 if (ret) {
2442 dev_err(&hdev->pdev->dev,
2443 "mac autoneg/speed/duplex query failed %d\n", ret);
2444 return ret;
2445 }
2446
2447 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2448 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2449 if (ret) {
2450 dev_err(&hdev->pdev->dev,
2451 "mac speed/duplex config failed %d\n", ret);
2452 return ret;
2453 }
2454 }
2455
2456 return 0;
2457}
2458
2459static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2460{
2461 struct hclge_vport *vport = hclge_get_vport(handle);
2462 struct hclge_dev *hdev = vport->back;
2463
2464 return hclge_update_speed_duplex(hdev);
2465}
2466
2467static int hclge_get_status(struct hnae3_handle *handle)
2468{
2469 struct hclge_vport *vport = hclge_get_vport(handle);
2470 struct hclge_dev *hdev = vport->back;
2471
2472 hclge_update_link_status(hdev);
2473
2474 return hdev->hw.mac.link;
2475}
2476
d039ef68 2477static void hclge_service_timer(struct timer_list *t)
46a3df9f 2478{
d039ef68 2479 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2480
d039ef68 2481 mod_timer(&hdev->service_timer, jiffies + HZ);
c5f65480 2482 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2483 hclge_task_schedule(hdev);
2484}
2485
2486static void hclge_service_complete(struct hclge_dev *hdev)
2487{
2488 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2489
2490 /* Flush memory before next watchdog */
2491 smp_mb__before_atomic();
2492 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2493}
2494
ca1d7669
SM		 2495static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2496{
2497 u32 rst_src_reg;
c1a81619 2498 u32 cmdq_src_reg;
ca1d7669
SM		 2499
2500 /* fetch the events from their corresponding regs */
2501 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
c1a81619
SM		 2502 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2503
2504 /* Assumption: If by any chance reset and mailbox events are reported
2505 * together then we will only process reset event in this go and will
2506 * defer the processing of the mailbox events. Since, we would have not
2507 * cleared RX CMDQ event this time we would receive again another
2508 * interrupt from H/W just for the mailbox.
2509 */
ca1d7669
SM		 2510
2511 /* check for vector0 reset event sources */
2512 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2513 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2514 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2515 return HCLGE_VECTOR0_EVENT_RST;
2516 }
2517
2518 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2519 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2520 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2521 return HCLGE_VECTOR0_EVENT_RST;
2522 }
2523
2524 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2525 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2526 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2527 return HCLGE_VECTOR0_EVENT_RST;
2528 }
2529
c1a81619
SM		 2530 /* check for vector0 mailbox(=CMDQ RX) event source */
2531 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2532 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2533 *clearval = cmdq_src_reg;
2534 return HCLGE_VECTOR0_EVENT_MBX;
2535 }
ca1d7669
SM		 2536
2537 return HCLGE_VECTOR0_EVENT_OTHER;
2538}
2539
2540static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2541 u32 regclr)
2542{
c1a81619
SM		 2543 switch (event_type) {
2544 case HCLGE_VECTOR0_EVENT_RST:
ca1d7669 2545 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
c1a81619
SM		 2546 break;
2547 case HCLGE_VECTOR0_EVENT_MBX:
2548 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2549 break;
2550 }
ca1d7669
SM		 2551}
2552
466b0c00
L		 2553static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2554{
2555 writel(enable ? 1 : 0, vector->addr);
2556}
2557
2558static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2559{
2560 struct hclge_dev *hdev = data;
ca1d7669
SM		 2561 u32 event_cause;
2562 u32 clearval;
466b0c00
L		 2563
2564 hclge_enable_vector(&hdev->misc_vector, false);
ca1d7669
SM		 2565 event_cause = hclge_check_event_cause(hdev, &clearval);
2566
c1a81619 2567 /* vector 0 interrupt is shared with reset and mailbox source events.*/
ca1d7669
SM		 2568 switch (event_cause) {
2569 case HCLGE_VECTOR0_EVENT_RST:
cb1b9f77 2570 hclge_reset_task_schedule(hdev);
ca1d7669 2571 break;
c1a81619
SM		 2572 case HCLGE_VECTOR0_EVENT_MBX:
2573 /* If we are here then,
2574 * 1. Either we are not handling any mbx task and we are not
2575 * scheduled as well
2576 * OR
2577 * 2. We could be handling a mbx task but nothing more is
2578 * scheduled.
2579 * In both cases, we should schedule mbx task as there are more
2580 * mbx messages reported by this interrupt.
2581 */
2582 hclge_mbx_task_schedule(hdev);
2583
ca1d7669
SM		 2584 default:
2585 dev_dbg(&hdev->pdev->dev,
2586 "received unknown or unhandled event of vector0\n");
2587 break;
2588 }
2589
2590 /* we should clear the source of interrupt */
2591 hclge_clear_event_cause(hdev, event_cause, clearval);
2592 hclge_enable_vector(&hdev->misc_vector, true);
466b0c00
L		 2593
2594 return IRQ_HANDLED;
2595}
2596
2597static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2598{
2599 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2600 hdev->num_msi_left += 1;
2601 hdev->num_msi_used -= 1;
2602}
2603
2604static void hclge_get_misc_vector(struct hclge_dev *hdev)
2605{
2606 struct hclge_misc_vector *vector = &hdev->misc_vector;
2607
2608 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2609
2610 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2611 hdev->vector_status[0] = 0;
2612
2613 hdev->num_msi_left -= 1;
2614 hdev->num_msi_used += 1;
2615}
2616
2617static int hclge_misc_irq_init(struct hclge_dev *hdev)
2618{
2619 int ret;
2620
2621 hclge_get_misc_vector(hdev);
2622
ca1d7669
SM		 2623 /* this would be explicitly freed in the end */
2624 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2625 0, "hclge_misc", hdev);
466b0c00
L		 2626 if (ret) {
2627 hclge_free_vector(hdev, 0);
2628 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2629 hdev->misc_vector.vector_irq);
2630 }
2631
2632 return ret;
2633}
2634
ca1d7669
SM		 2635static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2636{
2637 free_irq(hdev->misc_vector.vector_irq, hdev);
2638 hclge_free_vector(hdev, 0);
2639}
2640
4ed340ab
L		 2641static int hclge_notify_client(struct hclge_dev *hdev,
2642 enum hnae3_reset_notify_type type)
2643{
2644 struct hnae3_client *client = hdev->nic_client;
2645 u16 i;
2646
2647 if (!client->ops->reset_notify)
2648 return -EOPNOTSUPP;
2649
2650 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2651 struct hnae3_handle *handle = &hdev->vport[i].nic;
2652 int ret;
2653
2654 ret = client->ops->reset_notify(handle, type);
2655 if (ret)
2656 return ret;
2657 }
2658
2659 return 0;
2660}
2661
2662static int hclge_reset_wait(struct hclge_dev *hdev)
2663{
2664#define HCLGE_RESET_WATI_MS 100
2665#define HCLGE_RESET_WAIT_CNT 5
2666 u32 val, reg, reg_bit;
2667 u32 cnt = 0;
2668
2669 switch (hdev->reset_type) {
2670 case HNAE3_GLOBAL_RESET:
2671 reg = HCLGE_GLOBAL_RESET_REG;
2672 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2673 break;
2674 case HNAE3_CORE_RESET:
2675 reg = HCLGE_GLOBAL_RESET_REG;
2676 reg_bit = HCLGE_CORE_RESET_BIT;
2677 break;
2678 case HNAE3_FUNC_RESET:
2679 reg = HCLGE_FUN_RST_ING;
2680 reg_bit = HCLGE_FUN_RST_ING_B;
2681 break;
2682 default:
2683 dev_err(&hdev->pdev->dev,
2684 "Wait for unsupported reset type: %d\n",
2685 hdev->reset_type);
2686 return -EINVAL;
2687 }
2688
2689 val = hclge_read_dev(&hdev->hw, reg);
2690 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2691 msleep(HCLGE_RESET_WATI_MS);
2692 val = hclge_read_dev(&hdev->hw, reg);
2693 cnt++;
2694 }
2695
4ed340ab
L		 2696 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2697 dev_warn(&hdev->pdev->dev,
2698 "Wait for reset timeout: %d\n", hdev->reset_type);
2699 return -EBUSY;
2700 }
2701
2702 return 0;
2703}
2704
2705static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2706{
2707 struct hclge_desc desc;
2708 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2709 int ret;
2710
2711 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2712 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2713 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2714 req->fun_reset_vfid = func_id;
2715
2716 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2717 if (ret)
2718 dev_err(&hdev->pdev->dev,
2719 "send function reset cmd fail, status =%d\n", ret);
2720
2721 return ret;
2722}
2723
f2f432f2 2724static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2725{
2726 struct pci_dev *pdev = hdev->pdev;
2727 u32 val;
2728
f2f432f2 2729 switch (hdev->reset_type) {
4ed340ab
L		 2730 case HNAE3_GLOBAL_RESET:
2731 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2732 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2733 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2734 dev_info(&pdev->dev, "Global Reset requested\n");
2735 break;
2736 case HNAE3_CORE_RESET:
2737 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2738 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2739 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2740 dev_info(&pdev->dev, "Core Reset requested\n");
2741 break;
2742 case HNAE3_FUNC_RESET:
2743 dev_info(&pdev->dev, "PF Reset requested\n");
2744 hclge_func_reset_cmd(hdev, 0);
cb1b9f77
SM		 2745 /* schedule again to check later */
2746 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2747 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2748 break;
2749 default:
2750 dev_warn(&pdev->dev,
f2f432f2 2751 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2752 break;
2753 }
2754}
2755
f2f432f2
SM		 2756static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2757 unsigned long *addr)
2758{
2759 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2760
2761 /* return the highest priority reset level amongst all */
2762 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2763 rst_level = HNAE3_GLOBAL_RESET;
2764 else if (test_bit(HNAE3_CORE_RESET, addr))
2765 rst_level = HNAE3_CORE_RESET;
2766 else if (test_bit(HNAE3_IMP_RESET, addr))
2767 rst_level = HNAE3_IMP_RESET;
2768 else if (test_bit(HNAE3_FUNC_RESET, addr))
2769 rst_level = HNAE3_FUNC_RESET;
2770
2771 /* now, clear all other resets */
2772 clear_bit(HNAE3_GLOBAL_RESET, addr);
2773 clear_bit(HNAE3_CORE_RESET, addr);
2774 clear_bit(HNAE3_IMP_RESET, addr);
2775 clear_bit(HNAE3_FUNC_RESET, addr);
2776
2777 return rst_level;
2778}
2779
2780static void hclge_reset(struct hclge_dev *hdev)
2781{
2782 /* perform reset of the stack & ae device for a client */
2783
2784 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2785
2786 if (!hclge_reset_wait(hdev)) {
2787 rtnl_lock();
2788 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2789 hclge_reset_ae_dev(hdev->ae_dev);
2790 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2791 rtnl_unlock();
2792 } else {
2793 /* schedule again to check pending resets later */
2794 set_bit(hdev->reset_type, &hdev->reset_pending);
2795 hclge_reset_task_schedule(hdev);
2796 }
2797
2798 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2799}
2800
4ed340ab
L		 2801static void hclge_reset_event(struct hnae3_handle *handle,
2802 enum hnae3_reset_type reset)
2803{
2804 struct hclge_vport *vport = hclge_get_vport(handle);
2805 struct hclge_dev *hdev = vport->back;
2806
2807 dev_info(&hdev->pdev->dev,
2808 "Receive reset event , reset_type is %d", reset);
2809
2810 switch (reset) {
2811 case HNAE3_FUNC_RESET:
2812 case HNAE3_CORE_RESET:
2813 case HNAE3_GLOBAL_RESET:
cb1b9f77
SM		 2814 /* request reset & schedule reset task */
2815 set_bit(reset, &hdev->reset_request);
2816 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2817 break;
2818 default:
2819 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2820 break;
2821 }
2822}
2823
2824static void hclge_reset_subtask(struct hclge_dev *hdev)
2825{
f2f432f2
SM		 2826 /* check if there is any ongoing reset in the hardware. This status can
2827 * be checked from reset_pending. If there is then, we need to wait for
2828 * hardware to complete reset.
2829 * a. If we are able to figure out in reasonable time that hardware
2830 * has fully resetted then, we can proceed with driver, client
2831 * reset.
2832 * b. else, we can come back later to check this status so re-sched
2833 * now.
2834 */
2835 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2836 if (hdev->reset_type != HNAE3_NONE_RESET)
2837 hclge_reset(hdev);
4ed340ab 2838
f2f432f2
SM		 2839 /* check if we got any *new* reset requests to be honored */
2840 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2841 if (hdev->reset_type != HNAE3_NONE_RESET)
2842 hclge_do_reset(hdev);
4ed340ab 2843
4ed340ab
L		 2844 hdev->reset_type = HNAE3_NONE_RESET;
2845}
2846
cb1b9f77 2847static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2848{
cb1b9f77
SM		 2849 struct hclge_dev *hdev =
2850 container_of(work, struct hclge_dev, rst_service_task);
2851
2852 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2853 return;
2854
2855 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2856
4ed340ab 2857 hclge_reset_subtask(hdev);
cb1b9f77
SM		 2858
2859 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2860}
2861
c1a81619
SM		 2862static void hclge_mailbox_service_task(struct work_struct *work)
2863{
2864 struct hclge_dev *hdev =
2865 container_of(work, struct hclge_dev, mbx_service_task);
2866
2867 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2868 return;
2869
2870 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2871
2872 hclge_mbx_handler(hdev);
2873
2874 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2875}
2876
46a3df9f
S		 2877static void hclge_service_task(struct work_struct *work)
2878{
2879 struct hclge_dev *hdev =
2880 container_of(work, struct hclge_dev, service_task);
2881
716aaac1
JS		 2882 /* The total rx/tx packets statstics are wanted to be updated
2883 * per second. Both hclge_update_stats_for_all() and
2884 * hclge_mac_get_traffic_stats() can do it.
2885 */
c5f65480
JS		 2886 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2887 hclge_update_stats_for_all(hdev);
2888 hdev->hw_stats.stats_timer = 0;
716aaac1
JS		 2889 } else {
2890 hclge_mac_get_traffic_stats(hdev);
c5f65480
JS		 2891 }
2892
46a3df9f
S		 2893 hclge_update_speed_duplex(hdev);
2894 hclge_update_link_status(hdev);
716aaac1 2895 hclge_update_led_status(hdev);
46a3df9f
S		 2896 hclge_service_complete(hdev);
2897}
2898
2899static void hclge_disable_sriov(struct hclge_dev *hdev)
2900{
2a32ca13
AB		 2901 /* If our VFs are assigned we cannot shut down SR-IOV
2902 * without causing issues, so just leave the hardware
2903 * available but disabled
2904 */
2905 if (pci_vfs_assigned(hdev->pdev)) {
2906 dev_warn(&hdev->pdev->dev,
2907 "disabling driver while VFs are assigned\n");
2908 return;
2909 }
46a3df9f 2910
2a32ca13 2911 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2912}
2913
2914struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2915{
2916 /* VF handle has no client */
2917 if (!handle->client)
2918 return container_of(handle, struct hclge_vport, nic);
2919 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2920 return container_of(handle, struct hclge_vport, roce);
2921 else
2922 return container_of(handle, struct hclge_vport, nic);
2923}
2924
2925static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2926 struct hnae3_vector_info *vector_info)
2927{
2928 struct hclge_vport *vport = hclge_get_vport(handle);
2929 struct hnae3_vector_info *vector = vector_info;
2930 struct hclge_dev *hdev = vport->back;
2931 int alloc = 0;
2932 int i, j;
2933
2934 vector_num = min(hdev->num_msi_left, vector_num);
2935
2936 for (j = 0; j < vector_num; j++) {
2937 for (i = 1; i < hdev->num_msi; i++) {
2938 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2939 vector->vector = pci_irq_vector(hdev->pdev, i);
2940 vector->io_addr = hdev->hw.io_base +
2941 HCLGE_VECTOR_REG_BASE +
2942 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2943 vport->vport_id *
2944 HCLGE_VECTOR_VF_OFFSET;
2945 hdev->vector_status[i] = vport->vport_id;
887c3820 2946 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2947
2948 vector++;
2949 alloc++;
2950
2951 break;
2952 }
2953 }
2954 }
2955 hdev->num_msi_left -= alloc;
2956 hdev->num_msi_used += alloc;
2957
2958 return alloc;
2959}
2960
2961static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2962{
2963 int i;
2964
887c3820
SM		 2965 for (i = 0; i < hdev->num_msi; i++)
2966 if (vector == hdev->vector_irq[i])
2967 return i;
2968
46a3df9f
S		 2969 return -EINVAL;
2970}
2971
0d3e6631
YL		 2972static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2973{
2974 struct hclge_vport *vport = hclge_get_vport(handle);
2975 struct hclge_dev *hdev = vport->back;
2976 int vector_id;
2977
2978 vector_id = hclge_get_vector_index(hdev, vector);
2979 if (vector_id < 0) {
2980 dev_err(&hdev->pdev->dev,
2981 "Get vector index fail. vector_id =%d\n", vector_id);
2982 return vector_id;
2983 }
2984
2985 hclge_free_vector(hdev, vector_id);
2986
2987 return 0;
2988}
2989
46a3df9f
S		 2990static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2991{
2992 return HCLGE_RSS_KEY_SIZE;
2993}
2994
2995static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2996{
2997 return HCLGE_RSS_IND_TBL_SIZE;
2998}
2999
46a3df9f
S		 3000static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3001 const u8 hfunc, const u8 *key)
3002{
d44f9b63 3003 struct hclge_rss_config_cmd *req;
46a3df9f
S		 3004 struct hclge_desc desc;
3005 int key_offset;
3006 int key_size;
3007 int ret;
3008
d44f9b63 3009 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 3010
3011 for (key_offset = 0; key_offset < 3; key_offset++) {
3012 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3013 false);
3014
3015 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3016 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3017
3018 if (key_offset == 2)
3019 key_size =
3020 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3021 else
3022 key_size = HCLGE_RSS_HASH_KEY_NUM;
3023
3024 memcpy(req->hash_key,
3025 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3026
3027 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3028 if (ret) {
3029 dev_err(&hdev->pdev->dev,
3030 "Configure RSS config fail, status = %d\n",
3031 ret);
3032 return ret;
3033 }
3034 }
3035 return 0;
3036}
3037
89523cfa 3038static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3039{
d44f9b63 3040 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3041 struct hclge_desc desc;
3042 int i, j;
3043 int ret;
3044
d44f9b63 3045 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3046
3047 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3048 hclge_cmd_setup_basic_desc
3049 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3050
a90bb9a5
YL		 3051 req->start_table_index =
3052 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3053 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3054
3055 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3056 req->rss_result[j] =
3057 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3058
3059 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3060 if (ret) {
3061 dev_err(&hdev->pdev->dev,
3062 "Configure rss indir table fail,status = %d\n",
3063 ret);
3064 return ret;
3065 }
3066 }
3067 return 0;
3068}
3069
3070static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3071 u16 *tc_size, u16 *tc_offset)
3072{
d44f9b63 3073 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3074 struct hclge_desc desc;
3075 int ret;
3076 int i;
3077
3078 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3079 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3080
3081 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3082 u16 mode = 0;
3083
3084 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3085 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
46a3df9f 3086 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
a90bb9a5 3087 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
46a3df9f 3088 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3089
3090 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3091 }
3092
3093 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3094 if (ret) {
3095 dev_err(&hdev->pdev->dev,
3096 "Configure rss tc mode fail, status = %d\n", ret);
3097 return ret;
3098 }
3099
3100 return 0;
3101}
3102
3103static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3104{
d44f9b63 3105 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3106 struct hclge_desc desc;
3107 int ret;
3108
3109 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3110
d44f9b63 3111 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429
YL		 3112
3113 /* Get the tuple cfg from pf */
3114 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3115 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3116 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3117 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3118 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3119 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3120 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3121 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
46a3df9f
S		 3122 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3123 if (ret) {
3124 dev_err(&hdev->pdev->dev,
3125 "Configure rss input fail, status = %d\n", ret);
3126 return ret;
3127 }
3128
3129 return 0;
3130}
3131
3132static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3133 u8 *key, u8 *hfunc)
3134{
3135 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3136 int i;
3137
3138 /* Get hash algorithm */
3139 if (hfunc)
89523cfa 3140 *hfunc = vport->rss_algo;
46a3df9f
S		 3141
3142 /* Get the RSS Key required by the user */
3143 if (key)
3144 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3145
3146 /* Get indirect table */
3147 if (indir)
3148 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3149 indir[i] = vport->rss_indirection_tbl[i];
3150
3151 return 0;
3152}
3153
3154static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3155 const u8 *key, const u8 hfunc)
3156{
3157 struct hclge_vport *vport = hclge_get_vport(handle);
3158 struct hclge_dev *hdev = vport->back;
3159 u8 hash_algo;
3160 int ret, i;
3161
3162 /* Set the RSS Hash Key if specififed by the user */
3163 if (key) {
46a3df9f
S		 3164
3165 if (hfunc == ETH_RSS_HASH_TOP ||
3166 hfunc == ETH_RSS_HASH_NO_CHANGE)
3167 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3168 else
3169 return -EINVAL;
3170 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3171 if (ret)
3172 return ret;
89523cfa
YL		 3173
3174 /* Update the shadow RSS key with user specified qids */
3175 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3176 vport->rss_algo = hash_algo;
46a3df9f
S		 3177 }
3178
3179 /* Update the shadow RSS table with user specified qids */
3180 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3181 vport->rss_indirection_tbl[i] = indir[i];
3182
3183 /* Update the hardware */
89523cfa 3184 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3185}
3186
f7db940a
L		 3187static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3188{
3189 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3190
3191 if (nfc->data & RXH_L4_B_2_3)
3192 hash_sets |= HCLGE_D_PORT_BIT;
3193 else
3194 hash_sets &= ~HCLGE_D_PORT_BIT;
3195
3196 if (nfc->data & RXH_IP_SRC)
3197 hash_sets |= HCLGE_S_IP_BIT;
3198 else
3199 hash_sets &= ~HCLGE_S_IP_BIT;
3200
3201 if (nfc->data & RXH_IP_DST)
3202 hash_sets |= HCLGE_D_IP_BIT;
3203 else
3204 hash_sets &= ~HCLGE_D_IP_BIT;
3205
3206 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3207 hash_sets |= HCLGE_V_TAG_BIT;
3208
3209 return hash_sets;
3210}
3211
3212static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3213 struct ethtool_rxnfc *nfc)
3214{
3215 struct hclge_vport *vport = hclge_get_vport(handle);
3216 struct hclge_dev *hdev = vport->back;
3217 struct hclge_rss_input_tuple_cmd *req;
3218 struct hclge_desc desc;
3219 u8 tuple_sets;
3220 int ret;
3221
3222 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3223 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3224 return -EINVAL;
3225
3226 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429 3227 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 3228
6f2af429
YL		 3229 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3230 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3231 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3232 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3233 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3234 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3235 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3236 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 3237
3238 tuple_sets = hclge_get_rss_hash_bits(nfc);
3239 switch (nfc->flow_type) {
3240 case TCP_V4_FLOW:
3241 req->ipv4_tcp_en = tuple_sets;
3242 break;
3243 case TCP_V6_FLOW:
3244 req->ipv6_tcp_en = tuple_sets;
3245 break;
3246 case UDP_V4_FLOW:
3247 req->ipv4_udp_en = tuple_sets;
3248 break;
3249 case UDP_V6_FLOW:
3250 req->ipv6_udp_en = tuple_sets;
3251 break;
3252 case SCTP_V4_FLOW:
3253 req->ipv4_sctp_en = tuple_sets;
3254 break;
3255 case SCTP_V6_FLOW:
3256 if ((nfc->data & RXH_L4_B_0_1) ||
3257 (nfc->data & RXH_L4_B_2_3))
3258 return -EINVAL;
3259
3260 req->ipv6_sctp_en = tuple_sets;
3261 break;
3262 case IPV4_FLOW:
3263 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3264 break;
3265 case IPV6_FLOW:
3266 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3267 break;
3268 default:
3269 return -EINVAL;
3270 }
3271
3272 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6f2af429 3273 if (ret) {
f7db940a
L		 3274 dev_err(&hdev->pdev->dev,
3275 "Set rss tuple fail, status = %d\n", ret);
6f2af429
YL		 3276 return ret;
3277 }
f7db940a 3278
6f2af429
YL		 3279 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3280 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3281 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3282 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3283 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3284 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3285 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3286 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3287 return 0;
f7db940a
L		 3288}
3289
07d29954
L		 3290static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3291 struct ethtool_rxnfc *nfc)
3292{
3293 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3294 u8 tuple_sets;
07d29954
L		 3295
3296 nfc->data = 0;
3297
07d29954
L		 3298 switch (nfc->flow_type) {
3299 case TCP_V4_FLOW:
6f2af429 3300 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3301 break;
3302 case UDP_V4_FLOW:
6f2af429 3303 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3304 break;
3305 case TCP_V6_FLOW:
6f2af429 3306 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3307 break;
3308 case UDP_V6_FLOW:
6f2af429 3309 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3310 break;
3311 case SCTP_V4_FLOW:
6f2af429 3312 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3313 break;
3314 case SCTP_V6_FLOW:
6f2af429 3315 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3316 break;
3317 case IPV4_FLOW:
3318 case IPV6_FLOW:
3319 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3320 break;
3321 default:
3322 return -EINVAL;
3323 }
3324
3325 if (!tuple_sets)
3326 return 0;
3327
3328 if (tuple_sets & HCLGE_D_PORT_BIT)
3329 nfc->data |= RXH_L4_B_2_3;
3330 if (tuple_sets & HCLGE_S_PORT_BIT)
3331 nfc->data |= RXH_L4_B_0_1;
3332 if (tuple_sets & HCLGE_D_IP_BIT)
3333 nfc->data |= RXH_IP_DST;
3334 if (tuple_sets & HCLGE_S_IP_BIT)
3335 nfc->data |= RXH_IP_SRC;
3336
3337 return 0;
3338}
3339
46a3df9f
S		 3340static int hclge_get_tc_size(struct hnae3_handle *handle)
3341{
3342 struct hclge_vport *vport = hclge_get_vport(handle);
3343 struct hclge_dev *hdev = vport->back;
3344
3345 return hdev->rss_size_max;
3346}
3347
77f255c1 3348int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3349{
46a3df9f 3350 struct hclge_vport *vport = hdev->vport;
268f5dfa
YL		 3351 u8 *rss_indir = vport[0].rss_indirection_tbl;
3352 u16 rss_size = vport[0].alloc_rss_size;
3353 u8 *key = vport[0].rss_hash_key;
3354 u8 hfunc = vport[0].rss_algo;
46a3df9f 3355 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3356 u16 tc_valid[HCLGE_MAX_TC_NUM];
3357 u16 tc_size[HCLGE_MAX_TC_NUM];
268f5dfa
YL		 3358 u16 roundup_size;
3359 int i, ret;
68ece54e 3360
46a3df9f
S		 3361 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3362 if (ret)
268f5dfa 3363 return ret;
46a3df9f 3364
46a3df9f
S		 3365 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3366 if (ret)
268f5dfa 3367 return ret;
46a3df9f
S		 3368
3369 ret = hclge_set_rss_input_tuple(hdev);
3370 if (ret)
268f5dfa 3371 return ret;
46a3df9f 3372
68ece54e
YL		 3373 /* Each TC have the same queue size, and tc_size set to hardware is
3374 * the log2 of roundup power of two of rss_size, the acutal queue
3375 * size is limited by indirection table.
3376 */
3377 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3378 dev_err(&hdev->pdev->dev,
3379 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3380 rss_size);
268f5dfa 3381 return -EINVAL;
68ece54e
YL		 3382 }
3383
3384 roundup_size = roundup_pow_of_two(rss_size);
3385 roundup_size = ilog2(roundup_size);
3386
46a3df9f 3387 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3388 tc_valid[i] = 0;
46a3df9f 3389
68ece54e
YL		 3390 if (!(hdev->hw_tc_map & BIT(i)))
3391 continue;
3392
3393 tc_valid[i] = 1;
3394 tc_size[i] = roundup_size;
3395 tc_offset[i] = rss_size * i;
46a3df9f 3396 }
68ece54e 3397
268f5dfa
YL		 3398 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3399}
46a3df9f 3400
268f5dfa
YL		 3401void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3402{
3403 struct hclge_vport *vport = hdev->vport;
3404 int i, j;
46a3df9f 3405
268f5dfa
YL		 3406 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3407 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3408 vport[j].rss_indirection_tbl[i] =
3409 i % vport[j].alloc_rss_size;
3410 }
3411}
3412
3413static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3414{
3415 struct hclge_vport *vport = hdev->vport;
3416 int i;
3417
3418 netdev_rss_key_fill(vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3419
3420 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3421 vport[i].rss_tuple_sets.ipv4_tcp_en =
3422 HCLGE_RSS_INPUT_TUPLE_OTHER;
3423 vport[i].rss_tuple_sets.ipv4_udp_en =
3424 HCLGE_RSS_INPUT_TUPLE_OTHER;
3425 vport[i].rss_tuple_sets.ipv4_sctp_en =
3426 HCLGE_RSS_INPUT_TUPLE_SCTP;
3427 vport[i].rss_tuple_sets.ipv4_fragment_en =
3428 HCLGE_RSS_INPUT_TUPLE_OTHER;
3429 vport[i].rss_tuple_sets.ipv6_tcp_en =
3430 HCLGE_RSS_INPUT_TUPLE_OTHER;
3431 vport[i].rss_tuple_sets.ipv6_udp_en =
3432 HCLGE_RSS_INPUT_TUPLE_OTHER;
3433 vport[i].rss_tuple_sets.ipv6_sctp_en =
3434 HCLGE_RSS_INPUT_TUPLE_SCTP;
3435 vport[i].rss_tuple_sets.ipv6_fragment_en =
3436 HCLGE_RSS_INPUT_TUPLE_OTHER;
3437
3438 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3439 }
3440
3441 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3442}
3443
84e095d6
SM		 3444int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3445 int vector_id, bool en,
3446 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3447{
3448 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3449 struct hnae3_ring_chain_node *node;
3450 struct hclge_desc desc;
84e095d6
SM		 3451 struct hclge_ctrl_vector_chain_cmd *req
3452 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3453 enum hclge_cmd_status status;
3454 enum hclge_opcode_type op;
3455 u16 tqp_type_and_id;
46a3df9f
S		 3456 int i;
3457
84e095d6
SM		 3458 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3459 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3460 req->int_vector_id = vector_id;
3461
3462 i = 0;
3463 for (node = ring_chain; node; node = node->next) {
84e095d6
SM		 3464 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3465 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3466 HCLGE_INT_TYPE_S,
46a3df9f 3467 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
84e095d6
SM		 3468 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3469 HCLGE_TQP_ID_S, node->tqp_index);
11af96a4
FL		 3470 hnae_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3471 HCLGE_INT_GL_IDX_S,
3472 hnae_get_field(node->int_gl_idx,
3473 HNAE3_RING_GL_IDX_M,
3474 HNAE3_RING_GL_IDX_S));
84e095d6 3475 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3476 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3477 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
84e095d6 3478 req->vfid = vport->vport_id;
46a3df9f 3479
84e095d6
SM		 3480 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3481 if (status) {
46a3df9f
S		 3482 dev_err(&hdev->pdev->dev,
3483 "Map TQP fail, status is %d.\n",
84e095d6
SM		 3484 status);
3485 return -EIO;
46a3df9f
S		 3486 }
3487 i = 0;
3488
3489 hclge_cmd_setup_basic_desc(&desc,
84e095d6 3490 op,
46a3df9f
S		 3491 false);
3492 req->int_vector_id = vector_id;
3493 }
3494 }
3495
3496 if (i > 0) {
3497 req->int_cause_num = i;
84e095d6
SM		 3498 req->vfid = vport->vport_id;
3499 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3500 if (status) {
46a3df9f 3501 dev_err(&hdev->pdev->dev,
84e095d6
SM		 3502 "Map TQP fail, status is %d.\n", status);
3503 return -EIO;
46a3df9f
S		 3504 }
3505 }
3506
3507 return 0;
3508}
3509
84e095d6
SM		 3510static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3511 int vector,
3512 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3513{
3514 struct hclge_vport *vport = hclge_get_vport(handle);
3515 struct hclge_dev *hdev = vport->back;
3516 int vector_id;
3517
3518 vector_id = hclge_get_vector_index(hdev, vector);
3519 if (vector_id < 0) {
3520 dev_err(&hdev->pdev->dev,
84e095d6 3521 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3522 return vector_id;
3523 }
3524
84e095d6 3525 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3526}
3527
84e095d6
SM		 3528static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3529 int vector,
3530 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3531{
3532 struct hclge_vport *vport = hclge_get_vport(handle);
3533 struct hclge_dev *hdev = vport->back;
84e095d6 3534 int vector_id, ret;
46a3df9f
S		 3535
3536 vector_id = hclge_get_vector_index(hdev, vector);
3537 if (vector_id < 0) {
3538 dev_err(&handle->pdev->dev,
3539 "Get vector index fail. ret =%d\n", vector_id);
3540 return vector_id;
3541 }
3542
84e095d6 3543 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
0d3e6631 3544 if (ret)
84e095d6
SM		 3545 dev_err(&handle->pdev->dev,
3546 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3547 vector_id,
3548 ret);
46a3df9f 3549
0d3e6631 3550 return ret;
46a3df9f
S		 3551}
3552
3553int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3554 struct hclge_promisc_param *param)
3555{
d44f9b63 3556 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3557 struct hclge_desc desc;
3558 int ret;
3559
3560 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3561
d44f9b63 3562 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f
S		 3563 req->vf_id = param->vf_id;
3564 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3565
3566 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3567 if (ret) {
3568 dev_err(&hdev->pdev->dev,
3569 "Set promisc mode fail, status is %d.\n", ret);
3570 return ret;
3571 }
3572 return 0;
3573}
3574
3575void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3576 bool en_mc, bool en_bc, int vport_id)
3577{
3578 if (!param)
3579 return;
3580
3581 memset(param, 0, sizeof(struct hclge_promisc_param));
3582 if (en_uc)
3583 param->enable = HCLGE_PROMISC_EN_UC;
3584 if (en_mc)
3585 param->enable |= HCLGE_PROMISC_EN_MC;
3586 if (en_bc)
3587 param->enable |= HCLGE_PROMISC_EN_BC;
3588 param->vf_id = vport_id;
3589}
3590
3591static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3592{
3593 struct hclge_vport *vport = hclge_get_vport(handle);
3594 struct hclge_dev *hdev = vport->back;
3595 struct hclge_promisc_param param;
3596
3597 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3598 hclge_cmd_set_promisc_mode(hdev, &param);
3599}
3600
3601static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3602{
3603 struct hclge_desc desc;
d44f9b63
YL		 3604 struct hclge_config_mac_mode_cmd *req =
3605 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3606 u32 loop_en = 0;
46a3df9f
S		 3607 int ret;
3608
3609 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
a90bb9a5
YL		 3610 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3611 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3612 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3613 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3614 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3615 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3616 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3617 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3618 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3619 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3620 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3621 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3622 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3623 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3624 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3625
3626 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3627 if (ret)
3628 dev_err(&hdev->pdev->dev,
3629 "mac enable fail, ret =%d.\n", ret);
3630}
3631
c39c4d98
YL		 3632static int hclge_set_loopback(struct hnae3_handle *handle,
3633 enum hnae3_loop loop_mode, bool en)
3634{
3635 struct hclge_vport *vport = hclge_get_vport(handle);
3636 struct hclge_config_mac_mode_cmd *req;
3637 struct hclge_dev *hdev = vport->back;
3638 struct hclge_desc desc;
3639 u32 loop_en;
3640 int ret;
3641
3642 switch (loop_mode) {
3643 case HNAE3_MAC_INTER_LOOP_MAC:
3644 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3645 /* 1 Read out the MAC mode config at first */
3646 hclge_cmd_setup_basic_desc(&desc,
3647 HCLGE_OPC_CONFIG_MAC_MODE,
3648 true);
3649 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3650 if (ret) {
3651 dev_err(&hdev->pdev->dev,
3652 "mac loopback get fail, ret =%d.\n",
3653 ret);
3654 return ret;
3655 }
3656
3657 /* 2 Then setup the loopback flag */
3658 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3659 if (en)
3660 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3661 else
3662 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3663
3664 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3665
3666 /* 3 Config mac work mode with loopback flag
3667 * and its original configure parameters
3668 */
3669 hclge_cmd_reuse_desc(&desc, false);
3670 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3671 if (ret)
3672 dev_err(&hdev->pdev->dev,
3673 "mac loopback set fail, ret =%d.\n", ret);
3674 break;
3675 default:
3676 ret = -ENOTSUPP;
3677 dev_err(&hdev->pdev->dev,
3678 "loop_mode %d is not supported\n", loop_mode);
3679 break;
3680 }
3681
3682 return ret;
3683}
3684
46a3df9f
S		 3685static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3686 int stream_id, bool enable)
3687{
3688 struct hclge_desc desc;
d44f9b63
YL		 3689 struct hclge_cfg_com_tqp_queue_cmd *req =
3690 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3691 int ret;
3692
3693 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3694 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3695 req->stream_id = cpu_to_le16(stream_id);
3696 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3697
3698 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3699 if (ret)
3700 dev_err(&hdev->pdev->dev,
3701 "Tqp enable fail, status =%d.\n", ret);
3702 return ret;
3703}
3704
3705static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3706{
3707 struct hclge_vport *vport = hclge_get_vport(handle);
3708 struct hnae3_queue *queue;
3709 struct hclge_tqp *tqp;
3710 int i;
3711
3712 for (i = 0; i < vport->alloc_tqps; i++) {
3713 queue = handle->kinfo.tqp[i];
3714 tqp = container_of(queue, struct hclge_tqp, q);
3715 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3716 }
3717}
3718
3719static int hclge_ae_start(struct hnae3_handle *handle)
3720{
3721 struct hclge_vport *vport = hclge_get_vport(handle);
3722 struct hclge_dev *hdev = vport->back;
814e0274 3723 int i, ret;
46a3df9f 3724
814e0274
PL		 3725 for (i = 0; i < vport->alloc_tqps; i++)
3726 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3727
46a3df9f
S		 3728 /* mac enable */
3729 hclge_cfg_mac_mode(hdev, true);
3730 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3731 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 3732
3733 ret = hclge_mac_start_phy(hdev);
3734 if (ret)
3735 return ret;
3736
3737 /* reset tqp stats */
3738 hclge_reset_tqp_stats(handle);
3739
3740 return 0;
3741}
3742
3743static void hclge_ae_stop(struct hnae3_handle *handle)
3744{
3745 struct hclge_vport *vport = hclge_get_vport(handle);
3746 struct hclge_dev *hdev = vport->back;
814e0274 3747 int i;
46a3df9f 3748
814e0274
PL		 3749 for (i = 0; i < vport->alloc_tqps; i++)
3750 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3751
46a3df9f
S		 3752 /* Mac disable */
3753 hclge_cfg_mac_mode(hdev, false);
3754
3755 hclge_mac_stop_phy(hdev);
3756
3757 /* reset tqp stats */
3758 hclge_reset_tqp_stats(handle);
8cc6c1f7
FL		 3759 del_timer_sync(&hdev->service_timer);
3760 cancel_work_sync(&hdev->service_task);
3761 hclge_update_link_status(hdev);
46a3df9f
S		 3762}
3763
3764static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3765 u16 cmdq_resp, u8 resp_code,
3766 enum hclge_mac_vlan_tbl_opcode op)
3767{
3768 struct hclge_dev *hdev = vport->back;
3769 int return_status = -EIO;
3770
3771 if (cmdq_resp) {
3772 dev_err(&hdev->pdev->dev,
3773 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3774 cmdq_resp);
3775 return -EIO;
3776 }
3777
3778 if (op == HCLGE_MAC_VLAN_ADD) {
3779 if ((!resp_code) || (resp_code == 1)) {
3780 return_status = 0;
3781 } else if (resp_code == 2) {
eefd00a5 3782 return_status = -ENOSPC;
46a3df9f
S		 3783 dev_err(&hdev->pdev->dev,
3784 "add mac addr failed for uc_overflow.\n");
3785 } else if (resp_code == 3) {
eefd00a5 3786 return_status = -ENOSPC;
46a3df9f
S		 3787 dev_err(&hdev->pdev->dev,
3788 "add mac addr failed for mc_overflow.\n");
3789 } else {
3790 dev_err(&hdev->pdev->dev,
3791 "add mac addr failed for undefined, code=%d.\n",
3792 resp_code);
3793 }
3794 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3795 if (!resp_code) {
3796 return_status = 0;
3797 } else if (resp_code == 1) {
eefd00a5 3798 return_status = -ENOENT;
46a3df9f
S		 3799 dev_dbg(&hdev->pdev->dev,
3800 "remove mac addr failed for miss.\n");
3801 } else {
3802 dev_err(&hdev->pdev->dev,
3803 "remove mac addr failed for undefined, code=%d.\n",
3804 resp_code);
3805 }
3806 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3807 if (!resp_code) {
3808 return_status = 0;
3809 } else if (resp_code == 1) {
eefd00a5 3810 return_status = -ENOENT;
46a3df9f
S		 3811 dev_dbg(&hdev->pdev->dev,
3812 "lookup mac addr failed for miss.\n");
3813 } else {
3814 dev_err(&hdev->pdev->dev,
3815 "lookup mac addr failed for undefined, code=%d.\n",
3816 resp_code);
3817 }
3818 } else {
eefd00a5 3819 return_status = -EINVAL;
46a3df9f
S		 3820 dev_err(&hdev->pdev->dev,
3821 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3822 op);
3823 }
3824
3825 return return_status;
3826}
3827
3828static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3829{
3830 int word_num;
3831 int bit_num;
3832
3833 if (vfid > 255 || vfid < 0)
3834 return -EIO;
3835
3836 if (vfid >= 0 && vfid <= 191) {
3837 word_num = vfid / 32;
3838 bit_num = vfid % 32;
3839 if (clr)
a90bb9a5 3840 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3841 else
a90bb9a5 3842 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3843 } else {
3844 word_num = (vfid - 192) / 32;
3845 bit_num = vfid % 32;
3846 if (clr)
a90bb9a5 3847 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3848 else
a90bb9a5 3849 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3850 }
3851
3852 return 0;
3853}
3854
3855static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3856{
3857#define HCLGE_DESC_NUMBER 3
3858#define HCLGE_FUNC_NUMBER_PER_DESC 6
3859 int i, j;
3860
3861 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3862 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3863 if (desc[i].data[j])
3864 return false;
3865
3866 return true;
3867}
3868
d44f9b63 3869static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3870 const u8 *addr)
3871{
3872 const unsigned char *mac_addr = addr;
3873 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3874 (mac_addr[0]) | (mac_addr[1] << 8);
3875 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3876
3877 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3878 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3879}
3880
1db9b1bf
YL		 3881static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3882 const u8 *addr)
46a3df9f
S		 3883{
3884 u16 high_val = addr[1] | (addr[0] << 8);
3885 struct hclge_dev *hdev = vport->back;
3886 u32 rsh = 4 - hdev->mta_mac_sel_type;
3887 u16 ret_val = (high_val >> rsh) & 0xfff;
3888
3889 return ret_val;
3890}
3891
3892static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3893 enum hclge_mta_dmac_sel_type mta_mac_sel,
3894 bool enable)
3895{
d44f9b63 3896 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3897 struct hclge_desc desc;
3898 int ret;
3899
d44f9b63 3900 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3901 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3902
3903 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3904 enable);
3905 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3906 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3907
3908 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3909 if (ret) {
3910 dev_err(&hdev->pdev->dev,
3911 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3912 ret);
3913 return ret;
3914 }
3915
3916 return 0;
3917}
3918
3919int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3920 u8 func_id,
3921 bool enable)
3922{
d44f9b63 3923 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3924 struct hclge_desc desc;
3925 int ret;
3926
d44f9b63 3927 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3928 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3929
3930 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3931 enable);
3932 req->function_id = func_id;
3933
3934 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3935 if (ret) {
3936 dev_err(&hdev->pdev->dev,
3937 "Config func_id enable failed for cmd_send, ret =%d.\n",
3938 ret);
3939 return ret;
3940 }
3941
3942 return 0;
3943}
3944
3945static int hclge_set_mta_table_item(struct hclge_vport *vport,
3946 u16 idx,
3947 bool enable)
3948{
3949 struct hclge_dev *hdev = vport->back;
d44f9b63 3950 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3951 struct hclge_desc desc;
a90bb9a5 3952 u16 item_idx = 0;
46a3df9f
S		 3953 int ret;
3954
d44f9b63 3955 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f
S		 3956 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3957 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3958
a90bb9a5 3959 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
46a3df9f 3960 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3961 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3962
3963 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3964 if (ret) {
3965 dev_err(&hdev->pdev->dev,
3966 "Config mta table item failed for cmd_send, ret =%d.\n",
3967 ret);
3968 return ret;
3969 }
3970
3971 return 0;
3972}
3973
3974static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3975 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3976{
3977 struct hclge_dev *hdev = vport->back;
3978 struct hclge_desc desc;
3979 u8 resp_code;
a90bb9a5 3980 u16 retval;
46a3df9f
S		 3981 int ret;
3982
3983 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3984
d44f9b63 3985 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3986
3987 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3988 if (ret) {
3989 dev_err(&hdev->pdev->dev,
3990 "del mac addr failed for cmd_send, ret =%d.\n",
3991 ret);
3992 return ret;
3993 }
a90bb9a5
YL		 3994 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3995 retval = le16_to_cpu(desc.retval);
46a3df9f 3996
a90bb9a5 3997 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3998 HCLGE_MAC_VLAN_REMOVE);
3999}
4000
4001static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4002 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4003 struct hclge_desc *desc,
4004 bool is_mc)
4005{
4006 struct hclge_dev *hdev = vport->back;
4007 u8 resp_code;
a90bb9a5 4008 u16 retval;
46a3df9f
S		 4009 int ret;
4010
4011 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4012 if (is_mc) {
4013 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4014 memcpy(desc[0].data,
4015 req,
d44f9b63 4016 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4017 hclge_cmd_setup_basic_desc(&desc[1],
4018 HCLGE_OPC_MAC_VLAN_ADD,
4019 true);
4020 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4021 hclge_cmd_setup_basic_desc(&desc[2],
4022 HCLGE_OPC_MAC_VLAN_ADD,
4023 true);
4024 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4025 } else {
4026 memcpy(desc[0].data,
4027 req,
d44f9b63 4028 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 4029 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4030 }
4031 if (ret) {
4032 dev_err(&hdev->pdev->dev,
4033 "lookup mac addr failed for cmd_send, ret =%d.\n",
4034 ret);
4035 return ret;
4036 }
a90bb9a5
YL		 4037 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4038 retval = le16_to_cpu(desc[0].retval);
46a3df9f 4039
a90bb9a5 4040 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 4041 HCLGE_MAC_VLAN_LKUP);
4042}
4043
4044static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 4045 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 4046 struct hclge_desc *mc_desc)
4047{
4048 struct hclge_dev *hdev = vport->back;
4049 int cfg_status;
4050 u8 resp_code;
a90bb9a5 4051 u16 retval;
46a3df9f
S		 4052 int ret;
4053
4054 if (!mc_desc) {
4055 struct hclge_desc desc;
4056
4057 hclge_cmd_setup_basic_desc(&desc,
4058 HCLGE_OPC_MAC_VLAN_ADD,
4059 false);
d44f9b63
YL		 4060 memcpy(desc.data, req,
4061 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4062 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 4063 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4064 retval = le16_to_cpu(desc.retval);
4065
4066 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4067 resp_code,
4068 HCLGE_MAC_VLAN_ADD);
4069 } else {
c3b6f755 4070 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 4071 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4072 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 4073 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 4074 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 4075 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4076 memcpy(mc_desc[0].data, req,
d44f9b63 4077 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 4078 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 4079 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4080 retval = le16_to_cpu(mc_desc[0].retval);
4081
4082 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 4083 resp_code,
4084 HCLGE_MAC_VLAN_ADD);
4085 }
4086
4087 if (ret) {
4088 dev_err(&hdev->pdev->dev,
4089 "add mac addr failed for cmd_send, ret =%d.\n",
4090 ret);
4091 return ret;
4092 }
4093
4094 return cfg_status;
4095}
4096
4097static int hclge_add_uc_addr(struct hnae3_handle *handle,
4098 const unsigned char *addr)
4099{
4100 struct hclge_vport *vport = hclge_get_vport(handle);
4101
4102 return hclge_add_uc_addr_common(vport, addr);
4103}
4104
4105int hclge_add_uc_addr_common(struct hclge_vport *vport,
4106 const unsigned char *addr)
4107{
4108 struct hclge_dev *hdev = vport->back;
d44f9b63 4109 struct hclge_mac_vlan_tbl_entry_cmd req;
d07b6bb4 4110 struct hclge_desc desc;
a90bb9a5 4111 u16 egress_port = 0;
aa7a795e 4112 int ret;
46a3df9f
S		 4113
4114 /* mac addr check */
4115 if (is_zero_ether_addr(addr) ||
4116 is_broadcast_ether_addr(addr) ||
4117 is_multicast_ether_addr(addr)) {
4118 dev_err(&hdev->pdev->dev,
4119 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4120 addr,
4121 is_zero_ether_addr(addr),
4122 is_broadcast_ether_addr(addr),
4123 is_multicast_ether_addr(addr));
4124 return -EINVAL;
4125 }
4126
4127 memset(&req, 0, sizeof(req));
4128 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4129 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4130 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4131 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
a90bb9a5
YL		 4132
4133 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4134 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4135 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
46a3df9f 4136 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5 4137 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
46a3df9f 4138 HCLGE_MAC_EPORT_PFID_S, 0);
a90bb9a5
YL		 4139
4140 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4141
4142 hclge_prepare_mac_addr(&req, addr);
4143
d07b6bb4
JS		 4144 /* Lookup the mac address in the mac_vlan table, and add
4145 * it if the entry is inexistent. Repeated unicast entry
4146 * is not allowed in the mac vlan table.
4147 */
4148 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4149 if (ret == -ENOENT)
4150 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4151
4152 /* check if we just hit the duplicate */
4153 if (!ret)
4154 ret = -EINVAL;
4155
4156 dev_err(&hdev->pdev->dev,
4157 "PF failed to add unicast entry(%pM) in the MAC table\n",
4158 addr);
46a3df9f 4159
aa7a795e 4160 return ret;
46a3df9f
S		 4161}
4162
4163static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4164 const unsigned char *addr)
4165{
4166 struct hclge_vport *vport = hclge_get_vport(handle);
4167
4168 return hclge_rm_uc_addr_common(vport, addr);
4169}
4170
4171int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4172 const unsigned char *addr)
4173{
4174 struct hclge_dev *hdev = vport->back;
d44f9b63 4175 struct hclge_mac_vlan_tbl_entry_cmd req;
aa7a795e 4176 int ret;
46a3df9f
S		 4177
4178 /* mac addr check */
4179 if (is_zero_ether_addr(addr) ||
4180 is_broadcast_ether_addr(addr) ||
4181 is_multicast_ether_addr(addr)) {
4182 dev_dbg(&hdev->pdev->dev,
4183 "Remove mac err! invalid mac:%pM.\n",
4184 addr);
4185 return -EINVAL;
4186 }
4187
4188 memset(&req, 0, sizeof(req));
4189 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4190 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4191 hclge_prepare_mac_addr(&req, addr);
aa7a795e 4192 ret = hclge_remove_mac_vlan_tbl(vport, &req);
46a3df9f 4193
aa7a795e 4194 return ret;
46a3df9f
S		 4195}
4196
4197static int hclge_add_mc_addr(struct hnae3_handle *handle,
4198 const unsigned char *addr)
4199{
4200 struct hclge_vport *vport = hclge_get_vport(handle);
4201
4202 return hclge_add_mc_addr_common(vport, addr);
4203}
4204
4205int hclge_add_mc_addr_common(struct hclge_vport *vport,
4206 const unsigned char *addr)
4207{
4208 struct hclge_dev *hdev = vport->back;
d44f9b63 4209 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4210 struct hclge_desc desc[3];
4211 u16 tbl_idx;
4212 int status;
4213
4214 /* mac addr check */
4215 if (!is_multicast_ether_addr(addr)) {
4216 dev_err(&hdev->pdev->dev,
4217 "Add mc mac err! invalid mac:%pM.\n",
4218 addr);
4219 return -EINVAL;
4220 }
4221 memset(&req, 0, sizeof(req));
4222 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4223 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4224 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4225 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4226 hclge_prepare_mac_addr(&req, addr);
4227 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4228 if (!status) {
4229 /* This mac addr exist, update VFID for it */
4230 hclge_update_desc_vfid(desc, vport->vport_id, false);
4231 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4232 } else {
4233 /* This mac addr do not exist, add new entry for it */
4234 memset(desc[0].data, 0, sizeof(desc[0].data));
4235 memset(desc[1].data, 0, sizeof(desc[0].data));
4236 memset(desc[2].data, 0, sizeof(desc[0].data));
4237 hclge_update_desc_vfid(desc, vport->vport_id, false);
4238 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4239 }
4240
4241 /* Set MTA table for this MAC address */
4242 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4243 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4244
4245 return status;
4246}
4247
4248static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4249 const unsigned char *addr)
4250{
4251 struct hclge_vport *vport = hclge_get_vport(handle);
4252
4253 return hclge_rm_mc_addr_common(vport, addr);
4254}
4255
4256int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4257 const unsigned char *addr)
4258{
4259 struct hclge_dev *hdev = vport->back;
d44f9b63 4260 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4261 enum hclge_cmd_status status;
4262 struct hclge_desc desc[3];
4263 u16 tbl_idx;
4264
4265 /* mac addr check */
4266 if (!is_multicast_ether_addr(addr)) {
4267 dev_dbg(&hdev->pdev->dev,
4268 "Remove mc mac err! invalid mac:%pM.\n",
4269 addr);
4270 return -EINVAL;
4271 }
4272
4273 memset(&req, 0, sizeof(req));
4274 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4275 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4276 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4277 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4278 hclge_prepare_mac_addr(&req, addr);
4279 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4280 if (!status) {
4281 /* This mac addr exist, remove this handle's VFID for it */
4282 hclge_update_desc_vfid(desc, vport->vport_id, true);
4283
4284 if (hclge_is_all_function_id_zero(desc))
4285 /* All the vfid is zero, so need to delete this entry */
4286 status = hclge_remove_mac_vlan_tbl(vport, &req);
4287 else
4288 /* Not all the vfid is zero, update the vfid */
4289 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4290
4291 } else {
4292 /* This mac addr do not exist, can't delete it */
4293 dev_err(&hdev->pdev->dev,
d7629e74 4294 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 4295 status);
4296 return -EIO;
4297 }
4298
4299 /* Set MTB table for this MAC address */
4300 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4301 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4302
4303 return status;
4304}
4305
f5aac71c
FL		 4306static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4307 u16 cmdq_resp, u8 resp_code)
4308{
4309#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4310#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4311#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4312#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4313
4314 int return_status;
4315
4316 if (cmdq_resp) {
4317 dev_err(&hdev->pdev->dev,
4318 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4319 cmdq_resp);
4320 return -EIO;
4321 }
4322
4323 switch (resp_code) {
4324 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4325 case HCLGE_ETHERTYPE_ALREADY_ADD:
4326 return_status = 0;
4327 break;
4328 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4329 dev_err(&hdev->pdev->dev,
4330 "add mac ethertype failed for manager table overflow.\n");
4331 return_status = -EIO;
4332 break;
4333 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4334 dev_err(&hdev->pdev->dev,
4335 "add mac ethertype failed for key conflict.\n");
4336 return_status = -EIO;
4337 break;
4338 default:
4339 dev_err(&hdev->pdev->dev,
4340 "add mac ethertype failed for undefined, code=%d.\n",
4341 resp_code);
4342 return_status = -EIO;
4343 }
4344
4345 return return_status;
4346}
4347
4348static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4349 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4350{
4351 struct hclge_desc desc;
4352 u8 resp_code;
4353 u16 retval;
4354 int ret;
4355
4356 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4357 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4358
4359 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4360 if (ret) {
4361 dev_err(&hdev->pdev->dev,
4362 "add mac ethertype failed for cmd_send, ret =%d.\n",
4363 ret);
4364 return ret;
4365 }
4366
4367 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4368 retval = le16_to_cpu(desc.retval);
4369
4370 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4371}
4372
4373static int init_mgr_tbl(struct hclge_dev *hdev)
4374{
4375 int ret;
4376 int i;
4377
4378 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4379 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4380 if (ret) {
4381 dev_err(&hdev->pdev->dev,
4382 "add mac ethertype failed, ret =%d.\n",
4383 ret);
4384 return ret;
4385 }
4386 }
4387
4388 return 0;
4389}
4390
46a3df9f
S		 4391static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4392{
4393 struct hclge_vport *vport = hclge_get_vport(handle);
4394 struct hclge_dev *hdev = vport->back;
4395
4396 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4397}
4398
59098055
FL		 4399static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4400 bool is_first)
46a3df9f
S		 4401{
4402 const unsigned char *new_addr = (const unsigned char *)p;
4403 struct hclge_vport *vport = hclge_get_vport(handle);
4404 struct hclge_dev *hdev = vport->back;
18838d0c 4405 int ret;
46a3df9f
S		 4406
4407 /* mac addr check */
4408 if (is_zero_ether_addr(new_addr) ||
4409 is_broadcast_ether_addr(new_addr) ||
4410 is_multicast_ether_addr(new_addr)) {
4411 dev_err(&hdev->pdev->dev,
4412 "Change uc mac err! invalid mac:%p.\n",
4413 new_addr);
4414 return -EINVAL;
4415 }
4416
59098055 4417 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 4418 dev_warn(&hdev->pdev->dev,
59098055 4419 "remove old uc mac address fail.\n");
46a3df9f 4420
18838d0c
FL		 4421 ret = hclge_add_uc_addr(handle, new_addr);
4422 if (ret) {
4423 dev_err(&hdev->pdev->dev,
4424 "add uc mac address fail, ret =%d.\n",
4425 ret);
4426
59098055
FL		 4427 if (!is_first &&
4428 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 4429 dev_err(&hdev->pdev->dev,
59098055 4430 "restore uc mac address fail.\n");
18838d0c
FL		 4431
4432 return -EIO;
46a3df9f
S		 4433 }
4434
e98d7183 4435 ret = hclge_pause_addr_cfg(hdev, new_addr);
18838d0c
FL		 4436 if (ret) {
4437 dev_err(&hdev->pdev->dev,
4438 "configure mac pause address fail, ret =%d.\n",
4439 ret);
4440 return -EIO;
4441 }
4442
4443 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4444
4445 return 0;
46a3df9f
S		 4446}
4447
4448static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4449 bool filter_en)
4450{
d44f9b63 4451 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4452 struct hclge_desc desc;
4453 int ret;
4454
4455 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4456
d44f9b63 4457 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4458 req->vlan_type = vlan_type;
4459 req->vlan_fe = filter_en;
4460
4461 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4462 if (ret) {
4463 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4464 ret);
4465 return ret;
4466 }
4467
4468 return 0;
4469}
4470
391b5e93
JS		 4471#define HCLGE_FILTER_TYPE_VF 0
4472#define HCLGE_FILTER_TYPE_PORT 1
4473
4474static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4475{
4476 struct hclge_vport *vport = hclge_get_vport(handle);
4477 struct hclge_dev *hdev = vport->back;
4478
4479 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4480}
4481
46a3df9f
S		 4482int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4483 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4484{
4485#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4486 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4487 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4488 struct hclge_desc desc[2];
4489 u8 vf_byte_val;
4490 u8 vf_byte_off;
4491 int ret;
4492
4493 hclge_cmd_setup_basic_desc(&desc[0],
4494 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4495 hclge_cmd_setup_basic_desc(&desc[1],
4496 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4497
4498 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4499
4500 vf_byte_off = vfid / 8;
4501 vf_byte_val = 1 << (vfid % 8);
4502
d44f9b63
YL		 4503 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4504 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4505
a90bb9a5 4506 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4507 req0->vlan_cfg = is_kill;
4508
4509 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4510 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4511 else
4512 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4513
4514 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4515 if (ret) {
4516 dev_err(&hdev->pdev->dev,
4517 "Send vf vlan command fail, ret =%d.\n",
4518 ret);
4519 return ret;
4520 }
4521
4522 if (!is_kill) {
4523 if (!req0->resp_code || req0->resp_code == 1)
4524 return 0;
4525
4526 dev_err(&hdev->pdev->dev,
4527 "Add vf vlan filter fail, ret =%d.\n",
4528 req0->resp_code);
4529 } else {
4530 if (!req0->resp_code)
4531 return 0;
4532
4533 dev_err(&hdev->pdev->dev,
4534 "Kill vf vlan filter fail, ret =%d.\n",
4535 req0->resp_code);
4536 }
4537
4538 return -EIO;
4539}
4540
4541static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4542 __be16 proto, u16 vlan_id,
4543 bool is_kill)
4544{
4545 struct hclge_vport *vport = hclge_get_vport(handle);
4546 struct hclge_dev *hdev = vport->back;
d44f9b63 4547 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4548 struct hclge_desc desc;
4549 u8 vlan_offset_byte_val;
4550 u8 vlan_offset_byte;
4551 u8 vlan_offset_160;
4552 int ret;
4553
4554 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4555
4556 vlan_offset_160 = vlan_id / 160;
4557 vlan_offset_byte = (vlan_id % 160) / 8;
4558 vlan_offset_byte_val = 1 << (vlan_id % 8);
4559
d44f9b63 4560 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4561 req->vlan_offset = vlan_offset_160;
4562 req->vlan_cfg = is_kill;
4563 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4564
4565 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4566 if (ret) {
4567 dev_err(&hdev->pdev->dev,
4568 "port vlan command, send fail, ret =%d.\n",
4569 ret);
4570 return ret;
4571 }
4572
4573 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4574 if (ret) {
4575 dev_err(&hdev->pdev->dev,
4576 "Set pf vlan filter config fail, ret =%d.\n",
4577 ret);
4578 return -EIO;
4579 }
4580
4581 return 0;
4582}
4583
4584static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4585 u16 vlan, u8 qos, __be16 proto)
4586{
4587 struct hclge_vport *vport = hclge_get_vport(handle);
4588 struct hclge_dev *hdev = vport->back;
4589
4590 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4591 return -EINVAL;
4592 if (proto != htons(ETH_P_8021Q))
4593 return -EPROTONOSUPPORT;
4594
4595 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4596}
4597
5f6ea83f
PL		 4598static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4599{
4600 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4601 struct hclge_vport_vtag_tx_cfg_cmd *req;
4602 struct hclge_dev *hdev = vport->back;
4603 struct hclge_desc desc;
4604 int status;
4605
4606 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4607
4608 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4609 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4610 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4611 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B,
4612 vcfg->accept_tag ? 1 : 0);
4613 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B,
4614 vcfg->accept_untag ? 1 : 0);
4615 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4616 vcfg->insert_tag1_en ? 1 : 0);
4617 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4618 vcfg->insert_tag2_en ? 1 : 0);
4619 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4620
4621 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4622 req->vf_bitmap[req->vf_offset] =
4623 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4624
4625 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4626 if (status)
4627 dev_err(&hdev->pdev->dev,
4628 "Send port txvlan cfg command fail, ret =%d\n",
4629 status);
4630
4631 return status;
4632}
4633
4634static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4635{
4636 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4637 struct hclge_vport_vtag_rx_cfg_cmd *req;
4638 struct hclge_dev *hdev = vport->back;
4639 struct hclge_desc desc;
4640 int status;
4641
4642 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4643
4644 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4645 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4646 vcfg->strip_tag1_en ? 1 : 0);
4647 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4648 vcfg->strip_tag2_en ? 1 : 0);
4649 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4650 vcfg->vlan1_vlan_prionly ? 1 : 0);
4651 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4652 vcfg->vlan2_vlan_prionly ? 1 : 0);
4653
4654 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4655 req->vf_bitmap[req->vf_offset] =
4656 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4657
4658 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4659 if (status)
4660 dev_err(&hdev->pdev->dev,
4661 "Send port rxvlan cfg command fail, ret =%d\n",
4662 status);
4663
4664 return status;
4665}
4666
4667static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4668{
4669 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4670 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4671 struct hclge_desc desc;
4672 int status;
4673
4674 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4675 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4676 rx_req->ot_fst_vlan_type =
4677 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4678 rx_req->ot_sec_vlan_type =
4679 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4680 rx_req->in_fst_vlan_type =
4681 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4682 rx_req->in_sec_vlan_type =
4683 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4684
4685 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4686 if (status) {
4687 dev_err(&hdev->pdev->dev,
4688 "Send rxvlan protocol type command fail, ret =%d\n",
4689 status);
4690 return status;
4691 }
4692
4693 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4694
4695 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4696 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4697 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4698
4699 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4700 if (status)
4701 dev_err(&hdev->pdev->dev,
4702 "Send txvlan protocol type command fail, ret =%d\n",
4703 status);
4704
4705 return status;
4706}
4707
46a3df9f
S		 4708static int hclge_init_vlan_config(struct hclge_dev *hdev)
4709{
5f6ea83f
PL		 4710#define HCLGE_DEF_VLAN_TYPE 0x8100
4711
5e43aef8 4712 struct hnae3_handle *handle;
5f6ea83f 4713 struct hclge_vport *vport;
46a3df9f 4714 int ret;
5f6ea83f
PL		 4715 int i;
4716
4717 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4718 if (ret)
4719 return ret;
46a3df9f 4720
5f6ea83f 4721 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4722 if (ret)
4723 return ret;
4724
5f6ea83f
PL		 4725 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4726 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4727 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4728 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4729 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4730 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4731
4732 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4733 if (ret)
4734 return ret;
46a3df9f 4735
5f6ea83f
PL		 4736 for (i = 0; i < hdev->num_alloc_vport; i++) {
4737 vport = &hdev->vport[i];
4738 vport->txvlan_cfg.accept_tag = true;
4739 vport->txvlan_cfg.accept_untag = true;
4740 vport->txvlan_cfg.insert_tag1_en = false;
4741 vport->txvlan_cfg.insert_tag2_en = false;
4742 vport->txvlan_cfg.default_tag1 = 0;
4743 vport->txvlan_cfg.default_tag2 = 0;
4744
4745 ret = hclge_set_vlan_tx_offload_cfg(vport);
4746 if (ret)
4747 return ret;
4748
4749 vport->rxvlan_cfg.strip_tag1_en = false;
4750 vport->rxvlan_cfg.strip_tag2_en = true;
4751 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4752 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4753
4754 ret = hclge_set_vlan_rx_offload_cfg(vport);
4755 if (ret)
4756 return ret;
4757 }
4758
5e43aef8
L		 4759 handle = &hdev->vport[0].nic;
4760 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4761}
4762
052ece6d
PL		 4763static int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4764{
4765 struct hclge_vport *vport = hclge_get_vport(handle);
4766
4767 vport->rxvlan_cfg.strip_tag1_en = false;
4768 vport->rxvlan_cfg.strip_tag2_en = enable;
4769 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4770 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4771
4772 return hclge_set_vlan_rx_offload_cfg(vport);
4773}
4774
dd72140c 4775static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 4776{
d44f9b63 4777 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 4778 struct hclge_desc desc;
2866ccb2 4779 int max_frm_size;
46a3df9f
S		 4780 int ret;
4781
2866ccb2
FL		 4782 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4783
4784 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4785 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 4786 return -EINVAL;
4787
2866ccb2
FL		 4788 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
4789
46a3df9f
S		 4790 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4791
d44f9b63 4792 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
2866ccb2 4793 req->max_frm_size = cpu_to_le16(max_frm_size);
46a3df9f
S		 4794
4795 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4796 if (ret) {
4797 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4798 return ret;
4799 }
4800
2866ccb2
FL		 4801 hdev->mps = max_frm_size;
4802
46a3df9f
S		 4803 return 0;
4804}
4805
dd72140c
FL		 4806static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4807{
4808 struct hclge_vport *vport = hclge_get_vport(handle);
4809 struct hclge_dev *hdev = vport->back;
4810 int ret;
4811
4812 ret = hclge_set_mac_mtu(hdev, new_mtu);
4813 if (ret) {
4814 dev_err(&hdev->pdev->dev,
4815 "Change mtu fail, ret =%d\n", ret);
4816 return ret;
4817 }
4818
4819 ret = hclge_buffer_alloc(hdev);
4820 if (ret)
4821 dev_err(&hdev->pdev->dev,
4822 "Allocate buffer fail, ret =%d\n", ret);
4823
4824 return ret;
4825}
4826
46a3df9f
S		 4827static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4828 bool enable)
4829{
d44f9b63 4830 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4831 struct hclge_desc desc;
4832 int ret;
4833
4834 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4835
d44f9b63 4836 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4837 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4838 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4839
4840 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4841 if (ret) {
4842 dev_err(&hdev->pdev->dev,
4843 "Send tqp reset cmd error, status =%d\n", ret);
4844 return ret;
4845 }
4846
4847 return 0;
4848}
4849
4850static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4851{
d44f9b63 4852 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4853 struct hclge_desc desc;
4854 int ret;
4855
4856 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4857
d44f9b63 4858 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4859 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4860
4861 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4862 if (ret) {
4863 dev_err(&hdev->pdev->dev,
4864 "Get reset status error, status =%d\n", ret);
4865 return ret;
4866 }
4867
4868 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4869}
4870
814e0274
PL		 4871static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
4872 u16 queue_id)
4873{
4874 struct hnae3_queue *queue;
4875 struct hclge_tqp *tqp;
4876
4877 queue = handle->kinfo.tqp[queue_id];
4878 tqp = container_of(queue, struct hclge_tqp, q);
4879
4880 return tqp->index;
4881}
4882
84e095d6 4883void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 4884{
4885 struct hclge_vport *vport = hclge_get_vport(handle);
4886 struct hclge_dev *hdev = vport->back;
4887 int reset_try_times = 0;
4888 int reset_status;
814e0274 4889 u16 queue_gid;
46a3df9f
S		 4890 int ret;
4891
814e0274
PL		 4892 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
4893
46a3df9f
S		 4894 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4895 if (ret) {
4896 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4897 return;
4898 }
4899
814e0274 4900 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 4901 if (ret) {
4902 dev_warn(&hdev->pdev->dev,
4903 "Send reset tqp cmd fail, ret = %d\n", ret);
4904 return;
4905 }
4906
4907 reset_try_times = 0;
4908 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4909 /* Wait for tqp hw reset */
4910 msleep(20);
814e0274 4911 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 4912 if (reset_status)
4913 break;
4914 }
4915
4916 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4917 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4918 return;
4919 }
4920
814e0274 4921 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 4922 if (ret) {
4923 dev_warn(&hdev->pdev->dev,
4924 "Deassert the soft reset fail, ret = %d\n", ret);
4925 return;
4926 }
4927}
4928
4929static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4930{
4931 struct hclge_vport *vport = hclge_get_vport(handle);
4932 struct hclge_dev *hdev = vport->back;
4933
4934 return hdev->fw_version;
4935}
4936
f34ffffd
PL		 4937static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
4938 u32 *flowctrl_adv)
4939{
4940 struct hclge_vport *vport = hclge_get_vport(handle);
4941 struct hclge_dev *hdev = vport->back;
4942 struct phy_device *phydev = hdev->hw.mac.phydev;
4943
4944 if (!phydev)
4945 return;
4946
4947 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
4948 (phydev->advertising & ADVERTISED_Asym_Pause);
4949}
4950
61387774
PL		 4951static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4952{
4953 struct phy_device *phydev = hdev->hw.mac.phydev;
4954
4955 if (!phydev)
4956 return;
4957
4958 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
4959
4960 if (rx_en)
4961 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
4962
4963 if (tx_en)
4964 phydev->advertising ^= ADVERTISED_Asym_Pause;
4965}
4966
4967static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4968{
61387774
PL		 4969 int ret;
4970
4971 if (rx_en && tx_en)
40173a2e 4972 hdev->fc_mode_last_time = HCLGE_FC_FULL;
61387774 4973 else if (rx_en && !tx_en)
40173a2e 4974 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
61387774 4975 else if (!rx_en && tx_en)
40173a2e 4976 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
61387774 4977 else
40173a2e 4978 hdev->fc_mode_last_time = HCLGE_FC_NONE;
61387774 4979
40173a2e 4980 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
61387774 4981 return 0;
61387774
PL		 4982
4983 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
4984 if (ret) {
4985 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
4986 ret);
4987 return ret;
4988 }
4989
40173a2e 4990 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
61387774
PL		 4991
4992 return 0;
4993}
4994
1770a7a3
PL		 4995int hclge_cfg_flowctrl(struct hclge_dev *hdev)
4996{
4997 struct phy_device *phydev = hdev->hw.mac.phydev;
4998 u16 remote_advertising = 0;
4999 u16 local_advertising = 0;
5000 u32 rx_pause, tx_pause;
5001 u8 flowctl;
5002
5003 if (!phydev->link || !phydev->autoneg)
5004 return 0;
5005
5006 if (phydev->advertising & ADVERTISED_Pause)
5007 local_advertising = ADVERTISE_PAUSE_CAP;
5008
5009 if (phydev->advertising & ADVERTISED_Asym_Pause)
5010 local_advertising |= ADVERTISE_PAUSE_ASYM;
5011
5012 if (phydev->pause)
5013 remote_advertising = LPA_PAUSE_CAP;
5014
5015 if (phydev->asym_pause)
5016 remote_advertising |= LPA_PAUSE_ASYM;
5017
5018 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5019 remote_advertising);
5020 tx_pause = flowctl & FLOW_CTRL_TX;
5021 rx_pause = flowctl & FLOW_CTRL_RX;
5022
5023 if (phydev->duplex == HCLGE_MAC_HALF) {
5024 tx_pause = 0;
5025 rx_pause = 0;
5026 }
5027
5028 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5029}
5030
46a3df9f
S		 5031static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5032 u32 *rx_en, u32 *tx_en)
5033{
5034 struct hclge_vport *vport = hclge_get_vport(handle);
5035 struct hclge_dev *hdev = vport->back;
5036
5037 *auto_neg = hclge_get_autoneg(handle);
5038
5039 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5040 *rx_en = 0;
5041 *tx_en = 0;
5042 return;
5043 }
5044
5045 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5046 *rx_en = 1;
5047 *tx_en = 0;
5048 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5049 *tx_en = 1;
5050 *rx_en = 0;
5051 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5052 *rx_en = 1;
5053 *tx_en = 1;
5054 } else {
5055 *rx_en = 0;
5056 *tx_en = 0;
5057 }
5058}
5059
61387774
PL		 5060static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5061 u32 rx_en, u32 tx_en)
5062{
5063 struct hclge_vport *vport = hclge_get_vport(handle);
5064 struct hclge_dev *hdev = vport->back;
5065 struct phy_device *phydev = hdev->hw.mac.phydev;
5066 u32 fc_autoneg;
5067
5068 /* Only support flow control negotiation for netdev with
5069 * phy attached for now.
5070 */
5071 if (!phydev)
5072 return -EOPNOTSUPP;
5073
5074 fc_autoneg = hclge_get_autoneg(handle);
5075 if (auto_neg != fc_autoneg) {
5076 dev_info(&hdev->pdev->dev,
5077 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5078 return -EOPNOTSUPP;
5079 }
5080
5081 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5082 dev_info(&hdev->pdev->dev,
5083 "Priority flow control enabled. Cannot set link flow control.\n");
5084 return -EOPNOTSUPP;
5085 }
5086
5087 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5088
5089 if (!fc_autoneg)
5090 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5091
5092 return phy_start_aneg(phydev);
5093}
5094
46a3df9f
S		 5095static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5096 u8 *auto_neg, u32 *speed, u8 *duplex)
5097{
5098 struct hclge_vport *vport = hclge_get_vport(handle);
5099 struct hclge_dev *hdev = vport->back;
5100
5101 if (speed)
5102 *speed = hdev->hw.mac.speed;
5103 if (duplex)
5104 *duplex = hdev->hw.mac.duplex;
5105 if (auto_neg)
5106 *auto_neg = hdev->hw.mac.autoneg;
5107}
5108
5109static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5110{
5111 struct hclge_vport *vport = hclge_get_vport(handle);
5112 struct hclge_dev *hdev = vport->back;
5113
5114 if (media_type)
5115 *media_type = hdev->hw.mac.media_type;
5116}
5117
5118static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5119 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5120{
5121 struct hclge_vport *vport = hclge_get_vport(handle);
5122 struct hclge_dev *hdev = vport->back;
5123 struct phy_device *phydev = hdev->hw.mac.phydev;
5124 int mdix_ctrl, mdix, retval, is_resolved;
5125
5126 if (!phydev) {
5127 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5128 *tp_mdix = ETH_TP_MDI_INVALID;
5129 return;
5130 }
5131
5132 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5133
5134 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
5135 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5136 HCLGE_PHY_MDIX_CTRL_S);
5137
5138 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
5139 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5140 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
5141
5142 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5143
5144 switch (mdix_ctrl) {
5145 case 0x0:
5146 *tp_mdix_ctrl = ETH_TP_MDI;
5147 break;
5148 case 0x1:
5149 *tp_mdix_ctrl = ETH_TP_MDI_X;
5150 break;
5151 case 0x3:
5152 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5153 break;
5154 default:
5155 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5156 break;
5157 }
5158
5159 if (!is_resolved)
5160 *tp_mdix = ETH_TP_MDI_INVALID;
5161 else if (mdix)
5162 *tp_mdix = ETH_TP_MDI_X;
5163 else
5164 *tp_mdix = ETH_TP_MDI;
5165}
5166
5167static int hclge_init_client_instance(struct hnae3_client *client,
5168 struct hnae3_ae_dev *ae_dev)
5169{
5170 struct hclge_dev *hdev = ae_dev->priv;
5171 struct hclge_vport *vport;
5172 int i, ret;
5173
5174 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5175 vport = &hdev->vport[i];
5176
5177 switch (client->type) {
5178 case HNAE3_CLIENT_KNIC:
5179
5180 hdev->nic_client = client;
5181 vport->nic.client = client;
5182 ret = client->ops->init_instance(&vport->nic);
5183 if (ret)
5184 goto err;
5185
5186 if (hdev->roce_client &&
e92a0843 5187 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5188 struct hnae3_client *rc = hdev->roce_client;
5189
5190 ret = hclge_init_roce_base_info(vport);
5191 if (ret)
5192 goto err;
5193
5194 ret = rc->ops->init_instance(&vport->roce);
5195 if (ret)
5196 goto err;
5197 }
5198
5199 break;
5200 case HNAE3_CLIENT_UNIC:
5201 hdev->nic_client = client;
5202 vport->nic.client = client;
5203
5204 ret = client->ops->init_instance(&vport->nic);
5205 if (ret)
5206 goto err;
5207
5208 break;
5209 case HNAE3_CLIENT_ROCE:
e92a0843 5210 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5211 hdev->roce_client = client;
5212 vport->roce.client = client;
5213 }
5214
3a46f34d 5215 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5216 ret = hclge_init_roce_base_info(vport);
5217 if (ret)
5218 goto err;
5219
5220 ret = client->ops->init_instance(&vport->roce);
5221 if (ret)
5222 goto err;
5223 }
5224 }
5225 }
5226
5227 return 0;
5228err:
5229 return ret;
5230}
5231
5232static void hclge_uninit_client_instance(struct hnae3_client *client,
5233 struct hnae3_ae_dev *ae_dev)
5234{
5235 struct hclge_dev *hdev = ae_dev->priv;
5236 struct hclge_vport *vport;
5237 int i;
5238
5239 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5240 vport = &hdev->vport[i];
a17dcf3f 5241 if (hdev->roce_client) {
46a3df9f
S		 5242 hdev->roce_client->ops->uninit_instance(&vport->roce,
5243 0);
a17dcf3f
L		 5244 hdev->roce_client = NULL;
5245 vport->roce.client = NULL;
5246 }
46a3df9f
S		 5247 if (client->type == HNAE3_CLIENT_ROCE)
5248 return;
a17dcf3f 5249 if (client->ops->uninit_instance) {
46a3df9f 5250 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5251 hdev->nic_client = NULL;
5252 vport->nic.client = NULL;
5253 }
46a3df9f
S		 5254 }
5255}
5256
5257static int hclge_pci_init(struct hclge_dev *hdev)
5258{
5259 struct pci_dev *pdev = hdev->pdev;
5260 struct hclge_hw *hw;
5261 int ret;
5262
5263 ret = pci_enable_device(pdev);
5264 if (ret) {
5265 dev_err(&pdev->dev, "failed to enable PCI device\n");
5266 goto err_no_drvdata;
5267 }
5268
5269 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5270 if (ret) {
5271 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5272 if (ret) {
5273 dev_err(&pdev->dev,
5274 "can't set consistent PCI DMA");
5275 goto err_disable_device;
5276 }
5277 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5278 }
5279
5280 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5281 if (ret) {
5282 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5283 goto err_disable_device;
5284 }
5285
5286 pci_set_master(pdev);
5287 hw = &hdev->hw;
5288 hw->back = hdev;
5289 hw->io_base = pcim_iomap(pdev, 2, 0);
5290 if (!hw->io_base) {
5291 dev_err(&pdev->dev, "Can't map configuration register space\n");
5292 ret = -ENOMEM;
5293 goto err_clr_master;
5294 }
5295
709eb41a
L		 5296 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5297
46a3df9f
S		 5298 return 0;
5299err_clr_master:
5300 pci_clear_master(pdev);
5301 pci_release_regions(pdev);
5302err_disable_device:
5303 pci_disable_device(pdev);
5304err_no_drvdata:
5305 pci_set_drvdata(pdev, NULL);
5306
5307 return ret;
5308}
5309
5310static void hclge_pci_uninit(struct hclge_dev *hdev)
5311{
5312 struct pci_dev *pdev = hdev->pdev;
5313
887c3820 5314 pci_free_irq_vectors(pdev);
46a3df9f
S		 5315 pci_clear_master(pdev);
5316 pci_release_mem_regions(pdev);
5317 pci_disable_device(pdev);
5318}
5319
5320static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5321{
5322 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5323 struct hclge_dev *hdev;
5324 int ret;
5325
5326 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5327 if (!hdev) {
5328 ret = -ENOMEM;
5329 goto err_hclge_dev;
5330 }
5331
46a3df9f
S		 5332 hdev->pdev = pdev;
5333 hdev->ae_dev = ae_dev;
4ed340ab 5334 hdev->reset_type = HNAE3_NONE_RESET;
cb1b9f77 5335 hdev->reset_request = 0;
ca1d7669 5336 hdev->reset_pending = 0;
46a3df9f
S		 5337 ae_dev->priv = hdev;
5338
46a3df9f
S		 5339 ret = hclge_pci_init(hdev);
5340 if (ret) {
5341 dev_err(&pdev->dev, "PCI init failed\n");
5342 goto err_pci_init;
5343 }
5344
3efb960f
L		 5345 /* Firmware command queue initialize */
5346 ret = hclge_cmd_queue_init(hdev);
5347 if (ret) {
5348 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5349 return ret;
5350 }
5351
5352 /* Firmware command initialize */
46a3df9f
S		 5353 ret = hclge_cmd_init(hdev);
5354 if (ret)
5355 goto err_cmd_init;
5356
5357 ret = hclge_get_cap(hdev);
5358 if (ret) {
e00e2197
CIK		 5359 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5360 ret);
46a3df9f
S		 5361 return ret;
5362 }
5363
5364 ret = hclge_configure(hdev);
5365 if (ret) {
5366 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5367 return ret;
5368 }
5369
887c3820 5370 ret = hclge_init_msi(hdev);
46a3df9f 5371 if (ret) {
887c3820 5372 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
46a3df9f
S		 5373 return ret;
5374 }
5375
466b0c00
L		 5376 ret = hclge_misc_irq_init(hdev);
5377 if (ret) {
5378 dev_err(&pdev->dev,
5379 "Misc IRQ(vector0) init error, ret = %d.\n",
5380 ret);
5381 return ret;
5382 }
5383
46a3df9f
S		 5384 ret = hclge_alloc_tqps(hdev);
5385 if (ret) {
5386 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5387 return ret;
5388 }
5389
5390 ret = hclge_alloc_vport(hdev);
5391 if (ret) {
5392 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5393 return ret;
5394 }
5395
7df7dad6
L		 5396 ret = hclge_map_tqp(hdev);
5397 if (ret) {
5398 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5399 return ret;
5400 }
5401
cf9cca2d 5402 ret = hclge_mac_mdio_config(hdev);
5403 if (ret) {
5404 dev_warn(&hdev->pdev->dev,
5405 "mdio config fail ret=%d\n", ret);
5406 return ret;
5407 }
5408
46a3df9f
S		 5409 ret = hclge_mac_init(hdev);
5410 if (ret) {
5411 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5412 return ret;
5413 }
46a3df9f
S		 5414
5415 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5416 if (ret) {
5417 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5418 return ret;
5419 }
5420
46a3df9f
S		 5421 ret = hclge_init_vlan_config(hdev);
5422 if (ret) {
5423 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5424 return ret;
5425 }
5426
5427 ret = hclge_tm_schd_init(hdev);
5428 if (ret) {
5429 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5430 return ret;
68ece54e
YL		 5431 }
5432
268f5dfa 5433 hclge_rss_init_cfg(hdev);
68ece54e
YL		 5434 ret = hclge_rss_init_hw(hdev);
5435 if (ret) {
5436 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5437 return ret;
46a3df9f
S		 5438 }
5439
f5aac71c
FL		 5440 ret = init_mgr_tbl(hdev);
5441 if (ret) {
5442 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
5443 return ret;
5444 }
5445
cacde272
YL		 5446 hclge_dcb_ops_set(hdev);
5447
d039ef68 5448 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5449 INIT_WORK(&hdev->service_task, hclge_service_task);
cb1b9f77 5450 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
c1a81619 5451 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5452
466b0c00
L		 5453 /* Enable MISC vector(vector0) */
5454 hclge_enable_vector(&hdev->misc_vector, true);
5455
46a3df9f
S		 5456 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5457 set_bit(HCLGE_STATE_DOWN, &hdev->state);
cb1b9f77
SM		 5458 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5459 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
c1a81619
SM		 5460 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5461 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
46a3df9f
S		 5462
5463 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5464 return 0;
5465
5466err_cmd_init:
5467 pci_release_regions(pdev);
5468err_pci_init:
5469 pci_set_drvdata(pdev, NULL);
5470err_hclge_dev:
5471 return ret;
5472}
5473
c6dc5213 5474static void hclge_stats_clear(struct hclge_dev *hdev)
5475{
5476 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5477}
5478
4ed340ab
L		 5479static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5480{
5481 struct hclge_dev *hdev = ae_dev->priv;
5482 struct pci_dev *pdev = ae_dev->pdev;
5483 int ret;
5484
5485 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5486
c6dc5213 5487 hclge_stats_clear(hdev);
5488
4ed340ab
L		 5489 ret = hclge_cmd_init(hdev);
5490 if (ret) {
5491 dev_err(&pdev->dev, "Cmd queue init failed\n");
5492 return ret;
5493 }
5494
5495 ret = hclge_get_cap(hdev);
5496 if (ret) {
5497 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5498 ret);
5499 return ret;
5500 }
5501
5502 ret = hclge_configure(hdev);
5503 if (ret) {
5504 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5505 return ret;
5506 }
5507
5508 ret = hclge_map_tqp(hdev);
5509 if (ret) {
5510 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5511 return ret;
5512 }
5513
5514 ret = hclge_mac_init(hdev);
5515 if (ret) {
5516 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5517 return ret;
5518 }
5519
4ed340ab
L		 5520 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5521 if (ret) {
5522 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5523 return ret;
5524 }
5525
5526 ret = hclge_init_vlan_config(hdev);
5527 if (ret) {
5528 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5529 return ret;
5530 }
5531
f31c1ba6 5532 ret = hclge_tm_init_hw(hdev);
4ed340ab 5533 if (ret) {
f31c1ba6 5534 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 5535 return ret;
5536 }
5537
5538 ret = hclge_rss_init_hw(hdev);
5539 if (ret) {
5540 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5541 return ret;
5542 }
5543
5544 /* Enable MISC vector(vector0) */
5545 hclge_enable_vector(&hdev->misc_vector, true);
5546
5547 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5548 HCLGE_DRIVER_NAME);
5549
5550 return 0;
5551}
5552
46a3df9f
S		 5553static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5554{
5555 struct hclge_dev *hdev = ae_dev->priv;
5556 struct hclge_mac *mac = &hdev->hw.mac;
5557
5558 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5559
2a32ca13
AB		 5560 if (IS_ENABLED(CONFIG_PCI_IOV))
5561 hclge_disable_sriov(hdev);
46a3df9f 5562
d039ef68 5563 if (hdev->service_timer.function)
46a3df9f
S		 5564 del_timer_sync(&hdev->service_timer);
5565 if (hdev->service_task.func)
5566 cancel_work_sync(&hdev->service_task);
cb1b9f77
SM		 5567 if (hdev->rst_service_task.func)
5568 cancel_work_sync(&hdev->rst_service_task);
c1a81619
SM		 5569 if (hdev->mbx_service_task.func)
5570 cancel_work_sync(&hdev->mbx_service_task);
46a3df9f
S		 5571
5572 if (mac->phydev)
5573 mdiobus_unregister(mac->mdio_bus);
5574
466b0c00
L		 5575 /* Disable MISC vector(vector0) */
5576 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 5577 hclge_destroy_cmd_queue(&hdev->hw);
ca1d7669 5578 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5579 hclge_pci_uninit(hdev);
5580 ae_dev->priv = NULL;
5581}
5582
482d2e9c
PL		 5583static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5584{
5585 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5586 struct hclge_vport *vport = hclge_get_vport(handle);
5587 struct hclge_dev *hdev = vport->back;
5588
5589 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5590}
5591
5592static void hclge_get_channels(struct hnae3_handle *handle,
5593 struct ethtool_channels *ch)
5594{
5595 struct hclge_vport *vport = hclge_get_vport(handle);
5596
5597 ch->max_combined = hclge_get_max_channels(handle);
5598 ch->other_count = 1;
5599 ch->max_other = 1;
5600 ch->combined_count = vport->alloc_tqps;
5601}
5602
09f2af64
PL		 5603static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5604 u16 *free_tqps, u16 *max_rss_size)
5605{
5606 struct hclge_vport *vport = hclge_get_vport(handle);
5607 struct hclge_dev *hdev = vport->back;
5608 u16 temp_tqps = 0;
5609 int i;
5610
5611 for (i = 0; i < hdev->num_tqps; i++) {
5612 if (!hdev->htqp[i].alloced)
5613 temp_tqps++;
5614 }
5615 *free_tqps = temp_tqps;
5616 *max_rss_size = hdev->rss_size_max;
5617}
5618
5619static void hclge_release_tqp(struct hclge_vport *vport)
5620{
5621 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5622 struct hclge_dev *hdev = vport->back;
5623 int i;
5624
5625 for (i = 0; i < kinfo->num_tqps; i++) {
5626 struct hclge_tqp *tqp =
5627 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5628
5629 tqp->q.handle = NULL;
5630 tqp->q.tqp_index = 0;
5631 tqp->alloced = false;
5632 }
5633
5634 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5635 kinfo->tqp = NULL;
5636}
5637
5638static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5639{
5640 struct hclge_vport *vport = hclge_get_vport(handle);
5641 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5642 struct hclge_dev *hdev = vport->back;
5643 int cur_rss_size = kinfo->rss_size;
5644 int cur_tqps = kinfo->num_tqps;
5645 u16 tc_offset[HCLGE_MAX_TC_NUM];
5646 u16 tc_valid[HCLGE_MAX_TC_NUM];
5647 u16 tc_size[HCLGE_MAX_TC_NUM];
5648 u16 roundup_size;
5649 u32 *rss_indir;
5650 int ret, i;
5651
5652 hclge_release_tqp(vport);
5653
5654 ret = hclge_knic_setup(vport, new_tqps_num);
5655 if (ret) {
5656 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5657 return ret;
5658 }
5659
5660 ret = hclge_map_tqp_to_vport(hdev, vport);
5661 if (ret) {
5662 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5663 return ret;
5664 }
5665
5666 ret = hclge_tm_schd_init(hdev);
5667 if (ret) {
5668 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5669 return ret;
5670 }
5671
5672 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5673 roundup_size = ilog2(roundup_size);
5674 /* Set the RSS TC mode according to the new RSS size */
5675 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5676 tc_valid[i] = 0;
5677
5678 if (!(hdev->hw_tc_map & BIT(i)))
5679 continue;
5680
5681 tc_valid[i] = 1;
5682 tc_size[i] = roundup_size;
5683 tc_offset[i] = kinfo->rss_size * i;
5684 }
5685 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5686 if (ret)
5687 return ret;
5688
5689 /* Reinitializes the rss indirect table according to the new RSS size */
5690 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5691 if (!rss_indir)
5692 return -ENOMEM;
5693
5694 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5695 rss_indir[i] = i % kinfo->rss_size;
5696
5697 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5698 if (ret)
5699 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5700 ret);
5701
5702 kfree(rss_indir);
5703
5704 if (!ret)
5705 dev_info(&hdev->pdev->dev,
5706 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5707 cur_rss_size, kinfo->rss_size,
5708 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5709
5710 return ret;
5711}
5712
77b34110
FL		 5713static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5714 u32 *regs_num_64_bit)
5715{
5716 struct hclge_desc desc;
5717 u32 total_num;
5718 int ret;
5719
5720 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5721 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5722 if (ret) {
5723 dev_err(&hdev->pdev->dev,
5724 "Query register number cmd failed, ret = %d.\n", ret);
5725 return ret;
5726 }
5727
5728 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5729 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5730
5731 total_num = *regs_num_32_bit + *regs_num_64_bit;
5732 if (!total_num)
5733 return -EINVAL;
5734
5735 return 0;
5736}
5737
5738static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5739 void *data)
5740{
5741#define HCLGE_32_BIT_REG_RTN_DATANUM 8
5742
5743 struct hclge_desc *desc;
5744 u32 *reg_val = data;
5745 __le32 *desc_data;
5746 int cmd_num;
5747 int i, k, n;
5748 int ret;
5749
5750 if (regs_num == 0)
5751 return 0;
5752
5753 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
5754 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5755 if (!desc)
5756 return -ENOMEM;
5757
5758 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
5759 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5760 if (ret) {
5761 dev_err(&hdev->pdev->dev,
5762 "Query 32 bit register cmd failed, ret = %d.\n", ret);
5763 kfree(desc);
5764 return ret;
5765 }
5766
5767 for (i = 0; i < cmd_num; i++) {
5768 if (i == 0) {
5769 desc_data = (__le32 *)(&desc[i].data[0]);
5770 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
5771 } else {
5772 desc_data = (__le32 *)(&desc[i]);
5773 n = HCLGE_32_BIT_REG_RTN_DATANUM;
5774 }
5775 for (k = 0; k < n; k++) {
5776 *reg_val++ = le32_to_cpu(*desc_data++);
5777
5778 regs_num--;
5779 if (!regs_num)
5780 break;
5781 }
5782 }
5783
5784 kfree(desc);
5785 return 0;
5786}
5787
5788static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5789 void *data)
5790{
5791#define HCLGE_64_BIT_REG_RTN_DATANUM 4
5792
5793 struct hclge_desc *desc;
5794 u64 *reg_val = data;
5795 __le64 *desc_data;
5796 int cmd_num;
5797 int i, k, n;
5798 int ret;
5799
5800 if (regs_num == 0)
5801 return 0;
5802
5803 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
5804 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5805 if (!desc)
5806 return -ENOMEM;
5807
5808 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
5809 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5810 if (ret) {
5811 dev_err(&hdev->pdev->dev,
5812 "Query 64 bit register cmd failed, ret = %d.\n", ret);
5813 kfree(desc);
5814 return ret;
5815 }
5816
5817 for (i = 0; i < cmd_num; i++) {
5818 if (i == 0) {
5819 desc_data = (__le64 *)(&desc[i].data[0]);
5820 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
5821 } else {
5822 desc_data = (__le64 *)(&desc[i]);
5823 n = HCLGE_64_BIT_REG_RTN_DATANUM;
5824 }
5825 for (k = 0; k < n; k++) {
5826 *reg_val++ = le64_to_cpu(*desc_data++);
5827
5828 regs_num--;
5829 if (!regs_num)
5830 break;
5831 }
5832 }
5833
5834 kfree(desc);
5835 return 0;
5836}
5837
5838static int hclge_get_regs_len(struct hnae3_handle *handle)
5839{
5840 struct hclge_vport *vport = hclge_get_vport(handle);
5841 struct hclge_dev *hdev = vport->back;
5842 u32 regs_num_32_bit, regs_num_64_bit;
5843 int ret;
5844
5845 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5846 if (ret) {
5847 dev_err(&hdev->pdev->dev,
5848 "Get register number failed, ret = %d.\n", ret);
5849 return -EOPNOTSUPP;
5850 }
5851
5852 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
5853}
5854
5855static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
5856 void *data)
5857{
5858 struct hclge_vport *vport = hclge_get_vport(handle);
5859 struct hclge_dev *hdev = vport->back;
5860 u32 regs_num_32_bit, regs_num_64_bit;
5861 int ret;
5862
5863 *version = hdev->fw_version;
5864
5865 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5866 if (ret) {
5867 dev_err(&hdev->pdev->dev,
5868 "Get register number failed, ret = %d.\n", ret);
5869 return;
5870 }
5871
5872 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
5873 if (ret) {
5874 dev_err(&hdev->pdev->dev,
5875 "Get 32 bit register failed, ret = %d.\n", ret);
5876 return;
5877 }
5878
5879 data = (u32 *)data + regs_num_32_bit;
5880 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
5881 data);
5882 if (ret)
5883 dev_err(&hdev->pdev->dev,
5884 "Get 64 bit register failed, ret = %d.\n", ret);
5885}
5886
07f8e940
JS		 5887static int hclge_set_led_status_sfp(struct hclge_dev *hdev, u8 speed_led_status,
5888 u8 act_led_status, u8 link_led_status,
5889 u8 locate_led_status)
5890{
5891 struct hclge_set_led_state_cmd *req;
5892 struct hclge_desc desc;
5893 int ret;
5894
5895 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
5896
5897 req = (struct hclge_set_led_state_cmd *)desc.data;
5898 hnae_set_field(req->port_speed_led_config, HCLGE_LED_PORT_SPEED_STATE_M,
5899 HCLGE_LED_PORT_SPEED_STATE_S, speed_led_status);
5900 hnae_set_field(req->link_led_config, HCLGE_LED_ACTIVITY_STATE_M,
5901 HCLGE_LED_ACTIVITY_STATE_S, act_led_status);
5902 hnae_set_field(req->activity_led_config, HCLGE_LED_LINK_STATE_M,
5903 HCLGE_LED_LINK_STATE_S, link_led_status);
5904 hnae_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
5905 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
5906
5907 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5908 if (ret)
5909 dev_err(&hdev->pdev->dev,
5910 "Send set led state cmd error, ret =%d\n", ret);
5911
5912 return ret;
5913}
5914
5915enum hclge_led_status {
5916 HCLGE_LED_OFF,
5917 HCLGE_LED_ON,
5918 HCLGE_LED_NO_CHANGE = 0xFF,
5919};
5920
5921static int hclge_set_led_id(struct hnae3_handle *handle,
5922 enum ethtool_phys_id_state status)
5923{
5924#define BLINK_FREQUENCY 2
5925 struct hclge_vport *vport = hclge_get_vport(handle);
5926 struct hclge_dev *hdev = vport->back;
5927 struct phy_device *phydev = hdev->hw.mac.phydev;
5928 int ret = 0;
5929
5930 if (phydev || hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
5931 return -EOPNOTSUPP;
5932
5933 switch (status) {
5934 case ETHTOOL_ID_ACTIVE:
5935 ret = hclge_set_led_status_sfp(hdev,
5936 HCLGE_LED_NO_CHANGE,
5937 HCLGE_LED_NO_CHANGE,
5938 HCLGE_LED_NO_CHANGE,
5939 HCLGE_LED_ON);
5940 break;
5941 case ETHTOOL_ID_INACTIVE:
5942 ret = hclge_set_led_status_sfp(hdev,
5943 HCLGE_LED_NO_CHANGE,
5944 HCLGE_LED_NO_CHANGE,
5945 HCLGE_LED_NO_CHANGE,
5946 HCLGE_LED_OFF);
5947 break;
5948 default:
5949 ret = -EINVAL;
5950 break;
5951 }
5952
5953 return ret;
5954}
5955
716aaac1
JS		 5956enum hclge_led_port_speed {
5957 HCLGE_SPEED_LED_FOR_1G,
5958 HCLGE_SPEED_LED_FOR_10G,
5959 HCLGE_SPEED_LED_FOR_25G,
5960 HCLGE_SPEED_LED_FOR_40G,
5961 HCLGE_SPEED_LED_FOR_50G,
5962 HCLGE_SPEED_LED_FOR_100G,
5963};
5964
5965static u8 hclge_led_get_speed_status(u32 speed)
5966{
5967 u8 speed_led;
5968
5969 switch (speed) {
5970 case HCLGE_MAC_SPEED_1G:
5971 speed_led = HCLGE_SPEED_LED_FOR_1G;
5972 break;
5973 case HCLGE_MAC_SPEED_10G:
5974 speed_led = HCLGE_SPEED_LED_FOR_10G;
5975 break;
5976 case HCLGE_MAC_SPEED_25G:
5977 speed_led = HCLGE_SPEED_LED_FOR_25G;
5978 break;
5979 case HCLGE_MAC_SPEED_40G:
5980 speed_led = HCLGE_SPEED_LED_FOR_40G;
5981 break;
5982 case HCLGE_MAC_SPEED_50G:
5983 speed_led = HCLGE_SPEED_LED_FOR_50G;
5984 break;
5985 case HCLGE_MAC_SPEED_100G:
5986 speed_led = HCLGE_SPEED_LED_FOR_100G;
5987 break;
5988 default:
5989 speed_led = HCLGE_LED_NO_CHANGE;
5990 }
5991
5992 return speed_led;
5993}
5994
5995static int hclge_update_led_status(struct hclge_dev *hdev)
5996{
5997 u8 port_speed_status, link_status, activity_status;
5998 u64 rx_pkts, tx_pkts;
5999
6000 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER)
6001 return 0;
6002
6003 port_speed_status = hclge_led_get_speed_status(hdev->hw.mac.speed);
6004
6005 rx_pkts = hdev->hw_stats.mac_stats.mac_rx_total_pkt_num;
6006 tx_pkts = hdev->hw_stats.mac_stats.mac_tx_total_pkt_num;
6007 if (rx_pkts != hdev->rx_pkts_for_led ||
6008 tx_pkts != hdev->tx_pkts_for_led)
6009 activity_status = HCLGE_LED_ON;
6010 else
6011 activity_status = HCLGE_LED_OFF;
6012 hdev->rx_pkts_for_led = rx_pkts;
6013 hdev->tx_pkts_for_led = tx_pkts;
6014
6015 if (hdev->hw.mac.link)
6016 link_status = HCLGE_LED_ON;
6017 else
6018 link_status = HCLGE_LED_OFF;
6019
6020 return hclge_set_led_status_sfp(hdev, port_speed_status,
6021 activity_status, link_status,
6022 HCLGE_LED_NO_CHANGE);
6023}
6024
46a3df9f
S		 6025static const struct hnae3_ae_ops hclge_ops = {
6026 .init_ae_dev = hclge_init_ae_dev,
6027 .uninit_ae_dev = hclge_uninit_ae_dev,
6028 .init_client_instance = hclge_init_client_instance,
6029 .uninit_client_instance = hclge_uninit_client_instance,
84e095d6
SM		 6030 .map_ring_to_vector = hclge_map_ring_to_vector,
6031 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 6032 .get_vector = hclge_get_vector,
0d3e6631 6033 .put_vector = hclge_put_vector,
46a3df9f 6034 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 6035 .set_loopback = hclge_set_loopback,
46a3df9f
S		 6036 .start = hclge_ae_start,
6037 .stop = hclge_ae_stop,
6038 .get_status = hclge_get_status,
6039 .get_ksettings_an_result = hclge_get_ksettings_an_result,
6040 .update_speed_duplex_h = hclge_update_speed_duplex_h,
6041 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6042 .get_media_type = hclge_get_media_type,
6043 .get_rss_key_size = hclge_get_rss_key_size,
6044 .get_rss_indir_size = hclge_get_rss_indir_size,
6045 .get_rss = hclge_get_rss,
6046 .set_rss = hclge_set_rss,
f7db940a 6047 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 6048 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 6049 .get_tc_size = hclge_get_tc_size,
6050 .get_mac_addr = hclge_get_mac_addr,
6051 .set_mac_addr = hclge_set_mac_addr,
6052 .add_uc_addr = hclge_add_uc_addr,
6053 .rm_uc_addr = hclge_rm_uc_addr,
6054 .add_mc_addr = hclge_add_mc_addr,
6055 .rm_mc_addr = hclge_rm_mc_addr,
6056 .set_autoneg = hclge_set_autoneg,
6057 .get_autoneg = hclge_get_autoneg,
6058 .get_pauseparam = hclge_get_pauseparam,
61387774 6059 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6060 .set_mtu = hclge_set_mtu,
6061 .reset_queue = hclge_reset_tqp,
6062 .get_stats = hclge_get_stats,
6063 .update_stats = hclge_update_stats,
6064 .get_strings = hclge_get_strings,
6065 .get_sset_count = hclge_get_sset_count,
6066 .get_fw_version = hclge_get_fw_version,
6067 .get_mdix_mode = hclge_get_mdix_mode,
391b5e93 6068 .enable_vlan_filter = hclge_enable_vlan_filter,
46a3df9f
S		 6069 .set_vlan_filter = hclge_set_port_vlan_filter,
6070 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
052ece6d 6071 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6072 .reset_event = hclge_reset_event,
09f2af64
PL		 6073 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6074 .set_channels = hclge_set_channels,
482d2e9c 6075 .get_channels = hclge_get_channels,
f34ffffd 6076 .get_flowctrl_adv = hclge_get_flowctrl_adv,
77b34110
FL		 6077 .get_regs_len = hclge_get_regs_len,
6078 .get_regs = hclge_get_regs,
07f8e940 6079 .set_led_id = hclge_set_led_id,
46a3df9f
S		 6080};
6081
6082static struct hnae3_ae_algo ae_algo = {
6083 .ops = &hclge_ops,
6084 .name = HCLGE_NAME,
6085 .pdev_id_table = ae_algo_pci_tbl,
6086};
6087
6088static int hclge_init(void)
6089{
6090 pr_info("%s is initializing\n", HCLGE_NAME);
6091
6092 return hnae3_register_ae_algo(&ae_algo);
6093}
6094
6095static void hclge_exit(void)
6096{
6097 hnae3_unregister_ae_algo(&ae_algo);
6098}
6099module_init(hclge_init);
6100module_exit(hclge_exit);
6101
6102MODULE_LICENSE("GPL");
6103MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6104MODULE_DESCRIPTION("HCLGE Driver");
6105MODULE_VERSION(HCLGE_MOD_VERSION);
Ubuntu Eoan Linux kernel mirror