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Commit | Line | Data |
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46a3df9f S |
1 | /* |
2 | * Copyright (c) 2016~2017 Hisilicon Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #ifndef __HCLGE_MAIN_H | |
11 | #define __HCLGE_MAIN_H | |
12 | #include <linux/fs.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/phy.h> | |
dc8131d8 YL |
15 | #include <linux/if_vlan.h> |
16 | ||
46a3df9f S |
17 | #include "hclge_cmd.h" |
18 | #include "hnae3.h" | |
19 | ||
3c7624d8 | 20 | #define HCLGE_MOD_VERSION "1.0" |
46a3df9f S |
21 | #define HCLGE_DRIVER_NAME "hclge" |
22 | ||
23 | #define HCLGE_INVALID_VPORT 0xffff | |
24 | ||
25 | #define HCLGE_ROCE_VECTOR_OFFSET 96 | |
26 | ||
27 | #define HCLGE_PF_CFG_BLOCK_SIZE 32 | |
28 | #define HCLGE_PF_CFG_DESC_NUM \ | |
29 | (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) | |
30 | ||
31 | #define HCLGE_VECTOR_REG_BASE 0x20000 | |
466b0c00 | 32 | #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 |
46a3df9f S |
33 | |
34 | #define HCLGE_VECTOR_REG_OFFSET 0x4 | |
35 | #define HCLGE_VECTOR_VF_OFFSET 0x100000 | |
36 | ||
37 | #define HCLGE_RSS_IND_TBL_SIZE 512 | |
5392902d | 38 | #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) |
46a3df9f S |
39 | #define HCLGE_RSS_KEY_SIZE 40 |
40 | #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 | |
41 | #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 | |
42 | #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 | |
43 | #define HCLGE_RSS_HASH_ALGO_MASK 0xf | |
44 | #define HCLGE_RSS_CFG_TBL_NUM \ | |
45 | (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE) | |
46 | ||
f7db940a L |
47 | #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) |
48 | #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) | |
49 | #define HCLGE_D_PORT_BIT BIT(0) | |
50 | #define HCLGE_S_PORT_BIT BIT(1) | |
51 | #define HCLGE_D_IP_BIT BIT(2) | |
52 | #define HCLGE_S_IP_BIT BIT(3) | |
53 | #define HCLGE_V_TAG_BIT BIT(4) | |
54 | ||
46a3df9f S |
55 | #define HCLGE_RSS_TC_SIZE_0 1 |
56 | #define HCLGE_RSS_TC_SIZE_1 2 | |
57 | #define HCLGE_RSS_TC_SIZE_2 4 | |
58 | #define HCLGE_RSS_TC_SIZE_3 8 | |
59 | #define HCLGE_RSS_TC_SIZE_4 16 | |
60 | #define HCLGE_RSS_TC_SIZE_5 32 | |
61 | #define HCLGE_RSS_TC_SIZE_6 64 | |
62 | #define HCLGE_RSS_TC_SIZE_7 128 | |
63 | ||
40cca1c5 XW |
64 | #define HCLGE_MTA_TBL_SIZE 4096 |
65 | ||
46a3df9f S |
66 | #define HCLGE_TQP_RESET_TRY_TIMES 10 |
67 | ||
68 | #define HCLGE_PHY_PAGE_MDIX 0 | |
69 | #define HCLGE_PHY_PAGE_COPPER 0 | |
70 | ||
71 | /* Page Selection Reg. */ | |
72 | #define HCLGE_PHY_PAGE_REG 22 | |
73 | ||
74 | /* Copper Specific Control Register */ | |
75 | #define HCLGE_PHY_CSC_REG 16 | |
76 | ||
77 | /* Copper Specific Status Register */ | |
78 | #define HCLGE_PHY_CSS_REG 17 | |
79 | ||
a10829c4 | 80 | #define HCLGE_PHY_MDIX_CTRL_S 5 |
5392902d | 81 | #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) |
46a3df9f | 82 | |
a10829c4 JS |
83 | #define HCLGE_PHY_MDIX_STATUS_B 6 |
84 | #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 | |
46a3df9f | 85 | |
5f6ea83f PL |
86 | /* Factor used to calculate offset and bitmap of VF num */ |
87 | #define HCLGE_VF_NUM_PER_CMD 64 | |
88 | #define HCLGE_VF_NUM_PER_BYTE 8 | |
89 | ||
4ed340ab L |
90 | /* Reset related Registers */ |
91 | #define HCLGE_MISC_RESET_STS_REG 0x20700 | |
9ca8d1a7 | 92 | #define HCLGE_MISC_VECTOR_INT_STS 0x20800 |
4ed340ab L |
93 | #define HCLGE_GLOBAL_RESET_REG 0x20A00 |
94 | #define HCLGE_GLOBAL_RESET_BIT 0x0 | |
95 | #define HCLGE_CORE_RESET_BIT 0x1 | |
96 | #define HCLGE_FUN_RST_ING 0x20C00 | |
97 | #define HCLGE_FUN_RST_ING_B 0 | |
98 | ||
99 | /* Vector0 register bits define */ | |
100 | #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 | |
101 | #define HCLGE_VECTOR0_CORERESET_INT_B 6 | |
102 | #define HCLGE_VECTOR0_IMPRESET_INT_B 7 | |
103 | ||
c1a81619 SM |
104 | /* Vector0 interrupt CMDQ event source register(RW) */ |
105 | #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 | |
106 | /* CMDQ register bits for RX event(=MBX event) */ | |
107 | #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 | |
108 | ||
2866ccb2 FL |
109 | #define HCLGE_MAC_DEFAULT_FRAME \ |
110 | (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN + ETH_DATA_LEN) | |
111 | #define HCLGE_MAC_MIN_FRAME 64 | |
112 | #define HCLGE_MAC_MAX_FRAME 9728 | |
113 | ||
0979aa0b FL |
114 | #define HCLGE_SUPPORT_1G_BIT BIT(0) |
115 | #define HCLGE_SUPPORT_10G_BIT BIT(1) | |
116 | #define HCLGE_SUPPORT_25G_BIT BIT(2) | |
117 | #define HCLGE_SUPPORT_50G_BIT BIT(3) | |
118 | #define HCLGE_SUPPORT_100G_BIT BIT(4) | |
119 | ||
46a3df9f S |
120 | enum HCLGE_DEV_STATE { |
121 | HCLGE_STATE_REINITING, | |
122 | HCLGE_STATE_DOWN, | |
123 | HCLGE_STATE_DISABLED, | |
124 | HCLGE_STATE_REMOVING, | |
125 | HCLGE_STATE_SERVICE_INITED, | |
126 | HCLGE_STATE_SERVICE_SCHED, | |
cb1b9f77 SM |
127 | HCLGE_STATE_RST_SERVICE_SCHED, |
128 | HCLGE_STATE_RST_HANDLING, | |
c1a81619 | 129 | HCLGE_STATE_MBX_SERVICE_SCHED, |
46a3df9f | 130 | HCLGE_STATE_MBX_HANDLING, |
c5f65480 | 131 | HCLGE_STATE_STATISTICS_UPDATING, |
8d40854f | 132 | HCLGE_STATE_CMD_DISABLE, |
46a3df9f S |
133 | HCLGE_STATE_MAX |
134 | }; | |
135 | ||
ca1d7669 SM |
136 | enum hclge_evt_cause { |
137 | HCLGE_VECTOR0_EVENT_RST, | |
138 | HCLGE_VECTOR0_EVENT_MBX, | |
139 | HCLGE_VECTOR0_EVENT_OTHER, | |
140 | }; | |
141 | ||
46a3df9f S |
142 | #define HCLGE_MPF_ENBALE 1 |
143 | struct hclge_caps { | |
144 | u16 num_tqp; | |
145 | u16 num_buffer_cell; | |
146 | u32 flag; | |
147 | u16 vmdq; | |
148 | }; | |
149 | ||
150 | enum HCLGE_MAC_SPEED { | |
151 | HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ | |
152 | HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ | |
153 | HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ | |
154 | HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ | |
155 | HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ | |
156 | HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ | |
157 | HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ | |
158 | HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */ | |
159 | }; | |
160 | ||
161 | enum HCLGE_MAC_DUPLEX { | |
162 | HCLGE_MAC_HALF, | |
163 | HCLGE_MAC_FULL | |
164 | }; | |
165 | ||
166 | enum hclge_mta_dmac_sel_type { | |
167 | HCLGE_MAC_ADDR_47_36, | |
168 | HCLGE_MAC_ADDR_46_35, | |
169 | HCLGE_MAC_ADDR_45_34, | |
170 | HCLGE_MAC_ADDR_44_33, | |
171 | }; | |
172 | ||
173 | struct hclge_mac { | |
174 | u8 phy_addr; | |
175 | u8 flag; | |
176 | u8 media_type; | |
177 | u8 mac_addr[ETH_ALEN]; | |
178 | u8 autoneg; | |
179 | u8 duplex; | |
180 | u32 speed; | |
181 | int link; /* store the link status of mac & phy (if phy exit)*/ | |
182 | struct phy_device *phydev; | |
183 | struct mii_bus *mdio_bus; | |
184 | phy_interface_t phy_if; | |
0979aa0b FL |
185 | __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); |
186 | __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); | |
46a3df9f S |
187 | }; |
188 | ||
189 | struct hclge_hw { | |
190 | void __iomem *io_base; | |
191 | struct hclge_mac mac; | |
192 | int num_vec; | |
193 | struct hclge_cmq cmq; | |
194 | struct hclge_caps caps; | |
46a3df9f S |
195 | }; |
196 | ||
197 | /* TQP stats */ | |
198 | struct hlcge_tqp_stats { | |
199 | /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ | |
200 | u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ | |
201 | /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ | |
202 | u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ | |
203 | }; | |
204 | ||
205 | struct hclge_tqp { | |
206 | struct device *dev; /* Device for DMA mapping */ | |
207 | struct hnae3_queue q; | |
208 | struct hlcge_tqp_stats tqp_stats; | |
209 | u16 index; /* Global index in a NIC controller */ | |
210 | ||
211 | bool alloced; | |
212 | }; | |
213 | ||
214 | enum hclge_fc_mode { | |
215 | HCLGE_FC_NONE, | |
216 | HCLGE_FC_RX_PAUSE, | |
217 | HCLGE_FC_TX_PAUSE, | |
218 | HCLGE_FC_FULL, | |
219 | HCLGE_FC_PFC, | |
220 | HCLGE_FC_DEFAULT | |
221 | }; | |
222 | ||
223 | #define HCLGE_PG_NUM 4 | |
224 | #define HCLGE_SCH_MODE_SP 0 | |
225 | #define HCLGE_SCH_MODE_DWRR 1 | |
226 | struct hclge_pg_info { | |
227 | u8 pg_id; | |
228 | u8 pg_sch_mode; /* 0: sp; 1: dwrr */ | |
229 | u8 tc_bit_map; | |
230 | u32 bw_limit; | |
231 | u8 tc_dwrr[HNAE3_MAX_TC]; | |
232 | }; | |
233 | ||
234 | struct hclge_tc_info { | |
235 | u8 tc_id; | |
236 | u8 tc_sch_mode; /* 0: sp; 1: dwrr */ | |
46a3df9f S |
237 | u8 pgid; |
238 | u32 bw_limit; | |
239 | }; | |
240 | ||
241 | struct hclge_cfg { | |
242 | u8 vmdq_vport_num; | |
243 | u8 tc_num; | |
244 | u16 tqp_desc_num; | |
245 | u16 rx_buf_len; | |
0e7a40cd | 246 | u16 rss_size_max; |
46a3df9f S |
247 | u8 phy_addr; |
248 | u8 media_type; | |
249 | u8 mac_addr[ETH_ALEN]; | |
250 | u8 default_speed; | |
251 | u32 numa_node_map; | |
0979aa0b | 252 | u8 speed_ability; |
46a3df9f S |
253 | }; |
254 | ||
255 | struct hclge_tm_info { | |
256 | u8 num_tc; | |
257 | u8 num_pg; /* It must be 1 if vNET-Base schd */ | |
258 | u8 pg_dwrr[HCLGE_PG_NUM]; | |
c5795c53 | 259 | u8 prio_tc[HNAE3_MAX_USER_PRIO]; |
46a3df9f S |
260 | struct hclge_pg_info pg_info[HCLGE_PG_NUM]; |
261 | struct hclge_tc_info tc_info[HNAE3_MAX_TC]; | |
262 | enum hclge_fc_mode fc_mode; | |
263 | u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ | |
264 | }; | |
265 | ||
266 | struct hclge_comm_stats_str { | |
267 | char desc[ETH_GSTRING_LEN]; | |
268 | unsigned long offset; | |
269 | }; | |
270 | ||
271 | /* all 64bit stats, opcode id: 0x0030 */ | |
272 | struct hclge_64_bit_stats { | |
273 | /* query_igu_stat */ | |
274 | u64 igu_rx_oversize_pkt; | |
275 | u64 igu_rx_undersize_pkt; | |
276 | u64 igu_rx_out_all_pkt; | |
277 | u64 igu_rx_uni_pkt; | |
278 | u64 igu_rx_multi_pkt; | |
279 | u64 igu_rx_broad_pkt; | |
280 | u64 rsv0; | |
281 | ||
282 | /* query_egu_stat */ | |
283 | u64 egu_tx_out_all_pkt; | |
284 | u64 egu_tx_uni_pkt; | |
285 | u64 egu_tx_multi_pkt; | |
286 | u64 egu_tx_broad_pkt; | |
287 | ||
288 | /* ssu_ppp packet stats */ | |
289 | u64 ssu_ppp_mac_key_num; | |
290 | u64 ssu_ppp_host_key_num; | |
291 | u64 ppp_ssu_mac_rlt_num; | |
292 | u64 ppp_ssu_host_rlt_num; | |
293 | ||
294 | /* ssu_tx_in_out_dfx_stats */ | |
295 | u64 ssu_tx_in_num; | |
296 | u64 ssu_tx_out_num; | |
297 | /* ssu_rx_in_out_dfx_stats */ | |
298 | u64 ssu_rx_in_num; | |
299 | u64 ssu_rx_out_num; | |
300 | }; | |
301 | ||
302 | /* all 32bit stats, opcode id: 0x0031 */ | |
303 | struct hclge_32_bit_stats { | |
304 | u64 igu_rx_err_pkt; | |
305 | u64 igu_rx_no_eof_pkt; | |
306 | u64 igu_rx_no_sof_pkt; | |
307 | u64 egu_tx_1588_pkt; | |
308 | u64 egu_tx_err_pkt; | |
309 | u64 ssu_full_drop_num; | |
310 | u64 ssu_part_drop_num; | |
311 | u64 ppp_key_drop_num; | |
312 | u64 ppp_rlt_drop_num; | |
313 | u64 ssu_key_drop_num; | |
314 | u64 pkt_curr_buf_cnt; | |
315 | u64 qcn_fb_rcv_cnt; | |
316 | u64 qcn_fb_drop_cnt; | |
317 | u64 qcn_fb_invaild_cnt; | |
318 | u64 rsv0; | |
319 | u64 rx_packet_tc0_in_cnt; | |
320 | u64 rx_packet_tc1_in_cnt; | |
321 | u64 rx_packet_tc2_in_cnt; | |
322 | u64 rx_packet_tc3_in_cnt; | |
323 | u64 rx_packet_tc4_in_cnt; | |
324 | u64 rx_packet_tc5_in_cnt; | |
325 | u64 rx_packet_tc6_in_cnt; | |
326 | u64 rx_packet_tc7_in_cnt; | |
327 | u64 rx_packet_tc0_out_cnt; | |
328 | u64 rx_packet_tc1_out_cnt; | |
329 | u64 rx_packet_tc2_out_cnt; | |
330 | u64 rx_packet_tc3_out_cnt; | |
331 | u64 rx_packet_tc4_out_cnt; | |
332 | u64 rx_packet_tc5_out_cnt; | |
333 | u64 rx_packet_tc6_out_cnt; | |
334 | u64 rx_packet_tc7_out_cnt; | |
335 | ||
336 | /* Tx packet level statistics */ | |
337 | u64 tx_packet_tc0_in_cnt; | |
338 | u64 tx_packet_tc1_in_cnt; | |
339 | u64 tx_packet_tc2_in_cnt; | |
340 | u64 tx_packet_tc3_in_cnt; | |
341 | u64 tx_packet_tc4_in_cnt; | |
342 | u64 tx_packet_tc5_in_cnt; | |
343 | u64 tx_packet_tc6_in_cnt; | |
344 | u64 tx_packet_tc7_in_cnt; | |
345 | u64 tx_packet_tc0_out_cnt; | |
346 | u64 tx_packet_tc1_out_cnt; | |
347 | u64 tx_packet_tc2_out_cnt; | |
348 | u64 tx_packet_tc3_out_cnt; | |
349 | u64 tx_packet_tc4_out_cnt; | |
350 | u64 tx_packet_tc5_out_cnt; | |
351 | u64 tx_packet_tc6_out_cnt; | |
352 | u64 tx_packet_tc7_out_cnt; | |
353 | ||
354 | /* packet buffer statistics */ | |
355 | u64 pkt_curr_buf_tc0_cnt; | |
356 | u64 pkt_curr_buf_tc1_cnt; | |
357 | u64 pkt_curr_buf_tc2_cnt; | |
358 | u64 pkt_curr_buf_tc3_cnt; | |
359 | u64 pkt_curr_buf_tc4_cnt; | |
360 | u64 pkt_curr_buf_tc5_cnt; | |
361 | u64 pkt_curr_buf_tc6_cnt; | |
362 | u64 pkt_curr_buf_tc7_cnt; | |
363 | ||
364 | u64 mb_uncopy_num; | |
365 | u64 lo_pri_unicast_rlt_drop_num; | |
366 | u64 hi_pri_multicast_rlt_drop_num; | |
367 | u64 lo_pri_multicast_rlt_drop_num; | |
368 | u64 rx_oq_drop_pkt_cnt; | |
369 | u64 tx_oq_drop_pkt_cnt; | |
370 | u64 nic_l2_err_drop_pkt_cnt; | |
371 | u64 roc_l2_err_drop_pkt_cnt; | |
372 | }; | |
373 | ||
374 | /* mac stats ,opcode id: 0x0032 */ | |
375 | struct hclge_mac_stats { | |
376 | u64 mac_tx_mac_pause_num; | |
377 | u64 mac_rx_mac_pause_num; | |
378 | u64 mac_tx_pfc_pri0_pkt_num; | |
379 | u64 mac_tx_pfc_pri1_pkt_num; | |
380 | u64 mac_tx_pfc_pri2_pkt_num; | |
381 | u64 mac_tx_pfc_pri3_pkt_num; | |
382 | u64 mac_tx_pfc_pri4_pkt_num; | |
383 | u64 mac_tx_pfc_pri5_pkt_num; | |
384 | u64 mac_tx_pfc_pri6_pkt_num; | |
385 | u64 mac_tx_pfc_pri7_pkt_num; | |
386 | u64 mac_rx_pfc_pri0_pkt_num; | |
387 | u64 mac_rx_pfc_pri1_pkt_num; | |
388 | u64 mac_rx_pfc_pri2_pkt_num; | |
389 | u64 mac_rx_pfc_pri3_pkt_num; | |
390 | u64 mac_rx_pfc_pri4_pkt_num; | |
391 | u64 mac_rx_pfc_pri5_pkt_num; | |
392 | u64 mac_rx_pfc_pri6_pkt_num; | |
393 | u64 mac_rx_pfc_pri7_pkt_num; | |
394 | u64 mac_tx_total_pkt_num; | |
395 | u64 mac_tx_total_oct_num; | |
396 | u64 mac_tx_good_pkt_num; | |
397 | u64 mac_tx_bad_pkt_num; | |
398 | u64 mac_tx_good_oct_num; | |
399 | u64 mac_tx_bad_oct_num; | |
400 | u64 mac_tx_uni_pkt_num; | |
401 | u64 mac_tx_multi_pkt_num; | |
402 | u64 mac_tx_broad_pkt_num; | |
403 | u64 mac_tx_undersize_pkt_num; | |
200a88c6 | 404 | u64 mac_tx_oversize_pkt_num; |
46a3df9f S |
405 | u64 mac_tx_64_oct_pkt_num; |
406 | u64 mac_tx_65_127_oct_pkt_num; | |
407 | u64 mac_tx_128_255_oct_pkt_num; | |
408 | u64 mac_tx_256_511_oct_pkt_num; | |
409 | u64 mac_tx_512_1023_oct_pkt_num; | |
410 | u64 mac_tx_1024_1518_oct_pkt_num; | |
91f384f6 JS |
411 | u64 mac_tx_1519_2047_oct_pkt_num; |
412 | u64 mac_tx_2048_4095_oct_pkt_num; | |
413 | u64 mac_tx_4096_8191_oct_pkt_num; | |
dbecc779 XW |
414 | u64 rsv0; |
415 | u64 mac_tx_8192_9216_oct_pkt_num; | |
416 | u64 mac_tx_9217_12287_oct_pkt_num; | |
91f384f6 JS |
417 | u64 mac_tx_12288_16383_oct_pkt_num; |
418 | u64 mac_tx_1519_max_good_oct_pkt_num; | |
419 | u64 mac_tx_1519_max_bad_oct_pkt_num; | |
420 | ||
46a3df9f S |
421 | u64 mac_rx_total_pkt_num; |
422 | u64 mac_rx_total_oct_num; | |
423 | u64 mac_rx_good_pkt_num; | |
424 | u64 mac_rx_bad_pkt_num; | |
425 | u64 mac_rx_good_oct_num; | |
426 | u64 mac_rx_bad_oct_num; | |
427 | u64 mac_rx_uni_pkt_num; | |
428 | u64 mac_rx_multi_pkt_num; | |
429 | u64 mac_rx_broad_pkt_num; | |
430 | u64 mac_rx_undersize_pkt_num; | |
200a88c6 | 431 | u64 mac_rx_oversize_pkt_num; |
46a3df9f S |
432 | u64 mac_rx_64_oct_pkt_num; |
433 | u64 mac_rx_65_127_oct_pkt_num; | |
434 | u64 mac_rx_128_255_oct_pkt_num; | |
435 | u64 mac_rx_256_511_oct_pkt_num; | |
436 | u64 mac_rx_512_1023_oct_pkt_num; | |
437 | u64 mac_rx_1024_1518_oct_pkt_num; | |
91f384f6 JS |
438 | u64 mac_rx_1519_2047_oct_pkt_num; |
439 | u64 mac_rx_2048_4095_oct_pkt_num; | |
440 | u64 mac_rx_4096_8191_oct_pkt_num; | |
dbecc779 XW |
441 | u64 rsv1; |
442 | u64 mac_rx_8192_9216_oct_pkt_num; | |
443 | u64 mac_rx_9217_12287_oct_pkt_num; | |
91f384f6 JS |
444 | u64 mac_rx_12288_16383_oct_pkt_num; |
445 | u64 mac_rx_1519_max_good_oct_pkt_num; | |
446 | u64 mac_rx_1519_max_bad_oct_pkt_num; | |
46a3df9f | 447 | |
a6c51c26 JS |
448 | u64 mac_tx_fragment_pkt_num; |
449 | u64 mac_tx_undermin_pkt_num; | |
450 | u64 mac_tx_jabber_pkt_num; | |
451 | u64 mac_tx_err_all_pkt_num; | |
452 | u64 mac_tx_from_app_good_pkt_num; | |
453 | u64 mac_tx_from_app_bad_pkt_num; | |
454 | u64 mac_rx_fragment_pkt_num; | |
455 | u64 mac_rx_undermin_pkt_num; | |
456 | u64 mac_rx_jabber_pkt_num; | |
457 | u64 mac_rx_fcs_err_pkt_num; | |
458 | u64 mac_rx_send_app_good_pkt_num; | |
459 | u64 mac_rx_send_app_bad_pkt_num; | |
46a3df9f S |
460 | }; |
461 | ||
c5f65480 | 462 | #define HCLGE_STATS_TIMER_INTERVAL (60 * 5) |
46a3df9f S |
463 | struct hclge_hw_stats { |
464 | struct hclge_mac_stats mac_stats; | |
465 | struct hclge_64_bit_stats all_64_bit_stats; | |
466 | struct hclge_32_bit_stats all_32_bit_stats; | |
c5f65480 | 467 | u32 stats_timer; |
46a3df9f S |
468 | }; |
469 | ||
5f6ea83f PL |
470 | struct hclge_vlan_type_cfg { |
471 | u16 rx_ot_fst_vlan_type; | |
472 | u16 rx_ot_sec_vlan_type; | |
473 | u16 rx_in_fst_vlan_type; | |
474 | u16 rx_in_sec_vlan_type; | |
475 | u16 tx_ot_vlan_type; | |
476 | u16 tx_in_vlan_type; | |
477 | }; | |
478 | ||
dc8131d8 | 479 | #define HCLGE_VPORT_NUM 256 |
46a3df9f S |
480 | struct hclge_dev { |
481 | struct pci_dev *pdev; | |
482 | struct hnae3_ae_dev *ae_dev; | |
483 | struct hclge_hw hw; | |
466b0c00 | 484 | struct hclge_misc_vector misc_vector; |
46a3df9f S |
485 | struct hclge_hw_stats hw_stats; |
486 | unsigned long state; | |
487 | ||
4ed340ab | 488 | enum hnae3_reset_type reset_type; |
cb1b9f77 | 489 | unsigned long reset_request; /* reset has been requested */ |
ca1d7669 | 490 | unsigned long reset_pending; /* client rst is pending to be served */ |
46a3df9f S |
491 | u32 fw_version; |
492 | u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */ | |
493 | u16 num_tqps; /* Num task queue pairs of this PF */ | |
494 | u16 num_req_vfs; /* Num VFs requested for this PF */ | |
495 | ||
46a3df9f S |
496 | /* Base task tqp physical id of this PF */ |
497 | u16 base_tqp_pid; | |
498 | u16 alloc_rss_size; /* Allocated RSS task queue */ | |
499 | u16 rss_size_max; /* HW defined max RSS task queue */ | |
500 | ||
501 | /* Num of guaranteed filters for this PF */ | |
502 | u16 fdir_pf_filter_count; | |
503 | u16 num_alloc_vport; /* Num vports this driver supports */ | |
504 | u32 numa_node_mask; | |
505 | u16 rx_buf_len; | |
506 | u16 num_desc; | |
507 | u8 hw_tc_map; | |
508 | u8 tc_num_last_time; | |
509 | enum hclge_fc_mode fc_mode_last_time; | |
510 | ||
511 | #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 | |
512 | #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 | |
513 | u8 tx_sch_mode; | |
cacde272 YL |
514 | u8 tc_max; |
515 | u8 pfc_max; | |
46a3df9f S |
516 | |
517 | u8 default_up; | |
cacde272 | 518 | u8 dcbx_cap; |
46a3df9f S |
519 | struct hclge_tm_info tm_info; |
520 | ||
521 | u16 num_msi; | |
522 | u16 num_msi_left; | |
523 | u16 num_msi_used; | |
524 | u32 base_msi_vector; | |
46a3df9f | 525 | u16 *vector_status; |
887c3820 SM |
526 | int *vector_irq; |
527 | u16 num_roce_msi; /* Num of roce vectors for this PF */ | |
528 | int roce_base_vector; | |
46a3df9f S |
529 | |
530 | u16 pending_udp_bitmap; | |
531 | ||
532 | u16 rx_itr_default; | |
533 | u16 tx_itr_default; | |
534 | ||
535 | u16 adminq_work_limit; /* Num of admin receive queue desc to process */ | |
536 | unsigned long service_timer_period; | |
537 | unsigned long service_timer_previous; | |
538 | struct timer_list service_timer; | |
539 | struct work_struct service_task; | |
cb1b9f77 | 540 | struct work_struct rst_service_task; |
c1a81619 | 541 | struct work_struct mbx_service_task; |
46a3df9f S |
542 | |
543 | bool cur_promisc; | |
544 | int num_alloc_vfs; /* Actual number of VFs allocated */ | |
545 | ||
546 | struct hclge_tqp *htqp; | |
547 | struct hclge_vport *vport; | |
548 | ||
549 | struct dentry *hclge_dbgfs; | |
550 | ||
551 | struct hnae3_client *nic_client; | |
552 | struct hnae3_client *roce_client; | |
553 | ||
887c3820 SM |
554 | #define HCLGE_FLAG_MAIN BIT(0) |
555 | #define HCLGE_FLAG_DCB_CAPABLE BIT(1) | |
556 | #define HCLGE_FLAG_DCB_ENABLE BIT(2) | |
557 | #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) | |
46a3df9f S |
558 | u32 flag; |
559 | ||
560 | u32 pkt_buf_size; /* Total pf buf size for tx/rx */ | |
561 | u32 mps; /* Max packet size */ | |
46a3df9f S |
562 | |
563 | enum hclge_mta_dmac_sel_type mta_mac_sel_type; | |
564 | bool enable_mta; /* Mutilcast filter enable */ | |
5f6ea83f PL |
565 | |
566 | struct hclge_vlan_type_cfg vlan_type_cfg; | |
716aaac1 | 567 | |
dc8131d8 | 568 | unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; |
5f6ea83f PL |
569 | }; |
570 | ||
571 | /* VPort level vlan tag configuration for TX direction */ | |
572 | struct hclge_tx_vtag_cfg { | |
dcb35cce PL |
573 | bool accept_tag1; /* Whether accept tag1 packet from host */ |
574 | bool accept_untag1; /* Whether accept untag1 packet from host */ | |
575 | bool accept_tag2; | |
576 | bool accept_untag2; | |
5f6ea83f PL |
577 | bool insert_tag1_en; /* Whether insert inner vlan tag */ |
578 | bool insert_tag2_en; /* Whether insert outer vlan tag */ | |
579 | u16 default_tag1; /* The default inner vlan tag to insert */ | |
580 | u16 default_tag2; /* The default outer vlan tag to insert */ | |
581 | }; | |
582 | ||
583 | /* VPort level vlan tag configuration for RX direction */ | |
584 | struct hclge_rx_vtag_cfg { | |
585 | bool strip_tag1_en; /* Whether strip inner vlan tag */ | |
586 | bool strip_tag2_en; /* Whether strip outer vlan tag */ | |
587 | bool vlan1_vlan_prionly;/* Inner VLAN Tag up to descriptor Enable */ | |
588 | bool vlan2_vlan_prionly;/* Outer VLAN Tag up to descriptor Enable */ | |
46a3df9f S |
589 | }; |
590 | ||
6f2af429 YL |
591 | struct hclge_rss_tuple_cfg { |
592 | u8 ipv4_tcp_en; | |
593 | u8 ipv4_udp_en; | |
594 | u8 ipv4_sctp_en; | |
595 | u8 ipv4_fragment_en; | |
596 | u8 ipv6_tcp_en; | |
597 | u8 ipv6_udp_en; | |
598 | u8 ipv6_sctp_en; | |
599 | u8 ipv6_fragment_en; | |
600 | }; | |
601 | ||
46a3df9f S |
602 | struct hclge_vport { |
603 | u16 alloc_tqps; /* Allocated Tx/Rx queues */ | |
604 | ||
605 | u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ | |
606 | /* User configured lookup table entries */ | |
607 | u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE]; | |
89523cfa | 608 | int rss_algo; /* User configured hash algorithm */ |
6f2af429 YL |
609 | /* User configured rss tuple sets */ |
610 | struct hclge_rss_tuple_cfg rss_tuple_sets; | |
89523cfa | 611 | |
68ece54e | 612 | u16 alloc_rss_size; |
46a3df9f S |
613 | |
614 | u16 qs_offset; | |
615 | u16 bw_limit; /* VSI BW Limit (0 = disabled) */ | |
616 | u8 dwrr; | |
617 | ||
5f6ea83f PL |
618 | struct hclge_tx_vtag_cfg txvlan_cfg; |
619 | struct hclge_rx_vtag_cfg rxvlan_cfg; | |
620 | ||
46a3df9f S |
621 | int vport_id; |
622 | struct hclge_dev *back; /* Back reference to associated dev */ | |
623 | struct hnae3_handle nic; | |
624 | struct hnae3_handle roce; | |
40cca1c5 XW |
625 | |
626 | bool accept_mta_mc; /* whether to accept mta filter multicast */ | |
627 | unsigned long mta_shadow[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)]; | |
46a3df9f S |
628 | }; |
629 | ||
630 | void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, | |
631 | bool en_mc, bool en_bc, int vport_id); | |
632 | ||
633 | int hclge_add_uc_addr_common(struct hclge_vport *vport, | |
634 | const unsigned char *addr); | |
635 | int hclge_rm_uc_addr_common(struct hclge_vport *vport, | |
636 | const unsigned char *addr); | |
637 | int hclge_add_mc_addr_common(struct hclge_vport *vport, | |
638 | const unsigned char *addr); | |
639 | int hclge_rm_mc_addr_common(struct hclge_vport *vport, | |
640 | const unsigned char *addr); | |
641 | ||
642 | int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, | |
643 | u8 func_id, | |
644 | bool enable); | |
40cca1c5 XW |
645 | int hclge_update_mta_status_common(struct hclge_vport *vport, |
646 | unsigned long *status, | |
647 | u16 idx, | |
648 | u16 count, | |
649 | bool update_filter); | |
650 | ||
46a3df9f | 651 | struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); |
84e095d6 SM |
652 | int hclge_bind_ring_with_vector(struct hclge_vport *vport, |
653 | int vector_id, bool en, | |
654 | struct hnae3_ring_chain_node *ring_chain); | |
655 | ||
46a3df9f S |
656 | static inline int hclge_get_queue_id(struct hnae3_queue *queue) |
657 | { | |
658 | struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); | |
659 | ||
660 | return tqp->index; | |
661 | } | |
662 | ||
663 | int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); | |
dc8131d8 YL |
664 | int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, |
665 | u16 vlan_id, bool is_kill); | |
b2641e2a | 666 | int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); |
77f255c1 YL |
667 | |
668 | int hclge_buffer_alloc(struct hclge_dev *hdev); | |
669 | int hclge_rss_init_hw(struct hclge_dev *hdev); | |
268f5dfa | 670 | void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); |
dde1a86e SM |
671 | |
672 | void hclge_mbx_handler(struct hclge_dev *hdev); | |
84e095d6 | 673 | void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id); |
1a426f8b | 674 | void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id); |
1770a7a3 | 675 | int hclge_cfg_flowctrl(struct hclge_dev *hdev); |
2bfbd35d | 676 | int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); |
46a3df9f | 677 | #endif |