[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.h

/*
 * Copyright (c) 2016~2017 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __HCLGE_MAIN_H
#define __HCLGE_MAIN_H
#include <linux/fs.h>
#include <linux/types.h>
#include <linux/phy.h>
#include "hclge_cmd.h"
#include "hnae3.h"

#define HCLGE_MOD_VERSION "v1.0"
#define HCLGE_DRIVER_NAME "hclge"

#define HCLGE_INVALID_VPORT 0xffff

#define HCLGE_ROCE_VECTOR_OFFSET	96

#define HCLGE_PF_CFG_BLOCK_SIZE		32
#define HCLGE_PF_CFG_DESC_NUM \
	(HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)

#define HCLGE_VECTOR_REG_BASE		0x20000
#define HCLGE_MISC_VECTOR_REG_BASE	0x20400

#define HCLGE_VECTOR_REG_OFFSET		0x4
#define HCLGE_VECTOR_VF_OFFSET		0x100000

#define HCLGE_RSS_IND_TBL_SIZE		512
#define HCLGE_RSS_SET_BITMAP_MSK	GENMASK(15, 0)
#define HCLGE_RSS_KEY_SIZE		40
#define HCLGE_RSS_HASH_ALGO_TOEPLITZ	0
#define HCLGE_RSS_HASH_ALGO_SIMPLE	1
#define HCLGE_RSS_HASH_ALGO_SYMMETRIC	2
#define HCLGE_RSS_HASH_ALGO_MASK	0xf
#define HCLGE_RSS_CFG_TBL_NUM \
	(HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)

#define HCLGE_RSS_INPUT_TUPLE_OTHER	GENMASK(3, 0)
#define HCLGE_RSS_INPUT_TUPLE_SCTP	GENMASK(4, 0)
#define HCLGE_D_PORT_BIT		BIT(0)
#define HCLGE_S_PORT_BIT		BIT(1)
#define HCLGE_D_IP_BIT			BIT(2)
#define HCLGE_S_IP_BIT			BIT(3)
#define HCLGE_V_TAG_BIT			BIT(4)

#define HCLGE_RSS_TC_SIZE_0		1
#define HCLGE_RSS_TC_SIZE_1		2
#define HCLGE_RSS_TC_SIZE_2		4
#define HCLGE_RSS_TC_SIZE_3		8
#define HCLGE_RSS_TC_SIZE_4		16
#define HCLGE_RSS_TC_SIZE_5		32
#define HCLGE_RSS_TC_SIZE_6		64
#define HCLGE_RSS_TC_SIZE_7		128

#define HCLGE_TQP_RESET_TRY_TIMES	10

#define HCLGE_PHY_PAGE_MDIX		0
#define HCLGE_PHY_PAGE_COPPER		0

/* Page Selection Reg. */
#define HCLGE_PHY_PAGE_REG		22

/* Copper Specific Control Register */
#define HCLGE_PHY_CSC_REG		16

/* Copper Specific Status Register */
#define HCLGE_PHY_CSS_REG		17

#define HCLGE_PHY_MDIX_CTRL_S		(5)
#define HCLGE_PHY_MDIX_CTRL_M		GENMASK(6, 5)

#define HCLGE_PHY_MDIX_STATUS_B	(6)
#define HCLGE_PHY_SPEED_DUP_RESOLVE_B	(11)

/* Reset related Registers */
#define HCLGE_MISC_RESET_STS_REG	0x20700
#define HCLGE_GLOBAL_RESET_REG		0x20A00
#define HCLGE_GLOBAL_RESET_BIT		0x0
#define HCLGE_CORE_RESET_BIT		0x1
#define HCLGE_FUN_RST_ING		0x20C00
#define HCLGE_FUN_RST_ING_B		0

/* Vector0 register bits define */
#define HCLGE_VECTOR0_GLOBALRESET_INT_B	5
#define HCLGE_VECTOR0_CORERESET_INT_B	6
#define HCLGE_VECTOR0_IMPRESET_INT_B	7

enum HCLGE_DEV_STATE {
	HCLGE_STATE_REINITING,
	HCLGE_STATE_DOWN,
	HCLGE_STATE_DISABLED,
	HCLGE_STATE_REMOVING,
	HCLGE_STATE_SERVICE_INITED,
	HCLGE_STATE_SERVICE_SCHED,
	HCLGE_STATE_MBX_HANDLING,
	HCLGE_STATE_MBX_IRQ,
	HCLGE_STATE_RESET_INT,
	HCLGE_STATE_MAX
};

enum hclge_evt_cause {
	HCLGE_VECTOR0_EVENT_RST,
	HCLGE_VECTOR0_EVENT_MBX,
	HCLGE_VECTOR0_EVENT_OTHER,
};

#define HCLGE_MPF_ENBALE 1
struct hclge_caps {
	u16 num_tqp;
	u16 num_buffer_cell;
	u32 flag;
	u16 vmdq;
};

enum HCLGE_MAC_SPEED {
	HCLGE_MAC_SPEED_10M	= 10,		/* 10 Mbps */
	HCLGE_MAC_SPEED_100M	= 100,		/* 100 Mbps */
	HCLGE_MAC_SPEED_1G	= 1000,		/* 1000 Mbps   = 1 Gbps */
	HCLGE_MAC_SPEED_10G	= 10000,	/* 10000 Mbps  = 10 Gbps */
	HCLGE_MAC_SPEED_25G	= 25000,	/* 25000 Mbps  = 25 Gbps */
	HCLGE_MAC_SPEED_40G	= 40000,	/* 40000 Mbps  = 40 Gbps */
	HCLGE_MAC_SPEED_50G	= 50000,	/* 50000 Mbps  = 50 Gbps */
	HCLGE_MAC_SPEED_100G	= 100000	/* 100000 Mbps = 100 Gbps */
};

enum HCLGE_MAC_DUPLEX {
	HCLGE_MAC_HALF,
	HCLGE_MAC_FULL
};

enum hclge_mta_dmac_sel_type {
	HCLGE_MAC_ADDR_47_36,
	HCLGE_MAC_ADDR_46_35,
	HCLGE_MAC_ADDR_45_34,
	HCLGE_MAC_ADDR_44_33,
};

struct hclge_mac {
	u8 phy_addr;
	u8 flag;
	u8 media_type;
	u8 mac_addr[ETH_ALEN];
	u8 autoneg;
	u8 duplex;
	u32 speed;
	int link;	/* store the link status of mac & phy (if phy exit)*/
	struct phy_device *phydev;
	struct mii_bus *mdio_bus;
	phy_interface_t phy_if;
};

struct hclge_hw {
	void __iomem *io_base;
	struct hclge_mac mac;
	int num_vec;
	struct hclge_cmq cmq;
	struct hclge_caps caps;
	void *back;
};

/* TQP stats */
struct hlcge_tqp_stats {
	/* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
	u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
	/* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
	u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
};

struct hclge_tqp {
	struct device *dev;	/* Device for DMA mapping */
	struct hnae3_queue q;
	struct hlcge_tqp_stats tqp_stats;
	u16 index;	/* Global index in a NIC controller */

	bool alloced;
};

enum hclge_fc_mode {
	HCLGE_FC_NONE,
	HCLGE_FC_RX_PAUSE,
	HCLGE_FC_TX_PAUSE,
	HCLGE_FC_FULL,
	HCLGE_FC_PFC,
	HCLGE_FC_DEFAULT
};

#define HCLGE_PG_NUM		4
#define HCLGE_SCH_MODE_SP	0
#define HCLGE_SCH_MODE_DWRR	1
struct hclge_pg_info {
	u8 pg_id;
	u8 pg_sch_mode;		/* 0: sp; 1: dwrr */
	u8 tc_bit_map;
	u32 bw_limit;
	u8 tc_dwrr[HNAE3_MAX_TC];
};

struct hclge_tc_info {
	u8 tc_id;
	u8 tc_sch_mode;		/* 0: sp; 1: dwrr */
	u8 pgid;
	u32 bw_limit;
};

struct hclge_cfg {
	u8 vmdq_vport_num;
	u8 tc_num;
	u16 tqp_desc_num;
	u16 rx_buf_len;
	u8 phy_addr;
	u8 media_type;
	u8 mac_addr[ETH_ALEN];
	u8 default_speed;
	u32 numa_node_map;
};

struct hclge_tm_info {
	u8 num_tc;
	u8 num_pg;      /* It must be 1 if vNET-Base schd */
	u8 pg_dwrr[HCLGE_PG_NUM];
	u8 prio_tc[HNAE3_MAX_USER_PRIO];
	struct hclge_pg_info pg_info[HCLGE_PG_NUM];
	struct hclge_tc_info tc_info[HNAE3_MAX_TC];
	enum hclge_fc_mode fc_mode;
	u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
};

struct hclge_comm_stats_str {
	char desc[ETH_GSTRING_LEN];
	unsigned long offset;
};

/* all 64bit stats, opcode id: 0x0030 */
struct hclge_64_bit_stats {
	/* query_igu_stat */
	u64 igu_rx_oversize_pkt;
	u64 igu_rx_undersize_pkt;
	u64 igu_rx_out_all_pkt;
	u64 igu_rx_uni_pkt;
	u64 igu_rx_multi_pkt;
	u64 igu_rx_broad_pkt;
	u64 rsv0;

	/* query_egu_stat */
	u64 egu_tx_out_all_pkt;
	u64 egu_tx_uni_pkt;
	u64 egu_tx_multi_pkt;
	u64 egu_tx_broad_pkt;

	/* ssu_ppp packet stats */
	u64 ssu_ppp_mac_key_num;
	u64 ssu_ppp_host_key_num;
	u64 ppp_ssu_mac_rlt_num;
	u64 ppp_ssu_host_rlt_num;

	/* ssu_tx_in_out_dfx_stats */
	u64 ssu_tx_in_num;
	u64 ssu_tx_out_num;
	/* ssu_rx_in_out_dfx_stats */
	u64 ssu_rx_in_num;
	u64 ssu_rx_out_num;
};

/* all 32bit stats, opcode id: 0x0031 */
struct hclge_32_bit_stats {
	u64 igu_rx_err_pkt;
	u64 igu_rx_no_eof_pkt;
	u64 igu_rx_no_sof_pkt;
	u64 egu_tx_1588_pkt;
	u64 egu_tx_err_pkt;
	u64 ssu_full_drop_num;
	u64 ssu_part_drop_num;
	u64 ppp_key_drop_num;
	u64 ppp_rlt_drop_num;
	u64 ssu_key_drop_num;
	u64 pkt_curr_buf_cnt;
	u64 qcn_fb_rcv_cnt;
	u64 qcn_fb_drop_cnt;
	u64 qcn_fb_invaild_cnt;
	u64 rsv0;
	u64 rx_packet_tc0_in_cnt;
	u64 rx_packet_tc1_in_cnt;
	u64 rx_packet_tc2_in_cnt;
	u64 rx_packet_tc3_in_cnt;
	u64 rx_packet_tc4_in_cnt;
	u64 rx_packet_tc5_in_cnt;
	u64 rx_packet_tc6_in_cnt;
	u64 rx_packet_tc7_in_cnt;
	u64 rx_packet_tc0_out_cnt;
	u64 rx_packet_tc1_out_cnt;
	u64 rx_packet_tc2_out_cnt;
	u64 rx_packet_tc3_out_cnt;
	u64 rx_packet_tc4_out_cnt;
	u64 rx_packet_tc5_out_cnt;
	u64 rx_packet_tc6_out_cnt;
	u64 rx_packet_tc7_out_cnt;

	/* Tx packet level statistics */
	u64 tx_packet_tc0_in_cnt;
	u64 tx_packet_tc1_in_cnt;
	u64 tx_packet_tc2_in_cnt;
	u64 tx_packet_tc3_in_cnt;
	u64 tx_packet_tc4_in_cnt;
	u64 tx_packet_tc5_in_cnt;
	u64 tx_packet_tc6_in_cnt;
	u64 tx_packet_tc7_in_cnt;
	u64 tx_packet_tc0_out_cnt;
	u64 tx_packet_tc1_out_cnt;
	u64 tx_packet_tc2_out_cnt;
	u64 tx_packet_tc3_out_cnt;
	u64 tx_packet_tc4_out_cnt;
	u64 tx_packet_tc5_out_cnt;
	u64 tx_packet_tc6_out_cnt;
	u64 tx_packet_tc7_out_cnt;

	/* packet buffer statistics */
	u64 pkt_curr_buf_tc0_cnt;
	u64 pkt_curr_buf_tc1_cnt;
	u64 pkt_curr_buf_tc2_cnt;
	u64 pkt_curr_buf_tc3_cnt;
	u64 pkt_curr_buf_tc4_cnt;
	u64 pkt_curr_buf_tc5_cnt;
	u64 pkt_curr_buf_tc6_cnt;
	u64 pkt_curr_buf_tc7_cnt;

	u64 mb_uncopy_num;
	u64 lo_pri_unicast_rlt_drop_num;
	u64 hi_pri_multicast_rlt_drop_num;
	u64 lo_pri_multicast_rlt_drop_num;
	u64 rx_oq_drop_pkt_cnt;
	u64 tx_oq_drop_pkt_cnt;
	u64 nic_l2_err_drop_pkt_cnt;
	u64 roc_l2_err_drop_pkt_cnt;
};

/* mac stats ,opcode id: 0x0032 */
struct hclge_mac_stats {
	u64 mac_tx_mac_pause_num;
	u64 mac_rx_mac_pause_num;
	u64 mac_tx_pfc_pri0_pkt_num;
	u64 mac_tx_pfc_pri1_pkt_num;
	u64 mac_tx_pfc_pri2_pkt_num;
	u64 mac_tx_pfc_pri3_pkt_num;
	u64 mac_tx_pfc_pri4_pkt_num;
	u64 mac_tx_pfc_pri5_pkt_num;
	u64 mac_tx_pfc_pri6_pkt_num;
	u64 mac_tx_pfc_pri7_pkt_num;
	u64 mac_rx_pfc_pri0_pkt_num;
	u64 mac_rx_pfc_pri1_pkt_num;
	u64 mac_rx_pfc_pri2_pkt_num;
	u64 mac_rx_pfc_pri3_pkt_num;
	u64 mac_rx_pfc_pri4_pkt_num;
	u64 mac_rx_pfc_pri5_pkt_num;
	u64 mac_rx_pfc_pri6_pkt_num;
	u64 mac_rx_pfc_pri7_pkt_num;
	u64 mac_tx_total_pkt_num;
	u64 mac_tx_total_oct_num;
	u64 mac_tx_good_pkt_num;
	u64 mac_tx_bad_pkt_num;
	u64 mac_tx_good_oct_num;
	u64 mac_tx_bad_oct_num;
	u64 mac_tx_uni_pkt_num;
	u64 mac_tx_multi_pkt_num;
	u64 mac_tx_broad_pkt_num;
	u64 mac_tx_undersize_pkt_num;
	u64 mac_tx_overrsize_pkt_num;
	u64 mac_tx_64_oct_pkt_num;
	u64 mac_tx_65_127_oct_pkt_num;
	u64 mac_tx_128_255_oct_pkt_num;
	u64 mac_tx_256_511_oct_pkt_num;
	u64 mac_tx_512_1023_oct_pkt_num;
	u64 mac_tx_1024_1518_oct_pkt_num;
	u64 mac_tx_1519_max_oct_pkt_num;
	u64 mac_rx_total_pkt_num;
	u64 mac_rx_total_oct_num;
	u64 mac_rx_good_pkt_num;
	u64 mac_rx_bad_pkt_num;
	u64 mac_rx_good_oct_num;
	u64 mac_rx_bad_oct_num;
	u64 mac_rx_uni_pkt_num;
	u64 mac_rx_multi_pkt_num;
	u64 mac_rx_broad_pkt_num;
	u64 mac_rx_undersize_pkt_num;
	u64 mac_rx_overrsize_pkt_num;
	u64 mac_rx_64_oct_pkt_num;
	u64 mac_rx_65_127_oct_pkt_num;
	u64 mac_rx_128_255_oct_pkt_num;
	u64 mac_rx_256_511_oct_pkt_num;
	u64 mac_rx_512_1023_oct_pkt_num;
	u64 mac_rx_1024_1518_oct_pkt_num;
	u64 mac_rx_1519_max_oct_pkt_num;

	u64 mac_trans_fragment_pkt_num;
	u64 mac_trans_undermin_pkt_num;
	u64 mac_trans_jabber_pkt_num;
	u64 mac_trans_err_all_pkt_num;
	u64 mac_trans_from_app_good_pkt_num;
	u64 mac_trans_from_app_bad_pkt_num;
	u64 mac_rcv_fragment_pkt_num;
	u64 mac_rcv_undermin_pkt_num;
	u64 mac_rcv_jabber_pkt_num;
	u64 mac_rcv_fcs_err_pkt_num;
	u64 mac_rcv_send_app_good_pkt_num;
	u64 mac_rcv_send_app_bad_pkt_num;
};

struct hclge_hw_stats {
	struct hclge_mac_stats      mac_stats;
	struct hclge_64_bit_stats   all_64_bit_stats;
	struct hclge_32_bit_stats   all_32_bit_stats;
};

struct hclge_dev {
	struct pci_dev *pdev;
	struct hnae3_ae_dev *ae_dev;
	struct hclge_hw hw;
	struct hclge_misc_vector misc_vector;
	struct hclge_hw_stats hw_stats;
	unsigned long state;

	enum hnae3_reset_type reset_type;
	unsigned long reset_pending;	/* client rst is pending to be served */
	u32 fw_version;
	u16 num_vmdq_vport;		/* Num vmdq vport this PF has set up */
	u16 num_tqps;			/* Num task queue pairs of this PF */
	u16 num_req_vfs;		/* Num VFs requested for this PF */

	/* Base task tqp physical id of this PF */
	u16 base_tqp_pid;
	u16 alloc_rss_size;		/* Allocated RSS task queue */
	u16 rss_size_max;		/* HW defined max RSS task queue */

	/* Num of guaranteed filters for this PF */
	u16 fdir_pf_filter_count;
	u16 num_alloc_vport;		/* Num vports this driver supports */
	u32 numa_node_mask;
	u16 rx_buf_len;
	u16 num_desc;
	u8 hw_tc_map;
	u8 tc_num_last_time;
	enum hclge_fc_mode fc_mode_last_time;

#define HCLGE_FLAG_TC_BASE_SCH_MODE		1
#define HCLGE_FLAG_VNET_BASE_SCH_MODE		2
	u8 tx_sch_mode;
	u8 tc_max;
	u8 pfc_max;

	u8 default_up;
	u8 dcbx_cap;
	struct hclge_tm_info tm_info;

	u16 num_msi;
	u16 num_msi_left;
	u16 num_msi_used;
	u32 base_msi_vector;
	u16 *vector_status;
	int *vector_irq;
	u16 num_roce_msi;	/* Num of roce vectors for this PF */
	int roce_base_vector;

	u16 pending_udp_bitmap;

	u16 rx_itr_default;
	u16 tx_itr_default;

	u16 adminq_work_limit; /* Num of admin receive queue desc to process */
	unsigned long service_timer_period;
	unsigned long service_timer_previous;
	struct timer_list service_timer;
	struct work_struct service_task;

	bool cur_promisc;
	int num_alloc_vfs;	/* Actual number of VFs allocated */

	struct hclge_tqp *htqp;
	struct hclge_vport *vport;

	struct dentry *hclge_dbgfs;

	struct hnae3_client *nic_client;
	struct hnae3_client *roce_client;

#define HCLGE_FLAG_MAIN			BIT(0)
#define HCLGE_FLAG_DCB_CAPABLE		BIT(1)
#define HCLGE_FLAG_DCB_ENABLE		BIT(2)
#define HCLGE_FLAG_MQPRIO_ENABLE	BIT(3)
	u32 flag;

	u32 pkt_buf_size; /* Total pf buf size for tx/rx */
	u32 mps; /* Max packet size */

	enum hclge_mta_dmac_sel_type mta_mac_sel_type;
	bool enable_mta; /* Mutilcast filter enable */
	bool accept_mta_mc; /* Whether accept mta filter multicast */
};

struct hclge_vport {
	u16 alloc_tqps;	/* Allocated Tx/Rx queues */

	u8  rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
	/* User configured lookup table entries */
	u8  rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
	u16 alloc_rss_size;

	u16 qs_offset;
	u16 bw_limit;		/* VSI BW Limit (0 = disabled) */
	u8  dwrr;

	int vport_id;
	struct hclge_dev *back;  /* Back reference to associated dev */
	struct hnae3_handle nic;
	struct hnae3_handle roce;
};

void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
			      bool en_mc, bool en_bc, int vport_id);

int hclge_add_uc_addr_common(struct hclge_vport *vport,
			     const unsigned char *addr);
int hclge_rm_uc_addr_common(struct hclge_vport *vport,
			    const unsigned char *addr);
int hclge_add_mc_addr_common(struct hclge_vport *vport,
			     const unsigned char *addr);
int hclge_rm_mc_addr_common(struct hclge_vport *vport,
			    const unsigned char *addr);

int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
			      u8 func_id,
			      bool enable);
struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector,
				   struct hnae3_ring_chain_node *ring_chain);
static inline int hclge_get_queue_id(struct hnae3_queue *queue)
{
	struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);

	return tqp->index;
}

int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
int hclge_set_vf_vlan_common(struct hclge_dev *vport, int vfid,
			     bool is_kill, u16 vlan, u8 qos, __be16 proto);

int hclge_buffer_alloc(struct hclge_dev *hdev);
int hclge_rss_init_hw(struct hclge_dev *hdev);
#endif
Commit	Line	Data
46a3df9f S	1	/*
	2	* Copyright (c) 2016~2017 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	#ifndef __HCLGE_MAIN_H
	11	#define __HCLGE_MAIN_H
	12	#include <linux/fs.h>
	13	#include <linux/types.h>
	14	#include <linux/phy.h>
	15	#include "hclge_cmd.h"
	16	#include "hnae3.h"
	17
	18	#define HCLGE_MOD_VERSION "v1.0"
	19	#define HCLGE_DRIVER_NAME "hclge"
	20
	21	#define HCLGE_INVALID_VPORT 0xffff
	22
	23	#define HCLGE_ROCE_VECTOR_OFFSET 96
	24
	25	#define HCLGE_PF_CFG_BLOCK_SIZE 32
	26	#define HCLGE_PF_CFG_DESC_NUM \
	27	(HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
	28
	29	#define HCLGE_VECTOR_REG_BASE 0x20000
466b0c00	30	#define HCLGE_MISC_VECTOR_REG_BASE 0x20400
46a3df9f S	31
	32	#define HCLGE_VECTOR_REG_OFFSET 0x4
	33	#define HCLGE_VECTOR_VF_OFFSET 0x100000
	34
	35	#define HCLGE_RSS_IND_TBL_SIZE 512
5392902d	36	#define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
46a3df9f S	37	#define HCLGE_RSS_KEY_SIZE 40
	38	#define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0
	39	#define HCLGE_RSS_HASH_ALGO_SIMPLE 1
	40	#define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2
	41	#define HCLGE_RSS_HASH_ALGO_MASK 0xf
	42	#define HCLGE_RSS_CFG_TBL_NUM \
	43	(HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
	44
f7db940a L	45	#define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
	46	#define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
	47	#define HCLGE_D_PORT_BIT BIT(0)
	48	#define HCLGE_S_PORT_BIT BIT(1)
	49	#define HCLGE_D_IP_BIT BIT(2)
	50	#define HCLGE_S_IP_BIT BIT(3)
	51	#define HCLGE_V_TAG_BIT BIT(4)
	52
46a3df9f S	53	#define HCLGE_RSS_TC_SIZE_0 1
	54	#define HCLGE_RSS_TC_SIZE_1 2
	55	#define HCLGE_RSS_TC_SIZE_2 4
	56	#define HCLGE_RSS_TC_SIZE_3 8
	57	#define HCLGE_RSS_TC_SIZE_4 16
	58	#define HCLGE_RSS_TC_SIZE_5 32
	59	#define HCLGE_RSS_TC_SIZE_6 64
	60	#define HCLGE_RSS_TC_SIZE_7 128
	61
	62	#define HCLGE_TQP_RESET_TRY_TIMES 10
	63
	64	#define HCLGE_PHY_PAGE_MDIX 0
	65	#define HCLGE_PHY_PAGE_COPPER 0
	66
	67	/* Page Selection Reg. */
	68	#define HCLGE_PHY_PAGE_REG 22
	69
	70	/* Copper Specific Control Register */
	71	#define HCLGE_PHY_CSC_REG 16
	72
	73	/* Copper Specific Status Register */
	74	#define HCLGE_PHY_CSS_REG 17
	75
	76	#define HCLGE_PHY_MDIX_CTRL_S (5)
5392902d	77	#define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
46a3df9f S	78
	79	#define HCLGE_PHY_MDIX_STATUS_B (6)
	80	#define HCLGE_PHY_SPEED_DUP_RESOLVE_B (11)
	81
4ed340ab L	82	/* Reset related Registers */
	83	#define HCLGE_MISC_RESET_STS_REG 0x20700
	84	#define HCLGE_GLOBAL_RESET_REG 0x20A00
	85	#define HCLGE_GLOBAL_RESET_BIT 0x0
	86	#define HCLGE_CORE_RESET_BIT 0x1
	87	#define HCLGE_FUN_RST_ING 0x20C00
	88	#define HCLGE_FUN_RST_ING_B 0
	89
	90	/* Vector0 register bits define */
	91	#define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
	92	#define HCLGE_VECTOR0_CORERESET_INT_B 6
	93	#define HCLGE_VECTOR0_IMPRESET_INT_B 7
	94
46a3df9f S	95	enum HCLGE_DEV_STATE {
	96	HCLGE_STATE_REINITING,
	97	HCLGE_STATE_DOWN,
	98	HCLGE_STATE_DISABLED,
	99	HCLGE_STATE_REMOVING,
	100	HCLGE_STATE_SERVICE_INITED,
	101	HCLGE_STATE_SERVICE_SCHED,
	102	HCLGE_STATE_MBX_HANDLING,
	103	HCLGE_STATE_MBX_IRQ,
4ed340ab	104	HCLGE_STATE_RESET_INT,
46a3df9f S	105	HCLGE_STATE_MAX
	106	};
	107
ca1d7669 SM	108	enum hclge_evt_cause {
	109	HCLGE_VECTOR0_EVENT_RST,
	110	HCLGE_VECTOR0_EVENT_MBX,
	111	HCLGE_VECTOR0_EVENT_OTHER,
	112	};
	113
46a3df9f S	114	#define HCLGE_MPF_ENBALE 1
	115	struct hclge_caps {
	116	u16 num_tqp;
	117	u16 num_buffer_cell;
	118	u32 flag;
	119	u16 vmdq;
	120	};
	121
	122	enum HCLGE_MAC_SPEED {
	123	HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */
	124	HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */
	125	HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
	126	HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
	127	HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
	128	HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
	129	HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
	130	HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */
	131	};
	132
	133	enum HCLGE_MAC_DUPLEX {
	134	HCLGE_MAC_HALF,
	135	HCLGE_MAC_FULL
	136	};
	137
	138	enum hclge_mta_dmac_sel_type {
	139	HCLGE_MAC_ADDR_47_36,
	140	HCLGE_MAC_ADDR_46_35,
	141	HCLGE_MAC_ADDR_45_34,
	142	HCLGE_MAC_ADDR_44_33,
	143	};
	144
	145	struct hclge_mac {
	146	u8 phy_addr;
	147	u8 flag;
	148	u8 media_type;
	149	u8 mac_addr[ETH_ALEN];
	150	u8 autoneg;
	151	u8 duplex;
	152	u32 speed;
	153	int link; /* store the link status of mac & phy (if phy exit)*/
	154	struct phy_device *phydev;
	155	struct mii_bus *mdio_bus;
	156	phy_interface_t phy_if;
	157	};
	158
	159	struct hclge_hw {
	160	void __iomem *io_base;
	161	struct hclge_mac mac;
	162	int num_vec;
	163	struct hclge_cmq cmq;
	164	struct hclge_caps caps;
	165	void *back;
	166	};
	167
	168	/* TQP stats */
	169	struct hlcge_tqp_stats {
	170	/* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
	171	u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
	172	/* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
	173	u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
	174	};
	175
	176	struct hclge_tqp {
	177	struct device dev; / Device for DMA mapping */
178	struct hnae3_queue q;
179	struct hlcge_tqp_stats tqp_stats;
180	u16 index; /* Global index in a NIC controller */
181
182	bool alloced;
183	};
184
185	enum hclge_fc_mode {
186	HCLGE_FC_NONE,
187	HCLGE_FC_RX_PAUSE,
188	HCLGE_FC_TX_PAUSE,
189	HCLGE_FC_FULL,
190	HCLGE_FC_PFC,
191	HCLGE_FC_DEFAULT
192	};
193
194	#define HCLGE_PG_NUM 4
195	#define HCLGE_SCH_MODE_SP 0
196	#define HCLGE_SCH_MODE_DWRR 1
197	struct hclge_pg_info {
198	u8 pg_id;
199	u8 pg_sch_mode; /* 0: sp; 1: dwrr */
200	u8 tc_bit_map;
201	u32 bw_limit;
202	u8 tc_dwrr[HNAE3_MAX_TC];
203	};
204
205	struct hclge_tc_info {
206	u8 tc_id;
207	u8 tc_sch_mode; /* 0: sp; 1: dwrr */
46a3df9f S	208	u8 pgid;
	209	u32 bw_limit;
	210	};
	211
	212	struct hclge_cfg {
	213	u8 vmdq_vport_num;
	214	u8 tc_num;
	215	u16 tqp_desc_num;
	216	u16 rx_buf_len;
	217	u8 phy_addr;
	218	u8 media_type;
	219	u8 mac_addr[ETH_ALEN];
	220	u8 default_speed;
	221	u32 numa_node_map;
	222	};
	223
	224	struct hclge_tm_info {
	225	u8 num_tc;
	226	u8 num_pg; /* It must be 1 if vNET-Base schd */
	227	u8 pg_dwrr[HCLGE_PG_NUM];
c5795c53	228	u8 prio_tc[HNAE3_MAX_USER_PRIO];
46a3df9f S	229	struct hclge_pg_info pg_info[HCLGE_PG_NUM];
	230	struct hclge_tc_info tc_info[HNAE3_MAX_TC];
	231	enum hclge_fc_mode fc_mode;
	232	u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
	233	};
	234
	235	struct hclge_comm_stats_str {
	236	char desc[ETH_GSTRING_LEN];
	237	unsigned long offset;
	238	};
	239
	240	/* all 64bit stats, opcode id: 0x0030 */
	241	struct hclge_64_bit_stats {
	242	/* query_igu_stat */
	243	u64 igu_rx_oversize_pkt;
	244	u64 igu_rx_undersize_pkt;
	245	u64 igu_rx_out_all_pkt;
	246	u64 igu_rx_uni_pkt;
	247	u64 igu_rx_multi_pkt;
	248	u64 igu_rx_broad_pkt;
	249	u64 rsv0;
	250
	251	/* query_egu_stat */
	252	u64 egu_tx_out_all_pkt;
	253	u64 egu_tx_uni_pkt;
	254	u64 egu_tx_multi_pkt;
	255	u64 egu_tx_broad_pkt;
	256
	257	/* ssu_ppp packet stats */
	258	u64 ssu_ppp_mac_key_num;
	259	u64 ssu_ppp_host_key_num;
	260	u64 ppp_ssu_mac_rlt_num;
	261	u64 ppp_ssu_host_rlt_num;
	262
	263	/* ssu_tx_in_out_dfx_stats */
	264	u64 ssu_tx_in_num;
	265	u64 ssu_tx_out_num;
	266	/* ssu_rx_in_out_dfx_stats */
	267	u64 ssu_rx_in_num;
	268	u64 ssu_rx_out_num;
	269	};
	270
	271	/* all 32bit stats, opcode id: 0x0031 */
	272	struct hclge_32_bit_stats {
	273	u64 igu_rx_err_pkt;
	274	u64 igu_rx_no_eof_pkt;
	275	u64 igu_rx_no_sof_pkt;
	276	u64 egu_tx_1588_pkt;
	277	u64 egu_tx_err_pkt;
	278	u64 ssu_full_drop_num;
	279	u64 ssu_part_drop_num;
	280	u64 ppp_key_drop_num;
	281	u64 ppp_rlt_drop_num;
	282	u64 ssu_key_drop_num;
	283	u64 pkt_curr_buf_cnt;
	284	u64 qcn_fb_rcv_cnt;
	285	u64 qcn_fb_drop_cnt;
	286	u64 qcn_fb_invaild_cnt;
	287	u64 rsv0;
	288	u64 rx_packet_tc0_in_cnt;
	289	u64 rx_packet_tc1_in_cnt;
	290	u64 rx_packet_tc2_in_cnt;
	291	u64 rx_packet_tc3_in_cnt;
	292	u64 rx_packet_tc4_in_cnt;
293	u64 rx_packet_tc5_in_cnt;
294	u64 rx_packet_tc6_in_cnt;
295	u64 rx_packet_tc7_in_cnt;
296	u64 rx_packet_tc0_out_cnt;
297	u64 rx_packet_tc1_out_cnt;
298	u64 rx_packet_tc2_out_cnt;
299	u64 rx_packet_tc3_out_cnt;
300	u64 rx_packet_tc4_out_cnt;
301	u64 rx_packet_tc5_out_cnt;
302	u64 rx_packet_tc6_out_cnt;
303	u64 rx_packet_tc7_out_cnt;
304
305	/* Tx packet level statistics */
306	u64 tx_packet_tc0_in_cnt;
307	u64 tx_packet_tc1_in_cnt;
308	u64 tx_packet_tc2_in_cnt;
309	u64 tx_packet_tc3_in_cnt;
310	u64 tx_packet_tc4_in_cnt;
311	u64 tx_packet_tc5_in_cnt;
312	u64 tx_packet_tc6_in_cnt;
313	u64 tx_packet_tc7_in_cnt;
314	u64 tx_packet_tc0_out_cnt;
315	u64 tx_packet_tc1_out_cnt;
316	u64 tx_packet_tc2_out_cnt;
317	u64 tx_packet_tc3_out_cnt;
318	u64 tx_packet_tc4_out_cnt;
319	u64 tx_packet_tc5_out_cnt;
320	u64 tx_packet_tc6_out_cnt;
321	u64 tx_packet_tc7_out_cnt;
322
323	/* packet buffer statistics */
324	u64 pkt_curr_buf_tc0_cnt;
325	u64 pkt_curr_buf_tc1_cnt;
326	u64 pkt_curr_buf_tc2_cnt;
327	u64 pkt_curr_buf_tc3_cnt;
328	u64 pkt_curr_buf_tc4_cnt;
329	u64 pkt_curr_buf_tc5_cnt;
330	u64 pkt_curr_buf_tc6_cnt;
331	u64 pkt_curr_buf_tc7_cnt;
332
333	u64 mb_uncopy_num;
334	u64 lo_pri_unicast_rlt_drop_num;
335	u64 hi_pri_multicast_rlt_drop_num;
336	u64 lo_pri_multicast_rlt_drop_num;
337	u64 rx_oq_drop_pkt_cnt;
338	u64 tx_oq_drop_pkt_cnt;
339	u64 nic_l2_err_drop_pkt_cnt;
340	u64 roc_l2_err_drop_pkt_cnt;
341	};
342
343	/* mac stats ,opcode id: 0x0032 */
344	struct hclge_mac_stats {
345	u64 mac_tx_mac_pause_num;
346	u64 mac_rx_mac_pause_num;
347	u64 mac_tx_pfc_pri0_pkt_num;
348	u64 mac_tx_pfc_pri1_pkt_num;
349	u64 mac_tx_pfc_pri2_pkt_num;
350	u64 mac_tx_pfc_pri3_pkt_num;
351	u64 mac_tx_pfc_pri4_pkt_num;
352	u64 mac_tx_pfc_pri5_pkt_num;
353	u64 mac_tx_pfc_pri6_pkt_num;
354	u64 mac_tx_pfc_pri7_pkt_num;
355	u64 mac_rx_pfc_pri0_pkt_num;
356	u64 mac_rx_pfc_pri1_pkt_num;
357	u64 mac_rx_pfc_pri2_pkt_num;
358	u64 mac_rx_pfc_pri3_pkt_num;
359	u64 mac_rx_pfc_pri4_pkt_num;
360	u64 mac_rx_pfc_pri5_pkt_num;
361	u64 mac_rx_pfc_pri6_pkt_num;
362	u64 mac_rx_pfc_pri7_pkt_num;
363	u64 mac_tx_total_pkt_num;
364	u64 mac_tx_total_oct_num;
365	u64 mac_tx_good_pkt_num;
366	u64 mac_tx_bad_pkt_num;
367	u64 mac_tx_good_oct_num;
368	u64 mac_tx_bad_oct_num;
369	u64 mac_tx_uni_pkt_num;
370	u64 mac_tx_multi_pkt_num;
371	u64 mac_tx_broad_pkt_num;
372	u64 mac_tx_undersize_pkt_num;
373	u64 mac_tx_overrsize_pkt_num;
374	u64 mac_tx_64_oct_pkt_num;
375	u64 mac_tx_65_127_oct_pkt_num;
376	u64 mac_tx_128_255_oct_pkt_num;
377	u64 mac_tx_256_511_oct_pkt_num;
378	u64 mac_tx_512_1023_oct_pkt_num;
379	u64 mac_tx_1024_1518_oct_pkt_num;
380	u64 mac_tx_1519_max_oct_pkt_num;
381	u64 mac_rx_total_pkt_num;
382	u64 mac_rx_total_oct_num;
383	u64 mac_rx_good_pkt_num;
384	u64 mac_rx_bad_pkt_num;
385	u64 mac_rx_good_oct_num;
386	u64 mac_rx_bad_oct_num;
387	u64 mac_rx_uni_pkt_num;
388	u64 mac_rx_multi_pkt_num;
389	u64 mac_rx_broad_pkt_num;
390	u64 mac_rx_undersize_pkt_num;
391	u64 mac_rx_overrsize_pkt_num;
392	u64 mac_rx_64_oct_pkt_num;
393	u64 mac_rx_65_127_oct_pkt_num;
394	u64 mac_rx_128_255_oct_pkt_num;
395	u64 mac_rx_256_511_oct_pkt_num;
396	u64 mac_rx_512_1023_oct_pkt_num;
397	u64 mac_rx_1024_1518_oct_pkt_num;
398	u64 mac_rx_1519_max_oct_pkt_num;
399
400	u64 mac_trans_fragment_pkt_num;
401	u64 mac_trans_undermin_pkt_num;
402	u64 mac_trans_jabber_pkt_num;
403	u64 mac_trans_err_all_pkt_num;
404	u64 mac_trans_from_app_good_pkt_num;
405	u64 mac_trans_from_app_bad_pkt_num;
406	u64 mac_rcv_fragment_pkt_num;
407	u64 mac_rcv_undermin_pkt_num;
408	u64 mac_rcv_jabber_pkt_num;
409	u64 mac_rcv_fcs_err_pkt_num;
410	u64 mac_rcv_send_app_good_pkt_num;
411	u64 mac_rcv_send_app_bad_pkt_num;
412	};
413
414	struct hclge_hw_stats {
415	struct hclge_mac_stats mac_stats;
416	struct hclge_64_bit_stats all_64_bit_stats;
417	struct hclge_32_bit_stats all_32_bit_stats;
418	};
419
420	struct hclge_dev {
421	struct pci_dev *pdev;
422	struct hnae3_ae_dev *ae_dev;
423	struct hclge_hw hw;
466b0c00	424	struct hclge_misc_vector misc_vector;
46a3df9f S	425	struct hclge_hw_stats hw_stats;
	426	unsigned long state;
	427
4ed340ab	428	enum hnae3_reset_type reset_type;
ca1d7669	429	unsigned long reset_pending; /* client rst is pending to be served */
46a3df9f S	430	u32 fw_version;
	431	u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */
	432	u16 num_tqps; /* Num task queue pairs of this PF */
	433	u16 num_req_vfs; /* Num VFs requested for this PF */
	434
46a3df9f S	435	/* Base task tqp physical id of this PF */
	436	u16 base_tqp_pid;
	437	u16 alloc_rss_size; /* Allocated RSS task queue */
	438	u16 rss_size_max; /* HW defined max RSS task queue */
	439
	440	/* Num of guaranteed filters for this PF */
	441	u16 fdir_pf_filter_count;
	442	u16 num_alloc_vport; /* Num vports this driver supports */
	443	u32 numa_node_mask;
	444	u16 rx_buf_len;
	445	u16 num_desc;
	446	u8 hw_tc_map;
	447	u8 tc_num_last_time;
	448	enum hclge_fc_mode fc_mode_last_time;
	449
	450	#define HCLGE_FLAG_TC_BASE_SCH_MODE 1
	451	#define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
	452	u8 tx_sch_mode;
cacde272 YL	453	u8 tc_max;
cacde272 YL	454	u8 pfc_max;
46a3df9f S	455
46a3df9f S	456	u8 default_up;
cacde272	457	u8 dcbx_cap;
46a3df9f S	458	struct hclge_tm_info tm_info;
	459
	460	u16 num_msi;
	461	u16 num_msi_left;
	462	u16 num_msi_used;
	463	u32 base_msi_vector;
46a3df9f	464	u16 *vector_status;
887c3820 SM	465	int *vector_irq;
	466	u16 num_roce_msi; /* Num of roce vectors for this PF */
	467	int roce_base_vector;
46a3df9f S	468
	469	u16 pending_udp_bitmap;
	470
	471	u16 rx_itr_default;
	472	u16 tx_itr_default;
	473
	474	u16 adminq_work_limit; /* Num of admin receive queue desc to process */
	475	unsigned long service_timer_period;
	476	unsigned long service_timer_previous;
	477	struct timer_list service_timer;
	478	struct work_struct service_task;
	479
	480	bool cur_promisc;
	481	int num_alloc_vfs; /* Actual number of VFs allocated */
	482
	483	struct hclge_tqp *htqp;
	484	struct hclge_vport *vport;
	485
	486	struct dentry *hclge_dbgfs;
	487
	488	struct hnae3_client *nic_client;
	489	struct hnae3_client *roce_client;
	490
887c3820 SM	491	#define HCLGE_FLAG_MAIN BIT(0)
	492	#define HCLGE_FLAG_DCB_CAPABLE BIT(1)
	493	#define HCLGE_FLAG_DCB_ENABLE BIT(2)
	494	#define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
46a3df9f S	495	u32 flag;
	496
	497	u32 pkt_buf_size; /* Total pf buf size for tx/rx */
	498	u32 mps; /* Max packet size */
46a3df9f S	499
	500	enum hclge_mta_dmac_sel_type mta_mac_sel_type;
	501	bool enable_mta; /* Mutilcast filter enable */
	502	bool accept_mta_mc; /* Whether accept mta filter multicast */
	503	};
	504
	505	struct hclge_vport {
	506	u16 alloc_tqps; /* Allocated Tx/Rx queues */
	507
	508	u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
	509	/* User configured lookup table entries */
	510	u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
68ece54e	511	u16 alloc_rss_size;
46a3df9f S	512
	513	u16 qs_offset;
	514	u16 bw_limit; /* VSI BW Limit (0 = disabled) */
	515	u8 dwrr;
	516
	517	int vport_id;
	518	struct hclge_dev back; / Back reference to associated dev */
	519	struct hnae3_handle nic;
	520	struct hnae3_handle roce;
	521	};
	522
	523	void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
	524	bool en_mc, bool en_bc, int vport_id);
	525
	526	int hclge_add_uc_addr_common(struct hclge_vport *vport,
	527	const unsigned char *addr);
	528	int hclge_rm_uc_addr_common(struct hclge_vport *vport,
	529	const unsigned char *addr);
	530	int hclge_add_mc_addr_common(struct hclge_vport *vport,
	531	const unsigned char *addr);
	532	int hclge_rm_mc_addr_common(struct hclge_vport *vport,
	533	const unsigned char *addr);
	534
	535	int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
	536	u8 func_id,
	537	bool enable);
	538	struct hclge_vport hclge_get_vport(struct hnae3_handle handle);
	539	int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector,
	540	struct hnae3_ring_chain_node *ring_chain);
	541	static inline int hclge_get_queue_id(struct hnae3_queue *queue)
	542	{
	543	struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
	544
	545	return tqp->index;
	546	}
	547
	548	int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
	549	int hclge_set_vf_vlan_common(struct hclge_dev *vport, int vfid,
	550	bool is_kill, u16 vlan, u8 qos, __be16 proto);
77f255c1 YL	551
	552	int hclge_buffer_alloc(struct hclge_dev *hdev);
	553	int hclge_rss_init_hw(struct hclge_dev *hdev);
46a3df9f	554	#endif