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net: hns3: add vector status check before free vector
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3vf / hclgevf_main.c
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5bc3f5f3
SM		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
3
4#include <linux/etherdevice.h>
3a6b148b 5#include <net/rtnetlink.h>
5bc3f5f3
SM		 6#include "hclgevf_cmd.h"
7#include "hclgevf_main.h"
8#include "hclge_mbx.h"
9#include "hnae3.h"
10
11#define HCLGEVF_NAME "hclgevf"
12
1f05a70d
SM		 13static int hclgevf_init_hdev(struct hclgevf_dev *hdev);
14static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev);
5bc3f5f3
SM		 15static struct hnae3_ae_algo ae_algovf;
16
17static const struct pci_device_id ae_algovf_pci_tbl[] = {
18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
20 /* required last entry */
21 {0, }
22};
23
28d9cec8
YL		 24MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
25
5bc3f5f3
SM		 26static inline struct hclgevf_dev *hclgevf_ae_get_hdev(
27 struct hnae3_handle *handle)
28{
29 return container_of(handle, struct hclgevf_dev, nic);
30}
31
32static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
33{
34 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
35 struct hnae3_queue *queue;
36 struct hclgevf_desc desc;
37 struct hclgevf_tqp *tqp;
38 int status;
39 int i;
40
41 for (i = 0; i < hdev->num_tqps; i++) {
42 queue = handle->kinfo.tqp[i];
43 tqp = container_of(queue, struct hclgevf_tqp, q);
44 hclgevf_cmd_setup_basic_desc(&desc,
45 HCLGEVF_OPC_QUERY_RX_STATUS,
46 true);
47
48 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
49 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
50 if (status) {
51 dev_err(&hdev->pdev->dev,
52 "Query tqp stat fail, status = %d,queue = %d\n",
53 status, i);
54 return status;
55 }
56 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 57 le32_to_cpu(desc.data[1]);
5bc3f5f3
SM		 58
59 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
60 true);
61
62 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
63 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
64 if (status) {
65 dev_err(&hdev->pdev->dev,
66 "Query tqp stat fail, status = %d,queue = %d\n",
67 status, i);
68 return status;
69 }
70 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 71 le32_to_cpu(desc.data[1]);
5bc3f5f3
SM		 72 }
73
74 return 0;
75}
76
77static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
78{
79 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
80 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
81 struct hclgevf_tqp *tqp;
82 u64 *buff = data;
83 int i;
84
85 for (i = 0; i < hdev->num_tqps; i++) {
86 tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q);
87 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
88 }
89 for (i = 0; i < kinfo->num_tqps; i++) {
90 tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q);
91 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
92 }
93
94 return buff;
95}
96
97static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
98{
99 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
100
101 return hdev->num_tqps * 2;
102}
103
104static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
105{
106 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
107 u8 *buff = data;
108 int i = 0;
109
110 for (i = 0; i < hdev->num_tqps; i++) {
111 struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i],
112 struct hclgevf_tqp, q);
c36317be 113 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
5bc3f5f3
SM		 114 tqp->index);
115 buff += ETH_GSTRING_LEN;
116 }
117
118 for (i = 0; i < hdev->num_tqps; i++) {
119 struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i],
120 struct hclgevf_tqp, q);
c36317be 121 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
5bc3f5f3
SM		 122 tqp->index);
123 buff += ETH_GSTRING_LEN;
124 }
125
126 return buff;
127}
128
129static void hclgevf_update_stats(struct hnae3_handle *handle,
130 struct net_device_stats *net_stats)
131{
132 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
133 int status;
134
135 status = hclgevf_tqps_update_stats(handle);
136 if (status)
137 dev_err(&hdev->pdev->dev,
138 "VF update of TQPS stats fail, status = %d.\n",
139 status);
140}
141
142static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
143{
144 if (strset == ETH_SS_TEST)
145 return -EOPNOTSUPP;
146 else if (strset == ETH_SS_STATS)
147 return hclgevf_tqps_get_sset_count(handle, strset);
148
149 return 0;
150}
151
152static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
153 u8 *data)
154{
155 u8 *p = (char *)data;
156
157 if (strset == ETH_SS_STATS)
158 p = hclgevf_tqps_get_strings(handle, p);
159}
160
161static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
162{
163 hclgevf_tqps_get_stats(handle, data);
164}
165
166static int hclgevf_get_tc_info(struct hclgevf_dev *hdev)
167{
168 u8 resp_msg;
169 int status;
170
171 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0,
172 true, &resp_msg, sizeof(u8));
173 if (status) {
174 dev_err(&hdev->pdev->dev,
175 "VF request to get TC info from PF failed %d",
176 status);
177 return status;
178 }
179
180 hdev->hw_tc_map = resp_msg;
181
182 return 0;
183}
184
185static int hclge_get_queue_info(struct hclgevf_dev *hdev)
186{
187#define HCLGEVF_TQPS_RSS_INFO_LEN 8
188 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
189 int status;
190
191 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0,
192 true, resp_msg,
193 HCLGEVF_TQPS_RSS_INFO_LEN);
194 if (status) {
195 dev_err(&hdev->pdev->dev,
196 "VF request to get tqp info from PF failed %d",
197 status);
198 return status;
199 }
200
201 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16));
202 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16));
203 memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16));
204 memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16));
205
206 return 0;
207}
208
5bc3f5f3
SM		 209static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
210{
211 struct hclgevf_tqp *tqp;
212 int i;
213
1f05a70d
SM		 214 /* if this is on going reset then we need to re-allocate the TPQs
215 * since we cannot assume we would get same number of TPQs back from PF
216 */
217 if (hclgevf_dev_ongoing_reset(hdev))
218 devm_kfree(&hdev->pdev->dev, hdev->htqp);
219
5bc3f5f3
SM		 220 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
221 sizeof(struct hclgevf_tqp), GFP_KERNEL);
222 if (!hdev->htqp)
223 return -ENOMEM;
224
225 tqp = hdev->htqp;
226
227 for (i = 0; i < hdev->num_tqps; i++) {
228 tqp->dev = &hdev->pdev->dev;
229 tqp->index = i;
230
231 tqp->q.ae_algo = &ae_algovf;
232 tqp->q.buf_size = hdev->rx_buf_len;
233 tqp->q.desc_num = hdev->num_desc;
234 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
235 i * HCLGEVF_TQP_REG_SIZE;
236
237 tqp++;
238 }
239
240 return 0;
241}
242
243static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
244{
245 struct hnae3_handle *nic = &hdev->nic;
246 struct hnae3_knic_private_info *kinfo;
247 u16 new_tqps = hdev->num_tqps;
248 int i;
249
250 kinfo = &nic->kinfo;
251 kinfo->num_tc = 0;
252 kinfo->num_desc = hdev->num_desc;
253 kinfo->rx_buf_len = hdev->rx_buf_len;
254 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
255 if (hdev->hw_tc_map & BIT(i))
256 kinfo->num_tc++;
257
258 kinfo->rss_size
259 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc);
260 new_tqps = kinfo->rss_size * kinfo->num_tc;
261 kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
262
1f05a70d
SM		 263 /* if this is on going reset then we need to re-allocate the hnae queues
264 * as well since number of TPQs from PF might have changed.
265 */
266 if (hclgevf_dev_ongoing_reset(hdev))
267 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
268
5bc3f5f3
SM		 269 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
270 sizeof(struct hnae3_queue *), GFP_KERNEL);
271 if (!kinfo->tqp)
272 return -ENOMEM;
273
274 for (i = 0; i < kinfo->num_tqps; i++) {
275 hdev->htqp[i].q.handle = &hdev->nic;
276 hdev->htqp[i].q.tqp_index = i;
277 kinfo->tqp[i] = &hdev->htqp[i].q;
278 }
279
280 return 0;
281}
282
283static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
284{
285 int status;
286 u8 resp_msg;
287
288 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL,
289 0, false, &resp_msg, sizeof(u8));
290 if (status)
291 dev_err(&hdev->pdev->dev,
292 "VF failed to fetch link status(%d) from PF", status);
293}
294
295void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
296{
bc0b7416 297 struct hnae3_handle *rhandle = &hdev->roce;
5bc3f5f3 298 struct hnae3_handle *handle = &hdev->nic;
15a50665 299 struct hnae3_client *rclient;
5bc3f5f3
SM		 300 struct hnae3_client *client;
301
302 client = handle->client;
15a50665 303 rclient = hdev->roce_client;
5bc3f5f3
SM		 304
305 if (link_state != hdev->hw.mac.link) {
306 client->ops->link_status_change(handle, !!link_state);
15a50665 307 if (rclient && rclient->ops->link_status_change)
bc0b7416 308 rclient->ops->link_status_change(rhandle, !!link_state);
5bc3f5f3
SM		 309 hdev->hw.mac.link = link_state;
310 }
311}
312
313static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
314{
315 struct hnae3_handle *nic = &hdev->nic;
316 int ret;
317
318 nic->ae_algo = &ae_algovf;
319 nic->pdev = hdev->pdev;
320 nic->numa_node_mask = hdev->numa_node_mask;
a9c89a3f 321 nic->flags |= HNAE3_SUPPORT_VF;
5bc3f5f3
SM		 322
323 if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) {
324 dev_err(&hdev->pdev->dev, "unsupported device type %d\n",
325 hdev->ae_dev->dev_type);
326 return -EINVAL;
327 }
328
329 ret = hclgevf_knic_setup(hdev);
330 if (ret)
331 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
332 ret);
333 return ret;
334}
335
336static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
337{
1dc5378f
PL		 338 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
339 dev_warn(&hdev->pdev->dev,
340 "vector(vector_id %d) has been freed.\n", vector_id);
341 return;
342 }
343
5bc3f5f3
SM		 344 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
345 hdev->num_msi_left += 1;
346 hdev->num_msi_used -= 1;
347}
348
349static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
350 struct hnae3_vector_info *vector_info)
351{
352 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
353 struct hnae3_vector_info *vector = vector_info;
354 int alloc = 0;
355 int i, j;
356
357 vector_num = min(hdev->num_msi_left, vector_num);
358
359 for (j = 0; j < vector_num; j++) {
360 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
361 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
362 vector->vector = pci_irq_vector(hdev->pdev, i);
363 vector->io_addr = hdev->hw.io_base +
364 HCLGEVF_VECTOR_REG_BASE +
365 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
366 hdev->vector_status[i] = 0;
367 hdev->vector_irq[i] = vector->vector;
368
369 vector++;
370 alloc++;
371
372 break;
373 }
374 }
375 }
376 hdev->num_msi_left -= alloc;
377 hdev->num_msi_used += alloc;
378
379 return alloc;
380}
381
382static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
383{
384 int i;
385
386 for (i = 0; i < hdev->num_msi; i++)
387 if (vector == hdev->vector_irq[i])
388 return i;
389
390 return -EINVAL;
391}
392
393static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
394{
395 return HCLGEVF_RSS_KEY_SIZE;
396}
397
398static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle)
399{
400 return HCLGEVF_RSS_IND_TBL_SIZE;
401}
402
403static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
404{
405 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
406 struct hclgevf_rss_indirection_table_cmd *req;
407 struct hclgevf_desc desc;
408 int status;
409 int i, j;
410
411 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
412
413 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) {
414 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
415 false);
416 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE;
417 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK;
418 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
419 req->rss_result[j] =
420 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
421
422 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
423 if (status) {
424 dev_err(&hdev->pdev->dev,
425 "VF failed(=%d) to set RSS indirection table\n",
426 status);
427 return status;
428 }
429 }
430
431 return 0;
432}
433
434static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size)
435{
436 struct hclgevf_rss_tc_mode_cmd *req;
437 u16 tc_offset[HCLGEVF_MAX_TC_NUM];
438 u16 tc_valid[HCLGEVF_MAX_TC_NUM];
439 u16 tc_size[HCLGEVF_MAX_TC_NUM];
440 struct hclgevf_desc desc;
441 u16 roundup_size;
442 int status;
443 int i;
444
445 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
446
447 roundup_size = roundup_pow_of_two(rss_size);
448 roundup_size = ilog2(roundup_size);
449
450 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
451 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
452 tc_size[i] = roundup_size;
453 tc_offset[i] = rss_size * i;
454 }
455
456 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
457 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
928d369a 458 hnae_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B,
459 (tc_valid[i] & 0x1));
460 hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M,
461 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
462 hnae_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M,
463 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
5bc3f5f3
SM		 464 }
465 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
466 if (status)
467 dev_err(&hdev->pdev->dev,
468 "VF failed(=%d) to set rss tc mode\n", status);
469
470 return status;
471}
472
473static int hclgevf_get_rss_hw_cfg(struct hnae3_handle *handle, u8 *hash,
474 u8 *key)
475{
476 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
477 struct hclgevf_rss_config_cmd *req;
478 int lkup_times = key ? 3 : 1;
479 struct hclgevf_desc desc;
480 int key_offset;
481 int key_size;
482 int status;
483
484 req = (struct hclgevf_rss_config_cmd *)desc.data;
485 lkup_times = (lkup_times == 3) ? 3 : ((hash) ? 1 : 0);
486
487 for (key_offset = 0; key_offset < lkup_times; key_offset++) {
488 hclgevf_cmd_setup_basic_desc(&desc,
489 HCLGEVF_OPC_RSS_GENERIC_CONFIG,
490 true);
491 req->hash_config |= (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET);
492
493 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
494 if (status) {
495 dev_err(&hdev->pdev->dev,
496 "failed to get hardware RSS cfg, status = %d\n",
497 status);
498 return status;
499 }
500
501 if (key_offset == 2)
502 key_size =
503 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2;
504 else
505 key_size = HCLGEVF_RSS_HASH_KEY_NUM;
506
507 if (key)
508 memcpy(key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM,
509 req->hash_key,
510 key_size);
511 }
512
513 if (hash) {
514 if ((req->hash_config & 0xf) == HCLGEVF_RSS_HASH_ALGO_TOEPLITZ)
515 *hash = ETH_RSS_HASH_TOP;
516 else
517 *hash = ETH_RSS_HASH_UNKNOWN;
518 }
519
520 return 0;
521}
522
523static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
524 u8 *hfunc)
525{
526 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
527 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
528 int i;
529
530 if (indir)
531 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
532 indir[i] = rss_cfg->rss_indirection_tbl[i];
533
534 return hclgevf_get_rss_hw_cfg(handle, hfunc, key);
535}
536
537static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
538 const u8 *key, const u8 hfunc)
539{
540 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
541 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
542 int i;
543
544 /* update the shadow RSS table with user specified qids */
545 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
546 rss_cfg->rss_indirection_tbl[i] = indir[i];
547
548 /* update the hardware */
549 return hclgevf_set_rss_indir_table(hdev);
550}
551
552static int hclgevf_get_tc_size(struct hnae3_handle *handle)
553{
554 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
555 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
556
557 return rss_cfg->rss_size;
558}
559
560static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
ddd58c64 561 int vector_id,
5bc3f5f3
SM		 562 struct hnae3_ring_chain_node *ring_chain)
563{
5bc3f5f3
SM		 564 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
565 struct hnae3_ring_chain_node *node;
566 struct hclge_mbx_vf_to_pf_cmd *req;
567 struct hclgevf_desc desc;
ddd58c64 568 int i = 0;
5bc3f5f3
SM		 569 int status;
570 u8 type;
571
572 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
5bc3f5f3 573
5bc3f5f3 574 for (node = ring_chain; node; node = node->next) {
ce50439a
YL		 575 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM +
576 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i;
577
578 if (i == 0) {
579 hclgevf_cmd_setup_basic_desc(&desc,
580 HCLGEVF_OPC_MBX_VF_TO_PF,
581 false);
582 type = en ?
583 HCLGE_MBX_MAP_RING_TO_VECTOR :
584 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
585 req->msg[0] = type;
586 req->msg[1] = vector_id;
587 }
588
589 req->msg[idx_offset] =
928d369a 590 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B);
ce50439a 591 req->msg[idx_offset + 1] = node->tqp_index;
928d369a 592 req->msg[idx_offset + 2] = hnae_get_field(node->int_gl_idx,
593 HNAE3_RING_GL_IDX_M,
594 HNAE3_RING_GL_IDX_S);
ce50439a
YL		 595
596 i++;
597 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM -
598 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) /
599 HCLGE_MBX_RING_NODE_VARIABLE_NUM) ||
600 !node->next) {
5bc3f5f3
SM		 601 req->msg[2] = i;
602
603 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
604 if (status) {
605 dev_err(&hdev->pdev->dev,
606 "Map TQP fail, status is %d.\n",
607 status);
608 return status;
609 }
610 i = 0;
611 hclgevf_cmd_setup_basic_desc(&desc,
612 HCLGEVF_OPC_MBX_VF_TO_PF,
613 false);
614 req->msg[0] = type;
615 req->msg[1] = vector_id;
616 }
617 }
618
5bc3f5f3
SM		 619 return 0;
620}
621
622static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
623 struct hnae3_ring_chain_node *ring_chain)
624{
ddd58c64
PL		 625 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
626 int vector_id;
627
628 vector_id = hclgevf_get_vector_index(hdev, vector);
629 if (vector_id < 0) {
630 dev_err(&handle->pdev->dev,
631 "Get vector index fail. ret =%d\n", vector_id);
632 return vector_id;
633 }
634
635 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
5bc3f5f3
SM		 636}
637
638static int hclgevf_unmap_ring_from_vector(
639 struct hnae3_handle *handle,
640 int vector,
641 struct hnae3_ring_chain_node *ring_chain)
642{
643 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
644 int ret, vector_id;
645
646 vector_id = hclgevf_get_vector_index(hdev, vector);
647 if (vector_id < 0) {
648 dev_err(&handle->pdev->dev,
649 "Get vector index fail. ret =%d\n", vector_id);
650 return vector_id;
651 }
652
ddd58c64 653 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
7412200c 654 if (ret)
5bc3f5f3
SM		 655 dev_err(&handle->pdev->dev,
656 "Unmap ring from vector fail. vector=%d, ret =%d\n",
657 vector_id,
658 ret);
7412200c
YL		 659
660 return ret;
661}
662
663static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
664{
665 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
5bc3f5f3 666
56525e90 667 hclgevf_free_vector(hdev, vector);
5bc3f5f3
SM		 668
669 return 0;
670}
671
e8600a3d
PL		 672static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
673 bool en_uc_pmc, bool en_mc_pmc)
5bc3f5f3
SM		 674{
675 struct hclge_mbx_vf_to_pf_cmd *req;
676 struct hclgevf_desc desc;
677 int status;
678
679 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
680
681 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false);
682 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE;
e8600a3d
PL		 683 req->msg[1] = en_uc_pmc ? 1 : 0;
684 req->msg[2] = en_mc_pmc ? 1 : 0;
5bc3f5f3
SM		 685
686 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
687 if (status)
688 dev_err(&hdev->pdev->dev,
689 "Set promisc mode fail, status is %d.\n", status);
690
691 return status;
692}
693
e8600a3d
PL		 694static void hclgevf_set_promisc_mode(struct hnae3_handle *handle,
695 bool en_uc_pmc, bool en_mc_pmc)
5bc3f5f3
SM		 696{
697 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
698
e8600a3d 699 hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc);
5bc3f5f3
SM		 700}
701
702static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id,
703 int stream_id, bool enable)
704{
705 struct hclgevf_cfg_com_tqp_queue_cmd *req;
706 struct hclgevf_desc desc;
707 int status;
708
709 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
710
711 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
712 false);
713 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
714 req->stream_id = cpu_to_le16(stream_id);
715 req->enable |= enable << HCLGEVF_TQP_ENABLE_B;
716
717 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
718 if (status)
719 dev_err(&hdev->pdev->dev,
720 "TQP enable fail, status =%d.\n", status);
721
722 return status;
723}
724
725static int hclgevf_get_queue_id(struct hnae3_queue *queue)
726{
727 struct hclgevf_tqp *tqp = container_of(queue, struct hclgevf_tqp, q);
728
729 return tqp->index;
730}
731
732static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
733{
734 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
735 struct hnae3_queue *queue;
736 struct hclgevf_tqp *tqp;
737 int i;
738
739 for (i = 0; i < hdev->num_tqps; i++) {
740 queue = handle->kinfo.tqp[i];
741 tqp = container_of(queue, struct hclgevf_tqp, q);
742 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
743 }
744}
745
038efa64
XW		 746static int hclgevf_cfg_func_mta_type(struct hclgevf_dev *hdev)
747{
748 u8 resp_msg = HCLGEVF_MTA_TYPE_SEL_MAX;
749 int ret;
750
751 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
752 HCLGE_MBX_MAC_VLAN_MTA_TYPE_READ,
753 NULL, 0, true, &resp_msg, sizeof(u8));
754
755 if (ret) {
756 dev_err(&hdev->pdev->dev,
757 "Read mta type fail, ret=%d.\n", ret);
758 return ret;
759 }
760
761 if (resp_msg > HCLGEVF_MTA_TYPE_SEL_MAX) {
762 dev_err(&hdev->pdev->dev,
763 "Read mta type invalid, resp=%d.\n", resp_msg);
764 return -EINVAL;
765 }
766
767 hdev->mta_mac_sel_type = resp_msg;
768
769 return 0;
770}
771
772static u16 hclgevf_get_mac_addr_to_mta_index(struct hclgevf_dev *hdev,
773 const u8 *addr)
774{
775 u32 rsh = HCLGEVF_MTA_TYPE_SEL_MAX - hdev->mta_mac_sel_type;
776 u16 high_val = addr[1] | (addr[0] << 8);
777
778 return (high_val >> rsh) & 0xfff;
779}
780
781static int hclgevf_do_update_mta_status(struct hclgevf_dev *hdev,
782 unsigned long *status)
783{
784#define HCLGEVF_MTA_STATUS_MSG_SIZE 13
785#define HCLGEVF_MTA_STATUS_MSG_BITS \
786 (HCLGEVF_MTA_STATUS_MSG_SIZE * BITS_PER_BYTE)
787#define HCLGEVF_MTA_STATUS_MSG_END_BITS \
788 (HCLGEVF_MTA_TBL_SIZE % HCLGEVF_MTA_STATUS_MSG_BITS)
789 u16 tbl_cnt;
790 u16 tbl_idx;
791 u8 msg_cnt;
792 u8 msg_idx;
793 int ret;
794
795 msg_cnt = DIV_ROUND_UP(HCLGEVF_MTA_TBL_SIZE,
796 HCLGEVF_MTA_STATUS_MSG_BITS);
797 tbl_idx = 0;
798 msg_idx = 0;
799 while (msg_cnt--) {
800 u8 msg[HCLGEVF_MTA_STATUS_MSG_SIZE + 1];
801 u8 *p = &msg[1];
802 u8 msg_ofs;
803 u8 msg_bit;
804
805 memset(msg, 0, sizeof(msg));
806
807 /* set index field */
808 msg[0] = 0x7F & msg_idx;
809
810 /* set end flag field */
811 if (msg_cnt == 0) {
812 msg[0] |= 0x80;
813 tbl_cnt = HCLGEVF_MTA_STATUS_MSG_END_BITS;
814 } else {
815 tbl_cnt = HCLGEVF_MTA_STATUS_MSG_BITS;
816 }
817
818 /* set status field */
819 msg_ofs = 0;
820 msg_bit = 0;
821 while (tbl_cnt--) {
822 if (test_bit(tbl_idx, status))
823 p[msg_ofs] |= BIT(msg_bit);
824
825 tbl_idx++;
826
827 msg_bit++;
828 if (msg_bit == BITS_PER_BYTE) {
829 msg_bit = 0;
830 msg_ofs++;
831 }
832 }
833
834 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
835 HCLGE_MBX_MAC_VLAN_MTA_STATUS_UPDATE,
836 msg, sizeof(msg), false, NULL, 0);
837 if (ret)
838 break;
839
840 msg_idx++;
841 }
842
843 return ret;
844}
845
846static int hclgevf_update_mta_status(struct hnae3_handle *handle)
847{
848 unsigned long mta_status[BITS_TO_LONGS(HCLGEVF_MTA_TBL_SIZE)];
849 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
850 struct net_device *netdev = hdev->nic.kinfo.netdev;
851 struct netdev_hw_addr *ha;
852 u16 tbl_idx;
853
854 /* clear status */
855 memset(mta_status, 0, sizeof(mta_status));
856
857 /* update status from mc addr list */
858 netdev_for_each_mc_addr(ha, netdev) {
859 tbl_idx = hclgevf_get_mac_addr_to_mta_index(hdev, ha->addr);
860 set_bit(tbl_idx, mta_status);
861 }
862
863 return hclgevf_do_update_mta_status(hdev, mta_status);
864}
865
5bc3f5f3
SM		 866static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
867{
868 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
869
870 ether_addr_copy(p, hdev->hw.mac.mac_addr);
871}
872
3cbf5e2d
FL		 873static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
874 bool is_first)
5bc3f5f3
SM		 875{
876 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
877 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
878 u8 *new_mac_addr = (u8 *)p;
879 u8 msg_data[ETH_ALEN * 2];
3cbf5e2d 880 u16 subcode;
5bc3f5f3
SM		 881 int status;
882
883 ether_addr_copy(msg_data, new_mac_addr);
884 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr);
885
3cbf5e2d
FL		 886 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD :
887 HCLGE_MBX_MAC_VLAN_UC_MODIFY;
888
5bc3f5f3 889 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
3cbf5e2d 890 subcode, msg_data, ETH_ALEN * 2,
5a955cd2 891 true, NULL, 0);
5bc3f5f3
SM		 892 if (!status)
893 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
894
895 return status;
896}
897
898static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
899 const unsigned char *addr)
900{
901 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
902
903 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
904 HCLGE_MBX_MAC_VLAN_UC_ADD,
905 addr, ETH_ALEN, false, NULL, 0);
906}
907
908static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
909 const unsigned char *addr)
910{
911 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
912
913 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
914 HCLGE_MBX_MAC_VLAN_UC_REMOVE,
915 addr, ETH_ALEN, false, NULL, 0);
916}
917
918static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
919 const unsigned char *addr)
920{
921 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
922
923 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
924 HCLGE_MBX_MAC_VLAN_MC_ADD,
925 addr, ETH_ALEN, false, NULL, 0);
926}
927
928static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
929 const unsigned char *addr)
930{
931 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
932
933 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
934 HCLGE_MBX_MAC_VLAN_MC_REMOVE,
935 addr, ETH_ALEN, false, NULL, 0);
936}
937
938static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
939 __be16 proto, u16 vlan_id,
940 bool is_kill)
941{
942#define HCLGEVF_VLAN_MBX_MSG_LEN 5
943 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
944 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN];
945
946 if (vlan_id > 4095)
947 return -EINVAL;
948
949 if (proto != htons(ETH_P_8021Q))
950 return -EPROTONOSUPPORT;
951
952 msg_data[0] = is_kill;
953 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
954 memcpy(&msg_data[3], &proto, sizeof(proto));
955 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
956 HCLGE_MBX_VLAN_FILTER, msg_data,
957 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0);
958}
959
3849d494
YL		 960static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
961{
962 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
963 u8 msg_data;
964
965 msg_data = enable ? 1 : 0;
966 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
967 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data,
968 1, false, NULL, 0);
969}
970
5bc3f5f3
SM		 971static void hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
972{
973 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
974 u8 msg_data[2];
d3ea7fc4 975 int ret;
5bc3f5f3
SM		 976
977 memcpy(&msg_data[0], &queue_id, sizeof(queue_id));
978
d3ea7fc4
PL		 979 /* disable vf queue before send queue reset msg to PF */
980 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false);
981 if (ret)
982 return;
983
984 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data,
985 2, true, NULL, 0);
5bc3f5f3
SM		 986}
987
3a6b148b
SM		 988static int hclgevf_notify_client(struct hclgevf_dev *hdev,
989 enum hnae3_reset_notify_type type)
990{
991 struct hnae3_client *client = hdev->nic_client;
992 struct hnae3_handle *handle = &hdev->nic;
993
994 if (!client->ops->reset_notify)
995 return -EOPNOTSUPP;
996
997 return client->ops->reset_notify(handle, type);
998}
999
1000static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1001{
1002#define HCLGEVF_RESET_WAIT_MS 500
1003#define HCLGEVF_RESET_WAIT_CNT 20
1004 u32 val, cnt = 0;
1005
1006 /* wait to check the hardware reset completion status */
1007 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
928d369a 1008 while (hnae_get_bit(val, HCLGEVF_FUN_RST_ING_B) &&
1009 (cnt < HCLGEVF_RESET_WAIT_CNT)) {
3a6b148b
SM		 1010 msleep(HCLGEVF_RESET_WAIT_MS);
1011 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
1012 cnt++;
1013 }
1014
1015 /* hardware completion status should be available by this time */
1016 if (cnt >= HCLGEVF_RESET_WAIT_CNT) {
1017 dev_warn(&hdev->pdev->dev,
1018 "could'nt get reset done status from h/w, timeout!\n");
1019 return -EBUSY;
1020 }
1021
1022 /* we will wait a bit more to let reset of the stack to complete. This
1023 * might happen in case reset assertion was made by PF. Yes, this also
1024 * means we might end up waiting bit more even for VF reset.
1025 */
1026 msleep(5000);
1027
1028 return 0;
1029}
1030
1031static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1032{
1f05a70d
SM		 1033 int ret;
1034
3a6b148b
SM		 1035 /* uninitialize the nic client */
1036 hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1037
1f05a70d
SM		 1038 /* re-initialize the hclge device */
1039 ret = hclgevf_init_hdev(hdev);
1040 if (ret) {
1041 dev_err(&hdev->pdev->dev,
1042 "hclge device re-init failed, VF is disabled!\n");
1043 return ret;
1044 }
3a6b148b
SM		 1045
1046 /* bring up the nic client again */
1047 hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1048
1049 return 0;
1050}
1051
1052static int hclgevf_reset(struct hclgevf_dev *hdev)
1053{
1054 int ret;
1055
1056 rtnl_lock();
1057
1058 /* bring down the nic to stop any ongoing TX/RX */
1059 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1060
1061 /* check if VF could successfully fetch the hardware reset completion
1062 * status from the hardware
1063 */
1064 ret = hclgevf_reset_wait(hdev);
1065 if (ret) {
1066 /* can't do much in this situation, will disable VF */
1067 dev_err(&hdev->pdev->dev,
1068 "VF failed(=%d) to fetch H/W reset completion status\n",
1069 ret);
1070
1071 dev_warn(&hdev->pdev->dev, "VF reset failed, disabling VF!\n");
1072 hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1073
1074 rtnl_unlock();
1075 return ret;
1076 }
1077
1078 /* now, re-initialize the nic client and ae device*/
1079 ret = hclgevf_reset_stack(hdev);
1080 if (ret)
1081 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1082
1083 /* bring up the nic to enable TX/RX again */
1084 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1085
1086 rtnl_unlock();
1087
1088 return ret;
1089}
1090
d0e76212
SM		 1091static int hclgevf_do_reset(struct hclgevf_dev *hdev)
1092{
1093 int status;
1094 u8 respmsg;
1095
1096 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL,
1097 0, false, &respmsg, sizeof(u8));
1098 if (status)
1099 dev_err(&hdev->pdev->dev,
1100 "VF reset request to PF failed(=%d)\n", status);
1101
1102 return status;
1103}
1104
4aef908d
SM		 1105static void hclgevf_reset_event(struct hnae3_handle *handle)
1106{
1107 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1108
1109 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1110
1111 handle->reset_level = HNAE3_VF_RESET;
1112
bb2edc2e
SM		 1113 /* reset of this VF requested */
1114 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
1115 hclgevf_reset_task_schedule(hdev);
4aef908d
SM		 1116
1117 handle->last_reset_time = jiffies;
1118}
1119
5bc3f5f3
SM		 1120static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
1121{
1122 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1123
1124 return hdev->fw_version;
1125}
1126
1127static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
1128{
1129 struct hclgevf_misc_vector *vector = &hdev->misc_vector;
1130
1131 vector->vector_irq = pci_irq_vector(hdev->pdev,
1132 HCLGEVF_MISC_VECTOR_NUM);
1133 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
1134 /* vector status always valid for Vector 0 */
1135 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
1136 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
1137
1138 hdev->num_msi_left -= 1;
1139 hdev->num_msi_used += 1;
1140}
1141
f0412650
SM		 1142void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
1143{
1144 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) &&
1145 !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) {
1146 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1147 schedule_work(&hdev->rst_service_task);
1148 }
1149}
1150
85a86c48 1151void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
5bc3f5f3 1152{
85a86c48
SM		 1153 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) &&
1154 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) {
1155 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
5bc3f5f3 1156 schedule_work(&hdev->mbx_service_task);
85a86c48 1157 }
5bc3f5f3
SM		 1158}
1159
1160static void hclgevf_task_schedule(struct hclgevf_dev *hdev)
1161{
1162 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) &&
1163 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state))
1164 schedule_work(&hdev->service_task);
1165}
1166
bb2edc2e
SM		 1167static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev)
1168{
85a86c48
SM		 1169 /* if we have any pending mailbox event then schedule the mbx task */
1170 if (hdev->mbx_event_pending)
1171 hclgevf_mbx_task_schedule(hdev);
1172
bb2edc2e
SM		 1173 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state))
1174 hclgevf_reset_task_schedule(hdev);
1175}
1176
5bc3f5f3
SM		 1177static void hclgevf_service_timer(struct timer_list *t)
1178{
1179 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer);
1180
1181 mod_timer(&hdev->service_timer, jiffies + 5 * HZ);
1182
1183 hclgevf_task_schedule(hdev);
1184}
1185
f0412650
SM		 1186static void hclgevf_reset_service_task(struct work_struct *work)
1187{
1188 struct hclgevf_dev *hdev =
1189 container_of(work, struct hclgevf_dev, rst_service_task);
d0e76212 1190 int ret;
f0412650
SM		 1191
1192 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1193 return;
1194
1195 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1196
bb2edc2e
SM		 1197 if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
1198 &hdev->reset_state)) {
1199 /* PF has initmated that it is about to reset the hardware.
1200 * We now have to poll & check if harware has actually completed
1201 * the reset sequence. On hardware reset completion, VF needs to
1202 * reset the client and ae device.
1203 */
1204 hdev->reset_attempts = 0;
1205
3a6b148b
SM		 1206 ret = hclgevf_reset(hdev);
1207 if (ret)
1208 dev_err(&hdev->pdev->dev, "VF stack reset failed.\n");
bb2edc2e
SM		 1209 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
1210 &hdev->reset_state)) {
1211 /* we could be here when either of below happens:
1212 * 1. reset was initiated due to watchdog timeout due to
1213 * a. IMP was earlier reset and our TX got choked down and
1214 * which resulted in watchdog reacting and inducing VF
1215 * reset. This also means our cmdq would be unreliable.
1216 * b. problem in TX due to other lower layer(example link
1217 * layer not functioning properly etc.)
1218 * 2. VF reset might have been initiated due to some config
1219 * change.
1220 *
1221 * NOTE: Theres no clear way to detect above cases than to react
1222 * to the response of PF for this reset request. PF will ack the
1223 * 1b and 2. cases but we will not get any intimation about 1a
1224 * from PF as cmdq would be in unreliable state i.e. mailbox
1225 * communication between PF and VF would be broken.
1226 */
1227
1228 /* if we are never geting into pending state it means either:
1229 * 1. PF is not receiving our request which could be due to IMP
1230 * reset
1231 * 2. PF is screwed
1232 * We cannot do much for 2. but to check first we can try reset
1233 * our PCIe + stack and see if it alleviates the problem.
1234 */
1235 if (hdev->reset_attempts > 3) {
1236 /* prepare for full reset of stack + pcie interface */
1237 hdev->nic.reset_level = HNAE3_VF_FULL_RESET;
1238
1239 /* "defer" schedule the reset task again */
1240 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1241 } else {
1242 hdev->reset_attempts++;
1243
1244 /* request PF for resetting this VF via mailbox */
d0e76212
SM		 1245 ret = hclgevf_do_reset(hdev);
1246 if (ret)
1247 dev_warn(&hdev->pdev->dev,
1248 "VF rst fail, stack will call\n");
bb2edc2e
SM		 1249 }
1250 }
f0412650
SM		 1251
1252 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1253}
1254
5bc3f5f3
SM		 1255static void hclgevf_mailbox_service_task(struct work_struct *work)
1256{
1257 struct hclgevf_dev *hdev;
1258
1259 hdev = container_of(work, struct hclgevf_dev, mbx_service_task);
1260
1261 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
1262 return;
1263
1264 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1265
85a86c48 1266 hclgevf_mbx_async_handler(hdev);
5bc3f5f3
SM		 1267
1268 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1269}
1270
1271static void hclgevf_service_task(struct work_struct *work)
1272{
1273 struct hclgevf_dev *hdev;
1274
1275 hdev = container_of(work, struct hclgevf_dev, service_task);
1276
1277 /* request the link status from the PF. PF would be able to tell VF
1278 * about such updates in future so we might remove this later
1279 */
1280 hclgevf_request_link_info(hdev);
1281
bb2edc2e
SM		 1282 hclgevf_deferred_task_schedule(hdev);
1283
5bc3f5f3
SM		 1284 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1285}
1286
1287static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
1288{
1289 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
1290}
1291
1292static bool hclgevf_check_event_cause(struct hclgevf_dev *hdev, u32 *clearval)
1293{
1294 u32 cmdq_src_reg;
1295
1296 /* fetch the events from their corresponding regs */
1297 cmdq_src_reg = hclgevf_read_dev(&hdev->hw,
1298 HCLGEVF_VECTOR0_CMDQ_SRC_REG);
1299
1300 /* check for vector0 mailbox(=CMDQ RX) event source */
1301 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
1302 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1303 *clearval = cmdq_src_reg;
1304 return true;
1305 }
1306
1307 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n");
1308
1309 return false;
1310}
1311
1312static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
1313{
1314 writel(en ? 1 : 0, vector->addr);
1315}
1316
1317static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
1318{
1319 struct hclgevf_dev *hdev = data;
1320 u32 clearval;
1321
1322 hclgevf_enable_vector(&hdev->misc_vector, false);
1323 if (!hclgevf_check_event_cause(hdev, &clearval))
1324 goto skip_sched;
1325
85a86c48 1326 hclgevf_mbx_handler(hdev);
5bc3f5f3
SM		 1327
1328 hclgevf_clear_event_cause(hdev, clearval);
1329
1330skip_sched:
1331 hclgevf_enable_vector(&hdev->misc_vector, true);
1332
1333 return IRQ_HANDLED;
1334}
1335
1336static int hclgevf_configure(struct hclgevf_dev *hdev)
1337{
1338 int ret;
1339
1340 /* get queue configuration from PF */
1341 ret = hclge_get_queue_info(hdev);
1342 if (ret)
1343 return ret;
1344 /* get tc configuration from PF */
1345 return hclgevf_get_tc_info(hdev);
1346}
1347
1f05a70d
SM		 1348static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
1349{
1350 struct pci_dev *pdev = ae_dev->pdev;
1351 struct hclgevf_dev *hdev = ae_dev->priv;
1352
1353 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
1354 if (!hdev)
1355 return -ENOMEM;
1356
1357 hdev->pdev = pdev;
1358 hdev->ae_dev = ae_dev;
1359 ae_dev->priv = hdev;
1360
1361 return 0;
1362}
1363
5bc3f5f3
SM		 1364static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
1365{
1366 struct hnae3_handle *roce = &hdev->roce;
1367 struct hnae3_handle *nic = &hdev->nic;
1368
1369 roce->rinfo.num_vectors = HCLGEVF_ROCEE_VECTOR_NUM;
1370
1371 if (hdev->num_msi_left < roce->rinfo.num_vectors ||
1372 hdev->num_msi_left == 0)
1373 return -EINVAL;
1374
1375 roce->rinfo.base_vector =
1376 hdev->vector_status[hdev->num_msi_used];
1377
1378 roce->rinfo.netdev = nic->kinfo.netdev;
1379 roce->rinfo.roce_io_base = hdev->hw.io_base;
1380
1381 roce->pdev = nic->pdev;
1382 roce->ae_algo = nic->ae_algo;
1383 roce->numa_node_mask = nic->numa_node_mask;
1384
1385 return 0;
1386}
1387
1388static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
1389{
1390 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1391 int i, ret;
1392
1393 rss_cfg->rss_size = hdev->rss_size_max;
1394
1395 /* Initialize RSS indirect table for each vport */
1396 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
1397 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max;
1398
1399 ret = hclgevf_set_rss_indir_table(hdev);
1400 if (ret)
1401 return ret;
1402
1403 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max);
1404}
1405
1406static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
1407{
1408 /* other vlan config(like, VLAN TX/RX offload) would also be added
1409 * here later
1410 */
1411 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
1412 false);
1413}
1414
1415static int hclgevf_ae_start(struct hnae3_handle *handle)
1416{
1417 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1418 int i, queue_id;
1419
1420 for (i = 0; i < handle->kinfo.num_tqps; i++) {
1421 /* ring enable */
1422 queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]);
1423 if (queue_id < 0) {
1424 dev_warn(&hdev->pdev->dev,
1425 "Get invalid queue id, ignore it\n");
1426 continue;
1427 }
1428
1429 hclgevf_tqp_enable(hdev, queue_id, 0, true);
1430 }
1431
1432 /* reset tqp stats */
1433 hclgevf_reset_tqp_stats(handle);
1434
1435 hclgevf_request_link_info(hdev);
1436
1437 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1438 mod_timer(&hdev->service_timer, jiffies + HZ);
1439
1440 return 0;
1441}
1442
1443static void hclgevf_ae_stop(struct hnae3_handle *handle)
1444{
1445 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1446 int i, queue_id;
1447
1448 for (i = 0; i < hdev->num_tqps; i++) {
1449 /* Ring disable */
1450 queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]);
1451 if (queue_id < 0) {
1452 dev_warn(&hdev->pdev->dev,
1453 "Get invalid queue id, ignore it\n");
1454 continue;
1455 }
1456
1457 hclgevf_tqp_enable(hdev, queue_id, 0, false);
1458 }
1459
1460 /* reset tqp stats */
1461 hclgevf_reset_tqp_stats(handle);
d14992df
FL		 1462 del_timer_sync(&hdev->service_timer);
1463 cancel_work_sync(&hdev->service_task);
42b11ab7 1464 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
d14992df 1465 hclgevf_update_link_status(hdev, 0);
5bc3f5f3
SM		 1466}
1467
1468static void hclgevf_state_init(struct hclgevf_dev *hdev)
1469{
1f05a70d
SM		 1470 /* if this is on going reset then skip this initialization */
1471 if (hclgevf_dev_ongoing_reset(hdev))
1472 return;
1473
5bc3f5f3
SM		 1474 /* setup tasks for the MBX */
1475 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task);
1476 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1477 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1478
1479 /* setup tasks for service timer */
1480 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0);
1481
1482 INIT_WORK(&hdev->service_task, hclgevf_service_task);
1483 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1484
f0412650
SM		 1485 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task);
1486
5bc3f5f3
SM		 1487 mutex_init(&hdev->mbx_resp.mbx_mutex);
1488
1489 /* bring the device down */
1490 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1491}
1492
1493static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
1494{
1495 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1496
1497 if (hdev->service_timer.function)
1498 del_timer_sync(&hdev->service_timer);
1499 if (hdev->service_task.func)
1500 cancel_work_sync(&hdev->service_task);
1501 if (hdev->mbx_service_task.func)
1502 cancel_work_sync(&hdev->mbx_service_task);
f0412650
SM		 1503 if (hdev->rst_service_task.func)
1504 cancel_work_sync(&hdev->rst_service_task);
5bc3f5f3
SM		 1505
1506 mutex_destroy(&hdev->mbx_resp.mbx_mutex);
1507}
1508
1509static int hclgevf_init_msi(struct hclgevf_dev *hdev)
1510{
1511 struct pci_dev *pdev = hdev->pdev;
1512 int vectors;
1513 int i;
1514
1f05a70d
SM		 1515 /* if this is on going reset then skip this initialization */
1516 if (hclgevf_dev_ongoing_reset(hdev))
1517 return 0;
1518
5bc3f5f3
SM		 1519 hdev->num_msi = HCLGEVF_MAX_VF_VECTOR_NUM;
1520
1521 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1522 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1523 if (vectors < 0) {
1524 dev_err(&pdev->dev,
1525 "failed(%d) to allocate MSI/MSI-X vectors\n",
1526 vectors);
1527 return vectors;
1528 }
1529 if (vectors < hdev->num_msi)
1530 dev_warn(&hdev->pdev->dev,
1531 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1532 hdev->num_msi, vectors);
1533
1534 hdev->num_msi = vectors;
1535 hdev->num_msi_left = vectors;
1536 hdev->base_msi_vector = pdev->irq;
1537
1538 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1539 sizeof(u16), GFP_KERNEL);
1540 if (!hdev->vector_status) {
1541 pci_free_irq_vectors(pdev);
1542 return -ENOMEM;
1543 }
1544
1545 for (i = 0; i < hdev->num_msi; i++)
1546 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
1547
1548 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1549 sizeof(int), GFP_KERNEL);
1550 if (!hdev->vector_irq) {
1551 pci_free_irq_vectors(pdev);
1552 return -ENOMEM;
1553 }
1554
1555 return 0;
1556}
1557
1558static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
1559{
1560 struct pci_dev *pdev = hdev->pdev;
1561
1562 pci_free_irq_vectors(pdev);
1563}
1564
1565static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
1566{
1567 int ret = 0;
1568
1f05a70d
SM		 1569 /* if this is on going reset then skip this initialization */
1570 if (hclgevf_dev_ongoing_reset(hdev))
1571 return 0;
1572
5bc3f5f3
SM		 1573 hclgevf_get_misc_vector(hdev);
1574
1575 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
1576 0, "hclgevf_cmd", hdev);
1577 if (ret) {
1578 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
1579 hdev->misc_vector.vector_irq);
1580 return ret;
1581 }
1582
3efc51e2
XW		 1583 hclgevf_clear_event_cause(hdev, 0);
1584
5bc3f5f3
SM		 1585 /* enable misc. vector(vector 0) */
1586 hclgevf_enable_vector(&hdev->misc_vector, true);
1587
1588 return ret;
1589}
1590
1591static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
1592{
1593 /* disable misc vector(vector 0) */
1594 hclgevf_enable_vector(&hdev->misc_vector, false);
3efc51e2 1595 synchronize_irq(hdev->misc_vector.vector_irq);
5bc3f5f3
SM		 1596 free_irq(hdev->misc_vector.vector_irq, hdev);
1597 hclgevf_free_vector(hdev, 0);
1598}
1599
2e32e9a5
PL		 1600static int hclgevf_init_client_instance(struct hnae3_client *client,
1601 struct hnae3_ae_dev *ae_dev)
5bc3f5f3 1602{
2e32e9a5 1603 struct hclgevf_dev *hdev = ae_dev->priv;
5bc3f5f3
SM		 1604 int ret;
1605
1606 switch (client->type) {
1607 case HNAE3_CLIENT_KNIC:
1608 hdev->nic_client = client;
1609 hdev->nic.client = client;
1610
1611 ret = client->ops->init_instance(&hdev->nic);
1612 if (ret)
1613 return ret;
1614
1615 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) {
1616 struct hnae3_client *rc = hdev->roce_client;
1617
1618 ret = hclgevf_init_roce_base_info(hdev);
1619 if (ret)
1620 return ret;
1621 ret = rc->ops->init_instance(&hdev->roce);
1622 if (ret)
1623 return ret;
1624 }
1625 break;
1626 case HNAE3_CLIENT_UNIC:
1627 hdev->nic_client = client;
1628 hdev->nic.client = client;
1629
1630 ret = client->ops->init_instance(&hdev->nic);
1631 if (ret)
1632 return ret;
1633 break;
1634 case HNAE3_CLIENT_ROCE:
4cc40db1
LO		 1635 if (hnae3_dev_roce_supported(hdev)) {
1636 hdev->roce_client = client;
1637 hdev->roce.client = client;
1638 }
5bc3f5f3 1639
4cc40db1 1640 if (hdev->roce_client && hdev->nic_client) {
5bc3f5f3
SM		 1641 ret = hclgevf_init_roce_base_info(hdev);
1642 if (ret)
1643 return ret;
1644
1645 ret = client->ops->init_instance(&hdev->roce);
1646 if (ret)
1647 return ret;
1648 }
1649 }
1650
1651 return 0;
1652}
1653
2e32e9a5
PL		 1654static void hclgevf_uninit_client_instance(struct hnae3_client *client,
1655 struct hnae3_ae_dev *ae_dev)
5bc3f5f3 1656{
2e32e9a5
PL		 1657 struct hclgevf_dev *hdev = ae_dev->priv;
1658
5bc3f5f3
SM		 1659 /* un-init roce, if it exists */
1660 if (hdev->roce_client)
1661 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
1662
1663 /* un-init nic/unic, if this was not called by roce client */
1664 if ((client->ops->uninit_instance) &&
1665 (client->type != HNAE3_CLIENT_ROCE))
1666 client->ops->uninit_instance(&hdev->nic, 0);
1667}
1668
5bc3f5f3
SM		 1669static int hclgevf_pci_init(struct hclgevf_dev *hdev)
1670{
1671 struct pci_dev *pdev = hdev->pdev;
1672 struct hclgevf_hw *hw;
1673 int ret;
1674
1f05a70d
SM		 1675 /* check if we need to skip initialization of pci. This will happen if
1676 * device is undergoing VF reset. Otherwise, we would need to
1677 * re-initialize pci interface again i.e. when device is not going
1678 * through *any* reset or actually undergoing full reset.
1679 */
1680 if (hclgevf_dev_ongoing_reset(hdev))
1681 return 0;
1682
5bc3f5f3
SM		 1683 ret = pci_enable_device(pdev);
1684 if (ret) {
1685 dev_err(&pdev->dev, "failed to enable PCI device\n");
6c46284e 1686 return ret;
5bc3f5f3
SM		 1687 }
1688
1689 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1690 if (ret) {
1691 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
1692 goto err_disable_device;
1693 }
1694
1695 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
1696 if (ret) {
1697 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
1698 goto err_disable_device;
1699 }
1700
1701 pci_set_master(pdev);
1702 hw = &hdev->hw;
1703 hw->hdev = hdev;
d2f70b04 1704 hw->io_base = pci_iomap(pdev, 2, 0);
5bc3f5f3
SM		 1705 if (!hw->io_base) {
1706 dev_err(&pdev->dev, "can't map configuration register space\n");
1707 ret = -ENOMEM;
1708 goto err_clr_master;
1709 }
1710
1711 return 0;
1712
1713err_clr_master:
1714 pci_clear_master(pdev);
1715 pci_release_regions(pdev);
1716err_disable_device:
1717 pci_disable_device(pdev);
6c46284e 1718
5bc3f5f3
SM		 1719 return ret;
1720}
1721
1722static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
1723{
1724 struct pci_dev *pdev = hdev->pdev;
1725
1726 pci_iounmap(pdev, hdev->hw.io_base);
1727 pci_clear_master(pdev);
1728 pci_release_regions(pdev);
1729 pci_disable_device(pdev);
5bc3f5f3
SM		 1730}
1731
1f05a70d 1732static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
5bc3f5f3 1733{
1f05a70d 1734 struct pci_dev *pdev = hdev->pdev;
5bc3f5f3
SM		 1735 int ret;
1736
1f05a70d
SM		 1737 /* check if device is on-going full reset(i.e. pcie as well) */
1738 if (hclgevf_dev_ongoing_full_reset(hdev)) {
1739 dev_warn(&pdev->dev, "device is going full reset\n");
1740 hclgevf_uninit_hdev(hdev);
1741 }
5bc3f5f3
SM		 1742
1743 ret = hclgevf_pci_init(hdev);
1744 if (ret) {
1745 dev_err(&pdev->dev, "PCI initialization failed\n");
1746 return ret;
1747 }
1748
1749 ret = hclgevf_init_msi(hdev);
1750 if (ret) {
1751 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
1752 goto err_irq_init;
1753 }
1754
1755 hclgevf_state_init(hdev);
1756
f4d51c27
YL		 1757 ret = hclgevf_cmd_init(hdev);
1758 if (ret)
1759 goto err_cmd_init;
1760
5bc3f5f3
SM		 1761 ret = hclgevf_misc_irq_init(hdev);
1762 if (ret) {
1763 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
1764 ret);
1765 goto err_misc_irq_init;
1766 }
1767
5bc3f5f3
SM		 1768 ret = hclgevf_configure(hdev);
1769 if (ret) {
1770 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
1771 goto err_config;
1772 }
1773
1774 ret = hclgevf_alloc_tqps(hdev);
1775 if (ret) {
1776 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
1777 goto err_config;
1778 }
1779
1780 ret = hclgevf_set_handle_info(hdev);
1781 if (ret) {
1782 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret);
1783 goto err_config;
1784 }
1785
038efa64
XW		 1786 /* Initialize mta type for this VF */
1787 ret = hclgevf_cfg_func_mta_type(hdev);
5bc3f5f3
SM		 1788 if (ret) {
1789 dev_err(&hdev->pdev->dev,
038efa64 1790 "failed(%d) to initialize MTA type\n", ret);
5bc3f5f3
SM		 1791 goto err_config;
1792 }
1793
1794 /* Initialize RSS for this VF */
1795 ret = hclgevf_rss_init_hw(hdev);
1796 if (ret) {
1797 dev_err(&hdev->pdev->dev,
1798 "failed(%d) to initialize RSS\n", ret);
1799 goto err_config;
1800 }
1801
1802 ret = hclgevf_init_vlan_config(hdev);
1803 if (ret) {
1804 dev_err(&hdev->pdev->dev,
1805 "failed(%d) to initialize VLAN config\n", ret);
1806 goto err_config;
1807 }
1808
1809 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME);
1810
1811 return 0;
1812
1813err_config:
5bc3f5f3
SM		 1814 hclgevf_misc_irq_uninit(hdev);
1815err_misc_irq_init:
f4d51c27
YL		 1816 hclgevf_cmd_uninit(hdev);
1817err_cmd_init:
5bc3f5f3
SM		 1818 hclgevf_state_uninit(hdev);
1819 hclgevf_uninit_msi(hdev);
1820err_irq_init:
1821 hclgevf_pci_uninit(hdev);
1822 return ret;
1823}
1824
1f05a70d 1825static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
5bc3f5f3 1826{
5bc3f5f3 1827 hclgevf_state_uninit(hdev);
f4d51c27
YL		 1828 hclgevf_misc_irq_uninit(hdev);
1829 hclgevf_cmd_uninit(hdev);
5bc3f5f3
SM		 1830 hclgevf_uninit_msi(hdev);
1831 hclgevf_pci_uninit(hdev);
1f05a70d
SM		 1832}
1833
1834static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
1835{
1836 struct pci_dev *pdev = ae_dev->pdev;
1837 int ret;
1838
1839 ret = hclgevf_alloc_hdev(ae_dev);
1840 if (ret) {
1841 dev_err(&pdev->dev, "hclge device allocation failed\n");
1842 return ret;
1843 }
1844
1845 ret = hclgevf_init_hdev(ae_dev->priv);
1846 if (ret)
1847 dev_err(&pdev->dev, "hclge device initialization failed\n");
1848
1849 return ret;
1850}
1851
1852static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
1853{
1854 struct hclgevf_dev *hdev = ae_dev->priv;
1855
1856 hclgevf_uninit_hdev(hdev);
5bc3f5f3
SM		 1857 ae_dev->priv = NULL;
1858}
1859
d65818a7
PL		 1860static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
1861{
1862 struct hnae3_handle *nic = &hdev->nic;
1863 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1864
1865 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
1866}
1867
1868/**
1869 * hclgevf_get_channels - Get the current channels enabled and max supported.
1870 * @handle: hardware information for network interface
1871 * @ch: ethtool channels structure
1872 *
1873 * We don't support separate tx and rx queues as channels. The other count
1874 * represents how many queues are being used for control. max_combined counts
1875 * how many queue pairs we can support. They may not be mapped 1 to 1 with
1876 * q_vectors since we support a lot more queue pairs than q_vectors.
1877 **/
1878static void hclgevf_get_channels(struct hnae3_handle *handle,
1879 struct ethtool_channels *ch)
1880{
1881 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1882
1883 ch->max_combined = hclgevf_get_max_channels(hdev);
1884 ch->other_count = 0;
1885 ch->max_other = 0;
1886 ch->combined_count = hdev->num_tqps;
1887}
1888
f72ed0d9
PL		 1889static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
1890 u16 *free_tqps, u16 *max_rss_size)
1891{
1892 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1893
1894 *free_tqps = 0;
1895 *max_rss_size = hdev->rss_size_max;
1896}
1897
16fc781e
FL		 1898static int hclgevf_get_status(struct hnae3_handle *handle)
1899{
1900 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1901
1902 return hdev->hw.mac.link;
1903}
1904
98ffd995
FL		 1905static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
1906 u8 *auto_neg, u32 *speed,
1907 u8 *duplex)
1908{
1909 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1910
1911 if (speed)
1912 *speed = hdev->hw.mac.speed;
1913 if (duplex)
1914 *duplex = hdev->hw.mac.duplex;
1915 if (auto_neg)
1916 *auto_neg = AUTONEG_DISABLE;
1917}
1918
1919void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
1920 u8 duplex)
1921{
1922 hdev->hw.mac.speed = speed;
1923 hdev->hw.mac.duplex = duplex;
1924}
1925
5bc3f5f3
SM		 1926static const struct hnae3_ae_ops hclgevf_ops = {
1927 .init_ae_dev = hclgevf_init_ae_dev,
1928 .uninit_ae_dev = hclgevf_uninit_ae_dev,
2e32e9a5
PL		 1929 .init_client_instance = hclgevf_init_client_instance,
1930 .uninit_client_instance = hclgevf_uninit_client_instance,
5bc3f5f3
SM		 1931 .start = hclgevf_ae_start,
1932 .stop = hclgevf_ae_stop,
1933 .map_ring_to_vector = hclgevf_map_ring_to_vector,
1934 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
1935 .get_vector = hclgevf_get_vector,
7412200c 1936 .put_vector = hclgevf_put_vector,
5bc3f5f3
SM		 1937 .reset_queue = hclgevf_reset_tqp,
1938 .set_promisc_mode = hclgevf_set_promisc_mode,
1939 .get_mac_addr = hclgevf_get_mac_addr,
1940 .set_mac_addr = hclgevf_set_mac_addr,
1941 .add_uc_addr = hclgevf_add_uc_addr,
1942 .rm_uc_addr = hclgevf_rm_uc_addr,
1943 .add_mc_addr = hclgevf_add_mc_addr,
1944 .rm_mc_addr = hclgevf_rm_mc_addr,
038efa64 1945 .update_mta_status = hclgevf_update_mta_status,
5bc3f5f3
SM		 1946 .get_stats = hclgevf_get_stats,
1947 .update_stats = hclgevf_update_stats,
1948 .get_strings = hclgevf_get_strings,
1949 .get_sset_count = hclgevf_get_sset_count,
1950 .get_rss_key_size = hclgevf_get_rss_key_size,
1951 .get_rss_indir_size = hclgevf_get_rss_indir_size,
1952 .get_rss = hclgevf_get_rss,
1953 .set_rss = hclgevf_set_rss,
1954 .get_tc_size = hclgevf_get_tc_size,
1955 .get_fw_version = hclgevf_get_fw_version,
1956 .set_vlan_filter = hclgevf_set_vlan_filter,
3849d494 1957 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
4aef908d 1958 .reset_event = hclgevf_reset_event,
d65818a7 1959 .get_channels = hclgevf_get_channels,
f72ed0d9 1960 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
16fc781e 1961 .get_status = hclgevf_get_status,
98ffd995 1962 .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
5bc3f5f3
SM		 1963};
1964
1965static struct hnae3_ae_algo ae_algovf = {
1966 .ops = &hclgevf_ops,
3519af01 1967 .name = HCLGEVF_NAME,
5bc3f5f3
SM		 1968 .pdev_id_table = ae_algovf_pci_tbl,
1969};
1970
1971static int hclgevf_init(void)
1972{
1973 pr_info("%s is initializing\n", HCLGEVF_NAME);
1974
a4d090cc
FL		 1975 hnae3_register_ae_algo(&ae_algovf);
1976
1977 return 0;
5bc3f5f3
SM		 1978}
1979
1980static void hclgevf_exit(void)
1981{
1982 hnae3_unregister_ae_algo(&ae_algovf);
1983}
1984module_init(hclgevf_init);
1985module_exit(hclgevf_exit);
1986
1987MODULE_LICENSE("GPL");
1988MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
1989MODULE_DESCRIPTION("HCLGEVF Driver");
1990MODULE_VERSION(HCLGEVF_MOD_VERSION);
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