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UBUNTU: SAUCE: {topost} net: hns3: Use roce handle when calling roce callback function
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3vf / hclgevf_main.c
CommitLineData
5bc3f5f3
SM		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
3
4#include <linux/etherdevice.h>
3a6b148b 5#include <net/rtnetlink.h>
5bc3f5f3
SM		 6#include "hclgevf_cmd.h"
7#include "hclgevf_main.h"
8#include "hclge_mbx.h"
9#include "hnae3.h"
10
11#define HCLGEVF_NAME "hclgevf"
12
1f05a70d
SM		 13static int hclgevf_init_hdev(struct hclgevf_dev *hdev);
14static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev);
5bc3f5f3
SM		 15static struct hnae3_ae_algo ae_algovf;
16
17static const struct pci_device_id ae_algovf_pci_tbl[] = {
18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
20 /* required last entry */
21 {0, }
22};
23
28d9cec8
YL		 24MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
25
5bc3f5f3
SM		 26static inline struct hclgevf_dev *hclgevf_ae_get_hdev(
27 struct hnae3_handle *handle)
28{
29 return container_of(handle, struct hclgevf_dev, nic);
30}
31
32static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
33{
34 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
35 struct hnae3_queue *queue;
36 struct hclgevf_desc desc;
37 struct hclgevf_tqp *tqp;
38 int status;
39 int i;
40
41 for (i = 0; i < hdev->num_tqps; i++) {
42 queue = handle->kinfo.tqp[i];
43 tqp = container_of(queue, struct hclgevf_tqp, q);
44 hclgevf_cmd_setup_basic_desc(&desc,
45 HCLGEVF_OPC_QUERY_RX_STATUS,
46 true);
47
48 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
49 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
50 if (status) {
51 dev_err(&hdev->pdev->dev,
52 "Query tqp stat fail, status = %d,queue = %d\n",
53 status, i);
54 return status;
55 }
56 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
93991b65 57 le32_to_cpu(desc.data[1]);
5bc3f5f3
SM		 58
59 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
60 true);
61
62 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
63 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
64 if (status) {
65 dev_err(&hdev->pdev->dev,
66 "Query tqp stat fail, status = %d,queue = %d\n",
67 status, i);
68 return status;
69 }
70 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
93991b65 71 le32_to_cpu(desc.data[1]);
5bc3f5f3
SM		 72 }
73
74 return 0;
75}
76
77static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
78{
79 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
80 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
81 struct hclgevf_tqp *tqp;
82 u64 *buff = data;
83 int i;
84
85 for (i = 0; i < hdev->num_tqps; i++) {
86 tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q);
87 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
88 }
89 for (i = 0; i < kinfo->num_tqps; i++) {
90 tqp = container_of(handle->kinfo.tqp[i], struct hclgevf_tqp, q);
91 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
92 }
93
94 return buff;
95}
96
97static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
98{
99 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
100
101 return hdev->num_tqps * 2;
102}
103
104static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
105{
106 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
107 u8 *buff = data;
108 int i = 0;
109
110 for (i = 0; i < hdev->num_tqps; i++) {
111 struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i],
112 struct hclgevf_tqp, q);
c36317be 113 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
5bc3f5f3
SM		 114 tqp->index);
115 buff += ETH_GSTRING_LEN;
116 }
117
118 for (i = 0; i < hdev->num_tqps; i++) {
119 struct hclgevf_tqp *tqp = container_of(handle->kinfo.tqp[i],
120 struct hclgevf_tqp, q);
c36317be 121 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
5bc3f5f3
SM		 122 tqp->index);
123 buff += ETH_GSTRING_LEN;
124 }
125
126 return buff;
127}
128
129static void hclgevf_update_stats(struct hnae3_handle *handle,
130 struct net_device_stats *net_stats)
131{
132 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
133 int status;
134
135 status = hclgevf_tqps_update_stats(handle);
136 if (status)
137 dev_err(&hdev->pdev->dev,
138 "VF update of TQPS stats fail, status = %d.\n",
139 status);
140}
141
142static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
143{
144 if (strset == ETH_SS_TEST)
145 return -EOPNOTSUPP;
146 else if (strset == ETH_SS_STATS)
147 return hclgevf_tqps_get_sset_count(handle, strset);
148
149 return 0;
150}
151
152static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
153 u8 *data)
154{
155 u8 *p = (char *)data;
156
157 if (strset == ETH_SS_STATS)
158 p = hclgevf_tqps_get_strings(handle, p);
159}
160
161static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
162{
163 hclgevf_tqps_get_stats(handle, data);
164}
165
166static int hclgevf_get_tc_info(struct hclgevf_dev *hdev)
167{
168 u8 resp_msg;
169 int status;
170
171 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0,
172 true, &resp_msg, sizeof(u8));
173 if (status) {
174 dev_err(&hdev->pdev->dev,
175 "VF request to get TC info from PF failed %d",
176 status);
177 return status;
178 }
179
180 hdev->hw_tc_map = resp_msg;
181
182 return 0;
183}
184
185static int hclge_get_queue_info(struct hclgevf_dev *hdev)
186{
187#define HCLGEVF_TQPS_RSS_INFO_LEN 8
188 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
189 int status;
190
191 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0,
192 true, resp_msg,
193 HCLGEVF_TQPS_RSS_INFO_LEN);
194 if (status) {
195 dev_err(&hdev->pdev->dev,
196 "VF request to get tqp info from PF failed %d",
197 status);
198 return status;
199 }
200
201 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16));
202 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16));
203 memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16));
204 memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16));
205
206 return 0;
207}
208
5bc3f5f3
SM		 209static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
210{
211 struct hclgevf_tqp *tqp;
212 int i;
213
1f05a70d
SM		 214 /* if this is on going reset then we need to re-allocate the TPQs
215 * since we cannot assume we would get same number of TPQs back from PF
216 */
217 if (hclgevf_dev_ongoing_reset(hdev))
218 devm_kfree(&hdev->pdev->dev, hdev->htqp);
219
5bc3f5f3
SM		 220 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
221 sizeof(struct hclgevf_tqp), GFP_KERNEL);
222 if (!hdev->htqp)
223 return -ENOMEM;
224
225 tqp = hdev->htqp;
226
227 for (i = 0; i < hdev->num_tqps; i++) {
228 tqp->dev = &hdev->pdev->dev;
229 tqp->index = i;
230
231 tqp->q.ae_algo = &ae_algovf;
232 tqp->q.buf_size = hdev->rx_buf_len;
233 tqp->q.desc_num = hdev->num_desc;
234 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
235 i * HCLGEVF_TQP_REG_SIZE;
236
237 tqp++;
238 }
239
240 return 0;
241}
242
243static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
244{
245 struct hnae3_handle *nic = &hdev->nic;
246 struct hnae3_knic_private_info *kinfo;
247 u16 new_tqps = hdev->num_tqps;
248 int i;
249
250 kinfo = &nic->kinfo;
251 kinfo->num_tc = 0;
252 kinfo->num_desc = hdev->num_desc;
253 kinfo->rx_buf_len = hdev->rx_buf_len;
254 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
255 if (hdev->hw_tc_map & BIT(i))
256 kinfo->num_tc++;
257
258 kinfo->rss_size
259 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc);
260 new_tqps = kinfo->rss_size * kinfo->num_tc;
261 kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
262
1f05a70d
SM		 263 /* if this is on going reset then we need to re-allocate the hnae queues
264 * as well since number of TPQs from PF might have changed.
265 */
266 if (hclgevf_dev_ongoing_reset(hdev))
267 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
268
5bc3f5f3
SM		 269 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
270 sizeof(struct hnae3_queue *), GFP_KERNEL);
271 if (!kinfo->tqp)
272 return -ENOMEM;
273
274 for (i = 0; i < kinfo->num_tqps; i++) {
275 hdev->htqp[i].q.handle = &hdev->nic;
276 hdev->htqp[i].q.tqp_index = i;
277 kinfo->tqp[i] = &hdev->htqp[i].q;
278 }
279
280 return 0;
281}
282
283static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
284{
285 int status;
286 u8 resp_msg;
287
288 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL,
289 0, false, &resp_msg, sizeof(u8));
290 if (status)
291 dev_err(&hdev->pdev->dev,
292 "VF failed to fetch link status(%d) from PF", status);
293}
294
295void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
296{
bc0b7416 297 struct hnae3_handle *rhandle = &hdev->roce;
5bc3f5f3 298 struct hnae3_handle *handle = &hdev->nic;
15a50665 299 struct hnae3_client *rclient;
5bc3f5f3
SM		 300 struct hnae3_client *client;
301
302 client = handle->client;
15a50665 303 rclient = hdev->roce_client;
5bc3f5f3
SM		 304
305 if (link_state != hdev->hw.mac.link) {
306 client->ops->link_status_change(handle, !!link_state);
15a50665 307 if (rclient && rclient->ops->link_status_change)
bc0b7416 308 rclient->ops->link_status_change(rhandle, !!link_state);
5bc3f5f3
SM		 309 hdev->hw.mac.link = link_state;
310 }
311}
312
313static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
314{
315 struct hnae3_handle *nic = &hdev->nic;
316 int ret;
317
318 nic->ae_algo = &ae_algovf;
319 nic->pdev = hdev->pdev;
320 nic->numa_node_mask = hdev->numa_node_mask;
a9c89a3f 321 nic->flags |= HNAE3_SUPPORT_VF;
5bc3f5f3
SM		 322
323 if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) {
324 dev_err(&hdev->pdev->dev, "unsupported device type %d\n",
325 hdev->ae_dev->dev_type);
326 return -EINVAL;
327 }
328
329 ret = hclgevf_knic_setup(hdev);
330 if (ret)
331 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
332 ret);
333 return ret;
334}
335
336static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
337{
617cb5a2
PL		 338 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
339 dev_warn(&hdev->pdev->dev,
340 "vector(vector_id %d) has been freed.\n", vector_id);
341 return;
342 }
343
5bc3f5f3
SM		 344 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
345 hdev->num_msi_left += 1;
346 hdev->num_msi_used -= 1;
347}
348
349static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
350 struct hnae3_vector_info *vector_info)
351{
352 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
353 struct hnae3_vector_info *vector = vector_info;
354 int alloc = 0;
355 int i, j;
356
357 vector_num = min(hdev->num_msi_left, vector_num);
358
359 for (j = 0; j < vector_num; j++) {
360 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
361 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
362 vector->vector = pci_irq_vector(hdev->pdev, i);
363 vector->io_addr = hdev->hw.io_base +
364 HCLGEVF_VECTOR_REG_BASE +
365 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
366 hdev->vector_status[i] = 0;
367 hdev->vector_irq[i] = vector->vector;
368
369 vector++;
370 alloc++;
371
372 break;
373 }
374 }
375 }
376 hdev->num_msi_left -= alloc;
377 hdev->num_msi_used += alloc;
378
379 return alloc;
380}
381
382static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
383{
384 int i;
385
386 for (i = 0; i < hdev->num_msi; i++)
387 if (vector == hdev->vector_irq[i])
388 return i;
389
390 return -EINVAL;
391}
392
393static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
394{
395 return HCLGEVF_RSS_KEY_SIZE;
396}
397
398static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle)
399{
400 return HCLGEVF_RSS_IND_TBL_SIZE;
401}
402
403static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
404{
405 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
406 struct hclgevf_rss_indirection_table_cmd *req;
407 struct hclgevf_desc desc;
408 int status;
409 int i, j;
410
411 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
412
413 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) {
414 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
415 false);
416 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE;
417 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK;
418 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
419 req->rss_result[j] =
420 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
421
422 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
423 if (status) {
424 dev_err(&hdev->pdev->dev,
425 "VF failed(=%d) to set RSS indirection table\n",
426 status);
427 return status;
428 }
429 }
430
431 return 0;
432}
433
434static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size)
435{
436 struct hclgevf_rss_tc_mode_cmd *req;
437 u16 tc_offset[HCLGEVF_MAX_TC_NUM];
438 u16 tc_valid[HCLGEVF_MAX_TC_NUM];
439 u16 tc_size[HCLGEVF_MAX_TC_NUM];
440 struct hclgevf_desc desc;
441 u16 roundup_size;
442 int status;
443 int i;
444
445 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
446
447 roundup_size = roundup_pow_of_two(rss_size);
448 roundup_size = ilog2(roundup_size);
449
450 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
451 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
452 tc_size[i] = roundup_size;
453 tc_offset[i] = rss_size * i;
454 }
455
456 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
457 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
e22b531b
HT		 458 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B,
459 (tc_valid[i] & 0x1));
460 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M,
461 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
462 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M,
463 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
5bc3f5f3
SM		 464 }
465 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
466 if (status)
467 dev_err(&hdev->pdev->dev,
468 "VF failed(=%d) to set rss tc mode\n", status);
469
470 return status;
471}
472
473static int hclgevf_get_rss_hw_cfg(struct hnae3_handle *handle, u8 *hash,
474 u8 *key)
475{
476 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
477 struct hclgevf_rss_config_cmd *req;
478 int lkup_times = key ? 3 : 1;
479 struct hclgevf_desc desc;
480 int key_offset;
481 int key_size;
482 int status;
483
484 req = (struct hclgevf_rss_config_cmd *)desc.data;
485 lkup_times = (lkup_times == 3) ? 3 : ((hash) ? 1 : 0);
486
487 for (key_offset = 0; key_offset < lkup_times; key_offset++) {
488 hclgevf_cmd_setup_basic_desc(&desc,
489 HCLGEVF_OPC_RSS_GENERIC_CONFIG,
490 true);
491 req->hash_config |= (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET);
492
493 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
494 if (status) {
495 dev_err(&hdev->pdev->dev,
496 "failed to get hardware RSS cfg, status = %d\n",
497 status);
498 return status;
499 }
500
501 if (key_offset == 2)
502 key_size =
503 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2;
504 else
505 key_size = HCLGEVF_RSS_HASH_KEY_NUM;
506
507 if (key)
508 memcpy(key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM,
509 req->hash_key,
510 key_size);
511 }
512
513 if (hash) {
514 if ((req->hash_config & 0xf) == HCLGEVF_RSS_HASH_ALGO_TOEPLITZ)
515 *hash = ETH_RSS_HASH_TOP;
516 else
517 *hash = ETH_RSS_HASH_UNKNOWN;
518 }
519
520 return 0;
521}
522
523static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
524 u8 *hfunc)
525{
526 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
527 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
528 int i;
529
530 if (indir)
531 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
532 indir[i] = rss_cfg->rss_indirection_tbl[i];
533
534 return hclgevf_get_rss_hw_cfg(handle, hfunc, key);
535}
536
537static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
538 const u8 *key, const u8 hfunc)
539{
540 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
541 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
542 int i;
543
544 /* update the shadow RSS table with user specified qids */
545 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
546 rss_cfg->rss_indirection_tbl[i] = indir[i];
547
548 /* update the hardware */
549 return hclgevf_set_rss_indir_table(hdev);
550}
551
552static int hclgevf_get_tc_size(struct hnae3_handle *handle)
553{
554 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
555 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
556
557 return rss_cfg->rss_size;
558}
559
560static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
4e223bdc 561 int vector_id,
5bc3f5f3
SM		 562 struct hnae3_ring_chain_node *ring_chain)
563{
5bc3f5f3
SM		 564 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
565 struct hnae3_ring_chain_node *node;
566 struct hclge_mbx_vf_to_pf_cmd *req;
567 struct hclgevf_desc desc;
4e223bdc 568 int i = 0;
5bc3f5f3
SM		 569 int status;
570 u8 type;
571
572 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
5bc3f5f3 573
5bc3f5f3 574 for (node = ring_chain; node; node = node->next) {
ce50439a
YL		 575 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM +
576 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i;
577
578 if (i == 0) {
579 hclgevf_cmd_setup_basic_desc(&desc,
580 HCLGEVF_OPC_MBX_VF_TO_PF,
581 false);
582 type = en ?
583 HCLGE_MBX_MAP_RING_TO_VECTOR :
584 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
585 req->msg[0] = type;
586 req->msg[1] = vector_id;
587 }
588
589 req->msg[idx_offset] =
e22b531b 590 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
ce50439a 591 req->msg[idx_offset + 1] = node->tqp_index;
e22b531b
HT		 592 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx,
593 HNAE3_RING_GL_IDX_M,
594 HNAE3_RING_GL_IDX_S);
ce50439a
YL		 595
596 i++;
597 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM -
598 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) /
599 HCLGE_MBX_RING_NODE_VARIABLE_NUM) ||
600 !node->next) {
5bc3f5f3
SM		 601 req->msg[2] = i;
602
603 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
604 if (status) {
605 dev_err(&hdev->pdev->dev,
606 "Map TQP fail, status is %d.\n",
607 status);
608 return status;
609 }
610 i = 0;
611 hclgevf_cmd_setup_basic_desc(&desc,
612 HCLGEVF_OPC_MBX_VF_TO_PF,
613 false);
614 req->msg[0] = type;
615 req->msg[1] = vector_id;
616 }
617 }
618
5bc3f5f3
SM		 619 return 0;
620}
621
622static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
623 struct hnae3_ring_chain_node *ring_chain)
624{
4e223bdc
PL		 625 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
626 int vector_id;
627
628 vector_id = hclgevf_get_vector_index(hdev, vector);
629 if (vector_id < 0) {
630 dev_err(&handle->pdev->dev,
631 "Get vector index fail. ret =%d\n", vector_id);
632 return vector_id;
633 }
634
635 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
5bc3f5f3
SM		 636}
637
638static int hclgevf_unmap_ring_from_vector(
639 struct hnae3_handle *handle,
640 int vector,
641 struct hnae3_ring_chain_node *ring_chain)
642{
643 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
644 int ret, vector_id;
645
646 vector_id = hclgevf_get_vector_index(hdev, vector);
647 if (vector_id < 0) {
648 dev_err(&handle->pdev->dev,
649 "Get vector index fail. ret =%d\n", vector_id);
650 return vector_id;
651 }
652
4e223bdc 653 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
7412200c 654 if (ret)
5bc3f5f3
SM		 655 dev_err(&handle->pdev->dev,
656 "Unmap ring from vector fail. vector=%d, ret =%d\n",
657 vector_id,
658 ret);
7412200c
YL		 659
660 return ret;
661}
662
663static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
664{
665 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
9c70f72a
YL		 666 int vector_id;
667
668 vector_id = hclgevf_get_vector_index(hdev, vector);
669 if (vector_id < 0) {
670 dev_err(&handle->pdev->dev,
671 "hclgevf_put_vector get vector index fail. ret =%d\n",
672 vector_id);
673 return vector_id;
674 }
5bc3f5f3 675
9c70f72a 676 hclgevf_free_vector(hdev, vector_id);
5bc3f5f3
SM		 677
678 return 0;
679}
680
e8600a3d
PL		 681static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
682 bool en_uc_pmc, bool en_mc_pmc)
5bc3f5f3
SM		 683{
684 struct hclge_mbx_vf_to_pf_cmd *req;
685 struct hclgevf_desc desc;
686 int status;
687
688 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
689
690 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false);
691 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE;
e8600a3d
PL		 692 req->msg[1] = en_uc_pmc ? 1 : 0;
693 req->msg[2] = en_mc_pmc ? 1 : 0;
5bc3f5f3
SM		 694
695 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
696 if (status)
697 dev_err(&hdev->pdev->dev,
698 "Set promisc mode fail, status is %d.\n", status);
699
700 return status;
701}
702
e8600a3d
PL		 703static void hclgevf_set_promisc_mode(struct hnae3_handle *handle,
704 bool en_uc_pmc, bool en_mc_pmc)
5bc3f5f3
SM		 705{
706 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
707
e8600a3d 708 hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc);
5bc3f5f3
SM		 709}
710
711static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id,
712 int stream_id, bool enable)
713{
714 struct hclgevf_cfg_com_tqp_queue_cmd *req;
715 struct hclgevf_desc desc;
716 int status;
717
718 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
719
720 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
721 false);
722 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
723 req->stream_id = cpu_to_le16(stream_id);
724 req->enable |= enable << HCLGEVF_TQP_ENABLE_B;
725
726 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
727 if (status)
728 dev_err(&hdev->pdev->dev,
729 "TQP enable fail, status =%d.\n", status);
730
731 return status;
732}
733
734static int hclgevf_get_queue_id(struct hnae3_queue *queue)
735{
736 struct hclgevf_tqp *tqp = container_of(queue, struct hclgevf_tqp, q);
737
738 return tqp->index;
739}
740
741static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
742{
743 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
744 struct hnae3_queue *queue;
745 struct hclgevf_tqp *tqp;
746 int i;
747
748 for (i = 0; i < hdev->num_tqps; i++) {
749 queue = handle->kinfo.tqp[i];
750 tqp = container_of(queue, struct hclgevf_tqp, q);
751 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
752 }
753}
754
038efa64
XW		 755static int hclgevf_cfg_func_mta_type(struct hclgevf_dev *hdev)
756{
757 u8 resp_msg = HCLGEVF_MTA_TYPE_SEL_MAX;
758 int ret;
759
760 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
761 HCLGE_MBX_MAC_VLAN_MTA_TYPE_READ,
762 NULL, 0, true, &resp_msg, sizeof(u8));
763
764 if (ret) {
765 dev_err(&hdev->pdev->dev,
766 "Read mta type fail, ret=%d.\n", ret);
767 return ret;
768 }
769
770 if (resp_msg > HCLGEVF_MTA_TYPE_SEL_MAX) {
771 dev_err(&hdev->pdev->dev,
772 "Read mta type invalid, resp=%d.\n", resp_msg);
773 return -EINVAL;
774 }
775
776 hdev->mta_mac_sel_type = resp_msg;
777
778 return 0;
779}
780
781static u16 hclgevf_get_mac_addr_to_mta_index(struct hclgevf_dev *hdev,
782 const u8 *addr)
783{
784 u32 rsh = HCLGEVF_MTA_TYPE_SEL_MAX - hdev->mta_mac_sel_type;
785 u16 high_val = addr[1] | (addr[0] << 8);
786
787 return (high_val >> rsh) & 0xfff;
788}
789
790static int hclgevf_do_update_mta_status(struct hclgevf_dev *hdev,
791 unsigned long *status)
792{
793#define HCLGEVF_MTA_STATUS_MSG_SIZE 13
794#define HCLGEVF_MTA_STATUS_MSG_BITS \
795 (HCLGEVF_MTA_STATUS_MSG_SIZE * BITS_PER_BYTE)
796#define HCLGEVF_MTA_STATUS_MSG_END_BITS \
797 (HCLGEVF_MTA_TBL_SIZE % HCLGEVF_MTA_STATUS_MSG_BITS)
798 u16 tbl_cnt;
799 u16 tbl_idx;
800 u8 msg_cnt;
801 u8 msg_idx;
802 int ret;
803
804 msg_cnt = DIV_ROUND_UP(HCLGEVF_MTA_TBL_SIZE,
805 HCLGEVF_MTA_STATUS_MSG_BITS);
806 tbl_idx = 0;
807 msg_idx = 0;
808 while (msg_cnt--) {
809 u8 msg[HCLGEVF_MTA_STATUS_MSG_SIZE + 1];
810 u8 *p = &msg[1];
811 u8 msg_ofs;
812 u8 msg_bit;
813
814 memset(msg, 0, sizeof(msg));
815
816 /* set index field */
817 msg[0] = 0x7F & msg_idx;
818
819 /* set end flag field */
820 if (msg_cnt == 0) {
821 msg[0] |= 0x80;
822 tbl_cnt = HCLGEVF_MTA_STATUS_MSG_END_BITS;
823 } else {
824 tbl_cnt = HCLGEVF_MTA_STATUS_MSG_BITS;
825 }
826
827 /* set status field */
828 msg_ofs = 0;
829 msg_bit = 0;
830 while (tbl_cnt--) {
831 if (test_bit(tbl_idx, status))
832 p[msg_ofs] |= BIT(msg_bit);
833
834 tbl_idx++;
835
836 msg_bit++;
837 if (msg_bit == BITS_PER_BYTE) {
838 msg_bit = 0;
839 msg_ofs++;
840 }
841 }
842
843 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
844 HCLGE_MBX_MAC_VLAN_MTA_STATUS_UPDATE,
845 msg, sizeof(msg), false, NULL, 0);
846 if (ret)
847 break;
848
849 msg_idx++;
850 }
851
852 return ret;
853}
854
855static int hclgevf_update_mta_status(struct hnae3_handle *handle)
856{
857 unsigned long mta_status[BITS_TO_LONGS(HCLGEVF_MTA_TBL_SIZE)];
858 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
859 struct net_device *netdev = hdev->nic.kinfo.netdev;
860 struct netdev_hw_addr *ha;
861 u16 tbl_idx;
862
863 /* clear status */
864 memset(mta_status, 0, sizeof(mta_status));
865
866 /* update status from mc addr list */
867 netdev_for_each_mc_addr(ha, netdev) {
868 tbl_idx = hclgevf_get_mac_addr_to_mta_index(hdev, ha->addr);
869 set_bit(tbl_idx, mta_status);
870 }
871
872 return hclgevf_do_update_mta_status(hdev, mta_status);
873}
874
5bc3f5f3
SM		 875static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
876{
877 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
878
879 ether_addr_copy(p, hdev->hw.mac.mac_addr);
880}
881
3cbf5e2d
FL		 882static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
883 bool is_first)
5bc3f5f3
SM		 884{
885 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
886 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
887 u8 *new_mac_addr = (u8 *)p;
888 u8 msg_data[ETH_ALEN * 2];
3cbf5e2d 889 u16 subcode;
5bc3f5f3
SM		 890 int status;
891
892 ether_addr_copy(msg_data, new_mac_addr);
893 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr);
894
3cbf5e2d
FL		 895 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD :
896 HCLGE_MBX_MAC_VLAN_UC_MODIFY;
897
5bc3f5f3 898 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
3cbf5e2d 899 subcode, msg_data, ETH_ALEN * 2,
5a955cd2 900 true, NULL, 0);
5bc3f5f3
SM		 901 if (!status)
902 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
903
904 return status;
905}
906
907static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
908 const unsigned char *addr)
909{
910 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
911
912 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
913 HCLGE_MBX_MAC_VLAN_UC_ADD,
914 addr, ETH_ALEN, false, NULL, 0);
915}
916
917static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
918 const unsigned char *addr)
919{
920 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
921
922 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
923 HCLGE_MBX_MAC_VLAN_UC_REMOVE,
924 addr, ETH_ALEN, false, NULL, 0);
925}
926
927static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
928 const unsigned char *addr)
929{
930 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
931
932 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
933 HCLGE_MBX_MAC_VLAN_MC_ADD,
934 addr, ETH_ALEN, false, NULL, 0);
935}
936
937static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
938 const unsigned char *addr)
939{
940 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
941
942 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
943 HCLGE_MBX_MAC_VLAN_MC_REMOVE,
944 addr, ETH_ALEN, false, NULL, 0);
945}
946
947static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
948 __be16 proto, u16 vlan_id,
949 bool is_kill)
950{
951#define HCLGEVF_VLAN_MBX_MSG_LEN 5
952 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
953 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN];
954
955 if (vlan_id > 4095)
956 return -EINVAL;
957
958 if (proto != htons(ETH_P_8021Q))
959 return -EPROTONOSUPPORT;
960
961 msg_data[0] = is_kill;
962 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
963 memcpy(&msg_data[3], &proto, sizeof(proto));
964 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
965 HCLGE_MBX_VLAN_FILTER, msg_data,
966 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0);
967}
968
3849d494
YL		 969static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
970{
971 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
972 u8 msg_data;
973
974 msg_data = enable ? 1 : 0;
975 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
976 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data,
977 1, false, NULL, 0);
978}
979
5bc3f5f3
SM		 980static void hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
981{
982 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
983 u8 msg_data[2];
d3ea7fc4 984 int ret;
5bc3f5f3
SM		 985
986 memcpy(&msg_data[0], &queue_id, sizeof(queue_id));
987
d3ea7fc4
PL		 988 /* disable vf queue before send queue reset msg to PF */
989 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false);
990 if (ret)
991 return;
992
993 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data,
994 2, true, NULL, 0);
5bc3f5f3
SM		 995}
996
3a6b148b
SM		 997static int hclgevf_notify_client(struct hclgevf_dev *hdev,
998 enum hnae3_reset_notify_type type)
999{
1000 struct hnae3_client *client = hdev->nic_client;
1001 struct hnae3_handle *handle = &hdev->nic;
1002
1003 if (!client->ops->reset_notify)
1004 return -EOPNOTSUPP;
1005
1006 return client->ops->reset_notify(handle, type);
1007}
1008
1009static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1010{
1011#define HCLGEVF_RESET_WAIT_MS 500
1012#define HCLGEVF_RESET_WAIT_CNT 20
1013 u32 val, cnt = 0;
1014
1015 /* wait to check the hardware reset completion status */
1016 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
e22b531b
HT		 1017 while (hnae3_get_bit(val, HCLGEVF_FUN_RST_ING_B) &&
1018 (cnt < HCLGEVF_RESET_WAIT_CNT)) {
3a6b148b
SM		 1019 msleep(HCLGEVF_RESET_WAIT_MS);
1020 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
1021 cnt++;
1022 }
1023
1024 /* hardware completion status should be available by this time */
1025 if (cnt >= HCLGEVF_RESET_WAIT_CNT) {
1026 dev_warn(&hdev->pdev->dev,
1027 "could'nt get reset done status from h/w, timeout!\n");
1028 return -EBUSY;
1029 }
1030
1031 /* we will wait a bit more to let reset of the stack to complete. This
1032 * might happen in case reset assertion was made by PF. Yes, this also
1033 * means we might end up waiting bit more even for VF reset.
1034 */
1035 msleep(5000);
1036
1037 return 0;
1038}
1039
1040static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1041{
1f05a70d
SM		 1042 int ret;
1043
3a6b148b
SM		 1044 /* uninitialize the nic client */
1045 hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1046
1f05a70d
SM		 1047 /* re-initialize the hclge device */
1048 ret = hclgevf_init_hdev(hdev);
1049 if (ret) {
1050 dev_err(&hdev->pdev->dev,
1051 "hclge device re-init failed, VF is disabled!\n");
1052 return ret;
1053 }
3a6b148b
SM		 1054
1055 /* bring up the nic client again */
1056 hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1057
1058 return 0;
1059}
1060
1061static int hclgevf_reset(struct hclgevf_dev *hdev)
1062{
1063 int ret;
1064
1065 rtnl_lock();
1066
1067 /* bring down the nic to stop any ongoing TX/RX */
1068 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1069
1070 /* check if VF could successfully fetch the hardware reset completion
1071 * status from the hardware
1072 */
1073 ret = hclgevf_reset_wait(hdev);
1074 if (ret) {
1075 /* can't do much in this situation, will disable VF */
1076 dev_err(&hdev->pdev->dev,
1077 "VF failed(=%d) to fetch H/W reset completion status\n",
1078 ret);
1079
1080 dev_warn(&hdev->pdev->dev, "VF reset failed, disabling VF!\n");
1081 hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1082
1083 rtnl_unlock();
1084 return ret;
1085 }
1086
1087 /* now, re-initialize the nic client and ae device*/
1088 ret = hclgevf_reset_stack(hdev);
1089 if (ret)
1090 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1091
1092 /* bring up the nic to enable TX/RX again */
1093 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1094
1095 rtnl_unlock();
1096
1097 return ret;
1098}
1099
d0e76212
SM		 1100static int hclgevf_do_reset(struct hclgevf_dev *hdev)
1101{
1102 int status;
1103 u8 respmsg;
1104
1105 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL,
1106 0, false, &respmsg, sizeof(u8));
1107 if (status)
1108 dev_err(&hdev->pdev->dev,
1109 "VF reset request to PF failed(=%d)\n", status);
1110
1111 return status;
1112}
1113
4aef908d
SM		 1114static void hclgevf_reset_event(struct hnae3_handle *handle)
1115{
1116 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1117
1118 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1119
1120 handle->reset_level = HNAE3_VF_RESET;
1121
bb2edc2e
SM		 1122 /* reset of this VF requested */
1123 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
1124 hclgevf_reset_task_schedule(hdev);
4aef908d
SM		 1125
1126 handle->last_reset_time = jiffies;
1127}
1128
5bc3f5f3
SM		 1129static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
1130{
1131 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1132
1133 return hdev->fw_version;
1134}
1135
1136static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
1137{
1138 struct hclgevf_misc_vector *vector = &hdev->misc_vector;
1139
1140 vector->vector_irq = pci_irq_vector(hdev->pdev,
1141 HCLGEVF_MISC_VECTOR_NUM);
1142 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
1143 /* vector status always valid for Vector 0 */
1144 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
1145 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
1146
1147 hdev->num_msi_left -= 1;
1148 hdev->num_msi_used += 1;
1149}
1150
f0412650
SM		 1151void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
1152{
1153 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) &&
1154 !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) {
1155 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1156 schedule_work(&hdev->rst_service_task);
1157 }
1158}
1159
85a86c48 1160void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
5bc3f5f3 1161{
85a86c48
SM		 1162 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) &&
1163 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) {
1164 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
5bc3f5f3 1165 schedule_work(&hdev->mbx_service_task);
85a86c48 1166 }
5bc3f5f3
SM		 1167}
1168
1169static void hclgevf_task_schedule(struct hclgevf_dev *hdev)
1170{
1171 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) &&
1172 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state))
1173 schedule_work(&hdev->service_task);
1174}
1175
bb2edc2e
SM		 1176static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev)
1177{
85a86c48
SM		 1178 /* if we have any pending mailbox event then schedule the mbx task */
1179 if (hdev->mbx_event_pending)
1180 hclgevf_mbx_task_schedule(hdev);
1181
bb2edc2e
SM		 1182 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state))
1183 hclgevf_reset_task_schedule(hdev);
1184}
1185
5bc3f5f3
SM		 1186static void hclgevf_service_timer(struct timer_list *t)
1187{
1188 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer);
1189
1190 mod_timer(&hdev->service_timer, jiffies + 5 * HZ);
1191
1192 hclgevf_task_schedule(hdev);
1193}
1194
f0412650
SM		 1195static void hclgevf_reset_service_task(struct work_struct *work)
1196{
1197 struct hclgevf_dev *hdev =
1198 container_of(work, struct hclgevf_dev, rst_service_task);
d0e76212 1199 int ret;
f0412650
SM		 1200
1201 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1202 return;
1203
1204 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1205
bb2edc2e
SM		 1206 if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
1207 &hdev->reset_state)) {
1208 /* PF has initmated that it is about to reset the hardware.
1209 * We now have to poll & check if harware has actually completed
1210 * the reset sequence. On hardware reset completion, VF needs to
1211 * reset the client and ae device.
1212 */
1213 hdev->reset_attempts = 0;
1214
3a6b148b
SM		 1215 ret = hclgevf_reset(hdev);
1216 if (ret)
1217 dev_err(&hdev->pdev->dev, "VF stack reset failed.\n");
bb2edc2e
SM		 1218 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
1219 &hdev->reset_state)) {
1220 /* we could be here when either of below happens:
1221 * 1. reset was initiated due to watchdog timeout due to
1222 * a. IMP was earlier reset and our TX got choked down and
1223 * which resulted in watchdog reacting and inducing VF
1224 * reset. This also means our cmdq would be unreliable.
1225 * b. problem in TX due to other lower layer(example link
1226 * layer not functioning properly etc.)
1227 * 2. VF reset might have been initiated due to some config
1228 * change.
1229 *
1230 * NOTE: Theres no clear way to detect above cases than to react
1231 * to the response of PF for this reset request. PF will ack the
1232 * 1b and 2. cases but we will not get any intimation about 1a
1233 * from PF as cmdq would be in unreliable state i.e. mailbox
1234 * communication between PF and VF would be broken.
1235 */
1236
1237 /* if we are never geting into pending state it means either:
1238 * 1. PF is not receiving our request which could be due to IMP
1239 * reset
1240 * 2. PF is screwed
1241 * We cannot do much for 2. but to check first we can try reset
1242 * our PCIe + stack and see if it alleviates the problem.
1243 */
1244 if (hdev->reset_attempts > 3) {
1245 /* prepare for full reset of stack + pcie interface */
1246 hdev->nic.reset_level = HNAE3_VF_FULL_RESET;
1247
1248 /* "defer" schedule the reset task again */
1249 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1250 } else {
1251 hdev->reset_attempts++;
1252
1253 /* request PF for resetting this VF via mailbox */
d0e76212
SM		 1254 ret = hclgevf_do_reset(hdev);
1255 if (ret)
1256 dev_warn(&hdev->pdev->dev,
1257 "VF rst fail, stack will call\n");
bb2edc2e
SM		 1258 }
1259 }
f0412650
SM		 1260
1261 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1262}
1263
5bc3f5f3
SM		 1264static void hclgevf_mailbox_service_task(struct work_struct *work)
1265{
1266 struct hclgevf_dev *hdev;
1267
1268 hdev = container_of(work, struct hclgevf_dev, mbx_service_task);
1269
1270 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
1271 return;
1272
1273 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1274
85a86c48 1275 hclgevf_mbx_async_handler(hdev);
5bc3f5f3
SM		 1276
1277 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1278}
1279
1280static void hclgevf_service_task(struct work_struct *work)
1281{
1282 struct hclgevf_dev *hdev;
1283
1284 hdev = container_of(work, struct hclgevf_dev, service_task);
1285
1286 /* request the link status from the PF. PF would be able to tell VF
1287 * about such updates in future so we might remove this later
1288 */
1289 hclgevf_request_link_info(hdev);
1290
bb2edc2e
SM		 1291 hclgevf_deferred_task_schedule(hdev);
1292
5bc3f5f3
SM		 1293 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1294}
1295
1296static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
1297{
1298 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
1299}
1300
1301static bool hclgevf_check_event_cause(struct hclgevf_dev *hdev, u32 *clearval)
1302{
1303 u32 cmdq_src_reg;
1304
1305 /* fetch the events from their corresponding regs */
1306 cmdq_src_reg = hclgevf_read_dev(&hdev->hw,
1307 HCLGEVF_VECTOR0_CMDQ_SRC_REG);
1308
1309 /* check for vector0 mailbox(=CMDQ RX) event source */
1310 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
1311 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1312 *clearval = cmdq_src_reg;
1313 return true;
1314 }
1315
1316 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n");
1317
1318 return false;
1319}
1320
1321static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
1322{
1323 writel(en ? 1 : 0, vector->addr);
1324}
1325
1326static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
1327{
1328 struct hclgevf_dev *hdev = data;
1329 u32 clearval;
1330
1331 hclgevf_enable_vector(&hdev->misc_vector, false);
1332 if (!hclgevf_check_event_cause(hdev, &clearval))
1333 goto skip_sched;
1334
85a86c48 1335 hclgevf_mbx_handler(hdev);
5bc3f5f3
SM		 1336
1337 hclgevf_clear_event_cause(hdev, clearval);
1338
1339skip_sched:
1340 hclgevf_enable_vector(&hdev->misc_vector, true);
1341
1342 return IRQ_HANDLED;
1343}
1344
1345static int hclgevf_configure(struct hclgevf_dev *hdev)
1346{
1347 int ret;
1348
1349 /* get queue configuration from PF */
1350 ret = hclge_get_queue_info(hdev);
1351 if (ret)
1352 return ret;
1353 /* get tc configuration from PF */
1354 return hclgevf_get_tc_info(hdev);
1355}
1356
1f05a70d
SM		 1357static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
1358{
1359 struct pci_dev *pdev = ae_dev->pdev;
1360 struct hclgevf_dev *hdev = ae_dev->priv;
1361
1362 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
1363 if (!hdev)
1364 return -ENOMEM;
1365
1366 hdev->pdev = pdev;
1367 hdev->ae_dev = ae_dev;
1368 ae_dev->priv = hdev;
1369
1370 return 0;
1371}
1372
5bc3f5f3
SM		 1373static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
1374{
1375 struct hnae3_handle *roce = &hdev->roce;
1376 struct hnae3_handle *nic = &hdev->nic;
1377
1378 roce->rinfo.num_vectors = HCLGEVF_ROCEE_VECTOR_NUM;
1379
1380 if (hdev->num_msi_left < roce->rinfo.num_vectors ||
1381 hdev->num_msi_left == 0)
1382 return -EINVAL;
1383
1384 roce->rinfo.base_vector =
1385 hdev->vector_status[hdev->num_msi_used];
1386
1387 roce->rinfo.netdev = nic->kinfo.netdev;
1388 roce->rinfo.roce_io_base = hdev->hw.io_base;
1389
1390 roce->pdev = nic->pdev;
1391 roce->ae_algo = nic->ae_algo;
1392 roce->numa_node_mask = nic->numa_node_mask;
1393
1394 return 0;
1395}
1396
1397static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
1398{
1399 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1400 int i, ret;
1401
1402 rss_cfg->rss_size = hdev->rss_size_max;
1403
1404 /* Initialize RSS indirect table for each vport */
1405 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
1406 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max;
1407
1408 ret = hclgevf_set_rss_indir_table(hdev);
1409 if (ret)
1410 return ret;
1411
1412 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max);
1413}
1414
1415static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
1416{
1417 /* other vlan config(like, VLAN TX/RX offload) would also be added
1418 * here later
1419 */
1420 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
1421 false);
1422}
1423
1424static int hclgevf_ae_start(struct hnae3_handle *handle)
1425{
1426 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1427 int i, queue_id;
1428
1429 for (i = 0; i < handle->kinfo.num_tqps; i++) {
1430 /* ring enable */
1431 queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]);
1432 if (queue_id < 0) {
1433 dev_warn(&hdev->pdev->dev,
1434 "Get invalid queue id, ignore it\n");
1435 continue;
1436 }
1437
1438 hclgevf_tqp_enable(hdev, queue_id, 0, true);
1439 }
1440
1441 /* reset tqp stats */
1442 hclgevf_reset_tqp_stats(handle);
1443
1444 hclgevf_request_link_info(hdev);
1445
1446 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1447 mod_timer(&hdev->service_timer, jiffies + HZ);
1448
1449 return 0;
1450}
1451
1452static void hclgevf_ae_stop(struct hnae3_handle *handle)
1453{
1454 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1455 int i, queue_id;
1456
1457 for (i = 0; i < hdev->num_tqps; i++) {
1458 /* Ring disable */
1459 queue_id = hclgevf_get_queue_id(handle->kinfo.tqp[i]);
1460 if (queue_id < 0) {
1461 dev_warn(&hdev->pdev->dev,
1462 "Get invalid queue id, ignore it\n");
1463 continue;
1464 }
1465
1466 hclgevf_tqp_enable(hdev, queue_id, 0, false);
1467 }
1468
1469 /* reset tqp stats */
1470 hclgevf_reset_tqp_stats(handle);
d14992df
FL		 1471 del_timer_sync(&hdev->service_timer);
1472 cancel_work_sync(&hdev->service_task);
42b11ab7 1473 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
d14992df 1474 hclgevf_update_link_status(hdev, 0);
5bc3f5f3
SM		 1475}
1476
1477static void hclgevf_state_init(struct hclgevf_dev *hdev)
1478{
1f05a70d
SM		 1479 /* if this is on going reset then skip this initialization */
1480 if (hclgevf_dev_ongoing_reset(hdev))
1481 return;
1482
5bc3f5f3
SM		 1483 /* setup tasks for the MBX */
1484 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task);
1485 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1486 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1487
1488 /* setup tasks for service timer */
1489 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0);
1490
1491 INIT_WORK(&hdev->service_task, hclgevf_service_task);
1492 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1493
f0412650
SM		 1494 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task);
1495
5bc3f5f3
SM		 1496 mutex_init(&hdev->mbx_resp.mbx_mutex);
1497
1498 /* bring the device down */
1499 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1500}
1501
1502static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
1503{
1504 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1505
1506 if (hdev->service_timer.function)
1507 del_timer_sync(&hdev->service_timer);
1508 if (hdev->service_task.func)
1509 cancel_work_sync(&hdev->service_task);
1510 if (hdev->mbx_service_task.func)
1511 cancel_work_sync(&hdev->mbx_service_task);
f0412650
SM		 1512 if (hdev->rst_service_task.func)
1513 cancel_work_sync(&hdev->rst_service_task);
5bc3f5f3
SM		 1514
1515 mutex_destroy(&hdev->mbx_resp.mbx_mutex);
1516}
1517
1518static int hclgevf_init_msi(struct hclgevf_dev *hdev)
1519{
1520 struct pci_dev *pdev = hdev->pdev;
1521 int vectors;
1522 int i;
1523
1f05a70d
SM		 1524 /* if this is on going reset then skip this initialization */
1525 if (hclgevf_dev_ongoing_reset(hdev))
1526 return 0;
1527
5bc3f5f3
SM		 1528 hdev->num_msi = HCLGEVF_MAX_VF_VECTOR_NUM;
1529
1530 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1531 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1532 if (vectors < 0) {
1533 dev_err(&pdev->dev,
1534 "failed(%d) to allocate MSI/MSI-X vectors\n",
1535 vectors);
1536 return vectors;
1537 }
1538 if (vectors < hdev->num_msi)
1539 dev_warn(&hdev->pdev->dev,
1540 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1541 hdev->num_msi, vectors);
1542
1543 hdev->num_msi = vectors;
1544 hdev->num_msi_left = vectors;
1545 hdev->base_msi_vector = pdev->irq;
1546
1547 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1548 sizeof(u16), GFP_KERNEL);
1549 if (!hdev->vector_status) {
1550 pci_free_irq_vectors(pdev);
1551 return -ENOMEM;
1552 }
1553
1554 for (i = 0; i < hdev->num_msi; i++)
1555 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
1556
1557 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1558 sizeof(int), GFP_KERNEL);
1559 if (!hdev->vector_irq) {
1560 pci_free_irq_vectors(pdev);
1561 return -ENOMEM;
1562 }
1563
1564 return 0;
1565}
1566
1567static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
1568{
1569 struct pci_dev *pdev = hdev->pdev;
1570
1571 pci_free_irq_vectors(pdev);
1572}
1573
1574static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
1575{
1576 int ret = 0;
1577
1f05a70d
SM		 1578 /* if this is on going reset then skip this initialization */
1579 if (hclgevf_dev_ongoing_reset(hdev))
1580 return 0;
1581
5bc3f5f3
SM		 1582 hclgevf_get_misc_vector(hdev);
1583
1584 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
1585 0, "hclgevf_cmd", hdev);
1586 if (ret) {
1587 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
1588 hdev->misc_vector.vector_irq);
1589 return ret;
1590 }
1591
1592 /* enable misc. vector(vector 0) */
1593 hclgevf_enable_vector(&hdev->misc_vector, true);
1594
1595 return ret;
1596}
1597
1598static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
1599{
1600 /* disable misc vector(vector 0) */
1601 hclgevf_enable_vector(&hdev->misc_vector, false);
1602 free_irq(hdev->misc_vector.vector_irq, hdev);
1603 hclgevf_free_vector(hdev, 0);
1604}
1605
e7e09222
PL		 1606static int hclgevf_init_client_instance(struct hnae3_client *client,
1607 struct hnae3_ae_dev *ae_dev)
5bc3f5f3 1608{
e7e09222 1609 struct hclgevf_dev *hdev = ae_dev->priv;
5bc3f5f3
SM		 1610 int ret;
1611
1612 switch (client->type) {
1613 case HNAE3_CLIENT_KNIC:
1614 hdev->nic_client = client;
1615 hdev->nic.client = client;
1616
1617 ret = client->ops->init_instance(&hdev->nic);
1618 if (ret)
1619 return ret;
1620
1621 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) {
1622 struct hnae3_client *rc = hdev->roce_client;
1623
1624 ret = hclgevf_init_roce_base_info(hdev);
1625 if (ret)
1626 return ret;
1627 ret = rc->ops->init_instance(&hdev->roce);
1628 if (ret)
1629 return ret;
1630 }
1631 break;
1632 case HNAE3_CLIENT_UNIC:
1633 hdev->nic_client = client;
1634 hdev->nic.client = client;
1635
1636 ret = client->ops->init_instance(&hdev->nic);
1637 if (ret)
1638 return ret;
1639 break;
1640 case HNAE3_CLIENT_ROCE:
4cc40db1
LO		 1641 if (hnae3_dev_roce_supported(hdev)) {
1642 hdev->roce_client = client;
1643 hdev->roce.client = client;
1644 }
5bc3f5f3 1645
4cc40db1 1646 if (hdev->roce_client && hdev->nic_client) {
5bc3f5f3
SM		 1647 ret = hclgevf_init_roce_base_info(hdev);
1648 if (ret)
1649 return ret;
1650
1651 ret = client->ops->init_instance(&hdev->roce);
1652 if (ret)
1653 return ret;
1654 }
1655 }
1656
1657 return 0;
1658}
1659
e7e09222
PL		 1660static void hclgevf_uninit_client_instance(struct hnae3_client *client,
1661 struct hnae3_ae_dev *ae_dev)
5bc3f5f3 1662{
e7e09222
PL		 1663 struct hclgevf_dev *hdev = ae_dev->priv;
1664
5bc3f5f3
SM		 1665 /* un-init roce, if it exists */
1666 if (hdev->roce_client)
1667 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
1668
1669 /* un-init nic/unic, if this was not called by roce client */
1670 if ((client->ops->uninit_instance) &&
1671 (client->type != HNAE3_CLIENT_ROCE))
1672 client->ops->uninit_instance(&hdev->nic, 0);
1673}
1674
5bc3f5f3
SM		 1675static int hclgevf_pci_init(struct hclgevf_dev *hdev)
1676{
1677 struct pci_dev *pdev = hdev->pdev;
1678 struct hclgevf_hw *hw;
1679 int ret;
1680
1f05a70d
SM		 1681 /* check if we need to skip initialization of pci. This will happen if
1682 * device is undergoing VF reset. Otherwise, we would need to
1683 * re-initialize pci interface again i.e. when device is not going
1684 * through *any* reset or actually undergoing full reset.
1685 */
1686 if (hclgevf_dev_ongoing_reset(hdev))
1687 return 0;
1688
5bc3f5f3
SM		 1689 ret = pci_enable_device(pdev);
1690 if (ret) {
1691 dev_err(&pdev->dev, "failed to enable PCI device\n");
6c46284e 1692 return ret;
5bc3f5f3
SM		 1693 }
1694
1695 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1696 if (ret) {
1697 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
1698 goto err_disable_device;
1699 }
1700
1701 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
1702 if (ret) {
1703 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
1704 goto err_disable_device;
1705 }
1706
1707 pci_set_master(pdev);
1708 hw = &hdev->hw;
1709 hw->hdev = hdev;
d2f70b04 1710 hw->io_base = pci_iomap(pdev, 2, 0);
5bc3f5f3
SM		 1711 if (!hw->io_base) {
1712 dev_err(&pdev->dev, "can't map configuration register space\n");
1713 ret = -ENOMEM;
1714 goto err_clr_master;
1715 }
1716
1717 return 0;
1718
1719err_clr_master:
1720 pci_clear_master(pdev);
1721 pci_release_regions(pdev);
1722err_disable_device:
1723 pci_disable_device(pdev);
6c46284e 1724
5bc3f5f3
SM		 1725 return ret;
1726}
1727
1728static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
1729{
1730 struct pci_dev *pdev = hdev->pdev;
1731
1732 pci_iounmap(pdev, hdev->hw.io_base);
1733 pci_clear_master(pdev);
1734 pci_release_regions(pdev);
1735 pci_disable_device(pdev);
5bc3f5f3
SM		 1736}
1737
1f05a70d 1738static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
5bc3f5f3 1739{
1f05a70d 1740 struct pci_dev *pdev = hdev->pdev;
5bc3f5f3
SM		 1741 int ret;
1742
1f05a70d
SM		 1743 /* check if device is on-going full reset(i.e. pcie as well) */
1744 if (hclgevf_dev_ongoing_full_reset(hdev)) {
1745 dev_warn(&pdev->dev, "device is going full reset\n");
1746 hclgevf_uninit_hdev(hdev);
1747 }
5bc3f5f3
SM		 1748
1749 ret = hclgevf_pci_init(hdev);
1750 if (ret) {
1751 dev_err(&pdev->dev, "PCI initialization failed\n");
1752 return ret;
1753 }
1754
1755 ret = hclgevf_init_msi(hdev);
1756 if (ret) {
1757 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
1758 goto err_irq_init;
1759 }
1760
1761 hclgevf_state_init(hdev);
1762
f4d51c27
YL		 1763 ret = hclgevf_cmd_init(hdev);
1764 if (ret)
1765 goto err_cmd_init;
1766
5bc3f5f3
SM		 1767 ret = hclgevf_misc_irq_init(hdev);
1768 if (ret) {
1769 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
1770 ret);
1771 goto err_misc_irq_init;
1772 }
1773
5bc3f5f3
SM		 1774 ret = hclgevf_configure(hdev);
1775 if (ret) {
1776 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
1777 goto err_config;
1778 }
1779
1780 ret = hclgevf_alloc_tqps(hdev);
1781 if (ret) {
1782 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
1783 goto err_config;
1784 }
1785
1786 ret = hclgevf_set_handle_info(hdev);
1787 if (ret) {
1788 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret);
1789 goto err_config;
1790 }
1791
038efa64
XW		 1792 /* Initialize mta type for this VF */
1793 ret = hclgevf_cfg_func_mta_type(hdev);
5bc3f5f3
SM		 1794 if (ret) {
1795 dev_err(&hdev->pdev->dev,
038efa64 1796 "failed(%d) to initialize MTA type\n", ret);
5bc3f5f3
SM		 1797 goto err_config;
1798 }
1799
1800 /* Initialize RSS for this VF */
1801 ret = hclgevf_rss_init_hw(hdev);
1802 if (ret) {
1803 dev_err(&hdev->pdev->dev,
1804 "failed(%d) to initialize RSS\n", ret);
1805 goto err_config;
1806 }
1807
1808 ret = hclgevf_init_vlan_config(hdev);
1809 if (ret) {
1810 dev_err(&hdev->pdev->dev,
1811 "failed(%d) to initialize VLAN config\n", ret);
1812 goto err_config;
1813 }
1814
1815 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME);
1816
1817 return 0;
1818
1819err_config:
5bc3f5f3
SM		 1820 hclgevf_misc_irq_uninit(hdev);
1821err_misc_irq_init:
f4d51c27
YL		 1822 hclgevf_cmd_uninit(hdev);
1823err_cmd_init:
5bc3f5f3
SM		 1824 hclgevf_state_uninit(hdev);
1825 hclgevf_uninit_msi(hdev);
1826err_irq_init:
1827 hclgevf_pci_uninit(hdev);
1828 return ret;
1829}
1830
1f05a70d 1831static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
5bc3f5f3 1832{
5bc3f5f3 1833 hclgevf_state_uninit(hdev);
f4d51c27
YL		 1834 hclgevf_misc_irq_uninit(hdev);
1835 hclgevf_cmd_uninit(hdev);
5bc3f5f3
SM		 1836 hclgevf_uninit_msi(hdev);
1837 hclgevf_pci_uninit(hdev);
1f05a70d
SM		 1838}
1839
1840static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
1841{
1842 struct pci_dev *pdev = ae_dev->pdev;
1843 int ret;
1844
1845 ret = hclgevf_alloc_hdev(ae_dev);
1846 if (ret) {
1847 dev_err(&pdev->dev, "hclge device allocation failed\n");
1848 return ret;
1849 }
1850
1851 ret = hclgevf_init_hdev(ae_dev->priv);
1852 if (ret)
1853 dev_err(&pdev->dev, "hclge device initialization failed\n");
1854
1855 return ret;
1856}
1857
1858static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
1859{
1860 struct hclgevf_dev *hdev = ae_dev->priv;
1861
1862 hclgevf_uninit_hdev(hdev);
5bc3f5f3
SM		 1863 ae_dev->priv = NULL;
1864}
1865
d65818a7
PL		 1866static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
1867{
1868 struct hnae3_handle *nic = &hdev->nic;
1869 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1870
1871 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
1872}
1873
1874/**
1875 * hclgevf_get_channels - Get the current channels enabled and max supported.
1876 * @handle: hardware information for network interface
1877 * @ch: ethtool channels structure
1878 *
1879 * We don't support separate tx and rx queues as channels. The other count
1880 * represents how many queues are being used for control. max_combined counts
1881 * how many queue pairs we can support. They may not be mapped 1 to 1 with
1882 * q_vectors since we support a lot more queue pairs than q_vectors.
1883 **/
1884static void hclgevf_get_channels(struct hnae3_handle *handle,
1885 struct ethtool_channels *ch)
1886{
1887 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1888
1889 ch->max_combined = hclgevf_get_max_channels(hdev);
1890 ch->other_count = 0;
1891 ch->max_other = 0;
1892 ch->combined_count = hdev->num_tqps;
1893}
1894
f72ed0d9
PL		 1895static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
1896 u16 *free_tqps, u16 *max_rss_size)
1897{
1898 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1899
1900 *free_tqps = 0;
1901 *max_rss_size = hdev->rss_size_max;
1902}
1903
16fc781e
FL		 1904static int hclgevf_get_status(struct hnae3_handle *handle)
1905{
1906 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1907
1908 return hdev->hw.mac.link;
1909}
1910
98ffd995
FL		 1911static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
1912 u8 *auto_neg, u32 *speed,
1913 u8 *duplex)
1914{
1915 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1916
1917 if (speed)
1918 *speed = hdev->hw.mac.speed;
1919 if (duplex)
1920 *duplex = hdev->hw.mac.duplex;
1921 if (auto_neg)
1922 *auto_neg = AUTONEG_DISABLE;
1923}
1924
1925void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
1926 u8 duplex)
1927{
1928 hdev->hw.mac.speed = speed;
1929 hdev->hw.mac.duplex = duplex;
1930}
1931
5bc3f5f3
SM		 1932static const struct hnae3_ae_ops hclgevf_ops = {
1933 .init_ae_dev = hclgevf_init_ae_dev,
1934 .uninit_ae_dev = hclgevf_uninit_ae_dev,
e7e09222
PL		 1935 .init_client_instance = hclgevf_init_client_instance,
1936 .uninit_client_instance = hclgevf_uninit_client_instance,
5bc3f5f3
SM		 1937 .start = hclgevf_ae_start,
1938 .stop = hclgevf_ae_stop,
1939 .map_ring_to_vector = hclgevf_map_ring_to_vector,
1940 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
1941 .get_vector = hclgevf_get_vector,
7412200c 1942 .put_vector = hclgevf_put_vector,
5bc3f5f3
SM		 1943 .reset_queue = hclgevf_reset_tqp,
1944 .set_promisc_mode = hclgevf_set_promisc_mode,
1945 .get_mac_addr = hclgevf_get_mac_addr,
1946 .set_mac_addr = hclgevf_set_mac_addr,
1947 .add_uc_addr = hclgevf_add_uc_addr,
1948 .rm_uc_addr = hclgevf_rm_uc_addr,
1949 .add_mc_addr = hclgevf_add_mc_addr,
1950 .rm_mc_addr = hclgevf_rm_mc_addr,
038efa64 1951 .update_mta_status = hclgevf_update_mta_status,
5bc3f5f3
SM		 1952 .get_stats = hclgevf_get_stats,
1953 .update_stats = hclgevf_update_stats,
1954 .get_strings = hclgevf_get_strings,
1955 .get_sset_count = hclgevf_get_sset_count,
1956 .get_rss_key_size = hclgevf_get_rss_key_size,
1957 .get_rss_indir_size = hclgevf_get_rss_indir_size,
1958 .get_rss = hclgevf_get_rss,
1959 .set_rss = hclgevf_set_rss,
1960 .get_tc_size = hclgevf_get_tc_size,
1961 .get_fw_version = hclgevf_get_fw_version,
1962 .set_vlan_filter = hclgevf_set_vlan_filter,
3849d494 1963 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
4aef908d 1964 .reset_event = hclgevf_reset_event,
d65818a7 1965 .get_channels = hclgevf_get_channels,
f72ed0d9 1966 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
16fc781e 1967 .get_status = hclgevf_get_status,
98ffd995 1968 .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
5bc3f5f3
SM		 1969};
1970
1971static struct hnae3_ae_algo ae_algovf = {
1972 .ops = &hclgevf_ops,
5bc3f5f3
SM		 1973 .pdev_id_table = ae_algovf_pci_tbl,
1974};
1975
1976static int hclgevf_init(void)
1977{
1978 pr_info("%s is initializing\n", HCLGEVF_NAME);
1979
a4d090cc
FL		 1980 hnae3_register_ae_algo(&ae_algovf);
1981
1982 return 0;
5bc3f5f3
SM		 1983}
1984
1985static void hclgevf_exit(void)
1986{
1987 hnae3_unregister_ae_algo(&ae_algovf);
1988}
1989module_init(hclgevf_init);
1990module_exit(hclgevf_exit);
1991
1992MODULE_LICENSE("GPL");
1993MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
1994MODULE_DESCRIPTION("HCLGEVF Driver");
1995MODULE_VERSION(HCLGEVF_MOD_VERSION);
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